Compal LA-2541, Compaq nx6125 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

EPW00 Schematics Document

Mobile AMD Athlon 64 with

3 3

4 4

A

ATI RS480M+ATI SB400

2005-04-15

REV:0.5

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/11 2006/03/11

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Cover Sheet
LA-2541

E

of

158Friday, April 15, 2005

0.4

A

Compal confidential

File Name : LA-2541

B

C

D

E

Thermal Sensor

1 1

ADM1032

page 4

Mobile
AMD Athlon 64

Fan Control

page 4

LVDS Panel
Interface

2 2

IDSEL:AD18
(PIRQH#,GNT#1,REQ#1)

CRT & TV OUT

Mini PCI
socket

3 3

page 28

BCM5788M

page 16

page 17

3.3V 33 MHz

IDSEL:AD17
(PIRQG#,GNT#3,REQ#3)

LAN

page 26

PCI BUS

IDSEL:AD20
(PIRQE#/F#,GNT#2,REQ#2)

CardBus & 1394
Controller

TI 7611

page 23,24

RTC CKT.

page 18

RJ45
CONN

page 27

Slot 0

page 24

Card
reader

page 23

1394
CONN

page 23

Power OK CKT.

page 40

Touch Pad
CONN

page 33

Power On/Off CKT.

page 38

754-pin

page 4, 5, 6, 7

HT 16x16 1000MHZ

ATI-RS480M

705 BGA

page 11, 12, 13, 14

A-Link Express
2 x PCIE

ATI-SB400

564 BGA

LPC BUS

EC SMSC
LPC47N250

page 37

Int.KBD

page 38

Memory BUS(DDR)

Single Channel

1 x PCIE

USB2.0

AC-LINK

BIOS

page 38

ATA-100

ATA-100

Primary IDE

Secondary IDE

DDR-SO-DIMM X2DDR1 -333

BANK 0, 1, 2, 3

SUPER I/O
LPC47N217

page 36

page 8,9,10

New Card
Connector

USB conn X3

Finger print

BT Conn

Audio CKT

HDD
Connector

CDROM
Connector

page 25

page 33

page 33

page 33

page 29

page 34

page 34

Clock Generator
ICS 951418

page 15

RJ11 CONN

page 30,39

MODEM

page 30

AMP & Audio Jack

page 31page 18,19,20,21

SPR Conn.

*RJ11 Conn
*RJ45 Conn
*Line IN Jack
*Line OUT Jack
*PS/2x2
*Parallel Port
*Serial Port
*CRT
*TV-OUT
*PCI Express
*USB x2

page 39

DC/DC Int erface CKT.

4 4

Power Circuit DC/DC

page 41

page 40~47

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Block Diagram
LA-2541

E

0.4

of

258Friday, April 15, 2005

A

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

O MEANS ON

X MEANS OFF

+5VALW

+3VALW

+1.8VALW

O

O

O

O

Only +3VL ON

+5VS

+3VS

+5V

+2.5V

+1.25V

+2.5VS

+1.8VS

+1.5VS

+2.5VDDA

+CPU_CORE

+1.2V_HT

+RS480_Core

OO

OO

O

X

XX

XX

Symbol note:

:means digital ground.

:means analog ground.

:means reserved(un-mount).@

4401@

5788@

7611@

4510@

:means populate for BCM4401 only.

:means populate for BCM5788M only.

:means populate for PCI7611 only.

:means populate for PCI4510 only.

PCI Devices

1 1

INTERNAL

PIRQ

A

B
B
D
D
D
A
A

E, F
H
GAD18

EXTERNAL

CARD BUS & 1394
LAN

Mini-PCI

DEVICE

SMBUS
IDE
LPC I/F
PCI to PCI
AC97 AUDIO
AC97 MODEM
OHCI#1 USB
OHCI#1 USB
EHCI USB
SATA#1
SATA#2

IDSEL #

AD20
AD17

REQ/GNT #

2
3
1

Jump

PJ1
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8

PJ9
PJ11
PJ12
PJ14

Normal operation KBC Internal ROM flash

Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad

J1
J2
J3
J4

Short Pad

Short Pad

No Short Pad
No Short Pad No Short Pad

J5
J6
J7
J8
J9

No Short Pad Short Pad
No Short Pad Short Pad

Short Pad No Short Pad

No Short Pad Short Pad

Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad
Short Pad

Short Pad

No Short Pad
No Short Pad

No Short Pad

Short PadNo Short Pad

Comment

+3VL

+3VALW

+1.8VALW

+5VALW

+1.5VS

+2.5V

+1.25V

+1.2V_HT

+RS480_Core

For ATE
For ATE

Clear CMOS

For ATE
For ATE
For ATE
For ATE
For ATE

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Notes List
LA-2541

of

358Friday, Ap ril 15, 2005

0.4

A

B

C

D

E

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0

LVREF1

44.2_0603_1%

H_CADIP[0..15]
H_CADIN[0..15]

LVREF0

12

R350

U10A

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

AF27

L0_REF1

AE26

L0_REF0

FOX_PZ75403-2941-42

Claw Hammer-DTR

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

HTT Interface

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

LDTSTOP_L

H_CADIP[0..15]<11>

4 4

3 3

+1.2V_HT

R353 49.9_0402_1%
R354 49.9_0402_1%

+1.2V_HT

1 2
1 2

H_CLKIP1<11>
H_CLKIN1<11>
H_CLKIP0<11>
H_CLKIN0<11>

H_CTLIP0<11>
H_CTLIN0<11>

R347 44.2_0603_1%

12

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP15

N26

H_CADON15

N27

H_CADOP14

L25

H_CADON14

M25

H_CADOP13

L26

H_CADON13

L27

H_CADOP12

J25

H_CADON12

K25

H_CADOP11

G25

H_CADON11

H25

H_CADOP10

G26

H_CADON10

G27

H_CADOP9

E25

H_CADON9

F25

H_CADOP8

E26

H_CADON8

E27

H_CADOP7

N29

H_CADON7

P29

H_CADOP6

M28

H_CADON6

M27

H_CADOP5

L29

H_CADON5

M29

H_CADOP4

K28

H_CADON4

K27

H_CADOP3

H28

H_CADON3

H27

H_CADOP2

G29

H_CADON2

H29

H_CADOP1

F28

H_CADON1

F27

H_CADOP0

E29

H_CADON0

F29

H_CLKOP1

J26

H_CLKON1

J27

H_CLKOP0

J29

H_CLKON0

K29
N25

P25

H_CTLOP0

P28

H_CTLON0

P27

LDTSTOP#

AJ27

H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>

H_CLKOP1 <11>
H_CLKON1 <11>
H_CLKOP0 <11>
H_CLKON0 <11>

H_CTLOP0 <11>
H_CTLON0 <11>

1 2

R336 1.2K_0402_5%

LDTSTOP# <13,18>

+2.5VS

PWM Fan Control circuit

+3VS

5

U28

1

FAN_PWM<38>

THERM#

INB

2

INA

P

4

O

G

TC7SH00FU_SSOP5

3

+5VS

JP7

1
2

ACES_85205-0200

FAN

1

C400

0.1U_0402_16V4Z

2

1

D21
RB751V_SOD323

2 1

6

2

1

D

Q28

G

3

SI3456DV-T1_TSOP6

S

4 5

C399

4.7U_0805_10V4Z

2

2 2

W=15mil

12

R124

10K_0402_5%

1 1

C202
2200P_0402_50V7K

A

+3VS

2

1

THERMDA_CPU
THERMDC_CPU

THERM#

C199

0.1U_0402_16V4Z

U11

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

SCLK

SDATA

ALERT#

8
7
6
5

Thermal Sensor
ADM1032

THERMDA_CPU
THERMDC_CPU

SB_SCLK <8,9,15,19>

THERM_SCI#

B

SB_SDAT <8,9,15,19>

THERMDA_CPU <6>
THERMDC_CPU <6>

THERM_SCI# <19>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Claw Harmmer CPU (Host Bus)

LA-2541

458Friday, April 15, 2005

E

of

0.4

A

B

C

D

E

+2.5V

DDR_SDQ[0..63]<8>

1 1

2 2

3 3

DDR_SDM[0..7]<8>

DDR_SDQS[0..7]<8>

+1.25VREF_CPU

50 mil width

R37034.8_0603_1%

12

R36934.8_0603_1%

12

DDR_SDQ63
DDR_SDQ62
DDR_SDQ61
DDR_SDQ60
DDR_SDQ59
DDR_SDQ58
DDR_SDQ57
DDR_SDQ56
DDR_SDQ55
DDR_SDQ54
DDR_SDQ53
DDR_SDQ52
DDR_SDQ51
DDR_SDQ50
DDR_SDQ49
DDR_SDQ48
DDR_SDQ47
DDR_SDQ46
DDR_SDQ45
DDR_SDQ44
DDR_SDQ43
DDR_SDQ42
DDR_SDQ41
DDR_SDQ40
DDR_SDQ39
DDR_SDQ38
DDR_SDQ37
DDR_SDQ36
DDR_SDQ35
DDR_SDQ34
DDR_SDQ33
DDR_SDQ32
DDR_SDQ31
DDR_SDQ30
DDR_SDQ29
DDR_SDQ28
DDR_SDQ27
DDR_SDQ26
DDR_SDQ25
DDR_SDQ24
DDR_SDQ23
DDR_SDQ22
DDR_SDQ21
DDR_SDQ20
DDR_SDQ19
DDR_SDQ18
DDR_SDQ17
DDR_SDQ16
DDR_SDQ15
DDR_SDQ14
DDR_SDQ13
DDR_SDQ12
DDR_SDQ11
DDR_SDQ10
DDR_SDQ9
DDR_SDQ8
DDR_SDQ7
DDR_SDQ6
DDR_SDQ5
DDR_SDQ4
DDR_SDQ3
DDR_SDQ2
DDR_SDQ1
DDR_SDQ0

DDR_SDM7
DDR_SDM6
DDR_SDM5
DDR_SDM4
DDR_SDM3
DDR_SDM2
DDR_SDM1
DDR_SDM0

DDR_SDQS7
DDR_SDQS6
DDR_SDQS5
DDR_SDQS4
DDR_SDQS3
DDR_SDQS2
DDR_SDQS1
DDR_SDQS0

MEMZN
MEMZP

AG12

D14
C14

C13

C11

AC1
AC3

AC2
AD1
AE1
AE3
AG3

AE2
AF1
AH3

AH9
AG5
AH5

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12
AJ14
AJ16

AA1
AG1
AH7

AH13

AB1

AJ13

A16
B15
A12
B11
A17
A15

A11
A10

AJ4

AJ3
AJ5
AJ6
AJ7

AJ9

A13

A14

AJ2
AJ8

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3

F1
G2
G1

L3

L1
G3

J2

L2
M1

W1
W3

W2

Y1

R1
A7

C2
H1

T1
A8

D1

J1

U10B

MEMVREF1
MEMZN

MEMZP
MEMDATA63

MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

Claw Hammer-DTR

DDR Memory

A CHANGEL ADDRESSB CHANGEL ADDRESS

MEMCKEA
MEMCKEB

MEMCLK_H7

MEMCLK_L7

MEMCLK_H6

MEMCLK_L6

MEMCLK_H5

MEMCLK_L5

MEMCLK_H4

MEMCLK_L4

MEMCLK_H3

MEMCLK_L3

MEMCLK_H2

MEMCLK_L2

MEMCLK_H1

MEMCLK_L1

MEMCLK_H0

MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

MEMADDB_B13
MEMADDB_B12
MEMADDB_B11
MEMADDB_B10

MEMADDB_B9
MEMADDB_B8
MEMADDB_B7
MEMADDB_B6
MEMADDB_B5
MEMADDB_B4
MEMADDB_B3
MEMADDB_B2
MEMADDB_B1
MEMADDB_B0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

AE8
AE7

D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

DDR_CKE0
DDR_CKE1

DDR_CLK7
DDR_CLK7#
DDR_CLK6
DDR_CLK6#
DDR_CLK5
DDR_CLK5#
DDR_CLK4
DDR_CLK4#

DDR_SCS#3
DDR_SCS#2
DDR_SCS#1
DDR_SCS#0

DDR_SMAA13
DDR_SMAA12
DDR_SMAA11
DDR_SMAA10
DDR_SMAA9
DDR_SMAA8
DDR_SMAA7
DDR_SMAA6
DDR_SMAA5
DDR_SMAA4
DDR_SMAA3
DDR_SMAA2
DDR_SMAA1
DDR_SMAA0

DDR_SMAB13
DDR_SMAB12
DDR_SMAB11
DDR_SMAB10
DDR_SMAB9
DDR_SMAB8
DDR_SMAB7
DDR_SMAB6
DDR_SMAB5
DDR_SMAB4
DDR_SMAB3
DDR_SMAB2
DDR_SMAB1
DDR_SMAB0

DDR_CKE0 <8>
DDR_CKE1 <9>

DDR_CLK7 <8>
DDR_CLK7# <8>
DDR_CLK6 <9>
DDR_CLK6# <9>
DDR_CLK5 <8>
DDR_CLK5# <8>
DDR_CLK4 <9>
DDR_CLK4# <9>

DDR_SCS#3 <9>
DDR_SCS#2 <9>
DDR_SCS#1 <8>
DDR_SCS#0 <8>

DDR_SRASA# <8>
DDR_SCASA# <8>
DDR_SWEA# <8>

DDR_SBSA1 <8>
DDR_SBSA0 <8>

DDR_SMAA[0..13] <8>

DDR_SRASB# <9>
DDR_SCASB# <9>
DDR_SWEB# <9>

DDR_SBSB1 <9>
DDR_SBSB0 <9>
DDR_SMAB[0..13] <9>

DDR_CLK5/5# & DDR_CLK7/7#
route to nearest DIMM
DDR_CLK4/4# & DDR_CLK6/6#
route to farthest DIMM

R130 120_0402_5%

DDR_CLK6
DDR_CLK5
DDR_CLK4

1 2

R129 120_0402_5%

1 2

R92 120_0402_5%

1 2

R83 120_0402_5%

1 2

within 1.00"

+2.5V

12

R320
1K_0402_1%

12

1

C418

R326
1K_0402_1%

2

0.1U_0402_16V4Z

DDR_CLK7#DDR_CLK7
DDR_CLK6#
DDR_CLK5#
DDR_CLK4#

+1.25VREF_CPU

1

C413
1000P_0402_50V7K

2

4 4

A

FOX_PZ75403-2941-42

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Claw Harmmer (Memory Bus)

LA-2541

E

558Friday, April 15 , 2005

of

0.4

A

H_THERMTRIP_S#

1 1

CPUCLK0_H<15>

CPUCLK0_L<15>

Place 169 Ohm within 0.5" from CPU
Route as DIF 5/5/5/20

+2.5VDDA

2 2

+2.5VS

3 3

@

4 4

C414
3900P_0402_50V7K

169_0402_1%

C415 3900P_0402_50V7K

L8
LQG21F4R7N00_0805

1 2

1

+

C84
100U_D2_10VM

2

4.7U_0805_6.3V6K

H_RST#

R319

JOPEN

DBREQ#
DBRDY
TCK
TMS
TDI
TRST#
TDO

H_RST#
H_PWRGD

J3

R445

560_0402_5%

A

1 2

R157 680_0402_5%

1 2

R324 680_0402_5%

100_0402_5%

12

R335

1

C92

2

0.22U_0603_10V7K

0.22U_0603_10V7K

H_PWRGD<18>

R334 80.6_0402_1%

Place within 0.5" from CPU
Route as 80 Ohm DIFF impedence 8/5/20

CPU_COREFB<49>
CPU_COREFB#<49>

+VDDA

1

C88

2

THERMDA_CPU<4>
THERMDC_CPU<4>

1

C535

12

12

Route as DIFF p air 10/5/10

3300P_0402_50V7K

1

C90

2

2

1 2

+2.5VS

560_0402_5%

R444

12

12

12

12

R441

@

R443
560_0402_5%

560_0402_5%

@

@

T4PAD
T5PAD
T3PAD

0.22U_0603_10V7K

T18PAD
T1PAD

560_0402_5%

R438

@

H_RST_CPU#
H_PWRGD

CLKIN
CLKIN#
FBCLKOUT

12

FBCLKOUT#

CPU_COREFB
CPU_COREFB#

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

50 mils width

VID4<49>
VID3<49>
VID2<49>
VID1<49>
VID0<49>

1

C534

2

12

@

R436
560_0402_5%

12

VID4
VID3
VID2
VID1
VID0

DBRDY
DBREQ#

TDO
TMS
TCK
TRST# SCANCLK2

TDI

4.7U_0805_6.3V6K

1

C532

2

+1.25V +1.25V

TP_K8_A28
TP_K8_AJ28

R435

12

560_0402_5%

+2.5VS

@

@

B

U10C

A20

THERMTRIP_L

AF20

RESET_L

AE18

PWROK

AJ21

CLKIN_H

AH21

CLKIN_L

AH19

FBCLKOUT_H

AJ19

FBCLKOUT_L

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AH25

VDDA1

AJ25

VDDA2

AG13

VID4

AF14

VID3

AG14

VID2

AF15

VID1

AE15

VID0

AH17

DBRDY

AE19

DBREQ_L

A26

THERMDA

A27

THERMDC

A22

TDO

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

D29

VLDT0_A

D27

VLDT0_A

D25

VLDT0_A

C28

VLDT0_A

C26

VLDT0_A

B29

VLDT0_A

B27

VLDT0_A

D17

VTT_A

A18

VTT_A

B17

VTT_A

C17

VTT_A

C16

VTT_A

A28

KEY1

AJ28

KEY0

FOX_PZ75403-2941-42

JP29

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@

B

Claw Hammer-DTR

Miscellaneous

Clock

Debug

JTAG

H_THERMTRIP_S# H_THERMTRIP#

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B

VTT_B
VTT_B
VTT_B
VTT_B
VTT_B

VTT_SENSE

+2.5VS

Issued Date

AG10

NC

E14

NC

D12

NC

E13

NC

C12

NC

D22

NC

C22

NC

B13

NC

B7

NC

C3

NC

K1

NC

R2

NC

AA3

NC

F3

NC

C23

NC

AG7

NC

AE22

NC

C24

NC

A25

NC

C9

NC

AE23

NC

AF23

NC

AF22

NC

AF21

NC

C1

NC

J3

NC

R3

NC

AA2

NC

D3

NC

AG2

NC

B18

NC

AH1

NC

AE21

NC

C20

NC

AG4

NC

C6

NC

AG6

NC

AE9

NC

AG9

NC

AF18

NC

AJ23

NC

AH23

NC

AE24

NC

AF24

NC

C15

NC

AG18

NC

AH18

NC

AG17

NC

AJ18

NC

C18

NC

A19

NC

D20

NC

C21

NC

D18

NC

C19

NC

B19

NC

AH29
AH27
AG28
AG26
AF29
AE28
AF25

AG15
AF16
AG16
AH16
AJ17
AE13

12

R131
680_0402_5%

TP_M_RESET#

TP_K8_D22
TP_K8_C22

CLAW_ANALOG3
CLAW_ANALOG2
CLAW_ANALOG1
CLAW_ANALOG0

BPSCLK
BPSCLK#
TP_K8_AE24
TP_K8_AF24
TP_K8_C15
TP_CPU_BP3
TP_CPU_BP2
BP1
BP0
SINCHN
BRN#
SCANCLK1

SCANEN
SCANSHENB
SCANSHENA

+1.2V_HT

VTT_SENSE

+2.5VS

12

R132
1K_0402_5%

2

Q9

3 1

MMBT3904_SOT23

C

+1.25V

T2 PAD

220U_D2_2.5VM

T17 PAD
T16 PAD

H_PWRGD

1

C416

470P_0402_50V7K@

T13 PAD
T11 PAD
T10 PAD
T9 PAD

H_RST#<18>

+2.5V

R323 820_0402_5%

1 2

R322 820_0402_5%

1 2

T12 PAD
T14 PAD
T15 PAD
T8 PAD
T7 PAD

R328 680_0402_5%

1 2

R333 680_0402_5%

1 2

R128 680_0402_5%

1 2

R127 680_0402_5%

1 2

R368 680_0402_5%

1 2

T6 PAD

+3VALW

12

2005/03/01 2006/03/11

C

2

R325

1 2

0_0402_5%

+3VALW

12

R126
10K_0402_5%

2

3 1

Compal Secret Data

Deciphered Date

H_RST_CPU#

1

C417

0.001U_0402_50V7M@

2

+2.5V

+2.5VS

R125

1K_0402_5%@

Q8

MMBT3904_SOT23@

H_THERMTRIP# <19>

+1.25V

4.7U_0805_6.3V6K

+1.25V

0.22U_0603_10V7K

MAINPWON <44,45,50>

D

E

Near Power Supply

1

1

2

1

2

1

2

+

+

C222

C201

C207

1U_0603_10V4Z@

D

C85

220U_D2_2.5VM

2

4.7U_0805_6.3V6K

1

C226

2

0.22U_0603_10V7K

1

C223

2

+3VS +2.5VDDA

C407

4.7U_0805_6.3V6K

1

C230

2

4.7U_0805_6.3V6K

0.22U_0603_10V7K

1

C224

2

0.22U_0603_10V7K

2

1

C231

2

1

C232

2

1

SCANCLK2
SCANCLK1
SCANEN
SCANSHENB

+1.2V_HT

1

+

2

100U_D2_10VM

C436

RP52

4 5
3 6
2 7
1 8

680_1206_8P4R_5%

0.22U_0603_10V7K

250 mil

1

1

C434

C433

2

2

0.22U_0603_10V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

4.7U_0805_6.3V6K

1

C55

2

4.7U_0805_6.3V6K

0.22U_0603_10V7K

1

C51

2

0.22U_0603_10V7K

+2.5VS

U29

1

IN

OUT

2

GND
SHDN3BYP

G914E_SOT23-5@

0.22U_0603_10V7K

1

C425

2

0.22U_0603_10V7K

1

C53

2

1

C50

2

1

2

Claw Harmmer (MISC)
LA-2541

4.7U_0805_6.3V6K

1

C58

2

4.7U_0805_6.3V6K

1

C52

2

0.22U_0603_10V7K

R318

1 2

0_0805_5%

5

4

1

C406

0.01U_0402_16V7K@

2

0.22U_0603_10V7K

1

C423

C426

2

1

2

0.22U_0603_10V7K

1

2

0.22U_0603_10V7K

E

1

C225

2

4.7U_0805_6.3V6K

1

C229

2

0.22U_0603_10V7K

2

C408
1U_0603_10V4Z

1

1

C424

2

658Friday, April 15 , 2005

C91

C89

0.4

A

U10E

B2

VSS

AH20

VSS

AB21

VSS

W22

+CPU_CORE +2.5V

U10D

L7

VDD

AC15

VDD

H18

VDD

B20

VDD

E21

VDD

H22

1 1

2 2

3 3

4 4

VDD

J23

VDD

H24

VDD

F26

VDD

N7

VDD

L9

VDD

V10

VDD

G13

VDD

K14

VDD

Y14

VDD

AB14

VDD

G15

VDD

J15

VDD

AA15

VDD

H16

VDD

K16

VDD

Y16

VDD

AB16

VDD

G17

VDD

J17

VDD

AA17

VDD

AC17

VDD

AE17

VDD

F18

VDD

K18

VDD

Y18

VDD

AB18

VDD

AD18

VDD

AG19

VDD

E19

VDD

G19

VDD

AC19

VDD

AA19

VDD

J19

VDD

F20

VDD

H20

VDD

K20

VDD

M20

VDD

P20

VDD

T20

VDD

V20

VDD

Y20

VDD

AB20

VDD

AD20

VDD

G21

VDD

J21

VDD

L21

VDD

N21

VDD

R21

VDD

U21

VDD

W21

VDD

AA21

VDD

AC21

VDD

F22

VDD

K22

VDD

M22

VDD

P22

VDD

T22

VDD

V22

VDD

Y22

VDD

AB22

VDD

AD22

VDD

E23

VDD

G23

VDD

L23

VDD

N23

VDD

R23

VDD

U23

VDD

W23

VDD

AA23

VDD

AC23

VDD

B24

VDD

D24

VDD

F24

VDD

K24

VDD

M24

VDD

P24

VDD

T24

VDD

V24

VDD

Y24

VDD

AB24

VDD

AD24

VDD

AH24

VDD

AE25

VDD

K26

VDD

P26

VDD

V26

VDD

FOX_PZ75403-2941-42

POWER

A

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

+CPU_CORE

VSS

M23

VSS

L24

VSS

AG25

VSS

AG27

VSS

D2

VSS

AF2

VSS

W6

VSS

Y7

VSS

AA8

VSS

AB9

VSS

AA10

VSS

J12

VSS

B14

VSS

Y15

VSS

AE16

VSS

J18

VSS

G20

VSS

R20

VSS

U20

VSS

W20

VSS

AA20

VSS

AC20

VSS

AE20

VSS

AG20

VSS

AJ20

VSS

D21

VSS

F21

VSS

H21

VSS

K21

VSS

M21

VSS

P21

VSS

T21

VSS

V21

VSS

Y21

VSS

AD21

VSS

AG21

VSS

B22

VSS

E22

VSS

G22

VSS

J22

VSS

L22

VSS

N22

VSS

R22

VSS

U22

VSS

AG29

VSS

AA22

VSS

AC22

VSS

AG22

VSS

AH22

VSS

AJ22

VSS

D23

VSS

F23

VSS

H23

VSS

K23

VSS

P23

VSS

T23

VSS

V23

VSS

Y23

VSS

AB23

VSS

AD23

VSS

AG23

VSS

E24

VSS

G24

VSS

J24

VSS

N24

VSS

R24

VSS

U24

VSS

W24

VSS

AA24

VSS

AC24

VSS

AG24

VSS

AJ24

VSS

B25

VSS

C25

VSS

B26

VSS

D26

VSS

H26

VSS

M26

VSS

T26

VSS

Y26

VSS

AD26

VSS

AF26

VSS

AH26

VSS

C27

VSS

B28

VSS

D28

VSS

G28

VSS

F15

VSS

H15

VSS

AB17

VSS

AD17

VSS

B16

VSS

G18

VSS

AA18

VSS

AC18

VSS

D19

VSS

F19

VSS

H19

VSS

K19

VSS

Y19

VSS

AB19

VSS

AD19

VSS

AF19

VSS

J20

VSS

L20

VSS

N20

VSS

FOX_PZ75403-2941-42

B

POWER

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18

Security Classification

F17
H17
K17
Y17

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE

820U_E9_2_5V_M_R7

+

C76

10U_0805_10V4Z

C126

4.7U_0805_6.3V6K

C511

1

+

C217

2

1

C137

2

10U_0805_10V4Z

1

C452

2

4.7U_0805_6.3V6K

330U_D_2VM_R15

1

2

820U_E9_2_5V_M_R7

+CPU_CORE

1

2

10U_0805_10V4Z

4 in Socket Cavity,
2 on backside under Socket

+CPU_CORE

1

2

4.7U_0805_6.3V6K

1

+

2

10U_0805_10V4Z

1

C154

2

4.7U_0805_6.3V6K

1

C544

2

330U_D_2VM_R15

1

+

C227

2

1

C127

2

10U_0805_10V4Z

1

C517

2

4.7U_0805_6.3V6K

CPU Decouping Capacitor

4.7U_0805_6.3V6K

1

1

2

4.7U_0805_6.3V6K

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

C121

C203

2

C228

10U_0805_10V4Z

1

C138

2

4.7U_0805_6.3V6K

1

C545

2

D

1

C155

2

1

C460

2

4.7U_0805_6.3V6K

D

+CPU_CORE

+CPU_CORE

1

C521

2

0.22U_0603_10V7K

Near Socket

+2.5V+2.5V

1

C194

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

2

E

1

C477
1000P_0402_50V7K

2

0.22U_0603_10V7K

1

C486

2

In Socket CavityClose to Socket

Loop Bandwidth
KHz

20
50

* 300 3300

1

C200

2

0.22U_0603_10V7K

Title

Size Document Number Rev

Custom

Date: Sheet

1

C476

0.1U_0402_16V4Z

2

1

C498

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

C478

2

Bulk Cappacitance
uF

1

C499

2

0.22U_0603_10V7K

1

C487

2

23000
9000

0.22U_0603_10V7K

1

C136

C164

2

0.22U_0603_10V7K

Claw Harmmer (Power & Ground)

1

2

LA-2541

0.22U_0603_10V7K

1

C124

2

C148

E

0.22U_0603_10V7K

1

C479

2

Total
ESR

2.5m ohm
(AMD)

0.9m ohm

1.5m ohm

758Friday, April 15 , 2005

of

0.4

A

+1.25VREF_MEM

+2.5V

DDR_DQ0
DDR_DQ5

DDR_DQS0

SB_SCLK<4,9,15,19>

SB_SDAT<4,9,15,19>

A

DDR_DQ3
DDR_DQ7

DDR_DQ9
DDR_DQ12

DDR_DQS1
DDR_DQ14

DDR_DQ15

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ19
DDR_DQ28

DDR_DQ24
DDR_DQS3

DDR_DQ26
DDR_DQ27

DDR_CKE0
DDR_SMAA12

DDR_SMAA9
DDR_SMAA7

DDR_SMAA5
DDR_SMAA3
DDR_SMAA1

DDR_SMAA10
DDR_SBSA0
DDR_SWEA#
DDR_SCS#0
DDR_SMAA13

DDR_DQ32
DDR_DQ36

DDR_DQS4
DDR_DQ34

DDR_DQ38
DDR_DQ40

DDR_DQ44
DDR_DQS5

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ49

DDR_DQS6
DDR_DQ50

DDR_DQ55
DDR_DQ56

DDR_DQ61
DDR_DQS7

DDR_DQ58
DDR_DQ59

+3VS

1 1

DDR_CLK5<5>
DDR_CLK5#<5>

2 2

DDR_CKE0<5>

DDR_SBSA0<5>
DDR_SWEA#<5>
DDR_SCS#0<5>

3 3

4 4

JP27

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

QTC_C106A-040SP11

B

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD

CKE0

DU/BA2

A11

A8

VSS

A6
A4
A2

A0
VDD
BA1

RAS#
CAS#

S1#

DU
VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

CK1#

CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7
VSS

DQ62
DQ63

VDD
SA0
SA1
SA2

DU

B

C

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

40mil

DDR_DQ4
DDR_DQ1

DDR_DM0
DDR_DQ2

DDR_DQ6
DDR_DQ8

DDR_DQ13
DDR_DM1

DDR_DQ10
DDR_DQ11

DDR_DQ16
DDR_DQ21

DDR_DM2
DDR_DQ22

DDR_DQ23
DDR_DQ25

DDR_DQ29
DDR_DM3

DDR_DQ30
DDR_DQ31

DDR_CKE0
DDR_SMAA11

DDR_SMAA8
DDR_SMAA6

DDR_SMAA4
DDR_SMAA2
DDR_SMAA0

DDR_SBSA1
DDR_SRASA#
DDR_SCASA#
DDR_SCS#1

DDR_DQ37
DDR_DQ33

DDR_DM4
DDR_DQ35

DDR_DQ39
DDR_DQ41

DDR_DQ45
DDR_DM5

DDR_DQ42
DDR_DQ43

DDR_DQ53
DDR_DQ52

DDR_DM6
DDR_DQ54

DDR_DQ51
DDR_DQ60

DDR_DQ57
DDR_DM7

DDR_DQ62
DDR_DQ63

STANDARD

SO-DIMM0

C

1

C63

0.1U_0402_16V4Z

2

DDR_SBSA1 <5>
DDR_SRASA# <5>
DDR_SCASA# <5>
DDR_SCS#1 <5>

DDR_CLK7# <5>
DDR_CLK7 <5>

D

DDR_SDQS[0..7]<5>
DDR_SDQ[0..63]<5>

+1.25VREF_MEM

DDR_SDQ0 DDR_DQ0
DDR_SDQ4
DDR_SDQ5
DDR_SDQ1

DDR_SDM0
DDR_SDQS0
DDR_SDQ2
DDR_SDQ3

DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9

DDR_SDQ12
DDR_SDQS1

DDR_SDM1 DDR_DM1

DDR_SDQ14

DDR_SDQ11

DDR_SDQ16 DDR_DQ16
DDR_SDQ17
DDR_SDQ21 DDR_DQ21

DDR_SDM2 DDR_DM2
DDR_SDQ18

DDR_SDQ28
DDR_SDQ25

DDR_SDQ24
DDR_SDQ29
DDR_SDQS3
DDR_SDM3

DDR_SDQ26
DDR_SDQ30
DDR_SDQ27
DDR_SDQ31

DDR_SDM[0..7]<5>
DDR_SMAA[0..13]<5>

RP8

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP11

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP14

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP15

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP16

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP17

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP20

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP23

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

RP24

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP27

1 8
2 7
3 6
4 5

10_0804_8P4R_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/03/01 2006/03/11

E

DDR_SDQS[0..7]

DDR_SDQ[0..63]
DDR_SDM[0..7]

DDR_SMAA[0..13]

DDR_DQ4
DDR_DQ5
DDR_DQ1

DDR_DM0
DDR_DQS0
DDR_DQ2
DDR_DQ3

DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9

DDR_DQ12
DDR_DQ13DDR_SDQ13
DDR_DQS1

DDR_DQ14
DDR_DQ10DDR_SDQ10
DDR_DQ15DDR_SDQ15
DDR_DQ11

DDR_DQ20DDR_SDQ20
DDR_DQ17

DDR_DQS2DDR_SDQS2
DDR_DQ18

DDR_DQ22DDR_SDQ22

DDR_DQ19DDR_SDQ19
DDR_DQ23DDR_SDQ23
DDR_DQ28
DDR_DQ25

DDR_DQ24
DDR_DQ29
DDR_DQS3
DDR_DM3

DDR_DQ26
DDR_DQ30
DDR_DQ27
DDR_DQ31

Compal Secret Data

Deciphered Date

E

F

RP36

DDR_SDQ32 DDR_DQ32
DDR_SDQ37
DDR_SDQ36 DDR_DQ36
DDR_SDQ33

DDR_SDQS4
DDR_SDM4 DDR_DM4
DDR_SDQ34
DDR_SDQ35

DDR_SDQ38
DDR_SDQ39

DDR_SDQ44
DDR_SDQ45
DDR_SDQS5
DDR_SDM5

DDR_SDQ47
DDR_SDQ42
DDR_SDQ46
DDR_SDQ43

DDR_SDQ48
DDR_SDQ53
DDR_SDQ49
DDR_SDQ52

DDR_SDQ54
DDR_SDQ50

DDR_SDQ51
DDR_SDQ55

DDR_SDQ57
DDR_SDQ61
DDR_SDM7
DDR_SDQS7 DDR_DQS7

DDR_SDQ62
DDR_SDQ58
DDR_SDQ63 DDR_DQ63
DDR_SDQ59

F

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

10_0804_8P4R_5%
RP37

10_0804_8P4R_5%
RP40

10_0804_8P4R_5%
RP43

10_0804_8P4R_5%

RP44

10_0804_8P4R_5%

RP47

10_0804_8P4R_5%

RP48

10_0804_8P4R_5%

RP51

10_0804_8P4R_5%

RP53

10_0804_8P4R_5%

RP56

10_0804_8P4R_5%

DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]

DDR_DQ37
DDR_DQ33

DDR_DQS4
DDR_DQ34

DDR_DQ35

DDR_DQ38
DDR_DQ39
DDR_DQ40DDR_SDQ40
DDR_DQ41DDR_SDQ41

DDR_DQ44
DDR_DQ45
DDR_DQS5
DDR_DM5

DDR_DQ47
DDR_DQ42
DDR_DQ46
DDR_DQ43

DDR_DQ48
DDR_DQ53
DDR_DQ49
DDR_DQ52

DDR_DM6DDR_SDM6
DDR_DQS6DDR_SDQS6
DDR_DQ54
DDR_DQ50

DDR_DQ51
DDR_DQ55
DDR_DQ60DDR_SDQ60
DDR_DQ56DDR_SDQ56

DDR_DQ57
DDR_DQ61
DDR_DM7

DDR_DQ62
DDR_DQ58

DDR_DQ59

G

DDR_DQ[0..63] <9>
DDR_DQS[0..7] <9>
DDR_DM[0..7] <9>

DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5

DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_SBSA0

DDR_SMAA11
DDR_SMAA8

12

R51
1K_0402_1%

12

DDR_SMAA6
DDR_SMAA4

DDR_SMAA2
DDR_SMAA0
DDR_SBSA1
DDR_SRASA#

DDR_SMAA13

DDR_SWEA#

DDR_SCASA#

DDR_SCS#0
DDR_SCS#1

DDR_CKE0

1

C64

0.1U_0402_16V4Z

2

BOM change

Layout note

Place these resistors
close to DIMM0,
all trace length<500 mil

Note:
DDR_SMAA13 Recommend for AMD

+2.5V

R60

1K_0402_1%

Title

Size Document Number Rev

Custom

Date: Sheet

G

DDR-SODIMM SLOT0
LA-2541

H

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

1 2

R116 47_0402_5%

1 2

R110 47_0402_5%

1 2

R109 47_0402_5%

R113 68_0402_5%

1 2
1 2

R108 68_0402_5%

1 2

R101 68_0402_5%

+1.25VREF_MEM

1

C62

2

858Friday, April 15 , 2005

H

+1.25V

RP29

18
27
36
45

RP33

18
27
36
45

RP28

18
27
36
45

RP32

18
27
36
45

1000P_0402_50V7K

of

0.4

A

+2.5V

JP28

1

VREF

3

DDR_DQ0
DDR_DQ5

DDR_DQS0
DDR_DQ3

DDR_DQ7

1 1

DDR_CLK4<5>
DDR_CLK4#<5>

2 2

DDR_CKE1<5>

DDR_SBSB0<5>
DDR_SWEB#<5>

DDR_SCS#2<5>

3 3

4 4

SB_SDAT<4,8,15,19>

SB_SCLK<4,8,15,19>

DDR_DQ9
DDR_DQ12

DDR_DQS1
DDR_DQ14

DDR_DQ15

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ19
DDR_DQ28

DDR_DQ24
DDR_DQS3

DDR_DQ26
DDR_DQ27

DDR_CKE1 DDR_CKE1
DDR_SMAB12

DDR_SMAB9
DDR_SMAB7

DDR_SMAB5
DDR_SMAB3
DDR_SMAB1

DDR_SMAB10
DDR_SBSB0
DDR_SWEB#
DDR_SCS#2 DDR_SCS#3
DDR_SMAB13

DDR_DQ32
DDR_DQ36

DDR_DQS4
DDR_DQ34

DDR_DQ38
DDR_DQ40

DDR_DQ44
DDR_DQS5

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ49

DDR_DQS6
DDR_DQ50

DDR_DQ55
DDR_DQ56

DDR_DQ61
DDR_DQS7

DDR_DQ58
DDR_DQ59

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU/A13

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

TYCO_1612560-1

DU/RESET#

DIMM1

REVERSE

A

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD
CKE0

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

A11

S1#

B

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

DU

100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

20 mil width

DDR_DQ4
DDR_DQ1

DDR_DM0
DDR_DQ2

DDR_DQ6
DDR_DQ8

DDR_DQ13
DDR_DM1

DDR_DQ10
DDR_DQ11

DDR_DQ16
DDR_DQ21

DDR_DM2
DDR_DQ22

DDR_DQ23
DDR_DQ25

DDR_DQ29
DDR_DM3

DDR_DQ30
DDR_DQ31

DDR_SMAB11
DDR_SMAB8

DDR_SMAB6
DDR_SMAB4
DDR_SMAB2
DDR_SMAB0

DDR_SBSB1
DDR_SRASB#
DDR_SCASB#

DDR_DQ37
DDR_DQ33

DDR_DM4
DDR_DQ35

DDR_DQ39
DDR_DQ41

DDR_DQ45
DDR_DM5

DDR_DQ42
DDR_DQ43

DDR_DQ53
DDR_DQ52

DDR_DM6
DDR_DQ54

DDR_DQ51
DDR_DQ60

DDR_DQ57
DDR_DM7

DDR_DQ62
DDR_DQ63

+3VS

+1.25VREF_MEM

1

C65

0.1U_0402_16V4Z

2

DDR_SBSB1 <5>
DDR_SRASB# <5>
DDR_SCASB# <5>
DDR_SCS#3 <5>

DDR_CLK6# <5>
DDR_CLK6 <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_DQ4
DDR_DQ1
DDR_DM0
DDR_DQ2

68_0804_8P4R_5%

DDR_DQ6
DDR_DQ8
DDR_DQ13
DDR_DM1

68_0804_8P4R_5%

DDR_DQ10
DDR_DQ11
DDR_DQ16
DDR_DQ21

68_0804_8P4R_5%

DDR_DM2
DDR_DQ22
DDR_DQ23
DDR_DQ25

68_0804_8P4R_5%

DDR_DQ29
DDR_DM3
DDR_DQ30

Note:
DDR_SMAB13 Recommend
for AMD.

Layout note

Place these resistor
close by DIMM1,
all trace length
Max=0.8"

DDR_DQS[0..7]<8>
DDR_DQ[0..63]<8>

DDR_DM[0..7]<8>
DDR_SMAB[0..13]<5>

2005/03/01 2006/03/11

C

DDR_DQS[0..7]

DDR_DQ[0..63]
DDR_DM[0..7]

DDR_SMAB[0..13]

Compal Secret Data

DDR_DQ31

68_0804_8P4R_5%

DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35

68_0804_8P4R_5%

DDR_DQ39
DDR_DQ41
DDR_DQ45
DDR_DM5

68_0804_8P4R_5%

DDR_DQ42
DDR_DQ43
DDR_DQ53
DDR_DQ52

68_0804_8P4R_5%

DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ60

68_0804_8P4R_5%

DDR_DQ57
DDR_DM7
DDR_DQ62
DDR_DQ63

68_0804_8P4R_5%

Deciphered Date

RP10

1 8
2 7
3 6
4 5

RP13

1 8
2 7
3 6
4 5

RP18

1 8
2 7
3 6
4 5

RP22

1 8
2 7
3 6
4 5

RP26

1 8
2 7
3 6
4 5

RP38

1 8
2 7
3 6
4 5

RP42

1 8
2 7
3 6
4 5

RP45

1 8
2 7
3 6
4 5

RP49

1 8
2 7
3 6
4 5

RP54

1 8
2 7
3 6
4 5

D

+1.25V

DDR_DQ0
DDR_DQ5
DDR_DQS0
DDR_DQ3

DDR_DQ7
DDR_DQ9
DDR_DQ12
DDR_DQS1

68_0804_8P4R_5%

DDR_DQ14
DDR_DQ15
DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18
DDR_DQ19
DDR_DQ28

DDR_DQ24
DDR_DQS3
DDR_DQ26
DDR_DQ27

68_0804_8P4R_5%

DDR_DQ32
DDR_DQ36
DDR_DQS4
DDR_DQ34

DDR_DQ38
DDR_DQ40
DDR_DQ44
DDR_DQS5

DDR_DQ47
DDR_DQ46
DDR_DQ48
DDR_DQ49

DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ56

DDR_DQ61
DDR_DQS7
DDR_DQ58
DDR_DQ59

Layout note

Place these resistor
closely DIMM1,
all trace
length<=800mil

D

E

+1.25V

RP9

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

RP12

1 8
2 7
3 6
4 5

RP19

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP21

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

RP25

1 8
2 7
3 6
4 5

RP39

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP41

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP46

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP50

1 8
2 7
3 6
4 5

68_0804_8P4R_5%
RP55

1 8
2 7
3 6
4 5

68_0804_8P4R_5%

Title

Size Document Number Rev

Custom

Date: Sheet

DDR_SMAB12
DDR_SMAB9
DDR_SMAB7
DDR_SMAB5

DDR_SMAB3
DDR_SMAB1
DDR_SMAB10
DDR_SBSB0

DDR_SMAB11
DDR_SMAB8
DDR_SMAB6
DDR_SMAB4

DDR_SMAB2
DDR_SMAB0
DDR_SBSB1
DDR_SRASB#

DDR_SMAB13

DDR_SWEB#

DDR_SCASB#

DDR_SCS#2

DDR_CKE1

DDR_SCS#3

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

1 2

R117 47_0402_5%

1 2

R111 47_0402_5%

1 2

R112 47_0402_5%

1 2

R114 68_0402_5%

1 2

R102 68_0402_5%

1 2

R115 68_0402_5%

DDR-SODIMM SLOT1

LA-2541

E

RP30

RP34

RP31

RP35

958Friday, April 15 , 2005

+1.25V

of

0.4

A

+2.5V

1

1

+

2

330U_6.3V_M

1 1

C180

+

C213
330U_6.3V_M

2

1

C95

2

4.7U_0805_6.3V6K

B

4.7U_0805_6.3V6K

1

C125

2

Near DIMMs

C

D

E

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

+1.25V

1

C66

2

0.1U_0402_16V4Z

+1.25V

2 2

1

C215

2

0.1U_0402_16V4Z

+1.25V

1

C139

2

0.1U_0402_16V4Z

+1.25V

1

C73

3 3

2

0.1U_0402_16V4Z

+1.25V

1

C221

2

0.1U_0402_16V4Z

+1.25V

1

C77

2

0.1U_0402_16V4Z

1

C204

2

0.1U_0402_16V4Z

1

C130

2

0.1U_0402_16V4Z

1

C80

2

0.1U_0402_16V4Z

1

C210

2

0.1U_0402_16V4Z

1

C128

2

0.1U_0402_16V4Z

1

C186

2

0.1U_0402_16V4Z

1

C141

2

0.1U_0402_16V4Z

1

C131

2

0.1U_0402_16V4Z

1

C192

2

0.1U_0402_16V4Z

1

C111

2

0.1U_0402_16V4Z

1

C182

2

0.1U_0402_16V4Z

1

C151

2

0.1U_0402_16V4Z

1

C107

2

0.1U_0402_16V4Z

1

C184

2

0.1U_0402_16V4Z

1

C113

2

0.1U_0402_16V4Z

1

C175

2

0.1U_0402_16V4Z

1

C165

2

0.1U_0402_16V4Z

1

C115

2

0.1U_0402_16V4Z

1

C179

2

0.1U_0402_16V4Z

1

C119

2

0.1U_0402_16V4Z

1

C120

2

0.1U_0402_16V4Z

1

C152

2

0.1U_0402_16V4Z

1

C122

2

0.1U_0402_16V4Z

1

C123

2

0.1U_0402_16V4Z

1

C174

2

0.1U_0402_16V4Z

1

C114

2

0.1U_0402_16V4Z

1

C166

2

0.1U_0402_16V4Z

1

C178

2

0.1U_0402_16V4Z

1

C116

2

0.1U_0402_16V4Z

1

C181

2

0.1U_0402_16V4Z

1

C106

2

0.1U_0402_16V4Z

1

C168

2

0.1U_0402_16V4Z

1

C183

2

0.1U_0402_16V4Z

1

C110

2

0.1U_0402_16V4Z

1

C189

2

0.1U_0402_16V4Z

1

C150

2

0.1U_0402_16V4Z

1

C153

2

0.1U_0402_16V4Z

1

C193

2

0.1U_0402_16V4Z

1

C158

2

0.1U_0402_16V4Z

1

C205

2

0.1U_0402_16V4Z

1

C78

2

0.1U_0402_16V4Z

1

C135

2

0.1U_0402_16V4Z

1

C211

2

0.1U_0402_16V4Z

1

C81

2

0.1U_0402_16V4Z

1

C214

2

0.1U_0402_16V4Z

1

C129

2

0.1U_0402_16V4Z

1

C220

2

0.1U_0402_16V4Z

1

C132

2

0.1U_0402_16V4Z

1

C67

2

0.1U_0402_16V4Z

1

C140

2

0.1U_0402_16V4Z

1

C75

2

0.1U_0402_16V4Z

+2.5V

1

C146

2

0.1U_0402_16V4Z

+2.5V

10U_0805_10V4Z

+1.25V

1

2

C209

1

C218

10U_0805_10V4Z

2

1

C145

2

0.1U_0402_16V4Z

4 4

1

2

0.1U_0402_16V4Z

A

C133

1

C147

2

0.1U_0402_16V4Z

1

C159

2

0.1U_0402_16V4Z

1

C169

2

0.1U_0402_16V4Z

B

1

C160

2

0.1U_0402_16V4Z

1

C170

2

0.1U_0402_16V4Z

1

C172

2

0.1U_0402_16V4Z

1

C161

2

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

C

1

C144

2

0.1U_0402_16V4Z

+2.5V

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

DDR SODIMM Decoupling

LA-2541

E

0.4

10 58Friday, April 15 , 2005

5

4

3

2

1

H_CADIP[0..15]<4>
H_CADIN[0..15]<4>

H_CADOP[0..15]<4>

D D

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4

1 2
1 2

H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP0

H_CTLON0

C C

H_CLKOP1<4>

H_CLKON1<4>

H_CLKOP0<4>

H_CLKON0<4>

H_CTLOP0<4>
H_CTLON0<4>

+1.2V_HT

B B

R346 49.9_0402_1%
R348 49.9_0402_1%

H_CADON[0..15]<4>

U9A

T26

HT_RXCAD15P

R26

HT_RXCAD15N

U25

HT_RXCAD14P

U24

HT_RXCAD14N

V26

HT_RXCAD13P

U26

HT_RXCAD13N

W25

HT_RXCAD12P

W24

HT_RXCAD12N

AA25

HT_RXCAD11P

AA24

HT_RXCAD11N

AB26

HT_RXCAD10P

AA26

HT_RXCAD10N

AC25

HT_RXCAD9P

AC24

HT_RXCAD9N

AD26

HT_RXCAD8P

AC26

HT_RXCAD8N

R29

HT_RXCAD7P

R28

HT_RXCAD7N

T30

HT_RXCAD6P

R30

HT_RXCAD6N

T28

HT_RXCAD5P

T29

HT_RXCAD5N

V29

HT_RXCAD4P

U29

HT_RXCAD4N

Y30

HT_RXCAD3P

W30

HT_RXCAD3N

Y28

HT_RXCAD2P

Y29

HT_RXCAD2N

AB29

HT_RXCAD1P

AA29

HT_RXCAD1N

AC29

HT_RXCAD0P

AC28

HT_RXCAD0N

Y26

HT_RXCLK1P

W26

HT_RXCLK1N

W29

HT_RXCLK0P

W28

HT_RXCLK0N

P29

HT_RXCTLP

N29

HT_RXCTLN

D27

HT_RXCALN

E27

HT_RXCALP

216MPA4AKA22HK RS480M BGA 706P

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

HYPER TRANSPORT CPU

I/F

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P

HT_TXCAD9N

HT_TXCAD8P

HT_TXCAD8N

HT_TXCAD7P

HT_TXCAD7N

HT_TXCAD6P

HT_TXCAD6N

HT_TXCAD5P

HT_TXCAD5N

HT_TXCAD4P

HT_TXCAD4N

HT_TXCAD3P

HT_TXCAD3N

HT_TXCAD2P

HT_TXCAD2N

HT_TXCAD1P

HT_TXCAD1N

HT_TXCAD0P

HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

H_CADIP15

R24

H_CADIN15

R25

H_CADIP14

N26

H_CADIN14

P26

H_CADIP13

N24

H_CADIN13

N25

H_CADIP12

L26

H_CADIN12

M26

H_CADIP11

J26

H_CADIN11

K26

H_CADIP10

J24

H_CADIN10

J25

H_CADIP9

G26

H_CADIN9

H26

H_CADIP8

G24

H_CADIN8

G25

H_CADIP7

L30

H_CADIN7

M30

H_CADIP6

L28

H_CADIN6

L29

H_CADIP5

J29

H_CADIN5

K29

H_CADIP4

H30

H_CADIN4

H29

H_CADIP3

E29

H_CADIN3

E28

H_CADIP2

D30

H_CADIN2

E30

H_CADIP1

D28

H_CADIN1

D29

H_CADIP0

B29

H_CADIN0

C29

H_CLKIP1

L24

H_CLKIN1

L25

H_CLKIP0

F29

H_CLKIN0

G29

H_CTLIP0

M29

H_CTLIN0

M28

R345 100_0402_5%

B28

1 2

A28

H_CLKIP1 <4>

H_CLKIN1 <4>

H_CLKIP0 <4>

H_CLKIN0 <4>

H_CTLIP0 <4>
H_CTLIN0 <4>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C529

C524

+2.5VS

U9B

AF17

MEM_A0

AK17

MEM_A1

AH16

MEM_A2

AF16

MEM_A3

AJ22

MEM_A4

AJ21

MEM_A5

AH20

MEM_A6

AH21

MEM_A7

AK19

MEM_A8

AH19

MEM_A9

AJ17

MEM_A10

AG16

MEM_A11

AG17

MEM_A12

AH17

MEM_A13

AJ18

MEM_A14

AG26

MEM_DM0

AJ29

MEM_DM1

AE21

MEM_DM2

AH24

MEM_DM3

AH12

MEM_DM4

AG13

MEM_DM5

AH8

MEM_DM6

AE8

MEM_DM7

AF25

MEM_DQS0P

AH30

MEM_DQS1P

AG20

MEM_DQS2P

AJ25

MEM_DQS3P

AH13

MEM_DQS4P

AF14

MEM_DQS5P

AJ7

MEM_DQS6P

AG8

MEM_DQS7P

AG25

MEM_DQS0N

AH29

MEM_DQS1N

AF21

MEM_DQS2N

AK25

MEM_DQS3N

AJ12

MEM_DQS4N

AF13

MEM_DQS5N

AK7

MEM_DQS6N

AF9

MEM_DQS7N

AE17

MEM_RAS#

AH18

MEM_CAS#

AE18

MEM_WE#

AJ19

MEM_CS#

AF18

MEM_CKE

AK16

MEM_CKP

AJ16

MEM_CKN

C520 0.47U_0603_16V7K

1 2

C188 0.47U_0603_16V7K

12

1

2

1

2

R358
1K_0402_1%

12

R359
1K_0402_1%

MEM_VREF

+1.8VS

1 2

R357

1 2

R123

1 2

0_0805_5%

0_0402_5%

1U_0603_10V4Z

C191

1 2

AE28

MEM_CAP1

AJ4

MEM_CAP2

AJ20

MEM_VMODE

AK20

MEM_VREF

AJ15

MPVDD

AJ14

MPVSS

216MPA4AKA22HK RS480M BGA 706P

MEM_A I/F

MEM_COMPP
MEM_COMPN

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7

AH5
AD30

R363 49.9_0402_1%@

1 2

R355 49.9_0402_1%@

1 2

+2.5VS

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RS480M HT/MEM

LA-2541

1

0.4

of

11 58Friday, April 15, 2005

5

D D

C C

PCIE_MRX_C_PTX_P0<26>
PCIE_MRX_C_PTX_N0<26>

PCIE_MRX_C_PTX_P1<40>
PCIE_MRX_C_PTX_N1<40>

SB_RX0P<18>
SB_RX0N<18>

SB_RX1P<18>
SB_RX1N<18>

B B

4

PCIE_MRX_C_PTX_P0
PCIE_MRX_C_PTX_N0

PCIE_MRX_C_PTX_N1

SB_RX0P
SB_RX0N

SB_RX1P
SB_RX1N

R356 10K_0402_5%

1 2
1 2

R121 8.25K_0402_1%

U9C

D8

GFX_RX0P

D7

GFX_RX0N

D5

GFX_RX1P

D4

GFX_RX1N

E4

GFX_RX2P

F4

GFX_RX2N

G5

GFX_RX3P

G4

GFX_RX3N

H4

GFX_RX4P

J4

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

G1

GFX_RX6P

G2

GFX_RX6N

K5

GFX_RX7P

K4

GFX_RX7N

L4

GFX_RX8P

M4

GFX_RX8N

N5

GFX_RX9P

N4

GFX_RX9N

P4

GFX_RX10P

R4

GFX_RX10N

P5

GFX_RX11P

P6

GFX_RX11N

P2

GFX_RX12P

R2

GFX_RX12N

T5

GFX_RX13P

T4

GFX_RX13N

U4

GFX_RX14P

V4

GFX_RX14N

W1

GFX_RX15P

W2

GFX_RX15N

AE1

GPP_RX0P

AE2

GPP_RX0N

AB2

GPP_RX1P

AC2

GPP_RX1N

PCIE I/F TO SLOT

GPP_RX2P
GPP_RX2N

GPP_RX3P
GPP_RX3N

216MPA4AKA22HK RS480M BGA 706P

SB_RX0P
SB_RX0N

PCIE I/F TO SB

SB_RX1P
SB_RX1N

PCE_ISET
PCE_TXISET

AG1

AB5
AB4

Y4

AA4

AH1
AC5

AC6
AH3

AJ3

3

A7

GFX_TX0P

B7

GFX_TX0N

B6

GFX_TX1P

B5

GFX_TX1N

A5

GFX_TX2P

A4

GFX_TX2N

B3

GFX_TX3P

B2

GFX_TX3N

C1

GFX_TX4P

D1

GFX_TX4N

D2

GFX_TX5P

E2

GFX_TX5N

F2

GFX_TX6P

F1

GFX_TX6N

H2

GFX_TX7P

J2

GFX_TX7N

J1

GFX_TX8P

K1

GFX_TX8N

K2

GFX_TX9P

L2

GFX_TX9N

M2

GFX_TX10P

M1

GFX_TX10N

N1

GFX_TX11P

N2

GFX_TX11N

R1

GFX_TX12P

T1

GFX_TX12N

T2

GFX_TX13P

PCIE I/F TO VIDEO

GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P
GPP_TX0N

GPP_TX1P
GPP_TX1N

GPP_TX2P
GPP_TX2N

GPP_TX3P
GPP_TX3N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

PCE_PCAL
PCE_NCAL

U2
V2
V1
Y2
AA2

PCIE_MTX_PRX_P0

AD2
AD1

AA1
AB1

Y5
Y6

W5
W4

AF2
AG2

AC4
AD4

AH2
AJ2

C167 0.1U_0402_16V4Z

PCIE_MTX_PRX_N0

C171 0.1U_0402_16V4Z

PCIE_MTX_PRX_P1PCIE_MRX_C_PTX_P1

C143 0.1U_0402_16V4Z
C149 0.1U_0402_16V4Z

SB_TX0P_C

C173 0.1U_0402_16V4Z

SB_TX0N_C

C176 0.1U_0402_16V4Z

SB_TX1P_C

C157 0.1U_0402_16V4Z

SB_TX1N_C

C162 0.1U_0402_16V4Z

R119 150_0402_1%

1 2
1 2

R120 82.5_0402_1%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1PCIE_MTX_PRX_N1

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

+1.2V_HT

2

SB_TX0P <18>
SB_TX0N <18>

SB_TX1P <18>
SB_TX1N <18>

PCIE_MTX_C_PRX_P0 <26>
PCIE_MTX_C_PRX_N0 <26>

PCIE_MTX_C_PRX_P1 <40>
PCIE_MTX_C_PRX_N1 <40>

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

RS480M PCIE/DVI Controller

Size Document Number Rev

Custom

2

Date: Sheet

LA-2541

12 58Friday, April 15, 2005

1

0.4

of

12

75_0402_1%

R340

12

75_0402_1%

R339

12

75_0402_1%

RED

GREEN

BLUE

R338

+1.8VS

1 2

1 2

+1.8VS

R360

4.7K_0402_5%

R364
470K_0402_5%

+1.8VS

FBML10160808121LMT_0603

12

12

R75

75_0402_1%

75_0402_1%

+1.8VS

L14

1 2

FBML10160808121LMT_0603

10U_0805_10V4Z
L34

150_0603_1%

10U_0805_10V4Z

+3VS

+3VS

R71

4.7K_0402_5%

1 2

L31

1 2

10U_0805_10V4Z

12

R73

R74

75_0402_1%

VSYNC<17>
HSYNC<17>

3VDDCCL<17>
3VDDCDA<17>

1

C101

2

1

C459

2

SUS_STAT#

L35

1 2

FBML10160808121LMT_0603

NB_REFCLK<15>

R70

4.7K_0402_5%

1 2

EDID_DAT_LCD

+3VS

FBML10160808121LMT_0603

0.1U_0402_16V4Z

1

1

C439

C430

1U_0603_10V4Z

2

2

1

C98

1U_0603_10V4Z

2

1

C461

1U_0603_10V4Z

2

BMREQ#<18>
EDID_CLK_LCD<16>
EDID_DAT_LCD<16>

L13

1 2

0.1U_0402_16V4Z

+1.8VS

ALLOW_LDTSTOP<18>

C457

+AVDD

1

C437

2

1

C438

2

R67 715_0402_1%

1 2

+NB_PLLVDD

+NB_HTPVDD

NB_RST#<18,26,35,37,38,39>

NB_PWRGD<18,38,41>

LDTSTOP#<4,18>

+NB_VDDR3

1 2

1U_0603_10V4Z

R68 10K_0402_5%

SPMEM_EN#<22>
LOAD_ROM#<22>

EDID_CLK_LCDEDID_CLK_LCD
EDID_DAT_LCD

2

1U_0603_10V4Z

1

+AVDDQ

CRMA
LUMA
COMPS

RED
GREEN
BLUE

12

C99

U9D

B27

AVDD1

C27

AVDD2

D26

AVSSN1

D25

AVSSN2

C24

AVDDDI

B24

AVSSDI

E24

AVDDQ

D24

AVSSQ

B25

C

A25

Y

A24

COMP

C25

RED

A26

GREEN

B26

BLUE

A11

DAC_VSYNC

B11

DAC_HSYNC

C26

RSET

E11

DAC_SCL

F11

DAC_SDA

A14

PLLVDD

B14

PLLVSS

M23

HTPVDD

L23

HTPVSS

D14

SYSRESET#

B15

POWERGOOD

B12

LDTSTOP#

C12

ALLOW_LDTSTOP

AH4

SUS_STAT#

H13

VDDR3_1

H12

VDDR3_2

A13

OSCIN

B13

OSCOUT

B9

TVCLKIN

F12

DFT_GPIO0/RSV

E13

DFT_GPIO1/RSV

D13

DFT_GPIO2/RSV

F10

BMREQb

C10

I2C_CLK

C11

I2C_DATA

AF4

THERMALDIODE_P

AE4

THERMALDIODE_N

216MPA4AKA22HK RS480M BGA 706P

CRT/TVOUT

PLL PWR

PM

CLOCKs

MIS.

TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXCLK_UP
TXCLK_UN

TXCLK_LP

TXCLK_LN

LVDS

LPVDD
LPVSS

LVDDR18D
LVDDR18A_1
LVDDR18A_2

LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

GFX_CLKP

GFX_CLKN

HTTSTCLK

HTREFCLK

SB_CLKP
SB_CLKN

DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV

TMDS_HPD

STRP_DATA

DDC_DATA

TESTMODE

LVDSB0+

D18

LVDSB0-

C18

LVDSB1+

B19

LVDSB1-

A19

LVDSB2+

D19

LVDSB2-

C19
D20
C20

LVDSA0+

B16

LVDSA0-

A16

LVDSA1+

D16

LVDSA1-

C16

LVDSA2+

B17

LVDSA2-

A17
E17
D17

LVDSBC+

B20

LVDSBC-

A20

LVDSAC+

B18

LVDSAC-

C17
E18

F17
E19
G20

+LVDDR18A

H20
G19

E20
F20
H18
G18
F19
H19
F18

E14
F14
F13

B8
A8

P23
N23

E8
E7

C13
C14
C15

A10
E10

R69 4.7K_0402_5%

B10
E12

C456

0.1U_0402_16V4Z

R498 0_0402_5%
R499 0_0402_5%@

R500 0_0402_5%

R352 10K_0402_5%

1 2

HTREFCLK

STRP_DATA

1 2

R343 4.7K_0402_5%

1 2

LVDSB0+ <16>
LVDSB0- <16>
LVDSB1+ <16>
LVDSB1- <16>
LVDSB2+ <16>
LVDSB2- <16>

LVDSA0+ <16>
LVDSA0- <16>
LVDSA1+ <16>
LVDSA1- <16>
LVDSA2+ <16>
LVDSA2- <16>

LVDSBC+ <16>
LVDSBC- <16>
LVDSAC+ <16>
LVDSAC- <16>

+LVDDR18D

NBSRCCLK <15>
NBSRCCLK# <15>

HTREFCLK <15>
SBLINKCLK <15>

SBLINKCLK# <15>

1 2

R327 2.2K_0402_5%

1 2

R329 2.2K_0402_5%@

1 2

FBML10160808121LMT_0603

1

1

C419
1U_0603_10V4Z

2

2

12
12

12

L29

INV_PWM <16>
ENVDD <16>

+3VS

STRP_DATA <48>

+3VS

+1.8VS

+LPVDD

0.1U_0402_16V4Z

1

+1.8VS

C443

0.1U_0402_16V4Z

12

R515
2K_0402_5%

2

1

C447

2

L30

1 2

FBML10160808121LMT_0603

1

C420
1U_0603_10V4Z

2

HTREFCLK

ENABLT <16>

ENVDD

12

R521
10K_0402_5%

L15

1 2

FBML10160808121LMT_0603

1

C100
1U_0603_10V4Z

2

+1.8VS

12

R46
10_0402_5%@

1

C56
10P_0402_25V8K@

2

L11

1 2

CHB1608B121_0603SVIDEO@

CRMA D_CRMA

COMPS

C94

C93

270P_0402_50V7KSVIDEO@

C103

270P_0402_50V7KSVIDEO@

SVIDEO@

270P_0402_50V7K

L12

1 2

CHB1608B121_0603SVIDEO@
L10

1 2

CHB1608B121_0603SVIDEO@

270P_0402_50V7KSVIDEO@

D_LUMALUMA

D_COMPS

C86

C83

SVIDEO@

270P_0402_50V7K

C87

D_LUMA <17,40>

D_CRMA <17,40>

D_COMPS <17,40>

270P_0402_50V7KSVIDEO@

RED

BLUE

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L28

1 2

HLC0603CSCC39NJT_0603

L27

1 2

HLC0603CSCC39NJT_0603

L26

1 2

HLC0603CSCC39NJT_0603

2005/03/01 2006/03/11

RED_L

GREEN_L

BLUE_L

1

C410

2

18P_0402_50V8J

Compal Secret Data

1

C411
18P_0402_50V8J

2

Deciphered Date

L25

1 2

HLC0603CSCCR11JT_0603

L24

1 2

HLC0603CSCCR11JT_0603

L23

1 2

HLC0603CSCCR11JT_0603

1

C412

2

18P_0402_50V8J

CRT_RED

CRT_GREENGREEN

CRT_BLUE

CRT_RED <17,40>

CRT_GREEN <17,40>

CRT_BLUE <17,40>

Title

Size Document Number Rev

Custom

Date: Sheet

RS480M VIDEO_IF/CLOCK GEN

LA-2541

13 58Friday, April 15, 2005

of

0.4

5

U9F

G10

VSS1

G12

VSS2

AD29

VSS3

AD27

VSS4

AC27

VSS5

G15

VSS6

G14

VSS7

Y24

VSS8

G13

VSS9

E9

VSS10

D15

VSS11

D9

VSS12

AD9

VSS13

G11

D D

VSS30

C C

B B

VSS89

A A

VSS14

F16

VSS15

G30

VSS16

AB28

VSS17

AB25

VSS18

D12

VSS19

AD24

VSS20

AA28

VSS21

G17

VSS22

Y23

VSS23

AC9

VSS24

R19

VSS25

Y27

VSS26

C28

VSS27

G16

VSS28

F25

VSS29

B30

VSS30

T24

VSS31

F26

VSS32

W27

VSS33

D11

VSS34

H11

VSS35

AD25

VSS36

H17

VSS37

H10

VSS38

H16

VSS39

H14

VSS40

E16

VSS41

D10

VSS42

E15

VSS43

F15

VSS44

U15

VSS45

V14

VSS46

R15

VSS47

T14

VSS48

N15

VSS49

V12

VSS50

N13

VSS51

P14

VSS52

U17

VSS53

T16

VSS54

R17

VSS55

P12

VSS56

T12

VSS57

R13

VSS58

W13

VSS59

W17

VSS60

P18

VSS61

V18

VSS62

M18

VSS63

U13

VSS64

N17

VSS65

W15

VSS66

V16

VSS67

T18

VSS68

M14

VSS69

M12

VSS70

M16

VSS71

P16

VSS72

U19

VSS73

AC16

VSS74

AG18

VSS75

AC23

VSS76

AD8

VSS77

AD11

VSS78

AD13

VSS79

AD16

VSS80

AD19

VSS81

AD23

VSS82

AG5

VSS83

AG6

VSS84

AG21

VSS85

AD17

VSS86

AG15

VSS87

AG12

VSS88

AF30

VSS89

AG24

VSS90

AG9

VSS91

AC19

VSS92

AG27

VSS93

AC11

VSS94

AD7

VSS95

AJ30

VSS96

AC21

VSS97

AK5

VSS98

AK10

VSS99

AC13

VSS100

AD21

VSS101

AK22

VSS102

AK29

VSS103

W19

VSS104

AE26

VSS105

AE27

VSS106

T27

VSS107

R27

VSS108

AD28

VSS109

F24

VSS110

F27

VSS111

G28

VSS112

216MPA4AKA22HK RS480M BGA 706P

5

GROUND

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51
VSSA52
VSSA53
VSSA54
VSSA55
VSSA56
VSSA57
VSSA58
VSSA59
VSSA60
VSSA61
VSSA62
VSSA63
VSSA64
VSSA65
VSSA66
VSSA67
VSSA68

VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120

VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132

R5
AE5
V5
N3
F7
F5
R3
AA6
T3
M6
C5
F8
M8
Y8
V3
C3
W3
K8
D3
C6
AA3
A2
AB3
P8
J6
C8
AD3
V8
F3
AE3
AF3
M5
AB7
G3
B4
P7
AA5
C9
C7
J5
R6
J3
AD5
D6
C4
K3
AB8
T7
Y7
AD6
K7
H7
M3
V6
H8
C2
AG3
L6
AJ1
M7
V7
F6
E6
U5
U6
E5
L5
T8

F28
H28
M24
J28
N19
K28
T23
L27

M27
H24
N28
P25
P28
E26
K25
U28
V25
V28
R23

VSSA22

VSSA59

4

+VDDA12_13

1

C429

4.7U_0805_6.3V6K

2

VSSA22

+VDDA18_13

1

C530

4.7U_0805_6.3V6K

2

VSSA59

+VDDHT30

1

C102

4.7U_0805_6.3V6K

2

VSS30

+VDDHT31

1

C509

4.7U_0805_6.3V6K

2

VSS89

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L16

1 2

+1.8VS

FBML10160808121LMT_0603

3

2

+1.2V_HT

C42122U_1206_10V4Z

12

C4320.1U_0402_16V4Z

12

C4850.1U_0402_16V4Z

12

C4310.1U_0402_16V4Z

12

C4810.1U_0402_16V4Z

12

C4510.1U_0402_16V4Z

12

C4960.1U_0402_16V4Z

12

C4460.1U_0402_16V4Z

12

C4440.1U_0402_16V4Z

12

C4660.1U_0402_16V4Z

12

C4820.1U_0402_16V4Z

12

C4680.1U_0402_16V4Z

12

C4650.1U_0402_16V4Z

12

C4950.1U_0402_16V4Z

12

+2.5VS

C53122U_1206_10V4Z

12

C5080.1U_0402_16V4Z

12

C5070.1U_0402_16V4Z

12

C5050.1U_0402_16V4Z

12

C5020.1U_0402_16V4Z

12

C5010.1U_0402_16V4Z

12

C5120.1U_0402_16V4Z

12

C5220.1U_0402_16V4Z

12

C5060.1U_0402_16V4Z

12

C5260.1U_0402_16V4Z

12

C5250.1U_0402_16V4Z

12

C5180.1U_0402_16V4Z

12

C5140.1U_0402_16V4Z

12

C5150.1U_0402_16V4Z

12

C5160.1U_0402_16V4Z

12

C5000.1U_0402_16V4Z

12

C5130.1U_0402_16V4Z

12

C5270.1U_0402_16V4Z

12

C5280.1U_0402_16V4Z

12

+VDD18

C1901U_0603_10V4Z

12

C1870.1U_0402_16V4Z

12

C5030.1U_0402_16V4Z

12

C5040.1U_0402_16V4Z

12

C4500.1U_0402_16V4Z

12

2005/03/01 2006/03/11

+VDDHT30
+VDDHT31

Compal Secret Data

U9E

N27

VDD_HT1

U27

VDD_HT2

V27

VDD_HT3

G27

VDD_HT4

V24

VDD_HT5

H27

VDD_HT6

K24

VDD_HT7

AB24

VDD_HT8

P27

VDD_HT9

J27

VDD_HT10

AA27

VDD_HT11

K27

VDD_HT12

P24

VDD_HT13

AB27

VDD_HT14

AB23

VDD_HT15

V23

VDD_HT16

G23

VDD_HT17

E23

VDD_HT18

W23

VDD_HT19

K23

VDD_HT20

J23

VDD_HT21

H23

VDD_HT22

U23

VDD_HT23

AA23

VDD_HT24

D23

VDD_HT25

F23

VDD_HT26

C23

VDD_HT27

B23

VDD_HT28

A23

VDD_HT29

A29

VDD_HT30

AC30

VDD_HT31

AK23

VDD_MEM1

AK28

VDD_MEM2

AK11

VDD_MEM3

AK4

VDD_MEM4

AE30

VDD_MEM5

AC14

VDD_MEM6

AD12

VDD_MEM7

AC18

VDD_MEM8

AC20

VDD_MEM9

AD10

VDD_MEM10

AD14

VDD_MEM11

AD15

VDD_MEM12

AD20

VDD_MEM13

AC10

VDD_MEM14

AD18

VDD_MEM15

AC12

VDD_MEM16

AD22

VDD_MEM17

AC22

VDD_MEM18

AH15

VDD_MEMCK

H15

VDD18_1

AC17

VDD18_2

AC15

VDD18_3

B21

VDD_CORE47

C21

VDD_CORE46

A22

VDD_CORE45

B22

VDD_CORE44

C22

VDD_CORE43

F21

VDD_CORE42

F22

VDD_CORE41

E21

VDD_CORE40

G21

VDD_CORE39

216MPA4AKA22HK RS480M BGA 706P

Deciphered Date

POWER

2

VDDA12_14

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDA12_13

VDDA18_1

VDDA18_2

VDDA18_3

VDDA18_4

VDDA18_5

VDDA18_6

VDDA18_7

VDDA18_8

VDDA18_9
VDDA18_10
VDDA18_11
VDDA18_12
VDDA18_13

VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8

VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38

1

+1.2V_HT

H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21

Custom

Date: Sheet

C483 22U_1206_10V4Z

1 2

C480 1U_0603_10V4Z

1 2

C449 0.1U_0402_16V4Z

1 2

C474 0.1U_0402_16V4Z

1 2

C497 0.1U_0402_16V4Z

1 2

C453 0.1U_0402_16V4Z

1 2

+VDDA12_13

+VDDA18

R365

12

0_0805_5%

C533 1U_0603_10V4Z

1 2

C519 0.1U_0402_16V4Z

1 2

C510 0.1U_0402_16V4Z

1 2

C492 0.1U_0402_16V4Z

1 2

C469 0.1U_0402_16V4Z

1 2

+VDDA18_13

+RS480_Core

C475 22U_1206_10V4Z

1 2

C458 22U_1206_10V4Z

1 2

C427 0.1U_0402_16V4Z

1 2

C470 0.1U_0402_16V4Z

1 2

C471 0.1U_0402_16V4Z

1 2

C472 0.1U_0402_16V4Z

1 2

C473 0.1U_0402_16V4Z

1 2

C488 0.1U_0402_16V4Z

1 2

C489 0.1U_0402_16V4Z

1 2

C490 0.1U_0402_16V4Z

1 2

C491 0.1U_0402_16V4Z

1 2

C445 0.1U_0402_16V4Z

1 2

C464 0.1U_0402_16V4Z

1 2

C467 0.1U_0402_16V4Z

1 2

C463 0.1U_0402_16V4Z

1 2

C442 0.1U_0402_16V4Z

1 2

C462 0.1U_0402_16V4Z

1 2

C455 0.1U_0402_16V4Z

1 2

C494 0.1U_0402_16V4Z

1 2

C454 0.1U_0402_16V4Z

1 2

C493 0.1U_0402_16V4Z

1 2

C484 0.1U_0402_16V4Z

1 2

Title

Size Document Number Rev

RS480M Power/GND

LA-2541

+1.8VS

14 58Friday, April 15, 2005

1

0.4

of

A

B

C

D

E

F

G

H

+3VS +3V_CLK

L7

NB_REFCLK<13>

2

Width=40 mils

C79

2.2U_0805_16V4Z

XTALIN_CLK
XTALOUT_CLK

+3VS

R455
10K_0402_5%

1 2

CLK_STOP

Q47
MMBT3904_SOT23

3 1

+3VS

12

L9

+3VS
CPPE_DOCK#<19,40>

NC_CLKREQ#<26>
+3VS

1 1

C108

22P_0402_50V8J

1 2

1 2

+RS480_Core

C109

22P_0402_50V8J

R508

1 2

1K_0402_5%

R509

1 2

1K_0402_5%@

2 2

3 3

VGATE<41,47,48,49>

1 2

CHB2012U121_0805

CHB2012U121_0805

12

Y2

14.31818MHZ_20P_6X1430004201

0.1U_0402_16V4Z

1

C68

C74

2

10U_0805_10V4Z

SB_SCLK<4,8,9,19>
SB_SDAT<4,8,9,19>

R52 33_0402_5%

1 2

R61 475_0402_1%

1 2

R85

1 2

10K_0402_5%

CPPE_DOCK#
NC_CLKREQ#

R82

1 2

10K_0402_5%

1

C69

2

0.1U_0402_16V4Z

CLK_STOP

SB_SCLK
SB_SDAT

0.1U_0402_16V4Z

1

1

C71

2

2

U8

43

VDDCPU

14

VDDSRC

21

VDDSRC

35

VDDSRC

32

VDDATI

51

VDD_PCI

48

VDDHTT

56

VDDREF

3

VDD48

1

X1

2

X2

6

CLK_STOP

7

SCLK

8

SDATA

52

REF2

37

IREF

11

CLKREQB#

10

CLKREQA#

5

GND

55

GND

36

GNDSRC

26

GNDSRC

20

GNDSRC

15

GNDSRC

31

GNDATI

49

GNDPCI

46

GNDHTT

42

GNDCPU

ICS951418BGT_TSSOP56

0.1U_0402_16V4Z

1

1

C105

C72

2

0.1U_0402_16V4Z

C104

2

0.1U_0402_16V4Z

VDDA
GNDA

CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1

SRCCLKT7
SRCCLKC7
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3

SRCCLKC3
ATIGCLKT1
ATIGCLKC1
ATIGCLKT0
ATIGCLKC0

SRCCLKT0

SRCCLKC0

PCICLK0

FS0/REF0
FS1/REF1

USB_48MHz

HTTCLK0

1

2

39
38

45
44
41
40

12
13
16
17
18
19
22
23
24
25
27
28
30
29
34
33

50

54
53
9

FS2

4
47

+3V_VDD

C70

0.1U_0402_16V4Z

CPUCLK0H
CPUCLK0L

PCIECLK0_R
PCIECLK0#_R

PCIECLKD#_R

SBSRCCLK_R
SBSRCCLK#_R

NBSRCCLK_R
NBSRCCLK#_R
SBLINKCLK_R
SBLINKCLK#_R

R86 33_0402_5%
R87 33_0402_5%

R78 33_0402_5%SPR@
R79 33_0402_5%SPR@

R80 33_0402_5%
R81 33_0402_5%

R56 33_0402_5%@
R57 33_0402_5%@
R54 33_0402_5%
R55 33_0402_5%

FS0

R528 33_0402_5%

FS1

R49 12_0402_5%SIO@

FS2

R50 33_0402_5%

R84 33_0402_5%

1 2

R76 33_0402_5%

1 2

R64 33_0402_5%

1 2

CHB2012U121_0805

1

1

C61

2

2

10U_0805_10V4Z

R65 15_0402_1%

1 2

R66 15_0402_1%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2

12

L6

12

PCIECLK0
PCIECLK0#

PCIECLK_DOCK
PCIECLK_DOCK#

SBSRCCLK
SBSRCCLK#

NBSRCCLK
NBSRCCLK#
SBLINKCLK
SBLINKCLK#

R53

51.1_0402_1%

+3VS+3V_VDD

CPUCLK0_H <6>
CPUCLK0_L <6>

R96 49.9_0402_1%
R97 49.9_0402_1%

R88 49.9_0402_1%SPR@
R89 49.9_0402_1%SPR@

R90 49.9_0402_1%
R91 49.9_0402_1%

R44 49.9_0402_1%@
R45 49.9_0402_1%@
R42 49.9_0402_1%
R43 49.9_0402_1%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

SB_INT <19>
CLK_14M_SIO <37>

CLK_14M_KBC <38>

CLK_48M_CB <23>
USBCLK_EXT <19>
HTREFCLK <13>

FF DF

R50

12ohm 33ohm

PCIECLK0
PCIECLK0#

PCIECLK_DOCKPCIECLKD_R
PCIECLK_DOCK#

SBSRCCLK
SBSRCCLK#

NBSRCCLK
NBSRCCLK#

SBLINKCLK
SBLINKCLK#

PCIECLK0 <26>
PCIECLK0# <26>

PCIECLK_DOCK <40>
PCIECLK_DOCK# <40>

SBSRCCLK <18>
SBSRCCLK# <18>

NBSRCCLK <13>
NBSRCCLK# <13>

SBLINKCLK <13>
SBLINKCLK# <13>

+3V_CLK

12

R58

FS0
FS1
FS2

4 4

10K_0402_5%

12

R59

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

12

R94

10K_0402_5%

EXT CLK FRE QU EN CY SELECT TABLE(MHZ)

FS2

FS1 CPU

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1
1 1 1

2005/03/01 2006/03/11

E

Compal Secret Data

Deciphered Date

F

SRCCLK

HTT

[2:1]

100.00

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

X/3 X/6

100.00

60.00 30.00

100.00

100.00

100.00

100.00

100.00

Title

Size Document Number Rev

Custom

Date: Sheet

G

USB

PCIFS0

48.00

Hi-ZHi-Z

48.00

48.00

48.00

73.1236.56

33.3366.66

48.00

33.3366.66

48.00

48.00

Clock Generator

LA-2541

COMMENT

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Normal HAMMER operation33.3366.66

0.4

of

15 58Friday, April 15, 2005

H

A

B

C

D

E

F

G

H

1 1

LVDSA2+<13>
LVDSA2-<13>

LVDSAC+<13>
LVDSAC-<13>

LVDSB0+<13>
LVDSB0-<13>

LVDSB1+<13>
LVDSB1-<13>

LVDSB2+<13>
LVDSB2-<13>

LVDSBC+<13>
LVDSBC-<13>

2 2

3 3

LCD Panel Connector

JP8

LVDSA2+
LVDSA2-

LVDSAC+ LVDSA1+
LVDSAC-

LVDSB0+

LVDSB0-

LVDSB1+
LVDSB1-

LVDSB2+
LVDSB2-

LVDSBC+

LVDSBC-

+3VS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

+LCDVDD +5VALW

12

R317

100_0402_1%

13

Q30

D

S

ENVDD

2N7002_SOT23

ENVDD<13>

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

ACES_87216-4012

R48

100K_0402_5%

1 2

2

G

1

O

I

3

2

LCD_ENABLT
DAC_BRIG
EDID_CLK_LCD

EDID_DAT_LCD

Q29
DTC124EK_SC59

G

LVDSA1-

LVDSA0+

LVDSA0-

0.047U_0402_16V4Z

INV_PWM <13>

+INVPWR_B+

1 2

L22
0_0805_5%

1

2

LVDSA1+ <13>

LVDSA1- <13>

LVDSA0+ <13>

LVDSA0- <13>

EDID_CLK_LCD <13>
EDID_DAT_LCD <13>

+INVPWR_B+B+

+LCDVDD

1

C60

2

0.1U_0402_16V4Z

The cap.'s colsely to LCD CONN.

+LCDVDD_A

10U_0805_10V4Z@

1

C46

2

1

C39

2

Q7
SI2301BDS_SOT23

1 3

D

G

2

C43

4.7U_0805_10V4Z

+3VS

S

R34

1 2

0_0805_5%

1

C38

0.01U_0402_16V7K

2

1

C59

4.7U_0805_10V4Z

2

+LCDVDD

R314

10K_0402_5%

LCD_ENABLT

+3VS

12

R517 0_0402_5%@

1 2

D23

2 1

RB751V_SOD323

D22

2 1

RB751V_SOD323

2 1

RB751V_SOD323

D34

ENABLT <13>

PCIRST_LCD# <18>

LID_SW# <19,39>

DAC_BRIG

+3VS

R316

1.8K_0603_1%

R315
1K_0402_1%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

E

Title

Size Document Number Rev

Custom

F

Date: Sheet

LVDS Connector

G

LA-2541

0.4

16 58Friday, April 15 , 2005

of

H

A

B

C

D

E

CRT CONNECTOR

1 1

+CRTVDD

C422

1 2

0.1U_0402_16V4Z

HSYNC<13>

2 2

VSYNC<13>

HSYNC

VSYNC CRT_VSYNC_R

5

A2Y

3

5

A2Y

3

R337 1K_0402_1%

1

U31

P

G

P

G

CRT_HSYNC_R

4

OE#

74AHCT1G125GW_SOT353-5

1

U32

4

OE#

74AHCT1G125GW_SOT353-5

1 2

R331

1 2

20_0402_5%

1 2

R332

20_0402_5%

CRT_HSYNC

CRT_VSYNC

CRT_HSYNC <40>

CRT_VSYNC <40>

CRT_RED<13,40>

CRT_GREEN<13,40>

CRT_BLUE<13,40>

D3
DAN217_SC59@

D4
DAN217_SC59@

1

2

2

3

D5
DAN217_SC59@

1

3

3VDDCCL<13>

3VDDCDA<13>

1

2

3

CRT_RED

CRT_GREEN
CRT_HSYNC

CRT_BLUE
CRT_VSYNC

+3VS

+5VS

+R_CRT_VCC

F1

1.1A_6VDC_FUSE

L33

1 2

FBM-L11-160808-800LMT 0603

L32

1 2

FBM-L11-160808-800LMT 0603

+3VS

R330

4.7K_0402_5%

3VDDCCL

3VDDCDA

4.7K_0402_5%

2N7002_SOT23

D2

2 1

21

RB411D_SOT23

C440

0.1U_0402_16V4Z

CRT_DDCDA

CRT_HSYNC_L

CRT_VSYNC_L

CRT_DDCCL

C441

10P_0402_50V8J

R351

G

2

Q31

S

S

2N7002_SOT23

220P_0402_50V7K

13

D

G

2

+CRTVDD

W=40mils

1

2

C435

10P_0402_50V8J

R344

4.7K_0402_5%

Q32

13

D

C428

R349

4.7K_0402_5%

CRT_DDCCL

CRT_DDCDA

JP9

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

FOX_DZ11A91-L7

+CRTVDD

C448
220P_0402_50V7K

16
17

CRT_DDCCL <40>

CRT_DDCDA <40>

TV-Out Connector

5P_0402_50V8C@

S-Video

C4

C5

5P_0402_50V8C@

SVIDEO@

SVIDEO@

SVIDEO@

R3

0_0603_5%
R2

0_0603_5%
R1

0_0603_5%

3 3

D_LUMA<13,40>

D_CRMA<13,40>

D_COMPS<13,40>

C3

5P_0402_50V8C

@

4 4

D19
DAN217_SC59@

TV_LUMA

TV_CRMA

TV_COMPS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D18
DAN217_SC59@

1

2

2

3

2005/03/01 2006/03/11

1

3

D20
DAN217_SC59@

1

2

Compal Secret Data

3

JP1

1
2
3
4
5
6
7

SUYIN_33007SR-07T1-C

Deciphered Date

+3VS

Title

Size Document Number Rev

Custom

D

Date: Sheet

CRT & TV out Connector

LA-2541

E

0.4

of

17 58Friday, April 15, 2005

PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#

PCI_PIRQG#
PCI_PIRQH#
PCI_PIRQE#
PCI_PIRQF#

R153

1

C250

18P_0402_50V8J

2

R154

1 2

470_0402_5%

5

+1.8VS

SB_32KHOSB_32KHI

4

1

Y5

IN

32.768KHZ_12.5P_Q13MC30610003

OUT

NC3NC

2

1 2

20M_0603_5%

+3VS

12

R400

1.2K_0402_5%

Q10

2

MMBT3904_SOT23

3 1

5

SB_RX0P<12>
SB_RX0N<12>
SB_RX1P<12>
SB_RX1N<12>

FBML10160808121LMT_0603

C272 1U_0603_10V4Z
C279 10U_0805_10V4Z
C270 0.1U_0402_16V4Z

1

C251

18P_0402_50V8J

2

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N

L19

1 2

1 2
1 2
1 2

Layout
change

C266 22U_1206_10V4Z
C589 0.1U_0402_16V4Z

C591 0.1U_0402_16V4Z
C598 0.1U_0402_16V4Z
C600 0.1U_0402_16V4Z
C604 0.1U_0402_16V4Z
C610 0.1U_0402_16V4Z
C606 0.1U_0402_16V4Z
C607 0.1U_0402_16V4Z

R167
R416
R407
R413

+3VS

12

R398

1.2K_0402_5%

FWH_INIT#

Q38

2

MMBT3904_SOT23

3 1

C268 0.01U_0402_16V8K
C269 0.01U_0402_16V8K
C265 0.01U_0402_16V8K
C267 0.01U_0402_16V8K

+1.8VS

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

SBSRCCLK<15>

SBSRCCLK#<15>

1 2
1 2
1 2
1 2

SB_TX0P<12>
SB_TX0N<12>
SB_TX1P<12>
SB_TX1N<12>

+PCIE_VDDR

+PCIE_PVDD

L18 CHB2012U121_0805

1 2

SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

PCI_PIRQE#<23>
PCI_PIRQF#<23>
PCI_PIRQG#<29>
PCI_PIRQH#<27>

LDTSTOP#<4,13>

ALLOW_LDTSTOP<13>

H_PWRGD<6>

BMREQ#<13>

H_RST#<6>

+3VS

RP61

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP62

1 8
2 7
3 6

D D

4 5

8.2K_0804_8P4R_5%

RP58

PCI_REQ#0

1 8

PCI_REQ#1

2 7

PCI_REQ#2

3 6

PCI_REQ#3

4 5

8.2K_0804_8P4R_5%
RP60

PCI_GNT#3

1 8

PCI_GNT#2

2 7

PCI_GNT#1

3 6

PCI_GNT#0

4 5

8.2K_0804_8P4R_5%
RP63

PCI_FRAME#

1 8

PCI_IRDY#

2 7

PCI_TRDY#

3 6

PCI_STOP#

4 5

8.2K_0804_8P4R_5%

C C

RP57

PCI_SERR#

1 8

PCI_PAR

2 7

PCI_DEVSEL#

3 6

LOCK#

4 5

8.2K_0804_8P4R_5%
RP59

FWH_WP#

1 8

FWH_TBL#

2 7

PCI_GNT#4

3 6

PCI_REQ#4

4 5

8.2K_0804_8P4R_5%

PCI_REQ#5

R232

1 2

8.2K_0402_5%

PCI_GNT#5

R233

1 2

8.2K_0402_5%

B B

R155
20M_0603_5%

1 2

A A

H_INIT#

R446 8.2K_0402_5%

1 2

A_RST#

R162
R411

+PCIE_VDDR

FWH_INIT# <39>

4

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N

SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

150_0402_1%

150_0402_1%

R402

1 2

4.12K_0603_1%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

SB_32KHI

SB_32KHO

H_INIT#

ALLOW_LDTSTOP

H_RST#

4

U19A

AH8

A_RST#

L27

PCIE_RCLKP

M27

PCIE_RCLKN

M30

PCIE_TX0P

N30

PCIE_TX0N

K30

PCIE_TX1P

L30

PCIE_TX1N

H30

PCIE_TX2P

J30

PCIE_TX2N

F30

PCIE_TX3P

G30

PCIE_TX3N

M29

PCIE_RX0P

N29

PCIE_RX0N

M28

PCIE_RX1P

N28

PCIE_RX1N

J29

PCIE_RX2P

K29

PCIE_RX2N

J28

PCIE_RX3P

K28

PCIE_RX3N

G27

12

PCIE_CALRP

H27

12

PCIE_CALRN

G28

PCIE_CALI

R30

PCIE_PVDD

F26

PCIE_VDDR_1

R29

PCIE_VDDR_2

G26

PCIE_VDDR_3

P26

PCIE_VDDR_4

K26

PCIE_VDDR_5

L26

PCIE_VDDR_6

P28

PCIE_VDDR_7

N26

PCIE_VDDR_8

P27

PCIE_VDDR_9

H28

PCIE_VSS_1

F29

PCIE_VSS_2

H29

PCIE_VSS_3

H26

PCIE_VSS_4

F27

PCIE_VSS_5

G29

PCIE_VSS_6

L29

PCIE_VSS_7

J26

PCIE_VSS_8

L28

PCIE_VSS_9

J27

PCIE_VSS_10

N27

PCIE_VSS_11

M26

PCIE_VSS_12

K27

PCIE_VSS_13

P29

PCIE_VSS_14

P30

PCIE_VSS_15

AJ8

CPU_STP#/DPSLP#

AK7

PCI_STP#

AG5

INTA#

AH5

INTB#

AJ5

INTC#

AH6

INTD#

AJ6

INTE#/GPIO33

AK6

INTF#/GPIO34

AG7

INTG#/GPIO35

AH7

INTH#/GPIO36

B2

X1

B1

X2

C29

CPU_PG/LDT_PG

A28

INTR/LINT0

C28

NMI/LINT1

B29

INIT#

D29

SMI#

E4

SLP#/LDT_STP#

B30

IGNNE#

F28

A20M#

E28

FERR#

E29

STPCLK#/ALLOW_LDTSTP

D25

LDT_PG/SSMUXSEL/GPIO0

E27

DPRSLPVR

D27

BMREQ#

D28

LDT_RST#

218S4EASA32K SB400 BGA 564P

3

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9

PCICLK_FB

PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#/ROMA10

CBE1#/ROMA1

CBE3#

FRAME#

IRDY#

PAR/ROMA19

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

REQ5#/GPIO13
REQ6#/GPIO31

GNT0#
GNT1#
GNT2#

GNT5#/GPIO14
GNT6#/GPIO32

CLKRUN#

LOCK#

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#
LDRQ1#

SERIRQ

RTCCLK

VBAT

RTC_GND

3

PCI_AD[0..31]

PCICLK0_R

L4
L3
L2
L1
M4
M3
M2
M1
N4
N3
N2

AJ7
W3
Y2
W4
Y3
V1
Y4
V2
W2
AA4
V4
AA3
U1
AA2
U2
AA1
U3
T4
AC1
R2
AD4
R3
AD3
R4
AD2
P2
AE3
P3
AE2
P4
AF2
N1
AF1
V3
AB4
AC2
AE4
T3
AC4
AC3
T2
U4
T1
AB2
AB3
AF4
AF3
AG2
AG3
AH1
AH2
AH3
AJ2
AK2
AJ3
AK3
AG4
AH4
AJ4
AG1
AB1

AG25
AH25
AJ25
AH24
AG24
AH26
AG26

AK27

C2
F3

A2
A1

R410 39_0402_5%

PCICLK1_R
PCICLK2_R
PCICLK3_R
PCICLK4_R
PCICLK5_R

PCICLK9_R
PCICLKFB

PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

2005/03/01 2006/03/11

1 2

R414 39_0402_5%

1 2

R181 39_0402_5%

1 2

R179 39_0402_5%

1 2

R420 39_0402_5%

1 2

R424 39_0402_5%

1 2

R423 39_0402_5%

1 2

A_RST#

PCI_PERR#
PCI_REQ#0

PCI_REQ#4
PCI_REQ#5
FWH_WP#
PCI_GNT#0

PCI_GNT#4
PCI_GNT#5
FWH_TBL#
PM_CLKRUN#
LOCK#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1

SIRQ

RTC_CLK

+RTCVCC

2

C245
1U_0603_10V4Z

1

Compal Secret Data

C605 0.1U_0402_16V4Z@

+3VS

C635 0.1U_0402_16V4Z

12

R460

8.2K_0402_5%

SN74LVC125APWLE_TSSOP14

PCI_CBE#0 <23,27,29>
PCI_CBE#1 <23,27,29>
PCI_CBE#2 <23,27,29>
PCI_CBE#3 <23,27,29>
PCI_FRAME# <23,27,29>
PCI_DEVSEL# <23,27,29>
PCI_IRDY# <23,27,29>
PCI_TRDY# <23,27,29>
PCI_PAR <23,27,29>
PCI_STOP# <23,27,29>
PCI_PERR# <23,27,29>
PCI_SERR# <23,27,29,38>

PCI_REQ#1 <29>
PCI_REQ#2 <23>
PCI_REQ#3 <27>

FWH_WP# <39>
PCI_GNT#1 <29>

PCI_GNT#2 <23>
PCI_GNT#3 <27>

FWH_TBL# <39>
PM_CLKRUN# <23,27,29,37,38>

LPC_AD0 <37,38,39>
LPC_AD1 <37,38,39>
LPC_AD2 <37,38,39>
LPC_AD3 <37,38,39>
LPC_FRAME# <37,38,39>

LPC_DRQ#0 <37>

SIRQ <23,37,38>

RTC_CLK <22>

AUTO_ON# <22>

1

14

P
I2O

G

7

SN74LVC125APWLE_TSSOP14

4

U38B

6

OE#

I5O

Deciphered Date

U38A

OE#

R456

PCI_AD[0..31]<22,23,27,29>

SB400

PCI CLKS

PCI EXPRESS INTERFACE

PCI INTERFACE

CBE2#/ROMWE#

DEVSEL#/ROMA0

TRDY#/ROMOE#

REQ3#/PDMA_REQ0#

REQ4#/PLL_BP33/PDMA_REQ1#

GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#

XTAL

LPC

CPU

RTC_IRQ#/ACPWR_STRAP

RTC

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

CLK_PCI_PCM <23>
CLK_PCI_FWH <39>
CLK_PCI_LAN <22,27>
CLK_PCI_MINI <22,29>
CLK_PCI_EC <22,38>
CLK_PCI_SIO <22,37>
CLK_PCI6 <22>
CLK_PCI7 <22>

1 2

1 2

3

1 2

33_0402_5%

12

R457
47K_0402_5%

CLK_PCI8 <22>

R458 33_0402_5%

1 2

12

R459
47K_0402_5%

NB_PWRGD<13,38,41>

close any door

JOPEN

2

PCI_RST#

KB_RST#<19,38>

NB_RST# <13,26,35,37,38,39>

Layout and BOM change

R518 0_0402_5%

PCIRST#

1 2

12

R5190_0402_5%@

+RTCVCC

W=20mils

J4

1 2

R122

1 2

1K_0402_5%

2

C185

0.1U_0402_16V4Z

1

Title

Size Document Number Rev

Custom

Date: Sheet

1

PCI_RST# <23,26,27,29,32>

PCI_PERR#
PM_CLKRUN#

I12O

R191 8.2K_0402_5%

1 2

R205 10K_0402_5%

1 2

11

RP68

10K_0804_8P4R_5%
RP69

100K_0804_8P4R_5%

PCIRST_LCD# <16>

ZZZ

KB_RST#
SIRQ
LPC_DRQ#1
LPC_DRQ#0

LPC_AD0
LPC_AD2
LPC_AD1
LPC_AD3

13

U38D

OE#

SN74LVC125APWLE_TSSOP14

LA-2541 REV0 M/B

BATT1

CR2025 RTC BATTERY

+BATT1.1

JP16

+-

W=20mils

E&T_7651

SB400-PCI-ECP/PCI/LPC/TRC

LA-2541

1

+3VS

18
27
36
45

18
27
36
45

21

0.4

of

18 58Friday, April 15, 2005

5

4

3

2

1

+3VALW

R397 10K_0402_5%

1 2

R142 4.7K_0402_5%

1 2

R399 4.7K_0402_5%

1 2

R143 4.7K_0402_5%

1 2

R391 10K_0402_5%

D D

+3VS

C C

+3VALW

B B

1 2

R389 10K_0402_5%

1 2

R392 10K_0402_5%

1 2

R156 10K_0402_5%

1 2

R382 10K_0402_5%

1 2

R141 10K_0402_5%

1 2

R390 10K_0402_5%

1 2

R146 10K_0402_5%

1 2

R140 10K_0402_5%

1 2

R144 47K_0402_5%

1 2

R147 2.2K_0402_5%

1 2

R148 2.2K_0402_5%

1 2

R152 10K_0402_5%

1 2

R219 2.2K_0402_5%

1 2

R379 10K_0402_5%4510@

1 2

R381 10K_0402_5%@

1 2

R386 10K_0402_5%

1 2

R380 10K_0402_5%

1 2

R383 10K_0402_5%

1 2

R409 10K_0402_5%

1 2

R377 10K_0402_5%

1 2

R169 10K_0402_5%

1 2

R412 10K_0402_5%

1 2

R403 10K_0402_5%

1 2

R405 8.2K_0402_5%

1 2

R387 10K_0402_5%

1 2

R502 100K_0402_1%

1 2

R149 10K_0402_5%

1 2

NIC_WAKE#
SB_SLP_S3#
SB_SLP_S5#
LID_SW#
BT_OFF
SYS_RESET#
PCI_PME#

OCP#
BT_DETECT#
LAN_LINK#
S3_STATE
USB_OC7#
THERM_SCI#

SB_SCLK
SB_SDAT
RUNSCI_EC#
GATEA20

BRD_ID0
BRD_ID1

AGP_STP#

AGP_BUSY#
SD_DETECT#

AC97_RST#

EXPCRD_RST#

AC97_BITCLK
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
BRD_ID1
PM_RSMRST#
NEWCARD_RST

MUTE#<32>

AC97_BITCLK

BRD_ID1

NEWCARD_RST<26>

XMIT_OFF#<29>

EXPCRD_RST#<40>

AC97_SDOUT<22,30>

AC97_SYNC<30>
AC97_RST#<30>

BOM and layout modify

+3VALW

A A

R554
0_0402_5%

SLP_S3#<26,38,40,42>

1 2

5

5

4

1

P

B

Y

2

A

G

3

U43

TC7SH08FU_SSOP5@

KBC_GPIO12 <38>

4

Y

+3VALW

5

P

B
A

G

3

U12
TC7SH08FU_SSOP5

4

Board ID Settings

ON/OFFBTN#<39>

H_THERMTRIP#<6>
LAN_LINK#<27,28,40>
RUNSCI_EC#<38>

PREP#<40>
PM_RSMRST#<38,46>

AC97_BITCLK<30>
AC97_SDIN0<30>

0

0

NIC_WAKE#<27>

SB_SLP_S5#<46>

SB_PWRGD<38>

MUTE#

SB_SPDIFO<22>

12

1

2

SB_SPKR<30>
SB_SCLK<4,8,9,15>
SB_SDAT<4,8,9,15>

1
2

OCP#<52>

BT_OFF<34>

PCI_PME#<23,29>

GATEA20<38>
KB_RST#<18,38>

SB_INT<15>

R408
10_0402_5%@

C590
10P_0402_25V8K@

SB_SLP_S3#
PM_RSMRST#

0

1

1 2

R384 10K_0402_5%

featureBRD_ID0

full-featured

de-featured

U19B

OCP#
BT_OFF
PCI_PME#
NIC_WAKE#
SB_SLP_S3#
SB_SLP_S5#
ON/OFFBTN#

R160 10K_0402_5%

1 2

R159 10K_0402_5%

1 2

LAN_LINK#
RUNSCI_EC#
S3_STATE
SYS_RESET#
PREP#

PM_RSMRST#

10K_0402_5%

R385

1 2

R378

1 2

BRD_ID1
AGP_STP#
AGP_BUSY#
NEWCARD_RST

SB_SCLK
SB_SDAT
XMIT_OFF#
EXPCRD_RST#
SD_DETECT#

AC97_BITCLK

R164 33_0402_5%

1 2

AC97_SDIN0
AC97_SDIN1
AC97_SDIN2

R173 33_0402_5%

1 2

MUTE#
BRD_ID0

10K_0402_5%7611@

SB_GPIO12

C6

TALERT#/TEMP_ALERT#/GPIO10

D5

BLINK/GPM6#

C4

PCI_PME#/GEVENT4#

D3

RI#/EXTEVNT0#

B4

SLP_S3#

E3

SLP_S5#

B3

PWR_BTN#

C3

PWR_GOOD

D4

SUS_STAT#

F2

TEST1

E2

TEST0

AJ26

GA20IN

AJ27

KBRST#

D6

SMBALERT#/THRMTRIP#/GEVENT2#

C5

LPC_PME#/GEVENT3#

A25

LPC_SMI#/EXTEVNT1#

D8

VOLT_ALERT#/S3_STATE/GEVENT5#

D7

SYS_RESET#/GPM7#

D2

WAKE#/GEVENT8#

D1

RSMRST#

A23

14M_X1/OSC

B23

14M_X2

AK24

SIO_CLK

B25

ROM_CS#/GPIO1

C25

GHI#/GPIO6

C23

VGATE/GPIO7

D24

AGP_STP#/GPIO4

D23

AGP_BUSY#/GPIO5

A27

FANOUT0/GPIO3

C24

SPKR/GPIO2

A26

SCL0/GPOC0#

B26

SDA0/GPOC1#

B27

DDC1_SCL/GPIO9

C26

DDC1_SDA/GPIO8

C27

DDC2_SCL/GPIO11

D26

DDC2_SDA/GPIO12

J2

NC1

K3

NC4

J3

NC3

K2

NC2

G1

AC_BITCLK

G2

AC_SDOUT

H4

AC_SDIN0

G3

AC_SDIN1

G4

AC_SDIN2

H1

AC_SYNC

H3

AC_RST#

H2

SPDIF_OUT

218S4EASA32K SB400 BGA 564P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

3

SB400

ACPI/WAKE UP EVENTS

USB_OC6#/FAN_ALERT#/GEVENT6#

USB_OC7#/CASE_ALERT#/GEVENT7#

CLK / RST

GPIOAC97 (NOT USED)

Compal Secret Data

Deciphered Date

48M_X1/USBCLK

48M_X2

USB_RCOMP

USB_VREFOUT

USB_ATEST1

USB_ATEST0
USB_OC0#/GPM0#
USB_OC1#/GPM1#

USB_OC2#/FANOUT1/GPM2#

USB_OC3#/GPM3#
USB_OC4#/GPM4#
USB_OC5#/GPM5#

USB_HSDP7+
USB_HSDM7-

USB_HSDP6+
USB_HSDM6-

USB_HSDP5+
USB_HSDM5-

AVSS_USB_10
AVSS_USB_11

USB PWR

AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

USB_HSDP4+
USB_HSDM4-

USB_HSDP3+
USB_HSDM3-

USB_HSDP2+
USB_HSDM2-

USB_HSDP1+
USB_HSDM1-

USB_HSDP0+
USB_HSDM0-

AVDDTX_0
AVDDTX_1
AVDDTX_2

AVDDTX_3
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3

AVDDC

AVSSC

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9

USB INTERFACE

A15
B15

R393

C15

USB_VREFOUTPREP#

D16
C16
D15

CPPE_DOCK#

B8

CPPE_NC#

C8

SB_LOW_BAT#

C7

WAKEUP_NC#

B7

THERM_SCI#

B6

BT_DETECT#

A6

LID_SW#

B5

USB_OC7#

A5
A11

B11
A10

B10
A14

B14
A13

B13
A18

B18
A17

B17
A21

B21
A20

B20

C21
C18
D13
D10
D20
D17
C14
C11

A16
B16
A9

A12
A19
A22
B9
B12
B19
B22
C9
C10
C12
C13
C17
C19
C20
C22
D9
D11
D12
D14
D18
D19
D21
D22

2

11.8K_0402_1%
T19 PAD

CPPE_DOCK# <15,40>
CPPE_NC# <26>

WAKEUP_NC# <26>
THERM_SCI# <4>
BT_DETECT# <34>

LID_SW# <16,39>

USBP7+ <34>

USBP7- <34>

USBP6+ <26>

USBP6- <26>

USBP5+ <34>

USBP5- <34>

USBP4+ <34>

USBP4- <34>

USBP3+ <40>

USBP3- <40>
USBP2+ <34>

USBP2- <34>

USBP1+ <34>
USBP1- <34>

USBP0+ <40>

USBP0- <40>

+AVDDTX

+AVDDRX

+AVDDC

Title

Size Document Number Rev

Custom

Date: Sheet

USBCLK_EXT <15>

WAKEUP_NC#

12

R388

10K_0402_5%

SB_LOW_BAT#

+AVDDTX

C592 10U_0805_10V4Z
C594 1U_0603_10V4Z
C572 0.1U_0402_16V4Z

C575 0.1U_0402_16V4Z
C576 0.1U_0402_16V4Z

L38 CHB2012U121_0805

+AVDDRX

C565 10U_0805_10V4Z
C563 1U_0603_10V4Z
C571 0.1U_0402_16V4Z

C573 0.1U_0402_16V4Z
C574 0.1U_0402_16V4Z

+AVDDC

C564 10U_0805_10V4Z
C562 1U_0603_10V4Z
C570 0.1U_0402_16V4Z

D24

2 1

RB751V_SOD323

L41 CHB2012U121_0805

1 2

1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2

L37 FBML10160808121LMT_0603

1 2

1 2
1 2
1 2

SB400 USB/ACPI/AC97/GPIO

LA-2541

1

+3VL+3VALW

12

R490
10K_0402_5%

+3VALW

LOW_BAT# <38>

19 58Friday, April 15 , 2005

12

R145

10K_0402_5%

+3VALW

+3VALW

+3VALW

of

0.4

5

4

3

2

1

PD_D[0..15]<35>
SD_D[0..15]<35>

D D

C C

B B

U19C

AK22

SATA_TX0+

AJ22

SATA_TX0-

AK21

SATA_RX0-

AJ21

SATA_RX0+

AK19

SATA_TX1+

AJ19

SATA_TX1-

AK18

SATA_RX1-

AJ18

SATA_RX1+

AK14

SATA_TX2+

AJ14

SATA_TX2-

AK13

SATA_RX2-

AJ13

SATA_RX2+

AK11

SATA_TX3+

AJ11

SATA_TX3-

AK10

SATA_RX3-

AJ10

SATA_RX3+

AJ15

SATA_CAL

AJ16

SATA_X1

AK16

SATA_X2

AK8

SATA_ACT#

AH15

PLLVDD_SATA

AH16

XTLVDD_SATA

AG10

AVDD_SATA_1

AG14

AVDD_SATA_2

AH12

AVDD_SATA_3

AG12

AVDD_SATA_4

AG18

AVDD_SATA_5

AG21

AVDD_SATA_6

AH18

AVDD_SATA_7

AG20

AVDD_SATA_8

AG9

AVSS_SATA_1

AF10

AVSS_SATA_2

AF11

AVSS_SATA_3

AF12

AVSS_SATA_4

AF13

AVSS_SATA_5

AF14

AVSS_SATA_6

AF15

AVSS_SATA_7

AF16

AVSS_SATA_8

AF17

AVSS_SATA_9

AF18

AVSS_SATA_10

AF19

AVSS_SATA_11

AF20

AVSS_SATA_12

AF21

AVSS_SATA_13

AF22

AVSS_SATA_14

AH9

AVSS_SATA_15

AG11

AVSS_SATA_16

AG15

AVSS_SATA_17

AG17

AVSS_SATA_18

AG19

AVSS_SATA_19

AG22

AVSS_SATA_20

AG23

AVSS_SATA_21

AF9

AVSS_SATA_22

AH17

AVSS_SATA_23

AH23

AVSS_SATA_24

AH13

AVSS_SATA_25

AH20

AVSS_SATA_26

AK9

AVSS_SATA_27

AJ12

AVSS_SATA_28

AK17

AVSS_SATA_29

AK23

AVSS_SATA_30

AH10

AVSS_SATA_31

AJ23

AVSS_SATA_32

218S4EASA32K SB400 BGA 564P

SB400

SERIAL ATA

SERIAL ATA POWER

PIDE_IORDY

PIDE_DACK#

PRIMARY ATA 66/100

SIDE_IORDY

SIDE_DACK#

SIDE_D0/GPIO15
SIDE_D1/GPIO16
SIDE_D2/GPIO17
SIDE_D3/GPIO18
SIDE_D4/GPIO19
SIDE_D5/GPIO20
SIDE_D6/GPIO21
SIDE_D7/GPIO22
SIDE_D8/GPIO23

SIDE_D9/GPIO24
SIDE_D10/GPIO25
SIDE_D11/GPIO26
SIDE_D12/GPIO27

SECONDARY ATA 66/100

SIDE_D13/GPIO28
SIDE_D14/GPIO29
SIDE_D15/GPIO30

AVSS_SATA_33
AVSS_SATA_34
AVSS_SATA_35
AVSS_SATA_36
AVSS_SATA_37
AVSS_SATA_38
AVSS_SATA_39
AVSS_SATA_40
AVSS_SATA_41
AVSS_SATA_42
AVSS_SATA_43
AVSS_SATA_44
AVSS_SATA_45

PIDE_IRQ

PIDE_A0
PIDE_A1
PIDE_A2

PIDE_DRQ
PIDE_IOR#

PIDE_IOW#

PIDE_CS1#
PIDE_CS3#

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8

PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

SIDE_IRQ

SIDE_A0

SIDE_A1

SIDE_A2

SIDE_DRQ
SIDE_IOR#

SIDE_IOW#

SIDE_CS1#
SIDE_CS3#

AD30
AE28
AD27
AC27
AD28
AD29
AE27
AE30
AE29
AC28
AC29

AF29
AF27
AG29
AH30
AH28
AK29
AK28
AH27
AG27
AJ28
AJ29
AH29
AG28
AG30
AF30
AF28

V29
T27
T28
U29
T29
V30
U28
W29
W30
R27
R28

V28
W28
Y30
AA30
Y28
AA28
AB28
AB27
AB29
AA27
Y27
AA29
W27
Y29
V27
U27

AG13
AH22
AK12
AH11
AJ17
AH14
AH19
AJ20
AH21
AJ9
AG16
AK15
AK20

PD_IORDY
PD_IRQA
PD_A0
PD_A1
PD_A2
PD_DACK#
PD_DREQ#
PD_IOR#
PD_IOW#
PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

SD_IORDY
SD_IRQA
SD_SBA0
SD_SBA1
SD_SBA2
SD_DACK#
SD_DREQ#
SD_SIOR#
SD_SIOW#
SD_SCS1#
SD_SCS3#

SD_D0
SD_D1
SD_D2
SD_D3
SD_D4
SD_D5
SD_D6
SD_D7
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15

PD_D[0..15]
SD_D[0..15]

PD_IORDY <35>

PD_IRQA <35>

PD_A0 <35>
PD_A1 <35>
PD_A2 <35>
PD_DACK# <22,35>

PD_DREQ# <35>

PD_IOR# <35>
PD_IOW # <35>
PD_CS#1 <35>
PD_CS#3 <35>

SD_IORDY <35>

SD_IRQA <35>

SD_SBA0 <35>
SD_SBA1 <35>
SD_SBA2 <35>
SD_DACK# <35>

SD_DREQ# <35>

SD_SIOR# <35>
SD_SIOW# <35>
SD_SCS1# <35>
SD_SCS3# <35>

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB400 IDE/SATA

LA-2541

0.4

of

20 58Friday, April 15, 2005

1

R451 1K_0402_5%

+5VS

+3VS

1 2

D10

1U_0603_10V4Z

2 1

RB751V_SOD323

C597 10U_0805_10V4Z

1 2

C587 0.1U_0402_16V4Z

1 2

C586 0.1U_0402_16V4Z

1 2

C585 0.1U_0402_16V4Z

1 2

C583 0.1U_0402_16V4Z

1 2

C582 0.1U_0402_16V4Z

1 2

C581 0.1U_0402_16V4Z

1 2

C584 0.1U_0402_16V4Z

1 2

2

1

2

C629

0.1U_0402_16V4Z

1

C292

C286 22U_1206_10V4Z

1 2

C595 0.1U_0402_16V4Z

1 2

C599 0.1U_0402_16V4Z

1 2

C603 0.1U_0402_16V4Z

1 2

C613 0.1U_0402_16V4Z

1 2

C620 0.1U_0402_16V4Z

1 2

C623 0.1U_0402_16V4Z

1 2

C611 0.1U_0402_16V4Z

1 2

C617 0.1U_0402_16V4Z

1 2

C630 0.1U_0402_16V4Z

1 2

C624 0.1U_0402_16V4Z

1 2

C577 0.1U_0402_16V4Z

1 2

C616 0.1U_0402_16V4Z

1 2

C631 0.1U_0402_16V4Z

1 2

C612 0.1U_0402_16V4Z

1 2

C622 0.1U_0402_16V4Z

1 2

C621 0.1U_0402_16V4Z

1 2

C567 0.1U_0402_16V4Z

1 2

C302 22U_1206_10V4Z

1 2

C289 22U_1206_10V4Z

1 2

C614 0.1U_0402_16V4Z

1 2

C609 0.1U_0402_16V4Z

1 2

C615 0.1U_0402_16V4Z

1 2

C628 0.1U_0402_16V4Z

1 2

C627 0.1U_0402_16V4Z

1 2

C618 0.1U_0402_16V4Z

1 2

C619 0.1U_0402_16V4Z

1 2

C608 0.1U_0402_16V4Z

1 2

C625 0.1U_0402_16V4Z

1 2

C601 0.1U_0402_16V4Z

1 2

C626 0.1U_0402_16V4Z

1 2

C602 0.1U_0402_16V4Z

1 2

C244 22U_1206_10V4Z

1 2

C566 0.1U_0402_16V4Z

1 2

C568 0.1U_0402_16V4Z

1 2

C578 0.1U_0402_16V4Z

1 2

C579 0.1U_0402_16V4Z

1 2

C580 0.1U_0402_16V4Z

1 2

+1.8VALW

+V5_VREF

FBM-L11-321611-260-LMT_1206

C559 10U_0805_10V4Z

1 2

C561 1U_0603_10V4Z

1 2

C569 0.1U_0402_16V4Z

1 2

+3VS

+1.8VS

+3VALW

C252 0.1U_0402_16V4Z

+1.2V_HT

12

+AVDD_CK

+1.8VS

12

L39

U19D

A30

VDDQ_1

AA26
AC30
AD26

AE26

AF24
AF25

AK26
AK30

M12
M13
M18
M19

W12
W13
W18
W19

AG6

D30
E24
E25

J5
K1
K5

N5

P5
R1
U5

U26
U30

V5

V26

Y1

Y26
AA5

AB5
AD5
AE1

AE5
AF6

AF7

AK1
AK4

N12
N13
N18
N19
V12
V13
V18
V19

A3

A7

E6

E7

E1

F5

E9

E10
E20
E21

E13
E14
E16
E17

C30

A24
B24

A4

A8

A29
B28

C1

E5

E8

E11
E12
E15
E18

SB400

VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6

S5_1.8V_1
S5_1.8V_2
S5_1.8V_3
S5_1.8V_4

USB_PHY_1.8V_1
USB_PHY_1.8V_2
USB_PHY_1.8V_3
USB_PHY_1.8V_4

CPU_PWR
V5_VREF
AVDDCK

AVSSCK
VSS_1

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11

218S4EASA32K SB400 BGA 564P

E19

VSS_12

E22

VSS_13

E23

VSS_14

E26

VSS_15

E30

VSS_16

F1

VSS_17

F4

VSS_18

G5

VSS_19

H5

VSS_20

J1

VSS_21

J4

VSS_22

K4

VSS_23

L5

VSS_24

M5

VSS_25

P1

VSS_26

R5

VSS_27

R26

VSS_28

T5

VSS_29

T26

VSS_30

T30

VSS_31

W1

VSS_32

W5

VSS_33

W26

VSS_34

Y5

VSS_35

AB26

VSS_36

AB30

VSS_37

AC5

VSS_38

AC26

VSS_39

AD1

VSS_40

AF5

VSS_41

AF8

VSS_42

AF23

VSS_43

AF26

VSS_44

AG8

VSS_45

AJ1

VSS_46

AJ24

VSS_47

AJ30

VSS_48

AK5

VSS_49

AK25

VSS_50

M14

VSS_51

M15

VSS_52

M16

VSS_53

POWER

VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

M17
N14
N15
N16
N17
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
W14
W15
W16
W17

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB400 Power/GND

LA-2541

of

21 58Friday, April 15, 2005

0.4

5

+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS

12

R406
10K_0402_5%

AUTO_ON#<18>

AC97_SDOUT<19,30>

RTC_CLK<18>

D D

SB_SPDIFO<19>

CLK_PCI_MINI<18,29>

CLK_PCI_EC<18,38>
CLK_PCI_SIO<18,37>

CLK_PCI6<18>
CLK_PCI7<18>
CLK_PCI8<18>

CLK_PCI_LAN<18,27>

12

R404
0_0402_5%@

4

12

12

R168
10K_0402_5%@

R163
10K_0402_5%

12

R396
10K_0402_5%

12

12

R170
10K_0402_5%@

R171
10K_0402_5%

12

12

R172
10K_0402_5%

R178
10K_0402_5%@

12

R418
10K_0402_5%@

12

R417
10K_0402_5%

3

12

R421
10K_0402_5%

12

R425
10K_0402_5%@

12

R428
10K_0402_5%

12

R427
10K_0402_5%@

12

R184
10K_0402_5%@

12

R185
10K_0402_5%

12

R422
10K_0402_5%

12

R426
10K_0402_5%@

+3VS

12

12

R183

10K_0402_5%@

R180
10K_0402_5%

2

1

NB STRAPS(internal
pulled up)

LOAD_ROM#<13>

SPMEM_EN#<13>

12

R341
3K_0402_5%@

12

R342

3K_0402_5%@

REQUIRED STRAPS

ACPWRON

AUTO_ON#

MANUAL

PULL

PWR ON

HIGH

PULL
LOW

DEFAULT

AUTO
PWR
ON

C C

AC97_SDOUT SB_SPDIFO

USE

DEBUG

STRAPS

IGNORE

DEBUG

STRAPS

DEFAULT

RTC_CLK

INTERNAL
RTC

DEFAULT

EXTERNAL
RTC (NOT
SUPPORTED
W/ IT8712 )

SIO 24MHz

SIO 48MHz

DEFAULT

CLK_PCI_LAN

48MHz XTAL
MODE

48MHz OSC /
Clock buffer
MODE

DEFAULT

CLK_PCI_MINI

USB PHY
PWRDOWN
DISABLE

DEFAULT

USB PHY
PWRDOWN
ENABLE

CLK_PCI_EC

INTERNAL
48MHz

DEFAULT

EXTERNAL
48MHz

CLK_PCI_SIO

14MHz OSC
MODE

DEFAULT

14MHz XTAL
MODE

CLK_PCI6

CPU I/F = K8

DEFAULT

CPU I/F = P4

CLK_PCI7

PCI_CLK8

ROM TYPE
H,H = PCI ROM

H,L = PMC LPC ROM

L,H = NORMAL LPC ROM

L,L = FWH ROM

DEFAULT

LOAD_ROM# :LO AD R OM S TRA P E NABLE strap

High, LOAD ROM STRAP DISABLE
Low, LOAD RO M STRAP ENABLE

SPMEM_EN#:SIDE PORT MEMORY ENABLE strap

High, SIDE PORT MEMORY DISABLE
Low, SIDE PORT MEMORY ENABLE

+3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS

12

PD_DACK#<20,35>
PCI_AD31<18,23,27,29>
PCI_AD30<18,23,27,29>
PCI_AD29<18,23,27,29>
PCI_AD28<18,23,27,29>
PCI_AD27<18,23,27,29>
PCI_AD26<18,23,27,29>

B B

PCI_AD25<18,23,27,29>
PCI_AD24<18,23,27,29>
PCI_AD23<18,23,27,29>

12

@

R198
10K_0402_5%

R202
1K_0402_5%

12

12

R203
10K_0402_5%

R204
10K_0402_5%@

12

R187
10K_0402_5%

12

R188
10K_0402_5%@

12

12

R199
10K_0402_5%

R200
10K_0402_5%@

12

12

R432
10K_0402_5%

R429
10K_0402_5%@

12

R442
10K_0402_5%@

12

R440
10K_0402_5%

12

12

R434
10K_0402_5%@

R433
10K_0402_5%

12

R437
10K_0402_5%@

12

R439
10K_0402_5%

12

12

R431
10K_0402_5%@

R430
10K_0402_5%

12

R194
10K_0402_5%

12

R195
10K_0402_5%@

DEBUG STRAPS

PD_DACK#

PULL
HIGH

PULL

A A

LOW

USE
LONG
RESET

DEFAULT

USE
SHORT
RESET

PCI_AD31

PLL CHARGE
PUMP CTRL
BIT 1 HI

DEFAULT

PLL CHARGE
PUMP CTRL
BIT 1 LO

PCI_AD30

PLL CHARGE
PUMP CTRL
BIT 0 HI

DEFAULT

PLL CHARGE
PUMP CTRL
BIT 0 LO

PCI_AD29

PLL VCO
CTRL BIT
1 HI

DEFAULT

PLL VCO
CTRL BIT
1 LO

PCI_AD28

PLL VCO
CTRL BIT
0 HI

DEFAULT

PLL VCO
CTRL BIT
0 LO

PCI_AD27 PCI_AD26

BYPASS
PCI PLL

USE PCI
PLL

DEFAULT

BYPASS
ACPI
BCLK

USE
ACPI
BCLK

DEFAULT

PCI_AD25 PCI_AD24

BYPASS IDE
PLL

USE IDE
PLL

DEFAULT

USE EEPROM
PCIE STRAPS

USE DEFAULT
PCIE STRAPS

DEFAULT

PCI_AD23

USE USB
PLL

BY PASS
USB PLL

DEFAULT

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Hardware Strap

LA-2541

0.4

of

22 58Friday, April 15, 2005

1

5

4

3

2

1

VCC

4A
4B

3A
3B

+3VS

14

MC_PWRON#

13

CB_SM_RB#

12
11

10
9
8

2

C324

1U_0603_10V4Z

1

SDWP#_SMCE#

12

R244

56.2_0603_1%

12

R242

56.2_0603_1%

12

R239

5.1K_0603_1%

SM_RB#

CardBus Co ntroller TI7611

LA-2541

2

C325

1U_0603_10V4Z

1

1

SM_RB# <25>

SDWP#_SMCE# <25>

8

4

4

3

3

2

GND15GND26GND37GND4

2

1

1

JP10
SUYIN_020204FR004S506ZL

of

23 58Friday, April 15, 2005

0.4

0.01U_0402_16V7K

0.1U_0402_16V4Z

+3VS_PLL

1U_0603_10V4Z

2

C319

D D

+3VS

R236

1 2

4.7K_0402_5%
R250

1 2

4.7K_0402_5%
R213

1 2

10K_0402_5%7611@

R251

1 2

10K_0402_5%

C C

BOM change

MSCLK_SDCLK_SMELWP#<25>
CB_MSBS_SDCMD_SMWE#<25>

MSD3_SDD3_SMD3<25>
MSD2_SDD2_SMD2<25>
MSD1_SDD1_SMD1<25>
MSD0_SDD0_SMD0<25>

CB_SDCLK_SMRE#

CB_SDWP#_SMCE#<25>

0.01U_0402_16V7K

CPS

PHY_TEST

MC_PWRON#

CNA

MC_PWRON#<25>

SD_CD#<25>
MS_CD#<25>
SM_CD#<25>

R224 0_0402_5%7611@

1 2

R536 0_0402_5%7611@

1 2

R537 0_0402_5%7611@

1 2

R538 0_0402_5%7611@

1 2

R539 0_0402_5%7611@

1 2

R540 0_0402_5%7611@

1 2

R209 0_0402_5%7611@

1 2

SDCMD_SMALE<25>

SDD0_SMD4<25>
SDD1_SMD5<25>
SDD2_SMD6<25>
SDD3_SMD7<25>

SMCLE<25>

1

R252 6.34K_0402_1%

1 2

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

XTPBIAS1

XTPB1+
XTPB1-

PHY_TEST

CPS
CNA

X_OUT
X_IN

CB_SM_RB#

TI requires to pull high this pin

B B

CLK_48M_CB<15>

CLK_48M_CB

12

R93

A A

10_0402_5%@

1

C112
10P_0402_25V8K@

2

+5VS

1 2

R208 10K_0402_5%7611@

VCCD1#<26>

R240 220_0402_5%

1 2
1 2

1 2

1 2

4510@

0_0402_5%

4510@

R247 220_0402_5%

+VDDPLL

C332 0.1U_0402_16V4Z4510@

CLK_48M_CB

R532 0_0402_5%7611@

R533

1M_0402_5%@

C342 10P_0402_50V8J

10U_0805_10V4Z

1

C317

2

U23B

U18

R0

U19

R1

U15

TPBIAS0

V15

TPA0+

W15

TPA0-

V14

TPB0+

W14

TPB0-

U17

TPBIAS1

V18

TPA1+

W18

TPA1-

V16

TPB1+

W16

TPB1-

R17

PHY_TEST_MA

M11

CPS

P15

CNA

R19

XO

R18

XI

R12

PC0(TEST1)

U13

PC1(TEST2)

V13

PC2(TEST3)

F1

MC_PWR_CTRL_0

F2

MC_PWR_CTRL_1

E3

SD_CD#

F5

MS_CD#

F6

SM_CD#

G5

MS_CLK/SD_CLK/SM_EL_WP#

F3

MS_BS/SD_CMD/SM_WE#

H5

MS_DATA3/SD_DAT3/SM_D3

G3

MS_DATA2/SD_DAT2/SM_D2

G2

MS_DATA1/SD_DAT1/SM_D1

G1

MS_SDIO(DATA0)/SD_DAT0/SM_D0

J5

SD_CLK/SM_RE#/SC_GPIO1

J3

SD_CMD/SM_ALE/SC_GPIO2

H3

SD_DAT0/SM_D4/SC_GPIO6

J6

SD_DAT1/SM_D5/SC_GPIO5

J1

SD_DAT2/SM_D6/SC_GPIO4

J2

SD_DAT3/SM_D7/SC_GPIO3

H7

SD_WP/SM_CE#

J7

SM_CLE/SC_GPIO0

K1

SM_R#/SC_RFU

K2

SM_PHYS_WP#/SC_FCB

L2

SC_CD#

K5

SC_CLK

K3

SC_RST

K7

SC_VCC_5V

L1

SC_DATA

L3

SC_OC#

L5

SC_PWR_CTRL

P12

TEST0

W17

NC

T19

RSVD

M1

CLK_48

1 2

C343

10P_0402_50V8J

R253

+3VS

1

C303

2

R13

R14

V17

AVDD

AVDD

AVDD

AGND

AGND

N12

U14

X_IN

12

X2

X_OUT

24.576MHZ_16P_XSL024576FG1H

C333 0.1U_0402_16V4Z

C297

1

1

+VDDPLL

2

2

M19

H1

T18

V19

VDPLL_33

VDPLL_15

W10

W3

VCCP

VCCP

VR_PORT

VR_PORT

PCI7621/7611/7421/7411

VSPLL

VSPLL

AGND

U16

SNC1R21GHK_PBGA288

T17

P14

C331

+VDDPLL

1 2

put C331 as close to
controller as possible

+3VS

FRAME#

DEVSEL#

PCIRST#

RI_OUT#/PME#

SUSPEND#

SPKROUT

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

0.1U_0402_16V4Z7611@

C326

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR

TRDY#

IRDY#

STOP#

IDSEL
PERR#
SERR#

REQ#

GNT#

PCICLK

GRST#

SCL
SDA

VR_EN#

Layout change

+3VS_PLL

1

2

1

1U_0603_10V4Z

U2
V1
V2
U3
W2
V3
U4
V4
V5
U5
R6
P6
W6
V6
U6
R7
V9
U9
R9
N9
V10
U10
R10
N10
V11
U11
R11
W12
V12
U12
N11
W13

W4
W7
W9
W11

P9
V7
R8
U7
W8
N8
W5
V8
U8
U1
T2

P5
R3
T1
T3

R2
L7
N3

M5
P1
P2
P3
N5
R1

M3
M2

H2

10K_0402_5%

1

C334

C330
10U_0805_10V4Z

2

2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2

PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

R235

1 2

100_0402_5%

CB_PME#

R226

1 2

4.7K_0402_5%

PCM_SPK#

R228

1 2

CARD_LED

4.7K_0402_5%

R215 220_0402_5%

1 2

R229

1 2

220_0402_5%

VR_EN#

12

R231

when VR_EN# is low, internal
regulator is actived

CARD_LED<25>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

R254

0_0603_5%

PCI_CBE#[0..3] <18,27,29>

PCI_AD[0..31] <18,22,27,29>

+3VS

R225

10K_0402_5%

CB_PME#PCI_AD1

PCI_PAR <18,27,29>
PCI_FRAME# <18,27,29>
PCI_TRDY# <18,27,29>
PCI_IRDY# <18,27,29>
PCI_STOP# <18,27,29>
PCI_DEVSEL# <18,27,29>

PCI_AD20

PCI_PERR# <18,27,29>
PCI_SERR# <18,27,29,38>
PCI_REQ#2 <18>
PCI_GNT#2 <18>

CLK_PCI_PCM <18>
PCI_RST# <18,26,27,29,32>

+3VS
PCM_SPK# <30>
PCI_PIRQE# <18>

PCI_PIRQF# <18>
SIRQ <18,37,38>

+3VS
PM_CLKRUN# <18,27,29,37,38>

If EEPROM is unused, SCL/SDA must be
pulled down to GND with 220ohm resistor.

G

2

1 2

S

Q18
2N7002_SOT23

7611@

12-21SYGC/S530-E1/TR8_GRN

12

R556

10K_0402_5%@

1 2

2005/03/01 2006/03/11

3

D

R495

13

CLK_PCI_PCM

1K_0402_5%7611@

MSBS_SDCMD_SMWE#<25>

PCI_PME# <19,29>

D17

2

Compal Secret Data

SDCLK_SMRE#<25>

12

R227
10_0402_5%@

1

C291
10P_0402_25V8K@

2

+3VS

213

CARDREADER LED

GREEN

R496

7611@

220_0402_5%

1 2

Q45

7611@

MMBT3904_SOT23

3 1

Deciphered Date

MC_PWRON#

CB_MSBS_SDCMD_SMWE#
MSBS_SDCMD_SMWE#

CB_SDCLK_SMRE#

SDCLK_SMRE# CB_SDWP#_SMCE#

PCM_SPK#

12

CLOSE TO CHIP

U41

1

1OE#

2

1A

3

1B

4

2OE#

5

2A

6

2B

7

GND

SN74CBTLV3125PWR_TSSOP14

7611@

Layout change

R531
33K_0402_5%@

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

C314

220P_0603_50V8J

4OE#

3OE#

12

R245

56.2_0603_1%

12

R241

56.2_0603_1%

1

2

CLOSE TO CHIP

XTPBIAS1

XTPB1+
XTPB1-

R243

1K_0402_5%

2

R246
1K_0402_5%

1 2

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

1

S1_D[0:15]

D D

C C

B B

S1_A16

S1_CD1#

S1_A[0..25]

R237

1 2

33_0402_5%

S1_D[0..15] <26>

S1_A[0..25] <26>

S1_IOWR#<26>
S1_IORD#<26>
S1_OE#<26>

S1_CE2#<26>

S1_REG#<26>

S1_CE1#<26>

S1_WAIT#<26>
S1_INPACK#<26>

S1_WE#<26>
S1_BVD1<26>
S1_WP<26>

S1_CLK

S1_RDY#<26>

S1_RST<26>
S1_BVD2<26>
S1_CD1#<26>

S1_CD2#<26>
S1_VS1<26>
S1_VS2<26>

S1_CD2#

C322

10P_0402_50V8J

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP

S1_RDY#
S1_RST
S1_BVD2
S1_CD1#

S1_CD2#
S1_VS1
S1_VS2

S1_D14
S1_D2
S1_A18

C321

10P_0402_50V8J

U23A

D1

A_CAD31/A_D10

C1

A_CAD30/A_D9

D3

A_CAD29/A_D1

C2

A_CAD28/A_D8

B1

A_CAD27/A_D0

B4

A_CAD26/A_A0

A4

A_CAD25/A_A1

E6

A_CAD24/A_A2

B5

A_CAD23/A_A3

C6

A_CAD22/A_A4

B6

A_CAD21/A_A5

G9

A_CAD20/A_A6

C7

A_CAD19/A_A25

B7

A_CAD18/A_A7

A7

A_CAD17/A_A24

A10

A_CAD16/A_A17

E11

A_CAD15/A_IOWR#

G11

A_CAD14/A_A9

C11

A_CAD13/A_IORD#

B11

A_CAD12/A_A11

C12

A_CAD11/A_OE#

B12

A_CAD10/A_CE2#

A12

A_CAD9/A_A10

E12

A_CAD8/A_D15

C13

A_CAD7/A_D7

F12

A_CAD6/A_D13

A13

A_CAD5/A_D6

C14

A_CAD4/A_D12

E13

A_CAD3/A_D5

A14

A_CAD2/A_D11

B14

A_CAD1/A_D4

E14

A_CAD0/A_D3

C5

A_CC/BE3#/A_REG#

F9

A_CC/BE2#/A_A12

B10

A_CC/BE1#/A_A8

G12

A_CC/BE0#/A_CE1#

G10

A_CPAR/A_A13

C8

A_CFRAME#/A_A23

A8

A_CTRDY#/A_A22

B8

A_CIRDY#/A_A15

A9

A_CSTOP#/A_A20

C9

A_CDEVSEL#/A_A21

E10

A_CBLOCK#/A_A19

F10

A_CPERR#/A_A14

B3

A_CSERR#/A_WAIT#

E7

A_CREQ#/A_INPACK#

B9

A_CGNT#/A_WE#

B2

A_CSTSCHG/A_BVD1(STSCHG/RI)

C3

A_CCLKRUN#/A_WP(IOIS16)

E9

A_CCLK/A_A16

C4

A_CINT#/A_READY(IREQ)

A6

A_CRST#/A_RESET

A2

A_CAUDIO/A_BVD2(SPKR#)

C15

A_CCD1#/A_CD1#

E5

A_CCD2#/A_CD2#

A3

A_CVS1/A_VS1#

E8

A_CVS2/A_VS2#

B13

A_CRSVD/A_D14

D2

A_CRSVD/A_D2

C10

A_CRSVD/A_A18

E2

A_USB_EN

E1

B_USB_EN

+3VS+S1_VCC

A11

H10

H11

H12

J12

VCCH8VCCH9VCC

VCC

VCC

VCCJ8VCCM7VCC

VCCAA5VCCA

VCCM9VCC

PCI7621/7611/7421/7411

GNDG7GNDG8GND

GND

GNDJ9GND

GND

GNDK9GND

GND

GNDL8GNDL9GND

J10

J11

K10

K11

H13

G13

D19

M10

L10

K19

M12

K12

N7

VCC

VCCK8VCC

VCC

VCCB

VCCB

B_CAD15/B_IOWR#

B_CAD13/B_IORD#

B_CC/BE3#/B_REG#

B_CC/BE0#/B_CE1#

B_CFRAME#/B_A23

B_CDEVSEL#/B_A21

B_CBLOCK#/B_A19

B_CSERR#/B_WAIT#

B_CREQ#/B_INPACK#

B_CSTSCHG/B_BVD1(STSCHG/RI)

B_CCLKRUN#/B_WP(IOIS16)

B_CINT#/B_READY(IREQ)

B_CRST#/B_RESET

B_CAUDIO/B_BVD2(SPKR#)

GND

GND

GND

SNC1R21GHK_PBGA288

M8

L11

L12

B_CAD31/B_D10

B_CAD30/B_D9
B_CAD29/B_D1
B_CAD28/B_D8
B_CAD27/B_D0
B_CAD26/B_A0
B_CAD25/B_A1
B_CAD24/B_A2
B_CAD23/B_A3
B_CAD22/B_A4
B_CAD21/B_A5
B_CAD20/B_A6

B_CAD19/B_A25

B_CAD18/B_A7
B_CAD17/B_A24
B_CAD16/B_A17

B_CAD14/B_A9
B_CAD12/B_A11

B_CAD11/B_OE#

B_CAD10/B_CE2#

B_CAD9/B_A10

B_CAD8B_D15

B_CAD7/B_D7

B_CAD6/B_D13

B_CAD5/B_D6

B_CAD4/B_D12

B_CAD3/B_D5

B_CAD2/B_D11

B_CAD1/B_D4
B_CAD0/B_D3

B_CC/BE2#/B_A12

B_CC/BE1#/B_A8

B_CPAR/B_A13

B_CTRDY#/B_A22

B_CIRDY#/B_A15

B_CSTOP#/B_A20

B_CPERR#/B_A14

B_CGNT#/B_WE#

B_CCLK/B_A16

B_CCD1#/B_CD1#
B_CCD2#/B_CD2#

B_CVS1/B_VS1#
B_CVS2/B_VS2#

B_CRSVD/B_D14

B_CRSVD/B_D2

B_CRSVD/B_A18

DATA
CLOCK
LATCH

+3VS

2

C316

B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19

F15
G18
K14
M18

K13
G19
H17
J13
J17
H19
J19
J18
B18
E18
J15

R534

F14
A18

1 2

0_0402_5%4510@

H18
B19

F17
C17
N13

B17
C18
F19

N17
A15
K15

TPS_DATA

N1

TPS_CLK

L6

TPS_LATCH

N2

TPS_DATA <26>

TPS_CLK <26,38>

TPS_LATCH <26>

1U_0603_10V4Z

1

+3VS

2

C296
1U_0603_10V4Z

1

+S1_VCC

1

C313

0.1U_0402_16V4Z

2

1

C323

0.1U_0402_16V4Z

2

1

C305

0.1U_0402_16V4Z

2

1

C307

0.1U_0402_16V4Z

2

1

C311

0.1U_0402_16V4Z

2

1

C328

0.01U_0402_16V7K

2

1

C327

0.01U_0402_16V7K

2

1

C329

0.1U_0402_16V4Z

2

1

C304

0.01U_0402_16V7K

2

1

C308

0.01U_0402_16V7K

2

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

CardBus con troller TI 7611

LA-2541

24 58Friday, April 15, 2005

1

0.4

of

5

4

3

2

1

+3VS

1

C690

7611@

0.1U_0402_16V4Z

D D

C C

B B

2

R553

10K_0402_1%@

+3VS

12

MC_PWRON#

U42

5

IN

3

SET

AATI4610AIGV-T1_SOT23-5@

Q55

SI2301BDS_SOT237611@

S

G

2

MC_PWRON#<23>

CARD_LED<23>

OUT
ON#

GND

D

13

7611@

10U_0805_10V4Z

SD_CD#<23>

MS_CD#<23>

+3VS

+SD_MS_VCC

1

MC_PWRON#

4
2

+SD_MS_VCC

1

C688

2

MC_PWRON#

R206

1 2
7611@

100K_0402_1%

7611@

RB751V_SOD323

12

R545

7611@

100K_0603_5%

100K_0402_5%

D41

21

RB751V_SOD3237611@

D42

21

RB751V_SOD3237611@

13

D

2

G

S

21

D8

7611@

Q17

Layout and BOM change

12

12

R547

13

D

2

G

S

2N7002_SOT237611@

21

D9

7611@

RB751V_SOD323

SD_CD#
SM_CD#

R546

7611@

100K_0402_5%

SM_CTRL#

7611@

2N7002_SOT23
Q56

SD_CD# <23>
SM_CD# <23>

SI2301BDS_SOT237611@

S

G

Q50

D

2

10U_0805_10V4Z

SM_RB#<23>

MSBS_SDCMD_SMWE#<23>

SDCLK_SMRE#<23>

SDWP#_SMCE#<23>

+SM_VCC

13

12

1

2

+SM_VCC

R221

7611@

100K_0603_5%

MSD0_SDD0_SMD0<23>
MSD1_SDD1_SMD1<23>
MSD2_SDD2_SMD2<23>
MSD3_SDD3_SMD3<23>

C299

7611@

0.1U_0402_16V4Z

SDD0_SMD4<23>
SDD1_SMD5<23>
SDD2_SMD6<23>
SDD3_SMD7<23>

1 2

SDCMD_SMALE<23>

1

2

R214

0_0402_5%7611@

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

MSCLK_SDCLK_SMELWP#
SM_PHYS_WP#
MSBS_SDCMD_SMWE#
SDCMD_SMALE

SM_CD#
SM_RB#

SDCLK_SMRE#
SDWP#_SMCE#

SMCLE<23>

Layout change

JP25

34

SM-D0 / XD-D0

33

SM-D1 / XD-D1

32

SM-D2 / XD-D2

31

SM-D3 / XD-D3

21

SM-D4 / XD-D4

22

SM-D5 / XD-D5

23

SM-D6 / XD-D6

24

SM-D7 / XD-D7

35

SM_WP-IN / XD_WP-IN

43

SM-WP-SW

36

#SM_-WE / XD_-WE

37

#SM-ALE / XD-ALE

25

SM-LVD

3

SM-CD-SW

29

SM_-VCC / XD_-VCC

26

#SM_R/-B / XD_R/-B

27

#SM_-RE / XD_-RE

28

#SM_-CE / XD_-CE

30

#SM_-CD

2

SM-CD-COM

38

SM-CLE / XD-CLE

45

45

46

46

7611_CONN@

5 IN 1 CONN

TAITW_R007-010-N3

SD-DAT3
SD-DAT2
SD-DAT1
SD-DAT0

SD-WP-SW

SD-CMD
SD_CLK
SD-VCC

SD-CD-SW

SD-CD-COM

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-SCLK

MS-INS

MS-BS

MS-VCC
XD-VCC

XD-CD

GND
GND

N/C

MSCLK_SDCLK_SMELWP#<23>

7611@

C298

SM_RB#

MSBS_SDCMD_SMWE#

MSD3_SDD3_SMD3

11

MSD2_SDD2_SMD2

12

MSD1_SDD1_SMD1

6

MSD0_SDD0_SMD0

7

CB_SDWP#_SMCE#

5

CB_MSBS_SDCMD_SMWE#

10

MSCLK_SDCLK_SMELWP#

8
9
4
42
41

15
14
16
18
19
17
13
20

40
39
1
44

+SD_MS_VCC

SD_CD#

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
CB_MSBS_SDCMD_SMWE#

SM_CD#

SDCLK_SMRE#

SDWP#_SMCE#

+SD_MS_VCC
+SM_VCC

Layout change

SM_CD# MS_CD# SD_CD#

1

C692

0.1U_0402_16V4Z@

2

1

C693

0.1U_0402_16V4Z@

2

1

C694

0.1U_0402_16V4Z@

2

+SM_VCC

R535

1 2

10K_0402_5%7611@

R525

1 2

10K_0402_5%7611@

R526

1 2

10K_0402_5%7611@

R527

1 2

10K_0402_5%7611@

CB_SDWP#_SMCE# <23>
CB_MSBS_SDCMD_SMWE# <23>

Close to card reader socket

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Layout and BOM change

2

Title

Size Document Number Rev

Custom

Date: Sheet

Card reader socket

LA-2541

1

of

25 58Friday, April 15, 2005

0.4

A

B

C

D

E

CardBus Power Switch

+5VS

+3VS

1 2

CPUSB#
CPPE_NC#

100K_0402_5%7611@

U20

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

NC0

9

AVCC

10

AVCC

17

NC1

18

NC2

SNP1X21DBR_SSOP247611@

U16

9

12V

5

5V

6

5V

3

3.3V

4

3.3V

7

U22

5

3.3Vin1

6

3.3Vin2

21

3.3Vaux_in

18

1.5Vin1

19

1.5Vin2

14

CPUSB#

15

CPPE#

4

STBY#

3

SHDN#

2

SYSRST#

GND

11

GND

SHDN

16

NC11NC210NC312NC413NC5

NEWCARD_RST<19>

20

12V

7

12V

14

NC3

13

3.3V

24

NC4

2

5V

1

5V

11

GND

23

NC5

22

NC6

16

NC7

6

NC8

13

VCC

12

VCC

11

VCC

10

VPP

1

VCCD0

2

VCCD1

15

VPPD0

14

VPPD1

8

OC

SNP1X11AIDBR_SSOP164510@

3.3Vout1

3.3Vout2

Aux_out

1.5Vout1

1.5Vout2

OC#

RCLKEN
PERST#

7611@

24

TPS2231PWPR_PWP24

B

+S1_VCC

+S1_VPP

TPS_CLK
TPS_LATCH

TPS_DATA

7
8

20

16
17

23
22

9

+3VS

+5VS

PERST#

C259 0.1U_0402_16V4Z

1 2
1 2

C258

4.7U_0805_10V4Z

C275 0.1U_0402_16V4Z

1 2
1 2

C278

4.7U_0805_10V4Z

VCCD1# <23>

+3VS_PEC

C310

1 2

+3V_PEC

C294

1 2

+1.5VS_PEC

C295

1 2

2

G

13

D

7611@

2

2N7002_SOT23

G

Q51

S

1U_0603_10V4Z7611@

1U_0603_10V4Z7611@

NC_CLKREQ#

13

D

S

S1_CE1#<24>
S1_OE#<24>

S1_WE#<24>
S1_RDY#<24>

+S1_VCC

+S1_VPP

S1_WP<24>

S1_CD1#<24>

S1_CE2#<24>

S1_VS1<24>
S1_IORD#<24>
S1_IOWR#<24>

+S1_VCC

+S1_VPP

S1_VS2<24>
S1_RST<24>

S1_WAIT#<24>

S1_INPACK#<24>
S1_REG#<24>

S1_BVD2<24>

S1_BVD1<24>

S1_CD2#<24>

1U_0603_10V4Z7611@

2N7002_SOT23@

Q48

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/11

+S1_VPP

+S1_VCC

10K_0402_5%

TPS_DATA
TPS_CLK
TPS_LATCH
PCI_RST#

R193

TPS_DATA<24>
TPS_CLK<24,38>

1 1

2 2

TPS_LATCH<24>
PCI_RST#<18,23,27,29,32>

C281 0.1U_0402_16V4Z

1 2

C283

1 2

4.7U_0805_10V4Z

C282 0.1U_0402_16V4Z

1 2

1 2

C284 4.7U_0805_10V4Z

43K_0402_5%

TPS_CLK

1 2

R230

4510@

New Card Power Switch

3 3

12

0.1U_0402_16V4Z7611@

+3VALW

0.1U_0402_16V4Z7611@

12

+1.5VS

12

0.1U_0402_16V4Z

1 2

+3VS

C309

C300

C301

7611@

SLP_S3#<19,38,40,42>

+3VALW

4 4

A

R238

NB_RST#<13,18,35,37,38,39>

S1_D[0:15]

S1_A[0..25]

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25

S1_VS2

S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

Compal Secret Data

S1_D[0..15] <24>

S1_A[0..25] <24>

JP22

B1

GND

B2

D3

B3

D4

B4

D5

B5

D6

B6

D7

B7

CE1#

B8

A10

B9

OE#

B10

A11

B11

A9

B12

A8

B13

A13

B14

A14

B15

WE#

B16

READY

B17

VCC

B18

VPP1

B19

A16

B20

A15

B21

A12

B22

A7

B23

A6

B24

A5

B25

A4

B26

A3

B27

A2

B28

A1

B29

A0

B30

D0

B31

D1

B32

D2

B33

WP

B34

GND

B35

GND

B36

CD1#

B37

D11

B38

D12

B39

D13

B40

D14

B41

D15

B42

CE2#

B43

VS1#

B44

IORD#

B45

IOWR#

B46

A17

B47

A18

B48

A19

B49

A20

B50

A21

B51

VCC

B52

VPP2

B53

A22

B54

A23

B55

A24

B56

A25

B57

VS2#

B58

RESET

B59

WAIT#

B60

INPACK#

B61

REG#

B62

SPKR#

B63

STSCHG#

B64

D8

B65

D9

B66

D10

B67

CD2#

B68

GND

JAE_PX20-BB2_LTCONN@

Deciphered Date

GND

USB_D-

USB_D+

CP_USB#
RESERVED
RESERVED

SMB_CLK
SMB_DATA

+1.5V
+1.5V

WAKE#

+3.3VAUX

PERST#

+3.3V
+3.3V

CLKREQ#

CP_PE#

REFCLK-

REFCLK+

GND
PERN0
PERP0

GND
PETN0
PETP0

GND

SHIELD_GND
SHIELD_GND
SHIELD_GND
SHIELD_GND

+3V_PEC

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26

3
4
5
6

D

USBP6­USBP6+
CPUSB#

PERST#

CPPE_NC#
PCIECLK0#
PCIECLK0

+3VS_PEC

1

C306

0.1U_0402_16V4Z

2

7611@

+1.5VS_PEC

1

C285

0.1U_0402_16V4Z

2

7611@

USBP6- <19>

USBP6+ <19>

+1.5VS_PEC

WAKEUP_NC# <19>

+3V_PEC
+3VS_PEC

NC_CLKREQ# <15>

CPPE_NC# <19>
PCIECLK0# <15>
PCIECLK0 <15>

PCIE_MRX_C_PTX_N0 <12>
PCIE_MRX_C_PTX_P0 <12>

PCIE_MTX_C_PRX_N0 <12>

PCIE_MTX_C_PRX_P0 <12>

R222

100K_0402_5%

CPPE_NC#
CPUSB#

+3VALW

12

12

R223
100K_0402_5%

R196
10K_0402_5%

7611@

1 2

R201

10K_0402_5%

7611@

1 2

Near to Express Card slot.

+3V_PEC

1

1

C290

4.7U_0805_10V4Z

2

7611@

1

C287

4.7U_0805_10V4Z

2

7611@

Title

Size Document Number Rev

Custom

Date: Sheet

C288

4.7U_0805_10V4Z

2

7611@

PCMCIA /Express card socket

LA-2541

26 58Friday, April 15, 2005

E

of

0.4

5

4.7U_0805_10V4Z

D D

+3VALW

PCI_AD[0..31]<18,22,23,29>

CLK_PCI_LAN

C C

B B

A A

12

R40

10_0402_5%@

1

C48

18P_0402_50V8J@

2

PCI_CBE#3<18,23,29>
PCI_CBE#2<18,23,29>
PCI_CBE#1<18,23,29>
PCI_CBE#0<18,23,29>

100_0402_5%

PCI_AD17

R41

PCI_FRAME#<18,23,29>

PCI_TRDY#<18,23,29>

PCI_DEVSEL#<18,23,29>

PCI_PERR#<18,23,29>
PCI_SERR#<18,23,29,38>

CLK_PCI_LAN<18,22>

PCI_PIRQH#<18>

+3VALW

NIC_WAKE#<19>

Y1

LAN_X1 LAN_X2

1 2

1

C26
27P_0402_50V8J

2

PCI_AD[0..31]

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27 LAN_MDI1+
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

LAN_AUXPWR

27P_0402_50V8J

5

LAN_IDSEL

CLK_PCI_LAN

1

C25

2

1 2

PCI_IRDY#<18,23,29>

PCI_STOP#<18,23,29>

PCI_PAR<18,23,29>

PCI_RST#<18,23,26,29,32>
PCI_GNT#3<18>
PCI_REQ#3<18>

1 2

R311 1K_0402_5%

25MHZ_16P_XSL025000FK1H

L2 0_0603_5%4401@

+3VS

L3 0_0603_5%5788@

U6A

B8

AD31

A8

AD30

C7

AD29

C6

AD28

B6

AD27

B5

AD26

A5

AD25

B4

AD24

B2

AD23

B1

AD22

C1

AD21

D3

AD20

D2

AD19

D1

AD18

E3

AD17

K1

AD16

L2

AD15

L1

AD14

M3

AD13

M2

AD12

M1

AD11

N2

AD10

N3

AD9

P3

AD8

N4

AD7

P4

AD6

M5

AD5

N5

AD4

P5

AD3

P6

AD2

M7

AD1

N7

AD0

C4

CBE3

F3

CBE2

L3

CBE1

M4

CBE0

A4

IDSEL

F2

FRAME

F1

IRDY

G3

TRDY

H3

DEVSEL

H1

STOP

J2

PERR

A2

SERR

J1

PAR

A3

PCI_CLK

H2

INTA

C2

PCI_RST

J3

GNT

C3

REQ

J12

VAUXPRSNT

F4

M66EN/(NC_F4)

A6

PME

BCM5788M_FBGA196

1 2

1 2

4.7U_0805_10V4Z

BCM5788M

/(BCM4401)

4

+3VALW

0.1U_0402_16V4Z

1

C22

2

+3V_LOM_PCI

0.1U_0402_16V4Z

1

C37

2

REGSUP12/(NC_B9)

REGCTL12/(NC_B10)

REGSEN12/(REG18OUT)

REGSUP25/(REGSUP18)

REGCTL25/(NC_C11)

REGSEN25/(REGSUP18)

EEDATA/(SPROM_CS)

EECLK/(SPROM_CLK)

LINKLED/(LINKLED10)

SPD100LED/(LINKLED100)

SPD1000LED/(COL_LED)

TRAFFICLED/(ACT_LED)

PLLVDD2/(PLLVDD)

NC_E10/(EEDATA_PXE)

NC_E11/(EECLK_PXE)

4

1

C391

2

0.1U_0402_16V4Z

20mils

1

C32

2

0.1U_0402_16V4Z

TRD3+/(NC_E13)

TRD3-/(NC_E14)

TRD2+/(NC_D13)

TRD2-/(NC_D14)

TRD1+/(RDP)
TRD1-/(RDN)
TRD0+/(TDP)

TRD0-/(TDN)

VESD1
VESD2
VESD3

GPIO0/(NC_H12)
GPIO1/(NC_K13)

GPIO2/(NC_J13)

NC_P7

TCK

TDO
TMS

TRST

XTALVDD

XTALO

XTALI

NC_G11

NC_H11

BIASVDD

RDAC

NC_A10

NC_C9

0.1U_0402_16V4Z

1

C401

2

0.1U_0402_16V4Z

1

C383

2

E13
E14
D13
D14
C13
C14
B13
B14

B9
B10
A9

B11
C11
C10

P1
G2
A1

P10
M10

H12
K13
J13

G13
H13
G12
G14

20mils

H14
P7

C12
D12

TDI

B12
A12
D11

J14
N10
N11

G11
E10
E11
H11

10mils

A14
D10

10mils

A10
C9

3

LAN_CTRL_2.5V

1

1

C41

2

1

2

C28

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C384

0.1U_0402_16V4Z

LAN_MDI3+
LAN_MDI3­LAN_MDI2+
LAN_MDI2-

LAN_MDI1­LAN_MDI0+
LAN_MDI0-

LAN_CTRL_2.5V

LAN_EEDA
LAN_EECLK

LAN_EEWP

R312 0_0402_5%5788@

LAN_ACTIVITY#

+1.2V_LAN_PLLVDD

0.1U_0402_16V4Z
C396

LAN_TRST#

LAN_X1_R
LAN_X2

+LAN_BIASVDD
LAN_RDAC

1

C402

C45

2

2

LAN_MIDI3+ <28>
LAN_MIDI3- <28>
LAN_MIDI2+ <28>
LAN_MIDI2- <28>
LAN_MIDI1+ <28>
LAN_MIDI1- <28>
LAN_MIDI0+ <28>
LAN_MIDI0- <28>

+2.5V_LAN

1 2

R313 0_0402_5%5788@

+1.2V_LAN
+3VALW
+2.5V_LAN
+3VALW

1 2

R310 1K_0402_5%5788@

1 2

1 2

R38 4.7K_0402_5%

+2.5V_LAN

1 2

R27 200_0402_1%

1.21K for BCM5788 1.27K for
BCM4401(P/N: SD034127100)

1 2

R39 1.21K_0402_1%

LAN_ACTIVITY# <28,40>

1

1

C397

2

2

2.2U_0805_16V4Z

LAN_X1

C405 1000P_0402_50V7K

1 2

LAN_CTRL_1.2V

+3VALW

+1.2V_LAN_PLLVDD

1 2

L20
0_0603_5%

1 2

L4 0_0603_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

3

10U_0805_10V4Z

+1.2V_LAN

+3V_LOM_PCI

LAN_LINK# <19,28,40>

+1.2V_LAN

+2.5V_LAN

+3VALW

PM_CLKRUN#<18,23,29,37,38>

1

2

2005/03/01 2006/03/11

3

PM_CLKRUN#

+2.5V_LAN

C47

0.1U_0402_16V4Z

Compal Secret Data

1

Q27
BCP69_SOT2235788@

2
4

+1.2V_LAN

0.1U_0402_16V4Z

Deciphered Date

+3VALW

1

C389

2

1

C385

2

0.1U_0402_16V4Z

LAN_EEDA
LAN_EECLK
LAN_EEDI
LAN_EEDO

1 2

R512 0_0603_5%@

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C387

2

U6B

E12

VDDC_E12

H5

VDDC_H5

H6

VDDC_H6

H7

VDDC_H7

H8

VDDC_H8

J5

VDDC_J5

J6

VDDC_J6

J7

VDDC_J7

J8

VDDC_J8

J9

VDDC_J9

J10

VDDC_J10

K5

VDDC_K5

K6

VDDC_K6

K7

VDDC_K7

K8

VDDC_K8

K9

VDDC_K9

K10

VDDC_K10

L5

VDDC_L5

L10

VDDC_L10

M14

VDDC_M14

N14

VDDC_N14

P8

VDDC_P8

P12

VDDC_P12

P13

VDDC_P13

P14

VDDC_P14

A7

VDDIO-PCI_A7

B3

VDDIO-PCI_B3

C5

VDDIO-PCI_C5

E1

VDDIO-PCI_E1

E4

VDDIO-PCI_E4

G1

VDDIO-PCI_G1

K3

VDDIO-PCI_K3

L4

VDDIO-PCI_L4

N6

VDDIO-PCI_N6

P2

VDDIO-PCI_P2

K14

VDDP_K14/(NC_K14)

L13

VDDP_L13/(NC_L13)

P11

VDDP_P11/(NC_P11)

A11

VDDIO_A11

F11

VDDIO_F11

K12

VDDIO_K12

L12

VDDIO_L12

C8

NC_C8

H4

CLKRUN

H10

NC_H10

J4

NC_J4

K4

NC_K4

J11

NC_J11/(GPIO_1)

K11

NC_K11/(GPIO_0)

L7

NC_L7

L8

NC_L8

BCM5788M_FBGA196

1
2
3
4

2

0.1U_0402_16V4Z

1

C388

2

0.1U_0402_16V4Z

1

C392

2

1

2

C390

BCM5788M

/(BCM4401)

AVDDL_F12/(AVDD_F12)
AVDDL_F13/(AVDD_F13)

LOW_POWER/(TESTMODE)

U2

CS

VCC

SK

NC

DI

NC

DO

GND

AT93C46-10SI-2.7_SO84401@

2

LAN_CTRL_1.2V

+2.5V_LAN +1.2V_LAN

0.1U_0402_16V4Z

1

C386

C393

2

0.1U_0402_16V4Z

VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8

VSS_D9/(NC_D9)

VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9

VSS_F10

VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9

VSS_G10

VSS_H9
VSS_K2

VSS_L6
VSS_L9

VSS_M6

VSS_M12

VSS_M13/(NC_M13)

VSS_N1
VSS_N12
VSS_N13

AVDD_F14/(NC_F14)

AVDD_A13/(NC_A13)

NC_L11/(VSS_L11)
NC_L14/(VSS_L14)

NC_M8

NC_M9/(VREF)

NC_N8/(EXT_POR)

NC_N9/(DOUT)

NC_P9/(DIN)

+3VALW

8
7
6
5

Q6

1

3

10U_0805_10V4Z

0.1U_0402_16V4Z

1

1

C403

2

2

B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13

+1.2V_LAN_AVDD

F12
F13

+2.5V_LAN_AVDD

F14
A13

C398

0.1U_0402_16V4Z

L11
L14

R513 0_0402_5%4401@

M8
M9
M11
N8

LAN_EEDI

N9

LAN_EEDO

P9

R24

4.7K_0402_5%5788@

LAN_EEWP
LAN_EECLK
LAN_EEDA

Title

Size Document Number Rev

B

Date: Sheet

BCP69_SOT2235788@

1

C23

2

0.1U_0402_16V4Z@

1

C395

2

0.1U_0402_16V4Z

1

1

2

2

1 2

1 2

R23 10K_0402_5%5788@

+3VALW

R22

1 2

1 2

0.1U_0402_16V4Z

1

2

1

C394

2

1 2

L21
0_0603_5%

1 2

L5

C404

0.1U_0402_16V4Z5788@

4.7K_0402_5%5788@

8
7
6
5

2
4

LAN contro lle r BCM5788M

LA-2541

C24

1

C656

2

0.1U_0402_16V4Z@

0_0603_5%5788@

C20

1 2

0.1U_0402_16V4Z

U4

VCC
WP
SCL

GND

SDA

AT24C64A_SO85788@

1

0.1U_0402_16V4Z@

C657

+1.2V_LAN
+2.5V_LAN

1

A0

2

A1

3

NC

4

1

1

2

C658

0.1U_0402_16V4Z@

20mils
20mils

27 58Friday, April 15 , 2005

1

C659

2

0.4

of

5

4

3

2

1

LAN_LINK#<19,27,40>

D D

C34 0.01U_0402_16V7K5788@

12

LAN_MIDI3+
LAN_MIDI3-

C36 0.01U_0402_16V7K5788@

12

LAN_MIDI2+
LAN_MIDI2-

C35 0.01U_0402_16V7K

12

LAN_MIDI1+
LAN_MIDI1-

C33 0.01U_0402_16V7K

12

LAN_MIDI0+
LAN_MIDI0-

C C

+2.5V_LAN

U7

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

R13 75_0402_5%5788@

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MCT_R

18

MCT3

17

MX3+

16

MX3-

MCT4

MX4+

MX4-

SQ-H40B-25788@

MCT_T

15
14
13

RJ45_MDI3+
RJ45_MDI3-

RJ45_MDI2+
RJ45_MDI2-

RJ45_MDI1+
RJ45_MDI1-

RJ45_MDI0+
RJ45_MDI0-

RJ45_MDI3+ <40>
RJ45_MDI3- <40>

RJ45_MDI2+ <40>
RJ45_MDI2- <40>

RJ45_MDI1+ <40>
RJ45_MDI1- <40>

RJ45_MDI0+ <40>
RJ45_MDI0- <40>

12

R14 75_0402_5%5788@

12

R18 75_0402_5%

12

R19 75_0402_5%

12

C380

12

1000P_1206_2KV7K

+3VALW

LAN_ACTIVITY#<27,40>

+3VALW

RJ45_MDI0­RJ45_MDI0+
RJ45_MDI1+
RJ45_MDI2+
RJ45_MDI2­RJ45_MDI1­RJ45_MDI3+
RJ45_MDI3-

LAN_LINK#

R302

12

300_0402_5%

LAN_ACTIVITY#

R301

12

300_0402_5%

JP2

2

PR1-

1

PR1+

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

FOX_JM36113-L1H7

12

LDE_YELLOW+

11

LDE_YELLOW-

SHLD113SHLD2

9

10

LED_GREEN

LED_ORANGE

14

BOM change

U5

+2.5V_LAN

LAN_MIDI1+
LAN_MIDI1-

LAN_MIDI0+
LAN_MIDI0-

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT
TD+7TX+

8

TD-

RX+

RX-

CT
NC
NC
CT

TX-

LF-H80P_16P4401@

RJ45_MDI1+

16

RJ45_MDI1-

15

MCT_R

14
13
12

MCT_T

11

RJ45_MDI0+

10

RJ45_MDI0-

9

R30

49.9_0402_1%5788@

B B

A A

LAN_MIDI3+<27>
LAN_MIDI3-<27>

LAN_MIDI2+<27>
LAN_MIDI2-<27>

LAN_MIDI1+<27>
LAN_MIDI1-<27>

LAN_MIDI0+<27>
LAN_MIDI0-<27>

LAN_MIDI3+

LAN_MIDI3-

LAN_MIDI2+

LAN_MIDI2-

49.9_0402_1%

LAN_MIDI1+

LAN_MIDI1-

49.9_0402_1%

49.9_0402_1%

LAN_MIDI0+

LAN_MIDI0-

49.9_0402_1%

R29

49.9_0402_1%5788@
R32

49.9_0402_1%5788@

R31

49.9_0402_1%5788@
R35

R33

R37

R36

12
12

12
12

12
12

12
12

C31

1 2

0.1U_0402_16V4Z5788@

C40

1 2

0.1U_0402_16V4Z5788@

C42

1 2

0.1U_0402_16V4Z

C44

1 2

0.1U_0402_16V4Z

Close to NIC U6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

LAN Magnetic & RJ45

LA-2541

1

0.4

28 58Friday, April 15 , 2005

of

A

B

C

D

E

+5VS

1

1 1

C57

0.01U_0402_16V7K

0.01U_0402_16V7K

2

C177

1

4.7U_0805_10V4Z

2

C82

1

0.01U_0402_16V7K

2

C134

1

0.1U_0402_16V4Z

2

C117

1

2

PCI_AD[0..31]

+3VS

C163

4.7U_0805_10V4Z

PCI_AD[0..31] <18,22,23,27>

1

0.01U_0402_16V7K

2

C97

1

0.1U_0402_16V4Z

2

C118

1

4.7U_0805_10V4Z

2

+3VS

1

C96

2

JP11

RINGTIP

2

112

KEY KEY

4

334

6

556

8

778

10

9910

WL_LED<36>

2 2

12

R118
1K_0402_5%

XMIT_OFF#

XMIT_OFF#<19>

+3VS

CLK_PCI_MINI<18,22>

PCI_REQ#1<18>

R99
100_0402_1%BT@

CH_DATA<34>

12

R105

10_0402_5%@

C156

10P_0402_50V8J@

3 3

PCI_CBE#3<18,23,27>

PCI_CBE#2<18,23,27>

PCI_IRDY#<18,23,27>

PM_CLKRUN#<18,23,27,37,38>

PCI_SERR#<18,23,27,38>
PCI_PERR#<18,23,27>

PCI_CBE#1<18,23,27>

1 2

XMIT_OFF#
PCI_PIRQG#

W=40mils

PCI_REQ#1
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17
PCI_IRDY#

PCI_SERR#
PCI_PERR#

PCI_CBE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3

W=30mils

+5VS

PCI_AD1

+5VS

101
103
105
107
109
111
113
115
117
119
121
123
125
127

111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101
103
105
107
109
111
113
115
117
119
121
123
125
127

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

122

122

124

124

126

126

128

128

PCI_PIRQG#

PCI_RST#CLK_PCI_MINI
PCI_GNT#1
PCI_PME#
PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINI_IDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16PCI_CBE#2

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_CBE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

W=40milsW=30mils

W=40mils

W=40mils

R100

1 2

1 2

1 2

+5VS
PCI_PIRQG# <18>

+3VALW
PCI_RST# <18,23,26,27,32>

+3VS
PCI_GNT#1 <18>

PCI_PME# <19,23>
CH_CLK <34>

100_0402_1%BT@

PCI_AD18CLK_PCI_MINI

R98

100_0402_1%

PCI_PAR <18,23,27>

PCI_FRAME# <18,23,27>
PCI_TRDY# <18,23,27>
PCI_STOP# <18,23,27>

PCI_DEVSEL# <18,23,27>

PCI_CBE#0 <18,23,27>

R4710K_0402_5%

+3VS
+3VALW

C142

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

+3VALW

1

C54

2

1

C49

4.7U_0805_10V4Z@

2

FOX_AS0A226-S2T

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Mini PCI slot

LA-2541

0.4

of

29 58Friday, April 15, 2005

E

A

B

C

D

E

W=40Mil

1

1

2

2

0.1U_0402_16V4Z

10K_0402_5%

C341

+VDDA_CODEC

12

R287
10K_0402_1%

C357

1 1

12

R280
10K_0402_1%

MONO_IN MONO_IN1 MONO_INR

C337

R258

12

PCM_SPK#<23>

1

C335

2

1 2

1U_0603_10V4Z

560_0402_5%

2

B

1

C

Q20

E

2SC2411K_SOT23

3

12

1U_0603_10V4Z

1 2

R279 20K_0402_5%

R286

1 2

10K_0402_5%

C351

1U_0603_10V4Z

+5VS

C336

4.7U_0805_10V4Z

12

0.1U_0402_16V4Z@

C338

R259

12

1U_0603_10V4Z

1 2

560_0402_5%

10K_0402_5%@

R265

12

D12

RB751V_SOD323

2 1

SB_SPKR<19>

2 2

For Layout:

Place decoupling caps near the
power pins of SmartAMC
device.

1

2

MONO_INR

+3VALW_CODEC

12

R266

249K_0402_1%

U25

1

RCOSC1

3

DIB_DATAN

4

DIB_DATAP

7

PWRCLKP

8

PWRCLKN

15

SDATA_OUT

16

SYNC

17

AC_RESET#

20

AC_ONLY

21

SDATA_IN0

22

BIT_CLK

11

ID0#

12

ID1#

14

EAPD

45

PC_BEEP

13

DSPKOUT

5

VDD5

2

GNDC2

GND8

6

10

18

VDDC18

GNDC9

9

19

VDDC10

GNDC19

AVSS_CLK

26

23

VDD_CLK

CD_IN_GND

LINE_OUT_L

LINE_OUT_R

MBIAS/AVDD

AGND35

35

41

33

44

AVDD33

AVDD44

MIC_IN

CD_IN_R

CD_IN_L

LINE_IN_L
LINE_IN_R

HP_OUT_L

HP_OUT_R

REF_FLT

VC_SCA

VREF_SCA

S_PDIF
GPIO_4
GPIO_5

XTLO

XTLI

AGND41

CX20468-31_TQFP48

2

1

29
32

31
30

27
28

39
40
42
43

38
37
36

34
46
47

R272 10K_0402_5%

48
24

25

R257

+3VALW

1 2

0_0805_5%

0.1U_0402_16V4Z

1

C347

2

10U_0805_10V4Z

3 3

DIB_DATAN<31>

DIB_DATAP<31>
PWRCLKP<31>
PWRCLKN<31>

1

1

C340

150P_0402_50V8J@

C339

150P_0402_50V8J@

2

2

AC97_SDOUT<19,22>

AC97_SYNC<19>
AC97_RST#<19>

AC97_SDIN0<19>

AC97_BITCLK<19>

1

C358

C348

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C349

2

2

0.1U_0402_16V4Z

1 2

R263 0_0402_5%

1 2

R262 0_0402_5%

1 2

R261 0_0402_5%

1 2

R260 0_0402_5%

1 2

R275 33_0402_5%

1 2

R271 33_0402_5%

C353

MUTE_LED<32,39>

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C354
1U_0603_10V4Z

2

0.1U_0402_16V4Z

LINE_IN_L
LINE_IN_R

+CODEC_REF

1 2

CODEC_HPS

33_0402_5%

1 2

R292

+3VAMP_CODEC

R295

1 2

0_0805_5%

1

C370

C352

10U_0805_10V4Z

2

C374 1U_0603_10V4Z

12

LINE_OUTL <32>
LINE_OUTR <32>

R270

1 2

2.2K_0402_5%

1 2

C363 15P_0402_50V8J

12

X1 24.576MHZ_16P_XSL024576FG1H

1 2

C367 15P_0402_50V8J

2005/03/01 2006/03/11

C

+VDDA_CODEC

MIC <33>

C369

0.1U_0402_16V4Z
R267

1K_0402_5%

Compal Secret Data

Deciphered Date

LINE_IN_L

LINE_IN_R

1

2

12

1

2

0.1U_0402_16V4Z

D11

RB751V_SOD323

12

C364

21

R249

4
2

8

2

C359
1U_0603_10V4Z

1

D

U24

VIN

SENSE or ADJ

DELAY
ERROR7CNOISE
SD

SI9182DH-AD_MSOP8

DLINE_IN_R_L

12

C3722.2U_0603_6.3V4ZSPR@

DLINE_IN_R_R

12

C3732.2U_0603_6.3V4ZSPR@

1

C362

2

0.1U_0402_16V4Z

HPS <32>

5

VOUT

6
1

1

C344

3

GND

2

0.01U_0402_16V7K

1 2

R548 0_0402_5%@

1 2

R549 0_0402_5%@

1 2

R550 0_0402_5%@

1 2

R551 0_0402_5%@

1 2

R552 0_0402_5%@

1 2

R264 0_1206_5%@

1 2

R248 0_1206_5%@

1 2

R278 0_1206_5%@

1 2

R294 0_1206_5%

Title

Size Document Number Rev

Custom

Date: Sheet

R255

1 2

12

10K_0603_1%

R256

5.9K_0603_1%

GNDAGND

1 2

1 2

CODEC CX20468-31

+VDDA_CODEC

1

C346

4.7U_0805_10V4Z

2

GNDA <32,33,40>

R2974.7K_0402_5%SPR@
R2994.7K_0402_5%SPR@

12

R2984.7K_0402_5%SPR@
R3004.7K_0402_5%SPR@

12

LA-2541

0.1U_0402_16V4Z

DLINE_IN_L <40>

DLINE_IN_R <40>

E

1

C345

2

0.4

of

30 58Friday, April 15, 2005

MTP28

MTP52

1

1

MTP26

1

MTP22

1

PWRCLKN<30>

MT902

MTP23

1

PWRCLKP<30>

DIB_DATAP<30>

DIB_DATAN<30>

MJ1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@

MJ1B

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

HEADER8@

2 3

MTP24

S X'FORM_ 835-00252

1

GND

MTP25

1

SECPRI

BR908_AC1

41

1

MC962
47P_0603_50V8J

2

PCLK

MTP27

1

MC922 10P_1808_3KV

MC924 10P_1808_3KV

MT922

2 3

30U_82154R_1%_1:1.67@

1 2

1 2

BR908_CC

MBR908A

6

BAV99DW-7_SOT363

1

2

4

5

MBR908B

3

BAV99DW-7_SOT363

41

SECPRI

0.001U_0402_50V7M@

1

MC974

MTP72

1

MC944

2

AGND_LSD

MTP29

MR932
15K_0402_5%

12

1 2

MMZ1608D301BT_0603

1

MC970

0.1U_0402_10V6K

2

MR922
0_0402_5%

DIB_P1

1 2

1 2

0_0402_5%

MTP73

MR924

1

MTP61

1

MC940
1U_0603_6.3V6M

2

0.001U_0402_50V7M

0.1U_0402_10V6K

2.2U_0805_10V6K

1

MC926
10P_0402_50V8J

1 2

MFB906

1

2

1

MC930

CLKCLK2

PWR+

MTP60

1

DIB_P2

DIB_N2

Vc_LSD
Vref_LSD

1

MC976

2

MTP30

MTP62

MTP63

1

2

1

AGND_LSD

26

1

27

28

1

22
25

29

VDD

0.1U_0402_10V6K

1

MC928

2

MU902

CLK

7

PWR+

DIB_P

DIB_N

3

Vc

4

VRef

8

NC1
NC2
NC3

PADDLE

AGND_LSD

2

AVdd

AGnd

6

DGND_LSD

MTP58

DC_GND

15

VDD

1

24

DVdd

AGND_LSD

MC978

0.1U_0402_10V6K

1 2

RAC1

TAC1

RAC2

TAC2

TRDC

EIC
RXI

GPIO1

RBias

VZ

EIO

EIF

TXO

TXF

DGnd

23

MTP59

1

DGND_LSD

RAC1

21

TAC1

20

MTP34

1

19

TRDC

18

EIC

12

MR910

11

237K_0805_1%

1 2

9
1

1

RBias

1 2

5

59K_0402_1%

1

VZ

10

1

EIO

17

EIF

16
14

TXO

13

TXF

CX20493-58_QFN28

1

MTP36

1

MTP35

MR902
1M_0805_5%

1 2
1 2

1M_0805_5%

MR904

MTP33

1

MC958

1 2

0.015U_0603_25V7K

RXI-1DIB_N1 RXI

MTP70

AGND_LSD

MR954
MTP69

MR908

1 2

348K_0805_1%

MTP68

1

MTP37

1

MTP38

MC902

RAC1/RING
TAC1/TIP

MR906 6.8M_0805_5%

1

2

AGND_LSD

1

MC904

MTP40

1 2

MC918

0.1U_0603_16V7K

1

MTP71

MC910

1 2

0.047U_1206_100V7K

MTP67

1 2
1 2

Use 59K_0402_1% for MR954

2

B

E

1

MTP65

AGND_LSD

1

MTP39

0.033U_1206_100V7K

0.033U_1206_100V7K

1

1

MTP32

2

B

C

MQ906

PMBTA42_SOT23

3 1

1

MTP64

12

MR938
110_0603_5%

RING_2

TIP_2

1 2

BRIDGE_CC

C

MQ902

PMBTA42_SOT23

E

3 1

MTP31

1 2

MMZ1608D301BT_0603

1

2

3

2

3

1

1 2

MMZ1608D301BT_0603

MC966

0.01U_0805_100V7M

2

1

3

1

1 2

AGND_LSD

MC906 and MC908 must be Y3 type
Capacitors for Nordic Countries
only

MFB902

MBR904
MMBD3004S_SOT23

AGND_LSDAGND_LSD

MBR906
MMBD3004S_SOT23

MFB904

4

MQ904

FZT458TA_SOT223

1

MR928
27_0805_5%

TIP_2

MTP66

1

MTP49

MOD_RING

MC906

1

470P_1808_3KV

2

GND

1

MC908
470P_1808_3KV

2

AGND_LSD

TB3100M-13-01_SMB

2

2
1

1

MOD_TIP

MRV902

1

MTP41

E&T_3800-02

1

MTP42

MJ2

2
1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

AMOM_modem

LA-2541

31 58Friday, April 15 , 2005

0.4

A

B

C

D

E

+5VS+5VAMP

100K_0402_5%@

100K_0402_5%

C255 100U_6.3V_M

1 2
1 2

C256 100U_6.3V_M

HPS <30>

+

+

12

R277

100K_0402_5%

12

R289

100K_0402_5%@

R166 30_0805_5%

10 dB

12

R276

12

R288

R161 30_0805_5%

1 2
1 2

+5VAMP

INTSPK_CL+

INTSPK_CR+

1K_0402_5%

R419

SPKL+
SPKL­SPKR+
SPKR-

C320

220P_0402_50V7K@

220P_0402_50V7K@

Gain Settings

GAIN0

0

0

1 0

1

GAIN1

0

1

1

Av(inv)

15.6 dB

21.6 dB

HEADPHONE OUT/LINE OUT

R401

1K_0402_5%

1 2

1 2

C318

220P_0402_50V7K@

6 dB

10 dB

C315

220P_0402_50V7K@

C312

SM05_SOT23@

JP24

1

1

2

2

3

3

4

4

2

2

3

1

D36

ACES_85205-0400

3

SM05_SOT23@

D37

1

Layout change

1 1

19

18

VDD

LOUT-

PVDD17PVDD2

LOUT+

ROUT-

ROUT+

SE/BTL#

HP/LINE#

GAIN1
GAIN0

BYPASS

GND424GND3

GND212GND1

TPA0312PWP_TSSOP24

13

R268

1 2

100K_0402_5%

R269

1 2

+5VAMP

23
20

8

10

6
5

14
22

21

D35

DLINE_OUT_R

U27

RLINEIN
RHPIN
RIN

LIN
LHPIN
LLINEIN

PC-BEEP
SHUTDOWN#

1

RB751V_SOD323@

100K_0402_5%

2

G

LINE_C_OUTR
RHPIN

LHPIN
LINE_C_OUTL

0.1U_0402_16V4Z

C655

1

13

D

2

S

DOCK_HPS<40>

Headphone Plug from NB

C356 0.047U_0603_16V7K

LINE_OUTR<30>

LINE_OUTL<30>

MUTE#<19>

2 2

3 3

1 2

C361 0.47U_0603_16V7K

1 2

C368 0.47U_0603_16V7K

1 2

C375 0.47U_0603_16V7K

C360 0.47U_0603_16V7K

1 2

C355 0.047U_0603_16V7K

1 2

R291 100K_0402_5%

MUTE_LED<30,39>

PCI_RST#<18,23,26,27,29>

1 2

C376 0.47U_0603_16V7K

1 2

1 2

Q21

2N7002_SOT23

1

C371

2

10U_0805_10V4Z

9
4
16
21

15
17

3
2

11

+5VAMP

2

I0

1

I1

1

C350

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C365

2

2

C377

0.47U_0603_16V7K

1

5

P

4

O

G

U26
TC7SH32FU_SSOP5

3

1

2

0.1U_0402_16V4Z

SPKL­SPKL+
SPKR­SPKR+

HPS

SPKR+
SPKL+

HPS

R273

0_1206_5%

C366

7

INTSPK_CR+

DLINE_OUT_R<40>
DLINE_OUT_L<40>

4 4

DLINE_OUT_R

INTSPK_CL+

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L40 KC FBM-11-160808-601T

1 2

L42 KC FBM-11-160808-601T

1 2

C588

47P_0402_50V8J

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

PR

PL

C593
47P_0402_50V8J

D

5
4
3

6
2
1

JP21

8

HP OUT

FOX_JA6033L-5S1-TR

Title

Size Document Number Rev

Custom

Date: Sheet

AMP & Audio Jack

LA-2541

E

0.4

of

32 58Friday, April 15, 2005

5

4

3

2

1

Internal/External MIC

D D

+MICAMP

+VDDA_CODEC

12

R134
3K_0402_5%

12

2

C240

1U_0603_10V4Z

JP17

1

C C

B B

A A

2

ACES_85205-0200

L17 CHB1608B121_0603

C234

1200P_0603_50V7K@

INT_MIC_CONN

EXT_MIC

1 2

1 2

C548 0.22U_0603_10V7K

1 2

C554 0.22U_0603_10V7K

1

+CODEC_REF

EXT_MIC

R135
3K_0402_5%

BOM change

C235 0.027U_0402_16V4Z

1 2

R516

1 2

3.3K_0402_5%

R375 100K_0402_5%

1 2

1 2

R376 14K_0402_1%

L36 CHB1608B121_0603

1 2

C558

470P_0402_50V7K

1

C660

2

1U_0603_10V4Z

R133

1 2

10K_0402_5%

1U_0603_10V4Z

1

C661

2

1

2

1 2

12

R514

10K_0402_5%

3

1

L44

0_0603_5%

2

SM05_SOT23@

D38

+VDDA_CODEC

1

C242

0.1U_0402_16V4Z

2

INT_MIC_CONN
INT_MIC

BOM change

C241

100P_0402_50V8J

C556

100P_0402_50V8J

R138 2.2K_0402_5%

1 2

R136 150K_0402_1%

1 2

C239 270P_0402_50V7K

+MICAMP

84

U34A

3

+

P

1

O

G

2

-

TLV2462CDR_SO8

+MICAMP

84

U34B

5

+

P

7

O

G

6

-

TLV2462CDR_SO8

C550 100P_0402_50V8J

R374 100K_0402_1%

1 2

7

5
4
3

6
2
1

JP20

8

FOX_JA6033L-5S1-TR

R137 1K_0402_1%

1 2

1

C243
1U_0603_10V4Z

2

MIC IN

+VDDA_CODEC

INT_MIC

MIC

MIC <30>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Internal / External MIC

LA-2541

1

0.4

of

33 58Friday, April 15, 2005

TP CONNECTOR

+5VS

TP_DATA<38>

TP_CLK<38>

JP19

6

6

5

5

4

4

3

3

2

2

1

1

ACES_87153-0601

1
4
2

SLP_S5

JP13

VCC
D0­D0+
VSS

G210G1

VCC

VSS

VCC

+USB_VCCA+5VALW

1

C195

0.47U_0603_16V7K

2

1

1

C537

2

1

C538
1000P_0402_50V7K

2

USBP7- <19>USBP4-<19>
USBP7+ <19>

100U_6.3V_M

5
6

D1-

7

D1+

8
9

G311G4

+USB_VCCA

4

D2+

5
6

D1-

10P_0402_50V8J@

C546

USBP7-

USBP4+

2

0.1U_0402_16V4Z

C543

10P_0402_50V8J@

+

C542

+5VALW +USB_VCCB

C16

1 2

0.1U_0402_16V4Z

12

AATI4610AIGV-T1_SOT23-5

R7

4.7K_0603_1%

USBP5-<19>
USBP5+<19>

VCC

I/O

+USB_VCCB

4

3

USBP5+USBP5-

D39

1

GND

2

I/O

PRTR5V0U2X_SOT143@

5

IN

3

SET

SLP_S5<40,42,48>

OUT
ON#
GND

100U_6.3V_M

10P_0402_50V8J@

U1

C7

1
4
2

SLP_S5

C1

W=40mils

1

+

C379

2

0.1U_0402_16V4Z

C2

10P_0402_50V8J@

1

C12

0.47U_0603_16V7K

2

1

1

2

2

+USB_VCCB

C378
1000P_0402_50V7K

JP3

1
2
3
4

5
6
7
8

SUYIN 020167MR004S511ZU_4p

C219

100U_6.3V_M

USBP4+<19>

BT CONN.

JP18

ACES_87212-0800BT_CONN@

1
2
3
4
5
6
7
8

+3V_BT
USBP2+ <19>

USBP2- <19>

BT_LED <36>

CH_DATA <29>
CH_CLK <29>

BT_DETECT# <19>

C536

1 2

0.1U_0402_16V4Z

AATI4610AIGV-T1_SOT23-5

12

R366

4.7K_0603_1%

+USB_VCCA +USB_VCCA

U33

5

OUT

IN

ON#

3

SET

GND

W=40mils W=40mils

1

1

C197

C216

10P_0402_50V8J@

2

C212

USBP4-

USBP7+

1

C196
1000P_0402_50V7K

2

10P_0402_50V8J@

1
2
3
4

12

SUYIN_020122MR008S540ZU

D40

1

D1+

2

GND

3

D2-

IP4220CZ6_SO6@

+

2

0.1U_0402_16V4Z

FINGER PRINT CONN.

C686

0.1U_0402_16V4ZFP@

USBP1-<19>

USBP1+<19>

+3VS

12

JP12

1

1

2

2

3

3

4

4

ACES_85205-0400

Q36

SI2301BDS_SOT23BT@

S

D

13

1

C549
1U_0603_10V4ZBT@

2

BT_OFF<19>

G

2

1

C237

2

0.01U_0402_16V7KBT@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V_BT+3VALW

1

1

C236

C238

0.1U_0402_16V4ZBT@

2

4.7U_0805_10V4ZBT@

2

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Bluetooth & USB CONN.

LA-2541

34 58Friday, April 15, 2005

0.4

5

4

3

2

1

HDD/ODDModule

Placea caps. near HDD CONN.

D D

+5VS

1

C277

2

1000P_0402_50V7K

0.1U_0402_16V4Z

1

C276

2

10U_0805_10V4Z@

1

C280

2

1U_0603_10V4Z@

1

C274

2

1

C273
10U_0805_10V4Z

2

PD_D[0..15]<20>

C C

B B

SD_D[0..15]<20>

A A

PD_D[0..15]

SD_D[0..15]

NB_RST#<13,18,26,37,38,39>

PD_DREQ#<20>

PD_IOW#<20>
PD_IOR#<20>

PD_IORDY<20>

PD_DACK#<20,22>
PD_IRQA<20>

PD_A1<20>
PD_A0<20>

PD_CS#1<20> PD_CS#3 <20>

+5VS

R510 100K_0402_5%

SD_SIOW#<20>

SD_IRQA<20>
SD_SBA1<20>
SD_SBA0<20>

SD_SCS1#<20> SD_SCS3# <20>

+5VS

R511 100K_0402_5%

SEC_CSEL

12

R367 470_0402_5%

NB_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2

PD_D0
PD_DREQ#

PD_IOW#
PD_IOR#
PD_IORDY PCSEL
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_ACT_LED#

1 2

1 2

+5VS

+5VS

NB_RST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0

SD_SIOW#
SD_IORDY
SD_IRQA
SD_SBA1
SD_SBA0
SD_SCS1#
ODD_ACT_LED#

+5VS
+5VS

JP23

9

SUYIN_200138FR044G277ZU

1

C198

2

1000P_0402_50V7K

112
334
556
778
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
GND45GND

0.1U_0402_16V4Z@

1

C208

2

2
4
6
8
10

10

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

1

C539

2

1U_0603_10V4Z@

Place caps. near ODD CONN.

JP14

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

OCTEK_CDR-50DU1

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14PD_D1
PD_D15

R207 470_0402_5%

1 2

PD_A2
PD_CS#3

SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ#
SD_SIOR#

SD_DACK#
PDIAG#

SD_SBA2
SD_SCS3#

W=80mils

C540 0.1U_0402_16V4Z

+5VS

10U_0805_10V4Z@

1

C541

2

R371 100K_0402_5%@

1 2

12

1

2

SD_DREQ# <20>

SD_SIOR# <20>
SD_DACK# <20>SD_IORDY<20>

PD_A2 <20>

C206
10U_0805_10V4Z

SD_SBA2 <20>

+5VS
+5VS
+5VS

HDD_ACT_LED#

ODD_ACT_LED#

+5VS

D32

RB751V_SOD323

D33

RB751V_SOD323

R190

100K_0402_5%

ACT_LED#

21

21

+5VS

12

+5VS

E

R192

1 2

1K_0402_5%

B

2

3

Q16

C

MMBT3906_SOT23

1

ACT_LED <36>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

HDD / ODD connector

LA-2541

1

0.4

of

35 58Friday, April 15, 2005

5

4

3

2

1

+3VL

D D

C C

ACT_LED<35>

HDD/ODD LED

GREEN

12

R296

560_0402_5%

21

D14

17-21SYGC/S530-E1/TR8_GRN

270_0402_5%

BATT FULL LED

GREEN

BAT_GRNLED#<38>

BAT_LED#<38>

R285

R555
270_0402_5%

21

34

D16

Charger LED

19-22UYSYGC/S530-A2/TR8_G/Y

AMBER

POWER LED

Wireless / Bluetooth LED

WL_BT_LED#<39>

WL_LED<29>

B B

BT_LED<34>

WL_LED

BT_LED

12

R281

100K_0402_5%BT@

1 2

1K_0402_5%

1 2

12

R283
100K_0402_5%

R284

R282

1K_0402_5%BT@

2

2

Q24
MMBT3904_SOT23

3 1

Q23

MMBT3904_SOT23BT@

3 1

BLUE

R293

1 2

220_0402_5%

+5VS

21

D13
HT-170CBS-DT_BLUE_0805

STB_LED#<38,39,40>

GREEN

STB_LED#

R274

1 2

1K_0402_5%

BOM and layout modify

+3VALW

21

D15

17-21SYGC/S530-E1/TR8_GRN

E

3

B

Q22

2

C

MMBT3906_SOT23

1
12

R290
220_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

3

Compal Secret Data

Deciphered Date

Title

Size Docu ment Number Rev

B

2

Date: Sheet

LED INDICATOR

LA-2541

0.4

36 58Friday, April 15, 2005

1

of

A

B

C

+3VS

DCD#1
RI#1
CTS#1
DSR#1

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%SIO@

RP7

D

E

1 1

2 1

SIO@

RXD1 <40>

0.1U_0402_16V4ZSIO@

1

C381

2

R309 1K_0402_5%SIO@

1 2

TXD1 <40>
DSR#1 <40>
RTS#1 <40>
CTS#1 <40>
DTR#1 <40>
RI#1 <40>
DCD#1 <40>

LPTINIT# <40>
LPTSLCTIN# <40>
LPD0 <40>
LPD1 <40>
LPD2 <40>
LPD3 <40>
LPD4 <40>
LPD5 <40>
LPD6 <40>
LPD7 <40>
LPTSLCT <40>
LPTPE <40>
LPTBUSY <40>
LPTACK# <40>
LPTERR# <40>
LPTAFD# <40>
LPTSTB# <40>

1

1

C29

C382

2

2

0.1U_0402_16V4ZSIO@

+3VS

4.7U_0805_10V4ZSIO@

LPC_AD0<18,38,39>
LPC_AD1<18,38,39>
LPC_AD2<18,38,39>
LPC_AD3<18,38,39>

LPC_FRAME#<18,38,39>

LPC_DRQ#0<18>

R26

+3VS

RP4

+3VS

RP2

R11

1 2

R306

1 2

R305

1 2

R12

1 2

R308

1 2

2 2

3 3

SIO_GPIO46

18

SIO_GPIO45

27

SIO_GPIO44

36

SIO_GPIO43

45

10K_0804_8P4R_5%SIO@

SIO_IRQ

18

SIO_GPIO12

27

SIO_GPIO10

36

SER_SHD

45

10K_0804_8P4R_5%SIO@

SIO_GPIO23

10K_0402_5%SIO@

SIO_GPIO41

10K_0402_5%SIO@

SIO_GPIO42

10K_0402_5%SIO@

+3VS

12

1 2

R307 10K_0402_5%SIO@

R25
10_0402_5%@

CLK_14M_SIOCLK_PCI_SIO

12

1

SIO_GPIO11

10K_0402_5%SIO@

SIO_GPIO40

10K_0402_5%SIO@

C21
18P_0402_50V8J

@

@

2

NB_RST#<13,18,26,35,38,39>

1 2

10K_0402_5%SIO@

PM_CLKRUN#<18,23,27,29,38>

CLK_PCI_SIO<18,22>

CLK_14M_SIO<15>

R28
10_0402_5%@

C30
10P_0402_25V8K

SIRQ<18,23,38>

SER_SHD<40>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_PD#
PM_CLKRUN#

CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

SIO_GPIO41
SIO_GPIO42
SIO_GPIO43
SIO_GPIO44
SIO_GPIO45
SIO_GPIO46
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

SIO_GPIO23

U3

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64SIO@

Base I/O Address

0 = 02Eh
1 = 04Eh*

LPC I/F

GPIO

POWER

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

SERIAL I/F

DCD1#

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

BUSY

PARALLEL I/F

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

RXD1

62

TXD1

63

DSR#1

64

RTS#1

1

CTS#1

2

DTR#1

3

RI#1

4

DCD#1

5
37

38
39

LPTINIT#

41

LPTSLCTIN#

42

LPD0

44

LPD1

46

LPD2

47

LPD3

48

LPD4

49

LPD5

50

LPD6

51

LPD7

53

LPTSLCT

55

LPTPE

56

PE

LPTBUSY

57

LPTACK#

58

LPTERR#

59

LPTAFD#

60

LPTSTB#

61

7
11
26
45
54

1

C27

2

0.1U_0402_16V4ZSIO@

LPD2
LPD1
LPD0
LPTSLCTIN#

LPD6
LPD5
LPD4
LPD3

LPTBUSY
LPTPE
LPTSLCT
LPD7

LPTSTB#
LPTAFD#
LPTERR#
LPTACK#

LPTINIT#

RB420D_SOT23

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%SIO@

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%SIO@

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%SIO@

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%SIO@

1 2

4.7K_0402_5%SIO@

+5VS_PRN+5VS

D1

RP1

RP3

RP5

RP6

R16

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/11

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Super I/O LPC47N217

LA-2541

E

0.4

37 58Friday, April 15, 2005

5

4

+3VL +3VS

3

2

1

BOM and layout change

1

C639

+3VL

D D

C C

B B

A A

1 8
2 7
3 6
4 5

47K_0804_8P4R_5%

1 8
2 7
3 6
4 5

47K_0804_8P4R_5%

+5VS

1 2

10K_0402_5%

1 2

10K_0402_5%

1 8
2 7
3 6
4 5

+3VS

12

R472
10K_0402_5%

LPCPD#

CLK_PCI_EC

12

R476
10_0402_5%@

C643

RP64

KSI3
KSI2
KSI1
KSI0

RP65

KSI7
KSI6
KSI5
KSI4

R466

TP_CLK

R468

TP_DATA

RP66

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

10K_0804_8P4R_5%

Layout and BOM change

+3VL +RTCVCC

10P_0402_50V8J@

D31

2 1

RB751V_SOD323

10P_0402_50V8J

0.1U_0402_16V4Z

1 2

R493
2M_0402_5%@

1

IN

C653

2

32.768KHZ_12.5P_1TJS125DJ2A073

0.1U_0402_16V4Z

2

KSO[0..13]<39>

KSI[0..7]<39>

PM_CLKRUN#<18,23,27,29,37>

CLK_PCI_EC<18,22>
RUNSCI_EC#<19>

Layout and BOM change

LPC_FRAME#<18,37,39>

R494

120K_0402_5%

4

Y6

OUT

C654
10P_0402_50V8J

NC3NC

1U_0603_10V4Z

1

C645

0.1U_0402_16V4Z

2

KSO[0..13]

KSI[0..7]

TP_CLK<34>
TP_DATA<34>
KBD_CLK<40>
KBD_DATA<40>
PS2_CLK<40>
PS2_DATA<40>

SIRQ<18,23,37>

LPC_AD3<18,37,39>
LPC_AD2<18,37,39>
LPC_AD1<18,37,39>
LPC_AD0<18,37,39>

NB_RST#<13,18,26,35,37,39>

12

+RTCVCC

2

C651

1

C650

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRUN#
SIRQ
CLK_PCI_EC

RUNSCI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#
NB_RST#
LPCPD#

CRY1
CRY2

1

C649

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

17
16
15
14
13
12
10

9
7
6
5
4
3
2

25
24
23
22
21
20
19
18

26
27
29
31
32
33

44
46
43
59

40
39
37
35

41
42
34

53
54

51
52

12

R486
300_0402_5%

U39

1

C634

2

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/OUT8/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#
LPCPD#

XTAL1
XTAL2

VCC0
XOSEL

1

C633

4.7U_0805_10V4Z

Power Mgmt/SIRQ

2

VCC111VCC167VCC181VCC194VCC230VCC238VCC2

Keyboard/Mouse Interface

LPC

Bus

AGND

55

SMSC_LPC47N250_TQFP-100P

GND92GND79GND65GND45GND36GND28GND

AGND FILTER

C652

1 2

0.1U_0402_16V4Z

1

2

47

Access Bus Interface

8

1

2

OUT0

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO2

GPIO3
GPIO4/KSO14
GPIO5/KSO15

GPIO7/PWM3

GPIO8/RXD

GPIO9/TXD

GPIO12/AB2A_CLK
GPIO14/AB2B_CLK

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM

FWP#

EA#

CLOCK

32KHZ_OUT

RESET_OUT#

PWRGD

VCC1_PWRGD

24MHZ_OUT

TEST PIN

MODE

DMS_LED#

BAT_LED#

FDD_LED#/8051RX

C644

0.1U_0402_16V4Z

99
100

98
97
96
95
93

62
63
64
66

68
69
70

71
72
73
74
75
76
77

78
80

86
87

84
85

56
82
83
48
58
49
61
60
50

1
57

91
88
90
89

C640

0.1U_0402_16V4Z

GPIO11/AB2A_DATA
GPIO13/AB2B_DATA
GPIO15/FAN_TACH1

General Purpose I/O Interface

GPIO16/FAN_TACH2

PWR_LED#/8051TX

Miscellaneous

LPC47N250-MD_TQFP100

MODE

PGM

SHORT PADS

PGM

NO SHORT PADS

EA#

FWP#

NO SHORT PADS

J8

1 2

J6

1 2

J9

1 2

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

1K_0402_5%

1K_0402_5%

1 2

1K_0402_5%

R487

R483

R492

R477

R479

1

C637

0.1U_0402_16V4Z

2

KBC_PWR_ON
BAT_GRNLED#

BATSELB_A#
KBRST

FAN_PWM
CHGCTRL

ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15

PM_RSMRST#

DIGI_RX
DIGI_TX

BATCON
KBC_GPIO12
ADP_PRES
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M

NUM_LED#
SLP_S3#

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

PGM
FWP#
EA#
CLK_14M_KBC
S_CLK
SB_PWRGD
NB_PWRGD
VCC1_PWRGD

MODE

BAT_LED#
STB_LED#
CAPS_LED#

1. For normal operation:

a. Short J8
b. Open J6
c. Open J9

+3VL

2. For KBC internal ROM flash:

a. Open J8
b. Short J6
c. Short J9

12

1

C641

4.7U_0805_10V4Z

2

KBC_PWR_ON <44>
BAT_GRNLED# <36>

BATSELB_A# <51>

FAN_PWM <4>
CHGCTRL <43,51>

ON/OFFBTN_KBC# <39>
LOW_BAT# <19>
KSO14 <39>
KSO15 <39>

PM_RSMRST# <19,46>

BATCON <51>
KBC_GPIO12 <19>
ADP_PRES <43,45,51>
THM_MBAY# <50>
PCI_SERR# <18,23,27,29>
THM_MAIN# <50>

NUM_LED# <39>
SLP_S3# <19,26,40,42>

AB1A_DATA <50>
AB1A_CLK <50>

AB1B_DATA <50>
AB1B_CLK <50>

CLK_14M_KBC <15>
SB_PWRGD <19>

NB_PWRGD <13,18,41>
VCC1_PWRGD <41>

BAT_LED# <36>
STB_LED# <36,39,40>
CAPS_LED# <39>

+3VL

R497

100K_0402_5%

D30

21

RB751V_SOD323

1 2

R488 33_0402_5%7611@

13

D

1 2

2N7002_SOT23

2

G

Q46

S

+3VL

12

R491

100K_0402_5%

KBC_GPIO12

GATEA20 <19>

AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

NUM_LED#

SB_PWRGD

FWP# NB_PWRGD

RP67

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%
R481

1 2

100K_0402_5%

TPS_CLK <24,26>

1 2

R489

1 2

10K_0402_5%

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

For KBC debugging used.

KB_RST# <18,19>

100K_0402_5%

THM_MAIN#

+3VL

R484

47K_0402_5%

+3VL

+3VL

12

R507

CLK_14M_KBC

JP30

1
2
3
4
5
6

ACES_85201-0602@

12

R480
10_0402_5%@

1

C648
10P_0402_25V8K@

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

EC LPC47N250

LA-2541

0.4

of

38 58Friday, April 15, 2005

1

5

4

3

2

1

BIOS ROM

INT_KBD CONN.

KSO[0..15]<38>

KSI[0..7]<38>

JP15

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

ACES_85203-2402

KSO[0..15]

KSI[0..7]

KSI1

25

25

KSI7

26

26

KSI6

27

27

KSO9

28

28

KSI4

29

29

KSI5

30

30

KSO0

31

31

KSI2

32

32

KSI3

33

33

KSO5

34

34

KSO1

35

35

KSI0

36

36

KSO2

37

37

KSO4

38

38

KSO7

39

39

KSO8

40

40

KSO6

41

41

KSO3

42

42

KSO12

43

43

KSO13

44

44

KSO14

45

45

KSO11

46

46

KSO10

47

47

KSO15

48

48

C662 56P_0402_50V8J

KSI3

1 2

C663 56P_0402_50V8J

KSO5

1 2

C664 56P_0402_50V8J

KSO1

1 2

C665 56P_0402_50V8J

KSI0

1 2

C666 56P_0402_50V8J

KSO2

1 2

C667 56P_0402_50V8J

KSO4

1 2

C668 56P_0402_50V8J

KSO7

1 2

C669 56P_0402_50V8J

KSO8

1 2

C670 56P_0402_50V8J

KSI1

1 2

C671 56P_0402_50V8J

KSI7

1 2

C672 56P_0402_50V8J

KSI6

1 2

C673 56P_0402_50V8J

KSO9

1 2

C674 56P_0402_50V8J

KSI4

1 2

C675 56P_0402_50V8J

KSI5

1 2

C676 56P_0402_50V8J

KSO0

1 2

C677 56P_0402_50V8J

KSI2

1 2

U15

24

A0/ID0

23

A1/ID1

22

A2/ID2

21

D D

C C

FWH_TBL#<18>

FWH_WP#<18>

CLK_PCI_FWH

R189

1 2

100_0402_5%

12

R415
10_0402_5%@

1

C596
10P_0402_25V8K@

2

FWH_TBL#
FWH_WP#

FWH_GPI

20
19

18
17
16
15

7
1

3
4
5
6

8
11
13
14
31
36

A3/ID3
A4/TBL#

A5/WP#
A6/FGP10

A7/FGP11
A8/FGP12
A9/FGP13
A10/FGP14

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

SST49LF008A-33-4C-EI_TSOP40@

VDD2
VDD1

VSS3
VSS2
VSS1

DQ0/FWH0
DQ1/FWH1
DQ2/FWH2
DQ3/FWH3
WE#/FWH4

DQ4/RES
DQ5/RES
DQ6/RES
DQ7/RES

R/C#/CLK

RST#

OE#/INIT#

IC

39
10

40
30
29

25
26
27
28
38

32
33
34
35

9
12
37

2

+3VS

1

C271

0.1U_0402_16V4Z

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

CLK_PCI_FWH
NB_RST#
FWH_INIT#

FWH_IC

1

C254

0.1U_0402_16V4Z

2

LPC_AD0 <18,37,38>
LPC_AD1 <18,37,38>
LPC_AD2 <18,37,38>
LPC_AD3 <18,37,38>
LPC_FRAME# <18,37,38>

CLK_PCI_FWH <18>
NB_RST# <13,18,26,35,37,38>

FWH_INIT# <18>

12

R158
10K_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH_TBL#
FWH_WP#

U18

13

DQ0/FWH0/LAD0

14

DQ1/FWH1/LAD1

15

DQ2/FWH2/LAD2

17

DQ3/FWH3/LAD3

18

DQ4/RES

19

DQ5/RES

20

DQ6/RES

21

DQ7/RES

8

A4/TBL#

7

A5/WP#

6

A6/FGPI0/GPI0

5

A7/FGPI1/GPI1

4

A8/FGPI2/GPI2

3

A9/FGPI3/GPI3

30

A10/FGPI4/GPI4

1

NC

22

NC

26

NC

27

NC

SST49LF004B-33-4C-NH_PLCC32

LFRAME#/FWH4/WE#

VDD
VDD

VSS
VSS

RST#

CLOCK/R/C#

IC/MODE

INIT#/OCE#

ID0/A0
ID1/A1
ID2/A2
ID3/A3

25
32

16
28

2
31
29
24

12
11
10
9

23

+3VS

NB_RST#
CLK_PCI_FWH

FWH_ICFWH_GPI

FWH_INIT#

LPC_FRAME#

Switch Board conn./ LID Switch

JP6

KSO12<38>

+3VS
+5VS

KSI0<38>
KSI1<38>
KSI4<38>
KSI5<38>
KSI6<38>
KSI7<38>

WL_BT_LED#<36>

MUTE_LED<30,32>

NUM_LED#<38>

CAPS_LED#<38>

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

ACES_85203-1402

SW1

2

4

ESE11MV9_4P

1

3

1

C6

0.1U_0402_16V4Z

2

LID_SW# <16,19>

C678 56P_0402_50V8J

KSO14

1 2

C679 56P_0402_50V8J

KSO11

1 2

C680 56P_0402_50V8J

KSO10

1 2

C681 56P_0402_50V8J

KSO15

1 2

C682 56P_0402_50V8J

KSO6

1 2

C683 56P_0402_50V8J

KSO3

1 2

C684 56P_0402_50V8J

KSO12

1 2

C685 56P_0402_50V8J

KSO13

1 2

B B

+3VALW

ON/OFF#

R473

100K_0402_5%

JP4

1

1

2

2

3

3

4

4

ACES_85205-0400

ON/OFFBTN_KBC# <38>

ON/OFFBTN# <19>

12

+3VALW

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

BIOS BOM/SW B D CONN/KB CONN

LA-2541

1

of

39 58Friday, April 15, 2005

0.4

ON/OFF#<40>

STB_LED#<36,38,40>

ON/OFFBTN_KBC#

D28

RB751V_SOD323

0.1U_0402_16V4Z

1 2

C689

21

Power button

Layout and BOM change

+3VL

C642

2

G

4

12

R485
100K_0402_5%

13

D

2N7002_SOT23
Q44

S

+3VL

+3VL

12

R475

100K_0402_5%

ON/OFF#

A A

5

C638

0.1U_0402_16V4Z

14

U40A

P

1

O2I

G

1

SN74LVC14APWLE_TSSOP14

7

2

R474

1 2

100K_0402_5%

1

0.1U_0402_16V4Z

2

A

B

C

D

E

1

2

L1

12

1

C18
1000P_0402_50V7KSPR@

2

JP26A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

JAE_SP03-14588-PCL03

SPR_CONN@

+DOCKVIN

P1G1

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

DETECT
RJ45_MDI3+

RJ45_MDI3­RJ45_MDI1+

RJ45_MDI1­PWR_LED

1 2

R9 1K_0402_5%SPR@

DOCK CONN. 184PIN

+DOCKVIN

RJ45_MDI3+ <28>
RJ45_MDI3- <28>

RJ45_MDI1+ <28>
RJ45_MDI1- <28>

SLP_S5#_5R

USBP0-

C8 10P_0402_50V8J@

USBP0+

C9 10P_0402_50V8J@

USBP3-

C10 10P_0402_50V8J@

USBP3+

C11

LPTACK#<37>

LPTBUSY<37>

LPTPE<37>

LPTSLCT<37>

LPD7<37>
LPD6<37>
LPD5<37>
LPD4<37>
LPD3<37>
LPD2<37>
LPD1<37>
LPD0<37>

LPTSLCTIN#<37>

LPTINIT#<37>

USBP0-<19>

USBP0+<19>
USBP3-<19>
USBP3+<19>

SER_SHD<37>

EXPCRD_RST#<19>

10P_0402_50V8J@

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

USBP0­USBP0+
USBP3­USBP3+

SER_SHD
EXPCRD_RST#
DETECT

DOCK_MOD_RING

JP26B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

165

GND

166

GND

167

GND

168

GND

169

GND

170

GND

G2

G2

RING

RING

SPR@

JAE_SP03-14588-PCL03

GND
GND
GND
GND
GND
GND

128

128

129

129

130

130

131

131

132

132

133

133

134

134

135

135

136

136

137

137

138

138

139

139

140

140

141

141

142

142

143

143

144

144

145

145

146

146

147

147

148

148

149

149

150

150

151

151

152

152

153

153

154

154

155

155

156

156

157

157

158

158

159

159

160

160

161

161

162

162

163

163

164

164

171
172
173
174
175
176

P2

P2

TIP

TIP

KBD_DATA
KBD_CLK
CPPE_DOCK#
PS2_DATA
PS2_CLK
DOCK_HPS#

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1

PCIE_MRX_C_PTX_P1
PCIE_MRX_C_PTX_N1

PCIECLK_DOCK
PCIECLK_DOCK#
PREP#

VA_ON#

12

R17

1K_0402_5%SPR@

+5VS

DOCK_MOD_TIP

KBD_DATA <38>
KBD_CLK <38>
CPPE_DOCK# <15,19>
PS2_DATA <38>
PS2_CLK <38>

DLINE_IN_L <30>
DLINE_IN_R <30>

DLINE_OUT_L <32>
DLINE_OUT_R <32>

PCIE_MTX_C_PRX_P1 <12>
PCIE_MTX_C_PRX_N1 <12>

PCIE_MRX_C_PTX_P1 <12>
PCIE_MRX_C_PTX_N1 <12>

PCIECLK_DOCK <15>
PCIECLK_DOCK# <15>
PREP# <19>

1

C19

0.1U_0402_16V4ZSPR@

2

1 1

ON/OFF#<39>

RJ45_MDI2+<28>
RJ45_MDI2-<28>

RJ45_MDI0+<28>
RJ45_MDI0-<28>

LAN_ACT#_DOCK

2 2

CRT_RED<13,17>

CRT_GREEN<13,17>

CRT_BLUE<13,17>

C15

5P_0402_50V8C@

5P_0402_50V8C@

3 3

R4 0_0402_5%SPR@
R5 0_0402_5%SPR@
R6 0_0402_5%SPR@

C14

C13

5P_0402_50V8C@

CRT_VSYNC<17>

CRT_HSYNC<17>

CRT_DDCDA<17>

CRT_DDCCL<17>

D_COMPS<13,17>

D_CRMA<13,17>

D_LUMA<13,17>

DCD#1<37>

RI#1<37>
DTR#1<37>
CTS#1<37>
RTS#1<37>
DSR#1<37>

TXD1<37>
RXD1<37>

LPTSTB#<37>
LPTAFD#<37>

LPTERR#<37>

LANLINK_STATUS#_DOCK

KC FBM-L18-453215-900LMA90T_1812SPR@

VIN

C17

1000P_0402_50V7KSPR@

ON/OFF#
RJ45_MDI2+

RJ45_MDI2­RJ45_MDI0+

RJ45_MDI0-

CRT_DDCDA
CRT_DDCCL

D_RED

12

D_GREEN

12

D_BLUE

12

D_COMPS
D_CRMA
D_LUMA

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

+3VALW +5VALW

LAN_ACT#_DOCK

13

R21

+3VALW

4 4

12

10K_0402_5%SPR@

A

D

2

G

S

13

D

2

G

S

SPR@

2N7002_SOT23
Q1

LAN_ACTIVITY#

LANLINK_STATUS#_DOCK

SPR@

2N7002_SOT23
Q2

LAN_LINK#

LAN_ACTIVITY# <27,28>

STB_LED#<36,38,39>

SLP_S3#<19,26,38,42>

LAN_LINK# <19,27,28>

B

12

R8

SPR@

10K_0402_5%

PWR_LED

13

D

SPR@

2N7002_SOT23

2

G

Q3

S

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SLP_S5<34,42,48>

2005/03/01 2006/03/11

12

R10

SPR@

100K_0402_5%

SLP_S5#_5R

13

D

Q4

2

SPR@

G

2N7002_SOT23

S

Compal Secret Data

Deciphered Date

12

DOCK_HPS#

D

R15
100K_0402_5%

2

G

+5VS+5VS

12

R20
100K_0402_5%

13

D

S

DOCK_HPS <32>

Q5

2N7002_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet

DOCK_MOD_TIP
DOCK_MOD_RING

SPR Connector

LA-2541

E

JP5

1
2

SPR@

ACES_85205-0200

40 58Friday, April 15, 2005

0.4

of

5

D D

C C

B B

4

+2.5VS

12

VGATE<15,47,48,49>

+3VL +3VL

1

R470
10K_0402_5%

3

C647

0.1U_0402_16V4Z

14

2

U40B

P

O4I

G

SN74LVC14APWLE_TSSOP14

7

D25

21

RB751V_SOD323
R462

1 2

100K_0402_5%

1U_0603_10V4Z

C632

1

2

R471

1 2

100K_0402_5%

C636

0.1U_0402_16V4Z

+3VS

+1.8VS

+RS480_Core

3

14

U40C

P

5

O6I

G

SN74LVC14APWLE_TSSOP14

1

7

2

SLP_S3<42,47>

U38C SN74LVC125APWLE_TSSOP14

I9O

R467

1 2

10K_0402_5%

R463

12

2

1K_0402_5%

R461

2

12

1K_0402_5%

8

OE#

10

Q42
MMBT3904_SOT23

3 1

Q41
MMBT3904_SOT23

3 1

D26

21

RB751V_SOD323

SLP_S3

2

G

12

12

+3VS

12

R469
10K_0402_5%

13

D

2N7002_SOT23
Q43

S

12

R465
47K_0402_5%

J5

SHORT PADS

For EC ATE

R464
100_0402_1%

2

VR_ON <49>

NB_PWR GD <13,18,38>

1

+3VL

12

D29

14

U40D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

A A

7

RB751V_SOD323@

2 1

R482
560K_0402_5%

1

C646

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VL

14

U40F

P

13

O12I

G

SN74LVC14APWLE_TSSOP14

7

2005/03/01 2006/03/11

3

+3VL

14

U40E

P

11

O10I

G

SN74LVC14APWLE_TSSOP14

7

Compal Secret Data

Deciphered Date

VCC1_PWRGD <38>

2

Title

Size Document Number Rev

Custom

Date: Sheet

Power OK

LA-2541

of

1

41 58Friday, April 15, 2005

0.4

A

B

C

D

E

F

G

H

I

J

+5VALW to +5VS Transfer

+5VS+5VALW

1

S

2

S

3

S

4

G

RUNON

C263

0.1U_0402_16V4Z

1

C264

2

0.1U_0402_16V4Z

1

C257

2

10U_0805_10V4Z

SLP_S3

SLP_S3#<19,26,38,40> SLP_S5#<46>

SLP_S3#

100K_0402_5%

SHORT PADS

SLP_S3

R165

J1

2

G

B+

12

12

For EC ATE

13

D

2N7002_SOT23
Q14

S

1

2

1 1

2 2

8
7
6
5

C253

10U_0805_10V4Z

U13

D
D
D
D

SI4800DY_SO8

1

2

VL VL

12

R176
100K_0402_5%

13

D

2N7002_SOT23

2

G

Q13

S

SLP_S5<34,40,48>SLP_S3<41,47>

SLP_S5

SLP_S5#

2

G

12

R175
100K_0402_5%

13

D

2N7002_SOT23
Q12

S

Discharge circuit

FM3

CF9

CF3

1

2

1

CF101CF13

1

1

H16
HOLEA

G

1

+5VS

FM4

12

R174
470_0402_5%

13

D

2N7002_SOT23
Q11

S

CF14

1

H20
HOLEA

1

H9
HOLEA

1

FM51FM6

1

CF2

1

1

H19
HOLEA

1

H10

H14

HOLEA

HOLEA

1

H18
HOLEA

1

1

SLP_S5

H13
HOLEA

1

H17
HOLEA

1

+1.25V

12

R372
470_0402_5%

13

D

2N7002_SOT23

2

G

Q37

S

H4

H6

HOLEA

HOLEA

1

1

H21

H22

HOLEA

HOLEA

1

1

H23
HOLEA

1

2

G

+2.5V

H24
HOLEA

1

12

R373
470_0402_5%

13

D

2N7002_SOT23
Q35

S

+3VALW to +3VS Transfer

2

G

2

G

12

13

D

S

+1.2V_HT

12

13

D

S

R454
470_0402_5%

2N7002_SOT23
Q39

R361
470_0402_5%

2N7002_SOT23
Q33

+3VS+3VALW

1

S

2

S

3

S

4

1

G

2

0.1U_0402_16V4Z

C260

1

C262

2

10U_0805_10V4Z

3 3

1

2

8
7
6
5

C261

10U_0805_10V4Z

U14

D
D
D
D

SI4800DY_SO8

RUNON

4 4

+2.5V to +2.5VS Transfer

+2.5VS+2.5V

C555

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C552

2

U35

S

D

S

D

S

D

G

D

SI4800DY_SO8

RUNON

1
2
3
4

1

2

8
7
6

1

5

C547

2

5 5

10U_0805_10V4Z

SLP_S3

+2.5VS+1.8VS

12

R362
470_0402_5%

13

D

SLP_S3 SLP_S3 SLP_S3 SLP_S5SLP_S3

2N7002_SOT23

2

G

Q34

S

+1.8VALW to +1.8VS Transfer

G

S
S
S

1
2
3
4

21

2

1

+1.8VS+1.8VALW

1

C560

2

0.1U_0402_16V4Z

C553

0.01U_0402_16V7K

1

C557

2

10U_0805_10V4Z

6 6

1

2

7 7

8
7
6
5

C551

10U_0805_10V4Z

RUNON

RB751V_SOD323

U36

D
D
D
D

SI4800DY_SO8

R177

22K_0402_5%
D7

H2
HOLEA

1

H11
HOLEA

1

M1
HOLEA

1

H3
HOLEA

1

H12
HOLEA

1

M2
HOLEA

1

H1
HOLEA

1

2

G

CF6

CF4

+3VS

1

H5
HOLEA

12

13

D

S

FM1

CF8

1

CF12

1

1

R197
470_0402_5%

Q15
2N7002_SOT23

FM2

1

CF5

1

1

CF11

1

1

H8
HOLEA

1

H7
HOLEA

1

CF7

CF1

1

1

1

H15
HOLEA

8 8

A

B

C

D

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2005/03/01 2006/03/11

F

Compal Secret Data

Deciphered Date

G

Title

Size Document Number Rev

Custom

H

Date: Sheet

DC/DC circuit

LA-2541

I

0.4

of

42 58Friday, April 15, 2005

J

A

B

C

D

VIN

PQ58
AO4407_SO8

PQ59

2

G

PR23

1 2

1M_0402_5%

@

VL

@

5

P

+

-

G

2

1
2
3 6

4

12

PR15
200K_0402_5%

PR18
150K_0402_5%

1 2

13

D

RHU002N06_SOT323

S

4

O

12

PD33

1SS355_SOD323

@

1 1

ADP_PRES

12

PR6

PR24

12

1 2

10K_0402_5%

1
3

12

PR34

@

23.7K_0402_1%

PU4 LMV321M7_SC70-5

ACOK <45,50>

2 2

VIN

23.7K_0402_1%

@

PR27

1 2

100K_0402_1%

@

BATT

PR31

100K_0402_1%

@

ACDET

PR35

@

200_0402_1%

VIN

1 2

3 3

12

PR39

100K_0402_1%

12

PR44

1 2

VL

8

PU5A

3

P

+

2

-

G

4

10K_0603_1%

12

PR50
130K_0402_1%

12

12

PR56

PC23

4 4

10K_0402_1%

0.022U_0402_16V7K

1 2

8

5

+

6

-

4

PR60

1 2

33K_0402_1%

4

REF

5

ANODE

PU5B

P

G

LMV431B_SOT23-5

A

8
7

5

CHGCTRL<38,51>

PR37

330K_0402_5%

1

O

LM393M_SO8

PR51
1M_0402_5%

7

O

LM393M_SO8

VL

PU25

CATHODE

NC
NC

P2

ACDRV#

PR28

1 2

140K_0402_1%

3
2
1

8
7

5

ACSET<52>

12

AC_CHG

1.24VREF

PC15

+3VL

PR40

10K_0402_5%

+3VL

PR21

12

2

12

PQ3

AO4407_SO8

1
2
36

4

0_0402_5%

1 2

+3VL

PR32

1 2

191K_0402_1%

0.1U_0603_16V7K

12

PC19

+3VL

1U_0603_6.3V6M

12

PC114

0.1U_0402_10V6K

5

SN74LVC1G17DBVR_SOT23-5

PU24

P

ADP_PRES

O4I

1

NC

G

3

12

PC113

0.1U_0402_10V6K

AC_CHG <51>

PR204

47K_0402_1%

PQ6

@

2

G

RHU002N06_SOT323

P4

0.015_2512_1%

12

AC_CHG

BQ24703VREF

12

PR33

12

PR36

13

D

S

PR16

1 2

PR19
100_0402_1%

ACDET

ALARM

12

43.2K_0402_1%

49.9K_0402_1%

+3VL

12

PR45

4.7K_0402_5%

1 2

PQ9

2

G

P3

PR17

1 2

0.018_2512_1%

1U_0603_6.3V6M

PC13

1 2

PR22

12

1.65K_0402_1%

PR26

12

1K_0402_1%

PR29

12

100K_0402_5%

PC18

4.7U_0805_10V6K

12

PC20

150P_0402_50V8J

ADP_PRES <38,45,51>

PR49

100K_0402_5%

BQ24703VREF

12

PR55
100_0402_5%

13

D

RHU002N06_SOT323

S

B

12

PU3

8

ACN

9

ACP

26

ACDET

5

ENABLE

28

ACSEL

19

ALARM

2

SRSET

3

ACSET
ACPRES27VHSP

13

IBAT

4

VREF

7

COMP

10

NC1

11

NC2

BQ24703_QFN28

12

PR38
150_0402_1%

12

PC21

ALARM <51>

PR20
100_0402_1%

ACDRV#

BATDRV#

BATSET
BATDEP

4.7U_0805_10V6K

P2

1 2

B+

PQ4
AO4407_SO8

1
2
3 6

PR41

3K_0402_5%

8
7

5

4

BATT

B+

12

VCC

PWM#

SRP
SRN

BATP

GND

NC4
NC3

12

PC11

PC12

4.7U_1206_25V6K

ACDRV#

25
22
21
16
15
12
24

18

VS

20
6

1
17
23
14

12

PC14

PR209

1 2

0_0402_5%

B+

1U_0805_50V4Z

0_0402_5%

1 2

PR25

36

578

241

PQ5
AO4407_SO8

PL2

2 1

4.7U_1206_25V6K
PD10

RLZ16B_LL34

1 2

15U_PLC1045P-150A_3.7A_20%

PD11
SKS30-04AT_TSMA

2 1

CV=12.6V(6 CELLS LI-ION)

B+

12

PR42

13.7K_0402_1%

12

PR48
301K_0402_1%

12

PR53
24K_0402_1%

12

PR57

8.87K_0402_1%

D

S

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATT

12

PR46
174K_0603_1%

12

PR52
20K_0402_1%

12

12

PR58

PC22

100P_0402_50V8J

13

G

RHU002N06_SOT323
PQ10

7.87K_0402_1%

2

2005/03/01 2006/03/01

INC.

16.8V(8 CELL LI-ION)

BATT

12

12

12

PQ7

13

D

RHU002N06_SOT323

2

G

S

Compal Secret Data

C

12

Deciphered Date

PR43

13.7K_0402_1%

PR47
301K_0603_0.1%

PR54
24K_0603_0.5%

PR59

8.87K_0402_1%

PR30

0.025_2512_1%

1 2

12

PR207

PC9

3K_0402_1%

1 2

0.1U_0402_16V7K

10.14.2004

D

S

12

13

2

G

BATT

1

12

PC16

2

PR208

3K_0402_1%

4.7U_1206_25V6K

PQ8
RHU002N06_SOT323

CELLSEL# <51>

PC17

10U_1206_25V6M

Icharger=3A
CELLSEL# =0, Vcharger= 12.6V
CELLSEL# =1, Vcharger= 16.8V

Title

Size Document Number Rev

Custom

Date: Sheet

Charger

LA-2541

D

43 57Friday, April 15, 2005

0.4

of

A

B

C

D

E

+3.3V/+5V

B+

1 1

PL3
FBM-L18-453215-900LMA90T_1812

1 2

2 2

B++

1

12

PC26

2200P_0402_50V7K

PC27

2

10U_1206_25V6M

PL4

10UH_D104C-919AS-100M_20%

PQ11

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

AO4912_SO8

12

+5VALWP

VS

1

PR72

+

1 2

PC35

2

150U_D_6.3VM

3 3

10.2K_0402_1%

@

PR75

0_0402_5%

1 2

PR73

47K_0402_5%

12

12

PC36

0.1U_0603_25V7K

0.1U_0603_50V4Z

5HG

8
7
6
5

MAX_LX5<52>

DL5

PC24

1 2

PR62

2.2_0402_5%

1 2

LX5

DH5

2VREF_1999

12

PC40

0.1U_0603_16V7K

RHU002N06_SOT323

PR63
0_0402_5%

1 2

BST5A

1 2

0_0402_5%@
PR74

1 2

PR301

1 2

0_0402_5%

MAINPWON <6,45,50>

VL

12

PR61
499K_0402_1%

13

D

PQ13

S

PC33

PR217
0_0402_5%

2VREF_1999

12

12

2

G

13

D

S

3

1

4.7_1206_5%

VL

12

4.7U_0805_10V4Z

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

PC38

0.22U_0603_10V7K

+3VL

PR79
100K_0402_5%

RHU002N06_SOT323

PQ14

2

G

2

PD12
CHP202U_SC70

VS

12

PR65

12

PC31

4.7U_1206_25V6K

12

PC34

20

18

V+

LD05

PU6

MAX1999EEI_QSOP28

GND

23

25

12

PC39

4.7U_0805_10V4Z

VL

PR64

1 2

47_0402_5%

12

0.1U_0603_50V4Z

13

17

5

VCC

TON

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

LDO3

10

+3VLP

1 2

KBC_PWR_ON <38>

12

2VREF_1999

PC32

1U_0805_16V7K

PR77
0_0402_5%

BST3BBST5B

PC28

0.1U_0603_16V7K

PR67

1 2

200K_0402_1%

PR70

1 2

499K_0402_1%

+3VLP

1 2

1 2

PR68

200K_0402_1%

PR71

499K_0402_1%

1 2

BST3A

PJ1

2 1

PAD-OPEN 2x2m

PC25

0.1U_0603_50V4Z

1 2

PR66
0_0402_5%

DH3

B++

12

PC29

0_0402_5%

2200P_0402_50V7K

PR69

12

PC30

4.7U_1206_25V6K

1 2

PQ12

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

3HG

LX3

DL3

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

12

PL5

10UH_D104C-919AS-100M_20%

+3VALWP

1 2

1 2

PR76

3.57K_0402_1%@

PR78

0_0402_5%

1

+

PC37
150U_D_6.3VM

2

+3VL

12

J7

NO SHORT PADS

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

3.3V / 5V
LA-2541

0.4

of

44 57Friday, April 15, 2005

E

A

B

C

D

PCN1

123

3

1 1

4

SINGATRON_2DC_S736I201

2 2

VL

1

ADPIN

2

4

EC10QS04_SOD106@

PR8
100K_0402_5%

1 2

PD1

PC1

100P_0402_50V8J

12

FBM-L18-453215-900LMA90T_1812

12

12

PR9
1M_0402_1%

12

VS

PR219

ACOK<43,50>

MAINPWON,44,50>

3 3

1 2

0_0402_5%@

PD6

2
3

RB715F_SOT323

8

PC7

0.1U_0603_16V7K

PU1A

1

LM393M_SO8

VL

O

4

PR14
10K_0402_5%

P

+

G

1

12

PL1

1 2

PC2
1000P_0402_50V7K

3
2

-

12

12

12

PC8

13

D

PQ1

1000P_0402_50V7K

S

RHU002N06_SOT323

12

PC3

100P_0402_50V8J

PR11
220K_0402_1%

2

G

13

PC4

B+

12

PR10
200K_0402_1%

12

PR12

PR13

1 2

47K_0402_5%

12

1000P_0402_50V7K

12

301K_0402_1%

+5VALW

2

PQ2
DTC115EUA_SC70

12

PC6

1500P_0402_50V7K

ADP_PRES <38,43,51>

PR1
10K_0402_5%

VMB_A

VMB_B

PD2

12

1N4148_SOD80

PD4

12

1N4148_SOD80

PR7

1 2

47_1206_5%

PR4

47_1206_5%

VIN

12

PD5
1N4148_SOD80

1 2

12

PC5

0.1U_0603_50V4Z

1 2

1 2

1 2

VS

PR2

1.5K_1206_5%

PR3

1.5K_1206_5%

1.5K_1206_5%
PR5

PD3

12

1N4148_SOD80

P4

VIN

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

DCIN / Pre-Charge

LA-2541

D

45 57Friday, April 15 , 2005

of

0.4

5

D D

4

1

12

PC42
10U_1206_25V6M

PC41

2

2200P_0402_50V7K

@

1 2

3

PR80
51_1206_5%

+5VALWP

2

B+++

PL6

12

FBM-L11-322513-151LMAT_1210

1

B+

0.01U_0402_16V7K

17

23

1 2

PR83

0_0402_5%

24
25

22
27

26

20
19
21
16

18

PC44

12

2.2U_0805_10V6K

PC48

12

1 2

PR87

2.74K_0402_1%

12

12

PR94

57.6K_0402_1%

PC50

0.1U_0603_25V7K

PR85

2.2_0402_5%

12

12

12

PR212
0_0402_5%

1 2

0_0402_5%

PR140

PC45

2200P_0402_50V7K @

PQ17

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

12

S1/A

D2
D2
G1

1
2
3
4

12

PD44

RB751V_SOD323

PR213
33_0402_5%

1 2

PL8

3.3UH_PLFC0745P-3R3A_30%

1 2

+3VALWP

+1.8VALWP

Iimit=(10.3-8uA*Rimit)*(Rsense+140)/(Rsense*Rds)

Rsense=2K,RILM=107K,Rds(on) tpy.=19.7mΩ,Max=24mΩ.
Iimit Min=9.6/107K*(100+2K)/(24mΩ*1.3)=6.0388A
Iimit Max=9.6/107K*(100+2K)/19.7mΩ=9.564A
+VCCP O.C.P. = 6.038A ~ 9.564A

PC46

4.7U_1206_25V6K

12

PC55

0.01U_0402_16V7K

@

PC58

1000P_0402_50V7K

12

12

12

PR92
10K_0402_1%

PR88

10K_0402_1%

+1.8VALWP

1

+

PC53

2

220U_D2_4VM

PC54

1 2

4.7U_0805_6.3V6K

1

PD13

CHP202U_SC70

PQ16

1

D2

2

D2

3

C C

+2.5VP

1

12

+

PC52

B B

PC51

2

4.7U_0805_6.3V6K

PR89

18.2K_0402_1%

PR91

10K_0402_1%

PL7

4.7UH_PLFC1045P-4R7A_5.5A_30%

220U_D2_4VM

12

12

PC56

0.01U_0402_16V7K

12

12

PC57
1000P_0402_50V7K

@

12

G1

4

S1/A

AO4912_SO8

SB_SLP_S5#<19>

PM_RSMRST#<19,38>

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

PC49

0.1U_0603_25V7K

1 2

PR84

2.2_0402_5%

0_0402_5%

PR211

12

12

PR90

10K_0402_5%

PD45

1 2

RB751V_SOD323

3

2

0.01U_0402_16V7K

1 2

12

0_0402_5%

PR86

2.74K_0402_1%

12

SLP_S5# <42>

PC47

12

PR82

12

PR93
91K_0402_1%

12

PC43

0.1U_0603_25V7K

14

PU7

12

SOFT1

BOOT1

UGATE1
PHASE1

ISL6227

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

VIN

GND

1

6

5
4

7
2

3

9

10

8

15
11

PR81

2.2_0402_5%

1 2

28

SOFT2

VCC

BOOT2

UGATE2

PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

OCSET2

DDR

13

ISL6227CA_SSOP28

Iimit=(10.3-8uA*Rimit)*(Rsense+140)/(Rsense*Rds)
Rsense=1K,RILM=51K,Rds(on) tpy.=19.7mΩ,Max=24mΩ.
Iimit Min=9.6/51K*(100+1K)/(24mΩ*1.3)=6.636A
Iimit Max=9.6/51K*(100+1K)/19.7mΩ=10.897A
+VCCP O.C.P. = 6.636A ~ 10.897A

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

2.5VP / 1.8VALWP
LA-2541

1

0.4

of

46 57Friday, April 15, 2005

5

D D

4

SLP_S3<41,42>

3

1 2

0.1U_0402_16V7K@

0_0402_5%

PC64

4.7U_0805_6.3V6K

PR100

PC68

+1.8VALW

2

G

PQ20

12

SN7002N_SOT23

1

PJ11

1

JUMP_43X79

2

2

12

13

D

S

PR99

2K_0402_1%

PR101

10K_0402_1%

12

12

PC66

0.1U_0402_16V7K

2

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

12

+1.5VSP

PC67

4.7U_0805_6.3V6K

12

6
5

NC

7

NC

8

NC

9

TP

+3VS

12

PC65
1U_0603_6.3V6M

1

C C

0_0402_5%

1 2

0.1U_0402_16V7K@

PR104

100K_0402_5%

PR105

PC75

12

13

D

2

G

S

1 2

+5VALW

B B

VGATE<15,41,48,49>

+5VALW

PR103

6.81K_0402_1%

2

G

PQ23
SN7002N_SOT23

1 2

13

D

PQ22
SN7002N_SOT23

S

PR107

10K_0402_1%

12

PC72

470P_0402_50V8J

1 2

5

PU10

7

6

3

VCC

OCSET

FB

GND

APW7057KC-TR_SOP8

PC76

1 2

0.1U_0402_16V7K@

BOOT

UGATE

PHASE

LGATE

12

PC69

PR102

1 2

10_0603_5% @

1U_0603_6.3V6M@

1

2

8

4

PR106

5.11K_0402_1%

1 2

PC77

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K
PC73

PD14

1N4148_SOD80

1 2

12

8
7
6
5

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4912_SO8

PQ21

S1/A

PJ12

2

112

JUMP_43X118

12

1

D2

2

D2

3

G1

4

1

PC70
10U_1206_25V6M

2

PC71

4.7U_1206_25V6K

PL9

3.3UH_PLFC0745P-3R3A_30%

1 2

1

+

2

+5VALW

+1.2V_HTP

1

+

PC74

PC121

2

220U_B2_2.5VM

220U_B2_2.5VM

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

A3

2

Date: Sheet

1.2V_HTP / +1.5V S P
LA-2541

1

0.4

47 57Friday, April 15 , 2005

of

5

4

3

2

1

D D

10U_1206_6.3V7K

PR97

PC305

1U_0603_6.3V6M

1 2

0.1U_0402_16V7K@

1

2

3

12

0_0402_5%

PC63

PC311

0.01U_0402_25V7Z

PU26

FB

SS

VCC

MAX8578

SLP_S5<34,40,42>

C C

STRP_DATA <13>

RHU002N06_SOT323

PQ65

13

PR311

1 2

220K_0402_5%

B B

RHU002N06_SOT323

1,47,49>

A A

PQ64

VGATE

D

2

G

S

VL

12

PR309

10K_0402_5%

PQ63

@

2

G

13

D

2

G

S

VGATE#

5

RHU002N06_SOT323

12

PR314

787_0603_1%

12

PR316

402_0603_1%

12

3300P_0402_50V7K

PC313

+5VS

PR324

1 2

0_0402_5%

13

D

S

12

PC59

PR315

10

OCSET

GND

4

+1.8VALW

12

2

G

PQ19

12

SN7002N_SOT23

PR325
0_0402_5% @

1 2

12

12

4.99K_0402_1%

9

8

DH

EN

7

LX

5

DL

6

BST

PD34

12

1SS355_SOD323

4

PR95

10K_0402_1%

13

D

PR98

10K_0402_1%

S

PR323

1 2

49.9K_0402_1%

PC312

0.1U_0603_16V7K

PR317
0_0402_5%

1 2

4.7_0402_5%

BST_LX

12

1.2V_BST

PC304

+3VALWP +3VALW

PU8

8
7
6
5

12

G2
D1/S2/K
D1/S2/K
D1/S2/K

2
3
4

AO4912_SO8

PC62
10U_1206_6.3V7K

VIN1VCNTL
GND
VREF
VOUT

APL5331KAC-TR_SO8

+1.25VP

PQ62

D2
D2
G1

S1/A

+2.5V

12

12

0.1U_0402_16V7K

VGATE

PR215

1 2

0.1U_0402_10V6K

12

PC61

1.2V_DH

1.2VLX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

1
2
3
4

1.2VDL

6
5

NC

7

NC

8

NC

9

TP

B+

12

PL16
FBM-L11-322513-151LMAT_1210

1

2

PC302

10U_1206_25V6M

1 2

12

PR318

7.32K_0603_1%

0.047U_0603_25V7M

1 2

866_0402_1%

Compal Secret Data

3

+3VALW

12

PC60
1U_0603_6.3V6M

12

PC314

0.1U_0603_25V7K

PL15

3.3UH_PLFC0745P-3R3_4.8A_30%

PC306

1 2

PR214

+5VALWP +5VALW

+2.5VP +2.5V

12

12

1

PR319

30_0402_5%

2

PC308

0.1U_0402_10V6K

Deciphered Date

(5A,200mils ,Via NO.= 10)

(8A,320mils ,Via NO.= 16) (2A,80mils ,Via NO.= 4)

3A,120mils ,Via NO.= 6)

+

PC307

330U_D2E_2.5VM

PJ3

2

112

JUMP_43X118

PJ5

2

112

JUMP_43X118

PJ7

2

112

JUMP_43X118

PJ9

2

112

JUMP_43X118

+RS480_CoreP

12

PR313
10_1206_5%

PQ67

13

D

RHU002N06_SOT323

2

G

S

2

PJ4

+1.8VALWP +1.8VALW

+1.5VSP +1.5VS

(2A,140mils ,Via NO.= 7)

+1.2V_HT+1.2V_HTP

+RS480_CoreP +RS480_Core

VGATE#

Title

Size Docu ment Number Rev

B

Date: Sheet

1.25VP / RS480_Core
LA-2541

2

112

JUMP_43X118

(5A,40mils ,Via NO.= 2)(5A,200mils ,Via NO.= 10)

4A,160mils ,Via NO.= 8)

PJ6

2

JUMP_43X79

PJ8

2

JUMP_43X79

PJ14

2

JUMP_43X118

1

112

112

112

+1.25V+1.25VP

0.4

48 57Friday, April 15, 2005

of

5

4

3

2

1

12

@

1 2

PR123 1.82K_0402_1%

49 57Friday, April 15 , 2005

B+

+CPU_CORE

PR210
10_0402_5%

CPU VCC SENSE

1 2

PC87

1000P_0402_50V7K

@

of

12

PR134

CPU_COREFB

0.4

0_0402_5%

+5VS

+3VS

12

D D

VID0<6>
VID1<6>
VID2<6>
VID3<6>
VID4<6>

VGATE<15,41,47,48>

PR124

C C

VR_ON1>

0_0402_5%

1 2

PR125

1 2

100K_0402_5% @

VCC

PR110 0_0402_5%
PR111 0_0402_5%
PR113 0_0402_5%
PR115 0_0402_5%
PR117 0_0402_5%
PR118 0_0402_5%

1 2

PR119 0_0402_5%

1 2

PR130

71.5K_0402_1%

1 2

PR131

1 2

121K_0402_1%

PR128 200K_0402_1%

12

PR132

1 2

80.6K_0402_1%

PC91 0.22U_0603_16V7K

PC92

100P_0402_50V8J

12

PR109 10K_0402_5%

12
12
12
12
12
12

For EC ATE

PR126

PC89

1 2

270P_0402_50V7K

1 2

PR96 0_0402_5%

REF

PR108 10_0402_5%

PC84
1U_0603_10V6K

1 2

VCC

J2 SHORT PADS

1 2

12

60.4K_0402_1%

REF
ILIM

12

2.2U_0603_6.3V4Z

1

10

VCC

24

D0

23

D1

22

D2

21

D3
D4
OVP
VROK
S0
S1
SHDN#
TIME
CCV
TON
REF
ILIM
OFS
SUS
SKIP
GND

PU11

MAX1544

20
19
25

4
5
6
1

12

2
8
9
7

3
18
11

VDD

BSTM

DHM

LXM
DLM

PGND

CMP
CMN

OAIN+

OAIN-

BSTS

DHS

LXS
DLS

CSP

CSN

GNDS

30
36

V+

26
28
27
29
31
37
38
17
16
15

FB

14

CCI

35
33
34
32
40
39
13

12

PC85

0.01U_0402_50V4Z

PR112

1 2

2.2_0402_5%

FB

1 2

PC90 470P_0402_50V8J

DHS
LXS
DLSREF

GNDS

DHM
LXM

PGND

OAIN+

BSTM

12

PC86

PR114
0_0402_5%

0.22U_0603_16V7K

1 2

DLM

PC300

@

BSTM

12

PQ25

4700P_0402_25V7K

PD16

2

3

CHP202U_SC70

PR135

1 2

2.2_0402_5%

2

PC83

12

PC122

12

@

1 2

1000P_0402_50V7K

PR205
10_0402_5%

PR133

100_0402_5%

CPU_COREFB#

B B

Near CPU GND

A A

12

PC97

0.22U_0603_16V7K

100K_0402_5%@
PR300

1 2

<6>

PC315

12

1000P_0402_50V7K

PC316

12

1000P_0402_50V7K

1 2

OAIN+

OAIN+

OAIN+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

PQ27

IRF7413Z_SO8
PR136

0_0402_5%

PC123

1 2

4700P_0402_25V7K@

Compal Secret Data

Deciphered Date

CPU_B+

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

S1S3G

S

IRF7832_SO8

4

2

PR127 820_0402_5%

1 2

+5VS

1

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

PQ28

S1S3G

S

IRF7832_SO8

4

2

PR138

1 2

820_0402_5%

12

PC78

PQ24

IRF7413Z_SO8

5

S

PQ26

4

2

12

PC93

5

PQ29

IRF7832_SO8

4

2

12

PC79

4.7U_1206_25V6K

4.7U_1206_25V6K

PR206

1 2

100K_0402_5%@

D8D7D6D

PD15

S1S3G

2 1

IRF7832_SO8

CPU_B+

12

12

PC94

PC95

4.7U_1206_25V6K

2200P_0402_50V7K

D8D7D6D

S1S3G

S

2

12

12

PC81

PC80

0.01U_0402_50V4Z

2200P_0402_50V7K

OAIN+

PL11

.56UH_MPC1040LR56_ 23A_20%

1 2

12

PR120

820_0402_5%

PC88

SKS30-04AT_TSMA

1 2

0.47U_0603_16V7K

12

PC96

4.7U_1206_25V6K

0.01U_0402_50V4Z
PL12

.56UH_MPC1040LR56_ 23A_20%

1 2

PR137
820_0402_5%

PD17

2 1

1 2

SKS30-04AT_TSMA

1 2

PC98

0.47U_0603_16V7K

Title

Size Document Number Rev

Custom

Date: Sheet

PL10

FBM-L18-453215-900LMA90T_1812

1 2

PR116

1 2

0.001_2512_5%

12

PR121 499_0402_1%

PR129

1 2

1.82K_0402_1%

PR122 499_0402_1%

+CPU_CORE

LA-2541

1

+

PC82

100U_25V_M

2

12

1

<6>

A

B

C

D

10.13.2004

PCN2

1

1 1

BATT+

SMD
SMC

ID

B/I

GND

TYCO_C-1746706_6P

EC_SMD_A

2

EC_SMC_A

3
4
5

AB/I_A <51>

PR139
330K_0402_5%@

12

6

VMB_A

12

PL13

FBM-L18-453215-900LMA90T_1812

1 2

PC99
1000P_0402_50V7K

12

PC100

0.01U_0402_50V4Z

BATT_A

PH1 near CPU :

PCBA thermal protection at 90 degree C
Recovery at 45 degree C

12

PR141

12

12

100_0402_5%

100_0402_5%

1K_0402_5%

PR151
1K_0402_5%

1 2

3
2

@SM05_SOT23

EC_SMC_B1

EC_SMD_A1
EC_SMC_A1

PR149

PD42

EC_SMD_B1

12

1 2

PR150

210K_0402_1%

1

+3VL

THM_MAIN# <38>

2

3

PD43
@SM24_SOT23

1

AB1A_DATA <38>
AB1A_CLK <38>

VMB_B

PL14

FBM-L18-453215-900LMA90T_1812

1 2

12

PC103
1000P_0402_50V7K

THM_MBAY# <38>

AB1B_DATA <38>
AB1B_CLK <38>

LM393M_SO8

PU12B

@

7

12

PC104

0.01U_0402_50V4Z

ACOK<43,45>

8

P

+

O

-

G

4

BATT_B

5
6

PQ30

PC102

13

D

2

G

S

RHU002N06_SOT323@

12

PR143

PR142

100_0402_5%

2 2

100_0402_5%

PCN3

1

BATT+

SUYIN_20163S-06G1-K

3 3

4 4

SMD
SMC

GND

B/I
TS

EC_SMD_B

2

EC_SMC_B

3

AB/I_B

4

TS_B

5
6

PR154

100_0402_5%

12

PR155

VL

PR145

8

5

P

+

6

-

G

4

PR147

150K_0402_1%

47K_0402_1%

1 2

PU1B

7

O

LM393M_SO8

VL

12

PQ15

2

G

13

D

RHU002N06_SOT323

S

MAINPWON <6,44,45>

12

PH1

PR146

10K_TH11-3H103FT_0603_1%

15K_0402_1%

1 2

12

2.55K_0603_1%

12

PC101

1000P_0402_50V7K

12

PR148
150K_0402_1%

12

PR144

0.22U_0402_10V4Z

+5VALWP

12

PR152
10K_0402_5%

@

12

PC106

@

0.1U_0603_16V7K

PU12A

1

LM393M_SO8

PR153

499K_0402_1%@

1 2

8

O

4

@

VS

12

PC105

@

0.01U_0402_50V4Z

3

P

+

2

-

G

PR157

10K_0402_1%@

1 2

12

VL

PC107

1000P_0402_50V7K

@

BATT

12

@

12

@

12

@

PR156
499K_0402_1%

PR158
365K_0603_1%

PR159
499K_0402_1%

PQ31

13

D

2

G

RHU002N06_SOT323@

S

CFET_B<51>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

BATTERY CONN / OTP

LA-2541

D

50 57Friday, April 15 , 2005

of

0.4

A

B

C

D

+3VL

1 1

+3VL

BATSELB_A

BATSELB_A#

2 2

PC109

1 2

1000P_0402_50V7K

PC111

1 2

1000P_0402_50V7K

PQ34

PR164

1 2

22K_0402_5%

1 2

PR165

22K_0402_5%

PQ35

RHU002N06_SOT323

2

G

2

G

1 2

13

D

RHU002N06_SOT323

S

13

D

S

ALARM<43>

PR163

47K_0402_5%

RHU002N06_SOT323

PQ37

13

D

S

1
2

2

G

5

PU14

P

INB

4

O

INA

G

74LVC1G02_04_SOT353

3

+3VL

1

5

P

NC

A2Y

G

3

ADP_PRES <38,43,45>

1

INB

2

INA

PU15

4

SN74LVC1G14DCKR_SC70-5~D

+3VL

5

1

PU18

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5~D

3

PR169

10K_0402_1%

1 2

RHU002N06_SOT323

S

ADP_PRES

BATCON <38>

CELLSEL#<43>

BATSELB_A

PQ41

D

13

G

2

PR170

1 2

220K_0402_5%

BATSELB_A#

12

PC317

+3VL

220P_0402_50V7K

12

PR175
100K_0402_5%

CELLSEL#

13

D

PQ47

2

G

S

RHU002N06_SOT323

2

470K_0402_5%

BATSELB_A#

+3VL

5

SN74LVC1G17DBVR_SOT23-5

PU16

P

O4I

1

NC

G

3

AC_CHG<43>

BATSELB_A#<38>

3 3

CHGCTRL38,43>

PD22

12

1N4148_SOD80

12

PC112

PR168

1 2

0.22U_0402_10V4Z

+3VL

PD27

CFET_A

2
3

RB715F_SOT323

1

12

4 4

CFET_B

2

PR216
100K_0402_5%

5

PU20

P

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

AB/I_A<50>

A

B

12

PC108

5

PU13

P

4

O

G

74LVC1G02_04_SOT353

3

+3VL

PU17

5

1

P

IN1

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

+3VL

PU19

5

1

P

IN1

O

2

IN2

G

3

SN74AHC1G08DCKR_SC70

PQ53
RHU002N06_SOT323

13

D

2

G

S

0.1U_0402_10V6K

BATT_B

RHU002N06_SOT323

LATCH

+3VL

BATT_A

PD18

2

1

3

PQ33

S

G

RB715F_SOT323

D

13

2

PR160

1 2

100_0402_5%

12

PC110

RHU002N06_SOT323

12

PR162

1.5M_0402_5%

0.01U_0402_16V7K

BATT

12

PR166
470K_0402_5%

1

C

PQ39

2

B

E

3

PD23

1 2

1N4148_SOD80

RHU002N06_SOT323

12

PR177
470K_0402_5%

C

PQ48

2

B

E

12

PD26

1 2

1N4148_SOD80

13

D

RHU002N06_SOT323

S

HMBT2222A_SOT23

1

3

4

4

PR173

1 2

10K_0402_5%

PQ52

BATT_IN

RHU002N06_SOT323

PR181

1 2

10K_0402_5%

CFET_A

2

G

12

PR171

10K_0402_5%

13

D

PQ42

2

G

S

13

D

S

BATT

PR180

10K_0402_5%

PQ49

2

G

CFET_B<50>

PQ36

13

2

G

D

RHU002N06_SOT323

S

BATT_IN

CFET_ABATT_IN

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

Compal Secret Data

INC.

HMBT2222A_SOT23

C

PR167
470K_0402_5%

1 2

PR178

1 2

470K_0402_5%

Deciphered Date

PQ32

D

S

1 3

1 2

G

2

PD24

21

B540C_SMC
PQ43

AO4407_SO8

1
2
3 6

4

PQ45

AO4407_SO8

1
2
3 6

4

PD25

21

B540C_SMC

PR161

0_0402_5%

PD21
RLZ6.2C_LL34

2 1

RHU002N06_SOT323

BATT_IN

RHU002N06_SOT323

8

8

7

7

5

5

8

8

7

7

5

5

RHU002N06_SOT323

RHU002N06_SOT323

BATT_IN

PD20
1SS355_SOD323

1 2

PQ38

13

D

2

G

S

PQ40

13

D

12

S

1
2
36

PR172

4.7K_0402_5%

12

PR174
470K_0402_5%

BATT_A

PQ44
AO4407_SO8

2

G

4

PQ46
AO4407_SO8

4

PQ50

2

G

PQ51

BATT_IN

2

G

Size Document Number Rev

Custom

Date: Sheet

12

1
2
36

PR176
470K_0402_5%

BATT_B

12

PR179

4.7K_0402_5%

13

D

S

13

D

S

Title

Charger

LA-2541

D

0.4

of

51 57Friday, April 15, 2005

5

D D

4

3

2

1

RB751V_SOD323

1 2

PD31

1SS355_SOD323 @

PD32

1SS355_SOD323@

12

PC119

1U_0805_16V7K

+5VS

+

-

1 2

8

P

0

G

LM358A_SO8

4

PR184

100K_0402_5%

1

1 2

PR192
1M_0603_1%

1 2

PR195

36.5K_0402_1%@

1 2

12

2

G

+5VS

12

12

PR193

13

D

S

PR183

133K_0402_1%

80.6K_0402_1%

PU22A

3
2

PC118

1 2

0.1U_0402_16V7K

PR199

1 2

0_0402_5%

PQ56
RHU002N06_SOT323

PU21A

8

3

P

+

1

0

2

-

LM358A_SO8

PR186

0_0402_5%

1 2

C C

B B

G

4

PR185

12

0_0402_5%

B+

P4

1 2

10K_0402_1%

12

PC120

12

1 2

PR189

0.01U_0402_16V7K

PR202
0_0402_5%

PR187

1K_0402_1%

1 2

PR194

100K_0603_0.5%

4

REF

CATHODE

5

ANODE

LMV431ACMX5_SOT23-5

PU21B

5

+

6

-

1 2

PC117

2200P_0402_50V7K

PU23

3
2

NC

1

NC

7

0

LM358A_SO8

12

12

MMBT3906_SOT23

PR196
909_0402_1%

PR198
10K_0603_0.1%

PQ54

PR322
100K_0402_5%

1 2

12

PR191

10K_0402_5%

E

3

B

2

C

1

PR320

1 2

39K_0603_1%

PR321

1 2

12K_0603_5%

2

PU22B

5

+

7

0

6

-

LM358A_SO8

ACSET <43> OCP# <19>

G

PR201

1 2

237K_0402_1%

13

D

PQ57
RHU002N06_SOT323

S

PR203

1 2

10K_0402_5%

PD29

RB751V_SOD323

PD30

1 2

12

PC116

12

PR197
10_0402_5%

+5VS

1U_0805_16V7K

MAX_LX5 <44>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

System OCP throttle

LA-2541

1

0.4

52 57Friday, April 15 , 2005

of

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Item Issue DescriptionDate

D D

1

41

2

41 CHARGER

CHARGER 08/17/2004

(DB)

08/17/2004
(DB)

Owner

HP

The reason for the change is reslove the
timing diff between two compatator for AC detect

add PQ33

Change PR16 to 15m ohm ,change PR17 to 18m ohm
change PR30 to 25m ohm.
add PR207,PR208,PC9

3

41

4

5 48 Battery CONN

C C

46 RS480_Core

CHARGER

645

7 46 RS480_Core

8 50 Battery Selector

9 2.5V

45

10 51 OCP

08/26/2004
(DB)

10/14/2004
(SI-1)

10/14/2004
(SI-1)

11/1/2004
(SI-1)

12/27/2004
(SI2)

12/27/2004
(SI2)
12/27/2004
(SI2)

2/21/2005
(PV)

HP

HP

HP

To implement PS480 power play

To change main battery CONN. pin define for supporting
NiMH battery (10/20-Cancel the design change,don't support the NiMH battery)

HP

To add 1.8VALWP discharge circuit

HP To set RS480_Core(1.0V) from 1.04V to 1.0V Change PR314 from 750ohm to 787ohm ,

HP

HP

To change the work mode of OCP function

add a PC113 4.7uF cap for +3VL and
add PC114 a 4.7uF cap for VL.
Both caps can be non-installed

add PU26(MAX8576),PQ62(AO4912),PL15,PC307,

add PD44,PR2131.8VALWP

PR316 from 255ohm to 402ohm

Add PR216 (100k) to connect PU20 pin2

add PD45HW

Remove PR182,PR188,PR190,PR200,PQ55
add PR320,PR321,PR322

Solution Description Rev.Page# Title

DB

DB

DB

SI

SI

SI

SI2

SI2

SI2

PV

Request

B B

11

44 CHARGER

12 Battery Selector

A A

5

4/7/2005
(MV)
4/14/2005
(MV)

HP Airline with travel battery issue

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

2005/03/01 2006/03/01

3

Remove PU4,PD33,PR23,PR24,PR27,PR31,PR34,PR35

add PC317

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

PWR PIR Sheet (1)

LA-2541

1

MV

MV

0.4

of

53 57Friday, April 15, 2005

1

2

3

4

5

Reason for change PAGE Modify ListFixed IssueItem

<93.08.09>

1 1

<93.08.11>

1 codec is the primary codec and must be tied to A C_SDIN0 19, 30 Change A C97_SDI N2 to AC 97_SDIN 0 for COD EC

2

3

Conexant recommendation

This shutdown pin of TPS2211A does not have a internal pullup 26 Add R770 0.1

4

5

6

If +2.5V DDA can be connected to +2.5VS directly, we can save the cost of U4 6 Reserve R772 0.1

7

30 Change R351 and R352 to be zero ohm resistors

6 Connect pin 3(SD#) of U4 to +3VS directly 0. 1AMD recommendation

36 Delete Q79, R384 and R578Driving standby/power LED by STB_LED# pin directly for cost saving. 0.1

23, 24 Add Q85, D50, D51, R773, R774, R775 and C665. Change C403 and C406 from 0.33uF to 1uF 0. 1TI recommendation

M.B. Ver.

0.1

0.1

Connect pin 12 of U12 to PCI_RST#26

8

2 2

9

HP request 27, 28 Change NIC from RTL8110SBL to BCM5788M 0. 1

18 Change R141 from 4.53k 1% to 5.49k 1% 0.1ATI recommendation

33 Reserve C704

18 Add R799, R800, R801 and R802

<93.08.11>
<93.10.18>

10

11

12

re-annotation for process rule 4~30, 32~42 re-annotation for all components, excluding MOM and power components. 0.1

Power saving 5, 8 Change R51, R60, R320 and R326 from 100 ohm to 1K ohm 0.2

23 Change R496 from 150 ohm to 220 ohm

Change R285, R290 and R293 from 150 ohm to 220 ohm; Change R296 from 300 ohm to

36

560 ohm

Delete useless components which were reserved in rev.0.1 7, 13 De lete C233, C523, R321, C409, U30, R234, C293 and U21 0. 2

13

14

3 3

15

16

17

18

19

20

Pin-9(FS2) of U8(Clock gen.) is not a clock output pin. 13 Delete R95, a dd R72. 0.2

Use Link# instead of Activity# for NIC_LINK# function 1 9 Connect U19 .C5 to LAN_LINK# 0.2

CARD_LED is an active high signal 23 Change Q45 from MM BT3906 to MMBT3904 0.2

PETp0 a nd PETn0 should be connected to Tx on the host, PERp0 and PERn0
should be connected to Rx on the host.

26 Sw ap these differential pairs 0.2

Add an inverter bet ween KBRST from KBC(U39) to KBRST# in SB400(U19) 3 8 Add Q46 and R497 0.2

The reset signal(PCI_RST#) for LPC BIOS ROM de-assert too late 3 9 Use NB_RS T#(A_RST# ) instead of PCI_RST# 0 .2

PowerPlay support 13, 14 Add R327, connect U9.E10 to power circuit. Change VDD_CORE of U9 from +1.2V_HT to

VariBright support 13, 38 A dd R499 and R501, reserve R498 and R500 0. 2

+RS480_Core

depopulate R 499 and R501, populate R498 and R500

0.2

21 HP request 19 Add R502 0.2

36 Change Bat_LED to be on +3VL rail

Add R503, R504 and R505

38

4 4

<93.10.21>

1

22 Main battery pin definition change 38 Change the net of U39.76 from THM_MAIN# to KBC_GPIO16; Add R507 0.2

23 Mandatory ATI RS480 Design Change(PA_RS480F1) 11 Change R357 from 1K ohm to 0 ohm, delete R355 and R363 from BOM. 0. 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Delete Q40, add R508(reserved), R509 and Q4715

Deciphered Date

Title

Size Document Number Rev

Custom

4

Date: Sheet

HW PIR Sheet(1)

LA-2541

5

0.4

of

54 58Friday, April 15, 2005

1

2

3

4

5

M.B. Ver.

0.2

<93.10.21>

Reason for change PAGE Modify ListFixed IssueItem

23 ATI Application Note(AN_IXP400AG2) 20 Delete R 216, R217 and R218, pull SATA_X1, PLLVDD_SATA, XTALVDD_ SATA and

AVDD_SATA[8:1] to GND

24 Power team recommendation 16 Change R316 from 22K_+/-5% to 1.8K_+/-1%, Change R315 from 10K_+/-5% to 1K_+/-1% 0.2

1 1

<93.10.26>
<93.11.02>

25 IDE DASP# signal route error 35 Add D32, D33, R510 and R511

0.2

26 To fix USB signal rate failed issue 15 Populate R76 0.2

19 Do not populate C246 and C247 for external 48MHz OSC.

22 Populate R183 and R417, do not populate R418

27 To improve drive strength/Min Bottom Margin for PCIE 18

28

29

ATI Product Advisory(PA_IXP400AC10) 18 Short PJ 13; needn't to popu late U17, R182 and R186; Change C265, C267, C268 and C269

HP request 14 Delete D6

Change R402 from 5.49K ohm to 4.12K ohm 0 .2

back to 0.1uF

15 Popula te R508 and do not populate R509

0.2

0.2

19 Change R382 from 10K ohm to 47K ohm

38

Change R491, R497 and R507 from 10K ohm to 100K ohm

41 Change C636 from 1uF to 0.1uF

2 2

30

31

32

33

<93.11.09>

34

Charge LED show wrong color 3 6 Swap th e net of D16 pin 1 for the net of pin4 0. 2

Once powe r up Conexant CODEC, We got a pop sound issue. We have used SB
GPIO1 to asserted MUTE# for audio amp shutdown to avoided this pop sound.
Unfortunately, GPIO1 will output about 1 .2m second "Hi" pulse once SB get
aux-power, so we can't shutdown amp during this interval. We have to add RC
delay circuit to eliminate this pulse.

32 Change R291 from 10K ohm to 100K ohm, add C655 0.2

MIC can't work 33 Change the power of U34 from +VDDA_CODEC to +5VS 0.2

The gain of MIC amp. is too big 33 Cha nge R136 from 150K ohm to 100K ohm 0. 2

HP request 13

Change L23~L25 from FBM-L10-160808-800LMT to HLC0603CSCCR11JT; Change L26~L28
from 0 ohm to HLC0603CSCC39NJT

0.2

35 To improve overshoot for PCI clock 18 Change R410, R414, R181, R179, R420, R424 and R423 from 22 ohm to 39 ohm 0.2

36

3 3

37

38

39

<93.11.12>

40

41

<93.11.17>

42

43 HP request for microphone and audio

4 4

To improv e RTC accuracy 18 C hange C250 and C251 from 12pF to 18pF 0 .2

Broadcom recommendation 27

Add R513 and reserve R512 for BCM4401; Change R313 from 1K ohm to 0 ohm for
BCM5788M; Reserve C656~C659

28 Populate C35 for both BCM5788M and BCM4401

0.2

To improve background noise for microphone 33 Add L43, C660 and R514 0.2

To fix wh ite scree n issue after pressing Ctl+Alt+ Del to restart 13 A dd R 515 0.2

HP request

32

315, and 312 from 470pF to 220pF but still reserved only

0.2

Change C356 and C355 from 0.47uF (X7R 10%) to 0.047uF (X7R 10%); Change C320, 318,

16Add Lid switch control from HW side Add D34 0.2

change PCIRST# to NB_RST#

35

37

0.2

38

32

Add D35

33

Add L44,C661,R516

Change R376 to 14K

0.2

Change U34 to TLC2462

Change R136 to 150K

44 reserve for new card clock request 26

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

reserve Q48

Deciphered Date

0.2

Title

Size Document Number Rev

Custom

4

Date: Sheet

HW PIR Sheet (2)

LA-2541

5

0.4

of

55 58Friday, April 15, 2005

1

2

3

4

5

Fixed Issue

<93.11.18>

<93.12.23>

1 1

45 HP request 18 Add R518 and R519

46 Remove unused component

Reason for change PAGE Modi fy ListItem

16 Add R517

18 Del U17,R182,R186

19 De l R139

33

Del L43

47 Fixed ENVDD pulse when power on 13 Add R521

48 Fixed V,VS,SLP_S3 and SLPS5 pulse when ALWS apply

19

Add U12 (AND gate)

42 Pu ll high R175 and R176 to VL

Change U23 from 7411 to 761149 Support Smart Card 2 3,25

M.B. Ver.

0.2

0.3

0.3

0.3

0.3

U23 pin k7 pull high to +5VS

50

Reserve U41 (Quick switch)Support XD 1.2 23,25

0.3

Add R522,R523,R524,R525,R526,R527

51 Improve LAN performance

2 2

<93.12.29>

<94.01.07>

52 Reserve ESD diode on external MIC and speaker connector 32 Reseve D36,D37

53

Remove unused component

27

28

33 Reserve D38

18 De l PJ13,U17,R186,R182 (Modify net name from +1.9VS to +1.8VS)

Change R29 to 1.21K

Change U7 to PULSE_H5007

Del R103,R104,R106,R107 (10K 0402 5%)

2

0.3

0.3

0.3

19 Del R150,Y4,C246,C247,C248,C248,C249,Y3,R151,U37,R394

38 Del R520,C662,R505,R501,R503,R504

Reserve ESD diode on USB port54 34 Rese rve D39,D40,D41

0.3

55 For TI request 23, 25 Del R522,R523,R524 (on quick switch)

0.3

Change R452 to 2.2K

Change JP25,pin5 net name to CB_SDWP#_SMCE#

Change JP25 ,pin10 net nam e to CB_MSBS_SDCMD_SMWE#

3 3

Change JP25 ,pin13 net nam e to CB_MSBS_SDCMD_SMWE#

Reserve R531

Add R53 2 on net CLK_48M_CB for 7611

Add R53 3 on net CLK_48M_CB for 4510

Add R534 for 4510

<94.01.10>

56 0.3

For TI request 2 3,25 Add R535

Del R452

Add R536,R537,R538,R539,R540

Del R453

<94.01.13>

57 For MS ca rd issue 25 Del Q19

Add R544,Q50,R543R545

0.3

Reserve U42,Q49,R542,R541,C687,R546

58 For HP recommand 04 Cha nge R336 to 1.2K 0402 5%

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

18 Change R398 and R400 to 1.2K

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Custom

Date: Sheet

HW PIR Sheet (3)

LA-2541

5

0.3

0.4

of

56 58Friday, April 15, 2005

1

2

3

4

5

Reason for change PAGE Modify ListFixed IssueItem

<94.02.24>

59 Change RP8,RP11,RP14~RP17,RP20,RP23,RP24,RP27,RP36,RP37,RP40,RP43,RP44,RP47,RP48

Improve EMI issue on DDR data bus 8

,RP51,RP53,RP56 from 10Ω to 39Ω

60 For S3,S4 resume issue 1318Change L34 from FBML10160808121LMT bead to 150Ω 1% resistor

1 1

61

Support HW throttling (OCP) 19 Change U19. C6 NET NAME from THERM_SCI to OCP#

61 Can't detect Nee card when warm boot

19,29

Change C268,C269,C265,C267 from 0.1u to 0.01u

Change U19.B6 NETNAME from OCP# to THERM_SCI

19

19 Change MINIPCI_DIS# NETNAME to NEWCARD_RST

Del R395 and R530

19

Change R149 from pull high to pull down

19

Change MINI PCI_RST# N ETNAME to PCI_RST#

26

Add Q51

62 Modify LED brightness 3 6 Change R285 from 220Ω to 68Ω

63 Remove unused component and footprint 28 Del R303,Q25,Q26

M.B. Ver.

0.4

0.4

0.4

0.4

0.4

0.4

Del R47838

2 2

<94.03.07>

64 Connect Mini PCI clamp to GND 2 9 Connect JP11.127 and JP11.128 to GND 0.4

65 Remove unused footprint 15 Del R62,R63,R77

66 Fixed ATI SB400 32.576MHz RTC accuracy issue 18 Change Y5 to EPSON 12.5P 20ppm crystal

0.4

0.4

67 Modem time drift issue 30 Change C363 and C367 to 15PF 0.4

<94.03.09>

68 Separate Cardreader SM_XD power rail 25 Del U42,R545,R546 0.4

Add R546,R547,Q56,D41,D42

69 Change SB 14.318MHz from NB to clock gen

70

3 3

71

72

73

Change clock gen 14.318MHz driving method 15 Let Clock gen p in 54 only drive 14.318MHz to SB

Strap on SB400 PCICLK2 redefine. 2 5 Pop R180 and unpup R183

For ATI recommand to modify PCIE driving strength 1 2 Change R121 to 8.25KΩ, R120 to 82.5Ω

For ATI recommand 19 Let SB SUS_STAT# NC

13 Dele te R67 fo otprint and let NB OSCOUT pin NC.

19 Delete R529 footprint ,connect SB 14.318MHz from clock gen

Let Clock gen pin 53 dr ive 14.318MHz to Super IO and KBC

0.4

0.4

0.4

0.4

0.4

13 NB SUS_STAT# pull high to 1.8VS, R360 change to 4.7KΩ, R364 change to 470KΩ

74 Reserve USB ESD diode footprint

Reserve resistor footprint between A_ground and D_grou nd for ESD concern

75 Broadcom 5788M version change 27 Change 5788M from revA3 to revA5

76 TI 7611 version change 23 Change T I 7611 from revA to revC

34 Reserve D39 and D40 footprint

30 Reserve R548,R549,R550,R551,R552 footprint

0.4

0.4

0.4

77 Amber LED change for HP request 36 Change D16 t o 19-22UYSYGC/S530-A2/TR8 19X16 G/Y 0.4

78 Layout sp ace save 1 8 Add RP68,RP69

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Del R449,R210,R211,R450,R446,R447,R212,R220

Deciphered Date

4

Title

Size Document Number Rev

Custom

Date: Sheet

HW PIR Sheet (4)

LA-2541

5

of

57 58Friday, April 15, 2005

0.4

1

2

3

4

5

Reason for change PAGE Modify ListFixed IssueItem

<94.04.11>

79

80

1 1

81 For Sandisk MS pro 512MB card issue 23 Change R209,R224,R536,R537,R538,R539,R540 to 0 ohm 0. 5

82 For insert MS card shut down issue

DDR memtest failed 8 Change RP8,RP11,RP14~RP17,RP20,RP23,RP24,RP27,RP36,RP37,RP40,RP43,RP44,RP47,RP48

,RP51,RP53,RP56 from 39Ω to 10Ω

Workaround for S3 resume failed 19 Reserve U43 and add R554 0.5

25 Reserve U42,R553 and add C690

M.B. Ver.

0.5

0.5

Change Cardreader socket pin 45,46 to N.C.

Change Cardreader socket pin 1 to GND

83 For SM card detect abnormal issue 26 Change cardreader pin30 to GND

0.5

84 Charger and BATT full LED brightness abnormaml 36 Add R555 0.5

85 Improve EMI issue 39 Add C689

86 Improve internal mic noise 33 Change C235 to 0.047u and C239 to 220p

<94.04.14>

2 2

87 TI recommand 2 3 Reserve R556 (pull down on CARD_LED)

25 Reserve C692,C693,C694 (0.1u cap on card detect pin)

0.5

0.5

88 Improve internal mic noise 33 Change C235 to 0.027u and C239 to 270p

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

4

Date: Sheet

HW PIR Sheet (5)

LA-2541

5

0.4

of

58 58Friday, April 15, 2005