Compal LA-2522 Schematic
5
4
COMPAL CONFIDENTIAL
3
2
1
D D
MODEL NAME :
EGQ00
COMPAL P/N :
PCB NO :
Revision :
C C
2.0
EGQ00 Schematics Document
uFCBGA/uFCPGA Mobile Dothan
ATI RS300MD + SB200
2 Channel DDR1
2005-01-11
REV : 2.0
B B
Function/B
LS-2522
M/B LA-2522
WLAN SW/B
LS-2524
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
TP/B
LS-2523
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
CD-ROM/B
LA-2521
1
152, 18, 2005
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Compal confidential
Block Diagram
D D
CRT CONN.
& TV-OUT
+5VS
+3VS
C C
IDSEL:AD21
(PIRQB#,GNT#0,REQ#0)
TV Module
+3VS
PCI-IF
+2.5VS
+1.5VS
B B
page 24
page 34
3.3V 33MHz
IDSEL:AD20
(PIRQA/B/C/D#,GNT#2,REQ#2)
FAN
+5VS
page 39
INVPWR_B+
+3VS
(PIRQB#)
+VGA_CORE
+3VS
+2.5VS
+1.8VS
IDSEL:AD18
(PIRQC/D#,GNT#3,REQ#3)
MINI PCI
+5VS
+3VS
CardBus Controller
R5C842
+3V
1394
conn.
page 31
Card bus
2 Slot
page 32
CPU Thermal
ADM1032AR
+3VS
page 6
LCD Panel
17" WXGA
page 23
2 Back Light Type
AGP VGA
ATI M11P
page 17,18,19,20
VRAM
64MB/128MB
+2.5VS
page 21,22
page 33
PC Card Type II x1
AGP 8X
PCI BUS
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
10/100 LAN Ctrl.
RTL8100CL
page 31,32 page 30
SDIO
page 32
SD/MS/xD
Combo Slot
+3V
Transformer
& RJ45
page 30
3.3V 33MHz
uFCPGA CPU
+VCCP (1.05V)
+VCC_CORE
+3V
+3VS
HA#(3..31)
(PIRQA#)
+3VS
+2.5V
+2.5VS
+1.8VS
+1.5VS
System Bus
ATi RS300MD
A-Link
3.3V
66MHz
+5VALW
+3VALW
+3V
+3VS
+2.5V
+2.5VS
LPC BUS
3.3V 33MHz
Dothan
478pin
400 / 533MHz
868 u-BGA
page 9,10,11,12
ATi IXP150
457 BGA
page 25,26,27,28
page 6,7,8
HD#(0..63)
48MHz / 480Mb
2.5V 333MHz
Channel A
Channel B
AC-LINK
3.3V 24.576MHz
Secondary ATA100
Primary ATA100
+5VS +5VS
CPU ITP Pad
+VCCP
page 6
Memory BUS(DDR1)
Dual Channel
+2.5V
+1.25VS
HDD
page 29 page 29
LS-2521
USBPORT 0
X BUS
A A
ROM BIOS
SST39VF080
SST39VF040
+3VALW
page 38
Touch Pad
+5VS
5
4
page 39
+3VALW
+5VALW
ENE
KB910
page 37
USB2.0
2 port right side
3 port rear side
Int.KBD
page 39
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+5VS
3
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
Clock Generator
ICS951402AGT
ICS9P750
+3VS
+2.5VS
DDR-DIMM 1
BANK 0, 1
DDR-DIMM 2
BANK 2, 3
page 13,14,15
CDROM
CIR
+5VALW
JUSBP1
JUSBP2
JUSBP3
JUSBP4
JUSBP5
CIR
LS-2521
page 42
page 42
page 42
page 42
page 42
page 29
2
page 16
MDC
+5VS
+3V
page 33
AC97 CODEC
AD1981B
+5VS
+3V
AMP &
Phone/MIC Jack
+12VS
3 direction
UP/DOWN/MUTE
Title
Size Document Number Rev
Date: Sheet
page 35
page 36
星期五 二月
WLAN SW
+3V
+5VS
LS-2524
Fan Control X1
+5VS
FUNCTION/B
Touch-Motion
SW/LED
LS-2522
T/P BD
LS-2523
DC IN
CHARGER
+5VALWP/+3VALWP
1.8VP/1.05VP(+VCCP)
+1.5V
+1.15VS(VDD_CORE)
+12VP/+2.5VSP
+1.25VSP
CPU_CORE
BATT IN
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
252, 18, 2005
1
page 39
page 39
page 39
page 39
page 45
page 46
page 47
page 48
page 49
page 50
page 51
page 52
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of
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I2C / SMBUS ADDRESSING
D D
External PCI Devices
NB RS300MD A
VGA M11P A
A-LINK
AGP-PCI
TV Module
CARD BUS
R5C842
Card Socket A
Card Socket B
1394
Cardreader
LAN RT8100CL
IDSEL # PIRQREQ/GNT #DEVICE
AD21
AD20
AD19
0
2
1
B
A
B
C
D
D
Power Managment table
Signal
State
S0
S1
S3
+12VALW
+3VALW
+5VALW
ON
+12V
+5V
+3V
+2.5V
ON ON
ON ON ON
ON ON
+CPU_CORE
+VCCP
+5VS
+3VS
+2.5VS
+1.8VS
+1.25VS
+1.5VS
OFF
Bringup-Build
SST-Build
EVT-Build
DVT-Build
PVT-Build
PCB Rev
0.1
Data
Wireless LAN(MINI PCI) AD18 3 C,D
S5 S4/AC
S5 S4/AC don't exist
C C
Symbol note:
:means digital ground.
:means analog ground.
:means reserved.@
Ceramic Capacitor Spec
Guide:
Temperature Characteristics:
Symbol
0
CODE
Z5U
8
NP0 SH
H
UK
UJ
9
C0G
I
1
Z5V
A
J
SL
ON OFF
OFF OFF OFF
2
Z5P
B
BJ
3
Y5U
C
CH
4
5
Y5V Y5P
E
D
CK
CJ
X5R
OFF
SCHEMATICS VERSION LIST
VERSION ISSUE DATE REMARK
0.0A
7
6
X7R
F
G
SJ
First Release
Tolerance:
F
+-2%
CODE
A
+-0.05PF
B B
Symbol
B
+-0.1PF
C
+-0.25PF
D
+-0.5PF +-1PF
H
G
+-3%
J
+-5%
M
+-20%
N
+-30%
+100,-0%
+30,-10%
V
+20,-10%
+40,-20%
KQ
+-10%
X
Z
+80,-20%
P
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
ICH_SMBCLK
A A
ICH_SMBDATA
LCD_DDCCLK
LCD_DDCDATA
ENE KB910
ENE KB910
ICH6-M
ATi M22
5
INVERTER BATT
SERIAL SENSOR
EEPROM
THERMAL
(CPU)
4
SODIMM CLK CHIP
MINI PCI
LCD
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
05
352, 18, 20
1
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D D
ADAPTER
B+
+5VALWP
PJP4
PJP7
PJP1
+3VALWP
MAX1999EEI
page 44
+5VALW
page 42
+3VALW
page 42
SYSON
RUNON
SYSON
RUNON
BATTERY
+12VP
C C
SI4835DY
page 47
PJP2
+12V
page 42
VR_ON
+CPU_CORE
MAX1532
+5VS
B B
+3V
page 48
SUSP#
+2.5VS
+1.5VSP
ISL6227BCA
PJP8
page 41
+5VS
page 41
+3V
page 41
+3VS
page 41
+12VS
page 41
+2.5VP
PJP21
CBS_AVCC
CBS_BVCC
R5334V-E2-FB
RUNON
+1.8VSP
APL1085UC-TR
SYSON
page 45
PJP11+12VS
SUSP
page 32
PJP3
page 46
+5VS
VGA_COREP
FAN5234QSCX
+VGA_CORE
+1.8VS
page 46
PJP12
page 42
page 42
+5V
L34
+5VS
(HDD)
page 29 page 29
A A
+5VS
(CD)
5
+VDDA
S19182DH-AD
page 37
+LAN_IO
page 30
4
SD_EN
+SD_VCC
RT9701-CB
page 32
+1.5VS
page 42 page 42
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+2.5V
+2.5VS
page 41
2
+1.25VSP
APL5331KAC
page 47
+VCCPP
APL5331KAC
page 47
PJP8
PJP5
PJP10
Title
Size Document Number Rev
星期五 二月
Date: Sheet
+1.25VS
page 42
+VCCP
page 42
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
452, 18, 2005
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SMCLK
SB200
D D
page 26
SMDATA
+3VS
CLK GEN.
page 16
DIMM0
page 13
DIMM1
page 14
C C
SMB_EC_CK1
SIO
SMB_EC_DA1 +5VALW
BATTERY
page 49
KB910 B4
SMB_EC_CK2
+5VALWSMB_EC_DA2
B B
page 40
CPU
THERMAL
page 6
DDC3CLK
VGA
ATi M11
page 17
A A
5
DDC3DATA
4
+3VS
THERMAL
page 20
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
552, 18, 2005
1
of
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H_A#[3..31]9
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
D D
H_REQ#[0..4]9
H_ADSTB#09
H_ADSTB#19
C C
CLK_CPU_BCLK16
CLK_CPU_BCLK#16
H_ADS#9
H_BNR#9
H_RS#[0..2]9
+VCCP
H_DBSY#9
H_DPWR#9
H_PWRGOOD25
H_CPUSLP#25
TEST2
TEST1
H_BPRI#9
H_DEFER#9
H_DRDY#9
H_HIT#9
H_HITM#9
H_LOCK#9
H_RESET#9
H_TRDY#9
T25 PAD
T24 PAD
T1 PAD @
R54
R133
R136
330_0402_5%
1 2
@
@
1 2
1K_0402_5%@
1 2
1K_0402_5%@
+VCCP
+VCCP
B B
A A
1 2
R132 200_0402_5%
1 2
R135 56_0402_5%
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CPU_CK_ITP
CPU_CK_ITP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSLP#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
H_PWRGOOD
JCPU1A
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
U3
ADSTB0#
AE5
ADSTB1#
A16
ITP_CLK0
A15
ITP_CLK1
B15
BCLK0
B14
BCLK1
N2
ADS#
L1
BNR#
J3
BPRI#
N4
BR0#
L4
DEFER#
H2
DRDY#
K3
HIT#
K4
HITM#
A4
IERR#
J2
LOCK#
B11
RESET#
H1
RS0#
K1
RS1#
L2
RS2#
M3
TRDY#
C8
BPM0#
B8
BPM1#
A9
BPM2#
C9
BPM3#
A7
DBR#
M2
DBSY#
B7
DPSLP#
G1
DPRSTP#
C19
DPWR#
A10
PRDY#
B10
PREQ#
B17
PROCHOT#
E4
PWRGOOD
A6
SLP#
A13
TCK
C12
TDI
A12
TDO
C5
TEST1
F23
TEST2
C11
TMS
B13
TRST#
B18
THERMDA
A18
THERMDC
C17
THERMTRIP#
FOX_PZ47813-2749-42
Add pullups for PWRGOOD and THERMTRIP per INTEL
5
4
Dothan
ADDR GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
4
DATA GROUP
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
3
Check ITP connector.
H_D#[0..63] 9
H_D#0
A19
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
PM_STPCPU#9,16,25,48
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_A20M# 25
H_FERR# 25
H_IGNNE# 25
H_INIT# 25
H_INTR 25
H_NMI 25
H_STPCLK# 25
H_SMI# 25
R355
470_0402_5%
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_DSTBN#[0..3] 9
H_DSTBP#[0..3] 9
2
12
MMBT3904_SOT23
3
1 2
Q23
3 1
R337
470_0402_5%
2
+VCCP
12
R338
200_0402_5%
Q24
MMBT3904_SOT23
3 1
Test pad as closed as posible
H_DPSLP#
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
H_RESET#
ITP_TCK
CPU_CK_ITP
CPU_CK_ITP#
ITP_TDO
ITP_TRST#
ITP_TMS
ITP_TDI
CPU HOT
CPU Therml Sensor
+VCCP
R254
56_0402_5%
SMB_EC_CK237
SMB_EC_DA237
2
12
12
H_PROCHOT#
+VCCP
R51
@
47K_0402_5%
1 2
C49
0.1U_0603_25V7K@
+VCCP
H_THERMTRIP#
2
R253
56_0402_5%
+CPU_CORE
12
1 2
R64
56_0402_5%
T20PAD@
T19PAD@
T17PAD@
T13PAD@
T15PAD@
T11PAD@
T12PAD@
T9PAD@
T5PAD@
T3PAD@
T4PAD@
T8PAD@
T6PAD@
T10PAD@
T7PAD@
+3VS
12
1
C
2
B
E
3
H_THERMDA
H_THERMDC
SMB_EC_CK2
SMB_EC_DA2
8.2K_0402_5%
+3VS
12
R606
47K_0402_5%
2
B
1
+3V
R131
R234
1K_0402_5%
PROCHOT# 37
Q18
2SC2411K_SC59
+VCCP
+VCCP
150_0402_5%
1 2
R323
54.9_0603_1%
1 2
R324
54.9_0402_1%
R129
56_0402_5%
R322
37.4_0402_1%
1 2
R321
150_0402_5%
1 2
R125
680_0402_5%
1 2
R123
27.4_0402_1%
1 2
1 2
1 2
ITP_DBRESET#
ITP_TDO
H_RESET#
ITP_BPM#5
or 39.4Ohm
ITP_TMS
ITP_TDI
Place near CPU
ITP_TRST#
ITP_TCK
+3VS
1
C494
0.1U_0603_25V7M
1
C489
2200P_0402_50V7K
2
12
12
R249
R247
8.2K_0402_5%
1
C
Q7
E
2SC2411K_SC59
3
Title
Size Document Number Rev
Date: Sheet
U19
2
D+
3
ALERT#
D-
8
THERM#
SCLK
7
SDATA
ADM1032AR_SO8
MAINPWON 42,44,49
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
VDD1
GND
2
1
6
4
5
1
12
R237
10K_0402_5%
652, 18, 2005
C
of
5
4
3
2
1
+CPU_CORE
JCPU1B
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
FOX_PZ47813-2749-42
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
+VCCP
12
R233
56_0402_5%
CPU_BSEL0_RCPU_BSEL1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
B
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
+3VS
12
R236
1K_0402_5%
1
C
Q15
2SC2411K_SC59
E
3
CPU_BSEL0 11,16
2
H_PSI#48
+VCCP
12
R231
56_0402_5%
R111
54.9_0402_1%@
1 2
1 2
R121
54.9_0402_1%@
+VCCP
+CPU_CORE
V_CPU_GTLREF
T22 PAD
T21 PAD
T2 PAD
T18 PAD
T23 PAD
3
VCCSENSE
VSSSENSE
H_PSI#
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
CPU_BSEL0_R
CPU_BSEL1
COMP0
COMP1
COMP2
COMP3
@
@
@
@
@
CPU_BSEL1 11,16
Dothan A = J1 (+1.8VS)
Dothan B = J2 (+1.5VS)
2 1
12
@
R153 10K_0402_5%
+VCCP
4
+1.8VS
+1.5VS
R_A
12
R52
1K_0402_1%
R_B
12
R58
2K_0402_1%
R59
PAD-OPEN 2x2m@
PAD-OPEN 2x2m@
Layout close CPU
Layout Note:
500 mil max length
20 mils
12
R60
27.4_0402_1%
54.9_0402_1%
00: 133 MHZ
10: 100 MHZ
2 1
5 mils
12
D D
For test only ,CMOS output
CPU Voltage ID
CPU_VID048
CPU_VID148
CPU_VID248
C C
CPU_VID348
CPU_VID448
CPU_VID548
R152 0_0402_5%
R154 0_0402_5%
R156 0_0402_5%
R158 0_0402_5%
R161 0_0402_5%
R164 0_0402_5%
MOBILE BANIAS VID TABLE
VoltageVID[5..0]
0 0 0 0 0 0 1.708V
0 0 0 0 0 1 1.692V
0 0 0 0 1 0 1.676V
0 0 0 0 1 1 1.660V
0 0 0 1 0 0 1.644V
0 0 0 1 0 1 1.628V
0 0 0 1 1 0 1.612V
0 0 0 1 1 1 1.596V
0 0 1 0 0 0 1.580V
0 0 1 0 0 1 1.564V
0 0 1 0 1 0 1.548V
B B
A A
0 0 1 0 1 1 1.532V
0 0 1 1 0 0 1.516V
0 0 1 1 0 1 1.500V
0 0 1 1 1 0 1.484V
0 0 1 1 1 1 1.468V
0 1 0 0 0 0 1.452V
0 1 0 0 0 1 1.436V
0 1 0 0 1 0 1.420V
0 1 0 0 1 1 1.404V
0 1 0 1 0 0 1.388V
0 1 0 1 0 1 1.372V
0 1 0 1 1 0 1.356V
0 1 0 1 1 1 1.340V
0 1 1 0 0 0 1.324V
0 1 1 0 0 1 1.308V
0 1 1 0 1 0 1.292V
0 1 1 0 1 1 1.276V
0 1 1 1 0 0 1.260V
0 1 1 1 0 1 1.244V
0 1 1 1 1 0 1.228V
0 1 1 1 1 1 1.212V
5
+VCCP
R165 10K_0402_5%
12
@
12
12
12
12
12
12
VID[5..0]
1 0 0 0 0 0 1.196V
1 0 0 0 0 1 1.180V
1 0 0 0 1 0 1.164V
1 0 0 0 1 1 1.148V
1 0 0 1 0 0 1.132V
1 0 0 1 0 1 1.116V
1 0 0 1 1 0 1.100V
1 0 0 1 1 1 1.084V
1 0 1 0 0 0 1.068V
1 0 1 0 0 1 1.052V
1 0 1 0 1 0 1.036V
1 0 1 0 1 1 1.020V
1 0 1 1 0 0 1.004V
1 0 1 1 0 1 0.988V
1 0 1 1 1 0 0.972V
1 0 1 1 1 1 0.956V
1 1 0 0 0 0 0.940V
1 1 0 0 0 1 0.924V
1 1 0 0 1 0 0.908V
1 1 0 0 1 1 0.892V
1 1 0 1 0 0 0.876V
1 1 0 1 0 1 0.860V
1 1 0 1 1 0 0.844V
1 1 0 1 1 1 0.828V
1 1 1 0 0 0 0.812V
1 1 1 0 0 1 0.796V
1 1 1 0 1 0 0.780V
1 1 1 0 1 1 0.764V
1 1 1 1 0 0 0.748V
1 1 1 1 0 1 0.732V
1 1 1 1 1 0 0.716V
1 1 1 1 1 1 0.700V
R162 10K_0402_5%
12
@
Voltage
12
@
R159 10K_0402_5%
R155 10K_0402_5%
R157 10K_0402_5%
12
12
@
@
V_CPU_GTLREF
Resistor placed within 0.5" of CPU pin.
Trace should be at least 25 miles away from any other
toggling signal.
CPU CLK SPEED
CPU_BSEL0:CPU_BSEL1
OPEN
J1
J2
SHORT
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
27.4_0402_1%
R128
+VCCA_PROC
C62
20 mils
12
R130
1
1
C57
2
2
10U_1206_6.3V6M
0.01U_0402_16V7K
5 mils
12
54.9_0402_1%
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JCPU1C
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Dothan
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
POWER, GROUND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FOX_PZ47813-2749-42
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
AA11
AA13
AA15
AA17
AA19
AA21
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC11
AC13
AC15
AC17
AC19
AD10
AD12
AD14
AD16
AD18
AE11
AE13
AE15
AE17
AE19
AF10
AF12
AF14
AF16
AF18
M21
M24
Y22
AA5
AA7
AA9
AB6
AB8
AC9
AD8
AE9
AF8
M4
M5
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
752, 18, 2005
1
C
of
5
4
3
2
1
+CPU_CORE
D D
C C
1
C589
10U_0805_6.3V6M
2
+CPU_CORE
1
C127
10U_0805_6.3V6M
2
+CPU_CORE
1
C585
10U_0805_6.3V6M
2
+CPU_CORE
1
C556
10U_0805_6.3V6M
2
Vcc-core
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
B B
1
C117
10U_0805_6.3V6M
2
1
C118
10U_0805_6.3V6M
2
1
C591
10U_0805_6.3V6M
2
1
C557
10U_0805_6.3V6M
2
C,uF ESL,nH
1
2
1
2
1
2
1
2
ESR, mohm
C124
10U_0805_6.3V6M
C187
10U_0805_6.3V6M
C592
10U_0805_6.3V6M
C170
10U_0805_6.3V6M
3X330uF 9m ohm/3 3.5nH/4
35X10uF
5m ohm/35 0.6nH/35
1
C137
10U_0805_6.3V6M
2
1
C111
10U_0805_6.3V6M
2
1
C590
10U_0805_6.3V6M
2
1
C587
10U_0805_6.3V6M
2
1
C156
10U_0805_6.3V6M
2
1
C112
10U_0805_6.3V6M
2
1
C586
10U_0805_6.3V6M
2
1
C172
10U_0805_6.3V6M
2
+CPU_CORE
1
C190
10U_0805_6.3V6M
2
+CPU_CORE
1
C113
10U_0805_6.3V6M
2
+CPU_CORE
1
C576
10U_0805_6.3V6M
2
10uF 1206 X5R -> 85 degree
Near VCORE regulator.
+CPU_CORE
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
C498
1
C499
+
2
1
1
C625
+
+
2
2
330U_D2E_2.5VM_R9
1
C189
10U_0805_6.3V6M
2
1
C559
10U_0805_6.3V6M
2
1
C580
10U_0805_6.3V6M
2
330U_D2E_2.5VM_R9
1
C634
+
2
1
C188
10U_0805_6.3V6M
2
1
C567
10U_0805_6.3V6M
2
1
C568
10U_0805_6.3V6M
2
1
C157
10U_0805_6.3V6M
2
1
C573
10U_0805_6.3V6M
2
1
C562
10U_0805_6.3V6M
2
X7R
High Frequence Decoupling
ESR <= 3m ohm
Capacitor > 880 uF
1
C147
10U_0805_6.3V6M
2
1
C579
10U_0805_6.3V6M
2
1
C558
10U_0805_6.3V6M
2
+VCCP
1
+
C497
150U_D2_6.3VM
2
A A
5
1
C610
0.1U_0402_10V6K
2
1
C607
0.1U_0402_10V6K
2
1
C604
0.1U_0402_10V6K
2
4
1
C510
0.1U_0402_10V6K
2
1
C511
0.1U_0402_10V6K
2
1
C506
0.1U_0402_10V6K
2
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C601
0.1U_0402_10V6K
2
1
C508
0.1U_0402_10V6K
2
1
C509
0.1U_0402_10V6K
2
1
C507
0.1U_0402_10V6K
2
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M /B LA-2522
401318
星期五 二月
05
852, 18, 20
1
C
of
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
H_A#3
H_A#4
NB_SUS_STAT#
1 2
C86
1U_0603_10V4Z
NB_GTLREF
C574
220P_0402_50V7K
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
D D
H_ADSTB#06
C C
C61
0.1U_0402_10V6K
12
R57
330_0402_5%
1 2
+VCCP
+1.8VS
B B
L
L19
FBM-11-160808-121-T_0603
Note: PLACE CLOSE TO RC300M,
USE 10/10 WIDTH/SPACE
+VCCP
R295
49.9_0402_1%
1 2
12
R299
100_0402_1%
A A
H_ADSTB#16
H_ADS#6
H_BNR#6
H_BPRI#6
H_DEFER#6
H_DRDY#6
H_DBSY#6
H_DPWR#6
H_LOCK#6
H_RESET#6
H_RS#26
H_RS#16
H_RS#06
H_TRDY#6
H_HIT#6
H_HITM#6
NB_SUS_STAT#26
NB_RST#17,26
NB_PWRGD28
1 2
R294 24.9_0402_1%
1 2
R296 49.9_0402_1%
1 2
PLACE CLOSE TO U27 Ball
W28, USE 20/20
WIDTH/SPACE
1
C570
1U_0603_10V4Z
2
1
2
C73 CLOSE
TO Ball W28
U20A
M31
CPU_A3#
P29
CPU_A4#
M29
CPU_A5#
N34
CPU_A6#
N33
CPU_A7#
M30
CPU_A8#
N32
CPU_A9#
P32
CPU_A10#
P30
CPU_A11#
R34
CPU_A12#
P33
CPU_A13#
R33
CPU_A14#
N30
CPU_A15#
N31
CPU_A16#
M34
CPU_REQ0#
N29
CPU_REQ1#
R30
CPU_REQ2#
M33
CPU_REQ3#
L32
CPU_REQ4#
R31
CPU_ADSTB0#
U33
CPU_A17#
T33
CPU_A18#
R32
CPU_A19#
R29
CPU_A20#
U29
CPU_A21#
T31
CPU_A22#
V32
CPU_A23#
T30
CPU_A24#
U32
CPU_A25#
U30
CPU_A26#
V30
CPU_A27#
T29
CPU_A28#
V29
CPU_A29#
U31
CPU_A30#
V33
CPU_A31#
T34
CPU_ADSTB1#
L31
CPU_ADS#
K29
CPU_BNR#
H30
CPU_BPRI#
J31
CPU_DEFER#
L30
CPU_DRDY#
G31
CPU_DBSY#
F29
CPU_BR0#
K30
CPU_LOCK#
A21
CPU_CPURSET#
G29
CPU_RS2#
G30
CPU_RS1#
J29
CPU_RS0#
F30
CPU_TRDY#
J30
CPU_HIT#
H29
CPU_HITM#
D10
CPU_RSET
AE5
SUS_STAT#
AE6
SYSRESET#
E12
POWERGOOD
W33
CPU_COMP_N
W32
CPU_COMP_P
H26
CPVDD
J27
CPVSS
Y33
CPU_VREF
Y32
THERMALDIODE_N
AA33
THERMALDIODE_P
B21
TESTMODE
12
R269
CHS-216RS300MDA12_BGA868
Ra
0_0402_5%
PART 1
OF 7
Ra
ADDR. GROUP 1 ADDR. GROUP 0CONTROLMISC.
RS300M MODERESISTOR
NORMAL MODE
H_A#[3..31] 6
H_REQ#[0..4] 6
H_D#[0..63] 6
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_DSTBN1#
CPU_DSTBP1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBP2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_DSTBN3#
CPU_DSTBP3#
L33
K34
J34
J33
K32
K33
H31
J32
F32
H33
E33
D32
G32
E32
D33
F34
F33
G33
G34
B30
C32
A31
C33
B33
C34
B32
D34
D30
B31
C30
E29
E30
A30
B29
C29
A32
D31
E31
F28
D28
E27
E28
F27
C28
B28
A28
F25
A27
B27
C26
B26
C25
E25
D26
D27
E26
F26
B25
F24
A25
C24
E24
D24
A24
D23
C22
B24
E22
B23
D22
B22
C21
A22
F23
E23
F22
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_DINV#0 6
H_DSTBN#0 6
H_DSTBP#0 6
H_DINV#1 6
H_DSTBN#1 6
H_DSTBP#1 6
H_DINV#2 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#3 6
H_DSTBN#3 6
H_DSTBP#3 6
KC FBM-L11-201209-221LMAT_0805
220mA
+1.8VS
+1.8VS
L20
KC FBM-L11-201209-221LMAT_0805
+1.8VS
REFCLK1_NB16
CLK_AGP_66M16
CLK_MEM_66M16
L14
CHB1608U301_0603
L15
CHB1608U301_0603
1 2
0.1U_0402_10V6K
1 2
C83
10U_0805_10V4Z
80mA
+2.5VS
12
L13
+2.5VS_AVDD
1
C55
0.1U_0402_10V6K
1 2
C56
0.1U_0402_10V6K
1
1
C53
2
2
1
1
2
2
0.1U_0402_10V6K
1 2
R251
0_0402_5%
+3VS
CLK_AGP_66M
12
1
@
2
Note: PLACE CLOSE TO U2 (NB CHIP)
L
1
2
C54
0.1U_0402_10V6K
C82
REFCLK1_NB1
R265
56_0402_5%
1 2
1 2
12
R63
10K_0402_5%
10K_0402_5%@
R375
18_0402_5%@
C660
10P_0402_50V8J
2
+1.8VS_AVDDDI
+1.8VS_AVDDQ
PLLVDD_18H_A#26
12
R55
10K_0402_5%@
R56
10K_0402_5%@
CLK_AGP_66M
CLK_MEM_66M
R261
+3VS_VDDR3
1 2
1 2
CLK_MEM_66M
12
R353
18_0402_5%
1
C643
10P_0402_50V8J
2
1 2
L18
CHB1608U301_0603
U20D
G9
VDDR3
H9
VDDR3
A18
AVDD_25
B18
AVSSN
B17
AVDDDI_18
C17
AVSSDI
A19
AVDDQ
B19
AVSSQ
H14
PLLVDD_18
H15
PLLVSS
D18
RED
E18
GREEN
F18
BLUE
D13
DACHSYNC
E13
DACVSYNC
E11
DACSDA
F12
DACSCL
C18
RSET
A9
XTALIN
B9
XTALOUT
F9
ALINK_CLK
C8
AGPCLKOUT
D9
AGPCLKIN
C9
EXT_MEM_CLK
F10
USBCLK
D11
REF27
E10
OSC
CHS-216RS300MDA12_BGA868
R266
10K_0402_5%@
150mA
+3VS
1
C91
0.1U_0402_10V6K
2
PART 4 OF 7
CRT
SVID LVDS
SYS_FBCLKOUT#
CLK. GEN.
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD
LPVSS
LVDDR
LVDDR
LVSSR
LVSSR
Y_G
COMP
CPUSTOP#
SYSCLK
SYSCLK#
SYS_FBCLKOUT
HCLKIN#
HCLKIN
C
D15
E15
F15
D16
F16
E16
F17
E17
F14
E14
C13
B13
KC FBM-L11-201209-221LMAT_0805
C12
A13
C14
B14
+1.8VS_LPVDD
A16
A15
+1.8VS_LVDDR
B16
C16
B15
C15
F19
0.1U_0402_10V6K
D19
E19
2N7002_SOT23
E9
A12
R262 10K_0402_5%@
B12
R268 10K_0402_5%@
C11
B11
CLK_NB_BCLK#
B10
CLK_NB_BCLK
A10
C66
@
1 2
R250 0_0402_5% @
12
12
0.1U_0402_10V6K
1
1
C58
C51
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
Q20
2
KC FBM-L11-201209-221LMAT_0805
1
1
C65
2
2
1 2
R62 1K_0402_5%
13
D
2
G
S
CLK_NB_BCLK# 16
CLK_NB_BCLK 16
+1.8VS
L12
1 2
1
C50
2
10U_0805_10V4Z
1 2
L17
C69
10U_0805_10V4Z
NB_RST# 17,26
PM_STPCPU# 6,16,25,48
R267
@
10K_0402_5%
+3VS
1 2
+1.8VS
1 2
@
R252
10K_0402_5%
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
1
952, 18, 2005
C
of
5
4
3
2
1
DDR_A_SMA0
DDR_A_SMA1
DDR_A_SMA2
DDR_A_SMA3
DDR_A_SMA4
DDR_A_SMA5
DDR_A_SMA6
DDR_A_SMA7
DDR_A_SMA8
DDR_A_SMA9
DDR_A_SMA10
DDR_A_SMA11
DDR_A_SMA12
DDR_A_SMA13
DDR_A_SMA14
DDR_A_SMA15
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_SRAS#
DDR_A_SCAS#
DDR_A_SWE#
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
MEMA_CLK0
MEMA_CLK0#
DDR_A_SCKE0
DDR_A_SCKE1
DDR_A_SCS0#
DDR_A_SCS1#
1 2
C167
1U_0603_10V4Z
DDR_A_DM[0..7]
DDR_A_D[0..63]
DDR_A_DQS[0..7]
DDR_A_SMA[0..15]
MEN_COMP
MPVDD
U20B
AN21
AM21
AN20
AM18
AN17
AN14
AM15
AN12
AM13
AM11
AM22
AP10
AM9
AM27
AN22
AK33
AP4
AP11
AP17
AN25
AM34
AG32
AC32
AN29
AP31
AM30
AK1
AN4
AN10
AM17
AM25
AM33
AG33
AC33
AP22
AM23
AM7
AN7
AN32
AN33
AN31
AP32
AP25
AA34
AG3
AG19
AH19
AJ3
PART 2 OF 7
MEMA_A0
MEMA_A1
MEMA_A2
MEMA_A3
MEMA_A4
MEMA_A5
MEMA_A6
MEMA_A7
MEMA_A8
MEMA_A9
MEMA_A10
MEMA_A11
MEMA_A12
MEMA_A13
MEMA_A14
MEMA_A15
MEMA_DM0
MEMA_DM1
MEMA_DM2
MEMA_DM3
MEMA_DM4
MEMA_DM5
MEMA_DM6
MEMA_DM7
MEMA_RAS#
MEMA_CAS#
MEMA_WE#
MEMA_DQS0
MEMA_DQS1
MEMA_DQS2
MEMA_DQS3
MEMA_DQS4
MEMA_DQS5
MEMA_DQS6
MEMA_DQS7
MEMA_CK
MEMA_CK#
MEMA_CKE0
MEMA_CKE1
MEMA_CS#0
MEMA_CS#1
MEMA_CS#2
MEMA_CS#3
MEM_COMP
MEM_CAP2
MEM_CAP1
MPVDD
MPVSS
CHS-216RS300MDA12_BGA868
MEMA_DQ0
MEMA_DQ1
MEMA_DQ2
MEMA_DQ3
MEMA_DQ4
MEMA_DQ5
MEMA_DQ6
MEMA_DQ7
MEMA_DQ8
MEMA_DQ9
MEMA_DQ10
MEMA_DQ11
MEMA_DQ12
MEMA_DQ13
MEMA_DQ14
MEMA_DQ15
MEMA_DQ16
MEMA_DQ17
MEMA_DQ18
MEMA_DQ19
MEMA_DQ20
MEMA_DQ21
MEMA_DQ22
MEMA_DQ23
MEMA_DQ24
MEMA_DQ25
MEMA_DQ26
MEMA_DQ27
MEMA_DQ28
MEMA_DQ29
MEMA_DQ30
MEMA_DQ31
MEMA_DQ32
MEMA_DQ33
MEMA_DQ34
MEMA_DQ35
MEMA_DQ36
MEMA_DQ37
MEMA_DQ38
MEMA_DQ39
MEMA_DQ40
MEMA_DQ41
MEM I/F
MEMA_DQ42
MEMA_DQ43
MEMA_DQ44
MEMA_DQ45
MEMA_DQ46
MEMA_DQ47
MEMA_DQ48
MEMA_DQ49
MEMA_DQ50
MEMA_DQ51
MEMA_DQ52
MEMA_DQ53
MEMA_DQ54
MEMA_DQ55
MEMA_DQ56
MEMA_DQ57
MEMA_DQ58
MEMA_DQ59
MEMA_DQ60
MEMA_DQ61
MEMA_DQ62
MEMA_DQ63
MEM_DDRVREF
0.1U_0402_10V6K
0.1U_0402_10V6K
C205
C206
AH2
AJ1
AL1
AM1
AH3
AJ2
AK2
AL2
AM2
AN3
AM6
AN6
AN2
AP3
AN5
AP5
AN8
AN9
AN11
AN13
AM8
AM10
AM12
AM14
AN15
AN16
AN18
AN19
AM16
AP16
AM19
AM20
AP23
AM24
AM26
AM28
AN23
AN24
AN26
AN27
AM29
AM31
AL33
AK32
AN28
AN30
AL34
AK34
AJ32
AH32
AF33
AE33
AJ33
AH33
AF32
AE32
AD34
AD33
AB33
AA32
AE34
AD32
AB32
AB34
AP26
2
1
DDR_VREF
2
1
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
+2.5V+2.5V
12
R126
1K_0603_1%
12
R127
1K_0603_1%
DDR_B_DM[0..7]14
DDR_B_D[0..63]14
DDR_B_DQS[0..7]14
DDR_B_SMA[0..15]14
DDR_B_SRAS#14
DDR_B_SCAS#14
DDR_B_SWE#14
T16 PAD
T14 PAD
DDR_B_SCKE014
DDR_B_SCKE114
DDR_B_SCS0#14
DDR_B_SCS1#14
DDR_A_DM[0..7]13
DDR_A_D[0..63]13
D D
C C
B B
+1.8VS
DDR_A_DQS[0..7]13
DDR_A_SMA[0..15]13
DDR_A_SRAS#13
DDR_A_SCAS#13
DDR_A_SWE#13
MEMA_CLK016
MEMA_CLK0#16
DDR_A_SCKE013
DDR_A_SCKE113
DDR_A_SCS0#13
DDR_A_SCS1#13
R124 49.9_0402_1%
C577 0.47U_0603_10V7K
C198 0.47U_0603_10V7K
L23
CHB2012U121_0805
12
12
12
1 2
DDR_B_DM[0..7]
DDR_B_D[0..63]
DDR_B_DQS[0..7]
DDR_B_SMA[0..15]
@
@
DDR_B_SMA0
DDR_B_SMA1
DDR_B_SMA2
DDR_B_SMA3
DDR_B_SMA4
DDR_B_SMA5
DDR_B_SMA6
DDR_B_SMA7
DDR_B_SMA8
DDR_B_SMA9
DDR_B_SMA10
DDR_B_SMA11
DDR_B_SMA12
DDR_B_SMA13
DDR_B_SMA14
DDR_B_SMA15
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_SRAS#
DDR_B_SCAS#
DDR_B_SWE#
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_SCKE0
DDR_B_SCKE1
DDR_B_SCS0#
DDR_B_SCS1#
U20G
AK21
AJ21
AL20
AJ19
AJ18
AK15
AL15
AL13
AJ14
AK12
AJ22
AJ12
AK10
AL26
AK22
AG28
AL12
AK18
AK25
AJ31
AE30
AA30
AK28
AK31
AJ29
AK11
AL17
AJ25
AH30
AE31
AA31
AL22
AJ23
AL30
AL31
AJ30
AL32
AH5
AL6
AJ6
AK6
AL8
AJ9
PART 7 OF 7
MEMB_A0
MEMB_A1
MEMB_A2
MEMB_A3
MEMB_A4
MEMB_A5
MEMB_A6
MEMB_A7
MEMB_A8
MEMB_A9
MEMB_A10
MEMB_A11
MEMB_A12
MEMB_A13
MEMB_A14
MEMB_A15
MEMB_DM0
MEMB_DM1
MEMB_DM2
MEMB_DM3
MEMB_DM4
MEMB_DM5
MEMB_DM6
MEMB_DM7
MEMB_RAS#
MEMB_CAS#
MEMB_WE#
MEMB_DQS0
MEMB_DQS1
MEMB_DQS2
MEMB_DQS3
MEMB_DQS4
MEMB_DQS5
MEMB_DQS6
MEMB_DQS7
MEMB_CK
MEMB_CK#
MEMB_CKE0
MEMB_CKE1
MEMB_CS#0
MEMB_CS#1
MEMB_CS#2
MEMB_CS#3
CHS-216RS300MDA12_BGA868
MEMB_DQ0
MEMB_DQ1
MEMB_DQ2
MEMB_DQ3
MEMB_DQ4
MEMB_DQ5
MEMB_DQ6
MEMB_DQ7
MEMB_DQ8
MEMB_DQ9
MEMB_DQ10
MEMB_DQ11
MEMB_DQ12
MEMB_DQ13
MEMB_DQ14
MEMB_DQ15
MEMB_DQ16
MEMB_DQ17
MEMB_DQ18
MEMB_DQ19
MEMB_DQ20
MEMB_DQ21
MEMB_DQ22
MEMB_DQ23
MEMB_DQ24
MEMB_DQ25
MEMB_DQ26
MEMB_DQ27
MEMB_DQ28
MEMB_DQ29
MEMB_DQ30
MEMB_DQ31
MEMB_DQ32
MEMB_DQ33
MEMB_DQ34
MEMB_DQ35
MEMB_DQ36
MEMB_DQ37
MEMB_DQ38
MEMB_DQ39
MEMB_DQ40
MEMB_DQ41
MEM I/F
MEMB_DQ42
MEMB_DQ43
MEMB_DQ44
MEMB_DQ45
MEMB_DQ46
MEMB_DQ47
MEMB_DQ48
MEMB_DQ49
MEMB_DQ50
MEMB_DQ51
MEMB_DQ52
MEMB_DQ53
MEMB_DQ54
MEMB_DQ55
MEMB_DQ56
MEMB_DQ57
MEMB_DQ58
MEMB_DQ59
MEMB_DQ60
MEMB_DQ61
MEMB_DQ62
MEMB_DQ63
AG6
AH6
AJ4
AL3
AG5
AG4
AJ5
AK3
AK4
AM4
AJ8
AK8
AL4
AL5
AJ7
AK7
AJ10
AL10
AJ13
AK14
AK9
AJ11
AK13
AJ15
AJ16
AJ17
AK19
AJ20
AK16
AK17
AL19
AK20
AK23
AK24
AJ26
AK27
AJ24
AL24
AK26
AJ27
AJ28
AL29
AH28
AG29
AL27
AK29
AH29
AG30
AG31
AF29
AD30
AC30
AF30
AF31
AD29
AC29
AB31
AA29
Y30
W30
AB29
AB30
Y29
W29
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_VREF trace width of
L
20mils and space
A A
5
20mils(min)
4
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
of
1
10 52, 18, 2005
C
5
4
3
2
1
A_AD0
R76 0_0402_5%
1 2
R75
1 2
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
+AGPVREF
1 2
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
AGP_COMP
AGP_ST2
AGP_ST1
AGP_ST0
A_PAR25
A_STROBE#25
A_ACAT#25
A_END#25
PCI_PIRQA#17,25,31
A_DEVSEL#25
A_OFF#25
A_SBREQ#25
A_SBGNT#25
A_AD[0..31]
A_CBE#[0..3]
A_AD[0..31]25
A_CBE#[0..3]25
D D
C C
+3VS
AGP_GNT#17
AGP_REQ#17
AGP8X_DET#17
?
?
+AGPVREF17
+1.5VS
R66
169_0402_1%
Ra
AGP_COMP
B B
AGP_4X/8X#
Ra
8X=0
169R
4X=1
54.9R
AGP8X_DET#
RS300MD internal ppull-up
A A
U20C
AE4
AE2
AE3
AD2
AD1
AD3
AD5
AD6
AC1
AC2
AC4
AC5
AC6
AB2
AB4
AB5
AA4
AA2
AA3
W3
W4
W5
W6
V2
V1
V5
V6
U1
U2
U3
U4
U5
AC3
AB6
W2
V4
AA5
Y3
Y2
Y6
U6
Y5
AA6
T5
T6
R5
R6
G6
G5
J6
F6
F5
J5
H5
H6
CHS-216RS300MDA12_BGA868
+AGPVREF
AGP 8X
324_0402_1%
Rb
100_0402_1%
Rc
324_0402_1%
+AGPVREF
100_0402_1%
ALINK_AD0
ALINK_AD1
ALINK_AD2
ALINK_AD3
ALINK_AD4
ALINK_AD5
ALINK_AD6
ALINK_AD7
ALINK_AD8
ALINK_AD9
ALINK_AD10
ALINK_AD11
ALINK_AD12
ALINK_AD13
ALINK_AD14
ALINK_AD15
ALINK_AD16
ALINK_AD17
ALINK_AD18
ALINK_AD19
ALINK_AD20
ALINK_AD21
ALINK_AD22
ALINK_AD23
ALINK_AD24
ALINK_AD25
ALINK_AD26
ALINK_AD27
ALINK_AD28
ALINK_AD29
ALINK_AD30
ALINK_AD31
ALINK_CBE#0
ALINK_CBE#1
ALINK_CBE#2
ALINK_CBE#3
ALINK_PAR
ALINK_FRAME#
ALINK_IRDY#
ALINK_TRDY#
INTA#
ALINK_DEVSEL#
ALINK_STOP#
ALINK_SBREQ#
ALINK_SBGNT#
ALINK_REQ0#
ALINK_GNT0#
AGP_GNT
AGP_REQ
AGP8X_DET#
AGP_VREF/TMDS_VREF
AGP_COMP
AGP_ST2
AGP_ST1
AGP_ST0
PART 3 OF 7
AGP 4X
1K_0402_1%
1K_0402_1%
+1.5VS
Rb
12
R65
12
Rc
R67
2
C71
0.1U_0402_10V6K
1
0.233*VDDP for AGP 3.0
0.5*VDDP for AGP 2.0
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP_SBSTBF
AGP_SBSTBS
PCI Bus 0 / A-Link I/F
AGP_ADSTBF0
AGP_ADSTBS0
AGP_ADSTBF1
AGP_ADSTBS1
AGP_C#BE0
AGP_C#BE1
AGP_C#BE2
AGP_C#BE3
AGP_IRDY
AGP_TRDY
AGP_STOP
AGP_PAR
AGP_FRAME
AGP_DEVSEL
AGP_DBI_HI
AGP_DBI_LO
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP_RBF
AGP_WBF
AGP_SBA0#
AGP_SBA1#
AGP_SBA2#
AGP_SBA3#
AGP_SBA4#
AGP_SBA5#
AGP_SBA6#
AGP_SBA7#
T2
T3
R2
R3
P2
P3
N3
N2
M3
L2
L3
K2
K3
J2
J1
J3
H3
G2
G3
F2
F1
F3
E1
E2
C1
C2
C3
B2
D4
B3
A3
C4
A6
C6
M1
M2
D3
D2
L1
H1
H2
E3
L5
M6
N6
N5
L6
M5
B4
A4
K6
K5
B8
C7
B7
A7
B6
C5
B5
D5
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
AGP_SBSTB 17
AGP_SBSTB# 17
AGP_ADSTB0 17
AGP_ADSTB0# 17
AGP_ADSTB1 17
AGP_ADSTB1# 17
AGP_IRDY# 17
AGP_TRDY# 17
AGP_STOP# 17
AGP_PAR 17
AGP_FRAME# 17
AGP_DEVSEL# 17
AGP_DBI_HI 17
AGP_DBI_LO 17
AGP_RBF# 17
AGP_WBF# 17
AGP_AD[0..31] 17
AGP_SBA[0..7] 17
AGP_C/BE#[0..3] 17
AGP_ST[0..2] 17
A_AD31
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_AD18A_AD18
A_AD17A_AD17
A_PAR25
A_PAR
+3VS
R93
10K_0402_5%
1 2
1 2
R92
4.7K_0402_5%
1 2
R86
4.7K_0402_5%
1 2
R77 10K_0402_5%
1 2
R78 4.7K_0402_5%@
1 2
R79 10K_0402_5%@
1 2
R425 4.7K_0402_5%
1 2
R80 10K_0402_5%
1 2
R410 4.7K_0402_5%@
1 2
R94 10K_0402_5%
1 2
R95 4.7K_0402_5%@
1 2
R83 10K_0402_5%@
1 2
R84 4.7K_0402_5%
1 2
R90 10K_0402_5%@
1 2
R91 4.7K_0402_5%
1 2
R85 10K_0402_5%
1 2
R433 4.7K_0402_5%@
1 2
R107 10K_0402_5%
1 2
R106 4.7K_0402_5%@
1 2
R103 10K_0402_5%
1 2
R104 4.7K_0402_5%@
1 2
R101 4.7K_0402_5%@
1 2
R102 4.7K_0402_5%
1 2
R96 4.7K_0402_5%@
1 2
R97 4.7K_0402_5%
1 2
R99 4.7K_0402_5%@
1 2
R100 4.7K_0402_5%
1 2
R109 4.7K_0402_5%
1 2
R110 4.7K_0402_5%@
R87
10K_0402_5%
1 2
D9
2 1
CH751H-40_SC76
D8
2 1
CH751H-40_SC76
A_AD[31..30 ] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
CPU_BSEL1 7,16
CPU_BSEL0 7,16
A_AD29: STRAP CONFIGURATION
+3VS
DEFAULT : 1
A_AD28: SPREAD SPECTRUM ENABLE
+3VS
DEFAULT: 0
A_AD27: FrcS hortReset#
+3VS
DEFAULT : 1
A_AD26 : ENABLE IOQ
+3VS
DEFAULT : 1
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
+3VS
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
+3VS
DEFAULT : 1
A_AD23 : CLOCK BYPASS DISABLE
+3VS
DEFAULT : 1
A_AD22 : OSC CLOCK SELECT
+3VS
DEFAULT : 1
A_AD21 : AUTO_CAL ENABLE
+3VS
DEFAULT : 1
A_AD20 : INTERNAL CLK GEN ENABLE
+3VS
DEFAULT: 0
A_AD18 : ENABLE PHASE CALIBRATION
+3VS
DEFAULT: 0
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
+3VS
DEFAULT: 0
PAR: EXTENDED DEBUG MODE
+3VS
DEFAULT : 1
0: REDUCEDE SET
1: FULL SET
0: DISABLE
1: ENABLE
0: TEST MODE
1: NORMAL MODE
0: IOQ=1
1: IOQ=12
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
0: BANIAS CPU
1: OTHER CPU
0: TEST MODE
1: NORMAL
0: OSC DRIVES PCICLK
1: OSC DRIVES REFCLK
0: DISABLE
1: ENABLE
0: DISABLE
1: ENABLE
0: DISABLE
1: ENABLE
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
0: DEBUG MODE
1: NORMAL
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
1
C
of
11 52, 18, 2005
5
U20E
G10
1330mA
D D
C C
+VCCP
500mA
B B
VDD_CORE
G12
VDD_CORE
G16
VDD_CORE
H10
VDD_CORE
H12
VDD_CORE
H16
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N15
VDD_CORE
N16
VDD_CORE
N19
VDD_CORE
N20
VDD_CORE
N21
VDD_CORE
N22
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P15
VDD_CORE
P16
VDD_CORE
P19
VDD_CORE
P20
VDD_CORE
P21
VDD_CORE
P22
VDD_CORE
R13
VDD_CORE
R14
VDD_CORE
R15
VDD_CORE
R16
VDD_CORE
R19
VDD_CORE
R20
VDD_CORE
R21
VDD_CORE
R22
VDD_CORE
Y13
VDD_CORE
Y14
VDD_CORE
Y15
VDD_CORE
Y16
VDD_CORE
Y19
VDD_CORE
Y20
VDD_CORE
Y21
VDD_CORE
Y22
VDD_CORE
AA13
VDD_CORE
AA14
VDD_CORE
AA15
VDD_CORE
AB22
VDD_CORE
AB21
VDD_CORE
AB20
VDD_CORE
AB19
VDD_CORE
AB16
VDD_CORE
AB15
VDD_CORE
AB14
VDD_CORE
AB13
VDD_CORE
AA22
VDD_CORE
AA21
VDD_CORE
AA20
VDD_CORE
AA19
VDD_CORE
AA16
VDD_CORE
W34
VDDR2_CPU
U27
VDDR2_CPU
T28
VDDR2_CPU
T27
VDDR2_CPU
N28
VDDR2_CPU
N27
VDDR2_CPU
M28
VDDR2_CPU
M27
VDDR2_CPU
K28
VDDR2_CPU
K27
VDDR2_CPU
H27
VDDR2_CPU
H25
VDDR2_CPU
H23
VDDR2_CPU
H21
VDDR2_CPU
H20
VDDR2_CPU
G28
VDDR2_CPU
G27
VDDR2_CPU
G25
VDDR2_CPU
G21
VDDR2_CPU
F21
VDDR2_CPU
F20
VDDR2_CPU
E21
VDDR2_CPU
E20
VDDR2_CPU
D21
VDDR2_CPU
D20
VDDR2_CPU
C20
VDDR2_CPU
CHS-216RS300MDA12_BGA868
PART 5
OF 7
CORE PWR
CPU I/F PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
MEM I/F PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
ALINK PWR
VDD_18
VDD_18
VDD_18
VDD_18
W31
Y27
AB27
AB28
AC31
AD27
AD28
AF27
AG1
AG7
AG8
AG10
AG12
AG14
AG16
AG18
AG22
AG24
AG26
AG27
AG34
AH10
AH14
AH16
AH22
AH26
AL9
AL16
AL23
AP2
AP7
AP13
AP19
AP28
AP33
R8
R7
R4
P6
P5
P1
N8
N4
L8
L7
L4
K8
J4
G4
E4
A2
H8
E7
D7
U7
U8
W8
Y1
AA7
AA8
AD7
AD8
AF4
AF5
AF6
AF26
AF9
J26
J9
+2.5V+1.5VS_CORE
VDDP_AGP
+1.8VS
180mA
+3VS
500mA
4
400mA
+1.5VS_VDDP
230mA
POP For 150G
DEPOP For 150A
R68 0_0603_5%
1 2
1 2
R69 0_0603_5%@
+1.5VS
+3VS
U20F
PART 6 OF 7
A33
VSS
B1
VSS
B20
VSS
B34
VSS
C10
VSS
C19
VSS
C23
VSS
C27
VSS
C31
VSS
D6
VSS
D8
VSS
D12
VSS
D14
VSS
D17
VSS
D25
VSS
D29
VSS
E5
VSS
E6
VSS
E8
VSS
F4
VSS
F7
VSS
F8
VSS
F11
VSS
F13
VSS
F31
VSS
G8
VSS
G13
VSS
G15
VSS
G18
VSS
GND
G19
VSS
G22
VSS
G24
VSS
H4
VSS
H7
VSS
H11
VSS
H13
VSS
H17
VSS
H18
VSS
H19
VSS
H22
VSS
H24
VSS
H32
VSS
J7
VSS
J8
VSS
J28
VSS
K4
VSS
K31
VSS
L27
VSS
L29
VSS
M4
VSS
M7
VSS
M8
VSS
M32
VSS
N17
VSS
N18
VSS
P4
VSS
P7
VSS
P8
VSS
P17
VSS
P18
VSS
P27
VSS
P31
VSS
R1
VSS
AF1
VSS
AF2
VSS
AF3
VSS
AF7
VSS
AF8
VSS
AG2
VSS
AG9
VSS
AG11
VSS
AG13
VSS
AG15
VSS
AG17
VSS
AG20
VSS
AG21
VSS
AG23
VSS
AG25
VSS
AH4
VSS
AH8
VSS
AH11
VSS
AH13
VSS
AH17
VSS
AH20
VSS
AH23
VSS
AH25
VSS
AH31
VSS
AH34
VSS
AN1
VSS
AN34
VSS
AP8
VSS
AP14
VSS
AP20
VSS
CHS-216RS300MDA12_BGA868
3
V13
VSS
V14
VSS
V15
VSS
V16
VSS
V17
VSS
V18
VSS
V19
VSS
V20
VSS
V21
VSS
V22
VSS
V27
VSS
V28
VSS
V31
VSS
V34
VSS
W13
VSS
W14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W15
W16
W17
W18
W19
W20
W21
W22
W27
W28
Y4
Y7
Y8
Y17
Y18
Y31
AA1
V8
V7
V3
U22
U21
U20
U19
U18
U17
U16
U15
U14
U13
T32
T22
T21
T20
T19
T18
T17
T16
T15
T14
T13
T8
T4
R28
R27
R18
R17
AA17
AA18
AA27
AA28
AB3
AB8
AB17
AB18
AC7
AC8
AC27
AD4
AD31
AE8
AE27
AE28
AE29
AK5
AK30
AL7
AL11
AL14
AL18
AL21
AL25
AL28
AM3
AM5
AM32
AP29
10U_0805_10V4Z
10U_0805_10V4Z
C98
22U_1206_10V4Z
C495
47U_B_6.3VM
+1.8VS
1
C162
C80
2
0.1U_0402_10V6K
+3VS
1
C158
2
0.1U_0402_10V6K
+1.5VS
+1.5VS_VDDP
1
C79
2
0.1U_0402_10V6K
+VCCP
1
+
C76
2
0.1U_0402_10V6K
C164
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.1U_0402_10V6K
1
C85
2
0.1U_0402_10V6K
1
C120
2
L16
FBM-L11-321611-260-LMT_1206
1 2
L22
KC FBM-L18-453215-900LMA90T_1812
0.1U_0402_10V6K
1
C90
2
0.1U_0402_10V6K
1
C75
2
1
C175
2
0.1U_0402_10V6K
1
C136
2
0.1U_0402_10V6K
12
1
C106
2
0.1U_0402_10V6K
1
C93
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C176
2
0.1U_0402_10V6K
1
C95
2
0.1U_0402_10V6K
1
C100
2
1
C173
0.1U_0402_10V6K
2
1
C174
2
0.1U_0402_10V6K
+1.5VS_VDDP
+1.5VS_CORE
1
C105
2
0.1U_0402_10V6K
1
C114
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C141
2
0.1U_0402_10V6K
1
C88
2
0.1U_0402_10V6K
1
C119
2
1
C128
2
0.1U_0402_10V6K
1
C59
2
0.1U_0402_10V6K
1
C129
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
1
2
0.1U_0402_10V6K
1
C78
2
1
C159
2
1
C96
0.1U_0402_10V6K
2
1
2
0.1U_0402_10V6K
1
1
C52
2
+1.5VS_CORE
1
C77
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C74
2
1
C70
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C116
2
1
C104
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C107
2
1
C101
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C132
2
1
C103
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C115
2
4.7U_0805_10V4Z
1
1
+
C140
47U_B_6.3VM
A A
2
C97
2
4.7U_0805_10V4Z
C110
1
C135
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C144
2
1
C139
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C143
2
1
C133
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C145
2
1
C131
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C134
2
1
C146
2
0.1U_0402_10V6K
1
C108
2
0.1U_0402_10V6K
1
C102
2
0.1U_0402_10V6K
0.01U_0402_25V4Z
1
C109
2
1
2
1
C81
0.01U_0402_25V4Z
2
+2.5V
C204
150U_D2_6.3VM
1
+
C196
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C130
2
5
1
C152
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C161
2
1
C200
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C202
2
1
C179
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C180
2
1
1
C183
2
2
0.1U_0402_10V6K
4
0.1U_0402_10V6K
C171
1
C181
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C195
2
1
C185
2
0.1U_0402_10V6K
1
C155
2
0.1U_0402_10V6K
1
C182
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C142
2
3
1
C160
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C186
2
1
1
C201
0.1U_0402_10V6K
2
2
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
1
12 52, 18, 2005
C
of
5
4
3
2
1
DDR_A_SMA[0..15]10
DDR_A_DM[0..7]10
DDR_A_D[0..63]10
DDR_A_DQS[0..7]10
D D
DDR_A_SCKE110
DDR_A_SCS1#10
DDR_A_SCS0#10
DDR_A_SWE#10
DDR_A_SCAS#10
C C
DDR_A_D12
DDR_A_D2 DDR_AD_D2
DDR_A_D0
DDR_A_D1 DDR_AD_D1
DDR_A_D5 DDR_AD_D5
DDR_A_D6 DDR_AD_D6
DDR_A_DQS0 DDR_AD_DQS0
DDR_A_DM0 DDR_AD_DM0
DDR_A_D15
DDR_A_D14
DDR_A_D11
DDR_A_DQS1
B B
System Memory Layout Topology
DATA/DQS/DM
NB
A A
ADD/CONTROL
NB
DDR_A_SMA[0..15]
DDR_A_DM[0..7]
DDR_A_D[0..63]
DDR_A_DQS[0..7]
DDR_A_SMA10 DDR_AD_MA10
DDR_A_SMA1 DDR_AD_MA1
DDR_A_SMA3 DDR_AD_MA3
DDR_A_SMA4
DDR_A_SMA5
DDR_A_SMA7 DDR_AD_MA7
RP20 10_0804_8P4R_5%
RP22 10_0804_8P4R_5%
RP21 10_0804_8P4R_5%
RP18 10_0804_8P4R_5%
RP19 10_0804_8P4R_5%
RP23 10_0804_8P4R_5%
18
27
36
DDR_AD_MA2DDR_A_SMA2
45
RP24 10_0804_8P4R_5%
DDR_A_SMA11 DDR_AD_MA11
DDR_A_SMA15 DDR_AD_MA15
DDR_A_SCKE1 DDR_AD_CKE1
DDR_A_SCS1#
DDR_A_SCS0#
DDR_A_SCAS#
DDR_AD_D13DDR_A_D13
18
DDR_AD_D12
27
36
DDR_AD_D3DDR_A_D3
45
DDR_AD_D0
18
27
36
DDR_AD_D4DDR_A_D4
45
DDR_AD_D7DDR_A_D7
18
27
36
45
DDR_AD_D15
18
DDR_AD_D14
27
DDR_AD_D11
36
DDR_AD_D10
45
DDR_AD_DM1DDR_A_DM1
18
DDR_AD_DQS1
27
DDR_AD_D9DDR_A_D9
36
DDR_AD_D8DDR_A_D8
45
Rs
10R
DDR_AD_MA4
18
DDR_AD_MA5
27
36
DDR_AD_MA6DDR_A_SMA6
45
RP26 10_0804_8P4R_5%
RP11 10_0804_8P4R_5%
DDR_A_D25
DDR_A_D22
DDR_A_D23
DDR_A_DM2
DDR_A_DM3
DDR_A_DQS3
DDR_A_D30 DDR_AD_D30
DDR_A_D27
Rt
56R
DIMM0
Rt
Rs
33R
10R
DIMM0
5
18
27
36
45
DDR_AD_CS1#
18
DDR_AD_CS0#
27
DDR_AD_WE#DDR_A_SWE#
36
DDR_AD_CAS#
45
RP17 10_0804_8P4R_5%
RP15 10_0804_8P4R_5%
RP16 10_0804_8P4R_5%
RP14 10_0804_8P4R_5%
RP13 10_0804_8P4R_5%
+VTT
+VTT
DDR_A_SCKE010
DDR_A_SRAS#10
DDR_AD_D20DDR_A_D20
18
DDR_AD_D21DDR_A_D21
27
DDR_AD_D17DDR_A_D17
36
DDR_AD_D16DDR_A_D16
45
DDR_AD_D25
18
DDR_AD_D24DDR_A_D24
27
DDR_AD_D22
36
DDR_AD_D23
45
DDR_AD_D19DDR_A_D19
18
DDR_AD_D18DDR_A_D18
27
DDR_AD_DM2
36
DDR_AD_DQS2DDR_A_DQS2
45
DDR_AD_DM3
18
DDR_AD_DQS3
27
DDR_AD_D28DDR_A_D28
36
DDR_AD_D29DDR_A_D29
45
18
DDR_AD_D31DDR_A_D31
27
DDR_AD_D27
36
DDR_AD_D26DDR_A_D26
45
DDR_A_SMA8
DDR_A_SMA9 DDR_AD_MA9
DDR_A_SMA13 DDR_AD_MA13
RP25 10_0804_8P4R_5%
RP12 10_0804_8P4R_5%
RP9 10_0804_8P4R_5%
DDR_A_D35 DDR_AD_D35
RP10 10_0804_8P4R_5%
DDR_A_D33
RP8 10_0804_8P4R_5%
DDR_A_D38
RP7 10_0804_8P4R_5%
DDR_A_DM5
DDR_A_DQS5 DDR_AD_DQS5
RP6 10_0804_8P4R_5%
DDR_A_D47 DDR_AD_D47
DDR_A_D46 DDR_AD_D46
RP5 10_0804_8P4R_5%
DDR_A_D52 DDR_AD_D52
DDR_A_D49 DDR_AD_D49
RP4 10_0804_8P4R_5%
DDR_A_D50
DDR_A_DM6
DDR_A_DQS6
RP1 10_0804_8P4R_5%
DDR_A_D62
RP3 10_0804_8P4R_5%
DDR_A_D56
RP2 10_0804_8P4R_5%
DDR_A_D60
DDR_AD_MA8
18
DDR_AD_MA12DDR_A_SMA12
27
36
DDR_AD_CKE0DDR_A_SCKE0
45
DDR_AD_RAS#DDR_A_SRAS#
18
DDR_AD_MA14DDR_A_SMA14
27
DDR_AD_MA0DDR_A_SMA0
36
45
18
DDR_AD_D34DDR_A_D34
27
DDR_AD_DM4DDR_A_DM4
36
DDR_AD_DQS4DDR_A_DQS4
45
DDR_AD_D33
18
DDR_AD_D32DDR_A_D32
27
DDR_AD_D37DDR_A_D37
36
DDR_AD_D36DDR_A_D36
45
DDR_AD_D40DDR_A_D40
18
DDR_AD_D41DDR_A_D41
27
DDR_AD_D39DDR_A_D39
36
DDR_AD_D38
45
DDR_AD_DM5
18
27
DDR_AD_D45DDR_A_D45
36
DDR_AD_D44DDR_A_D44DDR_A_D10
45
18
27
DDR_AD_D42DDR_A_D42
36
DDR_AD_D43DDR_A_D43
45
DDR_AD_D53DDR_A_D53
18
27
DDR_AD_D48DDR_A_D48
36
45
DDR_AD_D50
18
DDR_AD_D51DDR_A_D51
27
DDR_AD_DM6
36
DDR_AD_DQS6
45
DDR_AD_D63DDR_A_D63
18
DDR_AD_D62
27
DDR_AD_D58DDR_A_D58
36
DDR_AD_D59DDR_A_D59
45
DDR_AD_D56
18
DDR_AD_D57DDR_A_D57
27
DDR_AD_D55DDR_A_D55
36
DDR_AD_D54DDR_A_D54 DDR_A_SMA0
45
DDR_AD_DM7DDR_A_DM7
18
DDR_AD_DQS7DDR_A_DQS7
27
DDR_AD_D61DDR_A_D61
36
DDR_AD_D60
45
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
4
DDR_CLK016
DDR_CLK0#16
SMDATA14,16,26
SMCLK14,16,26
+2.5V +2.5V +2.5V +2.5V
DDR_AD_D0
DDR_AD_D1
DDR_AD_DQS0
DDR_AD_D2
DDR_AD_D3
DDR_AD_D8
DDR_AD_D9
DDR_AD_DQS1
DDR_AD_D10
DDR_AD_D11
DDR_AD_D16
DDR_AD_D17
DDR_AD_DQS2
DDR_AD_D18
DDR_AD_D19
DDR_AD_D24
DDR_AD_D25
DDR_AD_DQS3
DDR_AD_D26
DDR_AD_D27
DDR_AD_CKE1
DDR_AD_MA12
DDR_AD_MA9
DDR_AD_MA7
DDR_AD_MA5
DDR_AD_MA3
DDR_AD_MA1
DDR_AD_MA10
DDR_AD_MA13
DDR_AD_WE#
DDR_AD_CS0#
DDR_AD_MA15
DDR_AD_D32
DDR_AD_D33
DDR_AD_DQS4
DDR_AD_D34
DDR_AD_D35
DDR_AD_D40
DDR_AD_D41
DDR_AD_DQS5
DDR_AD_D42
DDR_AD_D43
DDR_AD_D48
DDR_AD_D49
DDR_AD_DQS6
DDR_AD_D50
DDR_AD_D51
DDR_AD_D56
DDR_AD_D57
DDR_AD_DQS7
DDR_AD_D58
DDR_AD_D59
+3VS
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
JAE_MM50-200B1-F1
Place Add/Command resisotrs
L
Close to Pin, max L = 300 mils
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDRA_VREF
DDR_AD_D4
DDR_AD_D5
DDR_AD_DM0
DDR_AD_D6
DDR_AD_D7
DDR_AD_D12
DDR_AD_D13
DDR_AD_DM1
DDR_AD_D14
DDR_AD_D15
DDRA_VREF trace width of
L
20mils and space 20mils(min)
DDR_AD_D20
DDR_AD_D21
DDR_AD_DM2
DDR_AD_D22
DDR_AD_D23
DDR_AD_D28
DDR_AD_D29
DDR_AD_DM3
DDR_AD_D30
DDR_AD_D31
DDR_AD_CKE0
DDR_AD_MA11
DDR_AD_MA8
DDR_AD_MA6
DDR_AD_MA4
DDR_AD_MA2
DDR_AD_MA0
DDR_AD_MA14
DDR_AD_RAS#
DDR_AD_CAS#
DDR_AD_CS1#
DDR_AD_D36
DDR_AD_D37
DDR_AD_DM4
DDR_AD_D38
DDR_AD_D39
DDR_AD_D44
DDR_AD_D45
DDR_AD_DM5
DDR_AD_D46
DDR_AD_D47
DDR_AD_D52
DDR_AD_D53
DDR_AD_DM6
DDR_AD_D54
DDR_AD_D55
DDR_AD_D60
DDR_AD_D61
DDR_AD_DM7
DDR_AD_D62
DDR_AD_D63
2
2
1
2
1
DDR_CLK1# 16
DDR_CLK1 16
C267
C269
+1.25VS
+1.25VS
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
+1.25VS
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
+1.25VS
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1
RP30
RP28
RP34
RP46
RP43
RP36
RP33
RP52
RP50
RP49
RP37
RP40
RP38
DDR_AD_D50
DDR_AD_D51
DDR_AD_DM6
DDR_AD_DQS6
DDR_AD_DM7
DDR_AD_DQS7
DDR_AD_D61
DDR_AD_D60
DDR_AD_D40
DDR_AD_D41
DDR_AD_D39
DDR_AD_D38
DDR_AD_D19
DDR_AD_D18
DDR_AD_DM2
DDR_AD_DQS2
DDR_AD_D30
DDR_AD_D31
DDR_AD_D27
DDR_AD_D26
DDR_AD_D33
DDR_AD_D32
DDR_AD_D37
DDR_AD_D36
DDR_AD_DM5
DDR_AD_DQS5
DDR_AD_D45
DDR_AD_D44
DDR_AD_D0
DDR_AD_D1
DDR_AD_D5
DDR_AD_D4
DDR_AD_D13
DDR_AD_D12
DDR_AD_D2
DDR_AD_D3
DDR_AD_DM1
DDR_AD_DQS1
DDR_AD_D9
DDR_AD_D8
DDR_A_SWE#
DDR_A_SCS0#
DDR_A_SCS1#
DDR_A_SCAS#
DDR_A_SMA3
DDR_A_SMA2
DDR_A_SMA7
DDR_A_SMA5
DDR_A_SRAS#
DDR_A_SMA14
of
13 52, 18, 2005
C
12
0.1U_0402_10V6K
12
0.1U_0402_10V6K
DDR_AD_D53
DDR_AD_D52
R149
DDR_AD_D48
DDR_AD_D49
1K_0603_1%
DDR_AD_D63
R147
DDR_AD_D62
DDR_AD_D58
1K_0603_1%
DDR_AD_D59
DDR_AD_D56
DDR_AD_D57
DDR_AD_D55
DDR_AD_D54
DDR_AD_D20
DDR_AD_D21
DDR_AD_D17
DDR_AD_D16
DDR_AD_DM3
DDR_AD_DQS3
DDR_AD_D28
DDR_AD_D29
DDR_AD_D35
DDR_AD_D34
DDR_AD_DM4
DDR_AD_DQS4
DDR_AD_D47
DDR_AD_D46
DDR_AD_D42
DDR_AD_D43
DDR_AD_D7
DDR_AD_D6
DDR_AD_DQS0
DDR_AD_DM0
DDR_AD_D25
DDR_AD_D24
DDR_AD_D22
DDR_AD_D23
DDR_AD_D15
DDR_AD_D14
DDR_AD_D11
DDR_AD_D10
DDR_A_SMA9
DDR_A_SCKE0
DDR_A_SMA11
DDR_A_SCKE1
DDR_A_SMA10
DDR_A_SMA13
DDR_A_SMA15
DDR_A_SMA1
DDR_A_SMA4
DDR_A_SMA12
DDR_A_SMA8
DDR_A_SMA6
Title
Size Document Number Rev
Date: Sheet
星期五 二月
RP31
56_0804_8P4R_5%
RP27
56_0804_8P4R_5%
RP29
56_0804_8P4R_5%
RP47
56_0804_8P4R_5%
RP44
56_0804_8P4R_5%
RP35
56_0804_8P4R_5%
RP32
56_0804_8P4R_5%
RP51
56_0804_8P4R_5%
RP45
56_0804_8P4R_5%
RP48
56_0804_8P4R_5%
RP42
33_0804_8P4R_5%
RP39
33_0804_8P4R_5%
RP41
33_0804_8P4R_5%
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
5
4
3
2
1
DDR_B_SMA[0..15]10
DDR_B_DM[0..7]10
DDR_B_D[0..63]10
DDR_B_DQS[0..7]10
D D
DDR_B_SRAS#10
DDR_B_SCKE010
DDR_B_SCS0#10
DDR_B_SWE#10
DDR_B_SCAS#10
DDR_B_SCS1#10
C C
DDR_B_D3
DDR_B_DM0 DDR_BD_DM0
DDR_B_DQS0 DDR_BD_DQS0
DDR_B_D4
DDR_B_D5
DDR_B_D1 DDR_BD_D1 DDR_B_DQS4 DDR_BD_DQS4
DDR_B_D0
DDR_B_D11
DDR_B_D10
DDR_B_D14 DDR_BD_D14
DDR_B_DQS1 DDR_BD_DQS1
B B
A A
DDR_B_DM1
DDR_B_D12
DDR_B_D20 DDR_BD_D20
DDR_B_D21 DDR_BD_D21
DDR_B_D17 DDR_BD_D17
DDR_B_D16
DDR_B_D22
DDR_B_D23
DDR_B_DQS2 DDR_BD_DQS2
DDR_B_DM2
DDR_B_D25 DDR_BD_D25
DDR_B_D24
DDR_B_D19 DDR_BD_D19
DDR_B_D18 DDR_BD_D18 DDR_BD_D50DDR_B_D50
DDR_B_DM3
DDR_B_DQS3 DDR_BD_DQS3
DDR_B_D29
DDR_B_D31 DDR_BD_D31
DDR_B_D30 DDR_BD_D30
DDR_B_D27
DDR_B_D26
DDR_B_SMA[0..15]
DDR_B_DM[0..7]
DDR_B_D[0..63]
DDR_B_DQS[0..7]
DDR_B_SMA14
DDR_B_SRAS#
DDR_B_SMA13
DDR_B_SMA10
DDR_B_SMA8 DDR_BD_MA8
DDR_B_SCKE0 DDR_BD_CKE0
RP64 10_0804_8P4R_5%
RP67 10_0804_8P4R_5%
DDR_B_SMA0 DDR_BD_MA0
DDR_B_SMA1
DDR_B_SMA3
DDR_B_SCS0# DDR_BD_CS0#
DDR_B_SWE# DDR_BD_WE#
DDR_B_SCAS#
RP77 10_0804_8P4R_5%
18
27
36
45
RP78 10_0804_8P4R_5%
18
27
36
45
RP76 10_0804_8P4R_5%
18
27
36
45
RP74 10_0804_8P4R_5%
18
27
36
45
RP75 10_0804_8P4R_5%
18
27
36
45
RP73 10_0804_8P4R_5%
18
27
36
45
RP72 10_0804_8P4R_5%
18
27
36
45
RP71 10_0804_8P4R_5%
18
27
36
45
RP70 10_0804_8P4R_5%
18
27
36
45
RP69 10_0804_8P4R_5%
18
27
36
45
5
18
27
36
45
18
27
36
45
DDR_BD_D3
DDR_BD_D2DDR_B_D2
DDR_BD_D4
DDR_BD_D5
DDR_BD_D0
DDR_BD_D9DDR_B_D9
DDR_BD_D8DDR_B_D8
DDR_BD_D7DDR_B_D7
DDR_BD_D6DDR_B_D6
DDR_BD_D11
DDR_BD_D10
DDR_BD_D15DDR_B_D15
DDR_BD_DM1
DDR_BD_D13DDR_B_D13
DDR_BD_D12
DDR_BD_D16
DDR_BD_D22
DDR_BD_D23
DDR_BD_DM2
DDR_BD_D24
DDR_BD_DM3
DDR_BD_D29
DDR_BD_D28DDR_B_D28
DDR_BD_D27
DDR_BD_D26
DDR_BD_MA14
DDR_BD_RAS#
DDR_BD_MA13
DDR_BD_MA10
DDR_BD_MA6DDR_B_SMA6
DDR_BD_MA11DDR_B_SMA11
RP65 10_0804_8P4R_5%
RP63 10_0804_8P4R_5%
18
27
36
45
18
27
36
45
DDR_B_SMA5
DDR_B_SMA7 DDR_BD_MA7
DDR_B_SMA15 DDR_BD_MA15
DDR_B_SMA9
DDR_B_SMA12 DDR_BD_MA12
DDR_B_SCKE110
DDR_BD_MA2DDR_B_SMA2
DDR_BD_MA1
DDR_BD_MA3
DDR_BD_CAS#
DDR_BD_CS1#DDR_B_SCS1#
RP62 10_0804_8P4R_5%
DDR_B_D32 DDR_BD_D32
DDR_B_D33
DDR_B_D37 DDR_BD_D37
DDR_B_D36
RP61 10_0804_8P4R_5%
DDR_B_D39 DDR_BD_D39
DDR_B_D38
DDR_B_DM4 DDR_BD_DM4
RP60 10_0804_8P4R_5%
DDR_B_D41
DDR_B_D40 DDR_BD_D40
DDR_B_D35 DDR_BD_D35
RP58 10_0804_8P4R_5%
DDR_B_D43
DDR_B_D42 DDR_BD_D42
DDR_B_D46 DDR_BD_D46
DDR_B_D47
RP59 10_0804_8P4R_5%
DDR_B_DQS5
DDR_B_DM5 DDR_BD_DM5
DDR_B_D44
DDR_B_D45
RP57 10_0804_8P4R_5%
DDR_B_D49 DDR_BD_D49
DDR_B_D48 DDR_BD_D48
DDR_B_D52
DDR_B_D53
RP56 10_0804_8P4R_5%
DDR_B_D54 DDR_BD_D54
DDR_B_D55
DDR_B_DQS6 DDR_BD_DQS6
DDR_B_DM6 DDR_BD_DM6
RP55 10_0804_8P4R_5%
DDR_B_D51
RP53 10_0804_8P4R_5%
DDR_B_D59 DDR_BD_D59
DDR_B_D58
DDR_B_D62 DDR_BD_D62
DDR_B_D63 DDR_BD_D63
RP54 10_0804_8P4R_5%
DDR_B_DQS7 DDR_BD_DQS7
DDR_B_DM7 DDR_BD_DM7
DDR_B_D57
DDR_B_D56 DDR_BD_D56
DDR_B_SCKE1 DDR_BD_CKE1
18
DDR_BD_D33
27
36
DDR_BD_D36
45
18
DDR_BD_D38
27
36
45
DDR_BD_D41
18
27
36
DDR_BD_D34DDR_B_D34
45
DDR_BD_D43
18
27
36
DDR_BD_D47
45
DDR_BD_DQS5
18
27
DDR_BD_D44
36
DDR_BD_D45
45
18
27
DDR_BD_D52
36
DDR_BD_D53
45
18
DDR_BD_D55
27
36
45
DDR_BD_D60DDR_B_D60
18
DDR_BD_D61DDR_B_D61
27
DDR_BD_D51
36
45
18
DDR_BD_D58
27
36
45
18
27
DDR_BD_D57
36
45
RP66 10_0804_8P4R_5%
RP68 10_0804_8P4R_5%
4
DDR_BD_MA4DDR_B_SMA4
18
DDR_BD_MA5
27
36
45
DDR_BD_MA9
18
27
36
45
+1.25VS
+2.5V +2.5V +2.5V +2.5V
JDIM2
1
VREF
3
DDR_BD_D0
DDR_BD_D1
DDR_BD_DQS0
DDR_BD_D2
DDR_BD_D3
DDR_BD_D8
DDR_BD_D9
DDR_BD_DQS1
DDR_BD_D10
DDR_BD_D11
DDR_CLK316
DDR_CLK3#16
DDR_BD_D16
DDR_BD_D17
DDR_BD_DQS2
DDR_BD_D18
DDR_BD_D19
DDR_BD_D24
DDR_BD_D25
DDR_BD_DQS3
DDR_BD_D26
DDR_BD_D27
DDR_BD_CKE1
DDR_BD_MA12
DDR_BD_MA9
DDR_BD_MA7
DDR_BD_MA5
DDR_BD_MA3
DDR_BD_MA1
DDR_BD_MA10
DDR_BD_MA13
DDR_BD_WE#
DDR_BD_CS0#
DDR_BD_MA15
DDR_BD_D32
DDR_BD_D33
DDR_BD_DQS4
DDR_BD_D34
DDR_BD_D35
DDR_BD_D40
DDR_BD_D41
DDR_BD_DQS5
DDR_BD_D42
DDR_BD_D43
DDR_BD_D48
DDR_BD_D49
DDR_BD_DQS6
DDR_BD_D50
DDR_BD_D51
DDR_BD_D56
DDR_BD_D57
DDR_BD_DQS7
DDR_BD_D58
DDR_BD_D59
SMDATA13,16,26
SMCLK13,16,26
+3VS
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
JAE_MM50-200B1-F1R
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDRB_VREF
DDR_BD_D4
DDR_BD_D5
DDR_BD_DM0
DDR_BD_D6
DDR_BD_D7
DDR_BD_D12
DDR_BD_D13
DDR_BD_DM1
DDR_BD_D14
DDR_BD_D15
DDRA_VREF trace width of
L
20mils and space 20mils(min)
DDR_BD_D20
DDR_BD_D21
DDR_BD_DM2
DDR_BD_D22
DDR_BD_D23
DDR_BD_D28
DDR_BD_D29
DDR_BD_DM3
DDR_BD_D30
DDR_BD_D31
DDR_BD_CKE0
DDR_BD_MA11
DDR_BD_MA8
DDR_BD_MA6
DDR_BD_MA4
DDR_BD_MA2
DDR_BD_MA0
DDR_BD_MA14
DDR_BD_RAS#
DDR_BD_CAS#
DDR_BD_CS1#
DDR_BD_D36
DDR_BD_D37
DDR_BD_DM4
DDR_BD_D38
DDR_BD_D39
DDR_BD_D44
DDR_BD_D45
DDR_BD_DM5
DDR_BD_D46
DDR_BD_D47
DDR_CLK4# 16
DDR_BD_D52
DDR_BD_D53
DDR_BD_DM6
DDR_BD_D54
DDR_BD_D55
DDR_BD_D60
DDR_BD_D61
DDR_BD_DM7
DDR_BD_D62
DDR_BD_D63
DDR_CLK4 16
+3VS
2
12
2
1
2
1
R428
1K_0603_1%
C697
0.1U_0402_10V6K
12
R434
1K_0603_1%
C694
0.1U_0402_10V6K
DDR_BD_D54
DDR_BD_D55
DDR_BD_DQS6
DDR_BD_DM6
56_0804_8P4R_5%
DDR_BD_DQS7
DDR_BD_DM7
DDR_BD_D57
DDR_BD_D56
56_0804_8P4R_5%
DDR_BD_D60
DDR_BD_D61
DDR_BD_D51
DDR_BD_D50
56_0804_8P4R_5%
DDR_BD_D20
DDR_BD_D21
DDR_BD_D17
DDR_BD_D16
56_0804_8P4R_5%
DDR_BD_D31
DDR_BD_D30
DDR_BD_D27
DDR_BD_D26
56_0804_8P4R_5%
DDR_BD_D39
DDR_BD_D38
DDR_BD_DQS4
DDR_BD_DM4
56_0804_8P4R_5%
DDR_BD_D43
DDR_BD_D42
DDR_BD_D46
DDR_BD_D47
56_0804_8P4R_5%
DDR_BD_D3
DDR_BD_D2
DDR_BD_DM0
DDR_BD_DQS0
56_0804_8P4R_5%
DDR_BD_D25
DDR_BD_D24
DDR_BD_D19
DDR_BD_D18
56_0804_8P4R_5%
DDR_BD_D11
DDR_BD_D10
DDR_BD_D14
DDR_BD_D15
56_0804_8P4R_5%
DDR_B_SMA14
DDR_B_SMA1
DDR_B_SMA0
DDR_B_SMA3
33_0804_8P4R_5%
DDR_B_SMA13
DDR_B_SRAS#
DDR_B_SMA10
DDR_B_SMA2
33_0804_8P4R_5%
DDR_B_SMA6
DDR_B_SMA11
DDR_B_SCKE0
DDR_B_SMA9
33_0804_8P4R_5%
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
RP118
RP120
RP119
RP107
RP111
RP113
RP116
RP103
RP109
RP106
RP81
RP80
RP83
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
+1.25VS
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
+1.25VS+1.25VS
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1
RP117
RP121
RP112
RP108
RP110
RP114
RP115
RP102
RP105
RP104
RP79
RP82
RP84
DDR_BD_D49
DDR_BD_D48
DDR_BD_D52
DDR_BD_D53
DDR_BD_D59
DDR_BD_D58
DDR_BD_D62
DDR_BD_D63
DDR_BD_D32
DDR_BD_D33
DDR_BD_D37
DDR_BD_D36
DDR_BD_D22
DDR_BD_D23
DDR_BD_DQS2
DDR_BD_DM2
DDR_BD_DM3
DDR_BD_DQS3
DDR_BD_D29
DDR_BD_D28
DDR_BD_D41
DDR_BD_D40
DDR_BD_D35
DDR_BD_D34
DDR_BD_DQS5
DDR_BD_DM5
DDR_BD_D44
DDR_BD_D45
DDR_BD_D4
DDR_BD_D5
DDR_BD_D1
DDR_BD_D0
DDR_BD_DQS1
DDR_BD_DM1
DDR_BD_D13
DDR_BD_D12
DDR_BD_D9
DDR_BD_D8
DDR_BD_D7
DDR_BD_D6
DDR_B_SCS0#
DDR_B_SWE#
DDR_B_SCAS#
DDR_B_SCS1#
DDR_B_SMA4
DDR_B_SMA5
DDR_B_SMA7
DDR_B_SMA8
DDR_B_SMA12
DDR_B_SMA15
DDR_B_SCKE1
of
14 52, 18, 2005
C
5
4
3
2
1
Layout note :
Distribute as close as possible
to DDR-SODIMM0.
Layout note :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V +2.5V
D D
C C
1
+
C268
220U_D2_4VM
2
1
C260
0.1U_0402_10V6K
2
+1.25VS
1
C277
0.1U_0402_10V6K
2
1
C258
0.1U_0402_10V6K
2
1
C253
0.1U_0402_10V6K
2
1
C256
0.1U_0402_10V6K
2
1
C254
0.1U_0402_10V6K
2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25VS
1
C297
0.1U_0402_10V6K
2
1
C283
0.1U_0402_10V6K
2
1
C266
0.1U_0402_10V6K
2
1
C255
0.1U_0402_10V6K
2
1
C298
0.1U_0402_10V6K
2
1
C264
0.1U_0402_10V6K
2
1
C251
0.1U_0402_10V6K
2
1
C282
0.1U_0402_10V6K
2
1
C250
0.1U_0402_10V6K
2
1
C263
0.1U_0402_10V6K
2
1
C275
0.1U_0402_10V6K
2
1
C257
0.1U_0402_10V6K
2
1
C265
0.1U_0402_10V6K
2
1
C294
0.1U_0402_10V6K
2
1
C252
0.1U_0402_10V6K
2
1
C261
0.1U_0402_10V6K
2
1
C288
0.1U_0402_10V6K
2
1
C262
0.1U_0402_10V6K
2
1
C259
0.1U_0402_10V6K
2
1
C280
0.1U_0402_10V6K
2
1
2
1
2
1
C291
0.1U_0402_10V6K
2
+
C244
220U_D2_4VM
C315
0.1U_0402_10V6K
1
C316
0.1U_0402_10V6K
2
1
C312
0.1U_0402_10V6K
2
1
C318
0.1U_0402_10V6K
2
1
C311
0.1U_0402_10V6K
2
1
C308
0.1U_0402_10V6K
2
1
C324
0.1U_0402_10V6K
2
1
C314
0.1U_0402_10V6K
2
1
C310
0.1U_0402_10V6K
2
1
C307
0.1U_0402_10V6K
2
1
C309
0.1U_0402_10V6K
2
1
C319
0.1U_0402_10V6K
2
1
C323
0.1U_0402_10V6K
2
1
C313
0.1U_0402_10V6K
2
1
C332
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C325
2
0.1U_0402_10V6K
1
C317
2
+1.25VS
1
C279
0.1U_0402_10V6K
2
1
C286
0.1U_0402_10V6K
2
1
C281
0.1U_0402_10V6K
2
1
C299
0.1U_0402_10V6K
2
1
C329
0.1U_0402_10V6K
2
1
C734
0.1U_0402_10V6K
2
1
C719
0.1U_0402_10V6K
2
1
C722
0.1U_0402_10V6K
2
1
C723
0.1U_0402_10V6K
2
+1.25VS
B B
1
C721
0.1U_0402_10V6K
2
1
C328
0.1U_0402_10V6K
2
1
C293
0.1U_0402_10V6K
2
1
C326
0.1U_0402_10V6K
2
+1.25VS
1
C292
0.1U_0402_10V6K
2
1
C718
0.1U_0402_10V6K
2
1
C290
0.1U_0402_10V6K
2
1
C289
0.1U_0402_10V6K
2
1
C729
0.1U_0402_10V6K
2
1
C285
0.1U_0402_10V6K
2
1
C726
0.1U_0402_10V6K
2
+1.25VS
1
C731
0.1U_0402_10V6K
2
A A
+1.25VS
1
C284
0.1U_0402_10V6K
2
1
C732
0.1U_0402_10V6K
2
1
C296
0.1U_0402_10V6K
2
5
1
C735
0.1U_0402_10V6K
2
1
C300
0.1U_0402_10V6K
2
1
C287
0.1U_0402_10V6K
2
1
C295
0.1U_0402_10V6K
2
1
C736
0.1U_0402_10V6K
2
1
C278
0.1U_0402_10V6K
2
4
1
C331
0.1U_0402_10V6K
2
1
C276
0.1U_0402_10V6K
2
1
C330
0.1U_0402_10V6K
2
1
C327
0.1U_0402_10V6K
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
星期五 二月
of
1
15 52, 18, 2005
C
5
4
3
2
1
+3VS_CLK
29
13
19
30
48
VDDSD
VDDAGP
GNDREF
GNDPCI
5
18
VDD48M
GNDPCI
24
25
9
1
VDDPCI
VDDPCI
VDDREF
FS3/PCICLK_F0
FS4/PCICLK_F1
GNDSD
GND48M
GNDAGP
46
41
33
VDDXTAL
SDRAMOUT
GNDCPU
ICS951402AGT_TSSOP48
XIN
XOUT
SCLK
SDATA
VTTPWRGD/PD#
CPU_STP#
PCI_STOP#
24/48#SEL
PCI33/66#SEL
48MHz_1
48MHz_0
FS2/REF2
FS1/REF1
FS0/REF0
IREF
FS1
FS0
FS2
FS3
FS4
PCI33/66#
42
VDDCPU
GNDXTAL
8
D D
14.31818MHZ_20P_6X1430004201
SMCLK13,14,26
SMDATA13,14,26
VTT_PWRGD26,28
PM_STPCPU#6,9,25,48
PCI_STP#25
C C
B B
REFCLK1_NB9
CLK_14M_CODEC35
CLK_SB_14M26
CLK_14M_SIO38
C644
2.2P_0402_50V8C
1 2
12
Y3
1 2
C645
2.2P_0402_50V8C
R363 0_0402_5%
1 2
R369 0_0402_5%
1 2
R385 10K_0402_5%
1 2
1 2
T30 PAD
R364 20_0402_5%
1 2
R12 33_0402_5%
1 2
R358 33_0402_5%
1 2
1 2
R603
33_0402_5%@
+3VS
R600
10K_0402_5%
VTT_PWRGD
2
G
2N7002_SOT23
@
12
13
D
S
XTALIN_CLK
12
R354
@
10K_0402_5%
XTALOUT_CLK
R386
Q35
VTT_PWRGD
PCI33/66#
10K_0402_5%@
CLK_48M
CLK_IREF
R372
475_0402_1%
1 2
CLKEN# 48
U29
6
7
35
34
10
45
12
26
11
27
28
FS2
4
FS1
3
FS0
2
38
+3VS_CLK
12
12
12
R345
CPU_BSEL17,11
CPU_BSEL07,11
A A
FS4 With Spread Enabled…
0 0 0 1 0
0 0 0 0 1
**
0 0 0 0 0
CLOCK FREQUENCY SELECT TABLE
FS1 MEMFS2
FS3 FS0
5
CPU
200
133
100
21
D16 CH751H-40_SC76
21
D15 CH751H-40_SC76
200
*
133
Spreaf OFF OR
Center spread +/-0.3%
100
10K_0402_5%
R343
10K_0402_5%
12
R346
4.7K_0402_5%
A-LINK FREQ
**
4
+3VS_VDDA
36
VDDA
37
VSSA
40
CPUT0
39
CPUC0
44
CPUT1
43
CPUC1
47
32
AGPCLK0
31
AGPCLK1
14
15
16
PCICLK0
17
PCICLK1
20
PCICLK2
21
PCICLK3
22
PCICLK4
23
PCICLK5
12
R350
@
12
R344
R342
4.7K_0402_5%
PCI33/66# = HIGH
Note:
0 = PULL LOW
1 = PULL HIGH
VSSA
CLK_CPU_CLK
CLK_CPU_CLK#
CLK_NB
CLK_NB#
MEM_66M
AGP_66M
AGP_EXT_66M
FS3
FS4
12
@
10K_0402_5%
12
10K_0402_5%
66MHZ
33MHZPCI33/66# = LOW
1 2
R367
33_0402_5%
1 2
R370 33_0402_5%
1 2
R356
33_0402_5%
1 2
R360 33_0402_5%
1 2
R352 33_0402_5%
R374 33_0402_5%
1 2
R377 33_0402_5%
1 2
R373 33_0402_5%
1 2
POP For 150G
DEPOP For 150A
+3VS_CLK
12
12
R348
R347
@
10K_0402_5%
10K_0402_5%
12
12
R339
R340
10K_0402_5%
@
10K_0402_5%
+3VS +3VS_CLK
1
C649
2
10U_0805_10V4Z
C303
VSSA
100P_0402_25V8K
0.1U_0402_10V6K
C661
0.1U_0402_10V6K
1
2
R368
1 2
49.9_0402_1%
1 2
R371 49.9_0402_1%
R357
1 2
49.9_0402_1%
1 2
R361 49.9_0402_1%
CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6
CLK_NB_BCLK 9
CLK_NB_BCLK# 9
CLK_MEM_66M 9
CLK_AGP_66M 9
CLK_AGP_EXT_66M 17
CLK_ALINK_SB 25
1 2
L37
CHB2012U121_0805
+3VS +3VS_VDDA
1 2
L41
CHB2012U121_0805
CLK.BUFFER
1
C243
AVDD
VDD2.5
2
C223
2
0.1U_0402_10V6K
110_0402_5%
0.1U_0402_10V6K
+2.5VS
12
L26
CHB2012U121_0805
AVDD
R349
10K_0402_5%
R341
10K_0402_5%
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C220
0.1U_0402_10V6K
2
MEMA_CLK010
MEMA_CLK0#10
SMCLK13,14,26
SMDATA13,14,26
R134
1 2
R141 1.5K_0402_5%
1 2
R142 2.2K_0402_5%
1 2
Width=40 mils
1
1
C662
2
2
0.1U_0402_10V6K
1
C675
C673
2
10U_0805_10V4Z
0.1U_0402_10V6K
1
C242
2
16
4
12
15
21
28
33
37
45
35
36
13
14
32
34
1
9
18
24
25
31
40
48
17
0.1U_0402_10V6K
1
C657
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C668
2
0.1U_0402_10V6K
1
C646
2
1
C272
2
0.1U_0402_10V6K
C648
0.1U_0402_10V6K
1
C301
2
1
C663
2
100P_0402_25V8K
1
2
100P_0402_25V8K
2200P_0402_25V7K
1
1
C651
2
2
2200P_0402_25V7K
1
C271
2
C664
100P_0402_25V8K
C270
VDD2.5
0.1U_0402_10V6K
1
1
C219
C221
2
2
0.1U_0402_10V6K
U10
ICS9P750_TSSOP48
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SCLK
SDATA
CLK_INT
CLK_INC
RSTEP
RSPO
GND
GND
GND
GND
GND
GND
GND
GND
AGND
ICS9P750-T_TSSOP48
POWER
GROUND
Title
Size Document Number Rev
Date: Sheet
星期五 二月
1
1
C222
2
2
0.1U_0402_10V6K
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
DDRT6
DDRC6
DDRT7
Differential pair output
DDRC7
DDRT8
DDRC8
DDRT9
DDRC9
DDRT10
DDRC10
DDRT11
DDRC11
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2522
401318
3
2
5
6
11
10
20
19
22
23
8
7
44
43
38
39
29
30
27
26
47
46
42
41
1 2
L25
CHB2012U121_0805
1
C224
22U_1206_10V4Z
2
1
2200P_0402_25V7K
1
C647
2
1
2
+2.5VS
DDR_CLK0 13
DDR_CLK0# 13
DDR_CLK1 13
DDR_CLK1# 13
DDR_CLK3 14
DDR_CLK3# 14
DDR_CLK4 14
DDR_CLK4# 14
of
16 52, 18, 2005
1
2
C
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