Compal LA-2501, Inspiron 9200 Schematic

5

4

3

2

1

D D

Gilbert

REV : A00

@ : Nopop Component

C C

B B

Dothan Schematic with Capture CIS and Function field

uFCPGA Dothan

10-04-2004

A A

REV: 1.0

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2501

148Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

Compal confidential

HA#(3..31)

Dothan/Banias

uFCPGA CPU

System Bus

400MHz

Odem-B
MCH-M

593 FC-BGA

page 10,11,12

page 7,8,9

HD#(0..63)

Memory
BUS(DDRI)

2.5V 333MHz

SO-DIMM X2

BANK 0, 1, 2, 3

page 14,15

GUARDIAN

D D

EMC6N300

page 13

CRT CONN.

& TV-OUT

VGA

page 17

Board

AGP4X

VGA CONN.

C C

page 16

Block Diagram

Clock Generator

CK408M

page 6

Fan Control

page 13

LED/B

page 35

DC IN

page 37

MINI PCI

page 30

PCI BUS

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

3.3V 33MHz

LAN
BCM4401

CardBus Controller

B B

RICHO R5C841

page 28,29

page 26

Transformer

SDIO CONN.

page 29

1394 CONN.

page 28

Slot 0

page 29

& RJ45

page 27

LPC BUS

3.3V 33MHz

GPIO

X BUS

LCM CONN.

page33

A A

Multi-media

SST39VF080

page 33

Touch Pad

page 33

Hub Link

ICH4M

421 BGA

Macallan III

LPC to X-BUS
& Super I/O

page 31,32

page 18,19,20,21

48MHz / 480Mbps

Int.KBD

page 33

3.3V 14.318MHz

ATA100

CDROM

USB2.0

page 25

page 25

ATA100

HDD

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5

page 19

JUSB3 U
JUSB3 D
Blue Tooth

NEW CARD

JUSB2 U
JUSB2 D

Board

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

MDC

page 24

AC-LINK

AC97 CODEC

STAC9750

AMP &

Phone Jack

page 23

BATT IN/+2.5V

page 38

1.5V/1.05V(+VCCP)

page 39

5V/3.3V/15V

page 22

page 40

2.5V / 1.25V

Subwoofer

page 24

VCORE

page 41

page 42

CHARGER

page 43

1.2V/1.8V

page 44

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2501

248Tuesday, October 05, 2004

1

of

1.0

5

D D

4

3

2

1

PM TABLE

C C

power
plane

State

S0

S1

S3

S5 S4/AC

B B

S5 S4/AC don't exist

+3VALW
+5VALW

ON

ON

ON

ON

+3VSUS
+5VSUS
+2.5V_MEM
+1.5VSUS
+15V

ON ON

ON

ON

OFF

OFFOFF

+5VRUN
+3VRUN
+1.8VRUN
+1.5VRUN
+1.2VRUN
+VCC_CORE
+VCCP
V_1P25V_DDR_VTT

ON

OFF

OFF

OFF

PCI TABLE

PCI DEVICE

CARD BUS

MINI PCI

IDSEL

AD17

AD19

REQ#/GNT#

1

3

LAN AD16 4 C

PIRQ

B,C,D

D,B

USB TABLE

USB PORT#0DESTINATION

JUSB3 (Top)
1
2
3
4

JUSB3 (Bottom)

Blue Tooth

NEW CARD

JUSB2 (Top)
5 JUSB2 (Bottom)

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-2501

348Tuesday, October 05, 2004

1

1.0

of

5

D D

4

3

2

1

+5VALW

ADAPTER

PWR_SRC

+3VALW

BATTERY

C C

SUS_ON

+5VSUS

B B

+5VHDD +5VMOD +5VRUN VDDA

A A

RUN_ON

PL11, PD15

+15V +2.5VRUN

(Option)

AUDIO_AVDD_ON

+3VRUN

L25

SUS_ON

+3VSRC

RUN_ON

V3P3LAN

SUSPWROK_5V

+3VSUS

RUN_ON_D

+1.8VRUN

+VCC_CORE

RUN_ON_D

RUN_ON

+1.2VRUN

RUNPWROK

+1.5VSUS

RUN_ON SUSPWROK_1.5V

+1.5VRUN

RUNPWROK

+VCCP

SUSPWROK_5V

SUSPWROK_5V

+2.5VSUSP V_1P25V_DDR_VTT

PJP11,PJP12

+2.5V_MEM

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail

LA-2501

448Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

ICH_SMBCLK

D D

ICH4M

ICH_SMBDATA

+3VSUS

7002

+3VRUN

7002

CK_SCLK
CK_SDATA

CLK GEN.

DIMM1DIMM0

CLK_SMB
DAT_SMB

C C

+3VALW

GUARDIAN

24C04

Device Address

SIO

LPC47N354
Macallan III

SMBCLK_VGA
SMBDAT_VGA +5VALW VGA

ICH4M-SMBus

DIM0

DIM1

CLK GEN.

GUARDIAN

A0h

A2h

D2h

5Eh

B B

EC-SMBus

PBAT_SMBCLK
PBAT_SMBDAT +5VALW BATTERY

24C04

VGA

Battery

Charger

A2h

58h

16h

12h

CHARGER

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY

LA-2501

548Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

D
1

3

G

S

2

2N7002

D D

ICH_SMBDATA<19>

ICH_SMBCLK<19>

ICH_SMBDATA

+3VRUN

ICH_SMBCLK

+3VRUN

D

1 3

1 3

D

S

G

2

2

G

S

12

R118

R117

Q9

2.2K_0402_5%~D

2N7002_SOT23~D

Q10
2N7002_SOT23~D

12

2.2K_0402_5%~D

CK_SDATA

CK_SCLK

S2 S1 S0 CPU 3V66[0..4] 3V66_5/66IN
1 0 0 66 66IN 66 Input
1 0 1 100 66IN 66 Input

+3VRUN

BLM11A601S_0603~D

1 2

1 1 0 200 66IN 66 Input
1 1 1 133 66IN 66 Input

C C

0 0 0 66 66 66 Input
0 0 1 100 66 66 Input

*

0 1 0 200 66 66 Input

+3VRUN

1 2

BLM21PG600SN1D_0805~D

CK_SDATA <14,15>

CK_SCLK <14,15>

W=20 mils

L21

1

C401
10U_0805_10V4M~D

2

L20

CLK_VDD_CORE

1

2

CK_VDD_MAIN

C57

0.1U_0402_16V4Z~D

CK_VDD_MAIN

2

C42
10U_0805_10V4M~D

1

1

C78

0.1U_0402_10V6K~D

2

U7

1

VDD_REF

8

VDD_PCI

14

VDD_PCI

19

VDD_3V66

32

VDD_3V66

46

VDD_CPU

50

VDD_CPU

37

VDD_48MHZ

26

VDD_CORE

27

GND_CORE

0 1 1 133 66 66 Input

Mid

0
0

Mid
Mid

1

Mid

12

B B

R398
1K_0402_5%~D@

12

R395
0_0402_5%~D@

0

0
1

+VCCP+VCCP

Hi-z
TCLK/21
Reserve1
Reserve

12

R394
1K_0402_5%~D@

12

R400

0_0402_5%~D@

Hi-z
TCLK/2
Reserve
Reserve

+3VRUN

R571

1K_0402_5%~D

1 2

R574

1K_0402_5%~D

@

1 2

CPU_BSEL0 <8>
CPU_BSEL1 <8>

TCLK/2
Reserve
Reserve

+3VRUN

1 2

1 2

Hi-z

R572
1K_0402_5%~D

@

R575
1K_0402_5%~D

+3VRUN

1 2

1 2

R573
1K_0402_5%~D

@

R576
1K_0402_5%~D

CK_VDD_MAIN

12

R569
10K_0402_5%~D

R570
1K_0402_5%~D

@

1 2

C83

18P_0402_50V8J~D

C77

18P_0402_50V8J~D

H_STP_CPU#<20,42>

H_STP_PCI#<20>

CLK_ENABLE#<42>

ICH_SLP_S1#<20>

Please closely pin42

R385

1 2

475_0603_1%~D

12

12

Y1 14.31818MHz_20P_1BX14318CC1A~D

12

Place crystal within
500 mils of CK408

H_STP_CPU#

H_STP_PCI#
CLK_ENABLE#
ICH_SLP_S1#

CK_SCLK
CK_SDATA

MULT0

CLKIREF

CLKSEL0
CLKSEL1
CLKSEL2
CK_XTAL_OUT

CK_XTAL_IN

Dothan B only

A A

12

R577

2M_0603_5%~D

53

CPU_STOP#

34

PCI_STOP#

28

VTT_PWRGD#

25

PWR_DWN#

30

SCLK

29

SDATA

43

MULT0

42

IREF

54

SEL0

55

SEL1

40

SEL2

3

XTAL_OUT

@

2

XTAL_IN

4

GND_REF

9

GND_PCI

15

GND_PCI

20

GND_3V66

31

GND_3V66

36

GND_48MHZ

41

GND_IREF

47

GND_CPU

CY28346ZCT_TSSOP56~D

Place near each pin
W>40 mil

1

C49

0.1U_0402_10V6K~D

2

1

C89

0.1U_0402_10V6K~D

2

CK408

Rev 1.1

1

C62

0.1U_0402_10V6K~D

2

1

C69

0.1U_0402_10V6K~D

2

PCICLK_F0
PCICLK_F1
PCICLK_F2

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

CPUCLKT2

CPUCLKC2

3V66_0/DRCG

48MHZ_DOT

48MHZ_USB

3V66_1/VCH_CLK

66MHZ_IN/3V66_5

66MHZ_OUT0/3V66_2

66MHZ_OUT1/3V66_3

66MHZ_OUT2/3V66_4

REF

5
6
7

10
11
12
13
16
17
18

52

51

49

48

45

44

56

33

38
39

35
24
21

22

23

1

C44

0.1U_0402_10V6K~D

2

1

C72

0.1U_0402_10V6K~D

2

PCICLK_F2

PCICLK1 CK_33M_SIOPCI
PCICLK2

PCICLK5
PCICLK6 CK_33M_MINIPCI

CK_CPU0

CK_CPU0#

CK_CPU1

CK_CPU1#

CK_CPU2

CK_CPU2#

CLKREF

CLK48M_OUT0

CLK66M_OUT0

CLK66M_OUT2

CLK66M_OUT3

1

C53

0.1U_0402_10V6K~D

2

R83

1 2

33_0402_5%~D

R95

1 2

33_0402_5%~D
R123

1 2

33_0402_5%~D

R93

1 2

33_0402_5%~D
R106

1 2

33_0402_5%~D

R81

1 2

33_0402_5%~D
R80

1 2

49.9_0402_1%~D
R76

1 2

33_0402_5%~D
R75

1 2

R59

1 2

33_0402_5%~D
R58

1 2

R54

1 2

33_0402_5%~D
R53

1 2

R71

1 2

33_0402_5%~D
R70

1 2

R66

1 2

33_0402_5%~D
R65

1 2

49.9_0402_1%~D

R116

1 2

33_0402_5%~D
R112

1 2

10_0402_5%~D
R122

1 2

10_0402_5%~D
R84

1 2

33_0402_5%~D

R578

1 2

33_0402_5%~D
R579

1 2

33_0402_5%~D
R580

1 2

33_0402_5%~D

CK_33M_ICHPCI

CK_33M_LANPCI

CK_33M_CBPCI

CK_BCLK

CK_BCLK#

49.9_0402_1%~D

CK_ITP

49.9_0402_1%~D

CK_ITP#

49.9_0402_1%~D

CK_MCH_BCLK

49.9_0402_1%~D

CK_MCH_BCLK#

CK_14M_ICH

CK_14M_SIO

CK_14M_CODEC

CK_48M_ICH

CK_66M_ICH

CK_66M_MCH

CK_66M_AGP

CK_33M_ICHPCI <18>

CK_33M_SIOPCI <31>
CK_33M_LANPCI <26>

CK_33M_CBPCI <28>
CK_33M_MINIPCI <30>

CK_BCLK <7>

CK_BCLK# <7>

CK_ITP <7>

CK_ITP# <7>

CK_MCH_BCLK <10>

CK_MCH_BCLK# <10>

Place near CK408

CK_14M_ICH <19>

CK_14M_SIO <31>

CK_14M_CODEC <22>

CK_48M_ICH <19>

CK_66M_ICH <19>

CK_66M_MCH <10>

CK_66M_AGP <16>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator

LA-2501

648Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

H_A#[3..31]<10>

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<10>

H_ADSTB#0<10>

H_RS#[0..2]<10>

1 2

R9

H_ADSTB#1<10>

CK_BCLK<6>
CK_BCLK#<6>

H_ADS#<10>

H_BNR#<10>

H_BPRI#<10>

H_BR0#<10>

H_DEFER#<10>

H_DRDY#<10>

H_HIT#<10>
H_HITM#<10>

H_LOCK#<10>
H_RESET#<10>

ITP_DBRESET#<35>

H_DBSY#<10>

H_DPSLP#<11,18>

H_PROCHOT#<32>

H_PWRGOOD<18>

H_CPUSLP#<18>

1K_0402_5%~D@

1 2
1 2

@

1K_0402_5%~D

H_THERMDA<13>
H_THERMDC<13>
H_THERMTRIP#<13,20>

T29 PAD~D
T30 PAD~D

H_TRDY#<10>

H_DPWR#<11>

R99

R717

C C

R92

56_0402_5%~D

1 2

+VCCP

B B

DPRSLPVR<20,42>

0_0402_5%~D@

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22

H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_CK_ITP
CPU_CK_ITP#

CK_BCLK
CK_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSLPVRDPRSLPVR

ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO

TEST1

TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

JCPUA

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

AMP_1473129-1~D

Dothan

ADDR GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

DATA GROUP

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#

FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>

H_A20M# <18>

H_FERR# <18>

H_IGNNE# <18>

H_INIT# <18>

H_INTR <18>

H_NMI <18>

H_STPCLK# <18>

H_SMI# <18>

H_D#0H_A#3

A19

H_D#[0..63] <10>

H_RESET#

ITP_TDO

H_DSTBN#[0..3] <10>

H_DSTBP#[0..3] <10>

R20

22.6_0603_1%~D

1 2

CK_ITP<6>
CK_ITP#<6>

1 2

R31

22.6_0603_1%~D

Check ITP connector.

+VCCP

ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CK_ITP

CK_ITP#

ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

29

JITP

28

VTT1

27

GND6

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

GND7

MOLEX_52435-2891_28P~D@

30

+3VSUS

R11

150_0402_5%~D

1 2

+VCCP

R36

54.9_0603_1%~D

1 2

R19

54.9_0603_1%~D

1 2

+VCCP

R61

39.2_0603_1%~D

1 2

R62

150_0402_5%~D

1 2

R45

680_0402_5%~D

1 2

R44

27.4_0603_1%~D

1 2

+VCCP

1

C20

0.1U_0402_10V7K~D

2

Place near JITP

ITP_DBRESET#

H_RESET#

ITP_TMS

ITP_TDI

This shall place near CPU

ITP_TRST#

ITP_TCK

A A

Placed near CPU

CK_BCLK

CK_BCLK#

C936

12

2.2P_0402_50V8C~D@
C937

12

2.2P_0402_50V8C~D@

5

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(1/2)

LA-2501

748Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

R208

54.9_0603_1%~D@

+VCCA_PROC

+1.5VRUN

D D

C C

PJP3

2 1

PAD-OPEN 2x2m~D

SHORT

C117

0.01U_0402_16V7K~D

C122

1

2

Layout Note:
500 mil max length

+VCCP

B B

Layout close CPU

V_CPU_GTLREF

R_A

12

R201
1K_0603_1%~D

R_B

12

R203
2K_0603_1%~D

12

12

12

R416

R417

27.4_0603_1%~D

R426

54.9_0603_1%~D

12

Resistor placed within

0.5" of CPU pin.Trace

R427

27.4_0603_1%~D

54.9_0603_1%~D

should be at least 25
miles away from any
other toggling signal.

10U_0805_4VAM~D

1

2

H_PSI#<42>

VID0<42>
VID1<42>
VID2<42>
VID3<42>
VID4<42>
VID5<42>

54.9_0603_1%~D@

+VCC_CORE

V_CPU_GTLREF

CPU_BSEL0<6>
CPU_BSEL1<6>

1 2
1 2

R207

+VCCP

H_PSI#
VID0

VID1
VID2
VID3
VID4
VID5

T42 PAD~D
T43 PAD~D
T44 PAD~D
T45 PAD~D

VCCSENSE
VSSSENSE

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

JCPUB

AE7
AF6

F26

B1

N1

AC26

P23
W4

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16

K6
L5

L21

M6

M22

N5

N21

P6

P22

R5

R21

T6
T22
U21

D6

D8
D18
D20
D22

E5
E7

E9
E17
E19
E21

F6

F8
F18

E1

E2

F2

F3

G3
G4
H4

AD26

C16
C14

P25
P26
AB2
AB1

B2

C3
E26
AF7
AC1

AMP_1473129-1~D

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

VCCQ0
VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF

BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD
RSVD

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JCPUC

F20
F22

G5

G21

H6

H22

J5
J21
K22

U5
V6

V22

W5

W21

Y6
Y22
AA5
AA7
AA9

AA11
AA13
AA15
AA17
AA19
AA21

AB6
AB8

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8
AF10
AF12
AF14
AF16
AF18

M4

M5
M21
M24

N3

N6
N22
N23
N26

P2

P5
P21
P24

R1

R4

R6
R22
R25

T3

T5

T21
T23

AMP_1473129-1~D

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(2/2)

LA-2501

848Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

+VCC_CORE

1

C213
10U_0805_4VAM~D

D D

C C

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C463
10U_0805_4VAM~D

C165
10U_0805_4VAM~D

C214
10U_0805_4VAM~D

1

C138
10U_0805_4VAM~D

2

1

C464
10U_0805_4VAM~D

2

1

C127
10U_0805_4VAM~D

2

1

C465
10U_0805_4VAM~D

2

1

C128
10U_0805_4VAM~D

2

1

C208
10U_0805_4VAM~D

2

1

C166
10U_0805_4VAM~D

2

1

C209
10U_0805_4VAM~D

2

1

C139
10U_0805_4VAM~D

2

1

C163
10U_0805_4VAM~D

2

1

C215
10U_0805_4VAM~D

@

2

1

C466
10U_0805_4VAM~D

2

1

C212
10U_0805_4VAM~D

2

1

C168
10U_0805_4VAM~D

2

1

C211
10U_0805_4VAM~D

2

1

C210
10U_0805_4VAM~D

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C167
10U_0805_4VAM~D

C443
10U_0805_4VAM~D

C144
10U_0805_4VAM~D

1

C526
10U_0805_4VAM~D

2

1

C532
10U_0805_4VAM~D

@

2

1

C441
10U_0805_4VAM~D

2

10uF 0805 X6S -> (-55 ~ 105C, +/-22%) degree

1

C528
10U_0805_4VAM~D

2

1

C527
10U_0805_4VAM~D

2

1

C531
10U_0805_4VAM~D

2

1

C530
10U_0805_4VAM~D

2

1

C440
10U_0805_4VAM~D

2

1

C525
10U_0805_4VAM~D

@

2

1

C529
10U_0805_4VAM~D

2

1

C207
10U_0805_4VAM~D

@

2

1

C444
10U_0805_4VAM~D

2

X6S

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

@

@

330U_D2E_2.5VM_R9~D

C85

1

+

2

330U_D2E_2.5VM_R9~D

C665

ESR <= 3m ohm
Capacitor > 880 uF

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

1

C415

B B

+VCCA_PROC

C938

1

2

0.1U_0402_16V4Z~D
C939

0.1U_0402_16V4Z~D
C940

1

1

2

2

C941

C942

C943

1

1

2

2

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_4VAM~D

10U_0805_4VAM~D

C944

1

2

10U_0805_4VAM~D

C945

1

1

2

2

+

2

1

C416

+

+

2

2

+VCCP

1

+

C160
150U_D2_6.3VM~D

2

A A

1

C446

0.1U_0402_10V7K~D

2

1

C447

0.1U_0402_10V7K~D

2

1

C448

0.1U_0402_10V7K~D

2

1

C457

0.1U_0402_10V7K~D

2

1

C452

0.1U_0402_10V7K~D

2

1

C437

0.1U_0402_10V7K~D

2

1

C436

0.1U_0402_10V7K~D

2

1

C432

0.1U_0402_10V7K~D

2

1

C435

0.1U_0402_10V7K~D

2

1

C445

0.1U_0402_10V7K~D

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Bypass

LA-2501

948Tuesday, October 05, 2004

1

1.0

of

5

U15A

H_A#[3..31]<7>

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

B B

A A

H_ADSTB#1<7>

CK_MCH_BCLK#<6>
CK_MCH_BCLK<6>

H_ADS#<7>

H_TRDY#<7>

H_DRDY#<7>

H_DEFER#<7>

H_HITM#<7>
H_HIT#<7>
H_LOCK#<7>

H_BR0#<7>

H_BNR#<7>

H_BPRI#<7>

H_DBSY#<7>

H_RS#[0..2]<7>

H_DSTBN#[0..3]<7>

H_DSTBP#[0..3]<7>

H_RESET#<7>

H_DINV#0<7>
H_DINV#1<7>
H_DINV#2<7>
H_DINV#3<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CK_MCH_BCLK#
CK_MCH_BCLK

H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_RS#0
H_RS#1
H_RS#2

H_RESET#

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

U6
T5
R2
U3
R3
P7
T3
P4
P3
P5
R6
N2
N5
N3

J3
M3
M4
M5

L5
K3

J2

N6
L6
L2
K5
L3
L7
K4

J5

U2
T7
R7
U5
T4

R5
N7

K8

J8

U7
V4

W2

Y4
Y3
Y5

W3

V7
V3
Y7

V5
W7
W5
W6

AE17

AD4

AF6
AD11
AC15

AD3

AG6
AE11
AC16

AD5

AG5

AH9
AD15

RG82855PM_UFCBGA593

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

BCLK#
BCLK

ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BR0#
BNR#
BPRI#
DBSY#
RS#0
RS#1
RS#2

CPURST#

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
DBI#0
DBI#1
DBI#2
DBI#3

Odem

HOST

HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

HSWNG1
HSWNG0

HRCOMP1
HRCOMP0

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

4

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AE5
AF3
AC6
AC3
AF4
AE2
AG4
AG2
AE7
AE8
AH2
AC7
AG3
AD7
AH7
AE6
AC8
AG8
AG7
AH3
AF8
AH5
AC11
AC12
AE9
AC10
AE10
AD9
AG9
AC9
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

M7
P8
AA9
AB12

220P_0603_50V8J~D

AB16

H_SWNG1

AD13

H_SWNG0

AA7

H_RCOMP1

AC13

H_RCOMP0

AC2

27.4_0603_1%~D

C671

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1

2

220P_0603_50V8J~D

R593

1 2

C667

0.01U_0402_16V7K~D

H_SWNG1

C669

0.01U_0402_16V7K~D

H_SWNG0

MCH_GTLREF

1

2

C672

Placed near MCH

CK_MCH_BCLK

CK_MCH_BCLK#

H_D#[0..63] <7>

+VCCP

1

2

+VCCP

1

2

+VCCP

1

C673

1U_0805_10V6K~D

2

R594

27.4_0603_1%~D

1 2

C676

2.2P_0402_50V8C~D@

C677

2.2P_0402_50V8C~D@

12

12

12

12

12

R590

49.9_0603_1%~D

12

R591
100_0603_1%~D

12

12

R582
301_0402_1%~D

R583
150_0402_1%~D

R586
301_0402_1%~D

R587
150_0402_1%~D

3

R596
1K_0603_1%~D

R597
1K_0603_1%~D

+1.5VRUN

12

R_M

R_N

1 2

2

G_AD[0..31]<16>

G_C/BE#[0..3]<16>

G_FRAME#<16>
G_DEVSEL#<16>
G_IRDY#<16>
G_TRDY#<16>
G_STOP#<16>
G_PAR<16>

G_REQ#<16>

G_GNT#<16>

G_AD_STB0<16>
G_AD_STB0#<16>
G_AD_STB1<16>
G_AD_STB1#<16>

G_SBA[0..7]<16>

G_SB_STB<16>
G_SB_STB#<16>

G_RBF#<16>

G_WBF#<16>

G_PIPE#<16>

G_ST0<16>
G_ST1<16>
G_ST2<16>

CK_66M_MCH<6>

VREFCG <16>

12

R598

0_0402_5%~D@

VREFGC <16>

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#

G_AD_STB0
G_AD_STB0#
G_AD_STB1
G_AD_STB1#

G_SBA0
G_SBA1
G_SBA2
G_SBA3
G_SBA4
G_SBA5
G_SBA6
G_SBA7

G_SB_STB
G_SB_STB#

G_RBF#
G_WBF#
G_PIPE#

G_ST0
G_ST1
G_ST2

CK_66M_MCH

12

1

@

2

U15B

R27

GAD0

R28

GAD1

T25

GAD2

R25

GAD3

T26

GAD4

T27

GAD5

U27

GAD6

U28

GAD7

V26

GAD8

V27

GAD9

T23

GAD10

U23

GAD11

T24

GAD12

U24

GAD13

U25

GAD14

V24

GAD15

Y27

GAD16

Y26

GAD17

AA28

GAD18

AB25

GAD19

AB27

GAD20

AA27

GAD21

AB26

GAD22

Y23

GAD23

AB23

GAD24

AA24

GAD25

AA25

GAD26

AB24

GAD27

AC25

GAD28

AC24

GAD29

AC22

GAD30

AD24

GAD31

V25

GCBE#0

V23

GCBE#1

Y25

GCBE#2

AA23

GCBE#3

Y24

GFRAME#

W28

GDEVSEL#

W27

GIRDY#

W24

GTRDY#

W23

GSTOP#

W25

GPAR

AG24

GREQ#

AH25

GGNT#

R24

AD_STB0

R23

AD_STB#0

AC27

AD_STB1

AC28

AD_STB#1

AH28

SBA0

AH27

SBA1

AG28

SBA2

AG27

SBA3

AE28

SBA4

AE27

SBA5

AE24

SBA6

AE25

SBA7

AF27

SB_STB

AF26

SB_STB#

AE22

RBF#

AE23

WBF#

AF22

PIPE#

AG25

ST0

AF24

ST1

AG26

ST2

P22

66IN

RG82855PM_UFCBGA593
R595
22_0402_5%~D@

C675
10P_0402_50V8J~D

Odem

AGP

HUB

GND

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9

HI_10

HI_STB

HI_STB#

HLRCOMP

HI_REF

VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

GRCOMP

AGPREF

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

N25
N24

P27
P26

AB9
AD10
AF9
AJ9
A7
F8
J7
L8
N8
R8
U8
W8
AA8
AD8
AF7
AJ7
D5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
AF5
AJ5
A3
J4
L4
N4
R4
U4
W4
AA4
AC4
AE4
AJ3
E1
J1
L1
N1
R1
U1
W1
AA1
AC1
AE1
AG1

AD25
AA21

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

HUB_HLSTRB
HUB_HLSTRB#

HUB_RCOMP
HL_REF

C666

0.01U_0402_16V7K~D

AGP_RCOMP

1

C674

0.1U_0603_16V7K~D

2

1 2

1

2

36.5_0603_1%~D

1 2

HUB_HLSTRB <18>
HUB_HLSTRB# <18>

R581

36.5_0603_1%~D

150_0402_1%~D

R_C

150_0402_1%~D

R_D

R592

VREFGC <16>

1

HUB_HL[0..10] <18>

+1.8VRUN

+1.8VRUN

12

R584

HL_REF

12

R589

2

C668

1

HLREF_TERMHHLREF_TERML

R585

56.2_0402_1%~D@

1 2

R588
0_0402_5%~D

1 2

1

C670

2

470P_0402_50V7K~D@

0.01U_0402_16V7K~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Odem(1/3)

LA-2501

10 48Tuesday, October 05, 2004

1

1.0

of

5

NEED CHECK THIS POWER

1

+15V

O

1 2

8

IN+

4

R601
0_0402_5%~D@

PLANE

U39A
LM358M_SO8~D@

3

P

2

IN-

G

D D

NEED CHECK THIS POWER
PLANE

DDR_VREF_MCH

10U_0805_10V4M~D@

C C

B B

C679

1

2

+2.5V_MEM

12

12

R600

R599
10K_0603_1%~D@

10K_0603_1%~D@

4

1

C678

0.1U_0603_16V7K~D@

2

+15V

8

U39B
LM358M_SO8~D@

5

P

IN+

7

O

6

IN-

G

4

V_DDR_MCH_REF<14,15,41>

DDR_VREF_MCH

R602

0_0603_5%~D

1 2

1

C680

2

0.1U_0603_16V7K~D

3

C681

DDR_MA[0..12]<14,15>

1

2

0.1U_0603_16V7K~D

T46
PAD

DDR_DS[0..8]<14>

DDR_WE#<14,15>

CK_DDR_CK0#<14>
CK_DDR_CK1#<14>
CK_DDR_CK2#<14>
CK_DDR_CK3#<15>
CK_DDR_CK4#<15>
CK_DDR_CK5#<15>

DDR_CKE0_DIMM0<14>
DDR_CKE1_DIMM0<14>
DDR_CKE2_DIMM1<15>
DDR_CKE3_DIMM1<15>

DDR_CS0_DIMM0#<14>
DDR_CS1_DIMM0#<14>

DDR_CS2_DIMM1#<15>
DDR_CS3_DIMM1#<15>

V_1P25V_DDR_VTT

T48
PAD

T49
PAD

DDR_RAS#<14,15>
DDR_CAS#<14,15>

CK_DDR_CK0<14>
CK_DDR_CK1<14>
CK_DDR_CK2<14>
CK_DDR_CK3<15>
CK_DDR_CK4<15>
CK_DDR_CK5<15>

DDR_BS0<14,15>
DDR_BS1<14,15>

1

C682

0.1U_0603_16V7K~D

2

H_DPSLP#<7,18>

H_DPWR#<7>

DDR_CKE0_DIMM0
DDR_CKE1_DIMM0
DDR_CKE2_DIMM1
DDR_CKE3_DIMM1

DDR_CS0_DIMM0#
DDR_CS1_DIMM0#
DDR_CS2_DIMM1#
DDR_CS3_DIMM1#

R603

30.1_0603_1%~D

1 2

DDR_MA0
DDR_MA1
DDR_MA2
DDR_MA3
DDR_MA4
DDR_MA5
DDR_MA6
DDR_MA7
DDR_MA8
DDR_MA9
DDR_MA10
DDR_MA11
DDR_MA12

DDR_DS0
DDR_DS1
DDR_DS2
DDR_DS3
DDR_DS4
DDR_DS5
DDR_DS6
DDR_DS7
DDR_DS8

DDR_WE#
DDR_RAS#
DDR_CAS#

CK_DDR_CK0
CK_DDR_CK0#
CK_DDR_CK1
CK_DDR_CK1#
CK_DDR_CK2
CK_DDR_CK2#
CK_DDR_CK3
CK_DDR_CK3#
CK_DDR_CK4
CK_DDR_CK4#
CK_DDR_CK5
CK_DDR_CK5#

DDR_BS0
DDR_BS1

DDR_RCOMP

100mils

M_RCV#

AD26
AD27

E12
F17
E16
G17
G18
E18
F19
G20
G19
F21
F13
E20
G21
G22

F26
C26
C23
B19
D12

C8
C5

E3

E15

G11
F11

G8

J25
K25

G5

F5
G24
E24
G25
J24

G6

G7
K23
J23

G23
E22
H23
F23

E9
F7
F9
E7

G12
G13

J9

J21
J28
G15
G14

V8
Y8

2

U15C

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12
RSVD2

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SWE#
SRAS#
SCAS#

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

SCKE0
SCKE1
SCKE2
SCKE3

SCS#0
SCS#1
SCS#2
SCS#3

SBS0
SBS1

SMVREF0
SMVREF1

SMRCOMP
RCVENIN#
RCVENOUT#
DPSLP#

DPWR#
NC0
NC1

Odem

MEMORY

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8

SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71

RSTIN#

RSVD1

TESTIN#

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E4
C3
D3
F4
F3
B2
C2
E2
G4
C16
D16
B15
C14
B17
C17
C15
D14

J27
H27
H26

DDR_D0
DDR_D5
DDR_D3
DDR_D6
DDR_D1
DDR_D4
DDR_D2
DDR_D7
DDR_D8
DDR_D9
DDR_D15
DDR_D11
DDR_D13
DDR_D12
DDR_D10
DDR_D14
DDR_D16
DDR_D17
DDR_D18
DDR_D22
DDR_D20
DDR_D23
DDR_D21
DDR_D19
DDR_D24
DDR_D25
DDR_D29
DDR_D27
DDR_D28
DDR_D26
DDR_D30
DDR_D31
DDR_D32
DDR_D37
DDR_D38
DDR_D39
DDR_D33
DDR_D36
DDR_D34
DDR_D35
DDR_D44
DDR_D45
DDR_D46
DDR_D42
DDR_D40
DDR_D41
DDR_D43
DDR_D47
DDR_D48
DDR_D52
DDR_D51
DDR_D55
DDR_D49
DDR_D53
DDR_D54
DDR_D50
DDR_D56
DDR_D60
DDR_D62
DDR_D59
DDR_D57
DDR_D61
DDR_D58
DDR_D63
DDR_CB2
DDR_CB0
DDR_CB7
DDR_CB3
DDR_CB1
DDR_CB4
DDR_CB5
DDR_CB6

MCH_TEST#

PCIRST_MCH# <18>

1 2

R604

4.7K_0603_5%~D@

1

DDR_CB[0..7] <14>

+1.5VRUN

DDR_D[0..63] <14>

T47
PAD

RG82855PM_UFCBGA593

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Odem(2/3)

LA-2501

11 48Tuesday, October 05, 2004

1

1.0

of

5

U15D

+1.5VRUN

D D

+1.2VRUN

+1.8VRUN

C C

B B

+1.8VRUN

A A

one .01uf and 10
uf each two pins

1

C797

10U_0805_10V4M~D

2

+VCCP

+2.5V_MEM

1

C798

0.01U_0402_16V7K~D

2

5

R29

VCCAGP0

W29

VCCAGP1

AC29

VCCAGP2

AG29

VCCAGP3

U26

VCCAGP4

AA26

VCCAGP5

AE26

VCCAGP6

AJ25

VCCAGP7

AD23

VCCAGP8

AF23

VCCAGP9

R22

VCCAGP10

U22

VCCAGP11

W22

VCCAGP12

AA22

VCCAGP13

AB21

VCCAGP14

AD21

VCCAGP15

P17

VCC0

N16

VCC1

P15

VCC2

R16

VCC3

T15

VCC4

U16

VCC5

N14

VCC6

P13

VCC7

R14

VCC8

U14

VCC9

L29

VCCHL0

L25

VCCHL1

N26

VCCHL2

N23

VCCHL3

M22

VCCHL4

AG23

VCCP0

AJ23

VCCP1

AE21

VCCP2

AG21

VCCP3

AJ21

VCCP4

AB20

VCCP5

AC19

VCCP6

AD20

VCCP7

AE19

VCCP8

AF20

VCCP9

AG19

VCCP10

AJ19

VCCP11

AB18

VCCP12

AD18

VCCP13

AF18

VCCP14

AB14

VCCP15

AB10

VCCP16

M8

VCCP17

T8

VCCP18

AB8

VCCP19

C29

VCCSM0

G29

VCCSM1

A25

VCCSM2

D25

VCCSM3

K26

VCCSM4

D23

VCCSM5

H24

VCCSM6

K24

VCCSM7

L23

VCCSM8

A21

VCCSM9

F22

VCCSM10

H22

VCCSM11

K22

VCCSM12

D19

VCCSM13

H20

VCCSM14

A17

VCCSM15

F18

VCCSM16

H18

VCCSM17

D15

VCCSM18

F16

VCCSM19

H16

VCCSM20

A13

VCCSM21

F14

VCCSM22

H14

VCCSM23

D11

VCCSM24

H12

VCCSM25

A9

VCCSM26

F10

VCCSM27

H10

VCCSM28

D7

VCCSM29

H8

VCCSM30

K7

VCCSM31

A5

VCCSM32

E5

VCCSM33

H5

VCCSM34

J6

VCCSM35

C1

VCCSM36

G1

VCCSM37

T17

VCCGA

T13

VCCHA

RG82855PM_UFCBGA593

Odem

POWER GND

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90

RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

ETS#

4

E29
J29
N29
U29
AA29
AE29
A27
K27
AJ27
E26
G26
J26
L26
R26
W26
AC26
AF25
A23
F24
L24
M23
AC23
AH23
D21
H21
J22
L22
N22
T22
V22
Y22
AB22
AC21
AD22
AF21
AG22
AH21
A19
F20
H19
AB19
AC20
AD19
AE20
AF19
AG20
AH19
D17
H17
N17
R17
U17
AB17
AC18

1
AE18
AF17
AG18

2
AJ17

A15
F15
H15
N15
P16
R15
T16
U15
AB15
AD16
AF15
AJ15
D13
E14
H13
N13
P14
R13
T14
U13
AB13
AD14
AF13
AJ13
A11
F12
H11
AB11
AD12
AF11
AJ11
D9
H9

G16
G10
G9
H7
G2
G3

internal pull up

H3

H4

12

R606

4

C716

0.047U_0402_16V4Z~D

R605

10K_0402_5%~D@

1 2

1K_0402_5%~D@

1

2

+1.5VRUN

C683

150U_D2_4VK~D

C692

150U_D2_4VK~D

+1.8VRUN

C700

10U_0805_10V4M~D

+VCCP

C706

150U_D2_4VK~D

C717

1

+

2

1

+

2

1

2

1

+

2

0.047U_0402_16V4Z~D

+2.5V_MEM

3

C722

C742

C757

C771

C785

0.047U_0402_16V4Z~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

C687

2

0.01U_0402_16V7K~D

1

C696

2

0.015U_0402_16V7K~D

1

C710

2

0.1U_0402_16V4Z~D

1

2

C723

0.047U_0402_16V4Z~D

1

1

2

2

C743

0.1U_0402_10V6K~D

1

1

2

2

C758

0.1U_0402_10V6K~D

1

1

2

2

C772

0.1U_0402_10V6K~D

1

1

2

2

C786

0.1U_0402_10V6K~D

1

2

C744

C759

C773

C787

1

C688

2

0.01U_0402_16V7K~D

1

C697

2

0.01U_0402_16V7K~D

1

C711

2

0.1U_0402_16V4Z~D

1

2

C724

C725

0.047U_0402_16V4Z~D

1

1

2

2

C745

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

2

C760

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

2

C774

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

2

C788

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.047U_0402_16V4Z~D

C746

C761

C775

C789

C712

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_16V4Z~D

1

2

1

2

1

2

1

2

1

2

1

C689

2

0.01U_0402_16V7K~D

1

C698

2

0.022U_0402_16V7K~D

C726

C747

C762

C776

C790

0.047U_0402_16V4Z~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

C713

2

0.1U_0402_16V4Z~D

1

1

2

2

C727

0.047U_0402_16V4Z~D

1

1

2

2

C748

0.1U_0402_10V6K~D

1

1

2

2

C763

0.1U_0402_10V6K~D

1

1

2

2

C777

0.1U_0402_10V6K~D

1

1

2

2

C791

0.1U_0402_10V6K~D

1

2

C719

0.047U_0402_16V4Z~D

1

C685

2

10U_0805_10V4M~D

1

C694

2

2.2U_0805_16VFZ~D

1

C702

2

0.1U_0402_16V4Z~D

1

C708

2

0.1U_0402_16V4Z~D

1

2

C720

0.047U_0402_16V4Z~D

1

2

1

2

1

2

1

C684

2

10U_0805_10V4M~D

+1.2VRUN

1

+

C693

150U_D2_4VK~D

2

1

C701

2

0.1U_0402_16V4Z~D

1

C707

2

0.1U_0402_16V4Z~D

1

1

2

2

C718

0.047U_0402_16V4Z~D

C755

C769

C783

1

C686

2

0.01U_0402_16V7K~D

1

C695

2

0.22U_0603_10V7K~D

1

C703

2

0.1U_0402_16V4Z~D

1

C709

2

0.1U_0402_16V4Z~D

1

1

2

2

C721

0.047U_0402_16V4Z~D

1

1

2

2

C741

0.1U_0402_10V6K~D

1

1

2

2

C756

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

2

C770

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

2

C784

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

C690

C699

C728

C749

C764

C778

C792

0.01U_0402_16V7K~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

2

1

2

C714

0.1U_0402_16V4Z~D

1

2

C729

1

2

C750

1

2

C765

1

2

C779

1

2

C793

2

C691

0.01U_0402_16V7K~D

1

22U_1206_10V4Z~D

2

1

2

C730

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

2

C751

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

2

C766

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

2

C780

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

2

C794

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

1

2

+2.5V_MEM

C733

0.047U_0402_16V4Z~D

1

C705

2

1

1

2

2

C734

0.047U_0402_16V4Z~D

V_1P25V_DDR_VTT

10U_0805_10V4M~D

C753

1

C754

2

C735

1

2

0.047U_0402_16V4Z~D

1

2

10U_0805_10V4M~D

C736

1

2

0.047U_0402_16V4Z~D

1

1

2

2

C737

C738

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

V_1P25V_DDR_VTT

C739

0.047U_0402_16V4Z~D

1

2

+2.5V_MEM

C740

0.047U_0402_16V4Z~D

1

+

C715

2

150U_D2_4VK~D

1

C704

22U_1206_10V4Z~D

2

C731

C752

C767

C781

C795

0.047U_0402_16V4Z~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

2

1

2

1

2

1

2

1

2

C732

0.047U_0402_16V4Z~D

0402

C768

0.1U_0402_10V6K~D

C782

0.1U_0402_10V6K~D

C796

0.1U_0402_10V6K~D

1

2

1

2

1

2

1

2

1

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Odem(3/3)

LA-2501

12 48Tuesday, October 05, 2004

1

1.0

of

5

+15V

R104

100K_0402_5%~D

FAN1_PWM<32>

D D

FAN2_PWM<32>

C C

1 2

R111

100K_0402_5%~D

1 2

FAN1VREF
FAN1_VFB

1

C75

2

1U_0603_10V4Z~D

R483

1 2

150K_0402_5%~D

FAN2VREF
FAN2_VFB

1

C84

2

1U_0603_10V4Z~D

R96

1 2

150K_0402_5%~D

8

3

P

IN+

O

2

IN-

G

4

C583

2200P_0402_50V7K~D@

1 2

R481

100K_0402_5%~D

12

RB751V_SOD323~D

+15V

8

5

P

IN+

O

6

IN-

G

4

C74

2200P_0402_50V7K~D@

1 2

R82

100K_0402_5%~D

12

RB751V_SOD323~D

U4A
LM358M_SO8~D

U4B
LM358M_SO8~D

1

7

FAN1_ON

D18

1

C51

2

FAN2_ON

D5

4

+5VRUN

6

2

1

D

Q47

G

3

S

SI3456DV-T1_TSOP6~D

4 5

1000P_0402_50V7K~D

1000P_0402_50V7K~D

FAN1_VOUT

1 2

R716

0_0402_5%~D

FAN2_5V

FAN2_5V <16>
FAN2_TACH_FB <16>

1

1

+

C257

C560

2

2

2 1

47U_D_16VM_R70~D

@

+5VRUN

6

2

1

0.1U_0603_25V7K~D

2 1

D

Q7

G

3

S

SI3456DV-T1_TSOP6~D

4 5

1

1

+

C65

2

47U_D_16VM_R70~D

C64

@

2

3

JFAN1

1

1

2

2

3

3

MOLEX_53398-0390~D

CPU

FAN1

JFAN2

1

1

2

2

3

3

MOLEX_53398-0390~D

VGA

FAN2

+3VRUN

12

R476
10K_0402_5%~D

1

C559
1000P_0402_50V7K~D

@

2

+3VRUN

12

R57
10K_0402_5%~D

1

C54
1000P_0402_50V7K~D

@

2

2

FAN1 Control and Tachometer

FAN1_TACH <32>

FAN2 Control and Tachometer

FAN2_TACH <32>

1

C

B

E3

2

2222 SYMBOL(SOT23-NEW)

Note: +3VRUN leakage issue from ATI M22

THERMATRIP_VGA#

+3VRUN

OTEMP<16>

R37

1 2

2.2K_0402_5%~D

C

2

B

E

3 1

Q12
MMBT3904_SOT23~D

R47

1 2

0_0402_5%~D@

1

H_THERMDA<7>

B B

A A

H_THERMDC<7>

+3VSUS

+RTC_CELL

+3VSUS

2200P_0402_50V7K~D

R428

49.9_0603_1%~D

1 2

C496

0.1U_0402_16V4Z~D

1

2

5

C508

0.1U_0402_16V4Z~D

12

R421

51.1K_0603_1%~D

12

R418

12.1K_0603_1%~D

C505

1

2

R430

8.2K_0402_5%~D

1 2

1

2

SUSPWROK<20,35>

ICH_PWRGD#<35>

POWER_SW#<32,35>

DAT_SMB<32,33>
CLK_SMB<32,33>

C483

0.1U_0402_16V4Z~D

1

C478
2200P_0402_50V7K~D

2

1 2

R453 1K_0402_5%~D

+3VSUS_R

1 2

R444 1K_0402_5%~D

1 2

R433 1K_0402_5%~D

THERMATRIP2#

THERMATRIP_VGA#

1

2

R452

1 2

U25

1

THDAT_SMB

2

THCLK_SMB

13

SMBADDRSEL

18

REM_DIODE2_P

17

REM_DIODE2_N

4

+3VSUS

11

VSUS_PWRGD

10

+RTC_PWR3V

5

+3V_PWROK

21

POWER_SW

6

THERMTRIP1

7

THERMTRIP2

8

THERMTRIP3

22

VSET

14

HW_LOCK

3

VSS

EMC6N300_SSOP24~D

1K_0402_5%~D

4

ATF_INT

RESSERVED

REM_DIODE1_N
REM_DIODE1_P

THERMTRIP_SIO

THERM_STP

INTRUDER

VCP

+5VSUS

12

9

23

16

19
20

15
24

12

R424

2.21K_0603_1%~D

1

C489

2

2200P_0402_50V7K~D

+3VALW

12

ATF_INT# <31>

E

B

2

+5VSUS

12

R450
10K_0402_5%~D

3

Q40

C

MMBT3904_SOT23~D

1

5V_CAL_SIO# <31>

2

12

R475
10KB_0603_1%_TSM1A103F34D3R~D

13

D

Q46

2N7002_SOT23~D

REN_DIODE_NTHERMATRIP1#
REN_DIODE_P

R451
100K_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

G

S

1

C503

2

2200P_0402_50V7K~D

THERMTRIP_SIO <32>
THERM_STP# <40>
INTRUDER# <19>

Trace width = 10mil

+VCCP

R120

2.2K_0402_5%~D

1 2

MMBT3904_SOT23~D

H_THERMTRIP#<7,20>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

LA-2501

Date: Sheet

+3VSUS

12

R124

8.2K_0402_5%~D

THERMATRIP1#

1

C

E

3

12

1

C95

0.1U_0402_16V4Z~D

2

R386

8.2K_0402_5%~D

THERMATRIP2#

1

C406

0.1U_0402_16V4Z~D

2

2

B

Q8

+3VSUS

Compal Electronics, Inc.
Thermal sensor and Fan

13 48Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

DDR_D[0..63]<11>

DDR_D5

R850
R851
R852
R853

R756
R758
R760
R761

R858
R860
R862
R864

R762
R764
R766
R768

R721
R724
R770
R771
R772
R774

R870
R871
R872
R873

R778
R779
R780
R782

R878
R879
R880
R882

R786
R787
R788
R789

R888
R890
R892
R894

R896
R898
R900
R901
R902

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D

DDR_BS0<11,15>
DDR_BS1<11,15>
DDR_CAS#<11,15>
DDR_WE#<11,15>

DDR_RAS#<11,15>

DDR_D1
DDR_D4

D D

DDR_DS0
DDR_D6
DDR_D2

DDR_D9
DDR_D12
DDR_D8

DDR_D13
DDR_D10
DDR_D11

DDR_D15 DDR_D15_R
DDR_D14 DDR_D14_R
DDR_D22

C C

DDR_D21
DDR_D19
DDR_D18

DDR_D16
DDR_D20
DDR_D17

DDR_D23
DDR_D26
DDR_D29
DDR_D30

DDR_DS3
DDR_D25
DDR_D28

B B

DDR_D31
DDR_D27
DDR_CB7
DDR_CB3

DDR_DS8
DDR_CB1
DDR_CB4
DDR_CB0 DDR_CB0_R

DDR_CB6
DDR_CB2
DDR_CB5 DDR_CB5_R
DDR_MA0 DDR_MA0_R

A A

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12
12

DDR_BS0
DDR_BS1
DDR_CAS#
DDR_WE#
DDR_RAS#

5

DDR_D5_R
DDR_D1_R
DDR_D4_R
DDR_D0_RDDR_D0

DDR_DS0_R
DDR_D6_R
DDR_D2_R
DDR_D3_RDDR_D3

DDR_D9_R
DDR_D12_R
DDR_D8_R
DDR_D7_RDDR_D7

DDR_D13_R
DDR_D10_R
DDR_D11_R
DDR_DS1_RDDR_DS1

DDR_D22_R
DDR_D21_R
DDR_D19_R
DDR_D18_R

DDR_D16_R
DDR_D20_R
DDR_D17_R
DDR_DS2_RDDR_DS2

DDR_D23_R
DDR_D26_R
DDR_D29_R
DDR_D30_R

DDR_DS3_R
DDR_D25_R
DDR_D28_R
DDR_D24_RDDR_D24

DDR_D31_R
DDR_D27_R
DDR_CB7_R
DDR_CB3_R

DDR_DS8_R
DDR_CB1_R
DDR_CB4_R

DDR_CB6_R
DDR_CB2_R

DDR_D32

R754

DDR_D33
DDR_D36 DDR_D36_R

DDR_D35
DDR_D38
DDR_D34

DDR_D46
DDR_DS5
DDR_D42

DDR_D44
DDR_D40
DDR_D41 DDR_D41_R

DDR_D43
DDR_D47
DDR_D51
DDR_D54
DDR_D50
DDR_DS6

DDR_D48
DDR_D52
DDR_D53 DDR_D53_R
DDR_D49

DDR_D57 DDR_D57_R
DDR_D60
DDR_D56
DDR_D55

DDR_DS7
DDR_D61
DDR_D59 DDR_D59_R
DDR_D58

DDR_D63 DDR_D63_R
DDR_D62
DDR_MA7
DDR_MA11 DDR_MA11_R

DDR_MA12
DDR_MA9
DDR_MA4
DDR_MA5

DDR_MA8
DDR_MA6
DDR_MA3 DDR_MA3_R
DDR_MA1 DDR_MA1_R
DDR_MA2 DDR_MA2_RDDR_MA10 DDR_MA10_R

R904

10_0402_5%~D

R905

10_0402_5%~D

R906

10_0402_5%~D

R907

10_0402_5%~D

R908

10_0402_5%~D

10_0402_5%~D

R755

10_0402_5%~D

R757

10_0402_5%~D

R759

10_0402_5%~D

R854

10_0402_5%~D

R855

10_0402_5%~D

R856

10_0402_5%~D

R857

10_0402_5%~D

R859

10_0402_5%~D

R861

10_0402_5%~D

R863

10_0402_5%~D

R865

10_0402_5%~D

R763

10_0402_5%~D

R765

10_0402_5%~D

R767

10_0402_5%~D

R769

10_0402_5%~D

R722

10_0402_5%~D

R725

10_0402_5%~D

R866

10_0402_5%~D

R867

10_0402_5%~D

R868

10_0402_5%~D

R869

10_0402_5%~D

R773

10_0402_5%~D

R775

10_0402_5%~D

R776

10_0402_5%~D

R777

10_0402_5%~D

R874

10_0402_5%~D

R875

10_0402_5%~D

R876

10_0402_5%~D

R877

10_0402_5%~D

R781

10_0402_5%~D

R783

10_0402_5%~D

R784

10_0402_5%~D

R785

10_0402_5%~D

R726

10_0402_5%~D

R727

10_0402_5%~D

R886

10_0402_5%~D

R887

10_0402_5%~D

R889

10_0402_5%~D

R891

10_0402_5%~D

R893

10_0402_5%~D

R895

10_0402_5%~D

R897

10_0402_5%~D

R899

10_0402_5%~D

R728

10_0402_5%~D

R729

10_0402_5%~D

R903

10_0402_5%~D

DDR_BS0_R

12

DDR_BS1_R

12

DDR_CAS_R#

12

DDR_WE_R#

12

DDR_RAS_R#

12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12

12
12
12
12
12

DDR_D32_R
DDR_D33_R

DDR_DS4_RDDR_DS4

DDR_D35_R
DDR_D38_R
DDR_D34_R
DDR_D37_RDDR_D37

DDR_D46_R
DDR_DS5_R
DDR_D42_R
DDR_D39_RDDR_D39

DDR_D44_R
DDR_D40_R

DDR_D45_RDDR_D45

DDR_D43_R
DDR_D47_R
DDR_D51_R
DDR_D54_R
DDR_D50_R
DDR_DS6_R

DDR_D48_R
DDR_D52_R

DDR_D49_R

DDR_D60_R
DDR_D56_R
DDR_D55_R

DDR_DS7_R
DDR_D61_R

DDR_D58_R

DDR_D62_R
DDR_MA7_R

DDR_MA12_R
DDR_MA9_R
DDR_MA4_R
DDR_MA5_R

DDR_MA8_R
DDR_MA6_R

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

4

DDR_CB[0..7]<11>

DDR_DS[0..8]<11>

DDR_MA[0..12]<11,15>

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

V_1P25V_DDR_VTT

R718

1 2

56_0402_5%~D

R719

1 2

56_0402_5%~D

R720

1 2

56_0402_5%~D

R723

1 2

56_0402_5%~D

DDR_CKE0_DIMM0

DDR_CKE1_DIMM0

DDR_CS0_DIMM0#

DDR_CS1_DIMM0#

JDIM1

1

VREF

3

DDR_D0_R
DDR_D1_R

DDR_DS0_R
DDR_D2_R

DDR_D3_R
DDR_D8_R

DDR_D9_R
DDR_DS1_R

DDR_D10_R
DDR_D11_R

CK_DDR_CK0<11>

CK_DDR_CK0#<11>

CK_DDR_CK2<11>
CK_DDR_CK2#<11>

DDR_CKE1_DIMM0<11>

DDR_CS0_DIMM0#<11>

CK_SDATA<6,15>
CK_SCLK<6,15>

+2.5V_MEM

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CK_DDR_CK0
CK_DDR_CK0#

DDR_D16_R
DDR_D17_R

DDR_DS2_R
DDR_D18_R

DDR_D19_R
DDR_D24_R

DDR_D25_R
DDR_DS3_R

DDR_D26_R
DDR_D27_R

DDR_CB0_R
DDR_CB1_R

DDR_DS8_R
DDR_CB2_R

DDR_CB3_R

CK_DDR_CK2
CK_DDR_CK2#

DDR_CKE1_DIMM0 DDR_CKE0_DIMM0
DDR_MA12_R

DDR_MA9_R
DDR_MA7_R

DDR_MA5_R
DDR_MA3_R
DDR_MA1_R

DDR_MA10_R
DDR_BS0_R
DDR_WE_R# DDR_CAS_R#

DDR_D32_R
DDR_D33_R

DDR_DS4_R
DDR_D34_R

DDR_D35_R
DDR_D40_R

DDR_D41_R
DDR_DS5_R

DDR_D42_R
DDR_D43_R

DDR_D48_R
DDR_D49_R

DDR_DS6_R
DDR_D50_R

DDR_D51_R
DDR_D56_R

DDR_D57_R
DDR_DS7_R

DDR_D58_R
DDR_D59_R

CK_SDATA
CK_SCLK

+3VSUS

R607

1 2

10K_0402_5%~D

DIMM0_ID

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

FOX_ASOA426-B2S-TR~D

STANDARD

DU/RESET#

DIMM0

VREF

DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD
RAS#

CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

VSS

A11

BA1

S1#

SA0
SA1
SA2

A8
A6

A4
A2
A0

DU

DU

+2.5V_MEM+2.5V_MEM

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

C799

0.1U_0402_16V4Z~D

V_DDR_MCH_REF
DDR_D4_R

DDR_D5_R

DDR_D6_R
DDR_D7_R

DDR_D12_R
DDR_D13_R

DDR_D14_R
DDR_D15_R

DDR_D20_R
DDR_D21_R

DDR_D22_R
DDR_D23_R

DDR_D28_R
DDR_D29_R

DDR_D30_R
DDR_D31_R

DDR_CB4_R
DDR_CB5_R

DDR_CB6_R
DDR_CB7_R

DDR_MA11_R
DDR_MA8_R

DDR_MA6_R
DDR_MA4_R
DDR_MA2_R
DDR_MA0_R

DDR_BS1_R
DDR_RAS_R#

DDR_CS1_DIMM0#DDR_CS0_DIMM0#

DDR_D36_R
DDR_D37_R

DDR_D38_R
DDR_D39_R

DDR_D44_R
DDR_D45_R

DDR_D46_R
DDR_D47_R

CK_DDR_CK1#
CK_DDR_CK1

DDR_D52_R
DDR_D53_R

DDR_D54_R
DDR_D55_R

DDR_D60_R
DDR_D61_R

DDR_D62_R
DDR_D63_R

12

V_DDR_MCH_REF <11,15,41>

2

C800

0.1U_0402_16V4Z~D

1

DDR_CKE0_DIMM0 <11>

DDR_CS1_DIMM0# <11>

CK_DDR_CK1# <11>

CK_DDR_CK1 <11>

DDR_D0_R
DDR_D1_R
DDR_D2_R
DDR_D3_R
DDR_D4_R
DDR_D5_R
DDR_D6_R
DDR_D7_R
DDR_D8_R
DDR_D9_R
DDR_D10_R
DDR_D11_R
DDR_D12_R
DDR_D13_R
DDR_D14_R
DDR_D15_R
DDR_D16_R
DDR_D17_R
DDR_D18_R
DDR_D19_R
DDR_D20_R
DDR_D21_R
DDR_D22_R
DDR_D23_R
DDR_D24_R
DDR_D25_R
DDR_D26_R
DDR_D27_R
DDR_D28_R
DDR_D29_R
DDR_D30_R
DDR_D31_R
DDR_D32_R
DDR_D33_R
DDR_D34_R
DDR_D35_R
DDR_D36_R
DDR_D37_R
DDR_D38_R
DDR_D39_R
DDR_D40_R
DDR_D41_R
DDR_D42_R
DDR_D43_R
DDR_D44_R
DDR_D45_R
DDR_D46_R
DDR_D47_R
DDR_D48_R
DDR_D49_R
DDR_D50_R
DDR_D51_R
DDR_D52_R
DDR_D53_R
DDR_D54_R
DDR_D55_R
DDR_D56_R
DDR_D57_R
DDR_D58_R
DDR_D59_R
DDR_D60_R
DDR_D61_R
DDR_D62_R
DDR_D63_R

DDR_CB0_R
DDR_CB1_R
DDR_CB2_R
DDR_CB3_R
DDR_CB4_R
DDR_CB5_R
DDR_CB6_R
DDR_CB7_R

DDR_DS0_R
DDR_DS1_R
DDR_DS2_R
DDR_DS3_R
DDR_DS4_R
DDR_DS5_R
DDR_DS6_R
DDR_DS7_R
DDR_DS8_R

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2501

14 48Tuesday, October 05, 2004

1

DDR_D0_R <15>
DDR_D1_R <15>
DDR_D2_R <15>
DDR_D3_R <15>
DDR_D4_R <15>
DDR_D5_R <15>
DDR_D6_R <15>
DDR_D7_R <15>
DDR_D8_R <15>
DDR_D9_R <15>
DDR_D10_R <15>
DDR_D11_R <15>
DDR_D12_R <15>
DDR_D13_R <15>
DDR_D14_R <15>
DDR_D15_R <15>
DDR_D16_R <15>
DDR_D17_R <15>
DDR_D18_R <15>
DDR_D19_R <15>
DDR_D20_R <15>
DDR_D21_R <15>
DDR_D22_R <15>
DDR_D23_R <15>
DDR_D24_R <15>
DDR_D25_R <15>
DDR_D26_R <15>
DDR_D27_R <15>
DDR_D28_R <15>
DDR_D29_R <15>
DDR_D30_R <15>
DDR_D31_R <15>
DDR_D32_R <15>
DDR_D33_R <15>
DDR_D34_R <15>
DDR_D35_R <15>
DDR_D36_R <15>
DDR_D37_R <15>
DDR_D38_R <15>
DDR_D39_R <15>
DDR_D40_R <15>
DDR_D41_R <15>
DDR_D42_R <15>
DDR_D43_R <15>
DDR_D44_R <15>
DDR_D45_R <15>
DDR_D46_R <15>
DDR_D47_R <15>
DDR_D48_R <15>
DDR_D49_R <15>
DDR_D50_R <15>
DDR_D51_R <15>
DDR_D52_R <15>
DDR_D53_R <15>
DDR_D54_R <15>
DDR_D55_R <15>
DDR_D56_R <15>
DDR_D57_R <15>
DDR_D58_R <15>
DDR_D59_R <15>
DDR_D60_R <15>
DDR_D61_R <15>
DDR_D62_R <15>
DDR_D63_R <15>

DDR_CB0_R <15>
DDR_CB1_R <15>
DDR_CB2_R <15>
DDR_CB3_R <15>
DDR_CB4_R <15>
DDR_CB5_R <15>
DDR_CB6_R <15>
DDR_CB7_R <15>

DDR_DS0_R <15>
DDR_DS1_R <15>
DDR_DS2_R <15>
DDR_DS3_R <15>
DDR_DS4_R <15>
DDR_DS5_R <15>
DDR_DS6_R <15>
DDR_DS7_R <15>
DDR_DS8_R <15>

of

1.0

5

Layout Note:
Place these resistors
closely DIMM1,all
trace length<=800 mil

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

V_1P25V_DDR_VTT

R790

12

R792

12

R794

12

R796

12

R798

12

R800

12

R802

12

R804

12

R806

12

R808

12

R810

12

R812

12

R814

12

R816

12

R818

12

R820

12

R732
R733
R822

12

R824

12

R742
R743
R826

12

R827

12

R744
R745
R830

12

R832

12

R746
R747
R836

12

R838

12

R748
R749
R842

12

R844

12

R750
R751
R909

12

R911

12

R913

12

R915

12

R846

12

R847

12

R848

12

R849

12

R921

12

R923

12

R925

12

R791
R793
R795
R797
R799
R801
R803
R805
R807
R809
R811
R813
R815
R817
R819
R821
R730
R731
R823
R825
R753
R752
R734
R735
R828
R829
R831
R833
R834
R835
R837
R839
R840
R841
R843
R845
R739
R741
R910
R912
R914
R916
R917
R918
R919
R920
R922
R924
R926
R927

56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D

DDR_MA[0..12]<11,14>

D D

DDR_D0_R<14>
DDR_D1_R<14>
DDR_D2_R<14>
DDR_D3_R<14>
DDR_D4_R<14>
DDR_D5_R<14>
DDR_D6_R<14>
DDR_D7_R<14>
DDR_D8_R<14>
DDR_D9_R<14>
DDR_D10_R<14>
DDR_D11_R<14>
DDR_D12_R<14>
DDR_D13_R<14>
DDR_D14_R<14>
DDR_D15_R<14>
DDR_D16_R<14>
DDR_D17_R<14>
DDR_D18_R<14>
DDR_D19_R<14>
DDR_D20_R<14>
DDR_D21_R<14>
DDR_D22_R<14>
DDR_D23_R<14>
DDR_D24_R<14>
DDR_D25_R<14>
DDR_D26_R<14>
DDR_D27_R<14>

C C

B B

A A

DDR_D28_R<14>
DDR_D29_R<14>
DDR_D30_R<14>
DDR_D31_R<14>
DDR_D32_R<14>
DDR_D33_R<14>
DDR_D34_R<14>
DDR_D35_R<14>
DDR_D36_R<14>
DDR_D37_R<14>
DDR_D38_R<14>
DDR_D39_R<14>
DDR_D40_R<14>
DDR_D41_R<14>
DDR_D42_R<14>
DDR_D43_R<14>
DDR_D44_R<14>
DDR_D45_R<14>
DDR_D46_R<14>
DDR_D47_R<14>
DDR_D48_R<14>
DDR_D49_R<14>
DDR_D50_R<14>
DDR_D51_R<14>
DDR_D52_R<14>
DDR_D53_R<14>
DDR_D54_R<14>
DDR_D55_R<14>
DDR_D56_R<14>
DDR_D57_R<14>
DDR_D58_R<14>
DDR_D59_R<14>
DDR_D60_R<14>
DDR_D61_R<14>
DDR_D62_R<14>
DDR_D63_R<14>

DDR_CB0_R<14>
DDR_CB1_R<14>
DDR_CB2_R<14>
DDR_CB3_R<14>
DDR_CB4_R<14>
DDR_CB5_R<14>
DDR_CB6_R<14>
DDR_CB7_R<14>

DDR_DS0_R<14>
DDR_DS1_R<14>
DDR_DS2_R<14>
DDR_DS3_R<14>
DDR_DS4_R<14>
DDR_DS5_R<14>
DDR_DS6_R<14>
DDR_DS7_R<14>
DDR_DS8_R<14>

DDR_BS0<11,14>
DDR_BS1<11,14>
DDR_WE#<11,14>
DDR_CAS#<11,14>
DDR_RAS#<11,14>

DDR_D0_R
DDR_D1_R
DDR_D2_R
DDR_D3_R
DDR_D4_R
DDR_D5_R
DDR_D6_R
DDR_D7_R
DDR_D8_R
DDR_D9_R
DDR_D10_R
DDR_D11_R
DDR_D12_R
DDR_D13_R
DDR_D14_R
DDR_D15_R
DDR_D16_R
DDR_D17_R
DDR_D18_R
DDR_D19_R
DDR_D20_R
DDR_D21_R
DDR_D22_R
DDR_D23_R
DDR_D24_R
DDR_D25_R
DDR_D26_R
DDR_D27_R
DDR_D28_R
DDR_D29_R
DDR_D30_R
DDR_D31_R
DDR_D32_R
DDR_D33_R
DDR_D34_R
DDR_D35_R
DDR_D36_R
DDR_D37_R
DDR_D38_R
DDR_D39_R
DDR_D40_R
DDR_D41_R
DDR_D42_R
DDR_D43_R
DDR_D44_R
DDR_D45_R
DDR_D46_R
DDR_D47_R
DDR_D48_R
DDR_D49_R
DDR_D50_R
DDR_D51_R
DDR_D52_R
DDR_D53_R
DDR_D54_R
DDR_D55_R
DDR_D56_R
DDR_D57_R
DDR_D58_R
DDR_D59_R
DDR_D60_R
DDR_D61_R
DDR_D62_R
DDR_D63_R

DDR_CB0_R
DDR_CB1_R
DDR_CB2_R
DDR_CB3_R
DDR_CB4_R
DDR_CB5_R
DDR_CB6_R
DDR_CB7_R

DDR_DS0_R
DDR_DS1_R
DDR_DS2_R
DDR_DS3_R
DDR_DS4_R
DDR_DS5_R
DDR_DS6_R
DDR_DS7_R
DDR_DS8_R

DDR_BS0
DDR_BS1
DDR_WE#
DDR_CAS#
DDR_RAS#

5

DDR_D0_R
DDR_D4_R
DDR_D1_R
DDR_D5_R
DDR_DS0_R
DDR_D6_R
DDR_D2_R
DDR_D3_R
DDR_D7_R
DDR_D8_R
DDR_D12_R
DDR_D9_R
DDR_D13_R
DDR_DS1_R
DDR_D10_R
DDR_D14_R
DDR_D11_R
DDR_D15_R
DDR_D16_R
DDR_D20_R
DDR_D17_R
DDR_D21_R
DDR_DS2_R
DDR_D18_R
DDR_D22_R
DDR_D19_R
DDR_D23_R
DDR_D24_R
DDR_D28_R
DDR_D25_R
DDR_D29_R
DDR_DS3_R
DDR_D26_R
DDR_D30_R
DDR_D27_R
DDR_D31_R
DDR_CB0_R
DDR_CB4_R
DDR_CB1_R
DDR_CB5_R
DDR_DS8_R
DDR_CB2_R
DDR_MA6
DDR_MA7
DDR_MA4
DDR_MA5
DDR_CB6_R
DDR_CB3_R
DDR_CB7_R

56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D
56_0402_5%~D

4

DDR_D32_R

12

DDR_D36_R

12

DDR_D33_R

12

DDR_D37_R

12

DDR_DS4_R

12

DDR_D34_R

12

DDR_D38_R

12

DDR_D35_R

12

DDR_D39_R

12

DDR_D40_R

12

DDR_D44_R

12

DDR_D41_R

12

DDR_D45_R

12

DDR_DS5_R

12

DDR_D42_R

12

DDR_D46_R

12

DDR_D43_R

12

DDR_D47_R

12

DDR_D48_R

12

DDR_D52_R

12

DDR_D49_R

12

DDR_D53_R

12

DDR_D59_R

12

DDR_D63_R

12

DDR_DS6_R

12

DDR_D50_R

12

DDR_D54_R

12

DDR_D51_R

12

DDR_D55_R

12

DDR_D56_R

12

DDR_D60_R

12

DDR_D57_R

12

DDR_D61_R

12

DDR_DS7_R

12

DDR_D58_R

12

DDR_D62_R

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

4

DDR_WE#
DDR_MA10
DDR_MA11
DDR_MA12
DDR_MA8
DDR_MA9
DDR_MA2
DDR_MA3
DDR_MA0
DDR_MA1
DDR_BS1
DDR_BS0
DDR_RAS#
DDR_CAS#

3

+2.5V_MEM

JDIM2

1

VREF

3

DDR_D0_R
DDR_D1_R

DDR_DS0_R
DDR_D2_R

DDR_D3_R
DDR_D8_R

DDR_D9_R
DDR_DS1_R

DDR_D10_R
DDR_D11_R

CK_DDR_CK3<11>

CK_DDR_CK3#<11>

CK_DDR_CK5<11>
CK_DDR_CK5#<11>

DDR_CKE3_DIMM1<11>

DDR_CS2_DIMM1#<11>

CK_SDATA<6,14>
CK_SCLK<6,14>

+2.5V_MEM

CK_DDR_CK3
CK_DDR_CK3#

DDR_D16_R
DDR_D17_R

DDR_DS2_R
DDR_D18_R

DDR_D19_R
DDR_D24_R

DDR_D25_R
DDR_DS3_R

DDR_D26_R
DDR_D27_R

DDR_CB0_R
DDR_CB1_R

DDR_DS8_R
DDR_CB2_R

DDR_CB3_R

CK_DDR_CK5

CK_DDR_CK5#

DDR_CKE3_DIMM1
DDR_MA12

DDR_MA9

DDR_MA5
DDR_MA3
DDR_MA1

DDR_MA10
DDR_BS0
DDR_WE#
DDR_CS2_DIMM1#

DDR_D32_R
DDR_D33_R

DDR_DS4_R
DDR_D34_R

DDR_D35_R
DDR_D40_R

DDR_D41_R
DDR_DS5_R

DDR_D42_R
DDR_D43_R

DDR_D48_R
DDR_D49_R

DDR_DS6_R
DDR_D50_R

DDR_D51_R
DDR_D56_R

DDR_D57_R
DDR_DS7_R

DDR_D58_R
DDR_D59_R

CK_SDATA
CK_SCLK

+3VSUS

R608

1 2

10K_0402_5%~D

DIMM1_ID

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

FOX_ASOA426-B2R-TR~D

REVERSE

3

DU/RESET#

DIMM1

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD

VSS
DM8

VDD

VSS
VSS
VDD
VDD

VSS

VDD

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD

+2.5V_MEM

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CB4

74

CB5

76
78
80

CB6

82
84

CB7

86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116

BA1

118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

CK1

162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194

SA0

196

SA1

198

SA2

200

DU

C805

0.1U_0402_16V4Z~D

12

V_DDR_MCH_REF

DDR_D4_R
DDR_D5_R

DDR_D6_R
DDR_D7_R

DDR_D12_R
DDR_D13_R

DDR_D14_R
DDR_D15_R

DDR_D20_R
DDR_D21_R

DDR_D22_R
DDR_D23_R

DDR_D28_R
DDR_D29_R

DDR_D30_R
DDR_D31_R

DDR_CB4_R
DDR_CB5_R

DDR_CB6_R
DDR_CB7_R

DDR_CKE2_DIMM1
DDR_MA11

DDR_MA8
DDR_MA6DDR_MA7

DDR_MA4
DDR_MA2
DDR_MA0

DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_CS3_DIMM1#

DDR_D36_R
DDR_D37_R

DDR_D38_R
DDR_D39_R

DDR_D44_R
DDR_D45_R

DDR_D46_R
DDR_D47_R

CK_DDR_CK4#
CK_DDR_CK4

DDR_D52_R
DDR_D53_R

DDR_D54_R
DDR_D55_R

DDR_D60_R
DDR_D61_R

DDR_D62_R
DDR_D63_R

2

V_DDR_MCH_REF <11,14,41>

2

C806

0.1U_0402_16V4Z~D

1

DDR_CKE2_DIMM1 <11>

DDR_CS3_DIMM1# <11>

CK_DDR_CK4# <11>

CK_DDR_CK4 <11>

+3VSUS

2

Layout Note:
Place CAP near SOIDIMM

+2.5V_MEM

10U_0805_10V4M~D

1

2

C807

+2.5V_MEM

0.1U_0402_16V4Z~D

1

2

C817

+2.5V_MEM

10U_0805_10V4M~D

1

2

C825

+2.5V_MEM

1000P_0402_50V7K~D

1

2

C835

Layout Note:
Place these resistor
closely DIMM1,all
trace length Max=1.3"

DDR_CKE2_DIMM1

DDR_CKE3_DIMM1

DDR_CS2_DIMM1#

DDR_CS3_DIMM1#

10U_0805_10V4M~D

0.1U_0402_16V4Z~D

10U_0805_10V4M~D

1000P_0402_50V7K~D

1

150U_D2_4VK~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D

150U_D2_4VK~D

1

C802

+

2

1000P_0402_50V7K~D

1

1

2

2

C812

C813

1000P_0402_50V7K~D

1

1

2

2

C823

C822

1000P_0402_50V7K~D

1

1

2

2

C831

C830

1000P_0402_50V7K~D

1

1

2

2

C841

C840

1

C801

+

2

One 0.1uF CAP per power pin.
Place each cap close to pin.

0.1U_0402_16V4Z~D

1

2

C808

0.1U_0402_16V4Z~D

1

2

C818

0.1U_0402_10V6K~D

1

2

C826

1000P_0402_50V7K~D

1

2

C836

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C809

1

2

C819

1

2

C827

1

2

C837

0.1U_0402_16V4Z~D

0.1U_0402_10V6K~D

1000P_0402_50V7K~D

1

1

2

2

C811

C810

1000P_0402_50V7K~D

1

1

2

2

C821

C820

0.1U_0402_10V6K~D

1

1

2

2

C828

C829

1000P_0402_50V7K~D

1

1

2

2

C838

C839

C803

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

+2.5V_MEM

150U_D2_4VK~D

1

C804

+

+

2

1000P_0402_50V7K~D

1

1

2

2

C815

C814

1

2

C824

1000P_0402_50V7K~D

1

1

2

2

C832

C833

1

2

C842

Place by pin197 of each SODIMM

+3VSUS

V_1P25V_DDR_VTT

R736

1 2

56_0402_5%~D

R737

1 2

56_0402_5%~D

R738

1 2

56_0402_5%~D

R740

1 2

56_0402_5%~D

0.1U_0402_16V4Z~D

C843

1

C844

0.1U_0402_16V4Z~D

2

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2501

15 48Tuesday, October 05, 2004

1

of

150U_D2_4VK~D

1

2

1000P_0402_50V7K~D

1

2

C816

1000P_0402_50V7K~D

1

2

C834

1.0

5

R617
1K_0402_5%~D@

ICH_SUS_STAT#<20>

G_PWR_SRC

2

C854

1

0.1U_0603_25V7M~D

ST1 ST2

T50 PAD
T51 PAD

PCI_PIRQB#<18,28,30>

RUNPWROK<32,35,39,42,44>

+1.5VRUN

+1.5VRUN

C845

C855

X
0
1

0.1U_0603_25V7M~D

T52
PAD

0.1U_0402_16V4Z~D

2

1

1

X

1

2

C856

0.1U_0603_25V7M~D

DDR
TESTX
400 Mhz BPSB

AGP8X_DET_CG
AGP8X_DET_GC

ICH_SUS_STAT#

2

1

G_AD[0..31]<10>

G_C/BE#[0..3]<10>

G_SBA[0..7]<10>

G_ST0<10>
G_ST1<10>
G_ST2<10>

R615
10K_0402_5%~D@
R616
1K_0402_5%~D
R618
1K_0402_5%~D
R619
10K_0402_5%~D@
R620
10K_0402_5%~D@
R621
10K_0402_5%~D@
R622
10K_0402_5%~D@
R623
10K_0402_5%~D@
R624
10K_0402_5%~D@
R625
10K_0402_5%~D@
R626
10K_0402_5%~D@
R627
10K_0402_5%~D@
R628
10K_0402_5%~D@
R629
10K_0402_5%~D@

+5VSUS

5

CK_66M_AGP
G_REQ#
G_ST0
G_ST1
G_ST2

12

12

12

12

12

12

G_ST0
G_ST1
G_ST2
G_FRAME#
G_IRDY#
G_TRDY#
G_DEVSEL#
G_STOP#
G_PAR
G_PIPE#
G_WBF#
G_RBF#
G_REQ#
G_GNT#

G_AD_STB0
G_AD_STB0#
G_AD_STB1
G_AD_STB1#
G_SB_STB
G_SB_STB#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#

TV_Y
TV_C
TV_CVBS

DAT_DDC2
CLK_DDC2
HSYNC
VSYNC
VGA_RED
VGA_GRN
VGA_BLU

C852

G_AD_STB0

G_AD_STB1

G_SB_STB

G_AD_STB0#

G_AD_STB1#

G_SB_STB#

1

2

0.047U_0402_16V4Z~D

C853

0.047U_0402_16V4Z~D

1 2

VREFCG<10>

1

2

CK_66M_AGP<6>

+1.5VRUN

G_FRAME#<10>
G_DEVSEL#<10>

G_IRDY#<10>
G_TRDY#<10>
G_STOP#<10>

DAT_DDC2<17>

G_REQ#<10>

R609 10K_0402_5%~D@

R610 10K_0402_5%~D@

R611 10K_0402_5%~D@

R612 10K_0402_5%~D@

R613 10K_0402_5%~D@

R614 10K_0402_5%~D@

12
12
12
12
12
12
12
12
12
12
12
12
12
12

G_SB_STB<10>
G_SB_STB#<10>

G_PAR<10>
G_REQ#<10>
G_GNT#<10>
G_PIPE#<10>

TV_Y<17>
TV_C<17>
TV_CVBS<17>

CLK_DDC2<17>
HSYNC<17>
VSYNC<17>
VGA_RED<17>
VGA_GRN<17>
VGA_BLU<17>

D D

+1.5VRUN

C C

G_AD_STB0<10>
G_AD_STB0#<10>
G_AD_STB1<10>
G_AD_STB1#<10>

B B

A A

4

JVID

1

DVI_TX0+
DVI_TX0­DVI_TX1+
DVI_TX1­DVI_TX2+
DVI_TX2-

PCI_PIRQB# PCI_PIRQA#
CK_66M_AGP
G_REQ#

G_ST0
G_ST2

G_SB_STB
G_SB_STB#

G_SBA2
G_SBA4
G_SBA6
RUNPWROK

G_IRDY#
G_TRDY#
G_STOP#
G_C/BE#3

G_AD31
G_AD29

G_AD_STB1#
G_AD_STB1

G_AD27
G_AD25
G_C/BE#2

G_AD21
G_AD19
DBI_HI

VREFCG
G_AD15

G_AD13
G_AD11

G_AD9
G_AD7

G_AD_STB0#
G_AD_STB0

G_AD5
G_AD3
G_AD1

VSYNC
HSYNC
VGA_RED
VGA_GRN
VGA_BLU
TV_Y
TV_C
TV_CVBS

2

C857

1

0.1U_0603_25V7M~D

4

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

147

149

149

151

151

153

153

155

155

157

157

159

159

161

161

163

163

165

165

167

167

169

169

171

171

173

173

175

175

177

177

179

179

181

181

183

183

185

185

187

187

189

189

191

191

193

193

195

195

197

197

199

199

201

201

FOX_QT00200A-6120L~D

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

122

122

124

124

126

126

128

128

130

130

132

132

134

134

136

136

138

138

140

140

142

142

144

144

146

146

148

148

150

150

152

152

154

154

156

156

158

158

160

160

162

162

164

164

166

166

168

168

170

170

172

172

174

174

176

176

178

178

180

180

182

182

184

184

186

186

188

188

190

190

192

192

194

194

196

196

198

198

200

200

202

202

GC_BL_SUSPEND

+3VRUN

G_PWR_SRC

+5VALW

DVI_CLK+
DVI_CLK­DVI_SCLK_L
DVI_SDAT_L

DVI_DETECT_PIN

FAN2_TACH_FB
FAN2_5V

G_ST1
G_SBA0

G_SBA1
G_SBA3

G_SBA5
G_SBA7
G_DEVSEL#
PCIRST_AGP#
G_PIPE#

G_RBF#
G_WBF#
G_FRAME#
G_AD30

G_AD28
G_AD26

G_AD24
G_AD22

G_AD20
G_AD18
G_AD23

G_AD17
G_AD16
DBI_LO
G_AGPBUSY#
VREFGC_R

G_C/BE#1
G_AD14

G_AD12
G_AD10
G_AD8

G_AD6
G_AD4

G_AD2
G_AD0
G_C/BE#0

G_PAR
G_GNT#

STP_AGP_R#

M_SEN#
DAT_DDC2
CLK_DDC2

M_ID2#
SMBDAT_VGA
SMBCLK_VGA

FPVCC

3

+3VRUN

C

+3VRUN

PCI_PIRQA# <18>
FAN2_TACH_FB <13>
FAN2_5V <13>

+1.5VRUN

PCIRST_AGP# <18>

G_RBF# <10>
G_WBF# <10>

T53
PAD

1 2

R630

0_0402_5%~D

+1.5VRUN

GC_BL_SUSPEND <31>

+3VSUS

OTEMP <13>
M_SEN# <17>

M_ID2# <17>
SMBCLK_VGA <32>

1

C858

C859

2

0.1U_0402_16V4Z~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

G_AGPBUSY# <20>

SMBDAT_VGA <32>

FPVCC <32>

1

2

C860

2

1

0.1U_0402_16V4Z~D

0.1U_0603_25V7M~D

3

VREFGC <10>

+3VRUN

1 2

+15V
+5VRUN

1

C861

2

0.047U_0402_16V4Z~D

100K_0402_5%~D

1 2

2

B

E

3 1

Q57
MMBT3904_SOT23~D

10K_0402_5%~D

12

R545

R631
10K_0402_5%~D@

R632

0_0402_5%~D

1 2

1

C862

C863

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

R134

1

CLOSE
TO PIN

2

DVI_DETECT

STP_AGP# <20>

+3VRUN

+1.5VRUN

1

C846

2

0.047U_0402_16V4Z~D

C847

0.047U_0402_16V4Z~D

2

+5VRUN

1

1

C849

C848

2

2

0.047U_0402_16V4Z~D

2

1

+5VRUN

2

C512

Q59

0.1U_0603_25V7K~D

JDVI

1

DATA2#

2

DATA2

3

SHIELD24

4

DATA4#

5

DATA4

6

DDCCLK

7

DDCDATA

9

DATA1#

10

DATA1

11

SHIELD13

12

DATA3#

8

CRT_VSYNC

26

G1

27

G3

29

G5

31

NC1

JAE_DV2R024NDA~D

Q58

2N7002_SOT23~D

G

2

13

D

S

1

C66
220P_0402_50V7K~D

2

13

D

1

C67
220P_0402_50V7K~D

2

PWR_SRC G_PWR_SRC

2

2

C518

R463

1

1

0.1U_0603_25V7K~D
100K_0402_5%~D

RUN_ON<31,34,35,40,41,44>

Compal Electronics, Inc.
VGA and DVI connector

LA-2501

DVI_TX2­DVI_TX2+

DVI_SCLK
DVI_SDAT
DVI_TX1­DVI_TX1+

D22

RB751V_SOD323~D

2 1

DVI_SCLK_L

DVI_SDAT_L DVI_SDAT

1

2

0.047U_0402_16V4Z~D

1K_0402_5%~D

12

C850

R548

G

S

2N7002_SOT23~D

1

1

C851

2

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

L11

BLM31A260SPT_1206~D

DATA3

VCC5
GND5

HPDET

DATA0#

DATA0

SHIELD5

DATA5#

DATA5

SHIELDCLK

CLK

CLK#

G2
G4
G6

NC2

R38

1 2

0_0603_5%~D

R48

1 2

0_0603_5%~D

1
2
3 6

1 2

2

G

13
14
15
16
17
18
19
20
21
22
23
24

25
28
30
32

1

2

1

2

4

Q42
SI4435DY_SO8~D

GPWR_SRC_ON

12

R462
100K_0402_5%~D

PEG_PWRON#

13

D

Q44
2N7002_SOT23~D

S

1

12

DVI_SCLK

C658

220P_0402_50V7K~D@

C659

220P_0402_50V7K~D@

DVI_DETECT
DVI_TX0­DVI_TX0+

DVI_CLK+
DVI_CLK-

12

8
7

5

16 48Tuesday, October 05, 2004

0.1U_0402_16V4Z~D

10U_0805_10V4M~D

1

1

C17

C18

2

2

+5VRUN

5.6K_0402_5%~D

5.6K_0402_5%~D

12

R547

R546

1.0

of

5

TV_C<16>

D D

C C

VGA_RED<16>

VGA_GRN<16>

VGA_BLU<16>

B B

TV_CVBS<16>

TV_Y<16>

VGA_RED

VGA_GRN

VGA_BLU

75_0402_5%~D

12

C390

R363

75_0402_5%~D

12

R364

C389

12

75_0402_5%~D

C391

R362

75_0402_5%~D

12

12

R5

R4

DDA204U

A2

K1

A1

A A

K2

5

L68

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

@

82P_0402_50V8J~D

CLOSE TO JSVID

1

2

1

2

1

2

L66

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

@

82P_0402_50V8J~D

L67

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

@

82P_0402_50V8J~D

75_0402_5%~D

75_0402_5%~D

12

R6

DAT_DDC2<16>

CLK_DDC2<16>

C8

HSYNC<16>

VSYNC<16>

10P_0402_50V8J~D

1

2

4

82P_0402_50V8J~D

1

C384

2

82P_0402_50V8J~D

1

C382

2

82P_0402_50V8J~D

1

C383

2

10P_0402_50V8J~D

1

C9

2

Evaluate Package

1

C392

C393

2

33P_0402_50V8J~D

33P_0402_50V8J~D

4

1

C10

2

1

2

SVIDEO_C
SVIDEO_CVBS

SVIDEO_Y

10P_0402_50V8J~D

L71

BLM11A121S_0603~D

1 2

L70

BLM11A121S_0603~D

1 2

SPDIF<22>

L3

BLM18BB600SN1D_0603~D

1 2

L5

BLM18BB600SN1D_0603~D

1 2

L4

BLM18BB600SN1D_0603~D

1 2

CRT_VCC

12

@

R357

1K_0402_5%~D

C385

22P_0402_50V8J~D

R358

1K_0402_5%~D

1

C386

2

@

22P_0402_50V8J~D

3

D16
DA204U_SOT323~D

1

@

+3VSUS

2

3

+5VRUN

2

C23

1

0.1U_0402_16V4Z~D

SPDIF

+3VRUN

12

R356

1 2

2.2K_0402_5%~D

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SPDIF_SHDN

1

5

U1

P

4

OE#

A2Y

G

3

SN74AHCT1G125DCKR_SC70-5~D

D2
DA204U_SOT323~D

1

@

2

3

1

C2
10P_0402_50V8J~D

@

2

R3

1 2

2.2K_0402_5%~D

3

SPDIF_SHDN <22,31>

R7

SP_DIFBSP_DIF

12

220_0603_1%~D

1

@

2

C11

0.01U_0402_16V7K~D

D3
DA204U_SOT323~D

1

@

2

3

C6
10P_0402_50V8J~D

D14
DA204U_SOT323~D

1

@

2

3

Overlap R8,R1 & L6 for Pop Option

12

12

R2

110_0603_1%~D

1

C3
10P_0402_50V8J~D

@

2

M_SEN#<16>

M_ID2#<16>

2

SP_DIF_C

D4
DA204U_SOT323~D

1

@

2

3

2

R8

1 2

0_0805_5%~D

4 5

1 8

L6
TA08F010_4P~D@

2

300P_1808_3000V8K~D@

+5VRUN

D15
DA204U_SOT323~D

1

@

3

C1

RB751V_SOD323~D

21

D1

CRT_VCC

1

C5

0.1U_0402_16V4Z~D

2

1

JSVID

2
4
6
7
5
3
1
8
9

FOX_MH11777-WRUR6~D

SP_DIF_D

SP_DIF_E

1

12

R1
0_0805_5%~D

2

+3VSUS

0.01U_0402_16V7K~D

12

R10

1

2

M_SEN#
RED

DAT_DDC2
GREEN

JVGA_HS
BLUE

JVGA_VS
M_ID2#

CLK_DDC2

10K_0402_5%~D

C4

JVGA

6

11

1
7

12

2
8

13

14
10

15

18

19
3
9

4

5

FOX_DZ11A91-WL7-HT~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

TV_OUT and CRT connector

LA-2501

1

17 48Tuesday, October 05, 2004

of

1.0

182736

45

182736

45

182736

45

182736

45

12

R641

+3VSUS

PCI_PCIRST#

5

12

12

12

10K_0402_5%~D

5

R633

8.2K_0402_5%~D

R636

8.2K_0402_5%~D

12

R642

10K_0402_5%~D

1

IN1

2

IN2

4

IN1

5

IN2

10

IN1

9

IN2

13

IN1

12

IN2

CLKRUN#
PCI_DEVSEL#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_PERR#
PCI_IRDY#
PCI_SERR#

PCI_PLOCK#
PCI_PIRQA#
PCI_PIRQB#
PCI_REQ0#
PCI_REQB#

PCI_PIRQC#
PCI_REQ2#
PCI_PIRQD#

PCI_REQ4#
PCI_REQ1#
PCI_REQ3#

14

U13A

P

3

OUT

G

74VHC08MTC_TSSOP14~D

7

U13B

6

OUT

74VHC08MTC_TSSOP14~D
U13C

8

OUT

74VHC08MTC_TSSOP14~D
U13D

11

OUT

74VHC08MTC_TSSOP14~D

PCIRSTB1#

PCIRSTB2#

PCIRSTB3#

PCIRSTB4#

C866

0.1U_0402_16V4Z~D

12

R653

33_0402_5%~D

1 2

R654

33_0402_5%~D

1 2

R655

33_0402_5%~D

1 2

R656

33_0402_5%~D

1 2

R657

33_0402_5%~D

1 2

+3VRUN

RN113

8.2K_1206_8P4R_5%~D

+3VRUN

D D

RN114

8.2K_1206_8P4R_5%~D

+3VRUN

RN115

8.2K_1206_8P4R_5%~D

+3VRUN

C C

B B

A A

+3VRUN

RN117

8.2K_1206_8P4R_5%~D

R640

10K_0402_5%~D

+3VRUN

R646
10K_0402_5%~D

1 2

PCIRST_LOM#

PCIRST_MCH#

PCIRST_SIO#

PCIRST_AGP#

PCIRST_CB#

4

+3VSUS

4

PCI_AD[0..31]<26,28,30>

R639

PCI_DEVSEL#<26,28,30>

PCI_FRAME#<26,28,30>
PCI_TRDY#<26,28,30>
PCI_IRDY#<26,28,30>
PCI_STOP#<26,28,30>
PCI_PAR<26,28,30>
PCI_PERR#<26,28,30>

PCIRST_LOM# <26>

PCIRST_MCH# <11>

PCIRST_SIO# <31>

PCIRST_AGP# <16>

PCIRST_CB# <28,30>

PCI_C_BE3#<26,28,30>
PCI_C_BE2#<26,28,30>
PCI_C_BE1#<26,28,30>
PCI_C_BE0#<26,28,30>

CK_33M_ICHPCI<6>

10K_0402_5%~D@

CLKRUN#<26,28,30,31>

PCI_SERR#<26,28,30>

T81 PAD
T82 PAD

3

Hub interface Layout:

Route signal with 5/15

U16A

AB23

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

12

ICH_PME#<31>

ICH_PME#

PCI_DEVSEL#

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#

PCI_PLOCK#
PCI_SERR#

PCI_PCIRST#

ICH4_PINB5
PCI_REQB#
PCI_GNTA#
PCI_GNTB#
CK_33M_ICHPCI

P4
D2
R1
D3

P2

E1

P1

E2
M5

E4
N3

E3
N2

E5
N1

F4

F5

L3
H2

L2
G4

L1
G2

K2

J5
H4

J4
G5

K1
H3

J3
H5

N4
M4

K4

J2

W2

AC2

M3

F1

F2

L5

F3
G1

L4
M2

K5

U5

B5

A6

E8
C5

P5

FW82801DBM_BGA421_ADQ00~D

R650
10_0402_5%~D@

1 2

CLK_ICH_TERM

1

C868

8.2P_0402_50V8J~D@

2

ICH4

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PME#

CLKRUN#/GPIO24

DEVSEL#

FRAME#
TRDY#
IRDY#
STOP#
PAR
PERR#

PLOCK#
SERR#

PCIRST#

REQA#/GPIO0
REQB#/REQ5#/GPIO1
GNTA#/GPIO16
GNTB#/GNT5#/GPIO17
PCICLK

PCI INTERFACE

A20M#

W21

IGNNE#

AA21

FERR#

V22

INIT#

AB22

INTR

V21

NMI

W23

SMI#

V23

STPCLK#

U22

RCIN#

Y22

A20GATE
CPUSLP#

DPSLP#

HI10
HI11

HI_VSWING

HICOMP

HIREF

PIRQA#

PIRQB#
PIRQC#
PIRQD#

SERIRQ

APICD1

APICD0

APICCLK

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#

Y23
U21
U23

L19

HI0

L20

HI1

M19

HI2

M21

HI3

P19

HI4

R19

HI5

T20

HI6

R20

HI7

P23

HI8

L22

HI9

N22
K21

R22
P21
N20
R23
M23

D5
C2
B4
A3
C8
D7
C3
C4

J22
K20

H19
J19

B1
A2
B3
C7
B6

C1
E6
A7
B7
D6

CPUPWRGD

CPU INTERFACE

HUB LINKINTERRUPT INTERFACE

HI_STB#/HI_STBF

HI_STB/HI_STBS

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

trace/space,<< 8 inchs
Signal must match +/- 0.1" of HL_STB/STB# signals.

FERR#

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

ICH_HITERM
HUB_HLSTRB
HUB_HLSTRB#
ICH_HICOMP

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

IRQ_SERIRQ
H_PICD1

H_PICD0
NC_ICH_APIC

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#

H_FERR#

H_PWRGOOD

2

R634 56_0402_5%~D

0.01U_0402_16V7K~D

PCI_PIRQA# <16>
PCI_PIRQB# <16,28,30>
PCI_PIRQC# <26,28>
PCI_PIRQD# <28,30>

IRQ_SERIRQ <28,31>

R643 10K_0402_5%~D
R644 10K_0402_5%~D

R645 0_0402_5%~D

PCI_REQ1# <28>
PCI_REQ3# <30>

PCI_REQ4# <26>

T80
PAD

PCI_GNT1# <28>
PCI_GNT3# <30>

PCI_GNT4# <26>

R649

56_0603_5%~D

R651

332_0603_1%~D

12

HUB_HL[0..10] <10>

C864

12

HUB_HLSTRB <10>
HUB_HLSTRB# <10>

12

+VCCP

12

0.01U_0402_16V7K~D

12
12

12

T55
PAD

T56
PAD

H_A20M#
H_IGNNE#
H_FERR#
H_INIT#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
SIO_RCIN#
SIO_A20GATE
H_PWRGOOD
H_CPUSLP#
H_DPSLP#

12

12

R648
150_0603_1%~D

ICH_HITERM

12

R652
150_0603_1%~D

VCCHI

R637
1K_0402_5%~D@

1 2

R638

36.5_0603_1%~D

1 2

C865

+1.8VRUN

Place near ICH

H_A20M# <7>
H_IGNNE# <7>
H_FERR# <7>
H_INIT# <7>
H_INTR <7>
H_NMI <7>
H_SMI# <7>
H_STPCLK# <7>
SIO_RCIN# <31>
SIO_A20GATE <32>
H_PWRGOOD <7>
H_CPUSLP# <7>
H_DPSLP# <7,11>

+3VRUN

182736

45

IRQ_SERIRQ

2

C867

0.01U_0402_16V7K~D

1

1

RN116
10K_1206_8P4R_5%~D

10K_0402_5%~D

R647

+3VRUN

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(1/4)

LA-2501

18 48Tuesday, October 05, 2004

1

1.0

of

5

+3VSUS

4

3

2

1

12

R431

R658

10K_0402_5%~D

ICH_SMBDATA<6>

5

R667

R681

ICH_SMBCLK<6>

LPC_LAD[0..3]<31>

LPC_LFRAME#<31>

12P_0603_50V8J~D

12P_0603_50V8J~D

@

10K_0402_5%~D

12

R684

LPC_LDRQ0#<31>
LPC_LDRQ1#<31>

SPKR<22>

C871

CK_14M_ICH<6>

CK_48M_ICH<6>

CK_66M_ICH<6>

4.7K_0402_5%~D@

4.7K_0402_5%~D@

C872

12

+3VSUS

45
36
27

18
12
12

2

2

R682

12

Package

9.6X4.06 mm

01/07
Item 92

@

10K_0402_5%~D

R683

D D

C C

B B

A A

+RTC_CELL

+3VRUN

USB_OC5#<25>
USB_OC4#<25>
USB_OC1#<25>
USB_OC0#<25>

+5VSUS

USB_OC IS 5V
TOLERANT

RTC_RST<21>

ICH_AC_SDOUT_R
ICH_AC_BITCLK
ICH_AC_SDIN0
ICH_AC_SDIN1

R182

100K_0402_5%~D

1 2

INTRUDER#<13>

R662

10K_0402_5%~D@

1 2

1 2

LPC_LDRQ0#

R663

10K_0402_5%~D@

LPC_LDRQ1#

Note:
R540=22.6_1% for B0(QB63 part)

RN7
10K_1206_8P4R_5%~D

R665 10K_0402_5%~D
R666 10K_0402_5%~D

1 2

8.2K_0402_5%~D

CMOS_CLR
SHORT PADS

1

1

C873

2.2U_0805_16VFZ~D

1 2

1K_0402_5%~D@

1 2

R429

1 2

6.8K_0603_5%~D

6.8K_0603_5%~D

R437

12
12

R446

R664

22.6_0603_1%~D

USBP0+<25>
USBP0-<25>
USBP1+<25>
USBP1-<25>
USBP2+<24>
USBP2-<24>
USBP3+<28> IDE_SDA[0..2] <25>
USBP3-<28>
USBP4+<25>
USBP4-<25>
USBP5+<25>
USBP5-<25>

ICH_VBIAS

ICH_VBIAS<21>

12

1 2

32.768KHZ_12.5P_MC-306~L

12

+3VRUN

@

10K_0402_5%~D

12

X3

R678

@

C877

@

12

10_0402_5%~D

4.7P_0402_50V8C~D

1 2

CK_14M_ICH_TERM

2

1

12

R659

R660

0_0402_5%~D

ICH_SMBDATA
ICH_SMBCLK
USB2P0_SMI#

INTRUDER#

ICH_SMLINK0
ICH_SMLINK1

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

LPC_LDRQ1#
SPKR
USBRBIAS

USBP0+
USBP0­USBP1+
USBP1­USBP2+
USBP2­USBP3+
USBP3­USBP4+
USBP4­USBP5+
USBP5-

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#

USB_OC5#
ICH_RTCRST#

R668

10M_0603_5%~D

1 2

ICH_RTCX1

R671

ICH_RTCX2

CK_14M_ICH

CK_48M_ICH

CK_66M_ICH

R680

R679

1 2

10_0402_5%~D

@

@

CK_48M_ICH_TERM

2

C879

C878

1

4.7P_0402_50V8C~D

@

@

12

0_0402_5%~D

U16B

AB4

SMBDATA

AC4

SMBCLK

AA5

SMBALERT#/GPIO11

W6

INTRUDER#

AC3

SMLINK0

AB1

SMLINK1

T2

LAD0/FWH0

R4

LAD1/FWH1

T4

LAD2/FWH2

U2

LAD3/FWH3

T5

LFRAME#/FWH4

U3

LDRQ0#

U4

LDRQ1#

H23

SPKR

A23

USBRBIAS

B23

USBRBIAS#

C20

USBP0P

D20

USBP0N

A21

USBP1P

B21

USBP1N

C18

USBP2P

D18

USBP2N

A19

USBP3P

B19

USBP3N

C16

USBP4P

D16

USBP4N

A17

USBP5P

B17

USBP5N

B15

OC0#

C14

OC1#

A15

OC2#

B14

OC3#

A14

OC4#

D14

OC5#

W7

RTCRST#

AC7

RTCX1

12

10M_0603_5%~D

AC6

RTCX2

J23

CLK14

F19

CLK48

T21

CLK66

FW82801DBM_BGA421_ADQ00~D

1 2

10_0402_5%~D

CK_66M_ICH_TERM

2

1

10P_0402_50V8J~D

4

ICH4

SM INTERFACE

LPC INTERFACE

IDE INTERFACEAC LINK

USB INTERFACE

PDCS1#
PDCS3#

PDA2
PDA1
PDA0

PDD15
PDD14
PDD13
PDD12
PDD11
PDD10

PDD9
PDD8
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDDACK#

PDDREQ

PDIOR#

PDIOW#

PIORDY

IRQ15
IRQ14

SDCS1#
SDCS3#

SDA2
SDA1
SDA0

SDD15
SDD14
SDD13
SDD12
SDD11
SDD10

SDD9
SDD8
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

SDDACK#

SDDREQ

SDIOR#

SDIOW#

SIORDY

AC_RST#
AC_SYNC

AC_SDOUT

AC_SDIN0
AC_SDIN1
AC_SDIN2

AC_BIT_CLK

IDE_PDCS1#

Y13

IDE_PDCS3#

AB14

IDE_PDA2

W13

IDE_PDA1

AB13

IDE_PDA0

AA13

IDE_PDD15

Y11

IDE_PDD14

W11

IDE_PDD13

W10

IDE_PDD12

AB10

IDE_PDD11

W9

IDE_PDD10

AC9

IDE_PDD9

Y9

IDE_PDD8

AB9

IDE_PDD7

AA8

IDE_PDD6

Y8

IDE_PDD5

AB8

IDE_PDD4

AA7

IDE_PDD3

AA10

IDE_PDD2

Y10

IDE_PDD1

AC11

IDE_PDD0

AB11

IDE_PDDACK#

Y12

IDE_PDDREQ

AA11

IDE_PDIOR#

AC12

IDE_PDIOW#

W12

IDE_PDIORDY

AB12

IDE_IRQ15

AA19

IDE_IRQ14

AC13

IDE_SDCS1#

AB21

IDE_SDCS3#

AC22

IDE_SDA2

AC21

IDE_SDA1

AC20

IDE_SDA0

AA20

IDE_SDD15

Y17

IDE_SDD14

AA17

IDE_SDD13

Y16

IDE_SDD12

AB16

IDE_SDD11

Y15

IDE_SDD10

AA15

IDE_SDD9

AC15

IDE_SDD8

Y14

IDE_SDD7

AA14

IDE_SDD6

W14

IDE_SDD5

AB15

IDE_SDD4

W15

IDE_SDD3

AC16

IDE_SDD2

W16

IDE_SDD1

AB17

IDE_SDD0

W17

IDE_SDDACK#

AB19

IDE_SDDREQ

AB18

IDE_SDIOR#

Y18

IDE_SDIOW#

AA18

IDE_SDIORDY

AC19

ICH_AC_RST_R#

C13

ICH_AC_SYNC_R

C9

ICH_AC_SDOUT_R

D9

ICH_AC_SDIN0

D13

ICH_AC_SDIN1

A13
B13

ICH_AC_BITCLK

B8

R677

1 2

10_0402_5%~D

@

ICH_AC_BITCLK_TERM

2

C876

1

10P_0402_50V8J~D

@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

IDE_IRQ15 <25>

IDE_SDCS1# <25>
IDE_SDCS3# <25>

IDE_SDD[0..15] <25>

IDE_SDDACK# <25>
IDE_SDIOR# <25>

IDE_SDIOW# <25>
IDE_SDIORDY <25>

R672 33_0402_5%~D
R674 33_0402_5%~D

R675 33_0402_5%~D

12
12

12

R399

33_0402_5%~D

1 2

R401

33_0402_5%~D

1 2

R402

33_0402_5%~D

1 2

IDE_RST_HDD<31>

R661

1K_0402_5%~D

PIDEACT#<35>

+5VHDD

ICH_RST_MDC# <24>
ICH_SYNC_MDC <24>

ICH_SDOUT_MDC <24>
ICH_AC_SDIN0 <22>
ICH_AC_SDIN1 <24>

ICH_AC_BITCLK <22>

ICH_RST_AUDIO# <22>

ICH_SYNC_AUDIO <22>

ICH_SDOUT_AUDIO <22>

+5VHDD

12

0.1U_0402_16V4Z~D

C307

2

1

HDD Connector

IDE_RST_HDD
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

RPDDREQ
IDE_PDIOW#
IDE_PDIOR#
IDE_PDIORDY
IDE_PDDACK#
IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
PIDEACT#

0.1U_0402_16V4Z~D

C306

2

1

2

JHDD

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

FOX_HH99223-SB-7F~D

IDE_IRQ15

IDE_IRQ14

IDE_PDIORDY

IDE_SDIORDY

IDE_PDDREQ

IDE_SDDREQ

2

2

IDE_PDD8

4

4

IDE_PDD9

6

6

IDE_PDD10

8

8

IDE_PDD11

10

10

IDE_PDD12

12

12

IDE_PDD13

14

14

IDE_PDD14

16

16

IDE_PDD15

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

R436

1 2

10K_0402_5%~D

R298

10K_0402_5%~D

R669

4.7K_0402_5%~D

R670

4.7K_0402_5%~D

R673

0_0402_5%~D

1 2

R676

0_0402_5%~D

1 2

IDE_CSEL_PRI

ATA_66_PRI/PDIAG

IDE_PDA2
IDE_PDCS3#

12

12

12

1

2

C874

33P_0603_50V8J~D

4.7U_0805_10V4Z~D
C322

+3VRUN

+3VRUN

2

1

R306

470_0402_5%~D

1 2
1 2

10K_0402_5%~D

0.1U_0402_16V4Z~D

2

2

C869

1

1

RPDDREQ

RSDDREQ

2

C875

1

33P_0603_50V8J~D

R296

0.1U_0402_16V4Z~D

C870

+5VHDD

R291

@

10K_0402_5%~D

1 2

RSDDREQ <25>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(2/4)

LA-2501

19 48Tuesday, October 05, 2004

1

of

1.0

5

4

3

2

1

R686

10K_0402_5%~D

T62 PAD

T66
PAD

R706

100K_0402_5%~D

12

12

R687

R707

+3VRUN

10K_0402_5%~D

100K_0402_5%~D

12

ICH_RI#
ICH_BATLOW#
SIO_THRM#

G_AGPBUSY#
STP_AGP#
GMUXSEL
H_CPUPERF#
H_STP_CPU#
H_STP_PCI#

DPRSLPVR
SLP_S1_G#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#

ICH_PWRGD
IMVP_PWRGD

ICH_SUS_STAT#
ICH_SUSCLK
SIO_PWRBTN#

SUSPWROK

THRMTRIP#

12

1

C880

2

0.1U_0402_16V4Z~D

U16C

ICH4

Y1

RI#

AB2

BATLOW#/TP0

V1

THRM#

R2

AGPBUSY#/GPIO6

T3

C3_STAT#/GPIO21

J21

SSMUXSEL/GPIO23

Y20

CPUPERF#/GPIO22

W19

STP_CPU#/GPIO20

Y21

STP_PCI#/GPIO18

V20

DPRSLPVR

W18

SLP_S1#/GPIO19

Y4

SLP_S3#

Y2

SLP_S4#

AA2

SLP_S5#

AB6

PWROK

V19

VGATE/VRMPWRGD

AB3

SUS_STAT#/LPCPD#

AA4

SUSCLK

AA1

PWRBTN#

AA6

RSMRST#

Y3

SYS_RESET#

W20

THRMTRIP#

FW82801DBM_BGA421_ADQ00~D

BID2 BID1

000

PM INTERFACE

LAN INTERFACE

GPIO

LAN_RST#

LAN_RXD0
LAN_TXD0
LAN_RXD1
LAN_TXD1
LAN_RXD2
LAN_TXD2

LAN_RSTSYNC

LAN_CLK

EE_DIN

EE_DOUT

EE_CS

EE_SHCLK

GPIO7

GPIO8
GPIO12
GPIO13
GPIO25
GPIO27
GPIO28
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43

BID0BID3

0

Y5

A10
B10
A9
C10
A11
A12

B11
C11

D11
A8
D10
C12

R3
V4
V5
W3
V2
W1
W4
J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23

REV
X00

LAN_RST#

NC_EE_DIN
NC_EE_DOUT
NC_EE_CS
NC_EE_SHCLK

SB_GPIO7
SIO_EXT_SMI#
SIO_EXT_WAK#
SIO_EXT_SCI#
IEEE1394_PWREN
NC_ICH_GPIO27
NC_ICH_GPIO28
ICH_GPIO32
ICH_GPIO33
ICH_BID0
ICH_BID1
ICH_BID2
ICH_BID3
ICH_GPIO38
ICH_GPIO39
ICH_GPIO40
ICH_GPIO41
ICH_GPIO42
ICH_GPIO43

R688
0_0402_5%~D

1 2

R692

T57PAD
T58PAD

1K_0402_5%~D@

T59PAD

SIO_EXT_SMI# <31>
SIO_EXT_WAK# <31>
SIO_EXT_SCI# <31>

T60PAD
T61PAD
T63PAD
T64PAD

R695

T88PAD

T67PAD
T68PAD
T69PAD
T70PAD
T71PAD
T72PAD

10K_0402_5%~D

@

SLP_S1_G#
SIO_SLP_S3#

+3VRUN

12

R693
10K_0402_5%~D

1 2

+3VRUN

R697

R696

1 2

10K_0402_5%~D

R698

1 2

1 2

10K_0402_5%~D

@

+3VSUS

1

B

2

A

1 2

10K_0402_5%~D

@

R699 10K_0402_5%~D

1 2

R700 10K_0402_5%~D@

1 2

R701 10K_0402_5%~D

1 2

R702 10K_0402_5%~D

1 2

R708
0_0402_5%~D@

1 2

1

C881

0.047U_0402_16V4Z~D

2

5

U40

P

4

O

G

TC7SH08FU_SSOP5~D

3

ICH_SLP_S1#

ICH_SLP_S1# <6>

+3VSUS

12

12

R685

R448

10K_0402_5%~D

12

10K_0402_5%~D

SIO_THRM#<31>

G_AGPBUSY#<16>

STP_AGP#<16>

H_STP_CPU#<6,42>
H_STP_PCI#<6>

SIO_SLP_S3#<31>

SIO_SLP_S5#<31>

ICH_PWRGD<35>
IMVP_PWRGD<35,42>

ICH_SUS_STAT#<16>

SIO_PWRBTN#<31>

SUSPWROK<13,35>

R705

56_0402_5%~D

1 2

D D

+3VRUN

+VCCP +3VRUN

R694

1 2

12

R690

R691

1 2

10K_0402_5%~D

10K_0402_5%~D

12

100K_0402_5%~D

R704

1 2

56_0402_5%~D

R689

1K_0402_5%~D@

DPRSLPVR<7,42>

C C

+3VSUS +VCCP

R703

10K_0402_5%~D

H_THERMTRIP#<7,13>

B B

0001X01
00 01 A00

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(3/4)

LA-2501

20 48Tuesday, October 05, 2004

1

1.0

of

5

+3VRUN

D D

+3VSUS

+5VSUS

21

1 2

D74

RB751V_SOD323~D

2

C901
1U_0805_10V6K~D

1

VCCHI

R710

1K_0402_5%~D

C C

RTC_RST<19>

B B

A A

+RTC_CELL

+5VRUN

R709

1K_0402_5%~D

RTC_RST

D76

2 1

RB751V_SOD323~D

R713

1K_0402_5%~D

1 2

C928

0.047U_0402_16V4Z~D

1 2

C931

0.047U_0402_16V4Z~D

1 2

C934

0.047U_0402_16V4Z~D@

1 2

C935

0.047U_0402_16V4Z~D@

1 2

5

21

1 2

2

1

ICH_V5REF_SUS

2

C902

0.1U_0402_16V4Z~D

1

1 2

0.047U_0402_16V4Z~D

Z2101

1 2

D73

RB751V_SOD323~D

C892
1U_0805_10V6K~D

2

@

1

+1.5VRUN

R711

1K_0402_5%~D

C923

2200P_0603_50V7K~D@

ICH_V5REF_RUN

2

C893

0.1U_0402_16V4Z~D

1

C903

0.1U_0402_16V4Z~D
L88

BLM11A601S_0603~D

1 2

+1.8VRUN

+3VSUS

C924

1 2

3

2

1

2

C907

1

0.1U_0402_16V4Z~D

BLM21PG600SN1D_0805~D

1 2

2

D75
BAT54C_SOT23~D

1

ICH_VBIAS

2

C927
1U_0805_10V6K~D

1

4

C894

0.1U_0402_16V4Z~D

+1.5VRUN

1

C908

2

0.01U_0402_16V7K~D

L89

4

ICH_VBIAS<19>

+1.5VSUS

+3VSUS

+1.5VSUS

+3VSUS

+VCCP

VCCHI

VCC_RTC

1

C912

2

1U_0805_10V6K~D

C919

0.1U_0402_16V4Z~D

12

R712
22M_0603_5%@

12

R714

2.4M_0603_1%~D@

BAT54C

2

ICH4_VCCPLL

12

K2 K1

1

ICH_VBIAS

+3VRUN

3

U16D

Y6

VBIAS

E12

VCCSUS1_5_1

E13

VCCSUS1_5_2

E20

VCCSUS1_5_3

F14

VCCSUS1_5_4

G18

VCCSUS1_5_5

R6

VCCSUS1_5_6

T6

VCCSUS1_5_7

U6

VCCSUS1_5_8

E11

VCCSUS3_3_1

F10

VCCSUS3_3_2

F15

VCCSUS3_3_3

F16

VCCSUS3_3_4

F17

VCCSUS3_3_5

F18

VCCSUS3_3_6

K14

VCCSUS3_3_7

V7

VCCSUS3_3_8

V8

VCCSUS3_3_9

V9

VCCSUS3_3_10

F6

VCCLAN1_5_1/VCCSUS1_5_9

F7

VCCLAN1_5_2/VCCSUS1_5_10

E9

VCCLAN3_3_1/VCCSUS3_3_11

F9

VCCLAN3_3_2/VCCSUS3_3_12

E7

V5REF_1

V6

V5REF_2

E15

V5REF_SUS

AA23

V_CPU_IO_1

P14

V_CPU_IO_2

U18

V_CPU_IO_3

C22

VCCPLL

K10

VCC1_5_1

K12

VCC1_5_2

K18

VCC1_5_3

K22

VCC1_5_4

P10

VCC1_5_5

T18

VCC1_5_6

U19

VCC1_5_7

V14

VCC1_5_8

L23

VCCHI_1

M14

VCCHI_2

P18

VCCHI_3

T22

VCCHI_4

AB5

VCCRTC

A5

VCC3_3_1

AC17

VCC3_3_2

AC8

VCC3_3_3

B2

VCC3_3_4

H18

VCC3_3_5

H6

VCC3_3_6

J1

VCC3_3_7

J18

VCC3_3_8

K6

VCC3_3_9

M10

VCC3_3_10

P12

VCC3_3_11

P6

VCC3_3_12

U1

VCC3_3_13

V10

VCC3_3_14

V16

VCC3_3_15

V18

VCC3_3_16

A1

VSS_1

A16

VSS_2

A18

VSS_3

A20

VSS_4

A22

VSS_5

A4

VSS_6

AA12

VSS_7

AA16

VSS_8

AA22

VSS_9

AA3

VSS_10

AA9

VSS_11

AB20

VSS_12

AB7

VSS_13

AC1

VSS_14

AC10

VSS_15

AC14

VSS_16

AC18

VSS_17

AC23

VSS_18

AC5

VSS_19

FW82801DBM_BGA421_ADQ00~D

3

ICH4

POWER & GND

VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102

B12
B16
B18
B20
B22
B9
C15
C17
C19
C21
C23
C6
D1
D12
D15
D17
D19
D21
D23
D4
D8
D22
E10
E14
E16
E17
E18
E19
E21
E22
F8
G19
G21
G3
G6
H1
J6
K11
K13
K19
K23
K3
L10
L11
L12
L13
L14
L21
M1
M11
M12
M13
M20
M22
N10
N11
N12
N13
N14
N19
N21
N23
N5
P11
P13
P20
P22
P3
R18
R21
R5
T1
T19
T23
U20
V15
V17
V3
W22
W5
W8
Y19
Y7

2

+1.5VRUN

C882

150U_D2_4VK~D

+

1 2

C884

10U_0805_10V4M~D

1 2

C886

10U_0805_10V4M~D

1 2

C888

0.047U_0402_16V4Z~D

12

C890

0.047U_0402_16V4Z~D

12

C895

0.047U_0402_16V4Z~D

12

C897

0.047U_0402_16V4Z~D

12

C899

0.047U_0402_16V4Z~D

12

C904

0.047U_0402_16V4Z~D

12

+3VSUS

C910

0.047U_0402_16V4Z~D

1 2

C913

0.047U_0402_16V4Z~D

1 2

C915

0.047U_0402_16V4Z~D

1 2

C917

0.047U_0402_16V4Z~D

1 2

C920

10U_0805_10V4M~D

1 2

VCCHI

C925

10U_0805_10V4M~D

1 2

C929

0.047U_0402_16V4Z~D

1 2

C932

0.047U_0402_16V4Z~D

1 2

+3VRUN

10U_0805_10V4M~D

10U_0805_10V4M~D

10U_0805_10V4M~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

+1.5VSUS

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

10U_0805_10V4M~D

+VCCP

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C883

1 2

C885

1 2

C887

1 2

C889

1 2

C891

1 2

C896

1 2

C898

1 2

C900

1 2

C905

1 2

C906

1 2

C909

1 2

C911

1 2

C914

1 2

C916

1 2

C918

1 2

C921

1 2

C922

1 2

C926

1 2

C930

1 2

C933

1 2

1

DELL CONFIDENTIAL/PROPRIETARY

A1A2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(4/4)

LA-2501

21 48Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

VDDA

L16
BLM11A121S_0603~D

1 2

U8A

8

SN74LVC2G86DCTR_SSOP8~D

1

P

1A

7

1Y

2

1B

G

4

CBS_SPK_INV

12

@

43K_0402_5%~D

INT_CD_LANALOG_CD_L

CD_AUDIORET

NB_MICIN <23>

HP_OUT_L <23>

HP_OUT_R <23>

AUD_MONO_OUT <24>

AUD_LINE_OUT_L <23>

AUD_LINE_OUT_R <23>

R126

Z2401

Z2402

8

U8B

5

P

2A

2Y

6

2B

G

SN74LVC2G86DCTR_SSOP8~D

4

INT_CD_L <25>

CD_AUDIORET <25>

INT_CD_R <25>

TRACE>15 mil

1

C81

0.1U_0402_16V4Z~D

2

R115

10K_0402_5%~D

1 2

8.2K_0402_5%~D

@

Z2403 PC_BEEP

3

single gate TTL

0.1U_0402_16V4Z~D

Z2404

12

R105

CLOCK SOURCE

14.318 MHz
27 MHz
48 MHz

24.576 MHz

1

C93

C98

2

0.1U_0402_16V4Z~D

STAC9750

DVSS14DVSS2

7

VDDA

1

Note: This is reserved for
STAC9751 and TPS79333 only

2

2.2U_0805_10V6K~D

1

C100

2

0.1U_0402_16V4Z~D

9

38

LINE_IN_L

AVDD125AVDD2

DVDD11DVDD2

LINE_IN_R

CD_L

CD_C

CD_R

AUX_L

AUX_R

MIC1
MIC2

VIDEO_L

VIDEO_R

PHONE

PC_BEEP

HP_OUT_L

HP_COMM

HP_OUT_R

MONO_OUT

LOUT_L

LOUT_R

AVSS126AVSS2

STAC9750_TQFP48~D

42

1 2

BLM31A260SPT_1206~D

C106

+5VSUS

1

1

C115

D D

C C

B B

A A

2

0.1U_0402_16V4Z~D

ICH_AC_BITCLK<19>

MDC_AC_BITCLK<24>

ICH_AC_SDIN0<19>

ICH_SDOUT_AUDIO

R222

1 2

ICH_AC_SDOUT_TERM

1

2

47_0402_5%~D@

C258
22P_0402_50V8J~D

@

C99

C97

2

1U_0603_10V4Z~D

0.01U_0402_16V7K~D

ICH_RST_AUDIO#

ICH_SYNC_AUDIO

ICH_SDOUT_AUDIO

C266

@

2

1

1

2

AUDIO_AVDD_ON<32>

1 2

1 2

1 2

C267

@

27P_0603_50V8J~D

C190

CK_14M_CODEC

12

R219
33_0402_5%~D@

CK_14M_CODEC_TERM

1

C244

2

AUDIO_AVDD_ON TPS793475_BYPASS

C249
10P_0402_50V8J~D@

C248
10P_0402_50V8J~D@

C247
10P_0402_50V8J~D@

R233

33_0402_5%~D

1 2

R234

33_0402_5%~D

1 2

R235

33_0402_5%~D

1

2

22P_0402_50V8J~D@

1 2

1

C268

2

@

27P_0603_50V8J~D

27P_0603_50V8J~D

2

C194

1

2.2U_0805_10V6K~D

0.1U_0402_16V4Z~D

2

2

C195

1

1

0.1U_0402_16V4Z~D

U9

1
2
3

TPS793475DBVR_SOT23-5~D

SPK_SHUTDOWN#<23,24>

CK_14M_CODEC<6>

5

OUT

IN
GND

4

BYPASS

EN

+3VRUN

2

C545

C544

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

ICH_RST_AUDIO#<19>
ICH_SYNC_AUDIO<19>
ICH_SDOUT_AUDIO<19>

C197 1000P_0402_50V7K~D

1 2

C196 1000P_0402_50V7K~D

1 2

C198 0.1U_0402_16V4Z~D

1 2

@

SPDIF_SHDN<17,31>

SPDIF<17>
EAPD<23>

XTL_24M-

12

R221
0_0402_5%~D

C92

0.1U_0402_16V4Z~D

W=30 mil

1

2

1

PACKAGE : 8X4.5X1.5mm

2

R_ICH_AC_BITCLK

R_ICH_AC_SDIN0

AFLT1
AFLT2
VREFOUT
AC97VREFI

CAP2
SPK_SHUTDOWN#

SPDIF_SHDN

SPDIF
EAPD

12

R215
10K_0402_5%~D

R214

1K_0402_5%~D@

1 2
1 2

R212

1K_0402_5%~D@

CK_14M_CODEC

C541

2.2U_0805_16VFZ~D

1

2

VDDA=4.75V

U19

11

RESET#

10

SYNC

5

SDATA_OUT

6

BIT_CLK

8

SDATA_IN

29

AFLT1

30

AFLT2

28

VREFOUT

27

VREF

32

CAP2

43

GPIO0/NC

44

GPIO1/NC

48

SPDIF

47

EAPD

31

NC/BPCFG

33

NC/FLTIN

34

NC/FLTOUT

46

CID1

45

CID0

3

XTL_OUT

2

XTL_IN

+3VRUN

L25

@

SPKR<19>
BEEP<31>

R109

@

1 2

L1

BLM31A260SPT_1206~D

1 2

1

2

0.1U_0402_16V4Z~D

23

24
18

ANALOG_CD_C

19

ANALOG_CD_R INT_CD_R

20

14

15

CNB_MICIN

21
22
16
17

9750_PHONE

13

PC_BEEP

12

HP_OUT_L

39

HP_COMM

40

HP_OUT_R

41

37

35

36

VDDA

CBS_SPK<28>

0_0402_5%~D

1

5

P

NC

4

A2Y

G

U38

3

SN74AHCT1G14DCKR_SC70-5~D

C94 1U_0603_10V4Z~D

1 2

C96 1U_0603_10V4Z~D

1 2

C101 1U_0603_10V4Z~D

1 2

C222

0.22U_0603_10V7M~D

1 2
1 2

C217

0.1U_0402_16V4Z~D

C205

0.1U_0402_16V4Z~D

1 2

C226

1U_0805_10V7K~D

1 2

2

C193
1000P_0402_50V7K~D

1

2

C192
1000P_0402_50V7K~D

1

C252

1 2

Pin46
CID1

OPEN

1K

2

45

31

2

C251
1000P_0402_50V7K~D

1

@

Pin45
CID0

OPENOPEN

1K

OPEN

1K1K

Pin3
XTL_OUT

GND
GND
GND
GND

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

AC97 CODEC

LA-2501

22 48Tuesday, October 05, 2004

1

1.0

of

5

U18

SHDNR#
SHDNL#

INR
INL

C1P
C1N

C204

5

1

2

PVss

+3VRUN

19

PVDD

7

10

SVDD

PGND

SVss

SGND

2

17

+3VRUN

12

R216
10K_0402_5%~D

D D

C223

12

R218
10K_0402_5%~D

1U_0603_10V4Z~D

1U_0603_10V4Z~D

HP_OUT_R<22>
HP_OUT_L<22>

+5VRUN

C C

1 2
1 2

C216

AUD_LINE_IN_R
AUD_LINE_IN_L

1

C221
1U_0603_10V4Z~D

2

Gain Setting

12

R231
10K_0402_5%~D

14
18

15
13

1
3

1U_0603_10V4Z~D

4

1

C229
1U_0603_10V4Z~D

2

HP_SPK_R1HP_NB_SENSE

11

OUTR

HP_SPK_L1

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

MAX4411ETP-T_TQFN20~D

HP_NB_SENSE<31>

L79

BLM11A121S_0603~D

HP_SPK_R2

12

HP_SPK_L2

12

L77

BLM11A121S_0603~D

LINE OUT

+5VRUN

2

C500

1

100P_0402_50V8J~D

D11
DA204U_SOT323~D

1

@

2

3

2

C458

1

D10
DA204U_SOT323~D

1

2

100P_0402_50V8J~D

3

3

JAUDO

1
2
6
3

4
5

7
8

FOX_JA6333L-B6ST-7F~D

D13
DA204U_SOT323~D

1

@

@

2

3

D12
DA204U_SOT323~D

1

2

3

INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2

@

NB_MICIN<22>

R449

1 2

100_0402_5%~D

2

BLM11A121S_0603~D

1

C533
100P_0402_50V8J~D

2

1

C534

2

10U_0805_10V4M~D

BLM11A121S_0603~D

L81

EMICIN

12

2

C507

1

100P_0402_50V8J~D

60mil single end
connection near JACK

TRACE>15 mil

VDDA

L83

C539

100P_0402_50V8J~D

12

R465

1.33K_0603_1%~D

12

R464
2K_0402_5%~D

1 2

12

100P_0402_50V8J~D

2

1

C517

COINCELL

1
2
6
3

4
5

7
8

1

JMIC

FOX_JA6333L-B6ST-7F~D

COINCELL

JCOIN

1
2

MOLEX_53398-0290~D

1
2

AUD_GAIN0
AUD_GAIN1

+3VRUN

R447
100K_0402_5%~D

1 2

13

D

Q43

S

2N7002_SOT23~D

5

12

R236
10K_0402_5%~D@

HP_NB_SENSE

L84

BLM21AF121SN1D_0805~D

W=40mils

1

C573

0.1U_0402_16V4Z~D

2

U21

C264

0.047U_0402_16V4Z~D

1 2

C260

0.015U_0402_16V7K~D

13

D

Q41

S

2N7002_SOT23~D

1 2

C271

0.047U_0402_16V4Z~D

1 2

C563

0.015U_0402_16V7K~D

1 2

NB_MUTE<31>

2

G

AUD_LINE_OUT_R<22>

AUD_LINE_OUT_L<22>

2

G

13

D

Q45

S

2N7002_SOT23~D

4

7

17

9

5

19

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

16

15

6

VDD

PVDD1

GND41GND311GND213GND1

TPA6017A2PWPR_TSSOP20~D

20

+5VAMPVCC

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

NC

1 2

1

2

2
3

18

14

4

8

12
10

AUD_GAIN0
AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

INT_SPK_L1

INT_SPK_L2

BYPASS

+5VRUN

C269
10U_0805_10V4M~D

1

C272

0.1U_0402_16V4Z~D

2

1

C572

0.1U_0402_16V4Z~D

2

Added new
Amplifier, same as
Nimitz

1

C276

0.47U_0603_16V7K~D

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

C283

0.1U_0402_16V4Z~D

@

2

12

R223
10K_0402_5%~D@

B B

SPK_SHUTDOWN#<22,24>

A A

EAPD<22>

2

G

INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2

1
2
3
4

2

JSPK

1
2
3
4

MOLEX_53398-0490~D

Place close to connector

INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1

C630

GAIN0 GAIN1 AV(inv) INPUT

0
0
1
11

*

6dB

0

10dB

1

15.6dB

0

21.6dB

@

@

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

C631

1

C632

2

2

IMPEDANCE

90K ohm
70K ohm
45K ohm
25K ohm

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Amplifier and Phone Jack

LA-2501

1

@

0.1U_0402_16V4Z~D

23 48Tuesday, October 05, 2004

C633

@

0.1U_0402_16V4Z~D

1

2

1.0

of

5

4

3

2

1

+3VRUN

C379

1 2

JMDC

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

W=20 mil

IAC_BITCLK

131314141515161617171818191920

SUB_OUT1

1

C377

2
1

C378

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2

SUB_OUT2

2

RES0

4

RES1

6

3.3V

8

GND3

10

GND4

12

TYCO_1-1734054-2~D

20

MDC_AC_BITCLK <22>

Connector for MDC Rev1.5

SUB_OUT1
SUB_OUT2

1

C381

@

1000P_0402_50V7K~D

2

1

C380

1000P_0402_50V7K~D@

2

0.1U_0402_16V4Z~D

JBT

1

1

12

10K_0402_5%~D

SPK_SHUTDOWN#

C629

1 2

SUB_GAIN0
SUB_GAIN1

C626

1 2

1U_0805_25V4Z~D

1

C627

2

220P_0402_50V7K~D

2

2

3

3

4

4

5

11

5

11

6

12

6

12

7

7

8

8

9

9

10

10

JST_BM10B-SRSS-TB~D

24

23
22
21
20

12

R534

120K_0402_5%~D

5

1
2
3
4

7

C625

U33

VCC
SHDN

INN
INP
GAIN0
GAIN1

VCLAMP
VREF
BYPASS
COSC
ROSC

ICH_SDOUT_MDC<19>

R202

R532

1 2

51_0603_1%~D

R531

1 2

51_0603_1%~D

ICH_SYNC_MDC<19>
ICH_RST_MDC#<19>

0.22U_1206_25V7M~D

2 1

B130-13_SMA~D

2 1

B130-13_SMA~D

0.22U_1206_25V7M~D

ICH_AC_SDIN1<19>

+15V

1U_0805_25V4Z~D

10U_1210_25V6K~D

220U_25V_M~D

1

C646

2

1

+

C615

1

PGND

PGND12PGND

6

2

2

OUTN
OUTN

AGND18AGND

TPA3001D1PWP_TSSOP24~D

13

19

BSN

PVCC

OUTP
OUTP
PVCC

BSP

8
9
11
10

14
15
16
17

1 2

33_0402_5%~D

+15V

C623

1 2

1U_0805_25V4Z~D

C624

1 2

1U_0805_25V4Z~D

+15V

C621

1 2

D6

D7

C622

1 2

MDC_SDIN

L64

1 2

BLM21PG600SN1D_0805~D

1 2

BLM21PG600SN1D_0805~D

L65

D D

@

T17
PAD~D

C C

AUD_MONO_OUT<22>

B B

0.056U_0603_16V7K~D

SUB_VREF

COEX2_WLAN_ACTIVE<30>

HW_RADIO_DIS#<30,32>

COEX1_BT_ACTIVE<30>

C637

1 2

BT_ACTIVE<35>

USBP2-<19>
USBP2+<19>

0.1U_0603_16V7K~D

1

C636
1U_0805_25V4Z~D

2

COEX2_WLAN_ACTIVE
HW_RADIO_DIS#
COEX1_BT_ACTIVE
COEX3
USBP2­USBP2+

Place near BT

SPK_SHUTDOWN#<22,23>

C635

1 2

1000P_0402_50V7K~D

C634

1 2

R539

1 2

16K_0603_1%~D

1

2

R345

0.22U_0603_10V7K~D

C628

1U_0805_25V4Z~D

+3VSUS

C224

4.7U_0805_10V4Z~D

SUB_OUT2

SUB_OUT1

1

2

+15V

1

C219

2

0.1U_0402_16V4Z~D

ICH_SDOUT_MDC

ICH_SYNC_MDC

ICH_RST_MDC#

JWOFR

1

1

2

2

MOLEX_53398-0290~D

1

D8
DA204U_SOT323~D

@

2

3

ICH_SDOUT_MDC
MDC_AC_BITCLK

R205

10_0402_5%~D@

C201

10P_0402_50V8J~D@

C273
10P_0402_50V8J~D@

1 2

C281
10P_0402_50V8J~D@

1 2

C280
10P_0402_50V8J~D@

1 2

1

D9
DA204U_SOT323~D

@

2

3

R213

1 2

1 2

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

2

2

C235

10P_0402_50V8J~D@

1

1

SUB_VREF

SUB_GAIN0
SUB_GAIN1

A A

5

Gain Setting

12

R537
100K_0402_5%~D

12

R538
100K_0402_5%~D@

12

R535
100K_0402_5%~D

12

R536
100K_0402_5%~D@

4

GAIN0 GAIN1 Amplifier gain(db) INPUT

0

1

11

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0

1

0

12dB

18dB0

23.6dB

36dB

3

IMPEDANCE

241K ohm

168K ohm

104K ohm

33K ohm

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SUBWOOFER,BT PORT and MDC

LA-2501

24 48Tuesday, October 05, 2004

1

of

1.0

5

4

3

2

1

R41

USBP0+<19>

USBP0-<19>

USBP1+<19>

D D

USBP1-<19>

USBP4-<19>

USBP4+<19>

USBP5-<19>

USBP5+<19>

USBP0+

USBP0-

USBP1+

USBP1-

USBP4-

USBP4+ GND

USBP5-

USBP5+

USBP0_PWR

USBP1_PWR

0_0805_5%~D

1 2

PJP20
PAD-OPEN 2x2m~D

2 1

R42

0_0805_5%~D

1 2

C250

C278

@

150U_D2_6.3VM~D

150U_D2_6.3VM~D

USBP4_PWR

1

1

+

C575

2

2

USBP0_VCC
USBP0-

0.1U_0402_16V4Z~D

1

+

C576

2

0.1U_0402_16V4Z~D

@

USBP0+
GND

USBP1_VCC
USBP1­USBP1+
GND

1

2

JUSB3

8

8

7

7

6

6

5

5

10

10

9

9

4

4

3

3

2

2

1

1

JST_BM08B-SRSS-TB1~D

USBP5_PWR

R43

0_0805_5%~D

1 2

PJP21
PAD-OPEN 2x2m~D

2 1

R46

0_0805_5%~D

1 2

USB PORT#

1

1

+

C15

C21

2

150U_D2_6.3VM~D

0.1U_0402_16V4Z~D

1

+

C19

C16

2

150U_D2_6.3VM~D

@

0.1U_0402_16V4Z~D

@

USBP4_VCC

2

USBP4­USBP4+
GND

USBP5_VCC
USBP5­USBP5+

1

2

JUSB2

A1

A_VCC

A2

A_D-

A3

A_D+

A4

A_GND

B1

B_VCC

B2

B_D-

B3

B_D+

B4

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB11123-8Z4-HT~D

0
1
2
3
4
5

DESTINATION

JUSB3 (Bottom)
JUSB3 (Top)
BlueTooth
NEW CARD
JUSB2 (Top)
JUSB2 (Bottom)

CD-ROM Connector

C C

INT_CD_L<22>

CD_AUDIORET<22>
IDE_RST_MOD<31>

+5VMOD

100K_0402_5%~D

1 2

B B

SEC_CSEL

R524
470_0402_5%~D

1 2

R520

+5VMOD

C353

1 2

47P_0402_50V8J~D

INT_CD_L

C350

1 2

47P_0402_50V8J~D

IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0

IDE_SDIOW#
IDE_SDIORDY
IDE_IRQ15
IDE_SDA1
IDE_SDA0
IDE_SDCS1#
CDROM_ACT#

JMOD

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

SUYIN_80095AR-050G1T~D

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

Layout Note: Place close to CD-ROM CONN.

+5VMOD

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0603_10V4Z~D

1

1

C365

2

2

C368

C370

1

2

47P_0402_50V8J~D

IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
RSDDREQ
IDE_SDIOR#

RPDDACK#
PDIAG#

IDE_SDA2
IDE_SDCS3#

0.1U_0402_16V4Z~D

1

C363

2

C354

1 2

INT_CD_R

C367

1 2

10U_0805_10V4M~D

INT_CD_R <22>

R523

100K_0402_5%~D

1 2

+5VMOD

+5VMOD

Layout Note: W=80 mils

IDE_SDCS1#
IDE_SDCS3#

IDE_SDA2
IDE_SDA1
IDE_SDA0

IDE_SDD15
IDE_SDD14
IDE_SDD13
IDE_SDD12
IDE_SDD11
IDE_SDD10
IDE_SDD9
IDE_SDD8
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0

IDE_IRQ15
IDE_SDDACK#
RSDDREQ
IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY

IDE_SDDACK#

IDE_SDCS1# <19>
IDE_SDCS3# <19>
IDE_SDA[0..2] <19>

IDE_IRQ15 <19>
IDE_SDDACK# <19>
RSDDREQ <19>
IDE_SDIOR# <19>
IDE_SDIOW# <19>
IDE_SDIORDY <19>

R325

1 2

22_0402_5%~D

IDE_SDD[0..15] <19>

RPDDACK#

C261

0.1U_0402_16V4Z~D

C47

0.1U_0402_16V4Z~D

+5VSUS

1

2

+5VSUS

1

2

1

C259
10U_1206_16V4Z~D

2

USB_BACK_EN#<31>

1

C41
10U_1206_16V4Z~D

2

USB_BACK_EN#

USB_BACK_EN#

U20

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

U2

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

OC1#
OUT1
OUT2
OC2#

OC1#
OUT1
OUT2
OC2#

8
7
6
5

8
7
6
5

USB_OC0#

USB_OC1#

USB_OC4#

USB_OC5#

USB_OC0# <19>

USBP1_PWR
USBP0_PWR

USB_OC1# <19>

USB_OC4# <19>

USBP4_PWR
USBP5_PWR

USB_OC5# <19>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

USB 2.0 PORT and CD-ROM

LA-2501

1

25 48Tuesday, October 05, 2004

1.0

of

5

+3VSRC

D

6

S

VAUX_LAN

45

2

Q13

1

ENAB_3VLAN<34>

D D

Note: Place these components

as closeto the chip as possible.

L13

V_1P2_LAN

1 2

BLM11A601S_0603~D

G

SI3456DV-T1_TSOP6~D

3

C70

2

1

V_1P2_PLLVDD_PHY

1 2

BLM31A260SPT_1206~D

0.1U_0402_16V4Z~D

2.2U_0805_10V6K~D
C71

2

1

L28

C113

+3V_LOM_PCI

4.7U_0805_10V4Z~D

10U_0805_10V4M~D

C55

2

1

0.1U_0402_16V4Z~D
C103

C76

2

2

1

1

0.1U_0402_16V4Z~D

C80

C63

2

1

4

BCP69

V_3P3_LAN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C59

2

1

0.1U_0402_16V4Z~D
C108

2

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C104

C56

2

2

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C73

2

2

1

1

0.1U_0402_16V4Z~D

C82

2

2

1

1

V_3P3_LAN

LAN_CTRL_2P5V

BCP69_SOT223~D@

B

1

Q38

C

2

C1E

4

3

2

4

3

V_2P5_LAN

LAN_CTRL_1P2V

3

10U_0805_10V4M~D

C421

C60

0.1U_0402_16V4Z~D

C411

2

2

1

1

@

@

10U_0805_10V4M~D

4.7U_0805_10V4Z~D
C33

C22

2

2

1

1

1

Q36

BCP69_SOT223~D@

@

@

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C68

C61

2

1

2

2

1

1

@

3

2

0.1U_0402_16V4Z~D

C404

2

1

4

2

C45

1

V_2P5_LAN

@

4.7U_0805_10V4Z~D

10U_0805_10V4M~D

C402

C27

2

@

0.1U_0402_16V4Z~D

2

1

10U_0805_10V4M~D

2

C48

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C46

1

0.1U_0402_16V4Z~D

2

2

C37

C36

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C105

C29

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C43

1

0.1U_0402_16V4Z~D

2

2

C91

C31

1

1

1

V_1P2_LAN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C32

C30

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C50

C34

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

2

C35

1

1

For 5705M only

PCI_AD[0..31]<18,28,30>

C C

B B

V_3P3_LAN

A A

PCI_AD16

1K_0402_5%~D@

PCI_C_BE3#<18,28,30>
PCI_C_BE2#<18,28,30>
PCI_C_BE1#<18,28,30>
PCI_C_BE0#<18,28,30>

100_0402_5%~D

PCI_FRAME#<18,28,30>
PCI_IRDY#<18,28,30>
PCI_TRDY#<18,28,30>
PCI_DEVSEL#<18,28,30>
PCI_STOP#<18,28,30>

PCI_PERR#<18,28,30>
PCI_SERR#<18,28,30>

PCI_PAR<18,28,30>

CK_33M_LANPCI<6>

PCI_PIRQC#<18,28>

PCIRST_LOM#<18>

PCI_GNT4#<18>

PCI_REQ4#<18>

R35

1 2

R39

4.7K_0402_5%~D

SYS_PME#<28,30,31>

R130

10_0402_5%~D@

1 2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

R128

LAN_IDSEL

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
CK_33M_LANPCI

PCI_PIRQC#
PCIRST_LOM#
PCI_GNT4#
PCI_REQ4#

LAN_AUXPWR
SYS_PME#

12

CLK_82540_TERMCK_33M_LANPCI

12

5

B8

A8
C7
C6

B6

B5

A5

B4

B2

B1
C1
D3
D2
D1

E3

K1

L2

L1
M3
M2
M1
N2
N3

P3
N4

P4
M5
N5

P5

P6
M7
N7

C4

F3

L3
M4

A4

F2

F1
G3
H3
H1

J2

A2

J1

A3

H2
C2

J3
C3

J12

F4

A6

C114

1 2

8.2P_0402_50V8J~D@

U5A

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

BCM4401

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CBE3
CBE2
CBE1
CBE0

IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
PCI_CLK

INTA
PCI_RST
GNT
REQ

VAUXPRSNT
M66EN
PME

BCM4401KFB_FBGA196~D

REGSUP12

REGCTL12

REGSEN12
REGSUP25

REGCTL25

REGSEN25

EEDATA

LINKLEDB

SPD100LEDB
SPD1000LEDB
TRAFFICLEDB

PLLVDD2

XTALVDD

BIASVDD

SMB_CLK

SMB_DATA

4

TRD3+
TRD2+
TRD1+
TRD0+

VESD1
VESD2
VESD3

EECLK

XTALO

E13
E14

TRD3-

D13
D14

TRD2-

C13
C14

TRD1-

B13
B14

TRD0-

B9

LAN_CTRL_1P2V

B10
A9

B11

LAN_CTRL_2P5V

C11
C10

P1
G2
A1

LAN_EEDATA_SPROM_CS

P10

LAN_EECLK_SPROM_CLK

M10
H12

GPIO0

LAN_EEPROM_W

K13

GPIO1

J13

GPIO2

LINK_10#

G13

LINK_100#

H13

LED_1000#

G12

LAN_ACT#

G14

V_1P2_PLLVDD_PHY

H14
P7

NC

C12

TCK

D12

TDI

B12

TDO

A12

TMS

LAN_TRST#

D11

TRST

J14

XTALO

N10

XTALI

N11

XTALI

G11

SO

E10

SI

E11

SCLK

H11

CS

LAN_BIAS

A14

LAN_RDAC

D10

RDAC

A10
C9

R136

for 4401 :1.27K
for 5705M:1.2K

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

4.7K_0603_1%~D

R30

0_0402_5%~D

1 2

C25

27P_0402_50V8J~D

LAN_TX3+ <27>
LAN_TX3- <27>
LAN_TX2+ <27>
LAN_TX2- <27>
LAN_TX1+ <27>
LAN_TX1- <27>
LAN_TX0+ <27>
LAN_TX0- <27>

V_2P5_LAN
V_1P2_LAN
V_3P3_LAN
V_2P5_LAN

+3V_LOM_PCI

LINK_10# <27>
LINK_100# <27>
LED_1000# <27>
LAN_ACT# <27>

R135

12

V_2P5_LAN

2

1

12

R136

1.27K_0603_1%~D

V_1P2_LAN

U5B

E12

VDDC_E12

H5

VDDC_H5

H6

VDDC_H6

H7

VDDC_H7

H8

VDDC_H8

J5

VDDC_J5

J6

VDDC_J6

J7

VDDC_J7

J8

VDDC_J8

J9

VDDC_J9

J10

VDDC_J10

K5

VDDC_K5

K6

VDDC_K6

K7

V_3P3_LAN +3VRUN

@

BLM11A601S_0603~D

BLM11A601S_0603~D

12

12

L26

L27

+3V_LOM_PCI

Note: Place these components
as closeto the chip as possible.

X1

12

25MHz_20P_1BX25000CK1A~D

27P_0402_50V8J~D

2

C109
1000P_0402_50V7K~D

1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

C26

1

CLKRUN#<18,28,30,31>

L22

BLM11A601S_0603~D

1 2

3

0_0402_5%~D

1 2

V_2P5_LAN

Note: Place these components
as closeto the chip as possible.

V_2P5_LAN

V_3P3_LAN

R77

10U_0805_10V4M~D

2

C58

1

5705M_CLOCKRUN

VDDC_K7

K8

VDDC_K8

K9

VDDC_K9

K10

VDDC_K10

L5

VDDC_L5

L10

VDDC_L10

M14

VDDC_M14

N14

VDDC_N14

P8

VDDC_P8

P12

VDDC_P12

P13

VDDC_P13

P14

VDDC_P14

A7

VDDIO-PCI_A7

B3

VDDIO-PCI_B3

C5

VDDIO-PCI_C5

E1

VDDIO-PCI_E1

E4

VDDIO-PCI_E4

G1

VDDIO-PCI_G1

K3

VDDIO-PCI_K3

L4

VDDIO-PCI_L4

N6

VDDIO-PCI_N6

P2

VDDIO-PCI_P2

K14

VDDP_K14

L13

VDDP_L13

P11

VDDP_P11

A11

VDDIO_A11

F11

VDDIO_F11

K12

VDDIO_K12

L12

VDDIO_L12

C8

CSTSCHG

H4

CLKRUN

H10

NC_H10

J4

NC_J4

K4

NC_K4

J11

NC_J11

K11

NC_K11

L7

NC_L7

L8

NC_L8

BCM4401KFB_FBGA196~D

BCM4401

LOW_POWER

2

VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9

VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9

VSS_F10

VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9

VSS_G10

VSS_H9
VSS_K2

VSS_L6
VSS_L9

VSS_M6
VSS_M12
VSS_M13

VSS_N1
VSS_N12
VSS_N13

AVDDL_F12
AVDDL_F13

AVDD_F14
AVDD_A13

NC_L11
NC_L14

NC_M8
NC_M9

NC_N8
NC_N9
NC_P9

12

R72

R69

B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2

LAN_EEDATA_SPROM_CS

L6

LAN_EECLK_SPROM_CLK

L9

LAN_SPROM_DOUT

M6

LAN_SPROM_DIN

M12
M13
N1
N12
N13

AVDD1P2

F12
F13

AVDD2P5

F14
A13

R540

For 4401 only

R540

L11

1 2

L14

0_0402_5%~D

M8
M9

5705M_LOWPWR

M11
N8

NC_LAN_N9

N9

NC_LAN_P9

P9

LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS

10K_0402_5%~D

AT93C46-10SI-2.7_SO8~D

BLM11A601S_0603~D

1 2
1 2

2

C102

1

0_0402_5%~D@

1 2
1 2

1 2

0.1U_0402_16V4Z~D

2

@

1

R29

1U_0603_10V4Z~D

C86

R32 0_0402_5%~D
R34 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LAN Controller (BCM4401)

LA-2501

V_3P3_LAN

@

1K_0402_5%~D

12

12

R60

4.7K_0402_5%~D@

U3

1

CS

VCC

2

SK

3

DI

ORG

4

DO

GND

L18

L23

BLM11A601S_0603~D

@

1

@

0.1U_0402_16V4Z~D

C52

2

1

U6

8

VCC

7

WP

6

SCL

5

SDA

AT24C256_SO8~D@

V_3P3_LAN

8
7

NC

6
5

V_1P2_LAN
V_2P5_LAN

LAN_LOW_PWR <32>

LAN_SPROM_DOUT
LAN_SPROM_DIN

26 48Tuesday, October 05, 2004

Z2702

of

GND

1

A0

2

A1

3

NC

4

10K_0402_5%~D

12

R33

0.01U_0402_16V7K~D

2

C24

1

1.0

5

4

3

2

1

V_3P3_LAN

Layout Notice : Place
termination as close as
chip as possible

V_3P3_LAN

R350
10K_0402_5%~D

1 2

V_3P3_LAN

12

R387
10K_0402_5%~D@

1

LAN_ACT#

D72
RB495D_SOT23~D@

D D

LAN_TX0+<26>

LAN_TX0-<26>

LAN_TX1+<26>

LAN_TX1-<26>

LAN_TX2+<26>

LAN_TX2-<26>
LAN_TX3+<26>

LAN_TX3-<26>

@

@

C C

B B

R24

C40

@

49.9_0603_1%~D

49.9_0603_1%~D

R23

1 2

1 2

@

0.1U_0402_16V4Z~D

2

1

@

49.9_0603_1%~D

R21

R22

1 2

@

0.1U_0402_16V4Z~D

2

C39

1

49.9_0603_1%~D

49.9_0603_1%~D
R28

1 2

C28

49.9_0603_1%~D

R27

R25

1 2

1 2

0.1U_0402_16V4Z~D

2

C38

1

49.9_0603_1%~D

49.9_0603_1%~D
R26

1 2

1 2

0.1U_0402_16V4Z~D

2

1

LINK_10#<26>

LED_1000#<26>

LAN_ACT#<26>

LINK_10#

LED_1000#

For 5705M

3
2

R352
10K_0402_5%~D

1 2

V_2P5_LAN

C399 0.01U_0402_16V7K~D

1

2

C398 0.01U_0402_16V7K~D

V_3P3_LAN

200_0402_5%~D

200_0402_5%~D

12

12

R52

R377

JLOM

13

YELLOW

14

COMMON0

11

TRD1P

12

TRCT1

10

TRD1N

4

TRD2P

6

TRCT2

5

TRD2N

3

TRD3P

1

TRCT3

2

TRD3N

8

TRD4P

7

TRCT4

9

TRD4N

16

COMMON1

LINK_10#
LINK_100#

C396 0.01U_0402_16V7K~D

C397 0.01U_0402_16V7K~D

1

1

1

2

2

2

Place these caps as close
to the center tap pins
of the mag/connector.

17

GREEN

15

ORANGE

FOXCONN_JFM2411B-1112-7F~D

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

4 X 75 OHMS

1000pF 2KV

TRP1P

TRP1N

TRP2P

TRP2N

TRP3P

TRP3N

TRP4P

TRP4N

SHIELD018SHIELD1

202021

19

21

V_3P3_LAN

R355
10K_0402_5%~D

1 2

LINK_100#<26>

A A

LINK_100#

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LAN Transfomer and RJ45

LA-2501

1

27 48Tuesday, October 05, 2004

1.0

of

5

PCI_AD[0..31]<18,26,30>

D D

PCI_C_BE3#<18,26,30>
PCI_C_BE2#<18,26,30>
PCI_C_BE1#<18,26,30>
PCI_C_BE0#<18,26,30>

PCI_PAR<18,26,30>

PCI_FRAME#<18,26,30>
PCI_TRDY#<18,26,30>

C C

B B

PCI_AD17 CBS_IDSEL

+3VRUN

CLKRUN#<18,26,30,31>

+3VSUS

Layout Note: Place close to R5C841

CK_33M_CBPCI

@

10_0402_5%~D

12

R196

@

C171

4.7P_0402_50V8C~D

CK33M_CBS_TERM

2

1

A A

+3VSUS

R186

C657

12

1

2

5

100K_0402_5%~D

CBS_GRST#

1U_0603_10V4Z~D

PCI_IRDY#<18,26,30>
PCI_STOP#<18,26,30>
PCI_DEVSEL#<18,26,30>

1 2

PCI_PERR#<18,26,30>
PCI_SERR#<18,26,30>

PCI_REQ1#<18>

PCI_GNT1#<18>

CK_33M_CBPCI<6>

PCIRST_CB#<18,30>

R74 10K_0402_5%~D

1 2

R185 10K_0402_5%~D@

1 2

R183 0_0402_5%~D@

1 2

PCI_PIRQD#<18,30>
PCI_PIRQC#<18,26>
PCI_PIRQB#<16,18,30>

+3VSUS

R194 10K_0402_5%~D

1 2

R190 10K_0402_5%~D

1 2

R333 10K_0402_5%~D

+3VSUS

SYS_PME#<26,30,31>
CBS_SPK<22>

1 2

CB_HWSPND#<31>

R193 100K_0402_5%~D

1 2

IEEE1394_TPBIAS0

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

R192100_0402_5%~D

IRQ_SERIRQ<18,31>

CBS_SPK

R229

R241

C284

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ1#
PCI_GNT1#

PCIRST_CB#
CBS_GRST#

56.2_0603_1%~D

12

56.2_0603_1%~D

12

Z3008

270P_0402_50V7K~D

2

1

R239

R244

R261

M2
M1
N5
N4
N2
N1

P5

P4
R4
R2
R1

T2

T1
U2
U1

V1

T7

V7

W7

R8

T8

V8

W8

R9

V9

W9
T11
V11

W11

T12
V12

W12

P2

W2
W6

T9

V6

V3

W4

V4

V5

T5

P1

W5

T6

M4
M5

K1

L4
G2

L5

J2

K4

K2

J4
H1
H2
H4
H5
G1

G4

F1

F2

F4

56.2_0603_1%~D

12

56.2_0603_1%~D

12

5.1K_0603_1%~D

1 2

4

U17A

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR

FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL

PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#

INTA#
INTB#
INTC#

UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

RI_OUT#/PME#
SPKROUT
HWSPND#
TEST

R5C841_CSP208~D

0.01U_0402_16V7K~D

C243

C290

1

1

2

2

4

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1

R5C841

CSTSCHG/BVD1(STSCHG#/RI#)

0.33U_0603_10V7K~D

CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7

CAD6/CDATA13

CAD5/CDATA6

CAD4/CDATA12

CAD3/CDATA5

CAD2/CDATA11

CAD1/CDATA4
CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CCLKRUN#/WP(IOIS16#)

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CAUDIO/BVD2(SPKR#/LED)

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

Layout Note: Shield GND for
IEEE1394_TPA and TPB

CAD11/OE#

CAD10/CE2#

CGNT#/WE#

CCD1#/CD1#
CCD2#/CD2#

CVS1/VS1#
CVS2/VS2#

J1394

6
5

4
3
2
1

FOX_UV31413-WR01-TR~D

B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14

CBS_CC/BE3#

F16

CBS_CC/BE2#

K18

CBS_CC/BE1#

P15

CBS_CC/BE0#

V19

CBS_CPAR

N15

CBS_CFRAME#

K16

CBS_CTRDY#

L16

CBS_CIRDY#

K15

CBS_CSTOP#

M16

CBS_CDEVSEL#

L18

CBS_CBLOCK#

N19

CBS_CPERR#

N18

CBS_CSERR#

G16

CBS_CREQ#

G19

CBS_CGNT#

M15

CBS_CSTSCHNG

E18

CBS_CCLKRUN#

A18

CBS_CCLK_INTERNAL

L19

CBS_CINT#

M18

CBS_CRST#

H19

CBS_CAUDIO

F19

CBS_CCD1#_INTERNAL

T14

CBS_CCD2#_INTERNAL

D15

CBS_CVS1

R16

CBS_CVS2

H16

CBS_RSVD/D14

W18

CBS_RSVD/D2

C19

CBS_RSVD/A18

N16

3

CBS_CAD31 <29>
CBS_CAD30 <29>
CBS_CAD29 <29>
CBS_CAD28 <29>
CBS_CAD27 <29>
CBS_CAD26 <29>
CBS_CAD25 <29>
CBS_CAD24 <29>
CBS_CAD23 <29>
CBS_CAD22 <29>
CBS_CAD21 <29>
CBS_CAD20 <29>
CBS_CAD19 <29>
CBS_CAD18 <29>
CBS_CAD17 <29>
CBS_CAD16 <29>
CBS_CAD15 <29>
CBS_CAD14 <29>
CBS_CAD13 <29>
CBS_CAD12 <29>
CBS_CAD11 <29>
CBS_CAD10 <29>
CBS_CAD9 <29>
CBS_CAD8 <29>
CBS_CAD7 <29>
CBS_CAD6 <29>
CBS_CAD5 <29>
CBS_CAD4 <29>
CBS_CAD3 <29>
CBS_CAD2 <29>
CBS_CAD1 <29>
CBS_CAD0 <29>

CBS_CC/BE3# <29>
CBS_CC/BE2# <29>
CBS_CC/BE1# <29>
CBS_CC/BE0# <29>

CBS_CPAR <29>

CBS_CFRAME# <29>
CBS_CTRDY# <29>
CBS_CIRDY# <29>
CBS_CSTOP# <29>
CBS_CDEVSEL# <29>
CBS_CBLOCK# <29>
CBS_CPERR# <29>
CBS_CSERR# <29>
CBS_CREQ# <29>
CBS_CGNT# <29>

R230 47_0402_5%~D

CBS_CINT# <29>

CBS_CRST# <29>

CBS_CAUDIO <29>

CBS_CVS1 <29>
CBS_CVS2 <29>

CBS_RSVD/D14 <29>
CBS_RSVD/D2 <29>
CBS_RSVD/A18 <29>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Layout Note: Shield GND for
CBS_CAD13 and CBS_CAD15

CBS_CSTSCHNG <29>
CBS_CCLKRUN# <29>

12

CBS_CRST#

3

C255

12P_0402_50V8J

12

C256

12P_0402_50V8J

12

Layout Note: Place close to R5C841
and Shield GND for these signals

2

C253

1

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

CBS_CCLK <29>

CBS_CCD2# <29>

0_0402_5%~D

270P_0402_50V7K~D

0.01U_0402_16V7K~D

@

C236

1 2

2

1

CBS_CCD1# <29>

R217
0_0402_5%~D

270P_0402_50V7K~D

@

R211

C218

C400

1 2

2

1

1

2

R5C841XI

X4

24.576MHz_16P_1BG24576CKIA~D

1 2

R5C841XO

C234 0.01U_0402_16V7K~D

1 2

Layout Note: Shield GND
for USBP3+ and USBP3-

0.01U_0402_16V7K~D
10K_0603_1%~D

R191

1 2

USBP3+<19>
USBP3-<19>

VPPEN0<29>
VPPEN1<29>

VCC5EN#<29>
VCC3EN#<29>

2

Layout Note: Place close to R5C841
and Shield GND for SD_CLK

+3V_PHY

R5C841XI
R5C841XO

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

IEEE1394_TPBIAS0

100K_0402_5%~D

12

R188

R195

2

1

U17B

100K_0402_5%~D

12

D11

CPS

A16

XI

B16

XO

A14

FIL0

B12

TPAP0

A12

TPAN0

B13

TPBP0

A13

TPBN0

B10

TPAP1

A10

TPAN1

B11

TPBP1

A11

TPBN1

D12

TPBIAS0

D10

TPBIAS1

D13

VREF

B14

REXT

V14

USBDP

W14

USBDM

V13

VPPEN0

W13

VPPEN1

R13

VCC5EN#

T13

VCC3EN#

R7

REGEN#

R5C841_CSP208~D

SD_EN

R5C841

10K_0402_5%~D

12

R543

+3VSUS

U34

3
4

2

RT9701-CB_SOT23-5

VIN
VIN/CE

GND

B1

MDIO00

A2

MDIO01

A3

MDIO02

B3

MDIO03

B4

MDIO04

A5

MDIO05

B5

MDIO06

D5

MDIO07

A6

MDIO08

B6

MDIO09

D6

MDIO10

E6

MDIO11

A7

MDIO12

B7

MDIO13

D7

MDIO14

E7

MDIO15

A8

MDIO16

B8

MDIO17

D8

MDIO18

E8

MDIO19

1 2

Layout Note: Shield GND for SD_CLK

1

VOUT

5

VOUT

SD_EN

R73
0_0402_5%~D

For RICHO R5C841 Review Control

REV. Date

12/18/030.1

0.2 02/17/04

Remark

Initial

Lot Number
Changed

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CardBus Controller(R5C841)

LA-2501

1

SD_DET# <29>

SD_WP <29>

SD_CMD <29>

SD_DATA0 <29>
SD_DATA1 <29>
SD_DATA2 <29>
SD_DATA3 <29>

SD_CLK <29>

+SD_VCC

28 48Tuesday, October 05, 2004

1.0

of

5

+3VSUS

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

10U_0805_10V4M~D

C649

C206

C202

C176

1

0.01U_0402_16V7K~D

+3VSUS

C227

0.01U_0402_16V7K~D

1

2

0.1U_0402_16V4Z~D

1

2

2

1

C651

10U_0805_10V4M~D

1

2

+5VSUS

C156

C164

2

1

2

0.01U_0402_16V7K~D

C652

0.1U_0402_16V4Z~D

1

2

+3VRUN

D D

10U_0805_10V4M~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C240

C239

1

2

C C

B B

C228

C225

1

2

1

1

2

2

C650

C509

VPPEN0<28>
VPPEN1<28>

VCC3EN#<28>
VCC5EN#<28>

0.1U_0402_16V4Z~D

1

2

C241

1

2

1

2

0.47U_0603_16V7K~D

+3VSUS

0.01U_0402_16V7K~D

C653

1

2

C220

1

2

C200

1

2

0.01U_0402_16V7K~D

1

2

0.47U_0603_16V7K~D

11

13
15

16

Layout Note: Place close to SD CONN.

+SD_VCC

A A

C648

0.1U_0402_16V4Z~D

1U_0603_10V4Z~D

1

1

C660

2

2

5

0.01U_0402_16V7K~D

C254

1

1

2

2

0.01U_0402_16V7K~D

10U_0805_10V4M~D

C178

1

2

+3V_PHY

U14

VCC3IN

VCCOUT
VCCOUT
VCCOUT

VCC5IN
VCC5IN

3

EN0
EN1

VCC3_EN
VCC5_EN

FLG
GND

VPPOUT

SD_DATA3<28>

SD_CMD<28>

SD_CLK<28>
SD_DATA0<28>

SD_DATA1<28>
SD_DATA2<28>

SD_DET#<28>

SD_WP<28>

+SD_VCC

4

2
1

5

R5531V002-E2-FA_SSOP16~D

NC
NC
NC

R78

U17C

F5

G5
J19
K19

W3

R11
R12

A4

R6

E13

L1

E14

E10
E11
A17
B17

A9
B9

D9

D14
A15
B15

J1
J5
K5

E9
R10
T10
V10

W10

L15
M19

R5C841_CSP208~D

9
14
12

CBS_VPP

8

C355

7
6
10

+SD_VCC

33K_0402_5%~D

12

4

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3

VCC_MD3V

VCC_RIN1
VCC_RIN2

VCC_ROUT1
VCC_ROUT2

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

CBS_VCC+3VSUS

0.1U_0402_16V4Z~D

1

2

4

R5C841

0.1U_0402_16V4Z~D

C351

1

2

JSD

1

CD/DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

DETECT#

11

WP_VSS

12

WP

Molex_SD-67840-0002~D

GND1
GND2
GND3
GND4

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

3

L31

+3VSUS

L2
C1
D1
E1
C2
D2
E2
E4
E12

1 2

BLM21A601SPT_0805~D

C654

22U_D2_6.3VM~D

1

C177

1

+

2

2

2

+3V_PHY

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

C179

1

1

2

C655

1

C656

2

2

1

Place close to JCBUS

CBS_VCCCBS_VPP

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C13

2

CBS_CAD13 & CBS_CAD15 Layout Need to

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5

CBS_CAD7

CBS_CC/BE0#<28>

CBS_CC/BE1#<28>

CBS_CPAR<28>

CBS_CPERR#<28>
CBS_CGNT#<28>
CBS_CINT#<28>

CBS_VCC

CBS_VPP

CBS_CCLK<28>
CBS_CIRDY#<28>
CBS_CC/BE2#<28>

13
14
15
16

CBS_RSVD/D2<28>

CBS_CCLKRUN#<28>

CBS_CC/BE0#
CBS_CAD9
CBS_CAD11

CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR

CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#

CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22

CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26

CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

JCBUS

1

A_CAD0

2

A_CAD1

3

A_CAD3

4

A_CAD5

5

GND0

6

A_CAD7

7

A_PCI_C/BE0#

8

A_CAD9

9

A_CAD11

10

GND1

11

A_CAD12

12

A_CAD14

13

A_PCI_C/BE1#

14

A_CPAR

15

GND2

16

A_CPERR#

17

A_CGNT#

18

A_CINT#

19

+AVCC0

20

GND3

21

+AVPP0

22

A_CCLK

23

A_CIRDY

24

A_PCI_C/BE2#

25

GND4

26

A_CAD18

27

A_CAD20

28

A_CAD21

29

A_CAD22

30

GND5

31

A_CAD23

32

A_CAD24

33

A_CAD25

34

A_CAD26

35

GND6

36

A_CAD27

37

A_CAD29

38

CB_A_D2

39

A_CCLKRUN#

40

GND7

FOX_QT60080A-B121C-9F~D

Follow USB2.0 Designal Guildline.

80

GND15

A_CCD1#

A_CAD2
A_CAD4
A_CAD6

GND14

CB_A_D14

A_CAD8

A_CAD10

A_CVS1

GND13
A_CAD13
A_CAD15
A_CAD16

CB_A_A18

GND12

A_CBLOCK#

A_CSTOP#

A_CDEVSEL#

+AVCC1

GND11

+AVPP1

A_CTRDY#

A_CFRAME#

A_CAD17

GND10
A_CAD19

A_CVS2

A_CRST#

A_CSERR#

GND9

A_CREQ#

A_PCI_C/BE3#

A_CAUDIO

A_CSTSCHG

GND8
A_CAD28
A_CAD30
A_CAD31
A_CCD2#

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6

CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1

CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_RSVD/A18

CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17

CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#

CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG

CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#

CBS_CCD1# <28>

CBS_RSVD/D14 <28>

CBS_CVS1 <28>

CBS_RSVD/A18 <28>
CBS_CBLOCK# <28>

CBS_CSTOP# <28>
CBS_CDEVSEL# <28>

CBS_VCC

Width = 30mils

CBS_VPP

CBS_CTRDY# <28>
CBS_CFRAME# <28>

CBS_CVS2 <28>
CBS_CRST# <28>
CBS_CSERR# <28>

CBS_CREQ# <28>
CBS_CC/BE3# <28>
CBS_CAUDIO <28>
CBS_CSTSCHNG <28>

CBS_CCD2# <28>

0.01U_0402_16V7K~D

1

1

C410

C14

2

2

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

1

2

0.01U_0402_16V7K~D

C412

10U_0805_10V4M~D

1

C413

2

CBS_CAD31 <28>
CBS_CAD30 <28>
CBS_CAD29 <28>
CBS_CAD28 <28>
CBS_CAD27 <28>
CBS_CAD26 <28>
CBS_CAD25 <28>
CBS_CAD24 <28>
CBS_CAD23 <28>
CBS_CAD22 <28>
CBS_CAD21 <28>
CBS_CAD20 <28>
CBS_CAD19 <28>
CBS_CAD18 <28>
CBS_CAD17 <28>
CBS_CAD16 <28>
CBS_CAD15 <28>
CBS_CAD14 <28>
CBS_CAD13 <28>
CBS_CAD12 <28>
CBS_CAD11 <28>
CBS_CAD10 <28>
CBS_CAD9 <28>
CBS_CAD8 <28>
CBS_CAD7 <28>
CBS_CAD6 <28>
CBS_CAD5 <28>
CBS_CAD4 <28>
CBS_CAD3 <28>
CBS_CAD2 <28>
CBS_CAD1 <28>
CBS_CAD0 <28>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
CardBus/SD card Socket

LA-2501

29 48Tuesday, October 05, 2004

1

1.0

of

5

PCI_AD[0..31]<18,26,28>

D D

C C

B B

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

CK_33M_MINIPCI

R179
10_0402_5%~D

1 2

CK_33M_MINPCI_TERM

2

C157

4.7P_0402_50V8C~D

1

COEX2_WLAN_ACTIVE<24>

HW_RADIO_DIS#<24,32>

CK_33M_MINIPCI<6>

PCI_C_BE3#<18,26,28>

PCI_C_BE2#<18,26,28>

PCI_C_BE1#<18,26,28>

DEBUG_ENABLE<31>

PCI_IRDY#<18,26,28>

PCI_SERR#<18,26,28>
PCI_PERR#<18,26,28>

PCI_PIRQD#<18,28>

PCI_REQ3#<18>

CLKRUN#<18,26,28,31>

+5VRUN

4

R181
0_0402_5%~D

1 2

3

+3VRUN+3VRUN

JPCI

1

TIP

3

8PMJ-3

5

8PMJ-6

7

8PMJ-7

9

8PMJ-8

11

HW_RADIO_DIS#

PCI_PIRQD#

PCI_REQ3#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

CLKRUN#
PCI_SERR# PCI_STOP#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

LED1_GRNP

13

LED1_GRNN

15

CHSGND

17

INTB#

19

3.3V

21

RESERVED

23

GROUND

25

CLK

27

GROUND

29

REQ#

31

3.3V

33

AD31

35

AD29

37

GROUND

39

AD27

41

AD25

43

RESERVED

45

C/BE3#

47

AD23

49

GROUND

51

AD21

53

AD19

55

GROUND

57

AD17

59

C/BE2#

61

IRDY#

63

3.3V

65

CLKRUN#

67

SERR#

69

GROUND

71

PERR#

73

C/BE1#

75

AD14

77

GROUND

79

AD12

81

AD10

83

GROUND

85

AD8

87

AD7

89

3.3V

91

AD5

93

RESERVED

95

AD3

97

5V

99

AD1

101

GROUND

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND

115

SYS_AUDIO_OUT

117

SYS_AUDIO_OUT GND

119

AUDIO_GND

121

RESERVED

123

VCC5A

AMP_1318644-1~D

AC_SDATA_OUT

AC_CODEC_ID0#

SYS_AUDIO_IN

SYS_AUDIO_IN GND

AUDIO_GND

RING

8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5

LED2_YELP

LED2_YELN

RESERVED

INTA#

RESERVED

3.3VAUX
RST#

3.3V

GNT#

GROUND

PME#

RESERVED

AD30

3.3V
AD28
AD26
AD24

IDSEL

GROUND

AD22
AD20

PAR
AD18
AD16

GROUND

FRAME#

TRDY#
STOP#

3.3V
DEVSEL#
GROUND

AD15
AD13
AD11

GROUND

AD9

C/BE0#

3.3V

AD6
AD4
AD2

AD0
RESERVED
RESERVED

GROUND

M66EN

AC_RESET#

RESERVED

GROUND

MCPIACT#

3.3VAUX

2

4
6
8
10
12
14
16
18

5V

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

LED_WLAN24
LED_WLAN5

R146 0_0402_5%~D

MPCIACT#

2

R149 100K_0402_5%~D
R148 100K_0402_5%~D

PCI_PIRQB#

PCIRST_CB#CK_33M_MINIPCI
PCI_GNT3#
SYS_PME#

1 2

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

DEBUG_OUT

V_3P3_LAN

2

C137

0.1U_0402_16V4Z~D

1

LED_WLAN24
LED_WLAN5

1 2
1 2

PCI_PIRQB# <16,18,28>

PCIRST_CB# <18,28>
PCI_GNT3# <18>

SYS_PME# <26,28,31>

R147

@

10K_0402_5%~D

1 2

R145

100_0402_5%~D

PCI_PAR <18,26,28>

PCI_FRAME# <18,26,28>
PCI_TRDY# <18,26,28>
PCI_STOP# <18,26,28>

PCI_DEVSEL# <18,26,28>

PCI_C_BE0# <18,26,28>

DEBUG_OUT <31>

R150

1 2

10K_0402_5%~D

+3VRUN

5

U12

1

P

INB

4

O

2

INA

G

TC7SH32FU_SSOP5~D

3

COEX1_BT_ACTIVE <24>

12

PCI_AD19

+3VSUS

1

R138 200_0402_5%~D

1 2

V_3P3_LAN

2

C135

0.1U_0402_16V4Z~D

1

LED_WLAN_OUT <35>

+5VRUN

2

C136

0.1U_0402_16V4Z~D

1

+3VRUN

2

C158

0.047U_0402_16V4Z~D

1

A A

2

C133

0.047U_0402_16V4Z~D

1

2

C470

0.047U_0402_16V4Z~D

1

2

C159

0.047U_0402_16V4Z~D

1

2

C153

0.047U_0402_16V4Z~D

1

2

C132

0.047U_0402_16V4Z~D

1

2

C130

0.047U_0402_16V4Z~D

1

2

C131

0.047U_0402_16V4Z~D

1

2

C152

0.047U_0402_16V4Z~D

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

MINIPCI

LA-2501

30 48Tuesday, October 05, 2004

1

1.0

of

+3VALW

R330

D D

DEBUG_ENABLE<30>

DEBUG_OUT<30>

C C

B B

These Caps need to be
located as close to
power pins as possible

5

12

12

12

R321

10K_0402_5%~D

KSO_17<33>

R320

10K_0402_5%~D

10K_0402_5%~D

ATF_INT#
SYS_PME#
DEBUG_ENABLE

CB_HWSPND#<28>

HP_NB_SENSE<23>
RUN_ON_D<44>
VAUX_EN<34>

USB_BACK_EN#<25>

SIO_EXT_SMI#<20>
SIO_EXT_SCI#<20>
SIO_EXT_WAK#<20>
SIO_RCIN#<18>
NB_MUTE<23>
BEEP<22>

SIO_SLP_S3#<20>

SYS_PME#<26,28,30>

ATF_INT#<13>

SIO_SLP_S5#<20>
SPDIF_SHDN<17,22>

T79 PAD~D

RUN_ON<16,34,35,40,41,44>
ICH_PME#<18>
SIO_THRM#<20>
SUS_ON<34,35,40>
SIO_PWRBTN#<20>

5V_CAL_SIO#<13>
IDE_RST_HDD<19>

IDE_RST_MOD<25>
GC_BL_SUSPEND<16>

MODC_EN#<34>
HDDC_EN#<34>

CK_33M_SIOPCI<6>

R501

0_0402_5%~D@

R40

0_0402_5%~D

+3VRUN

T16 PAD~D
T40 PAD~D

T31 PAD~D

T32 PAD~D

T38 PAD~D

T90 PAD~D
T14 PAD~D
T35 PAD~D

CK_14M_SIO<6>

T6 PAD~D

12

12

254VCC0

2

C599

1

0.1U_0402_16V4Z~D

L46

BLM11A121S_0603~D

1 2

KSO_17

1.5mm SMT~D@

+RTC_CELL

D21

RB751V_SOD323~D

2 1

J1397

1

1

2

2

3

3

+3.3VX

4

CB_HWSPND#
HP_NB_SENSE
RUN_ON_D
VAUX_EN
KSO17
USB_BACK_EN#

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAK#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT

SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S5#
SPDIF_SHDN
LID_CL_SIO#

ICH_PCIE_WAKE#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
SIO_PWRBTN#

5V_CAL_SIO#
IDE_RST_HDD

IDE_RST_MOD
GC_BL_SUSPEND

MODC_EN#
HDDC_EN#

CK_33M_SIOPCI
CK_14M_SIO

+3VALW

+3VRUN

KPLLVCC

2

C352

0.1U_0402_16V4Z~D

1

R12

100K_0402_5%~D

1 2

U24A

F13

SGPIO30

F14

SGPIO31

E16

SGPIO32

E15

SGPIO33

E12

SGPIO34

E13

SGPIO35

D16

SGPIO36

D15

SGPIO37

C16

SGPIO40

B16

SGPIO41

C15

SGPIO42

A16

SGPIO43

D14

SGPIO44

C14

SGPIO45

C13

SGPIO46

B14

SGPIO47

T5

LGPIO50

N6

LGPIO51

L6

LGPIO52

R6

LGPIO53

T6

LGPIO54

L7

LGPIO55

P7

LGPIO56

N7

LGPIO57

A15

LGPIO60/SPCLK

D13

LGPIO61/SPDOUT

A14

LGPIO62/SPDIN

C12

LGPIO63

B13

LGPIO64

A13

LGPIO65

D12

LGPIO66

F11

LGPIO67

B12

LGPIO70

A12

LGPIO71

C11

LGPIO72

D11

LGPIO73

E11

LGPIO74

A11

LGPIO75

F10

LGPIO76

C10

LGPIO77

L3

PCI_CLK

L4

CLOCKI

B2

GPIO83/32KHZ_OUT

E2

VCCO/BAT

M7

VCC1_1

B11

VCC1_2

R13

VCC1_3

H12

VCC1_4

E14

VCC1_5

B7

VCC1_6

A1

VCC1_7

L11

VCC1_8

G2

VCC2_1

P4

VCC2_2

J2

VCC2_3

M2

VCC2_4

R5

VCC2_5/PLL

P6

VSS13/PLL

LPC47N354_LBGA256~D

LPC47N354

MACALLEN III

8051
GPIO

LPC
GPIO

CLOCK

VCC

256 - LBGA

3

EC_SCI/SPDIN

SER_IRQ

CLKRUN#

LDRQ0#

LPC INTERFACE

LDRQ1#

LFRAME#

LRESET#

DLAD0
DLAD1
DLAD2
DLAD3

DLDRQ1#

DLFRAME#

DSER_IRQ

DCLKRUN#

COM1

GPIO10/WK_SE14/IRMODE/IRRX3B

IR

GPIOB2/SLCTIN

GPIOB1/INIT

GPIOC0/PD0
GPIOC1/PD1
GPIOC2/PD2
GPIOC3/PD3
GPIOC4/PD4
GPIOC5/PD5
GPIOC6/PD6
GPIOC7/PD7

LPT

OUTD0/SLCT

OUTD1/PE

OUTD2/BUSY

OUTD3/ACK

OUTD4/ERROR

GPIOB0/STROBE

GPIOB3/ALF

GND

LAD0
LAD1
LAD2
LAD3

RXD1

TXD1

DSR
RTS
CTS
DTR

DCD

IRRX
IRTX

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

AGND

J12
T4
P5

M3
R1
T1
P3

M6
R3

N4
L2

N2
P1
P2
N3

R2
T2
R4
T3

R290 10K_0402_5%~D

K1

TXD0

K5

R289 10K_0402_5%~D

K2
K4

R288 10K_0402_5%~D

K3
K6

R517 10K_0402_5%~D

B10

RI

R300 10K_0402_5%~D

L1

H15
K14
M4

J4

R338

J5

J1
H2
H1
H3
H4
H5
H6
H8

F1
G5
G1
H7
J6

K7
J7

C2
G4
N5
R15
B15
G9
J3
N1
T10
J11
G14
B6

KAGND

F3

IRQ_SERIRQ
CLKRUN#

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ0#
LPC_LDRQ1#

LPC_LFRAME#
PCIRST_SIO#

1 2
1 2
1 2
1 2

1 2

10K_0402_5%~D

1 2

1 2

BLM11A121S_0603~D

+3.3VX

L85

IRQ_SERIRQ <18,28>

LPC_LDRQ0# <19>
LPC_LDRQ1# <19>

LPC_LFRAME# <19>
PCIRST_SIO# <18>

COINCELL

12

R509
1K_0402_5%~D

COINCELL_R

2

3

1

2

CLKRUN# <18,26,28,30>

LPC_LAD[0..3] <19>

+3VRUN

D20
BAT54C_SOT23~D

1

C596

2

1U_0603_10V4Z~D

CK_33M_SIOPCI
CK_14M_SIO

Note: For system debug
pin4 connect to serial port pin3

U36

1

NC

TXD0

2

IN A

3

GND

TC7SH04FU_SSOP5~D@

+3VALW

12

R324
100K_0402_5%~D

LID_CL_SIO#

1

R503

2

10_0402_5%~D@

+RTC_CELL

R502

10_0402_5%~D@

12

12

5

VCC

4

OUT Y

R329

10_0402_5%~D

C362

0.047U_0402_10V7K~D

1

+5VSUS

T13PAD~D

LID_CL#

12

LID_CL# <33>

+3VRUN+3VALW

1

1

C364

C601

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

A A

C614

0.1U_0402_16V4Z~D

1

1

1

1

C373

C7

2

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C12

2

0.1U_0402_16V4Z~D

1

C79

C87

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C600

0.1U_0402_16V4Z~D

2

1

2

C349

1

1

0.1U_0402_16V4Z~D

1

C88

C90

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C597

CK_14M_SIO_TERM

CK_33M_SIOPCI_TERM

2

2

C598

1

1

4.7P_0402_50V8C~D@

4.7P_0402_50V8C~D@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SIO LPC47N354(1/2)

LA-2501

31 48Tuesday, October 05, 2004

1

1.0

of

5

+5VALW

R322

IN2

12

4.7K_0402_5%~D

D D

R339

1 2

4.7K_0402_5%~D

R326

10K_0402_5%~D

@

C C

+3VALW+3VALW

+3VALW

R512

1 2

PBAT_ALARM#

1 2

10K_0402_5%~D

IN6
IN5

FPVCC

R513

4.7K_0402_5%~D

12

Note: SMSC errata
LPC47N354 A Rev Anomaly -

Touch Pad IMCLK and IMDAT signals are inverted

CLK_SM2<33>

+5VRUN

B B

R500

4.7K_0402_5%~D

DAT_KBD
CLK_KBD
CLK_SM1
DAT_SM1 CLK_32KX2

A A

DAT_SM2<33>

12

12

R299

1 2

4.7K_0402_5%~D

R301

R297

1 2

5

4.7K_0402_5%~D

4.7K_0402_5%~D

22P_0402_50V8J~D

22P_0402_50V8J~D

R507

R318

R511

1 2

1 2

10K_0402_5%~D

10K_0402_5%~D

@

@

BID0
BID1
BID2
BID3

@

CLK_SM2<33>
DAT_SM2<33>

PBAT_ALARM#<38>

KSO[0..15]<33>

C338

1 2

C339

1 2

R311

1 2

10K_0402_5%~D

@

+3VALW

PBAT_PRES#<38>

THERMTRIP_SIO<13>

T36 PAD~D

T33 PAD~D

KSO16<33>
CAP_LED#<35>
NUM_LED#<35>
SRL_LED#<35>

T15 PAD~D

PS_ID_DISABLE#<37>

T11 PAD~D

T8 PAD~D

T7 PAD~D

T9 PAD~D

T89 PAD~D

T37 PAD~D
T39 PAD~D

CLK_SM2
DAT_SM2

KSI[0..7]<33>

+3VRUN

1 2

10K_0402_5%~D

R319 10K_0402_5%~D@
R506 10K_0402_5%~D@
R510 10K_0402_5%~D@
R312 10K_0402_5%~D@

R327 100K_0402_5%~D

1 2

R331 100K_0402_5%~D

1 2

NB_PSID<37>

M_LED_C<33>
M_LED_B<33>
M_LED_A<33>

12

X6

32.768KHZ_12.5P_MC-306~D

3.8X12.1mm

CLK_32KX1

1 2
1 2
1 2
1 2

4

@

IN2

@

FPVCC
IN5
IN6
PBAT_PRES#

THERMTRIP_SIO
H_PROCHOT_SIO#

KSO16
CAP_LED#
NUM_LED#
SRL_LED#

NB_PSID
BID0

BID1
BID2
BID3
PS_ID_DISABLE#

SIO_MSCLK
SIO_MSDAT

CLK_SM1
DAT_SM1

CLK_SM2
DAT_SM2

CLK_KBD
DAT_KBD
PBAT_ALARM#

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6 SIO_FA11
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

4

U24B

A9

IN0 (WK_EE4)

B9

IN1 (WK_EE2)

B8

IN2 (WK_EE3)

A8

IN3 (GPWKUP)

C8

IN5 (WK_SE01)

D8

IN6 (WK_SE05)

E8

IN7 (WK_EE1)

H13

GPIO0 (WK_SE02)

H11

GPIO1 (WK_SE03)

H10

GPIO2 (WK_SE04)

G10

GPIO3 (TRIGGER)

G13

GPIO7 (WK_SE06)

J14

GPIO8 (WK_SE12)/IRRX2

J16

GPIO9 (WK_SE13)/IRTX2

G11

GPIO17 (WK_SE23)/A20M

F15

GPIO20 (WK_SE25)/PS2CLK/8051RX

F12

GPIO21 (WK_SE26)/PS2DAT/8051TX

B5

GPIO84

E5

GPIO85

D5

GPIO86

A4

GPIO87

B4

GPIO90

C5

GPIO91

A3

GPIO92

A2

GPIO93

C3

GPIO96

D3

GPIO97

B1

GPIOA0

D4

GPIOA1

C1

GPIOA2

D10

MSCLK/SPCLK

E10

MSDATA/SPDOUT

G6

EMCLK

G3

EMDAT

B3

GPIO94/IMCLK

C4

GPIO95/IMDAT

M1

KCLK

M5

KDAT

G15

GPIO6 (WK_SE11)/IRMODE/IRRX3A

G12

GPIO5 (WK_SE10)/KSO15

G16

GPIO4 (WK_SE07)/KSO14

R7

KSO13/GPIO18(WK_SE27)

T7

KSO12/OUT8/KBRST

K8

KSO11

J8

KSO10

L8

KSO9

M8

KSO8

N8

KSO7

P8

KSO6

T8

KSO5

R8

KSO4

R9

KSO3

T9

KSO2

P9

KSO1

N9

KSO0

M9

KSI7

L9

KSI6

K9

KSI5

K10

KSI4

M10

KSI3

R10

KSI2

N10

KSI1

P10

KSI0

E1

XTAL1

D1

XTAL2

LPC47N354_LBGA256~D

GPIO

K/B

LPC47N354

MACALLEN III

MISC

GPIO11 (WK_SE15)/AB2A_DATA

GPIO12 (WK_SE16)/AB2A_CLK

GPIO13 (WK_SE17)/AB2B_DATA

GPIO14 (WK_SE20)/AB2B_CLK
GPIO15 (WK_SE21)/FAN_TACH1
GPIO16 (WK_SE22)/FAN_TACH2

256 - LBGA

3

FPGM

TEST_PIN

XOSEL
SYSOPT0/GPIO80
SYSOPT1/GPIO81

BAT_LED

PWR_LED

GPIOA3/WINDMON

TESTA

VCC1RST#

RESET_OUT

PWRGD

ACAV_IN

POWER_SW_IN#

ALWON

OUT0

OUT1/IRQ8

OUT2/FRD

OUT3/FWR

OUT4

OUT5/KBRST

OUT6

OUT7/SMI

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

AB1A_CLK

AB1B_DATA

AB1B_CLK

AB1A_DATA

GPIO82/FAN_TACH3

GPIO19 (WK_SE24)

FA10
FA11
FA12
FA13
FA14
FA15

FLASH

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

FA16
FA17
FA18
FA19
FA20
FA21
FA22

FRD
FWR

3

FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9

FCS
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0

2

+3VALW

12

+3VALW

12

R528
1K_0402_5%~D

@

R527

L10
K12
E4

K15
K16
J9
J10
E3
F2

D2
L5
K13

F4
F5
F6

D7
C7
F7
A6
E6
D6
C6
E7
A7
G7
G8
F8

C9
F9
E9
D9
H16
H14
J15
J13
A10
H9
A5
F16

N12
T13
P12
T14
T15
R16
N13
P16
M14
N15
N16
M13
L12
M15
M16
L14
L13
L15
L16
K11
R14
T16
P13
P14
N14
P15
M12
R12
T12
P11
N11
M11
R11
T11

SIO_KAH_PGM

XOSEL
SYSOPT0
SYSOPT1
BAT1_LED#
BAT2_LED#

VCC1RST#
RESET_OUT#
RUNPWROK

ACAV_IN
ALWON
EEPROM_WC
HW_RADIO_DIS#

LAN_LOW_PWR
CHG_PBATT

AUDIO_AVDD_ON

FAN2_PWM
BREATH_LED
FAN1_PWM

CLK_SMB
SMBUS_DATA
SMBUS_CLK
DAT_SMB
SMBDAT_VGA
SMBCLK_VGA
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH
FAN2_TACH

SIO_A20GATE

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10

SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

FRD#
FWR#
FCS#
SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0

SIO_FA[0..19] <33>

FRD# <33>
FWR# <33>
FCS# <33>

SIO_FD[0..7] <33>

10K_0402_5%~D

12

R508 10K_0402_5%~D
R334 10K_0402_5%~D
R335 10K_0402_5%~D

BAT1_LED# <35>
BAT2_LED# <35>

VCC1RST# <33>
RESET_OUT# <35>
RUNPWROK <16,35,39,42,44>

ACAV_IN <43>
ALWON <40>
EEPROM_WC <33>
HW_RADIO_DIS# <24,30>

LAN_LOW_PWR <26>
CHG_PBATT <43>

AUDIO_AVDD_ON <22>

FAN2_PWM <13>
BREATH_LED <35>
FAN1_PWM <13>

CLK_SMB <13,33>

DAT_SMB <13,33>
SMBDAT_VGA <16>
SMBCLK_VGA <16>
PBAT_SMBDAT <38,43>

PBAT_SMBCLK <38,43>
FAN1_TACH <13>
FAN2_TACH <13>

SIO_A20GATE <18>

12
1 2
1 2

1 2

R505 0_0402_5%~D

R491

1K_0402_5%~D

1

C

E

3

POWER_SW#POWER_SW_IN#

POWER_SW# <13,35>

Level shifter

H_PROCHOT_SIO#

PROCHOT_SFTON

Q39

2

B

MMBT3904_SOT23~D

R409
56_0402_5%~D

1 2

R410
56_0402_5%~D

1 2

DAT_SMB

CLK_SMB

POWER_SW_IN#

SMBDAT_VGA

SMBCLK_VGA

PBAT_SMBDAT

PBAT_SMBCLK

SMBUS_DATA

SMBUS_CLK

LAN_LOW_PWR
CHG_PBATT

1

+VCCP

+VCCP

H_PROCHOT# <7>FPVCC<16>

R516

10K_0402_5%~D

1 2

R515

10K_0402_5%~D

1 2

R504
100K_0402_5%~D

1 2

1

C609
1U_0603_10V4Z~D

2

R337

8.2K_0402_5%~D

1 2

R525

8.2K_0402_5%~D

1 2

R336

8.2K_0402_5%~D

1 2

R526

8.2K_0402_5%~D

1 2

R519

10K_0402_5%~D

1 2

R518

10K_0402_5%~D

1 2

+3VALW

R323

10K_0402_5%~D

@

12

R304
100K_0402_5%~D

1 2

+3VALW

+RTC_CELL

+5VALW

+3VALW

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SIO LPC47N354(2/2)

LA-2501

32 48Tuesday, October 05, 2004

1

1.0

of

5

Note: SMSC errata
LPC47N354 A Rev Anomaly - Touch Pad IMCLK and IMDAT signals are inverted

4

3

2

1

+5VRUN +3VALW+3VALW

D D

R315

DAT_SM2<32>
CLK_SM2<32>

C C

DAT_SM2
CLK_SM2

4.7K_0402_5%~D

C356

10P_0402_50V8J~D

12

12

R316

4.7K_0402_5%~D

1

C357

2

10P_0402_50V8J~D

BLM11A601S_0603~D

1 2
1 2

BLM11A601S_0603~D

1

2

L47

L48

1

C359

C358

2

10P_0402_50V8J~D

10P_0402_50V8J~D

TP_DATA
TP_CLK

1

2

KSO_17<31>
M_LED_A<32>
M_LED_B<32>
M_LED_C<32>

KSO[0..15]<32>

KSI[0..7]<32>

LID_CL#<31>

+5VALW

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

LCM & Direct play SW & T PAD

JLCM

2

112

4

334

6

556

8

778

10

9910
11
13
151516
17
19

12

12

14

14

16
18

18

20

20

11
13

17
19

JST_BM20B-SRDS-G-TFC

TP_CLK
TP_DATA

C376

R5570_0402_5%~D

12

R5590_0402_5%~D

12

R5610_0402_5%~D

12

R5630_0402_5%~D

12

0.1U_0402_16V4Z~D

1

2

R558 0_0402_5%~D

1 2

R560 0_0402_5%~D

1 2

R562 0_0402_5%~D

1 2
1 2
1 2
1 2
1 2

C369

1

2

0.1U_0402_16V4Z~D

R568

1 2

0_1206_5%~D

FCS#<32>
FRD#<32>
FWR#<32>

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

R564 0_0402_5%~D
R565 0_0402_5%~D
R566 0_0402_5%~D
R567 0_0402_5%~D

SIO_FA[0..19]<32>

FCS#
FRD#
FWR#

+5VRUN

21
20
19
18
17
16
15
14

8
7

36

6
5
4
3
2

1
40
13
37

22
24

9

VCC
VCC
VPP

RP#/RESET#
WP#/RY/BY#

GND
GND

12

D0
D1
D2
D3
D4
D5
D6
D7

NC
NC

R495
0_0402_5%~D

31
30
11

25
26
27
28
32
33
34
35

10
12
29
38

23
39

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6

U32

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

CE#
OE#
WE#

MX29LV008BBTC-70_TSOP40~D

U27

1

NC

2
3
4

FWH_RST

VCC

A1

WP

A2

SCL

VSS

SDA

AT24C04N-10SI-2.7_SO8~D

SUB_6782U

SIO_FD0
SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7

R533

0_0402_5%~D

1

C590

0.1U_0402_16V4Z~D

2

8
7
6
5

EEPROM_WC
CLK_SMB
DAT_SMB

SMbus address A2

1

C361

C360

2

0.1U_0402_16V4Z~D

VCC1RST#

12

R302

FWH_RST

10K_0402_5%~D@

1 2

+3VALW

1

2

0.1U_0402_16V4Z~D

VCC1RST# <32>

EEPROM_WC <32>
CLK_SMB <13,32>
DAT_SMB <13,32>

SIO_FD[0..7] <32>

+3VALW

100P_0402_50V8J~D

1

2

JKYBD

25
24
23
22
21
20
19
18
17
16
15

30
29

14
13

28
27

12
11

26
10
9
8

31
7

32
6
5

33
4

34
3
2
1

JAE_FK2S030W11~D

KSI7
KSI6

B B

A A

KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16

KSO16<32>

KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

C946

100P_0402_50V8J~D

100P_0402_50V8J~D

C947

C948

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C949

1

2

100P_0402_50V8J~D

C951

C950

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C952

1

2

100P_0402_50V8J~D

C953

1

2

100P_0402_50V8J~D

C955

C954

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C957

C956

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C958

1

2

100P_0402_50V8J~D

C959

C960

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C961

C962

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C963

1

2

100P_0402_50V8J~D

C965

C964

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C966

1

2

100P_0402_50V8J~D

C967

C968

1

1

2

2

100P_0402_50V8J~D

100P_0402_50V8J~D

C366

C969

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

INT KB/LCM CONN./EEPROM

LA-2501

1

33 48Tuesday, October 05, 2004

1.0

of

5

Run Planes Enable

Q24

2

G

SUS_ON<31,35,40>

+15V

12

13

2

G

PWR_SRC

11
12

R347
100K_0402_5%~D

13

D

Q29
2N7002_SOT23~D

S

R314
100K_0402_5%~D

RUN_ENABLE

D

S

SUS_ON

1

C348

2

0.01U_0402_25V7K~D

ENAB_3VLAN <26>

12

R343
470K_0402_5%~D

+5VALW

D D

100K_0402_5%~D

RUN_ON_5V#

RUN_ON<16,31,35,40,41,44>

2N7002_SOT23~D

C C

B B

2

VAUX_EN<31>

G

A A

R310

2

G

Q23

PWR_SRC

12

R348
100K_0402_5%~D

N21917830

13

D

S

5

Q30

12

13

D

S

2N7002_SOT23~D

2N7002_SOT23~D

12

R344

200K_0402_5%~D

4

C408

+3VSRC

0.022U_0603_50V4Z~D

1

2

SI4810DY_SO8~D

8
7

5

+5VSUS

12

R332
10K_0402_5%~D

+1.5VSUS

8
7

5

Q18

1
2
36

4

Q52
SI3456DV-T1_TSOP6~D

D

6

S

45
2
1

G

3

Q55
SI4810DY_SO8~D

4

C321

4.7U_0805_10V4Z~D

C618

1
2
36

Note: Very close to Q55

PWR_SRC

12
11

2

G

R258
100K_0402_5%~D

13

D

Q15

S

4

R267

2N7002_SOT23~D

12

R262
200K_0402_5%~D

13

D

2

Q16

G

12

S

200K_0402_5%~D

2N7002_SOT23~D

1

2

4.7U_0805_10V4Z~D

+3VSRCPWR_SRC

R270

+3VRUN Source

+3VRUN

12

R277
10K_0402_5%~D

@

+5VRUN Source

+5VRUN

1

12

R522
10K_0402_5%~D

2

@

+1.5VRUN Source

0.1U_0402_16V4Z~D

C107

1

2

Q17

SI4810DY_SO8~D

8
7

5

4

12

1

C288

470K_0402_5%~D

2

0.1U_0402_16V4Z~D

3

+VCC_CORE

12

1

Z4005

2

13

RUN_ON_5V#

SUSPWROK_5V

+1.5VRUN

1

12

R384

C403

10K_0402_5%~D

2

@

4.7U_0805_10V4Z~D

+3VSUS
1
2

+3VSUS Source

36

1

C303

4.7U_0805_10V4Z~D

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

D

2

G

S

SUSPWROK_5V <40,41>

V_1P25V_DDR_VTT +3VRUN

R225

47_0805_5%~D@

Q14

2N7002_SOT23~D@

2

G

12

R89

100K_0402_5%~D@

SUSPWROK_5V#

13

D

Q48

2

2N7002_SOT23~D@

G

S

12
1

Z4006

2

13

D

S

2

R313

Q22

G

22_0805_5%~D@

2N7002_SOT23~D@

2

G

+1.5VSUS +2.5V_MEM+5VALW

12

R87

22_0805_5%~D@

Z4015

13

D

Q31

2N7002_SOT23~D@

S

2

12
1

R309

22_0805_5%~D@

Z4007

2

Q27

13

D

2N7002_SOT23~D@

2

S

G

12

R88

Z4018

13

D

2

G

S

+5VHDD Source

HDDC_EN#<31>

Q20
DTC144EKA_SOT23~D

+5VMOD Source

MODC_EN#<31>

DTC144EKA_SOT23~D

2

+1.5VRUN +VCCP +1.8VRUN

12
1

R308

22_0805_5%~D@

Z4009

22

Q26

13

D

2N7002_SOT23~D@

2

G

+15V

12

R287
100K_0402_5%~D

HDD_EN

13

+15V

12

R530
100K_0402_5%~D

2

13

S

C327

MOD_EN

C371

0.01U_0402_25V7K~D

2

G

+5VSUS

6

2

1

D

G

3

S

4 5

1

1

C315

2

2

0.01U_0402_25V7K~D

4.7U_1206_16V6K~D

+5VSUS

6

2

1

D

G

3

S

4 5
1

1

C620

2

2

4.7U_1206_16V6K~D

12
1

R307

Z4010

Q25

13

D

S

Q19

SI3456DV-T1_TSOP6~D

+5VHDD

Q28

SI3456DV-T1_TSOP6~D

+5VMOD

22_0805_5%~D@

Q34

12

1

Z4008

2

13

D

S

2N7002_SOT23~D@

R127

Q11

Q53

22_0805_5%~D@

2N7002_SOT23~D@

2

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

POWER CONTROL

LA-2501

1

47_0805_5%~D@

2N7002_SOT23~D@

12

R274

100K_0402_5%~D

12

R529
100K_0402_5%~D

1

2

G

+1.2VRUN

12
1

Z4011

2

13

D

S

R715
22_0805_5%~D@

Q61

2N7002_SOT23~D@

34 48Tuesday, October 05, 2004

1.0

of

5

U29B
74VHC08MTC_TSSOP14~D

+3VSUS

4

IN1

OUT

5

IN2

+3VSUS

14

U30A

1

P

IN1

OUT

2

IN2

G

74VHC08MTC_TSSOP14~D

7

ICH_PWRGD# <13>

6

3

10K_0402_5%~D

0.1U_0402_16V4Z~D

+3VSUS
4

IN1

5

IN2

OUT

+1.5VSUS

R482

C584

12

R550
100K_0402_5%~D

ICH_PWRGD#

13

D

Q60
2N7002_SOT23~D

S

IMVP_PWRGD

RUNPWROK

+3VRUN

IMVP_PWRGD<20,42>

ITP_DBRESET#<7>

D D

RESET_OUT#<32>

+3VSUS +3VALW

ICH_PWRGD

C C

2

G

4

U30B

6

74VHC08MTC_TSSOP14~D

13

IN1

12

IN2

12

12

1

2

R490

1

C

2

B

E

3

U30D

11

OUT

74VHC08MTC_TSSOP14~D

100K_0402_5%~D

Q50
MMBT3904_SOT23~D

ICH_PWRGD <20>

+3VSUS

8

U26C

P

A3Y

G

SN74LVC3G14DCTR_SSOP8~D

4

3

+3VRUN

12

R492
100K_0402_5%~D

5VRUNRC

1

C591

0.01U_0402_16V7K~D

2

1P8V_PWRGD<44>

5

1.5VSUS_PWRGD

+3VSUS

C589

0.1U_0402_16V4Z~D

1 2

8

U26A

P

7

A1Y

G

SN74LVC3G14DCTR_SSOP8~D

4

U30C

10

IN1

RUN_ON<16,31,34,40,41,44>

9

IN2

74VHC08MTC_TSSOP14~D

0_0402_5%~D

1 2

R293

OUT

+3VSUS

A6Y

8

SUS_ON<31,34,40>

2

8

U26B

P

2

G

SN74LVC3G14DCTR_SSOP8~D

4

R292

0_0402_5%~D@

1 2

1.5VSUS_PWRGD
SUS_ON

+3VSUS

C585

0.1U_0402_16V4Z~D

1 2

U29A

14

74VHC08MTC_TSSOP14~D

1

P

IN1

3

OUT

2

IN2

G

7

U29C

+3VSUS

10

IN1

8

OUT

9

IN2

74VHC08MTC_TSSOP14~D

+3VSUS

U29D
74VHC08MTC_TSSOP14~D

13

IN1

11

OUT

12

IN2

RUNPWROK

1

RUNPWROK <16,32,39,42,44>

SUSPWROK <13,20>

47K

Q3

10K

DTA114YKA_SC59~D

1 3

R_CAP

R_NUM

R_SRL

150_0402_5%~D

150_0402_5%~D

R13

150_0402_5%~D

12

R14

150_0402_5%~D

12

R15

150_0402_5%~D

12

R16

12

R17

BAT2_LED

12

4

CAP_LED

NUM_LED

SRL_LED

IN

PIDEACT#<19>

OUT

GND

1

DTA114YKA

32

CAP_LED#<32>

NUM_LED#<32>

B B

SRL_LED#<32>

BAT1_LED#<32>

A A

BAT2_LED#<32>

2

2

2

47K

10K

1 3

+5VALW

2

47K

10K

1 3

5

2

47K

Q4
DTA114YKA_SC59~D

10K

1 3

Q5
DTA114YKA_SC59~D

47K

Q6
DTA114YKA_SC59~D

10K

1 3

R_BAT1_LED BAT1_LED

Q1
DTA114YKA_SC59~D

R_BAT2_LED

+3VRUN

47K

Q2

2

BT_ACTIVE<24>

DTA114YKA_SC59~D

10K

R18

1 3

R_PIDEACT ACTLED

BREATH_LED<32>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

150_0402_5%~D

12

R373

10K_0402_5%~D

1 2

10K_0402_5%~D

BT_ACTIVE BT_MPCI_ACTIVE

1 2

3

BREATH_LED_B

R370

2

B

2

B

+3VALW

Z3901

E

E

R371
150_0402_5%~D

1 2

1

C

Q33
MMBT3904_SOT23~D

3

R_BREATH_LED

R_BT_MPCI_ACT

1

C

Q32
MMBT3904_SOT23~D

3

R_BT_MPCI_ACT
BAT2_LED
BAT1_LED

RJ_TIP
RJ_RING

R_BREATH_LED
ACTLED
CAP_LED
NUM_LED
SRL_LED
LED_WLAN_OUT
POWER_SW#
+5VALW_R

@

300P_1808_3000V8K~D

1

C970

C971

2

@

300P_1808_3000V8K~D

1

2

+5VALW

LED_WLAN_OUT<30>

JWIRE

1

RJ_RING

2

ACES_85204-0200

POWER_SW#<13,32>

1 2

1K_0402_5%~D

RJ_TIP

R375

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Power sequence/LED/RJ11

LA-2501

14

JLED

12

12

14

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

13

13

MOLEX_53398-1290~D

JPHON

1

1

2

2

3

GND1

4

GND2

SUYIN_100002FR006G202ZL~D

1

35 48Tuesday, October 05, 2004

1.0

of

5

CLP4

D D

CLP13

C C

SMD40M80@

1

GND

EMI_CLIP~D@

1

GND

EMI_CLIP~D@

FD2

1

SMD40M80@

FD10

1

FD11

1

SMD40M80@

CLP10

1

GND

EMI_CLIP~D@

CLP11

1

GND

EMI_CLIP~D@

HEX_STANDOFF~D

STAND1

1

Fiducial Mark

FD3

1

SMD40M80@

FD17

1

SMD40M80@

FD4

1

SMD40M80@

FD18

1

SMD40M80@

FD5

1

SMD40M80@

FD12

1

FIDUCAL@

FD6

1

SMD40M80@

FD13

1

FIDUCAL@

4

HEX STANDOFF

STAND2

1

HEX_STANDOFF~D

FD7

1

SMD40M80@

FD14

1

FIDUCAL@

3

PCB

2

1

BARE PCB

1

NC

STAND3

1

HEX_STANDOFF~D

FD8

1

SMD40M80@

FD15

1

FIDUCAL@

FD9

1

SMD40M80@

FD16

1

FIDUCAL@

STAND4

1

HEX_STANDOFF~D

FD21

1

FIDUCAL@

DAQ20_LA-2501 _REV1 _M/B~D

MY1

MYLAR(ZZZ)

1

NC

MYLAR_DIMMA~D

MY2

MYLAR(ZZZ)

1

NC

MYLAR_DIMMB~D

MY3

MYLAR(ZZZ)

1

NC

MYLAR_MINIPCI~D

MY4

MYLAR(ZZZ)

1

NC

SD_MINIPCI~D

ZZZ1

LOG LOW SUPPORT
MYLAR(ZZZ)

1

NC

LOG_LOW_MYLAR~D

ZZZ2

LOG LOW
GASKET(ZZZ)

1

NC

LOG_LOW_GASKET~D

ZZZ3

IO BRACKET(ZZZ)

1

NC

IO_BRACKET~D

ZZZ4

CONDUCTIVE
TAPE(ZZZ)

1

NC

CONDUCTIVE_TAPE~D

ZZZ5

RJ11_RUBBER (ZZZ)

1

NC

RJ11_RUBBER~D

ZZZ6

SD_RUBBER (ZZZ)

1

NC

SD_RUBBER~D

B B

H2
C315D126@

1

H14
C276D110

1

H15
C354T130BD110

A A

1

H11
C315D110

1

H4

H3

C315D126@

C276D126@

1

1

H17

H16

C315D102

C315D110@

1

1

H20
C276T103BD83

1

H33
O59X67D59X67N@

1

5

H6

H5
C276D126@

1

H19
C354T315BD110@

1

H26
C276D110

1

H7

C315D126@

C295T276BD110@

1

1

H21
C276D110

1

H27

H28

C276D110

C276D110@

1

1

H8
C315D126@

1

H23

H22

C315D91@

C315D91@

1

1

H29
C354T276BD126@

1

4

H10

H9
C315D126@

1

H24
C315D91@

1

H32
C276D110@

1

H12

C315D126@

C276D146

1

1

H25
C315D91@

1

H30

H31

C134D134N@

O236X134D236X134N@

1

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

EMI CLIP/STANDOFF

LA-2501

36 48Tuesday, October 05, 2004

1

1.0

of

5

4

3

2

1

+5VALW

+3VALW PWR_SRC

D D

PQ12

BSS138_SOT23~D

PS_ID

PR68

PR62

C C

Z-series AC Adaptor
Connctor

B B

9
8

7
6

D

1 3

1 2

100K_0402_1%~D

2

B

1 2

15K_0402_1%~D

PJDC1
FOX_JPD113D-506-TR~D

Low_PWR

GND_4

DC+_1

GND_3

DC+_2

DC-_1

GND_2

DC-_2

GND_1

MH1

MH2

S

G

2

C

E

PQ10

3 1

MMBT3904_SOT23~D

1
2
3
4
5

DCIN+

+5VALW

1 2

PR69
100K_0402_5%~D

@

PR75
0_0402_5%~D

1 2

PD9
DA204U_SOT323~D

PL15

FBMA-L11-160808-601LMT_0603~D

PL2

FBM-L18-453215-900LMA90T_1812~D

1 2

3

1

PS_ID_DISABLE# <32>

12

2

PR78

1 2

2.2K_0402_5%~D

NB_PSID <32>

DC_IN+ Source

PS_IDPWR_ID

PC3

1 2

0.47U_1812_50V7M~D

DC_IN

12

PR16

150K_0402_5%~D

1
2
3 6

PQ_G

PR11

100K_0402_5%~D

4

12

PQ1 SI4825DY_SO8~D

8
7

5

PD8

2 1

EC10QS04_SOD106~D

12

PC45

PC48

0.01U_0402_25V7K~D

1 2

PR57

0_0402_5%~D

12

PC34

0.1U_0805_50V7M~D

+DC_IN

12

12

PC1

10U_1210_25V7K~D

0.1U_0805_50V7M~D

+3.3VRTC Source

RTC_SHDN#

MAX1615EUK_SOT23-5~D

+3.3VX

PU2

1

IN

3

OUT

5

#SHDN

4

5/3+

GND

2

PC33

12

10U_1206_6.3V7K~D

THE POINT

NOTE: "THE POINT LOCATED
AT PS MODULE

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+DCIN

LA-2501

1

37 48Tuesday, October 05, 2004

0.1

of

5

D D

+3VALW

4

3

2

1

ESD Diodes

2

3

Primary Battery Connector

PJBAT

C C

12

PC40

2200P_0402_50V7K~D

BATT_PRES#

BATT_VOLT

10

GND

11

GND

SUYIN_200028MR009502ZL~D

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD19

DA204U_SOT323~D@

PR164

100_0402_5%~D

1 2

1

PR161

100_0402_5%~D

1 2

2

3

PD20

1

DA204U_SOT323~D@

PR155

100_0402_5%~D

1 2

3

PD17
DA204U_SOT323~D@

100_0402_5%~D

2

1

PR162

1 2

2

3

PD21

1

DA204U_SOT323~D@

PBATT+

PBAT_SMBCLK <32,43>
PBAT_SMBDAT <32,43>

PBAT_ALARM# <32>

EMI team suggest

PL13

FBM-L18-453215-900LMA90T_1812~D

1 2

1 2

PC41

0.1U_0805_50V7M~D

+VCHGR

+3VALW

PR156

10K_0402_5%~D

12

PBAT_PRES# <32>

9

8

7

6

5

4

3

2

1

SUYIN_20175A-09G1
TOP view

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Battery Conn./+2.5V

LA-2501

38 48Tuesday, October 05, 2004

1

0.1

of

A

B

C

D

+1.5VSUSP / +VCCP_1P05VP

PL14

1 1

FBM-L11-322513-151LMAT_1210~D

1 2

PWR_SRC

1

PC8

PC53

2

10U_1206_25V6M~D

Design current 3A for +1.5VSUSP

2 2

+1.5VSUSP

1

PD5

EP10QY03~D

@

3 3

+

PC12

2

2 1

220U_D_2.5VM~D

T84

PAD

+1.5VSUSP

+VCCP

12

PC73

0.1U_0805_25V7K~D

PR107

0_0603_5%~D@

1 2

PJP1

1 2

PAD-OPEN 4x4m
PJP2

1 2

PAD-OPEN 4x4m

3U_SPC-07040-3R0_5A_30%~D

12

PR108

10K_0402_1%~D

12

PR109

20K_0402_1%~D

1 2

12

PR104

0_0402_5%~D

12

PC70

1000P_0402_50V7K~D

@

+1.5VSUS

+VCCP_1P05VP

PL5

VCCP_PWRGD<42>

SUSPWROK_2P5V<41>

1 2

0.1U_0603_25V7K~D

SI4814DY_SO8~D

8
7
6
5

RUNPWROK<16,32,35,42,44>

PC9

PQ2

G1
S1/D2
S1/D2
S1/D2

12

2200P_0402_50V7K~D

+3VSUS

PR91

D1
D1
G2
S2

100K_0402_5%~D

SUSPWROK_2P5V

1
2
3
4

PR101

0_0402_5%~D

12

PD11

12

PC129

1000P_0402_50V7K~D

PC68

0.1U_0805_50V7M~D

2 1

RB751V-40_SOD323~D

12

12

PR100
0_0603_5%~D

PR24

1 2

0_0603_5%~D

1.5V_DL

1.5V_OUT

1.5V_FB

VCCP_PWRGD

MAX1845_VCC

+5VSUS

21

PD13

RB751V-40_SOD323~D

1.5V_BST2

1.5V_V+ 1.05V_BST

1.5V_BST

12

1.5V_DH

1.5V_LX

12

PR185

33K_0402_1%

12

PR188

11K_0402_1%~D

13

D

S

PQ34
2N7002_SOT23~D

PR92

20_0603_1%~D

1 2

12

PC65

4
19
18
17
16
20
15
14

7
11
12

6

8

9

2

G

1U_0603_10V6K~D

PU4

V+
BST2
DH2
LX2
CS2
DL2
OUT2
FB2
PGOOD
ON1
ON2
SKIP
OVP
UVP

MAX1845_VCC

22

VCC

GND

23

RUNPWROK <16,32,35,42,44>

PC67

1 2

4.7U_0805_6.3V6K~D

21

25

VDD

BST1

26

DH1

27

LX1

28

CS1

24

DL1

1

OUT1

2

FB1

10

REF

5

TON

3

ILIM1

13

ILIM2

MAX1845EEI_QSOP28~D

1.05V_DH

1.05V_LX

1.05V_DL

1.05V_OUT

1.05V_FB

MAX1845_REF

12

PC66

1U_0603_10V6K~D

PR86
0_0603_5%~D

1 2

PR94

0_0402_5%~D

@

1 2

PD10

RB751V-40_SOD323~D

PR80

1 2

0_0603_5%~D

12

PR90

150K_0402_1%~D

12

PR89

90.9K_0402_1%~D

1

10U_1206_25V6M~D

1

PC50

2

2

10U_1206_25V6M~D

12

PR97

1K_0402_1%~D

PR87

0_0603_5%~D@

1 2

12

PR96

20K_0402_1%~D

12

12

PC7

PC49

2200P_0402_50V7K~D

21

578

PQ15

12

PC52

1.05V_BST2

12

PR98

90.9K_0402_1%~D

12

PR99

280K_0402_1%~D

0.1U_0805_50V7M~D

IRF7811AV_SO8~D

3 6

578

3 6

241

241

PL4

1.8U +-30% DC104C-919AS-1R8N 9.5A~D

1 2

PQ16
FDS6676S_SO8~D

PC51

0.1U_0603_25V7K~D

Design current 5A for +VCCP_1P05VPPeak current 4.034A for +1.5VSUSP

Peak current 7.124A for +VCCP_1P05VP

+VCCP_1P05VP

1

1

12

PC11

PC69

0.1U_0805_25V7K~D

@

T83
PAD

330U_D2E_2.5VM~D

+

+

PC10

PD12

2

2

330U_D2E_2.5VM~D

EP10QY03~D

2 1

@

4 4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.5VSUSP /+VCCP_1P05VP

LA-2501

D

39 48Tuesday, October 05, 2004

0.1

of

5

4

3

2

1

DC/DC +3V/ +5V/ +15V

PL20

FBM-L11-322513-151LMAT_1210~D

PWR_SRC

D D

Design current 3.4A for +3.3VSRC
Peak current 4.758A for +3VSRCP

+3VSRCP

1

12

+

PC119

PC39

2

C C

B B

A A

330U_D3L_6.3VM_R25~D

PAD

+15VP

+5VSUSP

+3VSRCP

0.1U_0805_50V7M~D

T86

1 2

1 2

1 2

0_0603_5%~D@

1 2

PJP13

PAD-OPEN 4x4m

PJP8

PAD-OPEN 4x4m
PJP9

PAD-OPEN 4x4m

PR54

PR145

1 2

0_0402_5%~D

@

PR144

1 2

0_0402_5%~D

(150mA,Via NO.= 2)

+15V

(6A,240mils ,Via NO.= 12)

+5VSUS

(4A,160mils ,Via NO.= 8)

+3VSRC

1 2

Place these CAPs
close to FETs

10U_SPC-1204P-100_4.5A_20%~D

PL10

1 2

SUS_ON<31,34,35>

SUS_ON

PC98

1

2

10U_1206_25V6M~D

PC99

1

PC97

2

10U_1206_25V6M~D

12

12

PC106

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PQ29
SI4814DY_SO8~D

8

G1

D1

7

D1

S1/D2

6

G2

S1/D2

5

S1/D2

S2

SUS_ON<31,34,35>

ALWON<32>

THERM_STP#<13>

PR121

PR172

VCC_MAX1999

1 2

12

PC95

PC93

4.7U_1206_25V6K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

PR60

1 2

240K_0402_5%~D

PC29

0_0603_5%~D

FB3

PR61

2K_0402_1%~D

1 2

1
2
3
4

10_1206_5%~D

12

12

12

PR124

PC38

1000P_0402_50V7K~D

@

PR147

1K_0402_5%~D

1 2

1 2

10_1206_5%~D

PR49
0_0603_5%~D

1 2

12

+5VSUSP

22U_1206_6.3VAM~D

PC91

PC94

DH3
LX3
DL3

1U_0603_10V6K~D

BST3

10U_1206_6.3V7K~D

47_0603_5%~D

12

12

PC90

20
17

6
28
26
27
24
22

7

3

4
25

PR48

12

1

PD7

2

RB717F_SOT323~D

PU6

V+
VCC
SHDN
BST3
DH3
LX3
DL3
OUT3
FB3
ON3

ON5
LDO3

SKIP

MAX1999EEI_QSOP28~D

12

+3VALW

MAX1999_SKIP#

0_0402_5%~D

0_0402_5%~D@

12

PR137

Adding SKIP control

0_0402_5%~D

@

12

PR125

+5VALW

12

12

PC28

PC26

1U_0603_10V6K~D

BST_5BST_3

PR56

18

0_0603_5%~D

BST5

14

1 2

DH5

16

LX5

15

DL5

19
21

1

FB5

9

PRO#

10

ILIM5

11

ILIM3

5

REF

8

TON

13
23
2

12

12

RUN_ON <16,31,34,35,41,44>

PC116

0.1U_0603_25V7K~D

4.7U_1206_25V6K~D

1 2

PR126

0_0603_5%~D

12

PC120

1U_0805_10V7K~D

VCC_MAX1999

PR157

1 2

150_0603_1%~D

PC31

0.1U_0603_25V7K~D

1 2

+3VSRCP

PR140

1 2

100K_0402_5%~D

1000P_0603_50V8J~D@

30.9K_0402_1%~D

1 2

PU8

1
2
3
4

MB3800PNF_SOL-8~D

3

LDO5

BST5

DH5
LX5
DL5

OUT5

N.C.
FB5

PRO

ILIM5
ILIM3

REF
TON
GND

PGOOD

PR136

PR138

12

1 2

1.07K_0402_1%~D

PC96

PR122

-IN
SCP
VCC
BR/CTL

12

Place these CAPs
close to FETs

PC107

0.1U_0805_50V7M~D

578

3 6

241

578

3 6

241

SUSPWROK_5V <34,41>

ILIM5
ILIM3
PRO#
TON

22U_SPC_06704_22R0_1.5A_30%~D

8

FB

7

OSC

6

GND

5

OUT

12

12

PC113

2200P_0402_50V7K~D

PQ32
SI4800DY-T1_SO8~D

5.6U_CEP125-5R6MC_8.8A_20%~D

PQ27
SI4810DY_SO8~D

PR142

57.6K_0402_1%~D

PR148

147K_0402_1%~D

PL11

12

12

PR135

PC111

1 2

270P_0402_50V7K~D

Design current 4A for +5VSUS

PL9

12

REF

PR141

1 2

1 2

1 2

30.1K_0402_1%~D

PR146

1 2

147K_0402_1%~D

Peak current 5.7A for +5VSUSP

+5VSUSP

1

12

PC121

0.1U_0805_50V7M~D

PR55
0_0603_5%~D@

1 2

+

PC27

2

330U_D3L_6.3VM_R25~D

T85
PAD

1 2

1 2

VCC_MAX1999

PR58

0_0402_5%~D

1 2

@

PR59

1 2

0_0402_5%~D

PR120

@

PR123

0_0402_5%~D

0_0402_5%~D

PR143

PR149

@

0_0402_5%~D

1 2

1 2

0_0402_5%~D

Note: check the power consumption of +15V plane

+15VP

PD15

2 1

SKUL30-02AT_SMA

6

2

1

D

PQ30

G

S

4 5

SI3442DV_TSOP6~D

PC92

1

1

+

2

2

PC128

10U_1206_25V6M~D

15U_D2_25M_R90~D

3

12

PC110

3.92K_0402_1%~D

0.1U_0603_25V7K~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+3.3V/+5V/+15V

LA-2501

1

40 48Tuesday, October 05, 2004

0.1

of

5

4

3

2

1

+2.5V/ V_1P25V_DDR_VTT

DDR1 Termination

+5VSUS

PC22

1 2

4.7U_0805_6.3V6K~D

PU5

20

BST

18

DH

19

LX

21

DL

23

PGND1

16

VOUT

15

FB

1

TON

3

REF

+5VSUS

PR35

1 2

10_0402_5%~D

AVDD

12

0_0402_5%~D

PC19

26

AVDD

SHDNA

PGND2

SS

8

1 2

REFIN

12

PC18

1U_0603_10V6K~D

17

VIN

5

POK1

6

POK2

27

7

STBY

13

VTTI

14

11

12

VTT

9

VTTS

10

VTTR

MAX8550ETI_TQFN28~D

1000P_0402_50V7K~D

2.5V_1.25V_PWR_SRC

PR45 0_0402_5%~D

PC80

PR169

SUSPWROK_5V

@

TP0

28

2

22

VDD

SHDNB

OVP/ UVP

SKIP

GND

ILIM

4

25

24

1 2

1U_0603_10V6K~D

PR46

12

PR40

20_0603_1%~D

1 2

PC82

0.1U_0603_25V7K~D

1 2

1 2

470K_0402_5%~D

+1.25V_PWRGD

PC87

0.1U_0603_25V7K~D

12

PR34

1 2

470K_0402_5%~D

SUSPWROK_5V <34,40>

12

PC75

10U_1206_6.3V7K~D

1

+

PC17

PC86

2

150U _D2_6.3VM~D

@

SUSPWROK_2P5V <39>

+2.5V_MEM

1

PC20

2

22U_1206_6.3VAM~D

22U_1206_6.3VAM~D

V_DDR_MCH_REF <11,14,15>

1

2

PC21

22U_1206_6.3VAM~D

TP0

2N7002_SOT23~D

1

2

12

PR170

+5VSUS

PR37

100K_0402_5%~D

D

PQ23

S

V_1P25V_DDR_VTTP

PR171

1 2

0_0402_5%~D

0_0402_5%~D

@

1 2

PR168 0_0402_5%~D@

12

13

2

G

Design current 1.05A for V_1P25V_DDR_VTTP
Peak current 1.5A for V_1P25V_DDR_VTTP

SUSPWROK_5V <34,40>

RUN_ON <16,31,34,35,40,44>

PC78

12

0.1U_0805_50V7M~D

2.5V_1.25V_PWR_SRC

12

PC81

2200P_0402_50V7K~D

PQ24

FDS6676S_SO8~D

3 6

241

3 6

241

578

PQ25
IRF7811AV_SO8~D

578

PC83

0.1U_0603_25V7K~D

PC74

0.22U_0603_16V7K~D

PD14

RB751V-40_SOD323~D

12

21

PR113
0_0603_5%~D

1 2

2.5V_DH

2.5V_LX

2.5V_DL

2.5V_FB

PR36 0_0402_5%~D

2.5V_REF

PR41

12

51.1K_0402_1%~D

PR38

150K_0402_1%~D

12

1 2

12

D D

PWR_SRC

PL17

FBM-L11-322513-151LMAT_1210~D

12

2.5V_1.25V_PWR_SRC

1

PC79

2

10U_1206_25V6M~D

PC76

1

2

10U_1206_25V6M~D

Design current 10.6A for +2.5V_SUSP

+2.5VSUSP

C C

1

1

PC23

12

+

PC25

2

0.1U_0603_25V7K~D

220U_D2_4VM~D

T87

PAD

0_0603_5%~D@

1 2

PR117

PR116

PR118

12

45.3K_0603_1%~D

12

17.4K_0402_1%~D

+

PC24

2

220U_D2_4VM~D

B B

PL8

1.4UH_CEP125U-1R4_15.5A_20%~D

1 2

IC Populate No Populate

PJP6

PAD-OPEN 4x4m

1 2

PJP7

PAD-OPEN 4x4m

+2.5VSUSP

A A

V_1P25V_DDR_VTTP

1 2

PJP12

1 2

PAD-OPEN 4x4m

+2.5V_MEM

(8A,320mils ,Via NO.=16)

V_1P25V_DDR_VTT

(3A,200mils ,Via NO.=6)

MAX8550

MAX8550A

PR37,PQ23,PR171 PR168,PR170,PR169

PR168,PR170

PR37,PQ23,PR169,
PR171

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+2.5VSUSP/V_1P25V_DDR_VTTP

LA-2501

1

41 48Tuesday, October 05, 2004

0.1

of

8

7

6

5

4

3

2

1

VID 5

0

H H

10
1

G G

MAX1987_VCC

F F

PR186

0_0402_5%~D@

PR71

0_0402_5%~D

E E

PR187

0_0402_5%~D@

D D

C C

PBOOT voltage seeting up on 1.212V

B B

V I D

VID 4

VID 3

1

11101

1

1

1

The C4 Mode voltage
is 0.748V, S2 open

1 2

1 2

12

1 2

PR17

0_0402_5%~D

12

PR18

0_0402_5%~D@

12

PR15

0_0402_5%~D@

12

PR13

0_0402_5%~D

PR79

0_0402_5%~D

@

VID 2

1

0

1

1

PR8
0_0402_5%~D

MAX1987_VCC

12

PR14

0_0402_5%~D

12

PR74

0_0402_5%~D

@

DPRSLPVR<7,20>

CLK_ENABLE#<6>

CLK_ENABLE#<6>

12

12

VID 1

1 2

PR12

@

PR72

@

0

1

0

0_0402_5%~D

0_0402_5%~D

PR9
0_0402_5%~D@

12

12

+3VRUN

+3VRUN

VID 0

0_0402_5%~D@

0
1

1

00

Vcore

1.484

1.308

0.956

0.748

PR26

0_0402_5%~D@

PR25

PR27

100K_0402_1%~D@

1 2

V

VCCP_PWRGD<39>

IMVP_PWRGD<20,35>
CLK_ENABLE#<6>

H_PSI#<8>

H_STP_CPU#<6,20>

12

PC42

270P_0402_50V7K~D

PR22

100K_0402_1%~D@

1 2

12

12

PR23

100K_0402_1%~D@

1 2

DPRSLPVR<7,20>

PC2

0.22U_0603_16V7K~D

12

PR66

PR64

10K_0402_5%~D

@

VID5<8>
VID4<8>
VID3<8>
VID2<8>
VID1<8>
VID0<8>

PR1 0_0402_5%~D@

PR83 0_0402_5%~D

PR84 0_0402_5%~D

RUNPWROK<16,32,35,39,44>

12

12

PR3

100K_0402_1%~D

12

PC47

PR7

20.5K_0402_1%~D

100P_0402_50V8K~D

13

D

PQ8

2

G

S

13

D

PQ18

2

G

S

+3VRUN

12

PR65

10K_0402_1%~D

1.91K_0603_1%~D

12

0_0402_5%~D@

12

12

PR4 0_0402_5%~D

MAX1987_REFMAX1987_REF

12

PR20

15K_0402_1%~D

@

2

G

2N7002_SOT23~D@

2N7002_SOT23~D@

PR85

12

13

12

VID5
VID4
VID3
VID2
VID1
VID0

D

S

2

G

12

12

12

12

PR19

36K_0402_5%

@

PQ7

2N7002_SOT23~D@

13

D

S

+5VRUN

12

PR63

10_0805_5%~D

MAX1987_VCC

12

PC44

PR88
10K_0402_1%~D

22
23
24
25

26
27
28
29
30

8
7
6

5
4
3

21
44
43

9

14

10

11

2

1

12

PR82

30.1K_0402_1%~D

PQ17

2N7002_SOT23~D@

1U_0603_10V6K~D

PU3

SYSOK
IMVPOK
CLKEN#
D5

D4
D3
D2
D1
D0

S2
S1
S0

B2
B1
B0

PSI#
DPSLP#
SUS
SHDN#

CCV

REF

ILIM

TON

TIME

12

VCC

POS15NEG

+5VRUN

36

VDD

BSTM

DHM

LXM
DLM

CMP

CMN

CSP
CSN

OAIN+

OAIN-

CCI

DHS

LXS

DLS

BSTS

PGND

GND

DD0#

MAX1987ETM_TQFN48~D

16

12

PR5

1.24K_0603_1%~D

12

PR6

100K_0402_1%~D

42

V+

32
34
33
35

45
46

Remote Vcore sense

48
47

20

19

17

18

FB

39
40
38
41

37
13
31

PC5

PC43

470P_0402_50V7K~D

1 2

PR2

1M_0402_1%~D

1 2

12

10U_1206_6.3V7K~D

CPU_PWR_SRC

PR110

2.55K_0402_1%~D

12

21

PR10

2.2_0603_5%~D

1 2

1 2

12

+VCC_CORE

PR67

2.55K_0402_1%~D

RB751V-40_SOD323~D

PD1
RB751V-40_SOD323~D

PR93

0_0603_5%~D

1 2

PR102

1K_0402_1%~D

1 2

PR106

1K_0402_1%~D

1 2

PR103

1K_0402_1%~D

1 2

PR105

1K_0402_1%~D

PR21

2.2_0603_5%~D

CPU_PWR_SRC

12

PC60

0.1U_0603_25V7K~D

0.6UH_C-PI-1250-0R6_26A_30%~D

PD3

2 1

EC31QS04~D

@

12

12

PC61

PC64

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

0.6UH_C-PI-1250-0R6_26A_30%~D

PC55

PQ20

5

PQ21

D8D7D6D

IRF7821_SO8~D

S1S3G

S

4

2

5

PQ6

D8D7D6D

IRF7832_SO8~D

S1S3G

S

4

2

5

D8D7D6D

S1S3G

S

4

2

5

PQ3

D8D7D6D

IRF7832_SO8~D

S1S3G

S

4

2

5

PQ22

IRF7821_S08~D@

12

PC4

0.1U_0603_25V7K~D

PC142

1 2

1500P_0402_50V7K~D

@

PQ19

PR95

0_0603_5%~D

1 2

12

12

PC6

0.1U_0603_25V7K~D

PD2

2 1

+5VRUN

IRF7821_S08~D @

PC143

1 2

1500P_0402_50V7K~D

@

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

PQ5
IRF7832_SO8~D @

S1S3G

S

4

2

5

IRF7821_SO8~D

D8D7D6D

S1S3G

S

4

2

5

PQ4

D8D7D6D

IRF7832_SO8~D@

S1S3G

S

4

2

1

12

PC56

PC63

2

2200P_0402_50V7K~D

10U_1210_25V7K~D

PL7

12

CPU_PWR_SRC

1

1

PC59

PC58

2

2

10U_1210_25V7K~D

10U_1210_25V7K~D

PL6

1 2

PD4

2 1

EC31QS04~D

@

1

1

PC54

PC57

2

2

10U_1210_25V7K~D

10U_1210_25V7K~D

Output Capatitors in H/W, ESR=3m ohms

PR28

0.001_2512_5%~D

1 2

1

2

10U_1210_25V7K~D

PL16

FBM-L18-453215-900LMA90T_1812~D

12

PR29

0.001_2512_5%~D

1 2

12

PC62

0.1U_0603_25V7K~D

+VCC_CORE

12

PC71

0.01U_0402_25V7K~D

+VCC_CORE

1

+

PC141
220U_25V_M~D

2

12

PC72

0.01U_0402_25V7K~D

PWR_SRC

Change PR82:30.1k. Delete PR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23
and PR19 for BANIAS and DOTHAN

PR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23 and PR19 are only for YONAH CPU.

A A

TRANSITION TIMING:
(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us
(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/us
(c): EXIT SUSPEND (SUS=LOW, RUNPWROK=HIGH): 24.7mV/us

8

7

6

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

2

Compal Electronics, Inc.

+VCORE

LA-2501

42 48Tuesday, October 05, 2004

of

1

0.1

5

4

3

2

1

+DC_IN discharge path

PQ14 SI4825DY_SO8~D

8

1 2

13

D

PQ11
2N7002_SOT23~D

S

PDS

PR51

150K_0603_1%~D

12

PR53

+VCHGR

PR151

1 2

59K_0402_1%~D

13

D

S

PR154

7
5

PR73

10K_0402_5%~D

12

PR77

0_0402_5%~D@

1 2

PC112

1 2

MAX1535_CCS
MAX1535_CCI
MAX1535_CCV
MAX1535_DAC
CHVREF

TM

PR153

10K_0402_1%~D

1 2

TH

PR152

1 2

10K_0402_1%~D

1U_1206_25V7K~D

+DC_IN

D D

1

PC46

2

10U_1210_25V7K~D

C C

12

12

PR134

0_0402_5%~D

PR133

0_0402_5%~D

12

12

PC105

B B

PC104

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

ACAV_IN<32>

Vin Detector
High 17.859 V
Low 16.988 V

12

PR132

10K_0402_5%~D

12

PC103

0.01U_0402_25V7K~D

12

12

PC109

PC114

1U_0805_10V7K~D

0.1U_0603_25V7K~D

13

D

2

G

PQ13

S

2N7002_SOT23~D

PR70

10K_0402_5%~D

2

G

PR52

20K_0603_1%~D

PC32

0.01U_0402_25V7K~D

1 2

681K_0402_1%~D

ACAV_IN

+5VALW

PC118

1 2

1U_0805_10V7K~D

Connect GND side of PC150, PC151, PC152 to GND through 1 via.

PQ33

2N7002_SOT23~D

PD18

CHG_PBATT<32>

2 1

RB751V-40_SOD323~D

2

G

1 2

100K_0402_5%~D

1 2

AC_IN

PC122

1500P_0402_50V7K~D

1
2
36

4

PR81

100K_0402_5%~D

1 2

PDS

PDL

1 2

Adress : 12H

12

PR139

CSSP

29

5

CSSP

GND

CSSN

PC123

28

DHIV

CSSN

LDO

DLOV

DHI

DLO

PGND

CSIP
CSIN

SCL
SDA

VMAX

GND18IMAX

MAX1535BETJ_TQFN32~D

10

PR128

1 2

47.5K_0402_1%

1 2

255K_0402_1%~D

2

PC117

1

0.1U_0603_25V7M~D

@

PU7

31

PDS

27

SRC

1

DCIN

3

ACIN

32

ACOK

6

CCS

7

CCI

8

CCV

11

DAC

4

REF

19

BATT

12

VDD

13

THM

16

INT

30

PDL

17

I.C.

0_0402_5%~D

1 2

0.1U_0603_25V7M~D

@

25

2

24

26
23

22

21
20

15
14
9

0.01_2512_1%~D

1 2

12

PC124

1U_0805_25V4Z~D

PR163

DLOV

0_0805_5%~D

PR130

PR76

PR127

DLO

CHVREF

12

PWR_SRC+SDC_IN

PR150

0_0402_5%~D

1 2

ACAV_IN

PZD1

12

RLZ4.3B_LL34~D

SI4835DY_SO8~D

10K_0402_1%~D

1 2

PC108

1U_0603_10V6K~D

1 2

PR160

PC126

0.1U_0603_25V7K~D

1 2

33_0402_5%~D

CSIP
CSIN

PR129

182K_0402_1%~D

12

105K_0402_1%

1 2

12

PBAT_SMBCLK <32,38>
PBAT_SMBDAT <32,38>

VMAX=2.595V
Maximum charger voltage=12.975V

IMAX=0.64V
Maximum charger current=3.2A

PL19

FBM-L18-453215-900LMA90T_1812~D

36

241

PQ28

578

578

PC115

3 6

241

1 2

1000P_0402_50V7K~D

@

CHVREF

12

PR131

12

Reserver H-side MOSFET

PQ26

36

241

SI4835DY_SO8~D@

578

MAX1535_LX

PQ31
FDS6670S_SO8~D

1 2

PL12

8.2U_CEP125-8R2MC_5.8A_20%~D

PD16

EC31QS04~D

@

2 1

PR159

0_0402_5%~D

1 2

1 2

PC127

PC125

0.1U_0603_25V7K~D

@

0.1U_0603_25V7K~D

@

PQ9 SI4825DY_SO8~D

1
2
3 6

1

1

PC101

2

2

10U_1210_25V7K~D

10U_1210_25V7K~D

@

+VCHGR

PC30

1

PC36

PC35

1 2

2

10U_1210_25V7K~D

10U_1210_25V7K~D

0.1U_0603_25V7K~D

PC102

1 2

0.1U_0805_50V7M~D

PR50

0.01_2512_1%~D

1 2

PR158

0_0402_5%~D

1 2

1

PC100

2

10U_1210_25V7K~D

12

PC88

PC89

2200P_0402_50V7K~D

CHG_CS

1 2

8
7

5

4

PDL

+5VSUS

21

PD22

1SS355_SOD323~D

@

PR167

1 2

100K_0402_1%~D

@

1

1

PC37

2

2

10U_1210_25V7K~D

@

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Charger

LA-2501

43 48Tuesday, October 05, 2004

1

0.1

of

5

4

3

2

1

D D

+3VSUS

+1.2VRUNP +1.2VRUN

+1.8VRUNP +1.8VRUN

C C

PJP14

1 2

PAD-OPEN 4x4m

PJP15

1 2

PAD-OPEN 4x4m

10U_1206_6.3V7K~D

RUN_ON<16,31,34,35,40,41>

RUNPWROK<16,32,35,39,42>

PR183

0_0603_5%~D@

PR184

0_0603_5%~D

PC131

12

12

PC138

PR177

75K_0603_5%

1U_0603_6.3V~D

+3VSUS

PR182

@

12

12

N18039114

12

10K_0603_5%

PU9

14

VIN

15

VIN

16

VIN

20

RT

17

VBIAS

19

FSEL

18

SS/ENA

1

AGND

3

NC

TPS54312PWP_PTSSOP-20~D

BOOT

VSENSE

PGND

PGND

PGND

PWRGD

N18039098

6

PH

7

PH

8

PH

9

PH

10

PH

5

2

11

12

13

4

PC135

12

0.1U_0805_25V7K~D

PL21

5U_TPR6D38-5R0M~D

1 2

+3VSUS

12

PR181
10K_0603_5%

+1.2VRUN/+1.8VRUN SOURCE

+1.2VRUNP

+3VSUS

12

12

+

PC132

PC133

0.1U_0603_16V~D

470U_D_4VM_R15~D

PR173

RUN_ON<16,31,34,35,40,41>

RUN_ON_D<31>

1 2

0_0402_5%~D

PR174

1 2

0_0402_5%~D@

12

PC134

10U_1206_6.3V7K~D

PR166

1 2

10K_0402_1%~D

PD23

RB751V-40_SOD323~D

PC136

1 2

0.1U_0603_25V7K~D

21

12

PC130

PU10

9

BATT

1

PWM

2

GND

3

REF

6

SHDN#

MAX1927REUB~D

0.1U_0402_10V6K~D

COMP
PGND

+3VSUS

10

POK

8

LX

4

FB

5
7

12

PR175

10K_0603_5%

PL22

4.7U_SLF7032T4R7M1R7-2_1.7A_20%

1 2

N17322286
N17322307

12

PR178

12

49.9K_0603_1%~D

PC140

1500P_0402_50V7K~D

PC139

12

1P8V_PWRGD <35>

PR176

69.8K _0603_1%

PR179

49.9K _0402_1%

22P_0603_50V8J~D

12

12

+1.8VRUNP

1 2

NC_1.8V_TEST

12

PC137

10U_1206_6.3V7K~D

PR180
0_0603_5%~D

@

T73

PAD

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

+1.2V/ +1.8V

LA-2501

1

44 48Tuesday, October 05, 2004

0.1

of

5

4

Gilbert Version Change List ( P. I. R. List )

3

2

1

Request

Item Issue DescriptionDate

D D

Page# Title

1

2

3

4

Owner

06 06/07/2004 Dell X00

10~12 ODEM 06/07/2004 Dell Change Alviso to ODEM-B All parts changed on thesae pages

Clock change CK410M to CK409 for supporting ODEM-B Change all parts on whole page

ICH4M18-21 All parts changed on thesae pagesChange ICH6M to ICH4MDell06/07/2004

Dell06/07/2004

ICH4M just support 6 USB ports

5

6

16 ODEM-B Chipset not support PCIe interface Change PCIe Graphics Interface to AGP4X Dell06/07/2004AGP/DVI CONN.

7

8

C C

9

10

11

12

13

33

AGP/DVI CONN.

TV Tuner

Dell06/14/2004

Dell06/14/200418

Dell06/14/200420,32

TV Out/CRT X00

Support LBK GraphicsDell16 06/10/2004

Gilbert not support TV tuner

Gilbert not support TV tuner Deleted R40.ICH4M

14

15

16

B B

17

Caps nopup as LBK+ and C541, C195, C222 populated as LKB+Dell06/15/2004AC97CODEC22

C894, C903, C934, C935 no pops on LKB+ schematic.Dell06/15/2004ICH4M21

18

19

13,16

Thermal / VGA
Connector

20

Change Sullivan to GilbertODEM-B Solution with Gilbert NameDell01 06/10/2004Cover
Change Sullivan Graphics Connector Type to LBK Graphics

Connector Type
Deleted JTUNR, JTV1, JTV2, R556, R555, R79, R98, C434, C433, C424,
C439, C610, L73, L75, L74, R102, R103, C431, C419, C420, C438, C442.

Added T88, T89..Gilbert not support TV tunerICH4M / SIO

Pop R4~R6, C8~C10.Signal Integrity reasons as Sullivan requirementsDell06/14/200417

Changed R421 from 30.1K to 51.1K.Per TT#92358, OTP seeting from 90C to 85CDell06/14/2004FAN/Guardian13

Pop R179 and C157Per Vsevolod to fix an EMI issue.Dell06/14/2004MINIPCI30
No pops C96, C101 Changed C541 to 2.2uF. C196, C197

to 1000pF. C195 to 0.1uF and C222 to 0.22uF.
No pops C903, C934, C935 as LBK+. But leave C894
populated for each pin of 5V_REF.

Deleted R210 and Added C2261uF cap attached between R210 and GNDDell06/15/2004AC97CODEC22

JVID PIN 158 Connected to Guardian Pin 8VGA Thermaltrip#Compal06/18/2004

No pop R327, R331.Do not need PU by Dell requirements.Dell06/18/2004SIO32

Solution Description Rev.

X00

X00

X00Delete USB1 port USB Ports25

X00Delete SATA Bridge for ICH4M not Support.ICH4M not support SATACDROM Dell06/07/200425

X00

X00ODEM-B Chipset not support DDR2 interface Change DDR2 interface to DDR1Dell14,15 06/07/2004DDR1 Socket

X00

X00

X00

X00

X00

X00

X00

X00

X00

X00

X00

X00

21

22

23

24

A A

25

31 SIO 06/23/2004 Dell X00GPIO70 is labeled on the schematics as an input, needs to be an output.

31,32 SIO 06/23/2004 Dell

Dell06/18/2004SIO31

Dell06/23/2004SIO31

GPIO73 (USB_SIDE_EN#) needs to be removed, and you should use
GPIO35 (USB_BACK_EN#) in it's place.

Laguna found current surge on coin cell due to
false power switch detected by SIO.
Increase number of 0.1uF capacitors so there is 1 for
each VCC1 and VCC2 input pin for Macallan.

Reconnect from pin2 to pin1 of R666.OC#5 wrong connectionCompal06/18/2004ICH4M19
Added T90 connected to GPIO73. Pin3 of U20 reconnect to

USB_BACK_EN#.
Change the off-page arrows of IDE_RST_HDD
to show that it is an output.
Add pop option to connect +RTC_CELL to U24 pin E2, VCC0. Added
R40. Nopop R501. Changed R504 pin 2 from +3.3VX to +RTC_CELL.

Added C7, C12, C79, C87, C88, C90

X00

X00

X00

X00

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Changed-List History 1

LA-2501

45 48Tuesday, October 05, 2004

1

1.0

of

5

4

Gilbert Version Change List ( P. I. R. List )

3

2

1

Request
Owner

26

D D

25 USB

27

28

29

30

31

32

33

34

C C

35

36

37

38

39

40

41

42

B B

43

44

35 LED Dell

33

8

8

Keyboard

Dothan(2/2)

Dothan(2/2)

06/25/2004

06/25/2004

06/30/2004

06/30/2004

06/30/2004

CompalLED35

Dell

Dell

Dell

Bluetooth LED is to bright.
Green LED controll by Macallan-III pin J9, amber LED

by Macallan-III pin J10.
KYBD connector c-paks were changed to discrete for cost savings.

Was needed for initial revision of CPUs but is no longer required.

Option for 1.8V is legacy for early version of CPU.

16 07/01/2004 Dell Removed T54. JVID pin 177 connect to G_PWR_SRC. X00By Bo's requirement.VGA connector

7 Dell

Dothan(1/2)

14 DDRI DIMMA

07/01/2004

07/01/2004

Dell

Per Intel feedback: DPRSLPVR from the ICH4-M should be
a No-Connect to CPU.
855PM Chipset Platform Design Guide recommends using 56ohm
resistors for the pull up.

07/01/2004 Compal X00Per Compal EMI guys requirement to fix MDC cable issue. Added C970, C971.35 RJ11

24 SUBWOOFER 07/05/2004 Compal Change supplier to follow Dell PSL. C646 change to SANYO 25CV220AX. X00

20,32 ICH4M,SIO 08/18/2004 Compal Change board ID to X01.

16 VGA connector

22, 25

AC97 CODEC
and CD-ROM

Thermal sensor

13

USB2.0 PORT

25 X01

08/20/2004 Dell Support instant CD play while powered on. Added C94, C96, C101, C353, C354. X01

08/20/2004

08/20/2004

08/23/2004 DellThermal sensor13

Dell

Compal

USB port 0 and port 1 swapped according to the schematic notes.
Need to use 3Vrun instead of VCCP for the BJT base voltage, since

thermtrip_VGA#" is a 3V rail

35 LED 08/26/2004 Dell X01R13~18 change value from 470 ohm to 150 ohm.LEDs intensity improvement.

Added PJP20~PJP23, R41, R42, R43, R46.
Nopop L36, L42, L9, L12, C278, C576, C19, C16.

Deleted PJP22, PJP23. Reconnect PJP20, PJP21 Jumper.Implementation for increasing the current capability of the USB ports.Dell06/24/2004USB25

R375 value changed from 100 to 1K ohm.
Pin 11 of JLED connected to BAT2_LED,

pin 10 of JLED connected to BAT1_LED.
Removed CN1~CN6, added C946~C969.
Pop C946~C969 and C366.

Removed B_VID1~6, RN1, R37, R38, R378~R383.

Removed PJP5.

Nopop R9.

R718,R719,R720,R723 change value from 10 to 56 ohm.

Pop R695,nopop R699.
Pop R318,nopop R319.

Update USB mapping table.The USB port 0 is on the Bottom of the
left side dual stack connector and port 1 is on the top.

Connect pin 1 of R37 from +VCCP to +3VRUN

Solution Description Rev.Page# TitleItem Issue DescriptionDate

X0006/23/2004 Dell Implementation for increasing the current capability of the USB ports.

X00

X00

X00

X00

X00

X00

X00

X00

X01

X01C518 change value from 1000P to 0.1uF.Slow down the G_PWR_SRC that avoid AC surge current when system onDell08/18/2004

X01Added R37, Q12 pop and R47 nopop.+3VRUN leakage issue from ATI M22

X01

45

46

47

48

49

A A

32 SIO 08/26/2004 Compal Gilbert BIOS use ICH4 GPIO34~37 as Board ID. Nopop R318, R506, R510, R312. X01

Amplifier and

23 09/02/2004 Dell

Phone Jack

SUBWOOFER 09/02/2004 Dell

24

Final HW EQ change requests for Gilbert/Sullivan by Doug.

Final HW EQ change requests for Gilbert/Sullivan by Doug.

Cost savings for making this change.And it is same as Sullivan.9 CPU Bypass 09/02/2004 Dell X01

20 ICH4M 09/24/2004 Compal Change board ID to A00.

C260, C563 change value from 0.047U to 0.015U. X01

C634 change value from 0.22U to 0.1U.
R539 change value from 1.21K to 16K.

X01

C415,C416,C85,C665 change value from 220U to 330U.
Nopop C207,C215,C525,C532,C85,C665.
Pop R699,nopop R695.
Pop R696,nopop R700.

A00

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Changed-List History 2

LA-2501

46 48Tuesday, October 05, 2004

1

1.0

of

5

4

Gilbert Version Change List ( P. I. R. List )

3

2

1

Request

Item Issue DescriptionDate

D D

Page# Title

50

51

Owner

16 09/24/2004 Dell A00

34

VGA connector Remove redundance parts as Issues list requirements.

POWER
Control

09/24/2004 Compal A00

Add a 0.1uf capacitor very near Q55 pins 1,2 and 3
to help attenuate high-frequency noise. Change Q55 from SI4800 to SI4810

Deleted L86,L87.
Nopop C658,C659.
Added C107.

52

53

C C

35 A00Nopop C970 and C971.Change the cap value to 300pf and 3KV like Sullivan/Folsom but NOPOP Dell10/01/2004RJ11

Solution Description Rev.

A00Added R38 and R48.Dell09/30/200416 VGA connector Need to put back pads for L86, L87 but use zero ohms instead for EMI.

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Changed-List History 3

LA-2501

47 48Tuesday, October 05, 2004

1

1.0

of

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Request
Owner

1

D D

2

3

4

5

6

7

8

9

C C

10

39 +VCCP_1P05VP has undershoot while system is powering down. +VCCP_1P05VP 2004/6/14 DELL

42 To improve EMI and save some cost after power and EMI team verified.+VCC_CORE 2004/6/14 Compal No populate PQ4,PQ5,PQ19,PQ22.

41 MAX8550 2004/6/23 No populate PR169 and populate PR171.Delete PR42.To fix some schematics error for open issue item 59 ~61.DELL

42 +VCC_CORE 2004/6/24 Compal To reduce nosie problem while CPU in C3/C4 mode. Add and reserve PC141 220U_25V X00

42 +VCC_CORE 2004/6/29 Compal Reserve un-pop resistor for tuning C4 mode voltage level. Add up-pop resistor PR186 and PR187. X00

41 +2.5VSUSP 2004/7/2 Compal To improve capacitor voltage derating. Change PC23,PC24 from 330U_2.5 to 220U_4V X00

42 +VCC_CORE 2004/7/5 DELL To improve shoot-through. Reservev PC142 and PC143 100P_0402_50V8K X00

39 MAX1845 2004/7/6 Compal

11

12

44 +1.2V/+1.8V 2004/9/27 DELL X01Change PR178 from 150K_0402_1% to 49.9K_0402_1%.To improve Phase Margin of +1.8VRUN.

2004/6/14 DELL MAX 8550 will trigger UVP function while powering down.41 MAX8550 Connect pin2 of MAX8550 to signal SUSPWORK.

Compal2004/6/14+1.8VRUN44

Modify power up sequence for reduce surge current of +1.5VSUSP.
That must fine tune +2.5VRUN timming.

1.Add PR174 0_0402_5%.

2. Add PD23 RB751V.

1.Add PR185 33K_0402_1%.

2. Add PQ34 2N7002.

While RUNPWROK enables +VCCP_1P05VP,+1.5VSUSP will trigger
OVP function. This occurs on OVP pin in transition.

Add PR188 11K_0402_1% X00

2004/7/9 DELL X00Pop PR173, nopop PR174.44 +1.2V/+1.8V RUN_ON_D output is not supported by Gilbert BIOS code.

Solution Description Rev.Page# TitleItem Issue DescriptionDate

X00

X00

X00

X00

X00

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power-Changed-List History

LA-2501

1

48 48Tuesday, October 05, 2004

0.2

of