Page 1
A
B
C
D
E
LA-2411
1 1
2 2
Compal confidential
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic
3 3
4 4
A
B
2004-06-28
REV:0.3
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
星期三 七月
LA-2411
0.1
of
165, 07, 2004
E
Page 2
A
B
C
D
E
Compal confidential
File Name :LA2411
1 1
CRT & TV-OUT Conn.
LCD Conn
W/EXT VGA CHIP
W/EXT VGA CHIP
VGA DDR x2 CHB
2 2
page 23
ATI-M9+X/M10C
page 17,18,19,20,21
VGA DDR x2 CHA
page 25
page 25
page 22
Fan Control
page 7
W/O EXT VGA CHIP
W/O EXT VGA CHIP
AGP BUS
Intel Northwood/Prescott Processor
uFCBGA-479/uFCPGA-478 CPU
page 4,5,6
H_A#(3..31)
PSB
800MHz
H_D#(0..63)
ATI-RC300M
VGA M9 Embeded
868 pin u-BGA
page 8,9,10,11,12,13
A-Link
Thermal Sensor
ADM1032AR
page 7
Memory BUS(DDR)
2.5V DDR- 200/266
USB1.1
USB2.0
CLOCK GENERATOR
ICS951402AGT
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
BT
page 14,15,16
page 42
USB conn x4
page 35
Audio Codec
ALC 250
page 36
page 24
AMP & Audio Jack
page 37
MDC & BT Conn
3.3V 33 MHz
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
IEEE 1394
TI-TSB43AB22
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
3 3
Mini PCI
socket
page 41page 34
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)
RTL 81000CL
RJ45 CONN
LAN
page 33
page 33
CardBus Controller
RTC CKT.
page 26
Power OK CKT.
page 46
ENE910
page 44
PCI BUS
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
ENE 714/1410
Slot 0
page 32
page 31
Card slot
page 32
ATI-SB200
BGA 457 pin
page 26,27,28,29
LPC BUS
AC-LINK
Primary IDE
ATA-100
Secondary IDE
ATA-100
Mini-PCI solt
SUPER I/O SMC 207
page 42
page 41
HDD
Connector
page 30
CDROM
Connector
page 30
page 38
RJ11 CONN
page 42
CABLE CONN.
*RJ45 CONN
*LINE IN JACK
*DC JACK
*COM PORT
page 41
*USB CONN x1
Power On/Off CKT.
page 46
4 4
DC/DC Int erface CKT.
page 47
Touch Pad
page 40
EC I/O Bu ffer
page 45
Int.KBD
BIOS
page 43
page 45
FIR
page 43
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT
Power Circuit DC/DC
page 50,51,52,53,54,55,56,57
A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-2411
星期三 七月
Block Diagram
E
0.1
of
265, 07, 2004
Page 3
Voltage Rails
A
Power Plane
VIN
B+
+VCC_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
The voltage for Processor VID select
1.25V switched power rail for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V switched power rail for ATI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
S3
S0-S1
N/AONN/A
N/A
N/A
N/A
ON
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ONON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
OFF
ON
ON
ON
ON
ON
S5
N/A
OFF
OFF
OFF
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*+5VALW 5V always on power rail
ON*
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means bui ld ATI SB USB2.0 related to turn on the function .
NEC@ : means bu ild NEC USB2.0 related to turn on the function .
Board ID Table for AD channel
External PCI Devices
1 1
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
IDSEL # PIRQ
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
REQ/GNT #DEVICE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
A
A
N/A
D
B
A
C
A
D
A.B
C
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
A2
D2
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
7 NC
Board ID
0
1
2
3
4
5
6
7
AD_BID
0 V
Vtyp
AD_BID
0 V 0 V
V
AD_BID
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
PCB Revision
0.1
max
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
星期三 七月
LA-2411
Notes List
of
365, 07, 2004
0.1
Page 4
5
4
+VCC_CORE
3
2
1
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C C
H_REQ#[0..4]<8>
H_ADS#<8>
R230
51_0402_5%
+VCC_CORE
+VCC_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
VCCA VCCIOPLLConnect to CPU
AE23
VCCIOPLL VCCA
AD20
AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/
TESTHI12 TESTHI12AD25 DPSLP
Commend Commend
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Connect to CPU
Filter
Connect to GND CPU determine
Pull-up 200ohm
to +VCC_CORE
5
1 2
R231
1 2
H_BR0#<8>
H_BPRI#<8>
H_BNR#<8>
H_LOCK#<8>
CK_BCLK<24>
CK_BCLK#<24>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
COMPAT#
float
Pull-up 62ohm
to +VCC_CORE
51_0402_5%
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
CK_BCLK
CK_BCLK#
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VCCIOPLL
VSS
VSS
AF22
AF23
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
J1
K5
J4
J3
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
F3
E3
E2
A10
JP8A
VCC_0
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to GND
Connect to PLD
through 0ohm
4
A12
A14
VCC_1
Commend
A16
VCC_2
VSS_0H1VSS_1H4VSS_2
float
float
float
VCC_3
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
VCC_65C8VCC_66
VCC_84
VCC_85
F9
F11
VCC_67
VCC_68
VCC_69
VCC_78
VCC_79E8VCC_80
E18
E20
+VCC_CORE
1 2
VCC_70
VCC_77
E10
VCC_71D7VCC_72
VCC_73
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
AMP_3-1565030-1_Prescott
E12
E14
E16
12
R1099
47K_0402_5%
3 1
2
H_D#[0..63] <8>H_A#[3..31]<8>
+5VS+5VS
12
1
C
R1100
47K_0402_5%
Q106
2SC2411K_SC59
E3B
H_BOOTSELECT <54>
H_D#0
B21
D#0
H_D#1
B22
D#1
H_D#2
A23
D#2
H_D#3
A25
D#3
H_D#4
C21
D#4
H_D#5
D22
D#5
H_D#6
B24
D#6
H_D#7
C23
D#7
H_D#8
C24
D#8
H_D#9
B25
D#9
H_D#10
G22
H_D#11
H21
H_D#12
C26
H_D#13
D23
H_D#14
J21
H_D#15
D25
H_D#16
H22
H_D#17
E24
H_D#18
G23
H_D#19
F23
H_D#20
F24
H_D#21
E25
H_D#22
F26
H_D#23
D26
H_D#24
L21
H_D#25
G26
H_D#26
H24
H_D#27
M21
H_D#28
L22
H_D#29
J24
H_D#30
K23
H_D#31
H25
H_D#32
M23
H_D#33
N22
H_D#34
P21
H_D#35
M24
H_D#36
N23
H_D#37
M26
H_D#38
N26
H_D#39
N25
H_D#40
R21
H_D#41
P24
H_D#42
R25
H_D#43
R24
H_D#44
T26
H_D#45
T25
H_D#46
T22
H_D#47
T23
H_D#48
U26
H_D#49
U24
H_D#50
U23
H_D#51
V25
H_D#52
U21
H_D#53
V22
H_D#54
V24
H_D#55
W26
H_D#56
Y26
H_D#57
W25
H_D#58
Y23
H_D#59
Y24
H_D#60
Y21
H_D#61
AA25
H_D#62
AA22
H_D#63
AA24
2
Q107
MMBT3904_SOT23
A18
A20
AA10
AA12
AA14
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
Prescott
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
Northwood
AA4
AA7
AA11
AA13
AA9
AA15
AA17
AA19
AA23
AA26
AB10
Prescott
AB12
AB14
AB16
Northwood
MT
AB3
AB6
AB8
AC2
AC5
AC7
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC9
AC17
AC19
AC22
AC25
AD10
AD12
AD14
BOOTSELECT
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VCC_81
VCC_82
VCC_83
F13
F15
F17
F19
AD1
AD4
AD8
AD16
AD18
AD21
AD23
R899 22K_0402_5%
12
R900
100K_0402_5%
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
Pop
Depop
DepopPop
Pop Pop
Pop
Pop
Pop
Pop
Depop
Depop
Depop
Pop
Pop
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-2411
星期三 七月
, 2004
1
0.1
of
465, 07
Page 5
5
+VCC_CORE
R513 56_0402_5%
R515 56_0402_5%
D D
R519 56_0402_5%
C C
B B
+VCC_CORE
A A
H_FERR#
1 2
H_THERMTRIP#
1 2
R517 130_0402_5%
H_PROCHOT#
1 2
R518 300_0402_5%
H_PWRGOOD
1 2
H_RESET#
1 2
+VCC_CORE
L36 LQG21F4R7N00_0805
1 2
1 2
L37 LQG21F4R7N00_0805
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
R546
@54.9_0603_1%
1 2
If CPU is P4 , Change the resistor
R546 value to 75_0603_1%
R547
@54.9_0603_1%
1 2
Close to the ITP
R550
1K_0402_5%
12
R552 1K_0402_5%
1 2
12
R556 1K_0402_5%
ITP_TDO
ITP_DBRESET#
ITP_TMS
ITP_TDI
ITP_TCK
Place near SB200 (U6)
Place near CPU
+VCC_CORE
Note: Please change to 10uH, DC current
of 100mA parts and close to cap
33U_D2_8M_R35
C544
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>
H_FERR#<26>
H_IGNNE#<26>
H_PWRGOOD<26>
H_STPCLK#<26>
H_INIT#<26>
H_RESET#<8,26>
H_DBSY#<8>
H_DRDY#<8>
H_THERMDA<7>
H_THERMDC<7>
H_THERMTRIP#<7>
R529 56_0402_5%
1 2
R530 56_0402_5%
1 2
1 8
2 7
3 6
4 5
RP137 56_0804_8P4R_5%
1
1
C854
+
+
2
2
33U_D2_8M_R35
R1017->
Pop: Prescott
Depop: Northwood
51.1 Ohm for Northwood,
61.9 Ohm for Prescott
CPUCLK_STP#<11,26,54>
H_SMI#<26>
H_INTR<26>
H_NMI<26>
VCCSENSE<54>
VSSSENSE<54>
BSEL0<13,24>
BSEL1<13,24>
H_VCCA
+VCCVID
H_VSSA
61.9_0603_1%
R1125
1 2
12K_0402_5%
R1017
CK_ITP<24>
CK_ITP#<24>
R539
Close to the CPU
R559
1K_0402_5%
1 2
Between the CPU and ITP
ITP_TRST#
5
H_FERR#
H_PWRGOOD
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
12
+3VS
2
4
H_RS#0
H_RS#1
H_RS#2
1 2
0_0402_5%
CK_ITP
CK_ITP#
COMP0
COMP1
width= 10mil
12
R540
61.9_0603_1%
12
R993
4.7K_0402_5%
2
Q96
MMBT3904_SOT23
3 1
4
JP8B
F1
RS#0
G5
RS#1
F4
RS#2
AB2
RSP#
J6
TRDY#
C6
A20M#
B6
FERR#
B2
IGNNE#
B5
SMI#
AB23
PWRGOOD
Y4
STPCLK#
D1
LINT0
E5
LINT1
W5
INIT#
AB25
RESET#
H5
DBSY#
H2
DRDY#
AD6
BSEL0
AD5
BSEL1
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AC6
BPM#0
AB5
BPM#1
AC4
BPM#2
Y6
BPM#3
AA5
BPM#4
AB4
BPM#5
D4
TCK
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
AD20
VCCIOPLL
AE23
VCCA
A5
VCCSENSE
A4
VSSSENSE
AF3
VCCVIDLB
AD22
VSSA
AC26
ITP_CLK0
AD26
ITP_CLK1
L24
COMP0
P1
COMP1
CPU_STP#
Q95
MMBT3904_SOT23
3 1
AE11
AE13
AE15
AE17
AE19
AE22
AE24
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_129F8VSS_130
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
J22
G21
G24
4.7K_0402_5%
VID_PWRGD<53,54>
SN74LVC14APWLE_TSSOP14
AE7
J25
R545
3
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
Prescott
VID0
VID1
VID2
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
L23
L26
K21
K24
+3VS
U32A
1
+3VALW
N21
N24
M22
M25
14
P
O2I
G
7
P22
P25
2
G
R23
R26
H_VID_PWRGD
13
D
Q45
S
2N7002 1N_SOT23
3
T21
T24
V23
V26
Y22
U22
U25
+VCC_CORE
12
R_A
12
R558
R_B
169_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
Y25
W21
W24
GTL Reference Voltage
Layout note :
R553
100_0402_1%
2
1
VID3
VSS_181
Y5
AE5
AE4
AE3
AE2
AE1
VID0
VID1
VID2
VID3
VID4
VID5
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
C546
1U_0603_10V4Z
F10
F12
F14
VSS_121
VSS_122
VID4
VID5
AD3
1
C547
220P_0402_25V8K
2
F16
F18
VSS_123
VSS_124
VSS_125F2VSS_126
VIDPWRGD
AD2
2
F22
F25
F5
AF26
VSS_127
VSS_128
SKTOCC#
OPTIMIZED/COMPAT#
VCCVID
AMP_3-1565030-1_Prescott
AF4
+VCCVID
1
C932
0.1U_0402_10V6K
2
H_VID_PWRGD
2
1 2
@0_0402_5%
DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
R514
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
R_E
R541
680_0603_5%
1 2
R520 @0_0402_5%
1 2
H_TESTHI0_1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
RE
Pop: Prescott
Depop: Northwood
+VCCVID
1
+CPU_GTLREF
Pop: Northwood
Depop: Prescott
+VCC_CORE
R521 56_0402_5%
1 2
R522 56_0402_5%
1 2
RP136 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
R990 300_0402_5%
1 2
R527 56_0402_5%
1 2
1 2
1 2
1
CPU_STP#
for mobile CPU
45
36
27
18
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
W/O ITP
H_PROCHOT# <49>
H_CPUSLP# <26>
VID5
VID5<54>
VID4<54>
VID3<54>
VID2<54>
VID1<54>
VID0<54>
Title
Size Document N u mb er Re v
Date: Sheet
R542 1K_0402_5%
VID4
R543 1K_0402_5%
VID3
VID2
VID1
VID0
RP94 1K_1206_8P4R_5%
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-2411
星期三 七月
, 2004
565, 07
CPU_GHI# <27>
+3VS
of
0.1
Page 6
5
4
3
2
1
+VCC_CORE
1
C131
22U_1206_16V4Z
2
D D
+VCC_CORE
1
C142
22U_1206_16V4Z
2
+VCC_CORE
1
C152
22U_1206_16V4Z
2
C C
+VCC_CORE
1
C154
22U_1206_16V4Z
2
1
C132
22U_1206_16V4Z
2
1
C143
22U_1206_16V4Z
2
1
C153
22U_1206_16V4Z
2
1
C155
22U_1206_16V4Z
2
1
C133
22U_1206_16V4Z
2
1
C144
22U_1206_16V4Z
2
1
C156
22U_1206_16V4Z
2
Place 11 North of Socket(Stuff 6)
1
C134
22U_1206_16V4Z
2
1
C135
22U_1206_16V4Z
2
1
2
Place 12 Insid e So c ke t( S tu f f all)
1
C145
22U_1206_16V4Z
2
1
C146
22U_1206_16V4Z
2
1
2
Place 9 South o f So c ke t( U ns t uf f all)
1
C157
22U_1206_16V4Z
2
1
C158
22U_1206_16V4Z
2
1
2
C136
22U_1206_16V4Z
C147
22U_1206_16V4Z
C159
22U_1206_16V4Z
1
C137
22U_1206_16V4Z
2
1
C148
22U_1206_16V4Z
2
1
C160
22U_1206_16V4Z
2
1
C138
22U_1206_16V4Z
2
1
C149
22U_1206_16V4Z
2
1
C161
22U_1206_16V4Z
2
1
C139
22U_1206_16V4Z
2
1
C150
22U_1206_16V4Z
2
1
C162
22U_1206_16V4Z
2
1
C140
22U_1206_16V4Z
2
1
C151
22U_1206_16V4Z
2
1
C141
22U_1206_16V4Z
2
B B
+VCC_CORE
1
+
C163
820U_E9_2_5V_M_R7
2
+VCC_CORE
1
C174
+
470U_D2_2.5VM
2
+VCC_CORE
A A
1
C179
+
470U_D2_2.5VM
2
SANYO OS-CON 820uF H:13*3 (C163,C164,C165)
SANYO OS-CON 820uF H:9*2 (C166,C167)
5
1
+
C164
820U_E9_2_5V_M_R7
2
1
C175
+
470U_D2_2.5VM
2
1
C180
+
470U_D2_2.5VM
2
1
+
C165
820U_E9_2_5V_M_R7
2
1
C176
+
@470U_D2_2.5VM
2
1
C181
+
470U_D2_2.5VM
2
1
+
C166
820U_E9_2_5V_M_R7
2
1
C177
+
@470U_D2_2.5VM
2
1
C182
+
470U_D2_2.5VM
2
Place Insi de S oc ket around the edge
1
+
C167
820U_E9_2_5V_M_R7
2
1
C178
+
@470U_D2_2.5VM
2
1
C183
+
@470U_D2_2.5VM
2
4
+VCC_CORE
1
C168
0.22U_0603_10V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C169
0.22U_0603_10V7K
2
1
C170
0.22U_0603_10V7K
2
1
C171
0.22U_0603_10V7K
2
2
1
C172
0.22U_0603_10V7K
2
1
C173
0.22U_0603_10V7K
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Decoupling
LA-2411
星期三 七月
, 2004
1
0.1
of
665, 07
Page 7
5
4
3
2
1
Thermal Sensor ADM1032AR
+3VALW
W=15mil
12
R283
D D
@10K_0402_5%
2200P_0402_25V7K
C253
1
2
H_THERMDA
H_THERMDC
2
C251
1
0.1U_0402_10V6K
1
2
3
U8
VDD
D+
ALERT#
DTHERM#4GND
ADM1032AR_SOP8
Address:1001_100X
SCLK
SDATA
8
7
6
5
H_THERMDA
H_THERMDC
H_THER MDA <5>
H_TH ERMDC <5>
EC_SMC_2 <44>
EC_SMD_2 <44>
+VCC_CORE
C C
EN_FAN1<44> EN_FAN2<44>
B B
R286 300_0402_5%12C256 @1U_0603_10V6K
H_THERMTRIP#<5>
R915
10K_0402_5%
H_THERMTRIP#
FAN CONN.1 FAN CONN. 2
+12VALW
8
U10A
3
+IN
2
-IN
1 2
R917
P
OUT
G
LM358A_SO8
4
8.2K_0402_5%
1
R913 100_0402_5%
EN_FAN1 EN_FAN2
12
2
B
3
E
1 2
12
1
C
Q17
2SC2411K_SC59
2
B
2
C840
0.1U_0402_10V6K
1
D25
1N4148_SOD80
R919 10K_0402_5%
1 2
+3VS
MAINPWON <48,49,51>
+5VS
1SS355_SOD323
1
C
FMMT619_SOT23
Q90
E
3
FAN1 FAN2
12
C265
10U_0805_10V4Z
12
D67
1
C855
2
1000P_0402_16V7K
12
1
2
1
2
C838
10U_0805_16V4Z
JP10
1
2
3
ACES_85205-0300
C907
1000P_0402_16V7K
R916
10K_0402_5%
U10B
5
+IN
6
12
-IN
1 2
R918
7
OUT
LM358A_SO8
8.2K_0402_5%
R914 100_0402_5%
1 2
2
C841
0.1U_0402_10V6K
1
+3VS
FANSPEED2<44>FANSPEED1<44>
+5VS
1
C
FMMT619_SOT23
2
B
Q91
E
3
12
D26
1N4148_SOD80
10U_0805_10V4Z
R920 10K_0402_5%
1 2
C266
12
D68
1SS355_SOD323
1
2
1000P_0402_16V7K
1
C839
10U_0805_16V4Z
2
1
C856
2
1
2
JP11
1
2
3
ACES_85205-0300
C908
1000P_0402_16V7K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Thermal Sensor&FAN CTRL
LA-2411
星期三 七月
, 2004
1
0.1
of
765, 07
Page 8
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
U27A
@1U_0603_10V6K
1 2
C361
1 2
C99610U_0805_10V4Z
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
D D
H_ADSTB#0<5>
C C
H_ADSTB#1<5>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<5>
H_DBSY#<5>
H_BR0#<4>
H_LOCK#<4>
H_RESET#<5,26>
H_RS#2<5>
NB_RST#<17,26>
NB_PWRGD<10,46>
1 2
1 2
L34
1 2
H_RS#1<5>
H_RS#0<5>
H_TRDY#<5>
H_HIT#<4>
H_HITM#<4>
0.1U_0402_10V6K
C974
12
--> 412_0402_1%
R380 330_0402_5%
1 2
NB_SUS_STAT#<27>
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
R383
100_0402_1%
R384
169_0402_1%
+VCC_CORE
PLACE CLOSE TO U27 Ball
W28, USE 20/20
WIDTH/SPACE
1 2
12
1
C362
1U_0603_10V6K
2
1
C363
220P_0402_25V8K
2
C363 CLOSE
TO Ball W28
B B
+VCC_CORE
R381 24.9_0402_1%
R382 49.9_0402_1%
+1.8VS
HB-1M2012-121JT03_0805
NB_GTLREF
12
R385
4.7K_0402_5%
M28
P25
M25
N29
N30
M26
N28
P29
P26
R29
P30
P28
N26
N27
M29
N25
R26
L28
L29
R27
U30
T30
R28
R25
U25
T28
V29
T26
U29
U26
V26
T25
V25
U27
U28
T29
L27
K25
H26
J27
L26
G27
F25
K26
A17
G25
G26
J25
F26
J26
H25
A9
AH5
AG5
C7
V28
W29
H23
J23
W28
Y29
Y28
B17
216RC300M_BGA_718
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD
CPU_COMP_N
CPU_COMP_P
CPVDD
CPVSS
CPU_VREF
THERMALDIODE_N
THERMALDIODE_P
TESTMODE
PART 1 OF 6
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
MISC.
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_DSTBN0#
CPU_DSTBP0#
CPU_DSTBN1#
AGTL+ I/F
CPU_DSTBP1#
PENTIUM
CPU_DSTBN2#
CPU_DSTBP2#
CPU_DSTBN3#
CPU_DSTBP3#
IV
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_D#[0..63] <4>
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29
B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27
F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22
B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>
H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>
H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
+VCC_CORE
22U_1206_16V4Z_V1
A A
5
4
C364
0.1U_0402_10V6K
1
1
C366
C365
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C367
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C368
2
1
C369
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C370
2
2
1
C371
2
0.1U_0402_10V6K
1
C372
0.1U_0402_10V6K
2
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGTL+
星期三 七月
LA-2411
of
865, 07, 2004
1
0.1
Page 9
5
U27B
DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4
D D
DDRA_RAS#<14,15,16>
DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
C C
DDRA_CLK0<14>
DDRA_CLK0#<14>
DDRA_CLK1<14>
DDRA_CLK1#<14>
DDRA_CLK3<15>
DDRA_CLK3#<15>
DDRA_CLK4<15>
DDRA_CLK4#<15>
DDRA_CKE_R0<14,16>
DDRA_CKE_R1<14,16>
DDRA_CKE_R2<15,16>
DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>
DDRA_CS#1<14,16>
DDRA_CS#2<15,16>
DDRA_CS#3<15,16>
L35
B B
A A
+1.8VS
C857
0.1U_0402_10V6K
1 2
HB-1M2012-121JT03_0805
+2.5V
1
1
C858
2
2
@0.1U_0402_10V6K
@0.1U_0402_10V6K
C859
5
DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15
DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK3
DDRA_CLK3#
DDRA_CLK4
DDRA_CLK4#
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
C375
1 2
2.2U_0805_10V4Z
1
C860
2
@0.1U_0402_10V6K
MPVDD
MPVSS
1
2
DDR_VREF
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AJ8
AF9
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
0.1U_0402_10V6K
0.1U_0402_10V6K
L
1
C861
@0.1U_0402_10V6K
2
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
216RC300M_BGA_718
2
C376
1
DDR_VREF
2
C377
1
DDR_VREF trace width of
20mils and space
20mils(min)
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM I/F
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
+2.5V+2.5V
12
R408
1K_0603_1%
12
R409
1K_0603_1%
4
DDRA_DQ0
AG6
DDRA_DQ1
AJ7
DDRA_DQ2
AJ9
DDRA_DQ3
AJ10
DDRA_DQ4
AJ6
DDRA_DQ5
AH6
DDRA_DQ6
AH8
DDRA_DQ7
AH9
DDRA_DQ8
AE7
DDRA_DQ9
AE8
DDRA_DQ10
AE12
DDRA_DQ11
AF12
DDRA_DQ12
AF7
DDRA_DQ13
AF8
DDRA_DQ14
AE11
DDRA_DQ15
AF11
DDRA_DQ16
AJ12
DDRA_DQ17
AH12
DDRA_DQ18
AH14
DDRA_DQ19
AH15
DDRA_DQ20
AH11
DDRA_DQ21
AJ13
DDRA_DQ22
AJ15
DDRA_DQ23
AJ16
DDRA_DQ24
AF18
DDRA_DQ25
AG20
DDRA_DQ26
AG21
DDRA_DQ27
AF22
DDRA_DQ28
AF19
DDRA_DQ29
AF20
DDRA_DQ30
AE22
DDRA_DQ31
AF23
DDRA_DQ32
AJ21
DDRA_DQ33
AJ22
DDRA_DQ34
AJ24
DDRA_DQ35
AK25
DDRA_DQ36
AH21
DDRA_DQ37
AH22
DDRA_DQ38
AH24
DDRA_DQ39
AJ25
DDRA_DQ40
AK26
DDRA_DQ41
AK27
DDRA_DQ42
AJ28
DDRA_DQ43
AH29
DDRA_DQ44
AH25
DDRA_DQ45
AJ26
DDRA_DQ46
AJ29
DDRA_DQ47
AH30
DDRA_DQ48
AF29
DDRA_DQ49
AE29
DDRA_DQ50
AB28
DDRA_DQ51
AA28
DDRA_DQ52
AE28
DDRA_DQ53
AD28
DDRA_DQ54
AC29
DDRA_DQ55
AB29
DDRA_DQ56
AC26
DDRA_DQ57
AB25
DDRA_DQ58
Y26
DDRA_DQ59
W26
DDRA_DQ60
AE26
DDRA_DQ61
AD26
DDRA_DQ62
AA26
DDRA_DQ63
Y27
C373 0.47U_0603_16V7K
AF6
1 2
C374 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
C378
150U_D2_6.3VM
4
Group 6 sweep Group 7
R405 49.9_0402_1%
1 2
+2.5V
1
1
+
C379
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C380
2
0.1U_0402_10V6K
C381
3
DDRA_DQ8
DDRA_DQ12
DDRA_DQ9
DDRA_DQ13
DDRA_DQ10
DDRA_DQ14
DDRA_DQ11
DDRA_DQ15
DDRA_DQS1
DDRA_DM1
DDRA_DQ0
DDRA_DQ4
DDRA_DQ1
DDRA_DQ3
DDRA_DQ7
DDRA_DQ2
DDRA_DQ6
DDRA_DQS0 DDRA_SDQS0
DDRA_DM0
DDRA_DQ20
DDRA_DQ16
DDRA_DQ21
DDRA_DQ17
DDRA_DQ18
DDRA_DQ22
DDRA_DQ19
DDRA_DQ23
DDRA_DM2 DDRA_SDM2
DDRA_DQS2
DDRA_DQ24
DDRA_DQ28
DDRA_DQ25
DDRA_DQ29
DDRA_DQ26
DDRA_DQ30
DDRA_DQ27
DDRA_DQ31
DDRA_DQS3 DDRA_SDQS3
DDRA_DM3 DDRA_SDM3
0.1U_0402_10V6K
1
C382
2
0.1U_0402_10V6K
1
1
C383
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP28
1 4
2 3
0_0404_4P2R_5%
RP31
1 4
2 3
0_0404_4P2R_5%
RP34
1 4
2 3
0_0404_4P2R_5%
RP37
1 4
2 3
0_0404_4P2R_5%
R387 0_0402_5%
R388 0_0402_5%
RP40
1 4
2 3
0_0404_4P2R_5%
RP43
1 4
2 3
0_0404_4P2R_5%
RP45
1 4
2 3
0_0404_4P2R_5%
RP47
1 4
2 3
0_0404_4P2R_5%
R394 0_0402_5%
R397 0_0402_5%
RP49
1 4
2 3
0_0404_4P2R_5%
RP51
1 4
2 3
0_0404_4P2R_5%
RP53
1 4
2 3
0_0404_4P2R_5%
RP55
1 4
2 3
0_0404_4P2R_5%
R403 0_0402_5%
R406 0_0402_5%
RP57
1 4
2 3
0_0404_4P2R_5%
RP59
1 4
2 3
0_0404_4P2R_5%
RP61
1 4
2 3
0_0404_4P2R_5%
RP63
1 4
2 3
0_0404_4P2R_5%
R412 0_0402_5%
R415 0_0402_5%
1
C384
C385
2
0.1U_0402_10V6K
DDRA_SDQ8
DDRA_SDQ12
DDRA_SDQ9
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQS1
12
DDRA_SDM1
12
DDRA_SDQ0
DDRA_SDQ4
DDRA_SDQ1
DDRA_SDQ5DDRA_DQ5
DDRA_SDQ3
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ6
12
DDRA_SDM0
12
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
12
DDRA_SDQS2
12
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQ26
DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ31
12
12
0.1U_0402_10V6K
1
C386
2
1
C387
2
0.1U_0402_10V6K
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37
DDRA_DQ33
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35
DDRA_DQS4
DDRA_DM4
DDRA_DQ40
DDRA_DQ45
DDRA_DQ41
DDRA_DQ46
DDRA_DQ42
DDRA_DQ43
DDRA_DQS5
DDRA_DM5
DDRA_DQ60 DDRA_SDQ60
DDRA_DQ57 DDRA_SDQ57
DDRA_DQ58 DDRA_SDQ58
DDRA_DQ59 DDRA_SDQ59
DDRA_DQS7
DDRA_DM7
DDRA_DQ52 DDRA_SDQ52
DDRA_DQ49 DDRA_SDQ49
DDRA_DQ50
DDRA_DQ54
DDRA_DQ51
DDRA_DQ55
0.1U_0402_10V6K
1
1
C388
2
2
0.1U_0402_10V6K
2
RP27
1 4
2 3
0_0404_4P2R_5%
RP30
1 4
2 3
0_0404_4P2R_5%
RP33
1 4
2 3
0_0404_4P2R_5%
RP36
1 4
2 3
0_0404_4P2R_5%
R386 0_0402_5%
R389 0_0402_5%
RP41
1 4
2 3
0_0404_4P2R_5%
RP44
1 4
2 3
0_0404_4P2R_5%
RP46
1 4
2 3
0_0404_4P2R_5%
RP48
1 4
2 3
0_0404_4P2R_5%
R395 0_0402_5%
R398 0_0402_5%
RP50
1 4
2 3
0_0404_4P2R_5%
RP52
1 4
2 3
0_0404_4P2R_5%
RP54
1 4
2 3
0_0404_4P2R_5%
RP56
1 4
2 3
0_0404_4P2R_5%
R404 0_0402_5%
R407 0_0402_5%
RP58
1 4
2 3
0_0404_4P2R_5%
RP60
1 4
2 3
0_0404_4P2R_5%
RP62
1 4
2 3
0_0404_4P2R_5%
RP64
1 4
2 3
0_0404_4P2R_5%
R413 0_0402_5%
R416 0_0402_5%
0.1U_0402_10V6K
1
C390
C389
2
2
1
2
12
12
12
12
12
12
12
12
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ38
DDRA_SDQ34
DDRA_SDQ39
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ44DDRA_DQ44
DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47DDRA_DQ47
DDRA_SDQ43
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQ56DDRA_DQ56
DDRA_SDQ61DDRA_DQ61
DDRA_SDQ62DDRA_DQ62
DDRA_SDQ63DDRA_DQ63
DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ48DDRA_DQ48
DDRA_SDQ53DDRA_DQ53
DDRA_SDQ50
DDRA_SDQ54
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQS6DDRA_DQS6
DDRA_SDM6DDRA_DM6
1
C391
0.1U_0402_10V6K
2
1
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7] <14,15,16>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-DDR I/F
星期三 七月
LA-2411
of
965, 07, 2004
1
0.1
Page 10
5
4
3
2
1
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
D D
C C
?
B B
47U_B_6.3VM
A A
47U_B_6.3VM
A_PAR<13,26>
A_STROBE#<26>
A_ACAT#<26>
A_END#<26>
PCI_PIRQA#<17,26,31,34>
Rb
Rc
+1.5VS +3VS
C551
+1.5VS
C552
+1.5VS+1.5VS
R576
324_0402_1%
1 2
AGPREF_8X
R577
100_0402_1%
1 2
1
1
+
C553
2
2
0.1U_0402_10V6K
1
1
+
C570
2
2
0.1U_0402_10V6K
A_DEVSEL#<26>
A_SBREQ#<26>
A_SBGNT#<26>
AGP_GNT#<17>
AGP_REQ#<17>
AGP8X_DET#<17>
VREF_8X_IN<17>
R575
PLACE CLOSE TO
CONNECTOR
0.1U_0402_10V6K
C554
0.1U_0402_10V6K
5
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
1 2
Ra
1 2
169_0402_1%
1
C555
2
0.1U_0402_10V6K
1
C572
2
0.1U_0402_10V6K
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
1 2
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
C550
1 2
0.1U_0402_10V6K
AGP_COMP
+3VS
R945
NAGP@47K_0402
1 2
0.1U_0402_10V6K
1
C556
2
0.1U_0402_10V6K
1
2
R1005 0_0402_5%
A_OFF#<26>
+3VS
AGP8X_DET#
C571
AK5
AJ5
AJ4
AH4
AJ3
AJ2
AH2
AH1
AG2
AG1
AG3
AF3
AF1
AF2
AF4
AE3
AE4
AE5
AE6
AC2
AC4
AB3
AB2
AB5
AB6
AA2
AA4
AA5
AA6
Y3
Y5
Y6
AG4
AE2
AC3
AA3
AD5
AC6
AC5
AD2
W4
AD3
AD6
W5
W6
R570
V5
V6
K5
K6
M5
J6
J5
1
C557
2
0.1U_0402_10V6K
1
C573
2
U27C
ALINK_AD0
ALINK_AD1
ALINK_AD2
ALINK_AD3
ALINK_AD4
ALINK_AD5
ALINK_AD6
ALINK_AD7
ALINK_AD8
ALINK_AD9
ALINK_AD10
ALINK_AD11
ALINK_AD12
ALINK_AD13
ALINK_AD14
ALINK_AD15
ALINK_AD16
ALINK_AD17
ALINK_AD18
ALINK_AD19
ALINK_AD20
ALINK_AD21
ALINK_AD22
ALINK_AD23
ALINK_AD24
ALINK_AD25
ALINK_AD26
ALINK_AD27
ALINK_AD28
ALINK_AD29
ALINK_AD30
ALINK_AD31
ALINK_CBE#0
ALINK_CBE#1
ALINK_CBE#2
ALINK_CBE#3
PCI_PAR/ALINK_NC
PCI_FRAME#/ALINK_STROBE#
PCI_IRDY#/ALINK_ACAT#
PCI_TRDY#/ALINK_END#
INTA#
ALINK_DEVSEL#
PCI_STOP#/ALINK_OFF#
ALINK_SBREQ#
ALINK_SBGNT#
PCI_REQ#0/ALINK_NC
PCI_GNT#0/ALINK_NC
AGP2_GNT#/AGP3_GNT
AGP2_REQ#/AGP3_REQ
AGP8X_DET#
AGP_VREF/TMDS_VREF
AGP_COMP
216RC300M_BGA_718
0.1U_0402_10V6K
1
1
C559
C558
2
2
0.1U_0402_10V6K
+1.5VS
C574
0.1U_0402_10V6K
Ra
Rb
Rc
0.1U_0402_10V6K
1
C560
2
1
C575
2
0.1U_0402_10V6K
PART 3 OF 6
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
PCI Bus 0 / A-Link I/F
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
8X(M9+M10@)
169_0402_1%
324_0402_1%
100_0402_1%
1
1
C561
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C576
2
2
4
10U_0805_10V4Z
C632
0.1U_0402_10V6K
1
C578
C577
2
0.1U_0402_10V6K
4X(NAGP@)
1K_0402_1%
1K_0402_1%
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD31
AGP_PAR
AGP_ST0
AGP_ST1
AGP_ST2
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
E5
E6
T3
U2
G3
H2
R3
M1
L3
H1
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
C3
C2
D4
E4
F6
F5
G6
G5
L6
M6
L5
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#2/AGP3_CBE2
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
Depop
0.1U_0402_10V6K
1
1
C562
C563
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C938
C937
2
2
0.1U_0402_10V6K
Note: PLACE C L OS E TO U 27 (N B R C300M)
L
0.1U_0402_10V6K
1
1
C564
C565
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C939
C940
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI/PIPE#
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
1
C566
2
0.1U_0402_10V6K
1
C941
2
0.1U_0402_10V6K
3
0.1U_0402_10V6K
1
C567
2
0.1U_0402_10V6K
1
C942
2
AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>
AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>
1
C568
2
0.1U_0402_10V6K
1
C943
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C944
2
1
C569
2
1
C945
2
0.1U_0402_10V6K
C947
0.01U_0402_16V7Z
0.1U_0402_10V6K
1
C946
2
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA1
AGP_SBA0
Pop for internal AGP
Depop for M11P
NB_PWRGD<8,46>
+1.5VS
1
2
ATI request
0.01U_0402_16V7Z
1
1
C948
2
2
0.01U_0402_16V7Z
2
AGPAND LVDS MUXED SIGNALS
R560 NAPG@0_0402_5%
1 2
R561 NAPG@0_0402_5%
1 2
R562 NAPG@0_0402_5%
1 2
R563 NAPG@0_0402_5%
1 2
R994 NAPG@0_0402_5%
1 2
R995 NAPG@0_0402_5%
1 2
+3VS
ENBKL#
2
R568
G
1 2
13
D
Q1
S
NAPG@10K_0402_5%
NAGP@2N7002_SOT23
Pop for internal AGP
Depop for M11P
0.01U_0402_16V7Z
1
1
2
C935
C950
2
0.01U_0402_16V7Z
Title
Size Document Number Rev
Date: Sheet
星期三 七月
C864
0.01U_0402_16V7Z
1
C949
2
ENBKL#
ENAVDD <17,25>
AGP_STP# <17,27>
AGP_BUSY# <17,27>
DDC_DAT
DDC_CLK
+3VS
1 2
13
D
2
G
S
NAGP@2N7002_SOT23
0.01U_0402_16V7Z
1
1
C936
2
2
0.01U_0402_16V7Z
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R567
NAGP@10K_0402_5%
Q2
R569
1 2
NAGP@0_0402_5%
1
C934
C933
2
0.01U_0402_16V7Z
DDC_DAT <17,25>
DDC_CLK <17,25>
1
2
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-2411
1
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_CBE#[0..3] <17>
AGP_ST[0..2] <17>
ENBKL <17,44>
0.01U_0402_16V7Z
1
C951
2
of
10 65, 07, 2004
0.1
Page 11
5
4
3
2
1
D D
+2.5VS
12
L59
KC FBM-L11-201209-221LMAT_0805
1
C587
0.1U_0402_10V6K
C592
CLK_NB_BCLK#<24>
CLK_MEM_66M<24>
1
2
CLK_NB_BCLK<24>
CLK_AGP_66M<24>
2
+1.8VS_AVDDDI
+1.8VS_AVDDQ
PLLVDD_18
1
C593
0.1U_0402_10V6K
2
RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_BCLK
CLK_NB_BCLK#
CLK_AGP_66M
CLK_MEM_66M
R592 10K_0402_5%
TV_CRMA <17,46>
TV_LUMA <17,46>
TV_COMPS <17,46>
KC FBM-L11-201209-221LMAT_0805
L60
+1.8VS
C C
REFCLK1_NB<24>
CLK_AGP_66M
12
R588
@10_0402_5%
C601
@15P_0402_50V8J
CLK_MEM_66M
B B
12
R591
@10_0402_5%
C603
@15P_0402_50V8J
L
CRMA_R
LUMA_R TV_LUMA
L
CRT_R<17,25>
CRT_G<17,25>
CRT_B<17,25>
A A
CRT_HSYNC<17,25>
CRT_VSYNC<17,25>
DDCCLK_R
DDCDATA_R
5
1 2
0.1U_0402_10V6K
L61
+1.8VS
KC FBM-L11-201209-221LMAT_0805
+1.8VS
KC FBM-L11-201209-221LMAT_0805
1
C588
2
1 2
0.1U_0402_10V6K
L62
1 2
R585 0_0402_5%
1 2
R587
56_0402_5%
1
1
C590
C589
0.1U_0402_10V6K
2
2
1
C591
10U_0805_16V4Z
2
0.1U_0402_10V6K
R584 715 _0402_1%
1 2
12
+3VS
Note: PLACE CLOSE TO U27 (NB CHIP)
R597 NAPG@0_0402_5%
1 2
R598 NAPG@0_0402_5%
1 2
R599 NAPG@0_0402_5%
1 2
TV_CRMA
TV_COMPSCOMPS_R
Note: PLACE CLOSE TO U6 (VGA CHIP)
CRT_R
R594 NAPG@0_0402_5%
1 2
R595 NAPG@0_0402_5%
1 2
CRT_B BLUE_R
R596 NAPG@0_0402_5%
1 2
CRT_HSYNC
CRT_VSYNC
RP103
1 4
2 3
NAGP@0_4P2R_0402_5%
RP104
14
NAGP@0_4P2R_0402_5%
23
HSYNC_R
VSYNC_R
3VDDCCL
3VDDCDA
RED_R
GREEN_RCRT_G
4
3VDDCCL <17,25>
3VDDCDA <17,25>
L58
1 2
FBM-11-160808-121-T_0603
U27D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
D8
ALINK_CLK
B2
AGPCLKOUT
B3
AGPCLKIN
A3
EXT_MEM_CLK
D7
USBCLK
B7
REF27
C5
OSC
216RC300M_BGA_718
L
+3VS
1
C586
0.1U_0402_10V6K
2
PART 4 OF 6
LVDS
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
C_R
Y_G
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
CRMA_R
E15
LUMA_R
C15
COMPS_R
D15
DDCCLK_R
D6
DDCDATA_R
C6
D5
A8
B8
R590 1K_0402_5%
TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>
+1.8VS_LPVDD
+1.8VS_LVDDR
Q97
@2N7002 1N_SOT23
D
1 3
R589 @0_0402_5%
C594
0.1U_0402_10V6K
C598
0.1U_0402_10V6K
S
G
2
1
2
0.1U_0402_10V6K
1
2
CPUCLK_STP#
0.1U_0402_10V6K
1
C596
C595
2
10U_0805_16V4Z
1
C600
C599
2
10U_0805_16V4Z
+3VS
Note: PLACE CLOSE TO U27 (NB CHIP)
RC300M_X1
@1M_0402_1%
RC300M_X2
12
R593
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C604
12
@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201
C605
@18P_0402_50V8K
2
KC FBM-L11-201209-221LMAT_0805
1 2
L63
1
2
KC FBM-L11-201209-221LMAT_0805
1 2
L64
1
2
CPUCLK_STP# <5,26,54>
PCI_RST# <26,30,31,33,34,38,41,44>
Title
Size Document Number Rev
Date: Sheet
星期三 七月
+1.8VS
+1.8VS
Compal Electronics, Inc.
ATI RC300M-VIDEO I/F
LA-2411
1
0.1
of
11 65, 07, 2004
Page 12
5
4
3
2
1
+1.5VS +2.5V
D D
C C
B B
+VCC_CORE
+3VS
U27E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
216RC300M_BGA_718
PART 5 OF 6
CORE PWR
CPU I/F PWRALINK PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
MEM I/F PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
M9-M10@0_0603_5%
R418
1 2
R419 NAGP@0_0603_5%
1 2
+1.8VS
Pop for internal AGP
Depop for M11P
+1.5VS
+3VS
U27F
PART 6 OF 6
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7
VSS
216RC300M_BGA_718
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8
Pop for M11P
Depop for internal AGP
+1.8VS
C579
10U_0805_10V4Z
A A
5
4
1
C580
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C581
2
1
C582
2
0.1U_0402_10V6K
1
1
C583
0.1U_0402_10V6K
2
2
Compal Electronics, Inc.
ATI RC300M-POWER
星期三 七月
LA-2411
0.1
of
12 65, 07, 2004
1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Page 13
5
4
3
2
1
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
R420 10K_0402_5%
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
5
R422 4.7K_0402_5%
R425 4.7K_0402_5%
R427 10K_0402_5%
1 2
R429 @4. 7K_0402_5%
R430 @10K_0402_5%
1 2
R431 4.7K_0402_5%
R434 10K_0402_5%
1 2
R435 @4. 7K_0402_5%
R438 10K_0402_5%
1 2
R440 @4. 7K_0402_5%
R443 10K_0402_5%
1 2
R444 @4. 7K_0402_5%
R448 10K_0402_5%
1 2
R452 10K_0402_5%
1 2
R454 @4. 7K_0402_5%
R1309 10K_0402_5%
1 2
R457 @4. 7K_0402_5%
R461 10K_0402_5%
1 2
R462 @4. 7K_0402_5%
R464 @4. 7K_0402_5%
R465 4.7K_0402_5%
R466 @4. 7K_0402_5%
R467 @4. 7K_0402_5%
R468 @4. 7K_0402_5%
R469 @4. 7K_0402_5%
1 2
R424 10K_0402_5%
1 2
2 1
D85
RB751V_SOD323
2 1
D86
RB751V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 <5,24>
+3VS
BSEL0 <5,24>
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcS hortReset#
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3: NOT USED
A_CBE#0 :NO USED
4
A_AD[31..30 ] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
A_CBE#[0..3]
A_AD18
A_AD17
A_PAR<10,26>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
R421 @4. 7K_0402_5%
R423 4.7K_0402_5%
R426 @4. 7K_0402_5%
R428 4.7K_0402_5%
A_PAR
R463 @4. 7K_0402_5%
R460 4.7K_0402_5%
+3VS
+3VS
+3VS
2
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
0: DEBUG MODE
1: NORMAL
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-SYSTEM STRAP
星期三 七月
LA-2411
of
13 65, 07, 2004
1
0.1
Page 14
5
DDRA_SDQ[0..63]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
D D
C C
B B
Group 0 sweep Group 1
Group 6 sweep Group 7
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
3
+2.5V
JP24
1
VREF
3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_CLK0<9>
DDRA_CLK0#<9>
DDRA_CKE_R1<9,16>
DDRA_WE#<9,15,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE_R1 DDRA_CKE_R0
DDRA_ADD12
DDRA_ADD9
DDRA_ADD7
DDRA_ADD5
DDRA_ADD3
DDRA_ADD1
DDRA_ADD10
DDRA_ADD13
DDRA_WE#
DDRA_CS#0 DDRA_CS#1
DDRA_ADD15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<15, 24,27>
SMB_CK_CLK2<15,24,27>
+3VS
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
AMP_1565918-1
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
DIMM0
REVERSE
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
S1#
DU
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
DU
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_ADD11
DDRA_ADD8
DDRA_ADD6
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_ADD14
DDRA_RAS#
DDRA_CAS#
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
2
L
DDRA_CKE_R0 <9,16>
DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>
DDRA_CLK1# <9>
DDRA_CLK1 <9>
Group 6 sweep Group 7
+2.5V+2.5V
C411
0.1U_0402_10V6K
C412
0.1U_0402_10V6K
12
12
2
1
DDRA_VREF
2
1
DDRA_VREF trace width of
20mils and space 20mils(min)
R472
1K_0603_1%
R473
1K_0603_1%
1
System Memory Decoupling caps
+2.5V
1
C413
0.1U_0402_10V6K
2
A A
+2.5V
1
2
5
C426
0.1U_0402_10V6K
1
C414
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
C415
0.1U_0402_10V6K
2
1
C428
0.1U_0402_10V6K
2
1
C416
0.1U_0402_10V6K
2
1
C429
0.1U_0402_10V6K
2
1
C417
0.1U_0402_10V6K
2
1
C430
0.1U_0402_10V6K
2
1
C418
0.1U_0402_10V6K
2
1
C431
0.1U_0402_10V6K
2
4
1
C419
0.1U_0402_10V6K
2
1
C432
0.1U_0402_10V6K
2
1
C420
0.1U_0402_10V6K
2
1
C433
0.1U_0402_10V6K
2
1
C421
0.1U_0402_10V6K
2
1
C434
0.1U_0402_10V6K
2
1
C422
0.1U_0402_10V6K
2
1
C435
0.1U_0402_10V6K
2
3
1
C423
0.1U_0402_10V6K
2
1
C436
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C424
0.1U_0402_10V6K
2
1
C437
0.1U_0402_10V6K
2
1
C425
10U_0805_6.3V6M
2
1
C438
10U_0805_6.3V6M
2
Title
Size Document N u mb er Re v
2
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT1
LA-2411
星期三 七月
, 2004
1
0.1
of
14 65, 07
Page 15
5
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
DDRA_SDM[0..7]<9,14,16>
D D
C C
B B
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
Group 0 sweep Group 1
DDRA_CLK3<9>
DDRA_CLK3#<9>
Group 6 sweep Group 7
+2.5V
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE3
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#2
DDRA_SMA15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<14, 24,27>
SMB_CK_CLK2<14,24,27>
+3VS
JP23
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
AMP_1565917-1
4
DIMM1
STANDARD
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
3
C392
0.1U_0402_10V6K
DDRB_VREF
C393
0.1U_0402_10V6K
+2.5V+2.5V
12
12
DDRA_CKE_R3<9,16>
R470
1K_0603_1%
R471
1K_0603_1%
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
DDRA_SMA9
DDRA_SMA12
DDRA_SMA5
DDRA_SMA7
DDRA_SMA1
DDRA_SMA3
DDRA_SMA13
DDRA_SMA10
DDRA_WE# DDRA_SWE#
DDRA_CS#2 DDRA_SCS#2
+2.5V
2
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
22
VDD
24
26
DM1
28
VSS
30
32
34
VDD
36
VDD
38
VSS
40
VSS
42
44
46
VDD
48
DM2
50
52
VSS
54
56
58
VDD
60
62
DM3
64
VSS
66
68
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
88
VSS
90
VSS
92
VDD
94
VDD
96
98
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
120
122
S1#
124
DU
126
VSS
128
130
132
VDD
134
DM4
136
138
VSS
140
142
144
VDD
146
148
DM5
150
VSS
152
154
156
VDD
158
160
CK1
162
VSS
164
166
168
VDD
170
DM6
172
174
VSS
176
178
180
VDD
182
184
DM7
186
VSS
188
190
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE2
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#3
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
+3VS
DDRA_CLK4# <9>
DDRA_CLK4 <9>
2
1
2
1
DDRB_VREF trace width of
L
20mils and space
20mils(min)
2
DDRA_CKE3DDRA_CKE_R3
12
R1122 10_0402_5%
RP26
DDRA_ADD9
1 4
DDRA_ADD12
2 3
10_0404_4P2R_5%
RP32
DDRA_ADD5
1 4
DDRA_ADD7
2 3
10_0404_4P2R_5%
RP38
DDRA_ADD1
1 4
DDRA_ADD3
2 3
10_0404_4P2R_5%
RP42
DDRA_ADD13 DDRA_SMA14DDRA_ADD14
1 4
DDRA_ADD10
2 3
10_0404_4P2R_5%
12
R392 10_0402_5%
12
R401 10_0402_5%
DDRA_ADD15DDRA_SMA15
12
R391 10_0402_5%
DDRA_CKE_R2<9,16>
1
DDRA_CKE2DDRA_CKE_R2
12
R1121 10_0402_5%
RP29
1 4
2 3
10_0404_4P2R_5%
RP35
1 4
2 3
10_0404_4P2R_5%
RP39
1 4
2 3
10_0404_4P2R_5%
12
12
12
12
DDRA_SMA8
DDRA_SMA11
DDRA_SMA4
DDRA_SMA6
DDRA_SMA0
DDRA_SMA2
DDRA_ADD8
DDRA_ADD11
DDRA_ADD4
DDRA_ADD6
DDRA_ADD0
DDRA_ADD2
R390 10_0402_5%
DDRA_RAS#<9,14,16>
DDRA_CAS#<9,14,16>
DDRA_CS#3<9,16>
DDRA_RAS# DDRA_S RAS#
R396 10_0402_5%
DDRA_CAS# DDRA_S CAS#
R393 10_0402_5%
DDRA_CS#3 DDRA_SCS#3
R402 10_0402_5%
System Memory Decoupling caps
+2.5V
1
2
+2.5V
1
2
C394
22U_1206_10V4Z
C403
0.1U_0402_10V6K
A A
1
C395
0.1U_0402_10V6K
2
1
C404
0.1U_0402_10V6K
2
5
1
C396
0.1U_0402_10V6K
2
1
C405
0.1U_0402_10V6K
2
1
C397
0.1U_0402_10V6K
2
1
C406
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C407
0.1U_0402_10V6K
2
1
C399
0.1U_0402_10V6K
2
1
C408
0.1U_0402_10V6K
2
1
C400
0.1U_0402_10V6K
2
1
C409
0.1U_0402_10V6K
2
4
1
C401
10U_0805_6.3V6M
2
10U_0805_6.3V6M
0.1U_0402_10V6K
1
C410
2
150U_D2_6.3VM
C1120
1
C402
2
1
2
+
150U_D2_6.3VM
1
+
C1118
2
C1121
1
+
150U_D2_6.3VM
2
C1119
1
150U_D2_6.3VM
+
2
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT2
LA-2411
星期三 七月
, 2004
1
of
15 65, 07
0.1
Page 16
5
4
3
2
1
DDR Termination resistors & Decoupling caps
+1.25VS +1.25VS
RP65
DDRA_SDQ8
1 8
DDRA_SDQ9
2 7
DDRA_SDQ12
3 6
DDRA_SDQ13
4 5
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ[0..63]<9,14,15>
DDRA_SDQS[0..7]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
56 _0804_8P4R_5%
RP68
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP71
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP74
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP77
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP80
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP83
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP86
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP90
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
D D
C C
R474
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
RP66
DDRA_SDQ30
18
DDRA_SDQ31
27
DDRA_SDQ26
36
DDRA_SDQ27
45
56 _0804_8P4R_5%
RP69
DDRA_CKE_R0
14
DDRA_CKE_R1
23
33_0404_4P2R_5%
RP75
DDRA_ADD9
18
DDRA_ADD3
27
DDRA_ADD7
36
DDRA_ADD5
45
33_0804_8P4R_5%
RP78
DDRA_ADD1
18
DDRA_ADD10
27
DDRA_ADD13
36
DDRA_ADD15
45
33_0804_8P4R_5%
RP81
DDRA_ADD8
18
DDRA_ADD6
27
DDRA_ADD4
36
DDRA_ADD2
45
33_0804_8P4R_5%
RP84
DDRA_ADD0
18
DDRA_ADD14
27
DDRA_RAS#
36
DDRA_CAS#
45
33_0804_8P4R_5%
RP87
DDRA_WE#
14
DDRA_ADD11
23
33_0404_4P2R_5%
RP89
DDRA_CS#0
14
DDRA_CS#3
23
33_0404_4P2R_5%
DDRA_ADD12
12
33_0402_5%
RP72
DDRA_CKE_R3
14
DDRA_CKE_R2
23
33_0404_4P2R_5%
RP92
DDRA_CS#1
14
DDRA_CS#2
23
33_0404_4P2R_5%
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
PIR BOM & Layout 93.1.9
R1180
1 2
@100_0402_5%
DDRA_RAS# <9,14,15>
DDRA_CAS# <9,14,15>
DDRA_ WE # <9,14,15>
DDRA_CS#0 <9,14>
DDRA_CS#3 <9,15>
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
DDRA_CS#1 <9,14>
DDRA_CS#2 <9,15>
RP67
DDRA_SDQ32
18
DDRA_SDQ33
27
DDRA_SDQ36
36
DDRA_SDQ37
45
56 _0804_8P4R_5%
RP70
DDRA_SDQS4
18
DDRA_SDQ34
27
DDRA_SDM4
36
DDRA_SDQ38
45
56 _0804_8P4R_5%
RP73
DDRA_SDQ35
18
DDRA_SDQ39
27
DDRA_SDQ44
36
DDRA_SDQ40
45
56 _0804_8P4R_5%
RP76
DDRA_SDQ46
18
DDRA_SDQ47
27
DDRA_SDQ42
36
DDRA_SDQ43
45
56 _0804_8P4R_5%
RP79
DDRA_SDQ45
18
DDRA_SDM5
27
DDRA_SDQ41
36
DDRA_SDQS5
45
56 _0804_8P4R_5%
RP82
DDRA_SDQ60
18
DDRA_SDQ61
27
DDRA_SDQ56
36
DDRA_SDQ57
45
56 _0804_8P4R_5%
RP85
DDRA_SDM7
18
DDRA_SDQ62
27
DDRA_SDQS7
36
DDRA_SDQ58
45
56 _0804_8P4R_5%
RP88
DDRA_SDQ63
18
DDRA_SDQ52
27
DDRA_SDQ59
36
DDRA_SDQ48
45
56 _0804_8P4R_5%
RP91
DDRA_SDQ53
18
DDRA_SDM6
27
DDRA_SDQ49
36
DDRA_SDQS6
45
56 _0804_8P4R_5%
RP93
DDRA_SDQ54
18
DDRA_SDQ55
27
DDRA_SDQ51
36
DDRA_SDQ50
45
56 _0804_8P4R_5%
+2.5V
1
C475
0.1U_0402_10V6K
2
+2.5V
1
C493
0.1U_0402_10V6K
2
1
C476
0.1U_0402_10V6K
2
1
C494
0.1U_0402_10V6K
2
1
C477
0.1U_0402_10V6K
2
1
C495
0.1U_0402_10V6K
2
1
C478
0.1U_0402_10V6K
2
1
C496
0.1U_0402_10V6K
2
1
2
1
2
+1.25VS
C479
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
1
C480
0.1U_0402_10V6K
2
1
C481
0.1U_0402_10V6K
2
1
2
+1.25VS
C482
0.1U_0402_10V6K
B B
+2.5V
1
C451
0.1U_0402_10V6K
2
+1.25VS
1
C459
0.1U_0402_10V6K
2
+1.25VS
1
C467
0.1U_0402_10V6K
2
+1.25VS
1
A A
C483
0.1U_0402_10V6K
2
1
C452
0.1U_0402_10V6K
2
1
C460
0.1U_0402_10V6K
2
1
C468
0.1U_0402_10V6K
2
1
C484
0.1U_0402_10V6K
2
1
C453
0.1U_0402_10V6K
2
1
C461
0.1U_0402_10V6K
2
1
C469
0.1U_0402_10V6K
2
1
C485
0.1U_0402_10V6K
2
5
1
C454
0.1U_0402_10V6K
2
1
C462
0.1U_0402_10V6K
2
1
C470
0.1U_0402_10V6K
2
1
C486
0.1U_0402_10V6K
2
1
C455
0.1U_0402_10V6K
2
1
C463
0.1U_0402_10V6K
2
1
C471
0.1U_0402_10V6K
2
1
C487
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
1
C464
0.1U_0402_10V6K
2
1
C472
0.1U_0402_10V6K
2
1
C488
0.1U_0402_10V6K
2
1
C457
0.1U_0402_10V6K
2
1
C465
0.1U_0402_10V6K
2
1
C473
0.1U_0402_10V6K
2
1
C489
4.7U_0805_16V6K
2
4
1
C458
0.1U_0402_10V6K
2
+1.25VS
1
C466
0.1U_0402_10V6K
2
1
C474
0.1U_0402_10V6K
2
1
C490
4.7U_0805_16V6K
2
1
+
C491
@100U_D2_10M_R45
2
1
+
C492
100U_D2_10M_R45
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR Termination Resistors
LA-2411
星期三 七月
, 2004
1
0.1
of
16 65, 07
Page 17
5
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
D D
C184 @10P_0402_50V8K
1 2
CLK_AGP_EXT_66M<24>
@RB751V_SOD323
NB_RST#<8,26>
C C
VREF_8X_IN<10>
B B
A A
R264 47_0603_1%
+1.5VS
If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R249 @10_0402_5%
R6
0_0603_5%
1
C185
0.1U_0402_10V6K
2
(Closed to M26)
(15mil)
1 2
1 2
R1316
AGP8X_DET#
Low:
AGP3.0
R936 10K_0402_5%
R574 10K_0402_5%
AGP_SUS_STAT#<27>
1 2
D69
2 1
1 2
AGP_REQ#<10>
AGP_GNT#<10>
AGP_PAR<10>
AGP_STOP#<10>
AGP_DEVSEL#<10>
AGP_TRDY#<10>
AGP_IRDY#<10>
AGP_FRAME#<10>
PCI_PIRQA#<10,26,31,34>
AGP_WBF#<10>
AGP_STP#<10,27>
AGP_BUSY#<10,27>
AGP_RBF#<10>
AGP_ADSTB0<10>
AGP_ADSTB1<10>
AGP_ADSTB0#<10>
AGP_ADSTB1#<10>
AGP_SBSTB<10>
AGP_SBSTB#<10>
@47_0603_1%
AGP_DBI_HI/PIPE#<10>
AGP_DBI_LO<10>
R265
M9+M10@0_0402_5%
(15mil)
R266 715_0603_1%
TV_CRMA<11,46>
TV_LUMA<11,46>
TV_COMPS<11,46>
R275 1K_0603_5%
R253 0_0402_5%
5
1 2
AGP8X_DET#<10>
1 2
1 2
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
CLK_AGP_EXT_66M
NB_RST_R#NB_RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
(25mil)
AGP_DBI_HI/PIPE#
AGP_DBI_LO
TV_CRMA
TV_LUMA
TV_COMPS
SSIN
SSOUT
XTALIN
SUSSTAT#
U6A
H29
AD0
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AH30
STP_AGP#
AH29
AGP_BUSY#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
M29
AD_STBS_0
V26
AD_STBS_1
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB29
SB_STBF
AB28
SB_STBS
M26
AGPREF
M27
AGPTEST
AB25
DBI_HI
AB26
DBI_LO
AC25
AGP8X_DET#
AE11
DMINUS
AF11
DPLUS
AK21
R2SET
AJ23
C_R
AJ22
Y_G
AK22
COMP_B
AJ24
H2SYNC
AK24
V2SYNC
AG23
DDC3CLK
AG24
DDC3DATA
AK25
SSIN
AJ25
SSOUT
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
AG26
SUS_STAT#
SA002160E00(0301021300)
4
M10-P/(M9+X)
(1/6)
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
PCI/AGPAGP8XCLK
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U3N
BLON/(BLON#)
THRM
SSC DAC2
TEST_MCLK/(NC)
TEST_YCLK/(NC)
PLLTEST/(NC)
RSTB_MSK/(NC)
4
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
VREFG/(NC)
ROMCS#
DVOMODE
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
MCLK_SPREAD
AF2
AG4
AF5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AE10
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
R829
AJ13
R830 M10@0_0402_5%
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
R267 100K_0402_5%
AF12
AK27
R
AJ27
G
AJ26
B
AG25
AH25
AH26
AF25
AF24
AF26
R274 10K_0402_5%
B6
E8
AE25
AG29
R276
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N
R237
VREFG
STRAP_R
STRAP_S
STRAP_T
DVOMODE
R258 0_0402_5%
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACLKTXACLK+
TXB0TXB0+
TXB1TXB1+
TXB2TXB2+
TXBCLKTXBCLK+
ENAVDD
1 2
1 2
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
AGP_RSET
R272 499_0402_1%
3VDDCDA
3VDDCCL
1 2
1 2
1K_0603_5%
+3VS
12
R955
@10K_0402_5%
R235 @1K_0402_5%
1 2
XTALIN_SS
1 2
0_0402_5%
DDC_DAT <10,25>
DDC_CLK <10,25>
1 2
TXA0- <25>
TXA0+ <25>
TXA1- <25>
TXA1+ <25>
TXA2- <25>
TXA2+ <25>
TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>
TXBCLK- <25>
TXBCLK+ <25>
ENAVDD <10,25>
M9@0_0402_5%
ENBKL
CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>
(15mil)
1 2
3VDDCDA <11,25>
3VDDCCL <11,25>
+3VS
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DRAM128M
(25 mil)
ENBKL <10,44>
3
+3VS
12
R1149
@10K_0402_5%
For 8Mx32 VGA DRAM only
+3VS
12
R234
M10@1K_0603_1%
12
R239
M10@1K_0603_1%
Vedio Memory Config.
R S
0 0
*
0 1
1 0
1 1
+3VS
M9@10K_0402_5%
R1297
1 2
ENBKL
13
D
2
G
Q30
S
M9@2N7002_SOT23
Selection Table For W180
SS%
0
1
Size Vendor
4Mx32 Samsung
4Mx32 Hynix
8Mx32 Samsung
8Mx32 Hynix
Ra 261_0603_1%
180_0603_5%
150_0402_5%
Rb
Spread % Setting for
Freq. Range
Fin>Fout>Fin-1.25%
Fin>Fout>Fin-3.75%
2
AGP, DAC & LVDS INTERFACE
ID_Disable
GPIO8
STRAP_A
VGA_Disable
GPIO7
STRAP_B
GPIO4
STRAP_D
GPIO5
STRAP_E
GPIO6
STRAP_F
GPIO0
STRAP_G
GPIO1
STRAP_H
GPIO2
STRAP_J
GPIO3
STRAP_K
GPIO9
STRAP_O
GPIO11
STRAP_L
GPIO12
STRAP_M
GPIO13
STRAP_N
STRAP_R
STRAP_S
STRAP_T
M10-PM9+X
150_0402_5%
+3VS
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
12
R261
10K_0402_5%
1
C186
0.1U_0402_10V6K
2
For VGA DDR spread sprum
+3VS
12
R269 10K_0402_5%
12
R270 10K_0402_5%
L
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
2
R232 @10K_0402_5%
R233 @10K_0402_5%
R236 @10K_0402_5%
R238 @10K_0402_5%
R240 @10K_0402_5%
R241 M10@10K_0402_5%
R242 @10K_0402_5%
R243 M10@10K_0402_5%
R244 @10K_0402_5%
R245 @10K_0402_5%
R246 @10K_0402_5%
R247 @10K_0402_5%
R248 @10K_0402_5%
R250 @10K_0402_5%
R252 @10K_0402_5%
R254 @10K_0402_5%
R255 @10K_0402_5%
R256 @10K_0402_5%
R1255 10K_0402_5%
R257 @10K_0402_5%
R1256 10K_0402_5%
R259 @10K_0402_5%
R260 @10K_0402_5%
3.3V OSC out for W18 0
X1
4
OUT
VDD
1
GND
OE
27MHZ_15P
6
U7
1
7
8
VDD
X1/CLK
CLKOUT
FS1
FS2
GND
3
12
R16 0_0402_5%
Title
Size Document Number Rev
Date: Sheet
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
FREQOUT
3
2
0.1U_0402_10V6K
1
1
C188
2
2
0.1U_0402_10V6K
R268
5
R1 @0_0402_5%
2
X2
4
SS%
SS%
W180-01GT_SO8
星期三 七月
1.5V OSC out for M9+X
1.2V OSC out for
M10-P
Ra
1 2
R262 261_0603_1%
R263
150_0402_5%
Rb
1
C189
C190
2
0.1U_0402_10V6K
22_0402_5%
1 2
1 2
R271 @10K_0402_5%
1 2
R273
10K_0402_5%
1 2
Compal Electronics, Inc.
ATI M10-P & M9+X (AGP BUS)
LA-2411
1
+3VS
12
C187
@15P_0402_50V8J
L13
1 2
1
2.2U_0603_6.3V4Z
C191
FCM2012C-800_0805
2
XTALIN_SSFREQOUT
12
R2 @22_0402_5%
1
XTALIN
XTALIN_SS
17 65, 07, 2004
+3VS
+3VS
0.1
of
Page 18
5
4
3
2
1
D D
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
C C
B B
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
NMDA[0..63]<22>
NMAA[0..13]<22>
NDQMA[0..7]<22>
NDQSA[0..7]<22>
U6B
L25
DQA0
L26
DQA1
K25
DQA2
K26
DQA3
J26
DQA4
H25
DQA5
H26
DQA6
G26
DQA7
G30
DQA8
D29
DQA9
D28
DQA10
E28
DQA11
E29
DQA12
G29
DQA13
G28
DQA14
F28
DQA15
G25
DQA16
F26
DQA17
E26
DQA18
F25
DQA19
E24
DQA20
F23
DQA21
E23
DQA22
D22
DQA23
B29
DQA24
C29
DQA25
C25
DQA26
C27
DQA27
B28
DQA28
B25
DQA29
C26
DQA30
B26
DQA31
F17
DQA32
E17
DQA33
D16
DQA34
F16
DQA35
E15
DQA36
F14
DQA37
E14
DQA38
F13
DQA39
C17
DQA40
B18
DQA41
B17
DQA42
B15
DQA43
C13
DQA44
B14
DQA45
C14
DQA46
C16
DQA47
A13
DQA48
A12
DQA49
C12
DQA50
B12
DQA51
C10
DQA52
C9
DQA53
B9
DQA54
B10
DQA55
E13
DQA56
E12
DQA57
E10
DQA58
F12
DQA59
F11
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
SA002160E00(0301021300)
NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]
M10-P/(M9+X)
(2/6)
AA12/(AA13)
AA13/(AA12)
AA14/(NC)
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MEMORY INTERFACE
A
MVREFD
MVREFS/(NC)
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
DIMA0
DIMA1
NMAA0
E22
NMAA1
B22
NMAA2
B23
NMAA3
B24
NMAA4
C23
NMAA5
C22
NMAA6
F22
NMAA7
F21
NMAA8
C21
NMAA9
A24
NMAA10
C24
NMAA11
A25
NMAA12
E21
NMAA13
B20
C19
NDQMA0
J25
NDQMA1
F29
NDQMA2
E25
NDQMA3
A27
NDQMA4
F15
NDQMA5
C15
NDQMA6
C11
NDQMA7
E11
NDQSA0
J27
NDQSA1
F30
NDQSA2
F24
NDQSA3
B27
NDQSA4
E16
NDQSA5
B16
NDQSA6
B11
NDQSA7
F10
MVREFD
MVREFS
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA
NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#
NMRASA# <22>
NMCASA# <22>
NMWEA# <22>
NMCSA0# <22>
NMCSA1# <22>
NMCKEA <22>
NMCLKA0 <22>
NMCLKA0# <22>
NMCLKA1 <22>
NMCLKA1# <22>
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
D30
B13
B7
B8
MEMORY
INTERFACE A
MVREFD
0.1U_0402_10V6K
MVREFS
M10@0.1U_0402_16V4Z
Poped for M10-P
Depoped for
M9+X
C498
C503
1
2
1
2
(25 mil)
(25 mil)
+2.5VS
12
R475
1K_0402_1%
12
R478
1K_0402_1%
+2.5VS
12
R486
M10@1K_0402_1%
12
R487
M10@1K_0402_1%
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-A
星期三 七月
LA-2411
0.1
of
18 65, 07, 2004
1
Page 19
5
D D
4
3
2
1
MEMORY
INTERFACE B
NMDB[0..63]<23>
NMAB[0..13]<23>
NDQMB[0..7]<23>
NDQSB[0..7]<23>
C C
B B
NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
U6C
M10-P/(M9+X)
D7
DQB0
F7
(3/6)
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46
AA2
DQB47
AA6
DQB48
AA5
DQB49
AB6
DQB50
AB5
DQB51
AD6
DQB52
AD5
DQB53
AE5
DQB54
AE4
DQB55
AB2
DQB56
AB3
DQB57
AC2
DQB58
AC3
DQB59
AD3
DQB60
AE1
DQB61
AE2
DQB62
AE3
DQB63
SA002160E00(0301021300)
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12/(AB13)
AB13/(AB12)
AB14/(NC)
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
MEMORY INTERFACE B
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
MEMVMODE0
MEMVMODE1
DIMB0
DIMB1
MEMTEST
NMAB0
N5
NMAB1
M1
NMAB2
M3
NMAB3
L3
NMAB4
L2
NMAB5
M2
NMAB6
M5
NMAB7
P6
NMAB8
N3
NMAB9
K2
NMAB10
K3
NMAB11
J2
NMAB12
P5
NMAB13
P3
P2
NDQMB0
E6
NDQMB1
B2
NDQMB2
J5
NDQMB3
G3
NDQMB4
W6
NDQMB5
W2
NDQMB6
AC6
NDQMB7
AD2
NDQSB0
F6
NDQSB1
B3
NDQSB2
K6
NDQSB3
G1
NDQSB4
V5
NDQSB5
W1
NDQSB6
AC5
NDQSB7
AD1
NMRASB#
R2
NMCASB#
T5
NMWEB#
T6
NMCSB0#
R5
NMCSB1#
R6
NMCKEB
R3
NMCLKB0
N1
NMCLKB0#
N2
NMCLKB1
T2
NMCLKB1#
T3
R509 4.7K_0402_5%
C6
1 2
R510 4.7K_0402_5%
C7
1 2
E3
AA3
R511 47_0603_1%
C8
1 2
(15mil)
NMRASB# <23>
NMCASB# <23>
NMWEB# <23>
NMCSB0# <23>
NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>
NMCLKB0# <23>
NMCLKB1 <23>
NMCLKB1# <23>
+1.8VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-B
星期三 七月
LA-2411
0.1
of
19 65, 07, 2004
1
Page 20
5
4
3
2
1
U6D
M10-P/(M9+X)
VDDR1
(4/6)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
TPVDD
TPVSS
AVDD
A2VDD
A2VDD
A2VDDQ
A2VSSN
A2VSSN
A2VSSQ
AVSSN
AVSSQ
SA002160E00(0301021300)
VDDRH0
VDDRH1
VSSRH0
VSSRH1
MPVDD
MPVSS
PVDD
PVSS
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
I/O POWER
LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
LVDDR_18
LVDDR_18
LPVDD
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
VDD1DI
VDD2DI
VSS1DI
VSS2DI
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
AC11
AC20
AK12
AJ12
AH24
AG21
AH21
AF22
AH22
AJ21
AF23
AH23
AD24
B1
B30
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
D5
D8
D11
D13
D14
D17
D20
D23
D26
E27
F4
G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
T4
T7
T8
V4
V7
V8
D19
R4
H11
H20
L23
P8
Y23
Y8
Poped for
M10-P
1 2
1 2
1 2
+2.5VS
D D
C C
+2.5VS
R277 M10@0_0402_5%
R278 M10@0_0402_5%
R279
+1.5VS
M10@0_0805_5%
Poped for M10-P
Poped for M9+X
R282
B B
A A
+1.8VS
1 2
M9@0_0805_5%
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
F18
N6
F19
M6
A7
A6
AK28
AJ28
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
AC10
AC9
AD10
AD9
AG7
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
AE20
AE17
AF21
AE15
AJ20
AF20
AF15
AE19
AE16
AJ19
AE24
AE22
AE23
AE21
AF13
AF14
AG13
AG14
AH12
+LVDDR+VDDC1.5
+2.5VDDRH
+VDD_MEMPLL1.8
+VDD_PLL1.8
+3VS
+1.5VS
Poped for M10-P
R280 M10@0_0603_5%
1 2
1 2
R281 M9@0_0603_5%
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_PNLIO1.8
+VDD_PNLIO2.5
+VDD_PNLIO1.8
Poped for M9+X
C192
22U_1206_10V4Z
C197
22U_1206_10V4Z
+VDD_DAC2.5
C202
2.2U_0603_6.3V4Z
+VDD_PNLPLL1.8
C206
10U_0805_6.3V6M
+VDD_DAC1.8
C211
10U_0805_6.3V6M
+VDD_PNLIO1.8
C214
10U_0805_6.3V6M
+VDD_PNLIO2.5
C218
10U_0805_6.3V6M
+3VS
1
2
+1.5VS
1
2
1
2
1
2
1
2
1
2
1
2
C193
0.1U_0402_10V6K
C198
0.1U_0402_10V6K
(20 mil)
(20 mil)
C207
0.1U_0402_10V6K
(20 mil)
(20 mil)
(20 mil)
POWER
INTERFACE
0.1U_0402_10V6K
1
C194
2
L
0.1U_0402_10V6K
1
C199
2
1 2
CHB1608U301_0603
1
C203
0.1U_0402_10V6K
2
1
2
1 2
CHB1608U301_0603
1
C212
0.1U_0402_10V6K
2
1
C215
2
0.1U_0402_10V6K
1
C219
2
0.1U_0402_10V6K
SA052050010(MIC5205-2.8BM5), max:150mA
0.01U_0402_16V7K
1
C195
2
0.01U_0402_16V7K
1
1
C196
2
2
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
0.01U_0402_16V7K
1
C92
2
0.1U_0402_10V6K
L14
1 2
CHB1608U301_0603
1
C208
0.1U_0402_10V6K
2
L18
0.1U_0402_10V6K
C216
0.1U_0402_10V6K
C220
1
1
C200
2
2
+2.5VS
L16
+1.8VS
1
2
0.1U_0402_10V6K
1
2
MIC5205-2.8BM5_SOT23-5~D
C201
0.01U_0402_16V7K
+1.8VS
C217
L21
1 2
@CHB1608U301
U59
5
VOUT
2
GND
0.1U_0402_10V6K
1
C862
2
1U_0603_10V6K
10U_0805_6.3V6M
0.1U_0402_10V6K
1 2
CHB1608U301
1
2
1
C863
2
0.1U_0402_10V6K
+2.5VDDRH
C204
+VDD_PLL1.8
C209
+VDD_MEMPLL1.8
C213
L20
+2.5VS
1
VIN
4
PG
3
EN
0.1U_0402_10V6K
1
C865
2
(20 mil)
1
2
(20 mil)
1
2
(20 mil)
1
2
+1.8VS
0.1U_0402_10V6K
1
C549
@470P_0402_50V7K
2
1
C866
2
0.1U_0402_10V6K
CHB1608U301_0603
1
C205
0.1U_0402_10V6K
2
CHB1608U301_0603
1
C210
0.1U_0402_10V6K
2
1
2.2U_0603_6.3V4Z
C931
2
0.01U_0402_16V7K
1
C867
2
L15
1 2
L17
1 2
L19
1 2
CHB1608U301_0603
1
C868
2
0.1U_0402_10V6K
+2.5VS
+1.8VS
0.1U_0402_10V6K
1
1
C869
2
2
+1.8VS
As close as possible to related pin
+VDDC1.5 +LVDDR
1
1
2
C968
0.1U_0402_10V6K
2
0.1U_0402_10V6K
C967
+3VS
0.1U_0402_10V6K
1
C870
C871
2
0.1U_0402_10V6K
1
C969
2
1
2
1
C970
0.1U_0402_10V6K
2
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-A
星期三 七月
LA-2411
0.1
of
20 65, 07, 2004
1
Page 21
5
U6E
M10-P/(M9+X)
(5/6)
A10
VSS
A16
C224
C234
C245
AA30
AB23
AB24
AB27
AC12
AC14
AC16
AC18
AC4
AD12
AD16
AD18
AD25
AD30
AE27
AG11
AG15
AG18
AG22
AG27
AG5
AG9
AJ30
AK29
A2
A22
A29
AB1
AB4
AB7
AB8
AJ1
AK2
C1
C28
C3
C30
D10
D12
D15
D18
D21
D24
D25
D27
D4
D6
D9
E4
F27
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA002160E00(0301021300)
0.1U_0402_10V6K
1
2
1
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
C225
C235
C246
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
2
CORE POWER
C226
C236
C247
D D
C C
+VGA_CORE
1
+
47U_D2_6.3VM
B B
A A
2
+2.5VS
22U_1206_10V4Z
1
2
+2.5VS
22U_1206_10V4Z
1
2
C221
C232
C243
22U_1206_10V4Z
1
C223
2
1
C233
2
0.1U_0402_10V6K
1
C244
2
0.1U_0402_10V6K
1
2
22U_1206_10V4Z
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
2
4
H4
VSS
H8
VSS
H9
VSS
H12
VSS
H14
VSS
H18
VSS
H21
VSS
H23
VSS
H27
VSS
K1
VSS
K23
VSS
K24
VSS
K27
VSS
K30
VSS
K7
VSS
K8
VSS
L4
VSS
M30
VSS
M7
VSS
M8
VSS
N23
VSS
N24
VSS
N27
VSS
P4
VSS
R23
VSS
R24
VSS
R30
VSS
R7
VSS
R8
VSS
T1
VSS
T27
VSS
U23
VSS
U4
VSS
U8
VSS
V30
VSS
W23
VSS
W24
VSS
W27
VSS
W7
VSS
W8
VSS
Y4
VSS
G9
VSS
G12
VSS
G16
VSS
G18
VSS
G21
VSS
G24
VSS
0.1U_0402_10V6K
1
C227
2
1
C237
2
0.1U_0402_10V6K
1
C248
2
0.1U_0402_10V6K
1
C228
2
0.1U_0402_10V6K
0.01U_0402_16V7K
1
C238
2
0.01U_0402_16V7K
1
C249
2
POWER
INTERFACE
0.01U_0402_16V7K
1
2
1
2
1
2
1
C229
2
0.01U_0402_16V7K
C239
0.01U_0402_16V7K
C250
0.01U_0402_16V7K
C230
3
0.01U_0402_16V7K
1
C231
2
1
C222
+
150U_D2_6.3VM
2
2
+VGA_CORE
+VGA_CORE_CI
U6F
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
P18
VDDC
P19
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U17
VDDC
U18
VDDC
U19
VDDC
V12
VDDC
V13
VDDC
V14
VDDC
V17
VDDC
V18
VDDC
V19
VDDC
W12
VDDC
W13
VDDC
W14
VDDC
W17
VDDC
W18
VDDC
W19
VDDC
AB22
VDDC
AB9
VDDC
J10
VDDC
J12
VDDC
J14
VDDC
J15
VDDC
J16
VDDC
J17
VDDC
J19
VDDC
J21
VDDC
K22
VDDC
K9
VDDC
M22
VDDC
M9
VDDC
P22
VDDC
P9
VDDC
R22
VDDC
R9
VDDC
T22
VDDC
T9
VDDC
U22
VDDC
U9
VDDC
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
VDDC
SA002160E00(0301021300)
(20 mil)
1
C240
2
10U_0805_6.3V6M
M10-P/(M9+X)
(6/6)
M10-P&M9+X
COMMON
CORE POWER
M10-P
ONLY
M9+X
ONLY
0.1U_0402_10V6K
C241
1
0.1U_0402_10V6K
2
1
2
C242
As close as ppossible to related pin
AD15
VDDC
AD13
VDDC
AC17
VDDC
AC15
VDDC
AC13
VDDC
T12
VDDCI
M15
VDDCI
W16
VDDCI
R19
VDDCI
R12
VSS
R13
VSS
T13
VSS
R14
VSS
T14
VSS
N15
VSS
P15
VSS
R15
VSS
T15
VSS
U15
VSS
V15
VSS
W15
VSS
H16
VSS
M16
VSS
N16
VSS
P16
VSS
R16
VSS
T16
VSS
U16
VSS
V16
VSS
R17
VSS
T17
VSS
R18
VSS
T18
VSS
T19
VSS
AA22
VSS
AA9
VSS
J11
VSS
J13
VSS
J18
VSS
J20
VSS
J22
VSS
J9
VSS
L22
VSS
L9
VSS
N22
VSS
N9
VSS
W22
VSS
W9
VSS
L22
1 2
CHB1608U301
+VGA_CORE
+VGA_CORE_CI
480MIL
+VGA_CORE
JOPEN5
PAD-OPEN 4x4m
1 2
(12A,480mils ,Via NO.=24)
1
+1.2VS_VGA
As close as ppossible to related pin
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-B
星期三 七月
LA-2411
0.1
of
21 65, 07, 2004
1
Page 22
5
4
3
2
1
VGA DDR FOR CHANNEL A
C510
10U_0805_10V3M
+2.5VS+2.5VS
12
12
+2.5VS
1
2
R489
1K_0402_1%
R491
1K_0402_1%
NMCLKA1<18>
NMCLKA1#<18>
0.1U_0402_10V6K
1
C511
2
0.1U_0402_10V6K
1
2
C512
1
C513
2
10U_0805_10V3M
As close as ppossible to related pin
NMAA0
NMAA1
NMAA2
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NDQMA6
NDQMA7
NDQMA4
NDQMA5
NDQSA6
NDQSA7
NDQSA4
NDQSA5
VREF_2
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
K4D263238A-GC
1
C517
0.1U_0402_10V6K
2
NMCLKA1
10P_0402_50V8K
NMCLKA1#
NMCSA1#
C629
(25mil)
1
2
R626
56.2_0402_1%
R628
56.2_0402_1%
0.1U_0402_10V6K
1
C514
2
0.1U_0402_10V6K
U29
B11
VSSQB4VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
22U_1206_10V4Z
1
2
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
C515
D10
D11
VSSQ
1
C1122
2
0.1U_0402_10V6K
F10
VSSQE6VSSQE9VSSQF5VSSQ
G10
VSSQG5VSSQ
1
2
H10
VSSQH5VSSQ
C1124
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
1
C1125
0.1U_0402_10V6K
2
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
NMDA55
NMDA54
NMDA53
NMDA52
NMDA51
NMDA50
NMDA49
NMDA48
NMDA63
NMDA62
NMDA61
NMDA60
NMDA59
NMDA58
NMDA57
NMDA56
NMDA39
NMDA38
NMDA37
NMDA36
NMDA35
NMDA34
NMDA33
NMDA32
NMDA47
NMDA46
NMDA45
NMDA44
NMDA43
NMDA42
NMDA41
NMDA40
+2.5VS+2.5VS
+2.5VS
1
C504
D D
10U_0805_10V3M
2
0.1U_0402_10V6K
1
C505
2
1
2
0.1U_0402_10V6K
C506
10U_0805_10V3M
1
C507
2
1
C508
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C509
2
22U_1206_10V4Z
1
2
C1123
1
C1126
2
0.1U_0402_10V6K
As close as ppossible to related pin
(25mil)
NMCLKA0
C628
NMCLKA0#
NMCSA1#
NMAA[0..13]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
NMRASA#<18>
NMCASA#<18>
NMWEA#<18>
NMCSA0#<18>
NMCKEA<18>
1
2
R625
56.2_0402_1%
R627
56.2_0402_1%
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NDQMA2
NDQMA3
NDQMA0
NDQMA1
NDQSA2
NDQSA3
NDQSA0
NDQSA1
VREF_1
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
K4D263238A-GC
U28
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
D10
D11
VSSQ
F10
VSSQE6VSSQE9VSSQF5VSSQ
G10
VSSQG5VSSQ
H10
VSSQH5VSSQ
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
NMDA23
B7
NMDA22
C6
NMDA21
B6
NMDA20 NMAA3
B5
NMDA19
C2
NMDA18
D3
NMDA17
D2
NMDA16
E2
NMDA31
K13
NMDA30
K12
NMDA29
J13
NMDA28
J12
NMDA27
G13
NMDA26
G12
NMDA25
F13
NMDA24
F12
NMDA7
F3
NMDA6
F2
NMDA5
G3
NMDA4
G2
NMDA3
J3
NMDA2
J2
NMDA1
K2
NMDA0
K3
NMDA15
E13
NMDA14
D13
NMDA13
D12
NMDA12
C13
NMDA11
B10
NMDA10
B9
NMDA9
C9
NMDA8
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
NMAA[0..13]<18>
NMDA[0..63]<18>
NDQMA[0..7]<18>
NDQSA[0..7]<18>
C C
12
R488
1K_0402_1%
12
R490
1K_0402_1%
B B
1
2
NMCLKA0<18>
NMCLKA0#<18>
NMCSA1#<18>
C516
0.1U_0402_10V6K
10P_0402_50V8K
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA DDR FOR CHANNEL A
星期三 七月
LA-2411
0.1
of
22 65, 07, 2004
1
Page 23
5
4
3
2
1
VGA DDR FOR CHANNEL
+2.5VS
22U_1206_10V4Z
C518
1
2
0.1U_0402_10V6K
1
2
D D
C519
0.1U_0402_10V6K
1
C520
2
1
C521
2
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C522
2
1
C523
2
22U_1206_10V4Z
0.1U_0402_10V6K
1
C524
2
1
C525
2
0.1U_0402_10V6K
0.01U_0402_16V7K
1
C526
2
1
C527
0.01U_0402_16V7K
2
As close as ppossible to related pin
+2.5VS
1
2
22U_1206_10V4Z
C528
B
1
C531
2
0.01U_0402_16V7K
1
C529
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C530
2
As close as ppossible to related pin
0.01U_0402_16V7K
1
C532
2
1
C533
2
22U_1206_10V4Z
0.1U_0402_10V6K
1
C534
2
1
C535
2
0.1U_0402_10V6K
0.01U_0402_16V7K
1
C536
2
1
C537
0.01U_0402_16V7K
2
NMAB[0..13]<19>
NMDB[0..63]<19>
NDQMB[0..7]<19>
NDQSB[0..7]<19>
C C
+2.5VS
R495
1K_0603_1%
1 2
(25mil)
1
R496
1K_0603_1%
1 2
B B
C538
0.1U_0402_10V6K
2
NMCLKB0<19> NMCLKB1<19>
10P_0402_50V8K
NMCLKB0#<19>
NMCSB1#<19>
NMAB[0..13]
NMDB[0..63]
NDQMB[0..7]
NDQSB[0..7]
NMRASB#<19>
NMCASB#<19>
NMWEB#<19>
NMCSB0#<19>
NMCKEB<19>
R629
56.2_0402_1%
R631
1
C630
56.2_0402_1%
2
NMCLKB0# NMCLKB1#
NMCSB1# NMCSB1#
U30
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB0
NDQMB2
NDQMB1
NDQMB3
NDQSB0
NDQSB2
NDQSB1
NDQSB3
VREF_3
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
K4D263238A-GC
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
D10
D11
VSSQ
F10
VSSQE6VSSQE9VSSQF5VSSQ
G10
VSSQG5VSSQ
H10
VSSQH5VSSQ
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
NMDB7
B7
NMDB6
C6
NMDB5
B6
NMDB4
B5
NMDB3
C2
NMDB2
D3
NMDB1
D2
NMDB0
E2
NMDB23
K13
NMDB22NMAB9
K12
NMDB21
J13
NMDB20
J12
NMDB19
G13
NMDB18
G12
NMDB17
F13
NMDB16
F12
NMDB15
F3
NMDB14
F2
NMDB13
G3
NMDB12
G2
NMDB11
J3
NMDB10
J2
NMDB9
K2
NMDB8
K3
NMDB31
E13
NMDB30
D13
NMDB29
D12
NMDB28
C13
NMDB27
B10
B9
NMDB25
C9
NMDB24
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS
+2.5VS
NMCLKB1#<19>
R494
1K_0603_1%
1 2
R497
1K_0603_1%
1 2
1
2
NMCLKB1NMCLKB0
R632
10P_0402_50V8K
(25mil)
C539
0.1U_0402_10V6K
R630
1
C631
2
56.2_0402_1%
56.2_0402_1%
U31
NMAB0
NMAB1
NMAB2
NMAB3
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB5
NDQMB7
NDQMB4
NDQMB6
NDQSB5
NDQSB7
NDQSB4
NDQSB6
VREF_4
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
K4D263238A-GC
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
D10
D11
VSSQ
VSSQE6VSSQE9VSSQF5VSSQ
F10
G10
VSSQG5VSSQ
H10
VSSQH5VSSQ
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
NMDB47
B7
NMDB46
C6
NMDB45
B6
NMDB44
B5
NMDB43NMAB4
C2
NMDB42
D3
NMDB41
D2
NMDB40
E2
NMDB63
K13
NMDB62
K12
NMDB61
J13
NMDB60
J12
NMDB59
G13
NMDB58
G12
NMDB57
F13
NMDB56
F12
NMDB39
F3
NMDB38
F2
NMDB37
G3
NMDB36
G2
NMDB35
J3
NMDB34
J2
NMDB33
K2
NMDB32
K3
NMDB55
E13
NMDB54
D13
NMDB53
D12
NMDB52
C13
NMDB51
B10
NMDB50NMDB26
B9
NMDB49
C9
NMDB48
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA DDR FOR CHANNEL B
星期三 七月
LA-2411
0.1
of
23 65, 07, 2004
1
Page 24
A
1 1
2 2
B
+3VS
R1056 10K_0402_5%
R1111 10K_0402_5%
R962 10K_0402_5%
CLK_SB_48M<27>
CLK_SD_48M<31>
REFCLK1_NB<11>
CLK_14M_SIO<38>
CLK_SB_14M<27>
CLK_14M_CODEC<36>
R206 @33_0402_1%
R207 33_0402_1%
R996 68_0402_5%
R215 33_0402_1%
R997 33_0402_1%
R1068 33_0402_1%
C
C127 2.2P_0402_50V8C
C130 2.2P_0402_50V8C
SMB_CK_CLK2<14,15,27>
SMB_CK_DAT2<14,15,27>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VTT_PWRGD<27,46>
XTALIN_CLK
12
Y2
14.318MHZ
XTALOUT_CLK
+3VS
HB-1M2012-121JT03_0805
12
R963
@1M_0402_5%
SMB_CK_CLK2
SMB_CK_DAT2
24/48#
PCI33/66#
CLK_48M
CLK_SD
FS2
FS1
FS0
CLK_IREF
R218
475_0402_1%
1 2
L11
1 2
U5
6
XIN
7
XOUT
35
SCLK
34
SDATA
10
VTTPWRGD/PD#
45
CPU_STP#
12
PCI_STOP#
26
24/48#SEL
11
PCI33/66#SEL
27
48MHz_1
28
48MHz_0
4
FS2/REF2
3
FS1/REF1
2
FS0/REF0
38
IREF
D
+3V_CLK
42
8
Width=40 mils
10U_0805_6.3V6M
29
19
30
48
VDDSD
VDDPCI
VDD48M
VDDCPU
VDDAGP
GNDREF
GNDXTAL
GNDPCI
GNDPCI
GND48M
5
18
24
25
0.1U_0402_10V6K
1
C118
C119
2
13
9
1
VDDPCI
VDDREF
VDDXTAL
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDSD
GNDCPU
GNDAGP
ICS951402AGT_TSSOP48
46
41
33
1
2
VDDA
VSSA
E
0.1U_0402_10V6K
1
C120
2
0.1U_0402_10V6K
+3V_VDD
36
0.1U_0402_10V6K
VSSA
37
CLK_BCLK
40
CLK_BCLK#
39
CLK_NB
44
CLK_NB#
43
MEM_66M
47
AGP_66M
32
AGP_EXT_66M
31
FS3
14
FS4
15
16
17
20
21
22
23
0.1U_0402_10V6K
1
C121
C128
1
2
1
2
C123
C122
2
0.1U_0402_10V6K
10U_0805_6.3V6M
1
C129
2
0.1U_0402_10V6K
R195 33_0402_1%
1 2
R200 33_0402_1%
1 2
R201 33_0402_1%
1 2
R204 33_0402_1%
1 2
R205 33_0402_1%
1 2
R208 33_0402_1%
1 2
R210 M9_M10@33_0402_1%
1 2
R213 33_0402_1%
1 2
F
1
1
C124
0.1U_0402_10V6K
2
2
0.1U_0402_10V6K
1
1
C125
C126
2
2
CK_BCLK
R196 49.9_0402_1%
1 2
R197 49.9_0402_1%
1 2
CK_BCLK#
R202 49.9_0402_1%
1 2
R203 49.9_0402_1%
1 2
L12
1 2
CHB2012U121_0805
CK_BCLK <4>
CK_BCLK# <4>
CLK_NB_BCLK <11>
CLK_NB_BCLK# <11>
CLK_MEM_66M <11>
CLK_AGP_66M <11>
CLK_AGP_EXT_66M <17>
CLK_ALINK_SB <26>
CLK_BCLK
CLK_BCLK#
+3VS
G
R193 @0_0402_5%
R194 @0_0402_5%
H
CK_ITP <5>
CK_ITP# <5>
3 3
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
0 0 0 1 0
0 0 0 0 1
0 0 0 0 0
Note: 0 = PULL LOW
4 4
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
133
*
Spreaf OFF OR
Center spread +/-0.3%
BSEL1<5,13>
BSEL0<5,13>
133
100 100
10K_0402_5%
D83 RB751V_SOD323
D84 RB751V_SOD323
21
21
R219
+3V_CLK
12
12
R998
10K_0402_5%
FS1
FS0
FS2
FS3
FS4
PCI33/66#
12
R999
4.7K_0402_5%
12
R224
4.7K_0402_5%
12
R220
@10K_0402_5%
12
R225
10K_0402_5%
12
R221
@10K_0402_5%
12
R226
10K_0402_5%
12
R222
@10K_0402_5%
12
R227
10K_0402_5%
+3V_CLK
12
12
R223
10K_0402_5%
R228
@10K_0402_5%
A-LINK FREQ
PCI33/66# = HIGH
PCI33/66# = LOW 33MHZ
A
66MHZ
B
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C
D
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-2411
G
星期三 七月
0.1
of
24 65, 07, 2004
H
Page 25
5
LCD CONN
JP27
1
TXA2+<17>
TXA2-<17>
TXA1+<17>
TXA1-<17>
TXB2+<17>
TXB2-<17>
D D
TXA0+<17>
TXA0-<17>
TXACLK+<17>
TXACLK-<17>
TXB1+<17>
TXB1-<17>
TXA2+
TXA2-
TXA1+
TXA1-
TXB2+
TXB2-
TXA0+
TXA0-
TXACLK+
TXACLK-
TXB1+
TXB1-
+3VS
For M9/M110P/M11P
TXA2+_NB<11>
TXA2-_NB<11>
TXA1+_NB<11>
TXA1-_NB<11>
TXB2+_NB<11>
TXB2-_NB<11>
TXA0+_NB<11>
C C
TXA0-_NB<11>
TXACLK+_NB<11>
TXACLK-_NB<11>
TXB1+_NB<11>
TXB1-_NB<11>
TXA2+_NB
TXA2-_NB
TXA1+_NB
TXA1-_NB
TXB2+_NB
TXB2-_NB
TXA0+_NB
TXA0-_NB
TXACLK+_NB
TXACLK-_NB
TXB1+_NB
TXB1-_NB
+3VS
For internal AGP
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
M9-M10@JST BM40B-SRDS
JP28
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
NAGP@JST BM40B-SRDS
LCDVDD_A
2
2
4
4
6
6
8
8
TXB0+
10
10
TXB0-
12
12
14
14
TXBCLK+
16
16
TXBCLK-
18
18
20
20
DISPOFF#
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
LCDVDD_A
2
2
4
4
6
6
8
8
TXB0+_NB
10
10
TXB0-_NB
12
12
14
14
TXBCLK+_NB
16
16
TXBCLK-_NB
18
18
20
20
DISPOFF#
22
22
INVT_PWM
24
24
DAC_BRIG
26
26
28
28
DDC_CLK
30
30
DDC_DAT
32
32
34
34
36
36
38
38
40
40
INVPWR_B+
INVPWR_B+
AT LEAST 60 MIL
TXB0+ <17>
TXB0- <17>
TXBCLK+ <17>
TXBCLK- <17>
INVT_PWM <44>
DAC_BRIG <44>
DDC_CLK <10,17>
DDC_DAT <10,17>
AT LEAST 60 MIL
TXB0+_NB <11>
TXB0-_NB <11>
TXBCLK+_NB <11>
TXBCLK-_NB <11>
4
1
C618
2
10U_0805_10V3M
1000P_0402_50V8J
1
C619
2
DDC_CLK
DDC_DAT
27P_0402_50V8J
L41
1 2
KC FBM-L11-201209-221LMAT_0805
1
C620
0.01U_0402_50V7K
2
+3VS
R1007
2.2K_0402_5%
1 2
1 2
1
C993
1
2
2
R1008
2.2K_0402_5%
C994
27P_0402_50V8J
3
LCDVDD
0.1U_0402_10V6K
2
+3VS
12
R174
4.7K_0402_5%
R180
12
LCDVDD
12
13
D
S
2
DISPOFF#
1
C997
220P_0402_50V7K
2
+12VALW
2
G
13
22K
22K
R182
100K_0402_5%
2N7002_SOT23
Q12
DTC124EK_SOT23
BKOFF#<44>
1
C87
2
D16 RB751V_SOD323
+12VALW+5VS
1
C88
0.1U_0402_10V6K
2
21
1K_0402_1%
Q10
2N7002_SOT23
ENAVDD<10,17>
ENAVDD
R1115
1.2K_0402_5%
B+
+12VALW
R175
100K_0402_5%
R181
13
D
2
150K_0402_5%
G
Q11
S
SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V
1 2
KC FBM-L11-201209-221LMAT_0805
1 2
KC FBM-L11-201209-221LMAT_0805
1
C89
0.047U_0402_16V4Z
2
0.1U_0402_10V6K
1
INVPWR_B+
L2
L38
+3VS
13
D
2
G
Q9
S
SI2302DS 1N_SOT23
1
1
C90
2
2
SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V
1
C86
4.7U_0805_10V4Z
2
LCDVDD
C91
4.7U_0805_10V4Z
+3VS
D21
DAN217_SOT23
1
D22
DAN217_SOT23
1
D23
DAN217_SOT23
CRT CONNECTOR
3VDDCDA<11,17>
3VDDCCL<11,17>
B B
CRT_R<11,17>
CRT_G<11,17>
CRT_B<11,17>
CRT_VCC
135
CRT_HSYNC<11,17>
A A
CRT_VSYNC<11,17>
CRT_HSYNC
CRT_VSYNC
5
2 4
U57 74AHCT1G125GW
135
2 4
74AHCT1G125GW
U58
CRT_R
CRT_G
CRT_B
R1150
1 2
1K_0402
4
R1153 20_0402_5%
1 2
1 2
R1154 20_0402_5%
R185
75_0402_5%
L9
1 2
FBM-L10-160808-300LM-T
L10
1 2
FBM-L10-160808-300LM-T
1 2
10P_0402_50V8K
+5VS
DAN217_SOT23
3VDDCDA
3VDDCCL
L3 FCM2012C-800_0805
1 2
10P_0402_50V8K
1
C100
2
D42
1
R186
2
1 2
75_0402_5%
2
3
1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
L5 FCM2012C-800_0805
1 2
L6 FCM2012C-800_0805
1 2
1
C101
DAN217_SOT23
R187
75_0402_5%
2
1 2
D43
C102
10P_0402_50V8K
2
3
1
2
1
C103
22P_0402_25V8K
2
3
1
C104
2
22P_0402_25V8K
2
3
2
CRTL_R
CRTL_G
CRTL_B
1
C105
2
22P_0402_25V8K
CRT_HSYNCRFL
CRT_VSYNCRFL
2
+5VS CRT_VCC
R_CRT_VCC
C108
D17
2 1
RB411D_SOT23
4.7K_0402_5%
1
1
C109
2
2
10P_0402_50V8K
Title
Size Document Number Rev
Custom
Date: Sheet
1
3
10P_0402_50V8K
F1
21
1
FUSE_1A
C97
0.1U_0402_10V6K
R1117
220P_0402_25V8K
R1118
4.7K_0402_5%
1
C116
2
220P_0402_25V8K
2
C117
1
2
CRT_VCC
D
1 3
2
SUYIN_7849S-15G2T-HC
JP6
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
Q13
S
2N7002 1N_SOT23
G
Q14
D
S
1 3
2N7002 1N_SOT23
R191
G
2
4.7K_0402_5%
3VDDCDA
Compal Electronics, Inc.
LCD,CRT,TV-OUT & Inverter BD CONN.
星期三 七月
LA-2411
25 65, 07, 2004
1
3VDDCCL
R192
4.7K_0402_5%
+3VS
0.1
of
Page 26
5
12
R132
470_0402_5%
2
12
R1000
@470_0402_5%
2
12
12
12
12
12
12
12
12
12
A_AD[0..31]
A_CBE#[0..3]
SBCLK_STP#
+3VS
R131
330_0402_5%
H_CPUFERR#
CPURSTIN#
A_SERR#
PULL DOWN FOR S3
CLK_ALINK_SB
12
R134
10_0402_5%
C77
15P_0402_50V8J
+3VS
12
R40
1K_0402_5%
+3VS
12
R921
4.7K_0402_5%
PCI_PIRQB#<31>
R125 8.2K_0402_5%
A_AD[0..31]<10,13>
A_CBE#[0..3]<10,13>
+VCC_CORE
D D
Q5 MMBT3904_SOT23
H_FERR#<5>
H_RESET#<5,8>
+3VS
CPUCLK_STP#<5,11,54>
C C
H_PWRGOOD
**
H_CPUSLP#
H_SMI#
H_STPCLK#
H_IGNNE#
H_A20M#
H_INIT#
H_INTR
H_NMI
3 1
+VCC_CORE
Q98 @MMBT3904_SOT23
3 1
R946 8.2K_0402_5%
C1068 220P_0402_50V7K
C1067 220P_0402_50V7K
C1066 220P_0402_50V7K
C1065 220P_0402_50V7K
C1064 220P_0402_50V7K
C956 220P_0402_50V7K
C617 220P_0402_50V7K
C78 220P_0402_50V7K
C79 220P_0402_50V7K
PLACE CLOSE TO CPU SOCKET
+VCC_CORE
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
B B
H_STPCLK#
H_IGNNE#
A A
R149 200_0402_5%
1 2
R150 200_0402_5%
1 2
R151 200_0402_5%
1 2
R152 200_0402_5%
1 2
R153 200_0402_5%
1 2
R154 200_0402_5%
1 2
R156 200_0402_5%
1 2
R158 200_0402_5%
1 2
R171 20M_0603_5%
1 2
1
IN
1
C81
12P_0402_50V8J
32.768KHZ_12.5P_1TJS125DJ2A073
2
2
5
DPRSLPVR<54>
RTCX1RTCX2
4
Y1
OUT
NC3NC
C82
12P_0402_50V8J
R1001
47K_0402_5%
1 2
R1002 47K_0402_5%
1 2
12
R172
1
@20M_0603_5%
2
R1064 10K_0402_5%
R1065 10K_0402_5%
R1067 1K_0402_1%
0.1U_0402_10V6K
4
CLK_ALINK_SB<24>
A_STROBE#<10>
A_DEVSEL#<10>
A_ACAT#<10>
A_END#<10>
A_PAR<10,13>
A_OFF#<10>
A_SBREQ#<10>
A_SBGNT#<10>
PCI_PIRQA#<10,17,31,34>
PCI_PIRQC#<41>
PCI_PIRQD#<33,41>
R169
330_0402_5%
H_PWRGOOD<5>
H_INTR<5>
H_NMI<5>
H_INIT#<5>
H_SMI#<5>
H_CPUSLP#<5>
H_IGNNE#<5>
H_A20M#<5>
H_STPCLK#<5>
1 2
1 2
1 2
C872
R966
10K_0402_5%
NBRST# NB_RST#
SN74LVC14APWLE_TSSOP14
4
CLK_ALINK_SB
NBRST#
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
SBCLK_STP#
PCICLK_STP#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
+3VS
RTCX1
RTCX2
CPURSTIN#
H_A20M#
H_CPUFERR#
GPIO0
SB_APIC_D0
SB_APIC_D1
+3VALW
1
2
PCIRST#
3
12
SN74LVC14APWLE_TSSOP14
+3VALW +3VALW
14
U45E
P
11
G
7
B22
R22
H22
P23
L23
N23
N22
M23
M22
K22
M21
M20
L21
K21
L20
N21
K23
K20
F23
G21
F20
H21
F22
F21
G20
E21
E20
D23
D22
E22
D20
C23
D21
C22
L22
J23
G22
E23
H20
J21
G23
H23
J20
J22
P22
B21
B20
N20
R23
C20
P20
B23
P21
AC12
AC11
B18
E4
B17
B16
C17
C16
F19
D17
D18
E19
E16
E17
E18
C19
C18
B19
14
U45B
P
O4I
G
7
14
13
O10I
7
U3A
PCICLKF
A_RST#
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
CPU_STP#/DPSLP#
PCI_STP#
A_INTA#
INTB#
INTC#
INTD#
X1
X2
CPURSTIN#
CPU_PWRGD
INTR/LINT0
NMI/LINT1
INIT
SMI#
SLP#
IGNNE#
A20M#
FERR#
STPCLK#
SSMUXSEL/GPIO0
DPRSLPVR
APIC_D0
APIC_D1
APIC_CLK
South bridge SB200
9
U45F
P
O12I
G
SN74LVC14APWLE_TSSOP14
A-LINK INTERFACE
14
U45D
P
PCI_RST#
O8I
G
SN74LVC14APWLE_TSSOP14
7
3
Layout note:
Trace length of PCI_CLK_R + PCI_CLK_FB should
be less than 200 mils.
PCI_1394
SB200 SB
Part 1 of 3
PCI CLKS
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24/RTC_AD7
AD25/RTC_AD6
AD26/RTC_AD5
AD27/RTC_AD4
AD28/RTC_AD3
AD29/RTC_AD2
AD30/RTC_AD1
AD31/RTC_AD0
CBE#0/ROMA10
CBE#1/ROMA1
CBE#2/ROMWE#
PCI INTERFACE
CBE#3/RTC_RD#
DEVSEL#/ROMA0
TRDY#/ROMOE#
REQ#3/PDMAREQ0#
REQ#4/PLLBP33/PDMAREQ1#
XTAL
CPU
RTC
GNT#3/PDMAGNT0#
GNT#4/PLLBP50/PDMAGNT1#
GPIO1/ROMCS#
LPC
USBOC5#/GPM1
RTC_ALE/USBOC4#/GPIO3
RTC_WR#/RTC_CLKOUT
RTC_CS#/USBOC3#/GPIO2
PCI_RST# <11,30,31,33,34,38,41,44>
NB_RST# <8,17>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK_FB
PCIRST#
AD8/ROMA9
AD9/ROMA8
FRAME#
IRDY#
STOP#
PERR#
SERR#
REQ#0
REQ#1
REQ#2
GNT#0
GNT#1
GNT#2
CLKRUN#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#0
LDRQ#1
SERIRQ
VBAT
RTC_GND
PAR
B15
D16
A14
A15
A16
A17
D15
A18
A19
C15
B1
C1
A1
D2
B2
C2
A2
D3
C3
A3
D4
B4
C4
A4
D5
B5
C8
D8
B8
A8
C9
D9
B9
A9
C10
B10
D11
A10
C11
B11
D12
A11
B3
C5
A7
D10
B7
A6
C7
D7
A5
B6
C6
D6
B12
C12
D13
A12
C13
A13
B13
C14
D14
B14
A20
AB5
Y14
AA14
AB14
AA13
AB13
AC14
Y13
AC13
AA2
AB7
AB8
AC8
AC10
AB11
R122 39_0402_5%
PCI_LAN
R123 39_0402_5%
PCI_PCM
R124 39_0402_5%
PCI_MINI
R126 39_0402_5%
PCI_EC
R127 39_0402_5%
PCI_SIO
R128 39_0402_5%
PCI_CLK_R
R130 39_0402_5%
PCI_CLK_FB
PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#
GPIO1
R1151
10K_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
SIRQ
OVCUR#5
OVCUR#4
OVCUR#3
+SB_VBAT
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI_AD[0..31]
PCI_CBE#[0..3]
PCI_FRAME# <31,33,34,41>
PCI_DEVSEL# <31,33,34,41>
PCI_IRDY# <31,33,34,41>
PCI_TRDY# <31,33,34,41>
PCI_PAR <31,33,34,41>
PCI_STOP# <31,33,34,41>
PCI_PERR# <31,33,34,41>
PCI_SERR# <31,33,41>
PCI_REQ#0 <34>
PCI_REQ#1 <33>
PCI_REQ#2 <31>
PCI_REQ#3 <41>
PCI_REQ#4 <41>
PCI_GNT#0 <34>
PCI_GNT#1 <33>
PCI_GNT#2 <31>
PCI_GNT#3 <41>
PCI_GNT#4 <41>
PCI_CLKRUN# <33,38,41,44>
LPC_AD0 <38,44>
LPC_AD1 <38,44>
LPC_AD2 <38,44>
LPC_AD3 <38,44>
LPC_FRAME# <38,44>
LPC_DRQ#1 <38>
SIRQ <31,38,44>
OVCUR#3 <35>
2
C76 @22P_0402_50V8J
PCI_AD[0..31] <29,31,33,34,41>
PCI_CBE#[0..3] <31,33,34,41>
12
+3V
1U_0603_10V4Z
2
1 2
+SB_VBAT
C80
CLK_PCI_1394 <34>
CLK_PCI_LAN <33>
CLK_PCI_PCM <31>
CLK_PCI_MINI <41>
CLK_PCI_EC <44>
CLK_PCI_SIO <38>
1
2
R168 220_0805_5%
1 2
W=20mils
Title
Size Document Number Rev
Date: Sheet
1
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
8.2K _8P4R_0804_5%
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_FRAME#
8.2K _8P4R_0804_5%
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
8.2K _8P4R_0804_5%
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
8.2K _8P4R_0804_5%
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
8.2K _8P4R_0804_5%
PCI_REQ#4
8.2K_0402_5%
PCI_GNT#4
8.2K_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
100K_1206_8P4R_5%
SIRQ
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
PCI_CLKRUN#
GPIO0
OVCUR#3
OVCUR#4
OVCUR#5
10K_0804_8P4R_5%
R146
4.7K_0402_5%
R1155 10K_0402_5%
R1300 10K_0402_5%
R1157 10K_0402_5%
R1059 10K_0402_5%
1 2
RTC Battery
BATT1
-+
RTCBATT
+RTCVCC
R1298
1 2
220_0805_5%
No short
JOPEN1
1 2
Place J1 close
to DDR-SODIMM
+RTCBATT
12
1
C1128
0.1U_0402_16V4Z
2
+RTCBATT
3
Compal Electronics, Inc.
SB200M(1/4)- PCI/CPU/LPC
星期四 七月
LA-2411
1
RP14
4 5
3 6
2 7
1 8
RP15
4 5
3 6
2 7
1 8
RP16
4 5
3 6
2 7
1 8
RP17
4 5
3 6
2 7
1 8
RP18
4 5
3 6
2 7
1 8
RP21
4 5
3 6
2 7
1 8
RP138
1 8
2 7
3 6
4 5
12
12
12
1
2
26 65, 15, 2004
+3VS
R137
R138
12
+3V
D93
BAS40-04_SOT23
CHGRTC
0.1
of
Page 27
5
4
3
2
1
SB_EC_THERM#
SB_PM_BATLOW#
CLK_SB_48M<24>
D D
AC97_BITCLK
12
R71
@10_0402_5%
C74
@15P_0402_50V8J
CLK_SB_14M
12
R92
@10_0402_5%
C75
@15P_0402_50V8J
C C
RP111
1 8
2 7
3 6
4 5
RP112
RP113
OVCUR#0
OVCUR#1
B B
A A
OVCUR#2
IDERST_HD#<30>
IDERST_CD#<30>
+3VS
R934 1K_0603_5%
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
15K_1206_8P4R_5%
R1301 10K_0402_5%
R1302 10K_0402_5%
R1303 10K_0402_5%
+3VS
+3VS
1 2
12
12
1 2
AGP_STP#<10,17>
CPU_GHI#<5>
R120 10K_0402_5%
1 2
IDERST_HD#
R121 10K_0402_5%
1 2
IDERST_CD#
5
OVCUR#0<35>
USB20P5+<42>
USB20P5-<42>
USB20P3+<35>
USB20P3-<35>
USB20P2+<35>
USB20P2-<35>
USB20P1+<35>
USB20P1-<35>
USB20P0+<35>
USB20P0-<35>
USB20P4+
USB20P4USB20P5USB20P5+
USB20P3USB20P3+
USB20P2USB20P2+
USB20P1+
USB20P1USB20P0+
USB20P0-
+3V
R112 100K_0402_5%
R951 10K_0402_5%
D
1 3
Q89 2N7002 1N_SOT23
12
AGP_STP#
RB751V_SOD323
2 1
D13 RB751V_SOD323
2 1
D14 RB751V_SOD323
G
2
IDERSTHD#
IDERSTCD#
S
AGP_BUSY#AGP_BUSY#_R
D11 RB751V_SOD323
D77
R1293 @0_0402_5%
R63
12.4K_0603_1%
MII_TXD3<29>
MII_TXD2<29>
MII_TXD1<29>
MII_TXD0<29>
MII_TXEN<29>
R947 10K_0402_5%
+3V
R950 10K_0402_5%
SB_EEDO<29>
SB_EECLK<29>
EC_RSMRST#<44>
CLK_SB_14M<24>
R948 10K_0402_5%
+3V
EC_FLASH#<45>
OVCUR#2<35>
32KHZ_S5_OUT<29>
OVCUR#1<35>
SB_SPKR<37>
2 1
2 1
@10K_0402_5%
AGP_BUSY# <10,17>
R952
12
OSCLIN
USB_RCOMP
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
12
12
SB_EEDO
SB_EECLK
EC_RSMRST#
CLK_SB_14M
12
EC_FLASH#
OVCUR#2
32KHZ_S5_OUT
OVCUR#1
SB_SPKR
AGP_STP#_R
AGP_BUSY#_R
GHI
VGATE
IDERSTHD#
IDERSTCD#
R1003
33_0402_5%
1 2
4
OVCUR#0
USB20P5+
USB20P5-
USB20P4+
USB20P4-
USB20P3+
USB20P3-
USB20P2+
USB20P2-
USB20P1+
USB20P1-
USB20P0+
USB20P0-
VTT_PWRGD <24,46>
U3B
P3
USBCLK/CLK48
R1
USB_RCOMP
P1
USB_VREFOUT
N4
USB_ATEST1
N3
USB_ATEST0
P4
USBOC0#/GPM7
M2
USB_HSDP5+
M1
USB_FLDP5+
N2
USB_HSDM5-
N1
USB_FLDM5-
L4
USB_HSDP4+
L3
USB_FLDP4+
M4
USB_HSDM4-
M3
USB_FLDM4-
K2
USB_HSDP3+
K1
USB_FLDP3+
L2
USB_HSDM3-
L1
USB_FLDM3-
H2
USB_HSDP2+
H1
USB_FLDP2+
J2
USB_HSDM2-
J1
USB_FLDM2-
G3
USB_HSDP1+
J3
USB_FLDP1+
H3
USB_HSDM1-
K3
USB_FLDM1-
F1
USB_HSDP0+
F2
USB_FLDP0+
G1
USB_HSDM0-
G2
USB_FLDM0-
R5
MCOL
W1
MCRS
V4
MDCK
V2
MDIO
T1
RX_CLK
T3
RXD3
U2
RXD2
T5
RXD1
W4
RXD0
T2
RX_DV
U1
RX_ERR
T4
TX_CLK
U4
TXD3
V1
TXD2
U3
TXD1
V3
TXD0
W2
TX_EN
W3
PHY_PD
U5
PHY_RST#
Y7
CLK_25M
P2
EE_CS
R3
EE_DI
R2
EE_DO
R4
EE_CK
AB9
RSMRST#
A23
OSC_IN
W6
SIO_CLK
AB2
BLINK/GPM0
AA3
FANOUT1/USBOC2#/GPM2
W11
32KHZ_IN/GPM3
AB1
USBOC1#/GPM4
Y4
SPEAKER/GPM5
AA1
FANOUT0/GPM6
AC1
GPIO_X0/AGP_STP#
AC6
GPIO_X1/AGP_BUSY#
AC2
GPIO_X2/GHI#
AC3
GPIO_X3/VGATE
AC4
GPIO_X4
AC5
GPIO_X5
South bridge SB200
SB200 SB
Part 2 of 3
ACPI / WAKE UP EVENTS
USB INTERFACE
PRIMARY ATA 66/100
ETHERNET MIIEEPROMCLK / RST
SECONDARY ATA 66/100
GPIOGPIO_XTRA
SB_EC_THERM#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST1
TEST0
PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#
SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT
3
AB4
AC9
AC7
AA11
AB10
AA10
Y11
C21
Y10
AA5
AA6
Y5
AA4
AB3
Y6
W5
Y8
AA7
AB6
AA12
W12
Y12
AB12
AA8
AB17
AC16
AB15
AB16
AC15
Y16
AA17
AA16
AC17
Y15
AA15
AC18
AA18
AC19
AA19
AC20
AA20
AC21
AB21
AA21
Y20
AB20
Y19
AB19
Y18
AB18
Y17
AA23
AA22
AC23
Y21
AB23
Y22
W21
Y23
W20
AC22
AB22
W23
V21
V23
U21
U23
T21
T23
R21
R20
T22
T20
U22
U20
V22
V20
W22
E1
E2
Y1
Y2
Y3
E3
V5
E5
4.7K_0402_5%
SUS_STAT#
SB_PM_BATLOW#
LPC_PME#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
PCI_ACT_REQ#
SUS_STAT#
SB_TEST1
SB_TEST0
SB_GA20
SB_KBRST#
SB_AC_IN
SB_EC_SWI#
LPC_SMI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
PWR_STRP
IDEIORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3
IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15
IDEIORDYB
IDEIRQB
IDESAB0
IDESAB1
IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B
IDECS#B1
IDECS#B3
IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15
AC97_SDOUT_R
AC97_SYNC_R
SPDIF_OUT
+2.5V
+2.5V
R1185
1 2
Q3 M10@MMBT3904_SOT23
3 1
SLP_S3# <44>
SLP_S5# <44>
PWRBTN_OUT# <44>
SB_PWRGD <46>
SMB_CK_CLK2 <14,15,24>
SMB_CK_DAT2 <14,15,24>
PWR_STRP <29>
IDEIORDYA <30>
IDEIRQA <30>
IDESAA0 <30>
IDESAA1 <30>
IDESAA2 <30>
IDEDACK#A <30>
IDEREQA <30>
IDEIOR#A <30>
IDEIOW#A <30>
IDECS#A1 <30>
IDECS#A3 <30>
IDEDA[0..15] <30>
IDEIORDYB <30>
IDEIRQB <30>
IDESAB0 <30>
IDESAB1 <30>
IDESAB2 <30>
IDEDACK#B <30>
IDEREQB <30>
IDEIOR#B <30>
IDEIOW#B <30>
IDECS#B1 <30>
IDECS#B3 <30>
IDEDB[0..15] <30>
R117 33_0402_5%
R119 33_0402_5%
SPDIF_OUT <29>
M10@4.7K_0402_5%
R1186
1 2
2
AC97_BITCLK
AC97_SDOUT
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
AC97_SYNC
AC97_RST#
TALERT#/ETH_TALERT#
PME#/EXT_EVNT0#
RI#/EXT_EVNT1#
PCI_REQACT#
GA20_IN/GEVNT0#
KB_RST#/GEVNT1#
SMB_ALERT#/GEVNT2#
LPC_PME#/GEVNT3#
LPC_SMI#/GEVNT4#
GEVENT5#/ETH_VALERT#
GEVENT6#/ETH_FALERT#
GEVENT7#/ETH_CALERT#
GPOC0#/SCL0
GPOC1#/SDA0
GPOC2#/SCL1
GPOC3#/SDA1
RTC_IRQ#/PWR_STRP
AC97
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SB_EC_SWI#
SB_GA20 GA20
SB_KBRST#
SB_EC_SMI#
SB_SCI# SC I#
+3VS
12
M10@10K_0402_5%
R1187
AGP_SUS_STAT# <17>
2
D2 RB751V_SOD323
2 1
D3 RB751V_SOD323
2 1
D4 RB751V_SOD323
2 1
D5 RB751V_SOD323
2 1
D6 RB751V_SOD323
2 1
D7 RB751V_SOD323
2 1
D8 RB751V_SOD323
2 1
D9 RB751V_SOD323
2 1
D10 RB751V_SOD323
2 1
+3V
12
R1183
10K_0402_5%
1
C1010
0.1U_0402_10V6K
2
SUS_STAT#
AC97_BITCLK <36,42>
AC97_SDOUT <29,36,42>
AC97_SDIN0 <36>
AC97_SDIN1 <42>
AC97_SYNC <29,36,42>
AC97_RST# <36,42>
X2 48MHZ_4P_FN4800002
4
OUT
VDD
1
GND
OE
+2.5V
4.7K_0402_5%
R1188
1 2
2
Q4 MMBT3904_SOT23
3 1
Title
Size Document Number Rev
Date: Sheet
星期三 七月
EC_THERM#
PM_BATLOW#
EC_SWI#
KBRST#
ACINSB_AC_IN
EC_SMI#
LID_OUT#SB_LID_OUT#
3
2
GHI
AGP_STP#_R
AGP_BUSY#_R
SB_GA20
SB_KBRST#
LPC_PME#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
SB_EC_SWI#
LPC_SMI#
SB_AC_IN
PCI_ACT_REQ#
PWRBTN_OUT#
SLP_S3#
SLP_S5#
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
AC97_RST#
AGP_STP#
AGP_BUSY#
SB_TEST0
SB_TEST1
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
AC97_BITCLK
1 2
R1184
0_0402_5%
OSCLIN
+2.5V
R69
4.7K_0402_5%
1 2
R68
10K_0402_5%
1 2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
RP11 10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP12 2.2K_0804_8P4R_5%
R111 8.2K_0402_5%
1 8
2 7
3 6
4 5
RP140 8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
RP13 8.2K _8P4R_0804_5%
R1176 8.2K_0402_5%
Compal Electronics, Inc.
SB200M(2/4) - IDE/USB/MII
LA-2411
04
1
EC_THERM# <44>
PM_BATLOW# <44>
EC_SWI# <44>
GA20 <44>
KBRST# <44>
ACIN <44,48,51>
EC_SMI# <44>
SCI# <44>
LID_OUT# <44>
NB_SUS_STAT# <8>
+3V
RP107
10K_0804_8P4R_5%
RP108
10K_0804_8P4R_5%
RP109
10K_0804_8P4R_5%
RP110
10K_0804_8P4R_5%
+3VALW
+3VS
+3V
+3VS
of
27 65, 07, 20
0.1
Page 28
5
4
3
2
1
+3VS +3VS
0.1U_0402_10V6K
1
C34
C33
2
0.1U_0402_16V7Z
0.1U_0402_16V7Z
C883
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
1
2
0.1U_0402_10V6K
ATI request
+3V_AVDDC
C887
ATI request
+3V_AVDDUSB
1
+
C888
47U_B_6.3VM
2
ATI request
+2.5V_AVDDCK
1
C889
2
0.1U_0402_10V6K
1
C35
C36
2
0.1U_0402_10V6K
+3VS
1
C873
2
0.1U_0402_16V7Z
+2.5VS
1
C878
2
C885
0.1U_0402_10V6K
1
1
C37
C38
2
2
0.1U_0402_10V6K
ATI request
0.1U_0402_16V7Z
1
C874
0.1U_0402_16V7Z
1
C875
2
2
ATI request
1
C880
C879
2
0.1U_0402_16V7Z
ATI request
CLOSE TO
+2.5V
L6,H6,J6
C886
0.1U_0402_16V7K
+3VS
RB751V_SOD323
1
1
2
2
1
C876
2
0.1U_0402_16V7Z
1
1
2
2
D90
2 1
1U_0603_10V6K
C39
0.1U_0402_10V6K
1
C877
0.1U_0402_16V7Z
2
C881
0.1U_0402_16V7Z
C966
0.1U_0402_16V7K
+5VS
12
R1114
1K_0402_5%
1
C843
2
+2.5V
+3V_AVDDC
+3V
+3V_AVDDUSB
+2.5VS
+2.5V_AVDDCK
+2.5VALW
+3VALW
0.1U_0402_10V6K
+2.5VS
1
1
C69
2
2
1
C27
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C44
2
2
1
C53
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
2
C45
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C24
D D
C C
22U_1206_16V4Z_V1
22U_1206_16V4Z_V1
C23
22U_1206_16V4Z_V1
C40
C49
22U_1206_16V4Z_V1
2
+2.5VS
1
2
+2.5V
0.1U_0402_10V6K
1
C50
2
C25
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C42
C41
2
0.1U_0402_10V6K
1
1
C51
2
2
0.1U_0402_10V6K
1
C26
2
1
C43
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C52
2
1
C28
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C46
2
0.1U_0402_10V6K
1
C29
2
1
C47
2
0.1U_0402_10V6K
1
C30
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C32
C31
2
1
C48
0.1U_0402_10V6K
2
ATI request
+3V
0.1U_0402_10V6K
1
C55
R60
R61
R62
C54
2
+3V_AVDDC
1
C59
1U_0603_10V6K
2
+3V_AVDDUSB
0.1U_0402_10V6K
1
C63
C62
2
+2.5V_AVDDCK
1
C71
1U_0603_10V6K
2
22U_1206_16V4Z_V1
1 2
+3V
FBM-10-201209-260-T_0805
B B
1 2
+3V
FBM-10-201209-260-T_0805
22U_1206_16V4Z_V1
1 2
+2.5VS
FBM-10-201209-260-T_0805
A A
0.1U_0402_10V6K
1
1
C56
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C64
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C57
2
1
C60
0.1U_0402_10V6K
2
1
C66
C65
2
0.1U_0402_10V6K
0.01U_0402_16V7Z
1
1
C982
C72
2
2
1
C58
0.1U_0402_10V6K
2
0.01U_0402_16V7Z
1
C980
2
0.1U_0402_10V6K
1
1
C67
C68
2
2
0.1U_0402_10V6K
1
C96
C983
2
470P_0402_50V7K
1000P_0402_16V7K
0.1U_0402_16V7K
1
C981
2
1000P_0402_16V7K
680P_0402_50V7K
1
1
C93
2
2
680P_0402_50V7K
1
1
C98
2
2
680P_0402_50V7K
C882
1000P_0402_50V7K
1
C95
C94
2
470P_0402_50V7K
1
C99
2
+3V
10U_0805_10V6K
1
2
22U_1206_16V4Z_V1
E11
E12
E15
E7
E8
F11
F12
F15
F16
F17
F7
F8
G18
G19
H18
H19
M18
M19
N18
N19
T18
T19
U18
U19
V17
V18
W17
W18
J10
J11
J13
J14
K15
K9
L15
L9
N15
N9
P15
P9
R10
R11
R13
R14
P6
R6
V13
W13
V12
L6
H6
J6
P5
T6
U6
V9
V10
V11
W9
W10
F4
J4
K5
F3
K4
L5
D19
D1
A21
Y9
AA9
C70
0.1U_0402_10V6K
U3C
SB200 SB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
VDD_USB
VDD_USB
VDD_USB
AVDDC
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
AVDDTX0
AVDDTX1
AVDDTX2
AVDDRX0
AVDDRX1
AVDDRX2
VREF_CPU
5V_VREF
AVDD_CK
S5_2.5V
S5_3.3V
South bridge SB200
Part 3 of 3
POWER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_USB
VSS_USB
AVSSC
AVSSRX2
AVSSRX1
AVSSRX0
AVSSTX2
AVSSTX1
AVSSTX0
AVSSCK
E10
E13
E14
E6
E9
F10
F13
F14
F18
F6
F9
G6
J12
J15
J18
J19
J9
K10
K11
K12
K13
K14
K18
K19
L10
L11
L12
L13
L14
L18
L19
M10
M11
M12
M13
M14
M15
M6
M9
N10
N11
N12
N13
N14
N6
P10
P11
P12
P13
P14
P18
P19
R12
R15
R18
R19
R9
V14
V15
V16
V19
V6
V7
V8
W14
W15
W16
W19
W7
W8
H5
G5
N5
M5
J5
G4
K6
H4
F5
A22
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(3/4) - PWR
LA-2411
星期三 七月
0.1
of
28 65, 07, 2004
1
Page 29
5
D D
4
3
2
1
+3VALW +3V +3V
+3VS
12
12
R34
10K_0402_5%
R47
@10K_0402_5%
MANUAL
PWR ON
DEFAULT
PWR
ON
R953
10K_0402_5%
R35
@10K_0402_5%
12
R48
10K_0402_5%
IGN DEBUG SPEEDSTEP FREQLTCH
EEDO
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
EECK
ROM ON
PCI BUS
ROM ON
LPC
BUS
DEFAULT
R36
@10K_0402_5%
12
R49
10K_0402_5%
High : ENE910
Low : NS591L
C C
PWR_STRP<27>
SB_EEDO<27>
SB_EECLK<27>
AC97_SYNC<27,36,42>
AC97_SDOUT<27,36,42>
SPDIF_OUT<27>
MII_TXEN<27>
MII_TXD3<27>
MII_TXD2<27>
MII_TXD1<27>
MII_TXD0<27>
32KHZ_S5_OUT<27>
B B
REQUIRED SYSTEM STRAPS
STRAP
HIGH
STRAP
LOW
+3VS
1 2
AC_SYNC
INIT ACTIVE
HIGH
INIT ACTIVE
LOW (PIII)
DEFAULT
R37
@10K_0402_5%
R50
10K_0402_5%
+3VS +3VS
R38
@10K_0402_5%
12
R51
10K_0402_5%
33MHz NB
BUS
HI SPEED
A-LINK
DEFAULT
SIO 24MHzUSE
SIO 48MHzAUTO
DEFAULT
R39
@10K_0402_5%
12
R52
10K_0402_5%
CPU_STP#
ENABLE
SPEED
STEP
DISABLE
SPEED
STEP
DEFAULT
+3V +3V +3V +3V +3V
12
R41
10K_0402_5%
R54
@10K_0402_5%
TX_EN
DISABLE
CPU FREQ
SETTING
DEFAULT
ENABLE CPU
FREQSETTING
R42
10K_0402_5%
R55
@10K_0402_5%
R43
10K_0402_5%
R56
@10K_0402_5%
ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP
PROCESSOR FREQ MULTIPLIER
R44
10K_0402_5%
R57
@10K_0402_5%
R45
10K_0402_5%
R58
@10K_0402_5%
32KHZ_S5
32KHZ
OUTPUT
FROM SB200
(INT RTC)
DEFAULT
32KHZ INPUT
TO SB200
(EXT RTC)
+3VALW
12
R46
10K_0402_5%
R59
@10K_0402_5%
A A
5
PCI_AD26<26,31,33,34,41>
12
R967
@10K_0402_5%
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(4/4) - STRAPS
LA-2411
星期三 七月
0.1
of
29 65, 07, 2004
1
Page 30
5
U1B
IDEDA[0..15]
PD_D14
PD_D0
PD_D15
PD_D1
PD_D11
PD_D10
PD_D5
PD_D4
PD_D7
PD_D8
PD_D6
PD_D9
PD_D3
PD_D12
PD_D2
PD_D13
RP124
33_0804_8P4R_5%
R19
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4
5
9
10
12
PD_A0
PD_A2
PD_CS#3
PD_A1
SD_SBA0
SD_SBA1
SD_SBA2
SD_SCS3#
1 2
I0
I1
I0
I1
O
U1C
O
1 2
R32
SD_DREQ
SD_IDERST#
6
74HCT08PW_TSSOP14
HD_IDERST#
8
74HCT08PW_TSSOP14
PD_DREQ#
PD_DACK#
PD_CS#1
PD_IOR#
PD_IOW#
PD_IRQA
R968
8.2K_0402_5%
IDEIORDYB< 27>
5.6K_0402_5%
SD_SIOW#
SD_SIOR#
SD_SCS1#
SD_DACK#
SD_IRQ15
R33
8.2K_0402_5%
1 2
HD_IDERST#
+5VS
IDEIORDYA< 27>
IDERST_CD#<27>
PCI_RST#<11,26,31,33,34,38,41,44>
IDERST_HD#<27>
D D
IDEDA[0..15]<27>
IDEDA14
4 5
IDEDA0
3 6
IDEDA15
2 7
IDEDA1
1 8
RP1 33_0804_8P4R_5%
IDEDA11
4 5
IDEDA10
3 6
IDEDA5
2 7
IDEDA4
1 8
RP2 33_0804_8P4R_5%
IDEDA7
4 5
IDEDA8
3 6
IDEDA6
2 7
IDEDA9
1 8
RP3 33_0804_8P4R_5%
IDEDA3
4 5
IDEDA12
3 6
IDEDA2
2 7
IDEDA13
1 8
RP4 33_0804_8P4R_5%
C C
B B
A A
IDEREQA<27>
IDEDACK#A<27>
IDECS#A1<27>
IDEIOR#A<27>
IDEIOW#A<27>
IDEIRQA<27>
IDESAA0<27>
IDESAA2<27>
IDECS#A3<27>
IDESAA1<27>
IDESAB0<27>
IDESAB1<27>
IDESAB2<27>
IDECS#B3<27>
IDEDB[0..15]<27>
IDEDB5
IDEDB9
IDEDB4
IDEDB11
RP7 33_0804_8P4R_5%
IDEDB0
IDEDB15
IDEDB1
IDEDB14
RP8 33_0804_8P4R_5%
IDEDB6
IDEDB10
IDEDB8
IDEDB7
RP9
IDEDB3
IDEDB12
IDEDB2
IDEDB13
RP10
IDEREQB<27>
IDEIOW#B<27>
IDEIOR#B<27>
IDECS#B1<27>
IDEDACK#B<27>
IDEIRQB<27>
R11 33_0603_1%
4 5
3 6
2 7
1 8
R18 33_0603_1%
5.6K_0402_5%
IDESAA0
IDESAA2
IDECS#A3
IDESAA1
RP5 33_0804_8P4R_5%
IDESAB0
IDESAB1
RP6 33_8P4R_0804_5%
IDEDB[0..15]
SD_D5
4 5
SD_D9
3 6
SD_D4
2 7
SD_D11
1 8
SD_D0
4 5
SD_D15
3 6
SD_D1
2 7
SD_D14
1 8
SD_D6
4 5
SD_D10
3 6
SD_D8
2 7
SD_D7
1 8
33_0804_8P4R_5%
SD_D3
4 5
SD_D12
3 6
SD_D2
2 7
SD_D13
1 8
33_0804_8P4R_5%
R26 33_0603_1%
4 5
3 6
RP125 33_0804_8P4R_5%
2 7
1 8
R31 33_0603_1%
5
4
+5VS
12
13
1 2
1
2
I0
I1
10K_0402_5%
C22
14
I0
I1
7
U1D
O
74HCT08PW_TSSOP14
12
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#
+5VS
10U_0805_16V4Z
1 2
HDD_LED#
CDLED#
R3
R4 33_0402_5%
1 2
R15
1 2
10K_0402_5%
R969 33_0402_5%
R970 33_0402_5%
1 2
SD_DREQ
4
3
U1A
P
3
O
G
74HCT08PW_TSSOP14
ACT_LED# <44>
+5VS
1
C1
1000P_0402_50V7K
2
1
C2
10U_0805_16V4Z
2
Placea caps. near HDD CONN.
11
+5VS
+3VS
12
R25
4.7K_0402_5%
JP1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
OCTEK_HDD-22HG2_REVERSE
+3VS
R8
4.7K_0402_5%
1 2
PD_IORDY
SD_SIORDY
+5VS
1
C6
4.7U_0805_10V4Z
2
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PCSEL
R9 470_0402_5%
1 2
PD_A2
PD_CS#3
+5VS
C11 @10U_0805_6.3V6M
R611
10K_0402_5%
R24
1 2
10K_0402_5%
R614
470_0402_5%
1
C7
1U_0603_25V4Z
2
12
1 2
W=100mils
1
C14
2
1
C15
2
1U_0603_10V6K
1
C16
2
0.1U_0402_10V6K
1000P_0402_50V7K
Placea caps. ne ar CDROM CONN.
C17
+5VCD trace to CONN W=100mils
33P_0402_25V8K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
12
CDROM_L
SD_IDERST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0
CDLED#
+5VS
+5VS
SD_CSEL
1
2
2
1
C3
10U_0805_16V4Z
2
1
C8
4.7U_0805_10V4Z
2
JP2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
CD-ROM CONN.
+5VS
1
C4
1U_0603_10V6K
2
+5VS+5VS
1
C5
0.1U_0402_10V6K
2
1
C9
1U_0603_25V4Z
2
@47P_0402_25V8K
C12
1 2
CD_AGND
CDROM_R
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#
SD_DACK#
R1110 @10K_0402_5%
SD_SBA2
SD_SCS3#SD_SCS1#
W=80mils
C610 0.1U_0402_10V6K
1 2
R613 @100K_0402_5%
1 2
12
CD_AGND <36>
CDROM_R <36>CDROM_L<36>
+5VS
+5VS
+5VS
+5VS
W=100mils
1
C18
2
10U_0805_16V4Z
1
C19
2
1U_0603_10V6K
1
C20
2
0.1U_0402_10V6K
1000P_0402_50V7K
Placea caps. ne ar CDROM CONN.
+5VCD trace to CONN W=100mils
2
HDD/CD-ROM Module
+5VS
1
C21
2
Title
Size Document Number Rev
Date: Sheet
星期三 七月
1
Compal Electronics, Inc.
HDD & CDROM Connector
LA-2411
1
0.1
of
30 65, 07, 2004
Page 31
5
4
3
2
1
+3VS
1
2
+3VS
1
2
+S1_VCC
1
2
S1_WAIT# <32>
S1_INPACK# <32>
S1_WE# <32>
MSINS# <32>
XD_MS_PWREN# <32>
MSBS_XDD1 <32>
MSCLK_XDRE# <32>
MSD0_XDD2 <32>
MSD1_XDD6 <32>
MSD2_XDD5 <32>
MSD3_XDD3 <32>
C1027
0.1U_0402_16V4Z
C1031
0.1U_0402_16V4Z
C1035
0.1U_0402_16V4Z
S1_A16
2
1
C1028
0.1U_0402_16V4Z
2
1
C1032
0.1U_0402_16V4Z
2
1
C1036
0.1U_0402_16V4Z
2
10P_0402_50V8J
1
2
1
2
S1_CD1# S1_CD2#
C1040
C1029
0.1U_0402_16V4Z
C1033
0.1U_0402_16V4Z
1
C1037
0.1U_0402_16V4Z
2
1
2
2
1
1
2
10P_0402_50V8J
C1030
0.1U_0402_16V4Z
C1034
0.1U_0402_16V4Z
1
C1038
0.1U_0402_16V4Z
2
1
C1041
2
Closed to Pin A4Closed to Pin L12
Close chip termenal
MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSBS_XDD1
1 2
R1218 @43K_0402_5%
1 2
R1220 @43K_0402_5%
1 2
R1221 @43K_0402_5%
1 2
R1222 @43K_0402_5%
1 2
R1223 @43K_0402_5%
Title
Size Document Number Rev
Date: Sheet
Compal Electron i cs, Inc.
PCMCIA Controller ENE CB714
Custom
星期
, 07, 2004
三七月
LA-2411
1
of
31 65
0.1
G1
F3
VCC2
VCC1
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CCBE2#/A12
CCBE1#/A8
CIRDY#/A15
CTRDY#/A22
CSTOP#/A20
CPERR#/A14
CPAR/A13
CGNT#/WE#
CCLK/A16
SPKROUT
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14
MSINS#
SMBSY#
SMCD#
SMWP#
SMCE#
+S1_VCC
+3VS
B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
B7
A11
E11
H13
B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5
D11
D6
M9
B5
A4
L12
D9
C6
A2
E10
J13
H7
J8
H8
E9
G9
H9
G8
F9
H6
J7
J6
J5
S1_A[0..25]
S1_D[0..15]
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
S1_REG#
S1_A12
S1_A8
S1_CE1#
S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A19
S1_RDY#
PCM_SPK#
S1_BVD2
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14
XD_MS_PWREN#
MSBS_XDD1
MSD0_XDD2
MSD1_XDD6
MSD2_XDD5SDCM_XDALE
MSD3_XDD3
1 2
S1_A[0..25] <32>
S1_D[0..15] <32>
S1_IOWR# <32>
S1_IORD# <32>
S1_OE# <32>
S1_CE2# <32>
S1_REG# <32>
S1_CE1# <32>
S1_RST <32>
1 2
R1207 33_0402_5%
S1_BVD1 <32>
S1_WP <32>
S1_RDY# <32>
PCM_SPK# <37>
S1_BVD2 <32>
S1_CD2# <32>
S1_CD1# <32>
S1_VS2 <32>
S1_VS1 <32>
1 2
R1217 33_0402_5%
XDBSY# <32>
XDCD# <32>
XDWP# <32>
XDCE# <32>
R1308
2.2K_0402_5%
VPPD0<32>
VPPD1<32>
VCCD0#<32>
VCCD1#<32>
D D
C C
CLK_PCI_PCM
12
R1206
@10_0402_5%
1
C1039
@18P_0402_50V8K
2
+3VS +3VS
R1305
R20
1 2
1 2
B B
+VCC_5IN1
R1304
@0_0805_5%
1 2
A A
+3VS
Close chip termenal
1 2
R1306 0_0805_5%
1 2
R1208 43K_0402_5%
1 2
R1210 43K_0402_5%
1 2
R1212 43K_0402_5%
1 2
R1213 43K_0402_5%
1 2
R1214 43K_0402_5%
1 2
R1215 @43K_0402_5%
1 2
R1216 @43K_0402_5%
1 2
R1307 @43K_0402_5%
5
SM_CD#<32>
CARD_LED#<44>
SD_PULLHIGH
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
43K_0402_5%
SDCD#
SDWP
MSINS#
+3VS
10K_0402_5%
CLK_SD_48M<24>
SDCK_XDWE#<32>
PCI_AD[0..31]<26,29,33,34,41>
PCI_CBE#3<26,33,34,41>
PCI_CBE#2<26,33,34,41>
PCI_CBE#1<26,33,34,41>
PCI_CBE#0<26,33,34,41>
PCI_RST#<11,26,30,33,34,38,41,44>
PCI_FRAME#<26,33,34,41>
PCI_IRDY#<26,33,34,41>
PCI_TRDY#<26,33,34,41>
PCI_DEVSEL#<26,33,34,41>
PCI_STOP#<26,33,34,41>
PCI_PERR#<26,33,34,41>
PCI_SERR#<26,33,41>
PCI_PAR<26,33,34,41>
PCI_REQ#2<26>
PCI_GNT#2<26>
CLK_PCI_PCM<26>
PCI_PIRQA#<10,17,26,34>
PCI_PIRQB#<26>
SIRQ<26,38,44>
SDOC#<32>
+VCC_5IN1
SDCD#<32>
SDWP<32>
SDPWREN#<32>
1 2
SDCM_XDALE<32>
SDDA0_XDD7<32>
SDDA1_XDD0<32>
SDDA2_XDCL<32>
SDDA3_XDD4<32>
PCI_AD[0..3 1]
PCI_AD31
C2
PCI_AD30
C1
PCI_AD29
D4
PCI_AD28
D2
PCI_AD27
D1
PCI_AD26
E4
PCI_AD25
E3
PCI_AD24
E2
PCI_AD23
F2
PCI_AD22
F1
PCI_AD21
G2
PCI_AD20
G3
PCI_AD19
H3
PCI_AD18
H4
PCI_AD17
J1
PCI_AD16
J2
PCI_AD15
N2
PCI_AD14
M3
PCI_AD13
N3
PCI_AD12
K4
PCI_AD11
M4
PCI_AD10
K5
PCI_AD9
L5
PCI_AD8
M5
PCI_AD7
K6
PCI_AD6
M6
PCI_AD5
N6
PCI_AD4
M7
PCI_AD3
N7
PCI_AD2
L7
PCI_AD1
K7
PCI_AD0
N8
E1
J3
N1
N5
PCI_RST#
G4
J4
K1
K3
L1
L2
L3
M1
M2
A1
PCI_RST#
M11
M10
B1
H1
L8
L11
F4
K8
N9
K9
N10
L10
N11
J9
E7
E8
F8
G7
H5
F6
E5
E6
F7
F5
G6
G5
CLK_PCI_PCM A16_CLK
3V_PCM_SUSP
1 2
R1209 10K_0402_5%
R1211 100_0402_5%
1 2
R1219
4
PCM_IDPCI_AD20
PCI_PIRQA#
SD_PULLHIGH
PCI_PIRQB#
SDOC#
SDCD#
SDWP
SDPWREN#
33_0402_5%
SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
N13
M13
U37
VCCD0#
VCCD1#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CBE3#
CBE2#
CBE1#
CBE0#
PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK
RIOUT#_PME#
SUSPEND#
IDSEL
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
MFUNC7
GRST#
VCC_SD
SDCD#
SDWP/SMWPD#
SDPWREN33#
SDCLKI
SDCLK/SMWE#
SDCMD/SMALE
SDDAT0/SMDATA7
SDDAT1/SMDATA0
SDDAT2/SMCLE
SDDAT3/SMDATA4
GND_SD
IDSEL:
PCI_AD20
M12
VPPD1
N12
VPPD0
PCI Interface
B4
G13
A7
VCCA1
VCCA2
SD/MMC/MS/SM
GND1D3GND2H2GND3L4GND4M8GND5
K11
K2
N4
L6
C8
L9
H11
D12
VCC3
VCC4
VCC5
VCC9
VCC6
VCC7
VCC8
VCC10
CAD15/IOWR#
CCBE3#/REG#
CCBE0#/CE1#
CARDBUS
CRST#/RESET
CFRAME#/A23
CDEVSEL#/A21
CSERR#/WAIT#
CREQ#/INPACK#
CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CINT#/READY_IREQ#
CAUDIO/BVD2_SPKR#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3
GND6
GND7
GND8
CB714_LFBGA169
B6
F12
C10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.
3
Page 32
PCMCIA Power Controller
CardBus Socket
+VCC_5IN1
MSINS#<31>
SDDA1_XDD0<31>
MSBS_XDD1<31>
MSD0_XDD2<31>
MSD3_XDD3<31>
SDDA3_XDD4<31>
MSD2_XDD5<31>
MSD1_XDD6<31>
SDDA0_XDD7<31>
XDWP#<31>
+VCC_5IN1
C10440.1U_0402_16V4Z
C10480.1U_0402_16V4Z
C10494.7U_0805_10V4Z
C10520.1U_0402_16V4Z
C10534.7U_0805_10V4Z
R1224
10K_0402_5%
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSD0_XDD2
MSCLK_XDRE#
MSBS_XDD1
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
XDBSY#
MSCLK_XDRE#
XDCE#
SDCK_XDWE#
XDWP#
SDDA2_XDCL
SDCM_XDALE
XDCD#
+5VS
+5VS
+3VS
JP29
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
69
GND
71
GND
73
GND
75
GND
77
GND
79
GND
81
GND
83
GND
FOX_WZ21131-G2-P4
+VCC_5IN1
Reserve for Debug.
U60
1
GND
2
IN
3
IN
EN#4OC#
TPS2041ADR_SO8
35
GND
GND
GND
GND
GND
GND
GND
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S1_CD1#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
72
74
76
78
80
82
84
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#
+S1_VCC
+S1_VPP
xD PU and PD. Close to Socket
MSCLK_XDRE#
1 2
R1232 43K_0402_5%
R1235 2.2K_0402_5%
R1236 43K_0402_5%
R1238 43K_0402_5%
S1_WP
S1_OE#
S1_RST
S1_CE1#
S1_CE2#
1 2
1 2
1 2
OUT
OUT
OUT
8
7
6
5
SDCK_XDWE#
XDBSY#
+S1_VCC
12
R122743K_0402_5%
12
R122847K_0402_5%
12
R122947K_0402_5%
12
R123047K_0402_5%
12
R123147K_0402_5%
+VCC_5IN1
10K_0402_5%
XDCE# <31>
XDBSY# <31>
R1234
1 2
S1_CD1# <31>
S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>
S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>
S1_CD2# <31>
SDOC# <31>
C1050
C1054
S1_A[0..25]
S1_D[0..15]
1
0.1U_0402_16V4Z
2
1
0.01U_0402_25V4Z
2
+S1_VCC
C1051
+S1_VPP
C1055
1
2
1
2
+3VS
1 2
R1237 @43K_0402_5%
SD CLK
MS CLK
XDCD#
SDCK_XDWE#<31>
@10P_0402_50V8K
MSCLK_XDRE#<31>
@10P_0402_50V8K
SDPWREN#<31>
XD_MS_PWREN#<31>
S1_CE1#<31>
S1_OE#<31>
S1_WE#<31>
S1_RDY#<31>
+S1_VCC
S1_WP<31>
@0_0402_5%
@0_0402_5%
10K_0402_5%
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
+S1_VPP
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP
XDCD# <31>
SDCK_XDWE#
12
R1225
1
C1056
2
MSCLK_XDRE#
12
R1226
1
C1057
2
SD PWR Control
+3VS +3VS
+3VS
R1233
1 2
Close to
CardBus Conn.
4.7U_0805_10V4Z
SM_CD# <31>
S1_A[0..25]<31>
S1_D[0..15]<31>
10U_0805_10V4Z
SDDA2_XDCL <31>
SDCM_XDALE <31>
XDCE# <31>
MSCLK_XDRE# <31>
SDCK_XDWE# <31>
XDBSY# <31>
XDCD# <31>
+VCC_5IN1
+VCC_5IN1
SDWP <31>
SDCD# <31>
U38
9
12V
5
5V
6
5V
3
3.3V
4
3.3V
GND
7
1 2
JP31
31
VSS_MS(P1)
40
VSS_MS (P10)
33
VCC_MS(P3)
39
VCC_MS(P9)
35
RSVD_MS(P5)
37
RSVD_MS(P7)
34
SDIO_MS(P4)
38
SCLK_MS(P8)
36
INS_MS(P6)
32
BS_MS(P2)
10
D0_XD(P10)
11
D1_XD(P11)
12
D2_XD(P12)
13
D3_XD(P13)
14
D4_XD(P14)
15
D5_XD(P15)
16
D6_XD(P16)
17
D7_XD(P17)
2
R/B#_XD(P2)
3
RE#_XD(P3)
4
CE#_XD(P4)
7
WE#_XD(P7)
8
WP#_XD(P8)
5
CLE_XD(P5)
6
ALE_XD(P6)
18
VCC_XD(P18)
70
VCC_XD
1
CD/GND_XD(P1)
69
GND_XD
9
VSS_XD(P9)
67
GND0
68
GND1
PRO_FIT068-20-3100
VCC
VCC
VCC
VPP
VCCD0
VCCD1
VPPD0
VPPD1
OC
SHDN
CP-2211_SSOP16
16
13
12
11
10
1
2
15
14
8
+S1_VCC
40mil
+S1_VPP
20mil
MS INTERFACE XD INTERFACE
1 2
C1042 0.1U_0402_16V4Z
C1043 0.1U_0402_16V4Z
1 2
C1045 10U_0805_10V4Z
1 2
C1046 0.01U_0402_25V4Z
1 2
C1047 1U_0603_10V4Z
VCCD0# <31>
VCCD1# <31>
VPPD0 <31>
VPPD1 <31>
IO 1_SM(P6)
IO 2_SM(P7)
IO 3_SM(P8)
IO 4_SM(P9)
IO 5_SM(P13)
IO 6_SM(P14)
IO 7_SM(P15)
IO 8_SM(P16)
CLE_SM(P2)
ALE_SM(P3)
CE_SM(P21)
RE_SM(P20)
WE_SM(P4)
WP_SM(P5)
R/B_SM(P19)
CD/VSS_SM(P11)
LVD_SM(P17)
VCC_SM(P12)
SM INTERFACESD INTERFACE
VCC_SM(P22)
VSS_SM(P1)
VSS_SM(P10)
GND_SM(P18)
DAT0_SD(P7)
DAT1_SD(P8)
DAT2_SD(P9)
CD/DAT3_SD(P1)
CLK_SD(P5)
CMD_SD(P2)
VDD_SD(P4)
VSS1_SD(P6)
VSS2_SD(P3)
WP1_SM
WP2_SM
CD1_SM
CD2_SM
WP_SD
GND_SD
CD_SD
60
64
54
49
45
50
52
56
53
59
51
61
63
66
65
47
62
46
55
57
48
58
41
42
43
44
23
22
30
29
25
28
26
27
24
19
20
21
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
SDDA2_XDCL
SDCM_XDALE
XDCE#
MSCLK_XDRE#
SDCK_XDWE#
XDWP#
XDBSY#
XDCD#
SDWP
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
SDCK_XDWE#
SDCM_XDALE
SDWP
SDCD#
1
C1151
10U_0805_10V4Z
2
C1152
0.1U_0402_16V4Z
C1153
0.1U_0402_16V4Z
+VCC_5IN1
C1155
0.1U_0402_16V4Z
C1156
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electron i cs, Inc.
PCMCIA Socket
LA-2411
星期
, 07, 2004
三七月
of
32 65
0.1
Page 33
A
EN_WOL#<44>
C1077
1U_0603_10V4Z
+LANVDD
1
2
PCI_AD[0..31]<26,29,31,34,41>
PCI_CBE#[0..3]<26,31,34,41>
PCI_PAR<26,31,34,41>
PCI_FRAME#<26,31,34,41>
PCI_IRDY#<26,31,34,41>
PCI_TRDY#<26,31,34,41>
PCI_DEVSEL#<26,31,34,41>
PCI_STOP#<26,31,34,41>
PCI_PERR#<26,31,34,41>
PCI_SERR#<26,31,41>
PCI_REQ#1<26>
PCI_GNT#1<26>
PCI_PIRQD#<26,41>
ONBD_LAN_PME#<34,41,44,45>
PCI_RST#<11,26,30,31,34,38,41,44>
CLK_PCI_LAN<26>
PCI_CLKRUN#<26,38,41,44>
@15P_0402_50V8D
A
1
C1078
0.1U_0402_16V4Z
2
PCI_AD19
@10_0402_5%
R1282
C1105
1 1
2 2
3 3
4 4
2
Q124
SI2301DS_SOT23
PCI_AD[0..31]
PCI_CBE#[0..3]
R1274 100_0402_5%
1 2
1 2
1
2
G
+3VALW
S
D
1 3
B
1 2
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
B
R1258
@0_1206_5%
+LANVDD
104
103
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33
92
77
60
44
46
76
61
63
67
68
69
70
75
30
29
25
31
27
28
65
4
17
128
21
38
51
66
81
91
101
119
35
52
80
100
U39
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI I/F
C/BE#0
C/BE#1
C/BE#2
C/BE#3
IDSEL
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
REQ#
GNT#
INTA#
PME#
RST#
CLK
CLKRUN#
GND/VSS
GND/VSS
GND/VSS
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND
GND
GND
GND
RTL8100C_QFP128
C
CTRL25
EEDO
AUX/EEDI
EESK
EECS
LED0
LED1
LED2
NC/LED3
TXD+/MDI0+
TXD-/MDI0-
RXIN+/MDI1+
RXIN-/MDI1-
NC/MDI2+
NC/MDI2-
NC/MDI3+
NC/MDI3-
X1
X2
LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA
NC/M66EN
NC/AVDDH
NC/HV
NC/HSDAC+
NC/HG
NC/LG2
NC/LV2
NC/VSS
NC/VSS
NC/GND
NC/GND
NC/GND
NC/GND
LAN I/F
NC/GND
NC/GND
CTRL25
RTT3/CRTL18
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL
NC/AVDDL
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
Power
AVDD25/HSDAC-
8100C@0.1U_0402_16V4Z
C
+LANVDD
3
1
22U_1206_10V4Z
108
109
111
106
117
115
114
113
1
2
5
6
14
15
18
19
121
122
105
23
127
72
74
88
10
120
11
123
124
126
9
13
22
48
62
73
112
118
8
125
26
41
56
71
84
94
107
3
7
20
16
32
54
78
99
24
45
64
110
116
8110S@0.1U_0402_16V4Z
12
Q125
2SB1188_SOT89
+V2.5_LAN
2
1
C1073
2
R1260 3.6K_0402_5%
EEDO
EEDI
EESK
EECS
ACTIVITY#
LINK_10_100_1000#
TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1-
X1
X2
R1270 5.6K_0603_1%
@0_0402_5%
R1272
CTRL25
CTRL18
1
2
1
2
2
1
2
1
1
1
C1116
2
2
D
1
C1074
0.1U_0402_16V4Z
2
12
+5VS
12
R1266
1K_0402_5%
R1268 15K_0402_5%
12
R64 5.6K for 8100C
2.49K for 8110S
8110S@0.1U_0402_16V4Z
12
R1273
1
8110S@0_0805_5%
C1087
2
8110S@0.1U_0402_16V4Z
C1093
10U_0805_10V4Z
C1101
0.1U_0402_16V4Z
C1106
0.1U_0402_16V4Z
C1111
8110S@0.1U_0402_16V4Z
R1290 8100C@0_0805_5%
C1117
8100C@0.1U_0402_16V4Z
1
C1085
2
1 2
27P_0402_50V8J
1
2
1
2
2
0.1U_0402_16V4Z
1
2
1
1 2
1
2
C1094
0.1U_0402_16V4Z
C1102
0.1U_0402_16V4Z
C1107
C1112
D
E
+LANVDD
3
CTRL18
1
8110S@2SB1188_SOT89
+LANVDD
U62
4
DO
GND
3
DI
NC
2
SK
NC
1
CS
VCC
AT93C46-10SI-2.7_SO8
12
R1271 8110S@0_0805_5%
1 2
C1086
8110S@0.1U_0402_16V4Z
+V1.8_LAN
Y5
1
C1089
25MHZ_20P
2
1
C1095
0.1U_0402_16V4Z
2
1
C1103
0.1U_0402_16V4Z
2
2
C1108
0.1U_0402_16V4Z
1
2
C1113
1
8110S@0.1U_0402_16V4Z
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Q123
8110S@4.7U_0805_10V4Z
5
6
7
8
C1079
0.1U_0402_16V4Z
+LANVDD
X2X1
12
2
1
1
C1096
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
C1104
1
2
C1109
0.1U_0402_16V4Z
1
2
C1114
1
+V2.5_LAN
+V1.8_LAN
1
C1075
2
2
+LANVDD
1
49.9_0402_1%
C1090
27P_0402_50V8J
1
C1097
0.1U_0402_16V4Z
2
8110S@0.1U_0402_16V4Z
2
C1115
8110S@0.1U_0402_16V4Z
1
E
1
C1076
8110S@0.1U_0402_16V4Z
2
12
1
2
1
2
1 2
1 2
1 2
1 2
12
C1088
0.1U_0402_16V4Z
C1098
0.1U_0402_16V4Z
+V1.8_LAN
R1275
Place as close to
Magnetic
R1283 8100C@0_0805_5%
R1285 8110S@0_0805_5%
R1286 8110S@0_0805_5%
R1287 8100C@0_0805_5%
R1276
49.9_0402_1%
R1277
49.9_0402_1%
+LANVDD
F
12
1
C1091
0.1U_0402_16V4Z
2
Place as close to
LAN Chip
2
C1099
0.1U_0402_16V4Z
1
+LANVDD
+V2.5_LAN
+V1.8_LAN
+V2.5_LAN
F
+LANVDD
+LANVDD
RXIN-/MDI1RXIN+/MDI1+
TXD-/MDI0-
TXD+/MDI0+
12
R1278
49.9_0402_1%
LINK_10_100_1000#
R1259 300_0402_5%
ACTIVITY#
R1257 300_0402_5%
RJ45_TXRJ45_TX+
RJ45_RX+
RJ45_RX-
R1281
75_0402_1%
RJ45_GND
1 2
1000P_1206_2KV7K
0.1U_0402_16V4Z
1
C1092
0.1U_0402_16V4Z
2
Title
Size Document Number Rev
Date: Sheet
G
12
12
12
JP54
2
PR1-
1
PR1+
3
PR2+
R1284
75_0402_1%
1 2
C1100
1 2
C1080
1
2
3
4
5
6
8
4
5
6
7
8
U63
RD+
RDCT
NC
NC
CT
TD+7TX+
TD-
Pulse H0013
PR3+
PR3PR2PR4+
PR4-
LANGND
1
1
C1082
2
2
4.7U_0805_10V4Z
RX+
RX-
CT
NC
NC
CT
TX-
LDE_YELLOW+
16
15
14
13
12
11
10
9
75_0402_1%
Compal Electronics, Inc.
Gigabit Ethernet RTL8110S
LA-2411
G
星期三 七月
10
11
LED_GREEN
LDE_YELLOW-
SHLD113SHLD2
FOX_JM36113-L1H7
14
R1279
H
9
LED_ORANGE
RJ45_RXRJ45_RX+
RJ45_TXRJ45_TX+
12
12
R1280
75_0402_1%
RJ45_GND
0.1
of
33 65, 07, 2004
H
Page 34
5
D D
PCI_AD[0..31]<26,29,31,33,41>
C C
PCI_CBE#0<26,31,33,41>
PCI_CBE#1<26,31,33,41>
PCI_CBE#2<26,31,33,41>
PCI_CBE#3<26,31,33,41>
PCI_FRAME#<26,31,33,41>
PCI_TRDY#<26,31,33,41>
PCI_DEVSEL#<26,31,33,41>
B B
PCI_PERR#<26,31,33,41>
PCI_PIRQA#<10,17,26,31>
CLK_PCI_1394<26>
1 2
PCI_IRDY#<26,31,33,41>
PCI_STOP#<26,31,33,41>
PCI_PAR<26,31,33,41>
PCI_REQ#0<26>
PCI_GNT#0<26>
1 2
PCI_RST#<11,26,30,31,33,38,41,44>
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
CLK_PCI_1394
12
1
2
PCI_AD[0..31]
25
24
20
19
18
16
15
14
11
10
117
116
115
114
113
109
107
106
103
102
101
98
97
96
95
94
12
119
104
R717
105
100_0402_1%
120
121
123
124
125
127
128
93
92
R1310
88
0_0402_5%
89
90
R726
@10_0402_5%
C703
@18P_0402_50V8K
9
8
7
4
3
2
1
U42
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
PAR
REQ#
GNT#
INTA#
PCIRST#
PCICLK
NC41NC
PCI Bus
NC45NC48NC49NC50NC37NC51NC52NC53NC54NC40NC39NC35NC74NC75NC76NC77NC78NC64NC81NC82NC83NC84NC85I2CEN43CARDEN
42
4
+3VS
100
108
46
110
122
111
21
30
PVD36PVD
VCC99VCC
VCC
VCC5VCC17VCC32VCC
VCC
31
VCC
GND47GND
GND91GND
GND
Power
IEEE 1394
VT6301S
NC
44
R711
4.7K_0402_5%
118
126
112
38
GND
GND
GND6GND13GND23GND33GND
GND22GND
PVA
PVA
PVA
PVA
PVA
PVA
GND
GND
GND
GND
GND
GND
EEPROM
I/F
EECS
EEDO
EEDI/SDA
EECK/SCL
PM & Test
PME#
XCPS
XREXT
TPB0M
TPB0P
TPA0M
TPA0P
TPBIAS0
OSC
XI
57
PHYRESET#
XO
VT6301S-CD_LQFP128
58
1394 Differential Pairs
+3VS
3
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
+3VS
FCM2012C-800_0805
1 2
59
62
72
73
86
87
61
65
66
79
80
56
R5 @4.7K_0402_5%
26
27
EEDI_LAN
28
EECK_LAN
29
34
60
63
XTPB0-
67
XTPB0+
68
XTPA0-
69
XTPA0+PCI_AD16
70
XTPBIAS0
71
6.34K_0402_1%
55
2
C700
0.1U_0402_16V4Z
XO
XI
1
1
C683
2
L44
+3V_1394
2
C692
1
0.1U_0402_16V4Z
1394_PME# <33,41,44,45>
R716
C684
0.1U_0402_16V4Z
2
C693
1
0.1U_0402_16V4Z
+3VS
2
C705
47P_0402_50V8J
1
1
C685
2
0.1U_0402_16V4Z
2
1
+3VS
0.1U_0402_16V4Z
1
2
C694
R1311
1K_0402_5%
R1312
1K_0402_5%
2
1
C686
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C695
1
XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-
270P_0402_25V8K
0.1U_0402_16V4Z
1
C687
C688
2
U33
1
A0
2
A1
3
A2
4
GND
AT24C02N-10SC-2.7_SO8
12
R720
54.9_0402_1%
12
R722
54.9_0402_1%
1
C702
2
1
2
0.1U_0402_16V4Z
VCC
WC
SCL
SDA
C689
8
7
6
5
0.1U_0402_16V4Z
1
2
+3VS
EECK_LAN
EEDI_LAN
12
R721
54.9_0402_1%
12
R723
54.9_0402_1%
12
R727
4.99K_0603_1%
C690
Note:These components need to close to chip pins.
X3
C699
10P_0402_50V8K
XI
24.576MHz_16P_3XG-24576-43E1
2
1
1 2
R1315
1M_0402_5%
XO
2
1
C698
10P_0402_50V8K
+3VS
1
2
1 2
R715
560_0402_5%
1
C701
0.33U_0603_16V4Z
2
1
C691
0.1U_0402_16V4Z
JP33
4
4
3
3
6
2
5
2
1
1
FOX_UV31413-4R1-TR
6
5
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
IEEE 1394 CONTROLLER
LA-2411
星期三
07, 2004
七月
0.1
34 65,
1
Page 35
1
2
3
4
5
W=40mils
1
+
C315
C312
2
1
C1134@2.2P_0402_50V8C
2
1
+
2
1
C1136@2.2P_0402_50V8C
2
C316
0.1U_0402_10V6K
@2.2P_0402_50V8C
W=40mils
C313
0.1U_0402_10V6K
@2.2P_0402_50V8C
150U_D2_6.3VM
1 1
USB20P1-<27>
+5VALW
1
C1008
4.7U_0805_10V4Z
2 2
2
SYSON#
U14
1
2
3
4
G528_SO8
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
+USB_AS
8
7
6
5
1 2
R896
0_0402_5%
OVCUR#1 <27>
OVCUR#2 <27>
USB20P1+<27>
USB20P2-<27>
USB20P2+<27>
USB20P1USB20P1+
USB20P2USB20P2+
150U_D2_6.3VM
W=40mils
1
+
C308
C307
150U_D2_6.3VM
+5VALW
3 3
4.7U_0805_10V4Z
SYSON#<47>
C1002
1
2
SYSON#
U13
1
2
3
4
G528_SO8
GND
IN
IN
EN#
OUT
OUT
OUT
+USB_CS
8
7
6
5
FLG
1 2
R894 0_0402_5%
OVCUR#0 <27>
OVCUR#3 <26>
USB20P0-<27>
USB20P0+<27>
USB20P0USB20P0+
2
0.1U_0402_10V6K
1
C1138@2.2P_0402_50V8C
2
W=40mils
1
+
C1000
C1001
150U_D2_6.3VM
USB20P3-<27>
USB20P3+<27>
4 4
USB20P3USB20P3+
2
1
C1140@2.2P_0402_50V8C
2
0.1U_0402_10V6K
1
2
@2.2P_0402_50V8C
+USB_AS
1
1
C317
1000P_0402_50V7K
2
2
1
C1133
2
+USB_AS
1
1
C314
1000P_0402_50V7K
2
2
1
C1135
2
+USB_CS
1
1
C309
1000P_0402_50V7K
2
2
1
C1137
2
@2.2P_0402_50V8C
+USB_CS
1
1
C999
1000P_0402_50V7K
2
2
C1139
JP20
1
2
3
4
suyin_020167mr004s511zu_4p
JP19
1
2
3
4
suyin_020167mr004s511zu_4p
JP18
1
2
3
4
suyin_020167mr004s511zu_4p
JP48
1
2
3
4
suyin_020167mr004s511zu_4p
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
USB2.0 Connector
星期三 七月
LA-2411
5
0.1
of
35 65, 07, 2004
Page 36
A
B
C
D
E
F
G
H
+5VS
L29
1 2
KC FBM-L11-201209-221LMAT_0805
L30
1 2
KC FBM-L11-201209-221LMAT_0805
1
C716
1 1
2 2
3 3
4 4
10U_0805_10V4Z
LINE_IN_L<37>
LINE_IN_R<37>
CDROM_R<30>
CD_AGND<30>
2
R748 4.7K_0402_5%
R749 4.7K_0402_5%
R751 4.7K_0402_5%
R752 4.7K_0402_5%
R755 2.7K_0402_5%
R757 2.7K_0402_5%
MIC_IN<37>
MD_SPK<42>
R761
10K_0402_5%
R1196 0_0805_5%
R1197 0_0805_5%
R1198 0_0805_5%
0.1U_0402_16V4Z
1 2
1 2
1 2
R762
2.4K_0402_5%
1 2
1 2
1 2
22U_1206_10V4Z
C990
12
12
12
12
12
+5VAMP
40mil
1
C715
2
2
2
C989
0.1U_0402_16V4Z
1
1
2
C747
1
0.01U_0402_16V7K
4
2
8
CDROM_R_L
CDROM_R_R
2
1
U46
VIN
SENSE or ADJ
DELAY
ERROR7CNOISE
SD
SI9182DH-AD_MSOP8
NBA_PLUG<37>
CD_GNA
+AUD_VREF
C905
0.1U_0402_16V4Z
5
VOUT
6
1
3
GND
C991 1U_0603_10V4Z
C992 1U_0603_10V4Z
C734 1U_0603_10V4Z
C735 1U_0603_10V4Z
C736 1U_0603_10V4Z
C737 1U_0603_10V4Z
C904 1U_0603_10V4Z
C749 1U_0603_10V4Z
MONO_IN<37>
1
C720
0.1U_0402_16V4Z
2
NBA_PLUG
1 2
R1199 0_0402_5%
C1019 @0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R1200 @47K_0402_5%
+3VS
AC97_RST#<27,42>
AC97_SYNC<27,29,42>
AC97_SDOUT<27,29,42>
R771 0_0402_5%
1 2
EAPD<37>
+VDDA
12
1 2
+VDDA
12
R736
150K_0603_1%
12
R737
51K_0603_1%
1 2
L31
CHB2012U170_0805
HP_SENSE
CDROM_RC_L
CDROM_RC_R
CDGNDA
MICIN
MDC_RC_SPKMDC_R_SPK
1
C717
10U_0805_10V4Z
2
+VDDA
U47
14
AUX_L
15
AUX_R
16
JD2
17
JD1
23
LINE_IN_L
24
LINE_IN_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1
22
MIC2
13
PHONE
12
PC_BEEP
11
RESET#
10
SYNC
5
SDATA_OUT
45
NC
46
XTLSEL
47
SPDIFI/EAPD
48
SPDIFO
4
DVSS1
7
DVSS2
ALC250_LQFP48
R771
Stuff
No-Stuff
+AVDD_AC97
1
C1023
2
0.1U_0402_16V4Z
38
AVDD125AVDD2
LINE_OUT_L
LINE_OUT_R
MONO_OUT/VREFOUT3
MODE
14.318MHz External
24.576MHz Crystal
or Externa l Colck
40mil
1
2
9
DVDD11DVDD2
35
36
37
39
HP_OUT_L
41
HP_OUT_R
6
BIT_CLK
8
SDATA_IN
2
XTL_IN
3
XTL_OUT
29
AFILT1
30
AFILT2
28
VREFOUT
27
VREF
32
DCVOL
31
NC
33
VREFOUT2
34
VAUX
43
SCK
44
SDA
40
NC
26
AVSS1
42
AVSS2
C1024
10U_0805_10V4Z
1
2
R1202 22_0402_5%
AFILT1
AFILT2
1
C729
0.1U_0402_16V4Z
C1020 1000P_0402_50V7K
C1021 1000P_0402_50V7K
C730
10U_0805_10V4Z
2
C10 27P_0402_50V8J
1 2
R1201
12
12
1 2
1 2
1000P_0402_50V7K
22_0402_5%
+AUD_VREF
+3VS
1
C752
2
R1205
@1M_0402_5%
1 2
@22P_0402_50V8J
1
2
AC97_BITCLK <27,42>CDROM_L<30>
AC97_SDIN0 <27>
1
C1026
2
AUD_REF
C1022
1 2
1U_0603_10V4Z
C750
1 2
1U_0603_10V4Z
C751
1 2
@1U_0603_10V4Z
+AUD_VREF
10mil
1
C1017
1U_0603_10V4Z
C984
1000P_0402_50V7K
Y6 @24.576MHz_16P_3XG-24576-43E1
1 2
2
C985 4.7U_0805_10V4Z
1 2
C986 4.7U_0805_10V4Z
1 2
R1295 0_0402_5%
12
1
C1025
@22P_0402_50V8J
2
1
C745
1U_0603_10V4Z
2
1
C1018
0.1U_0402_16V4Z
2
LINE_OUTL <37>
LINE_OUTR <37>
CLK_14M_CODEC <24>
+AVDD_AC97
R7
1M_0402_5%
1 2
1
C746
0.1U_0402_16V4Z
2
CLK_14M_CODEC
12
R1143
@10_0402_5%
C973
@15P_0402_50V8J
GND GNDA
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
D
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
LA-2411
星期三 七月
G
AC97 CODEC
0.1
of
36 65, 07, 2004
H
Page 37
A
B
C
D
E
SPKL+
SPKL-
EAPD <36>
+5VAMP
Internal MIC
@WM-64PCY_2P
SPKR+
SPKL+
SPKR+
SPKR-
C1129
@220P_0402_50V7K
MIC1
1
2
150U_D2_6.3VM
C1059
1 2
+
1 2
+
C1058
150U_D2_6.3VM
1
1
2
2
@220P_0402_50V7K
INT_MIC
1
C257
220P_0402_50V7K
2
INTSPK_R1-2
INTSPK_L1-2
C1130
47_0402_5%
R1241
1 2
1 2
R1240
47_0402_5%
LINE_IN_R<36>
LINE_IN_L<36>
MIC_IN<36>
1 1
2 2
3 3
4 4
+5VAMP
BEEP#<44>
12
R971
10K_0402_5%
VOL_AMP
(0.65V -> 10dB )
12
R972
1.5K_0402_1%
LINE_OUTL<36>
LINE_OUTR<36>
+3VALW
14
4
P
A
5
B
G
7
Pin 2
SPKL+
SPKR+
LINE_OUTL
LINE_OUTR
+3VALW
12
R729
@100K_0402_1%
U18B
SN74LVC32APWLE_TSSOP14
O
6
R731
1 2
10K_0402_1%
0.22U_0603_10V7K
PCM_SPK#<31>
0.1U_0402_10V6K
SB_SPKR<27>
HIGH
LOW
NBA_PLUG<36>
C896 0.47U_0603_16V4Z
C890
0.47U_0603_16V4Z
1
C713
2
1
C979
2
PIN 6,20 ACTIVE
PIN 5,23 ACTIVE
NBA_PLUG
VOL_AMP
1 2
1 2
C8950.47U_0603_16V4Z
HP_L
1 2
HP_R
1 2
+3VALW
14
U45A
P
1
O2I
G
SN74LVC14APWLE_TSSOP14
7
+3VALW
14
U32F
P
13
O12I
G
SN74LVC14APWLE_TSSOP14
7
+3VALW
14
U45C
P
5
O6I
G
SN74LVC14APWLE_TSSOP14
7
C894
0.47U_0603_16V4Z
LEFT_2
RIGHT_2
1
C891
2
0.1U_0402_16V4Z
C712
1U_0603_10V6K
C721
1U_0603_10V6K
C722
1U_0603_10V6K
12
+5VAMP
1
2
1
C892
0.047U_0603_16V7K
2
R732
1 2
560_0402_5%
R739
1 2
12
560_0402_5%
R741
1 2
12
560_0402_5%
10K_0402
W=40Mil
1
C774
C773
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
U52
7
PVDD
SHUTDOWN#
18
PVDD
19
VDD
2
HP/LINE#
3
VOLUME
4
LOUT+
21
ROUT+
5
LLINEIN
23
RLINEIN
6
LHPIN
20
RHPIN
17
CLK
TPA0232PWP_TSSOP24
+VDDA
2
B
12
R742
SE/BTL#
PC-BEEP
BYPASS
LOUT-
ROUT-
GND
GND
GND
GND
12
R733
10K_0402_1%
12
R735
10K_0402_1%
1
C
Q56
E
2SC2411K_SOT23
3
D46
RB751V_SOD323
2 1
+5VAMP
12
R973
100K_0402_5%
SHUTDOWN#
22
15
14
11
9
16
10
LIN
8
RIN
1
12
13
24
C714 1U_0603_10V6K
1U_0603_10V4Z
12
R1063
1 2
39K_0603_1%
NBA_PLUG
BYPASS
C1011
MONO_IN1
13
D
Q119
2
G
2N7002_SOT23
S
R974 100K_0402_5%
1 2
1 2
C1014 0.1U_0402_16V4Z
SPKLSPKR-
2
2
C1012
C1013
1
1
0.47U_0603_16V4Z
R738
1 2
10K_0402_5%
C719
1 2
1U_0603_25V4Z
0.47U_0603_16V4Z
EAPD
2
1
MONO_IN <36>
L65 FBM-11-160808-700T_0603
1 2
L66 FBM-11-160808-700T_0603
1 2
L67 FBM-11-160808-700T_0603
1 2
L68 FBM-11-160808-700T_0603
1 2
1
1
C1131
2
2
@220P_0402_50V7K
INTSPK_R1-3
INTSPK_L1-3
FBM-11-160808-700T_0603
C1132
@220P_0402_50V7K
FBM-11-160808-700T_0603
L25
1 2
FBM-11-160808-700T_0603
L24
1 2
FBM-11-160808-700T_0603
2.2K_0402_5%
1 2
L23
220P_0402_50V7K
FBM-11-160808-700T_0603
L28
1 2
1 2
L27
330P_0402_50V7K
+AUD_VREF
R1245
C1062
C1060
12
1
2
1
1
2
2
LINE_IN_R-1
LINE_IN_L-1
12
R1246
@2.2K_0402_5%
LINE_IN_R-1
LINE_IN_L-1
1
C1063
220P_0402_50V7K
2
NBA_PLUG
INTSPK_R1-4
INTSPK_L1-4
C1061
330P_0402_50V7K
JP34
1
1
2
2
3
3
4
4
ACES_85205-0400
JP50
5
4
3
6
2
1
AMP_1-1470184-2
JP51
5
4
3
6
2
1
AMP_1-1470184-2
EXT.
MICPHONE
JACK
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
AMP & Audio Jack
星期三 七月
LA-2411
E
0.1
of
37 65, 07, 2004
Page 38
5
4
3
2
1
SUPER I/O SMsC FDC47N217
+3VS
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRRX
1 8
2 7
3 6
4 5
R797
@1K_0402_5%
RP151
4.7K_8P4R_1206_5%
JP49
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
@96212-1011S
1 2
DCD#1
12
R790
D D
C C
10_0402_5%
1
C788
18P_0402_50V8K
2
CLK_14M_SIOCLK_PCI_SIO
12
R791
@10_0402_5%
1
C789
@10P_0402_25V8K
2
R1173 10K_0402
+3VS
R1174 @10K_0402
R1291 10K_0402
+3VS
R1292 @10K_0402
LPC_AD0<26,44>
LPC_AD1<26,44>
LPC_AD2<26,44>
LPC_AD3<26,44>
LPC_FRAME#<26,44>
LPC_DRQ#1<26>
PCI_RST#<11,26,30,31,33,34,41,44>
+3VS
PCI_CLKRUN#<26,33,41,44>
CLK_PCI_SIO<26>
SIRQ<26,31,44>
+3VS
1 = M11
12
12
12
12
0 = UMA
M11_UMA_DET#
M11P_M11C_DET#
1 = M11P
0 = M11C
none = UMA
CLK_14M_SIO<24>
MDC_DET#<42>
+3VS
R798 10K_0402_5%
R796 1K_0402_5%
1 2
R792 10K_0402_5%
1 2
1 2
R795 10K_0402_5%
1 2
R793 10K_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#1
PCI_RST#
LPCPD#
1 2
R787 10K_0402_5%
PCI_CLKRUN#
CLK_PCI_SIO
SIRQ
IO_PME#
1 2
CLK_14M_SIO
MDC_DET#
U51
10
LAD0
12
LAD1
13
LAD2
14
LAD3
15
LFRAME#
16
LDRQ#
17
PCI_RESET#
18
LPCPD#
19
CLKRUN#
20
PCI_CLK
21
SER_IRQ
6
IO_PME#
9
CLK14
CLOCK
23
GPIO40
24
GPIO41
25
GPIO42
27
GPIO43
28
GPIO44
29
GPIO45
30
GPIO46
31
GPIO47
32
GPIO10
33
GPIO11/SYSOPT
34
GPIO12/IO_SMI#
35
GPIO13/IRQIN1
36
GPIO14/IRQIN2
40
GPIO23
8
VSS
22
VSS
43
VSS
52
VSS
LPC47N217_STQFP64
GPIO
POWER
+3VS
SERIAL I/F
FIR
LPC I/F
IRMODE/IRRX3
PARALLEL I/F
RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#
IRRX2
IRTX2
INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#
VTR
VCC
VCC
VCC
VCC
Base I/O Address
0 = 02Eh
*
1 = 04Eh
62
63
64
1
2
3
4
5
37
38
39
41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61
7
11
26
45
54
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRRX
IRTXOUT
IRMODE
C784
4.7U_0805_10V4Z
1 2
1
2
R794
1K_0402_5%
IRRX <43>
IRTXOUT <43>
IRMODE <43>
C785
0.1U_0402_16V4Z
1
2
1
2
C780
0.1U_0402_16V4Z
+3VS
C787
1
0.1U_0402_16V4Z
2
RI#1
CTS#1
DSR#1
+5V
60
U50
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
B B
A A
5
4
LPC_DRQ#1
LPC_FRAME#
PCI_CLKRUN#
SIRQ
CLK_PCI_SIO
PCI_RST#
CLK_14M_SIO
LPCPD#
IO_PME#
64
LAD0
2
LAD1
4
LAD2
7
LAD3
10
LPC_CLK_33
12
LDRQ1#
24
LDRQ0#
14
LFRAME#
16
CLKRUN#
19
SERIRQ
21
PCI_CLK
22
PCIRST#
23
SIO_14M
25
LPCPD#
47
IO_PME#
63
DLAD0
1
DLAD1
3
DLAD2
6
DLAD3
9
DLPC_CLK_33
11
DLDRQ1#
13
DLFRAME#
15
DCLKRUN#
18
DSER_IRQ
26
DSIO_14M
@LPC47N207-JN_STQFP64
LPC I/F
DLPC I/F
48
VTR
3.3V53.3V173.3V313.3V423.3V
3
GPIO10
GPIO11
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
RXD1
TXD1
DRSR1#
RTS1#/SYSOPT0
CTS1#
DTR1#/SYSOPT1
SERIAL I/F
IR
RI1#
DCD1#
IRTX2
IRRX2
IRMODE/IRRX3
GND08GND120GND229GND337GND445GND5
62
THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
27
M11_UMA_DET#
28
M11P_M11C_DET#
30
32
33
34
35
36
38
39
40
41
43
44
46
61
52
53
54
55
56
57
58
59
49
50
51
MDC_DET#
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRTXOUT
IRRX
IRMODE
1 2
R80 @10K_0402_5%
1 2
R991 @10K_0402_5%
1 2
R992 @10K_0402_5%
2
Compal Electronics, Inc.
Title
LPC SUPER I/O VIA VT1211
Size Document Number Re v
LA-2411
Date: Sheet
星期三 七
07, 2004
月
1
of
38 65,
0.1
Page 39
A
1 1
B
C
D
E
FM1
EMI Clip PAD
1
EP1
EMI-126X142
1
CF1
CF14
CF2
1
CF15
1
2 2
H1
HOLEA
1
H6
HOLEA
1
H16
HOLEA
1
3 3
H21
HOLEA
1
H26
HOLEA
1
1
1
1
CF3
CF16
H2
HOLEA
H7
HOLEA
H12
HOLEA
H17
HOLEA
H22
HOLEA
H27
HOLEA
1
1
CF5
CF4
CF6
1
1
1
CF18
CF17
CF19
1
1
1
H3
H4
HOLEA
HOLEA
1
H8
HOLEA
1
H13
HOLEA
1
H18
HOLEA
1
H23
HOLEA
1
H28
HOLEA
1
H9
HOLEA
1
H14
HOLEA
1
H19
HOLEA
1
H24
HOLEA
1
1
1
1
1
1
1
1
FM3
FM2
FM5
1
CF8
CF21
FM6
1
CF13
CF11
CF9
1
1
CF22
1
1
CF10
CF23
CF12
1
1
1
1
CF24
1
1
FM4
CF7
1
1
CF20
1
1
H5
HOLEA
1
H10
HOLEA
1
H20
HOLEA
1
H30
H31
HOLEA
HOLEA
1
1
4 4
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SPR Connector
星期三 七月
LA-2411
E
0.1
of
39 65, 07, 2004
Page 40
5
D D
4
3
2
1
+5VALW +5VALW +5VALW
(GRN) (GRN) (GRN)
R889
360_0603_5%
1 2
21
D62
HT-170UYG-DT GRN_0805
C C
CAPSLED#<44>
NUMLED#<44>
R882
360_0603_5%
1 2
21
D63
HT-170UYG-DT GRN_0805
MEDIA_LED#<44>
+3VALW+3VALW
R923
360_0603_5%
1 2
B B
R925
360_0603_5%
1 2
EN_WL#EN_BT#
TP_DATA<44>
TP_CLK<44>
EN_WL#<44>
EN_BT#<44>
WL_ON_LED#<44>
BT_ON_LED#<44>
PWR_SUSP_LED#<44>
PWR_LED#<44>
BATT_FULL_LED#<44>
BATT_CHGI_LED#<44>
R890
360_0603_5%
1 2
21
D65
HT-170UYG-DT GRN_0805
+5VALW
+5VS
TP_DATA
TP_CLK
EN_WL#
EN_BT#
WL_ON_LED#
BT_ON_LED#
E_MAIL_LED#<44>
JP53
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
+5VALW
(GRN)
R885
360_0603_5%
1 2
21
D60
HT-170UYG-DT GRN_0805
ACES_85201-2005
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Docu ment Number Rev
B
Date: Sheet
Compal Electronics, Inc.
LED INDICATOR
, 07, 2004
三七月
LA-2411
星期
1
40 65
of
0.1
Page 41
A
B
C
D
E
1 1
WL_ON<44>
PCI_PIRQD#<26,33>
CLK_PCI_MINI<26>
PCI_REQ#3<26>
PCI_AD31<26,31,33,34>
PCI_AD29<26,31,33,34>
PCI_AD27<26,31,33,34>
PCI_AD25<26,31,33,34>
WLAN_BT_DATA<42>
PCI_CBE#3<26,31,33,34>
PCI_AD23<26,31,33,34>
PCI_AD21<26,31,33,34>
PCI_AD19<26,31,33,34>
PCI_AD17<26,31,33,34>
PCI_CBE#2<26,31,33,34>
PCI_IRDY#<26,31,33,34>
PCI_CLKRUN#<26,33,38,44>
PCI_SERR#<26,31,33>
PCI_PERR#<26,31,33,34>
PCI_CBE#1<26,31,33,34>
PCI_AD14<26,31,33,34>
PCI_AD12<26,31,33,34>
PCI_AD10<26,31,33,34>
PCI_AD8<26,31,33,34>
PCI_AD7<26,31,33,34>
C280
0.1U_0402_10V6K
1
C269
+3VS
2
4.7U_0805_10V4Z
CLK_PCI_MINI
12
2 2
R302
@10_0402_5%
1
C275
@15P_0402_50V8J
2
0.1U_0402_10V6K
1
1
C270
2
2
1000P_0402_50V7K
C271
1
2
LAN RESERVED LAN RESERVED
WL_ON
D89 RB751V_SOD323
PCI_PIRQD#
W=40mils
TIP
21
CLK_PCI_MINI
PCI_AD5<26,31,33,34>
PCI_AD3<26,31,33,34>
+5VS
PCI_AD1<26,31,33,34>
3 3
+5VS
W=30mils
W=30mils
101
103
105
107
109
111
113
115
117
119
121
123
JP12
112
KEY KEY
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
127
AMP_1318644-1
127
128
RING
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
128
W=30mils
W=40mils
W=40mils
1 2
R301 100_0402_5%
W=40mils
PCI_PIRQC#
WLAN_PME#
PCI_AD18
PCI_AD22
PCI_AD18
+5VS
PCI_PIRQC# <26>
PCI_GNT#4 <26>PCI_REQ#4<26>
+3V
PCI_RST# <11,26,30,31,33,34,38,44>
PCI_GNT#3 <26>
WLAN_PME# <33,34,44,45>
WLAN_BT_CLK <42>
PCI_AD30 <26,31,33,34>
PCI_AD28 <26,31,33,34>
PCI_AD26 <26,29,31,33,34>
PCI_AD24 <26,31,33,34>
IDSEL : AD18
PCI_AD22 <26,31,33,34>
PCI_AD20 <26,31,33,34>
PCI_PAR <26,31,33,34>
PCI_AD18 <26,31,33,34>
PCI_AD16 <26,31,33,34>
PCI_FRAME# <26,31,33,34>
PCI_TRDY# <26,31,33,34>
PCI_STOP# <26,31,33,34>
PCI_DEVSEL# <26,31,33,34>
PCI_AD15 <26,31,33,34>
PCI_AD13 <26,31,33,34>
PCI_AD11 <26,31,33,34>
PCI_AD9 <26,31,33,34>
PCI_CBE#0 <26,31,33,34>
PCI_AD6 <26,31,33,34>
PCI_AD4 <26,31,33,34>
PCI_AD2 <26,31,33,34>
PCI_AD0 <26,31,33,34>
+3V
1
C272
0.1U_0402_10V6K
2
1
C273
2
1000P_0402_50V7K
4.7U_0805_10V4Z
C284
4.7U_0805_10V4Z
+5VS
1
C276
2
+3V
1
C285
2
0.1U_0402_10V6K
1
C274
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C278
C277
2
0.1U_0402_10V6K
1000P_0402_50V7K
1
C286
2
C281
4.7U_0805_10V4Z
+3VS
1
2
1
2
1
2
4 4
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Mini PCI Slot
LA-2411
星期三 七月
0.1
of
41 65, 07, 2004
E
Page 42
C303
4.7U_0805_10V4Z
+3VS
2
1
1
2
C304
0.1U_0402_10V6K
C954
1000P_0402_50V7K
+3V
1
2
1
C955
0.1U_0402_10V6K
2
C300
1000P_0402_50V7K
AC97_SDOUT<27,29,36>
+3VS
MDC Conn.
1
1
C301
0.1U_0402_10V6K
2
2
+3V
AC97_RST#<27,36>
JP17
1
MONO_OUT/PC_BEEP
3
GND
5
AUXA_RIGHT
7
AUXA_LEFT
9
CD_GND
11
CD_RIGHT
13
CD_LEFT
15
GND
17
3.3Vaux
19
GND
21
3.3Vmain
23
AC97_SDATA_OUT
25
AC97_RESET#
27
GND
29
AC97_MSTRCLK
ACES_88021-3000
@0.1U_0402_10V6K
1
C298
2
@1000P_0402_50V7K
AUDIO_PWDN
MONO_PHONE
Bluetooth Enable
AC97_SDATA_IN1
AC97_SDATA_IN0
1
C299
2
GND
USB Data+
USB Data-
PRIMARY DN
GND
AC97_SYNC
GND
AC97_BITCLK
+5VMDC
1 2
R319 0_0805_5%
C302
2
4
6
8
10
+5V
12
14
R323 10K_0402_5%
16
18
5Vd
20
22
R325 22_0402_5%
24
R326 22_0402_5%
26
28
30
12
@1000P_0402_50V7K
1 2
MD_SPK <36>
12
12
R327
@10_0402_5%
1 2
1
C305
@22P_0402_25V8K
2
+5VS
+3VS
R320
100K_0402_5%
1 2
+3V
MDC_DET# <38>
AC97_SYNC <27,29,36>
AC97_SDIN1 <27>
AC97_BITCLK <27,36>
RJ11 CONN.
FOXCONN_JM34613-L002-TR
3
L46
0_0603_5%
@220PF_3KV_1808
JP16
3
446
112
12
12
C977
2
5
12
MRING
TIP
5
6
L45
0_0603_5%
12
C978
JP47
1
1
2
2
MOLEX_53398_0290
@220PF_3KV_1808
BT CONNECTOR
+3VALW
S
G
BT_ON#<44>
2
Q99
SI2301DS_SOT23
D
1 3
USB5+
USB5-
ACES_87213-0800
JP43
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
BT_VCC
C957
10U_0805_10V3M
1
2
1
C958
0.1U_0402_10V6K
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
MDC , Bluetooth & USB CONN.
星期三 七月
LA-2411
of
42 65, 07, 2004
0.1
R981 0_0402_5%
USB20P5+<27>
USB20P5-<27>
WLAN_BT_DATA<41>
WLAN_BT_CLK<41>
1 2
R980 0_0402_5%
1 2
R21 0_0402_5%
1 2
R22 0_0402_5%
1 2
BT_VCC
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Page 43
5
4
3
2
1
INT_KBD CONN.
KSI[0..7]
KSO[0..15]
D D
C C
(Right)
KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSI4
KSO2
KSO1
KSO0
KSI5
KSI6
KSI7
(Left)
JP13
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
ACES_85202-2405
KSI[0..7] <44>
KSO[0..15] <44>
CP1
KSI2
KSO9
2
KSI3
3
KSO8
4 5
100P_1206_8P4C_50V8
CP2
KSO7
KSO6
2
KSO5
3
KSO4
4 5
100P_1206_8P4C_50V8
CP3
KSO0
KSI5
2
KSI6
3
KSI7
4 5
100P_1206_8P4C_50V8
CP4
KSO3
KSI4
2
KSO2
3
KSO1
4 5
100P_1206_8P4C_50V8
CP5
KSI0
KSO11
2
KSO10
3
KSI1
4 5
100P_1206_8P4C_50V8
CP6
KSO15
KSO14
2
KSO13
3
KSO12
4 5
100P_1206_8P4C_50V8
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
EC_ON<44>
Power BTN
EC_ON
Q112
@2N7002_SOT23
SW9
2
4
ESE11MV9_4P
ON/OFFBTN#
+3VALW
12
R306
470_0402_5%
1 2
R307 0_0402_5%
13
D
2
G
S
1
3
D30 @PSOT03C
D28
1
DAN202U_SC70
2
22K
Q21
DTC124EK_SOT23
3
2
R305 100K_0402_5%
1 2
3
2
13
22K
1000P_0402_50V7K
LID_SW# <44>
ON/OFF#
1
C289
2
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
Vishay = 47 Ohm
Agilent = 0 Ohm
+3VALW
ON/OFF# <44>
EC_PWR_ON# <48>
12
D29
RLZ20A_LL34
1
C291
2
10U_0805_10V4Z
+3VS
R1204
0_1206_5%
1 2
(30mil)
1
C294
0.1U_0402_16V4Z
2
D27 @PSOT03C
+IR_3VS
SW1
ON/OFFBTN#
2
3
TC010-PS11CET_5P
2
4
5
FIR Module
Vishay populate two 4.7 Ohm resistor
Agilent populate one 4.7 Ohm resistor
(60mil)
R309 4.7_1206_5%
+3VS
1 2
1 2
R308 @4.7_1206_5%
U12
2
IRED_C
4
RXD
6
VCC
8
GND
HSDL-3603-007_9P
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT
IRED_A
SD/MODE
MODE
1
3
TXD
GND
1
3
5
7
9
+IR_ANODE
(60mil)
IRTXOUT
IRMODEIRRX
C292
1 2
+
@150U_D2_6.3VM
IRTXOUT <38>
IRMODE <38>IRRX<38>
B B
SW8
PTC010-PS11CET_5P
2
KSO16 KSO16 KSO16 KSO16
4
A A
5
1
3
5
KSI0 <44> KSI1 <44> KSI2 <44> KSI3 <44>KSO16<44>
Internet ButtonConsole/E-MAIL Button USER Button1 USER Button 2
SW2
PTC010-PS11CET_5P
2
4
4
1
3
5
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SW10
PTC010-PS11CET_5P
2
4
5
SW11
1
3
2
PTC010-PS11CET_5P
2
4
5
Title
Size Document Number Rev
Date: Sheet
星期三 七月
1
3
Compal Electronics, Inc.
KBD,ON/OFF,T/P,LED & FIR
LA-2411
1
0.1
of
43 65, 07, 2004
Page 44
A
+3VALW
1000P_0402_50V7K
+3VALW
FBM-L11-160808-800LMT_0603
1 1
2 2
TP_DATA
TP_CLK
PS2_DATA
PS2_CLK
EC_SMD_2
EC_SMC_2
3 3
4 4
EC_SMD_1
EC_SMC_1
+3VALW
10P_0402_25V8K
32.768KHZ_12.5P_1TJS125DJ2A073
1000P_0402_50V7K
1
C1072
C1071
2
L32
C326
0.1U_0402_10V6K
L33
FBM-L11-160808-800LMT_0603
CLK_PCI_EC
12
R337
@10_0402_5%
1
C329
@15P_0402_50V8J
2
R1162 10K_0402_5%
KBD_DATA
1 2
KBD_CLK
1 2
R1163 10K_0402_5%
R1169 10K_0402_5%
1 2
1 2
R1170 10K_0402_5%
R1171 10K_0402_5%
1 2
1 2
R1172 10K_0402_5%
RP23
FSEL#
1 8
SELIO#
2 7
FRD#
3 6
EC_SMI#
4 5
10K_0804_8P4R_5%
SD309100200
RP24
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
1 2
1 2
1 2
C330
LID_SW#
1
2
1 2
R342 20K_0402_5%
R344 47K_0402_5%
R1123 @10K_0402_5%
R1299 @10K_0402_5%
1
C318
2
4.7U_0805_6.3V6K
12
2
1
ECAGND
12
+3VALW
+5VALW
VR_ON
SUSP#
SYSON
1 2
R340
@20M_0603_5%
1
IN
2
A
0.1U_0402_10V6K
1
C319
2
1
C327
1000P_0402_50V7K
2
+5VS
+5VS
+5VS
CRY2CRY1
*
4
Y3
OUT
NC3NC
0.01U_0402_16V7K
1
1
C320
2
2
0.1U_0402_10V6K
+EC_AVCC
+3VALW
R341
0_0402_5%
1 2
1
C331
12P_0402_50V8J
2
1
C321
+3VALW
2
R332
1 2
47K_0402_5%
C1070 0.1U_0402_10V6K
SCI#
SCI#<27>
KSO[0..15]<43>
+3VALW
+3VS
1 2
KBRST#<27>
KSI[0..7]<43>
100K_0402_5%
KB910 87591
R341
R340 no stuff020M
B
R926 0_0603_5%
1 2
R927 @0_0603_5%
1 2
1
C323
4.7U_0805_6.3V6K
LPC_FRAME#<26,38>
LPC_AD0<26,38>
LPC_AD1<26,38>
LPC_AD2<26,38>
LPC_AD3<26,38>
CLK_PCI_EC<26>
R984 @0_0402_5%
GA20<27>
R1250
1 2
TP_DATA<40>
LID_SW#<43>
BT_ON#<42>
EC_SMI#<27>
ACT_LED#<30>
EN_WL#<40>
EC_SWI#<27>
EN_WOL#<33>
EN_BT#<40>
CARD_LED#<31>
EC_RSMRST#<27>
ENBKL<10,17>
SIRQ<26,31,38>
1 2
TP_CLK<40>
SYSON<47>
SUSP#<45,47>
VR_ON<53>
BKOFF#<25>
FSEL#<45>
KSI[0..7]
KSO[0..15]
2
120K
B
C
+3VALW
0.1U_0402_10V6K
1
C324
2
7
8
9
15
14
13
CLK_PCI_EC
EC_RST#
GA20
KBRST#
EC_TINIT# PCI_RST#
10
18
19
22
23
31
5
6
KSI0
71
KSI1
72
KSI2
73
KSI3
74
KSI4
77
KSI5
78
KSI6
79
KSI7
80
KSO0
49
KSO1
50
KSO2
51
KSO3
52
KSO4
53
KSO5
56
KSO6
57
KSO7
58
KSO8
59
KSO9
60
KSO10
61
KSO11
64
KSO12
65
KSO13
66
KSO14
67
KSO15
68
105
EC_TCK
106
EC_TDO
107
EC_TDI
108
EC_TMS
109
KBD_CLK
110
KBD_DATA
111
PS2_CLK
114
PS2_DATA
115
TP_CLK
116
TP_DATA
117
LID_SW#
118
119
CRY1
158
CRY2
160
EC_SMI#
62
63
69
70
75
76
SYSON
148
SUSP#
149
VR_ON
155
156
3
4
27
28
FSEL#
173
174
47
PC87591L-VPCN01 A2_LQFP176
16
U15
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#
IOPD3/ECSCI#
GA20/IOPB5
KBRST/IOPB6
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
TINT#
TCK
TDO
TDI
TMS
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
32KX1/32KCLKIN
32KX2
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
SEL0#
SEL1#
CLK
VDD
Host interface
Key matrix scan
JTAG debug port
PS2 interface
PORTJ-2
PORTM
GND117GND235GND346GND4
R959 10K_0402_5%
+EC_AVCC
123
VCC134VCC245VCC3
122
159
ECAGND
R960 10K_0402_5%
95
136
157
166
VCC4
VCC5
VCC6
AD Input
DA output
PWM
or PORTA
PORTB
IOPB7/RING/PFAIL/RESET2
PORTC
PORTD-1
IOPD2/EXWINT24/RESET2
PORTE
IOPE7/CLKRUN/EXWINT46
PORTH
PORTI
PORTJ-1
PORTD-2
PORTK
PORTL
AGND
GND5
GND6
GND7
96
167
137
1 2
1 2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
161
AVCC
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPJ1/WR0
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#
NC212NC320NC421NC585NC686NC791NC892NC997NC10
NC1
11
R986 0_0402_5%
C
VBAT
DP/AD8
DN/AD9
IOPC0
IOPH6/A6
IOPH7/A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
IOPJ0/RD
SELIO#
IOPD4
IOPD5
IOPD6
IOPD7
IOPK0/A8
IOPK1/A9
AD0
AD1
AD2
AD3
DA0
DA1
DA2
DA3
98
R345 0_0402_5%
R1175
1
C322
0.1U_0402_10V6K
2
81
BID
82
83
ADP_IR
84
87
88
89
90
93
94
99
100
101
102
32
33
36
37
38
39
40
43
KSO16
153
EC_UTXD
154
EC_USCLK
162
EC_SMC_1
163
EC_SMD_1
164
165
168
EC_SMC_2
169
EC_SMD_2
170
FANSPEED1
171
172
175
176
1
AC_IN
26
29
30
2
44
24
25
KBA0
124
KBA1
125
KBA2
126
KBA3
127
KBA4
128
KBA5
131
KBA6
132
KBA7
133
ADB0
138
ADB1
139
ADB2
140
ADB3
141
ADB4
144
ADB5
145
ADB6
146
ADB7
147
FRD#
150
FWR#
151
SELIO#
152
41
42
54
55
KBA8
143
KBA9
142
KBA10
135
KBA11
134
KBA12
130
KBA13
129
KBA14
121
KBA15
120
KBA16
113
KBA17
112
KBA18
104
KBA19
103
48
SCI#
12
@0_0402_5%
E_MAIL_LED# <40>
MEDIA_LED# <40>
BATT_CHGI_LED# <40>
BATT_FULL_LED# <40>
PWR_SUSP_LED# <40>
PWR_LED# <40>
+3VALW
+RTCVCC
BATT_TEMPA <49>
1 2
0.01U_0402_16V7K
C325
BATT_OVP <50>
WL_ON_LED# <40>
BT_ON_LED# <40>
DAC_BRIG <25>
EN_FAN1 <7>
EN_FAN2 <7>
IREF <50>
INVT_PWM <25>
BEEP# <37>
ACOFF <50>
PM_BATLOW# <27>
EC_ON <43>
LID_OUT# <27>
KSO16 <43>
EC_SMC_1 <45,49>
EC_SMD_1 <45,49>
PCI_RST# <11,26,30,31,33,34,38,41>
PWRBTN_OUT# <27>
EC_SMC_2 <7>
EC_SMD_2 <7>
FANSPEED1 <7>
PME_EC# <33,34,41,45>
EC_THERM# <27>
FANSPEED2 <7>
WL_ON <41>
SLP_S3# <27>
ON/OFF# <43>
SLP_S5# <27>
PCI_CLKRUN# <26,33,38,41>
FRD # <45>
FWR# <45>
SELIO# <45>
CAPSLED# <40>
NUMLED# <40>
FSTCHG <50>
ECAGND
ADB[0..7]
KBA[0..19]
D
R331
1 2
1
10K_0402_5%
C328
0.22U_0603_10V7K
2
ADB[0..7] <45>
KBA[0..19] <45>
+3VALW
1 2
AC_IN
ADP_I <49,50>
0.1U_0402_10V6K
R338
BADDR1(KBA3) BADDR0(KBA2)
0
0
*
11
IRE
*
OBD 0
DEV 0
PROG
SHBM(KBA5)=1: Enable shared memory with host BIOS
TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
D
C911
0
1
01
ENV0 (KBA0) TRIS (KBA4)
Title
Size Document Number Rev
Date: Sheet
E
For EC Tools
+5VALW
JP52
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
@96212-1011S
ACIN <27,48,51>
+3VALW
+3VALW
12
R929
100K_0402_5%
BID
12
1
R931
0_0402_5%
2
10K_0402_5%
2 1
D36 RB751V_SOD323
R1251
1 2
@100K_0402_5%
KBA0
(ENV1)
KBA1
(BADDR0)
KBA2
(BADDR1)
KBA3
KBA4
(SHBM)
KBA5
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
KSO16
EC_UTXD
EC_USCLK
1 2
R1252 @1K_0402_5%
1 2
R333 1K_0402_5%
1 2
R334 @1K_0402_5%
1 2
R335 1K_0402_5%
1 2
R1253 @1K_0402_5%
1 2
R336 1K_0402_5%
I/O Address
Index
Data
2E 2F
4E
4F
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
Reserved
ENV1 (KBA1)
0
1
1
0
1
1
0
0
0
0
Compal Electronics, Inc.
KBD EC CTRL-ENE910
星期三 七月
LA-2411
44 65, 07, 2004
E
0.1
of
Page 45
OUTPUT
3
11
1
+5VALW
20
D0
VCC
D14Q1
D27Q2
D38Q3
D413Q4
D514Q5
D617Q6
D718Q7
CP
MR
GND
10
U17
Q0
C333
@0.1U_0402_16V7K
1 2
2
5
6
9
12
15
16
19
@SN74HCT273PW_TSSOP20
+3VALW
12
R12
@100K_0402_5%
ADB0
ADB1
AA
SELIO#<44>
ADB[0..7]<44>
KBA[0..19]<44>
ADB[0..7]
KBA[0..19]
KBA2
SELIO#
+5VALW
+3VALW
14
1
P
A
2
B
G
7
R352
1 2
@20K_0402_5%
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
AA
3
O
LARST#
U18ASN74LVC32APWLE_TSSOP14
C334
1 2
@1U_0603_10V6K
U19
KBA18
1
A18
KBA16
2
A16
KBA15
3
A15
KBA12
4
A12
KBA7
5
A7
KBA6
6
A6
KBA5
7
A5
KBA4
8
A4
KBA3
9
A3
KBA2
10
A2
KBA1
11
A1
KBA0
12
A0
ADB0
13
DQ0
ADB1
14
DQ1
ADB2
15
DQ2
16
VSS
512K8-90_PLCC32
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
FSEL#<44>
FRD#<44>
FSEL#
FRD#
FWE#
U20
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
READY/BUSY#
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
@SST39VF080-70_TSOP40
VCC0
VCC1
RP#
NC0
NC1
GND0
GND1
32
VDD
WE#
DQ7
DQ6
DQ5
DQ4
DQ3
D0
D1
D2
D3
D4
D5
D6
D7
NC
A17
A14
A13
A11
OE#
A10
CE#
FWE#
31
KBA17
30
KBA14
29
KBA13
28
KBA8
27
A8
KBA9
26
A9
KBA11
25
FRD#
24
KBA10
23
FSEL#
22
ADB7
21
ADB6
20
ADB5
19
ADB4
18
ADB3
17
31
30
ADB0
25
ADB1
26
ADB2
27
ADB3
28
ADB4
32
ADB5
33
ADB6
34
ADB7
35
RESET#
10
11
12
29
38
23
39
2
C336
0.1U_0402_10V6K
1
+3VALW
1 2
R360
@100K_0402_5%
+3VALW
SN74LVC32APWLE_TSSOP14
1
C338
0.1U_0402_10V6K
2
+3VALW
FWE#
U18C
+3VALW
12
+3VALW
14
P
A
8
O
B
G
7
R354
10K_0402_5%
9
10
1 3
D
Q29 2N7002 1N_SOT23
SUSP# <44,47>
2
G
EC_FLASH# <27>
S
FWR# <44>
WLAN_PME#<33,34,41,44>
ONBD_LAN_PME#<33,34,41,44>
MDM_PME#<33,34,41,44>
1394_PME#<33,34,41,44>
0.1U_0402_10V6K
EC_SMC_1<44,49>
EC_SMD_1<44,49>
C337
1
2
+3VALW
12
R356
4.7K_0402_5%
PME_EC# <33,34,41,44>
+5VALW +5VALW
12
8
7
6
5
12
R359
100K_0402_5%
U21
VCC
WC
SCL
SDA
AT24C164-10SC_SO8
GND
1
A0
2
A1
3
A2
4
12
R357
100K_0402_5%
R358
100K_0402_5%
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BIOS & EC I/O Port
星期三 七月
LA-2411
of
45 65, 07, 2004
0.1
Page 46
+3VS
SN74LVC32APWLE_TSSOP14
12
R601
10K_0402_5%
VCORE_PWRGD<54>
R605
1M_0402_5%
12
12
13
12
R1107
1K_0402_5%
+3VALW
A
B
14
U18D
P
G
7
O
11
SUSP<47,53>
R1106
1 2
330K_0402_5%
VTT_PWRGD <24,27>
0.1U_0402_16V7K
13
D
2
G
S
Q111
@2N7002_SOT23
+3VALW +3VALW
14
P
3
O4I
G
C606
1
2
U32B
7
SN74LVC14APWLE_TSSOP14
+3VALW
14
P
5
7
SN74LVC14APWLE_TSSOP14
+2.5VS
12
13
2
G
O6I
G
U32C
R608
1K_0402_5%
D
Q52
2N7002_SOT23
S
1 2
330K_0603_5%
R603
SUSP
12
R610
47K_0402_5%
2
G
NB_PWRGD <8,10>
0.47U_0603_10V7K
1
C607
2
13
D
Q110
@2N7002_SOT23
S
14
P
9
O8I
G
U32D
7
SN74LVC14APWLE_TSSOP14
+3VALW
14
P
11
G
7
R604 47_0603_5%
O10I
U32E
SN74LVC14APWLE_TSSOP14
1 2
12
R606
10K_0402_5%
SB_PWRGD <27>
1
1
C115
@68P_0402_50V8K
2
2
1
D20
@DAN217_SOT23
2
3
+3VS
JP7
1
2
TV_LUMAL
TV_CRMAL
TV_COMPSL
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
5
6
7
SUYIN_35138S-07T1-DF
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
POWER GOOD & P/S2 CKT
星期三 七月
LA-2411
of
46 65, 07, 2004
0.1
1
D19
TV_OUT CONNECTOR
TV_LUMA<11,17>
TV_CRMA<11,17>
TV_COMPS<11,17>
TV_LUMA
TV_CRMA
TV_COMPS
75_0402_5%
R188
12
R189
75_0402_5%
75_0402_5%
12
R190
12
1
C111
C110
2
@68P_0402_50V8K
@68P_0402_50V8K
1
2
@DAN217_SOT23
L4 CHB1608B121_0603
1 2
L7 CHB1608B121_0603
1 2
L8 CHB1608B121_0603
1 2
1
C112
@68P_0402_50V8K
2
@68P_0402_50V8K
2
C113
3
1
C114
2
@68P_0402_50V8K
Page 47
A
B
C
D
E
+2.5VALW to +2.5V Transfer
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C347
0.1U_0402_10V6K
+2.5V
C343
1
C344
10U_0805_6.3V6M
2
1
2
+2.5VALW
+12VALW
12
2
G
R362
100K_0402_5%
13
D
Q31
2N7002 1N_SOT23
S
1 1
SYSON#
1
2
8
7
6
C341
5
10U_0805_6.3V6M
U22
D
D
D
D
SI4800DY_SO8
1
2
+3VALW to +3V Transfer
+12VALW
12
R902
2
G
95.3K_0603_1%
13
D
Q74
2N7002 1N_SOT23
S
2 2
SYSON#
1
2
8
7
6
C351
5
10U_0805_6.3V6M
U25
D
D
D
D
SI4800DY_SO8
1
2
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C356
0.1U_0402_10V6K
+3V+3VALW
C354
1
C355
10U_0805_6.3V6M
2
1
2
+5VALW to +5V Transfer
+12VALW +12VALW
12
R904
47K_0402_5%
3 3
SYSON# SUSP
13
D
Q76
2
2N7002 1N_SOT23
G
S
1
2
8
7
6
C624
5
10U_0805_6.3V6M
U36
D
D
D
D
SI4800DY_SO8
1
2
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C627
0.1U_0402_10V6K
+5V+5VALW
1
2
C625
1
C626
10U_0805_6.3V6M
2
+2.5V to +2.5VS Transfer
+12VALW
12
R903
100K_0402_5%
13
2
G
D
Q75
2N7002 1N_SOT23
S
SUSP SUSP
+2.5VALW
1
C357
2
10U_0805_6.3V6M
U26
8
D
7
D
6
D
5
D
SI4800DY_SO8
+2.5VS
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C360
0.1U_0402_10V6K
2
1
2
C358
1
C359
10U_0805_6.3V6M
2
(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
+3VALW to +3VS Transfer
R363
95.3K_0603_1%
SUSP
2
G
+12VALW
12
13
D
Q32
2N7002 1N_SOT23
S
+3VALW
1
C342
2
10U_0805_6.3V6M
U23
8
D
7
D
6
D
5
D
SI4800DY_SO8
1
S
2
S
3
S
4
G
1
C348
0.1U_0402_10V6K
2
+3VS
1
C345
2
0.1U_0402_10V6K
1
C346
10U_0805_6.3V6M
2
+5VALW to +5VS Transfer
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C844
0.1U_0402_10V6K
2
+5VS
1
2
C352
1
C353
10U_0805_6.3V6M
2
R901
6.8K_0402_5%
2
G
12
13
D
S
1
C350
2
10U_0805_6.3V6M
Q73
2N7002 1N_SOT23
+5VALW
U24
8
D
7
D
6
D
5
D
SI4800DY_SO8
+1.5VSP to +1.5VS Transfer
12
R1101
68K_0402_5%
13
D
Q108
2
G
2N7002 1N_SOT23
S
Place close to PJP4
L
+1.5VSP +1.5VS+12VALW
1
C959
2
10U_0805_6.3V6M
SYSON#<35>
SYSON<44>
SUSP<46,53>
SUSP#<44,45>
U56
8
D
7
D
6
D
5
D
SI4800DY_SO8
SYSON#
SYSON
SUSP
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C962
0.1U_0402_10V6K
2
1
2
C960
1
C961
10U_0805_6.3V6M
2
(6A,240mils ,Via NO.= 12)
+5VALW
12
R369
10K_0402_5%
13
D
Q34
2
2N7002 1N_SOT23
G
S
+5VALW
12
R373
10K_0402_5%
13
D
Q38
2
G
2N7002 1N_SOT23
S
Discharge circuit
+1.8VS
2
G
12
R375
470_0402_5%
13
D
Q40
2N7002 1N_SOT23
S
12
R374
470_0402_5%
13
D
2
G
Q39
2N7002 1N_SOT23
S
A
4 4
SUSP SUSP
+2.5VS
12
R376
470_0402_5%
13
D
2
G
Q41
2N7002 1N_SOT23
S
SUSPSU SP
SUSP
B
2
G
+3VS +5VS+1.25VS
12
13
D
S
R377
470_0402_5%
Q42
2N7002 1N_SOT23
2
G
12
R378
470_0402_5%
13
D
Q43
2N7002 1N_SOT23
S
+1.2VS_VGA
12
R1116
470_0402_5%
13
D
2
G
S
C
Q115
2N7002 1N_SOT23
SUSP
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R1094
470_0402_5%
13
D
2
G
Q102
2N7002 1N_SOT23
S
SUSP SYSON# SYSON#SYSON#
+5V+1.5VS +3V
12
R1095
470_0402_5%
13
D
Q103
2
G
2N7002 1N_SOT23
S
D
12
R1102
470_0402_5%
13
D
Q109
2
G
2N7002 1N_SOT23
S
Title
Size Document Number Rev
Date: Sheet
星期三 七月
+2.5V
12
R372
470_0402_5%
13
D
Q36
2
G
2N7002 1N_SOT23
S
Compal Electronics, Inc.
DC/DC Circuits
LA-2411
47 65, 07, 2004
E
0.1
of
Page 48
A
B
C
D
E
Detector
PR9
22K_0603_1%
12
PC10
1000P_0603_16V7K
VL
Vin Detector
18.234 17.841 17.449
17.597 17.210 16.813
PR4
1M_0603_0.5%
1 2
VS
8
5
P
+
7
O
6
-
G
PU1B
4
LM393M_SO8
PR14
10K_0603_5%
PR1
10K_0603_5%
1 2
PD22
12
RB751V_SOD323
PD1
12
RB751V_SOD323
RLZ4.3B_LL34
12
RTCVREF
3.3V
12
PC7
0.1U_0603_16V7K
VL
DC_IN
12
12
PZD1
PR2
1M_0402_1%
PU1A
LM393M_SO8
1
O
PR7
10K_0805_5%
12
8
3
P
+
2
-
G
4
12
PR10
10K_0603_5%
12
PC8
12
VS
1000P_0603_16V7K
1 2
12
PR8
1K_0603_5%
PACIN
PR12
10K_0603_5%
PC5
0.01U_0603_50V7K
D
PQ46
S
ACIN <27,46,53>
PACIN <52>
12
PR191
499K_0603_1%
13
2
G
2N7002_SOT23
B+
12
12
PR5
PR192
1 2
47K_0603_5%
13
100K
DTC115EKA_SOT23
100K
PR3
432K_0603_1%
499K_0603_1%
PACIN
PQ47
2
12
+5VALW
PC6
1000P_0402_50V7K
1 1
PCN1
1
3
G
2
4
G
SINGA_2DC-G213-B04
2 2
CHGRTC
EC_PWR_ON#<45>
BATT+
PR230
1 2
200_0603_5%
RB751V_SOD323
CHGRTCP
100K_0603_1%
1 2
22K_0603_5%
3 3
4 4
1
2
PD8
PR38
PR39
PR43
1 2
200_0603_5%
12
12
RTCVREF
ADPIN
12
0.22U_1206_25V7K
3.3V
12
PC23
10U_0805_10V4Z
PC17
12
PC1
3
12
PC2
100P_0603_50V8J
1000P_0402_50V7K
2
PU3 G920AT24U_SOT89
OUT
GND
1
PL1
FBM-L18-453215-900LMA90T_1812
ADPIN
1 2
PC3
DC_IN
PD7
1N4148_SOD80
1 2
12
PR31
47_1206_5%
13
PQ2
TP0610T_SOT23
12
PC18
0.1U_0805_25V7K
12
PR41
200_0603_5%
2
IN
N2
12
PC22
1U_0805_50V4Z
12
100P_0603_50V8J
PD6
1N4148_SOD80
VS
DC_IN
PC4
1000P_0402_50V7K
12
2 1
12
N3
PD10
@RLZ16B_LL34
PR27
1 2
1.5K_1206_5%
PR28
1 2
1.5K_1206_5%
PR29
1 2
1.5K_1206_5%
DC_IN
12
PR6
82.5K_0603_0.1%
1 2
12
12
PC9
B+
PR11
0.047U_0603_16V7K
19.6K_0603_0.1%
DCSRD<52>
MAINPWON<7,51,53>
ACIN
Precharge detector
15.8 16.339 15.274
13.692 14.145 13.166
BATT
detector
11.489 11.852 11.133
9.380 9.658 9.025
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
星期三 七月
Detector
E
0.1
of
48 65, 07, 2004
Page 49
A
B
C
D
+3VALWP
VMB
12
PC11
1000P_0402_50V7K
PL2
1 2
C8B BPH 853025_2P
ADP_I<46,52>
BATT_TEMPA <46>
12
VREF
PC12
0.01U_0603_50V7K
1 2
BATT+
PR22
1 2
@11.5K_0603_1%
PR23
@200K_0603_1%
PR25
@100K_0603_1%
12
12
1 2
@75K_0603_1%
12
PC14
@1000P_0603_50V7K
PC97
@0.01U_0603_50V4Z
PR193
3
2
PR17
1 2
@1M_0603_1%
VS
8
PU2A
P
+
-
G
LM393M_SO8
4
VREF
12
PR21
@47K_0603_5%
13
D
S
PQ1
@2N7002_SOT23
1
O
12
PC15
@1000P_0603_50V7K
2
G
H_PROCHOT# <5,26>
PCN2
1 1
SUYIN_200275MR009G130ZL
2 2
BATT+
BATT+
SMD
SMC
GND
GND
1
2
TS_A
3
TS
EC_SMDA
4
EC_SMCA
5
6
7
PR18
100_0603_5%
12
PR19
100_0603_5%
12
PR24
1 2
6.49K_0603_1%
12
PR26
1K_0603_5%
1
3
PD3
@BAS40-04_SOT23
2
EC_SMD_1 <46,47>
EC_SMC_1 <46,47>
@BAS40-04_SOT23
PD4
1
3
2
1
@BAS40-04_SOT23
PD5
3
2
PH1 near main Battery CONN :
BAT. thermal protection at 80 degree C
Recovery at 45 degree C
+5VALWP
PR32
VL
3 3
2.15K_0603_1%
4 4
A
B
PR30
12
PC21
1000P_0402_50V7K
12
12
PH1
C
PR36
16.9K_0603_1%
1 2
12
PC20
10K_TH11-3H103FT_0603_1%
1U_0805_16V7K
12
PR42
150K_0402_1%
1 2
VS
8
5
P
+
6
-
G
4
PR40
12
150K_0402_1%
47K_0402_1%
12
7
O
PU2B
LM393M_SO8
VL
PC13
0.1U_0603_50V4Z
MAINPWON <7,50,53>
Title
Compal Electronics, Inc.
BATTERY CONN / OTP
Size Document Number Rev
Date: Sheet of
星期三
07, 2004
七月
D
49 65,
0.1
Page 50
A
DC_IN
PD30
1SS355_SOD323
12
PR240
1 2
12
1 1
1K_0603_5%
12
2
PC98
G
0.1U_0603_25V7K
2 2
<50>
DCSRD
PR195
47K_0402_5%
100K
2
13
D
PQ50
2N7002_SOT23
S
12
100K
IREF<46>
PR247
15K_0603_5%
13
PQ49
DTC115EKA_SOT23
PACIN<50>
ACOFF#
8
7
5
DTA144YKA_SC70
PQ48
10K
2
PACIN
1 2
3K_0603_5%
PD13
1 2
1SS355_SOD323
PR64
1 2
174K_0603_1%
47K
IREF=1.096*Icharge
PQ3
AO4407_SO8
4
1 3
150K_0603_1%
PR58
100K_0603_1%
PR53
1
2
36
2
G
PR65
PQ4
P2
AO4407_SO8
1
2
3 6
12
PR47
12
PC29
0.1U_0603_25V7K
200K_0603_5%
8
7
5
4
Throttling - 1 l e vel : ADP_I =1.4V
Throttling + 1 l eve l : ADP_I=1.14V
ADP_I<46,51>
12
12
12
12
PC32
13
D
S
PQ9
2N7002_SOT23
0.1U_0603_16V7K
PR56
10K_0603_1%
12
PR54
VREF
PC35
12
12
PC42
0.1U_0603_16V7K
IREF=0.44~3.3V
3 3
OVP voltage : LI
4S2P : 17.4V--> BATT_OVP= 1.94V
(BAT_OVP=0.1111 *VMB)
VL
12
8
PU5A
3
P
+
1
BATT_OVP<46>
4 4
A
0
2
-
G
LM358A_SO8
4
105K_0603_0.5%
VMB
12
12
PC43
0.1U_0603_50V4Z
12
PR72
PR69
340K_0603_1%
PR70
499K_0603_1%
P3
1 2
28.7K_0603_1%
4700P_0603_50V7K
1 2
1500P_0603_50V7K
0.1U_0603_16V7K
12
B
Iadp=0~6.5A
PR44
0.01_2512_1%(1W)
12
PR52
47K_0603_1%
PC33
PR57
1 2
1K_0603_1%
PC36
PR59
1 2
1K_0603_1%
PR62
12
10K_0603_1%
PC45
0.01U_0603_50V7K
B
12
PR66
95.3K_0603_0.1%
PR250
95.3K_0603_0.1%
PU4
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
FB2
6
VREF
7
FB1
8
-INE1
9
+INE1
10
OUTC1
11
OUTD
12
-INC1
MB3887_SSOP24
12
12
B+
PL3
FBM-L18-453215-900LMA90T_1812
1 2
24
+INC2
23
GND
22
CS
21
VCC(o)
20
OUT
19
VH
0.1U_0603_50V4Z
18
VCC
17
RT
16
-INE3
15
FB3
CTL
+INC1
FSTCHG<46>
47K_0603_1%
14
13
CHGSS
PC34
1 2
PR60
1 2
68K_0603_5%
PR63
1 2
DCSRD
+3VALWP
100K
2
12
PC24
4.7U_1206_25V6K
12
PR50
0_0603_5%
1 2
PC31
1 2
0.1U_0805_25V7K
1 2
0.1U_0805_25V7K
PC38
1 2
1500P_0603_50V7K
4.2V
12
PR68
47K_0603_5%
13
100K
DTC115EKA_SOT23
C
12
PC25
4.7U_1206_25V6K
PC30 2200P_0402_50V7K
PC37
2
G
PQ11
13
C
12
D
PQ10
2N7002_SOT23
S
CHGSS
PC26
0.1U_0805_25V7K
N18
SKS30-04AT_TSMA
PR67
12
143K_0603_0.1%
B++
12
PC28
2200P_0402_50V7K
36
241
PQ6
AO4407_SO8
578
LXCHRG
PL4
1 2
15U_SPC-1204P-150_4A_20%
PD14
2 1
D
PQ61 AO4407_SO8
1
2
3 6
8
7
5
4
1
2
3 6
PR48
1 2
47K_0603_5%
12
ACOFF#
13
PR61
1 2
0.02_2512_1%
PR51
10K_0603_5%
100K
2
100K
PQ8
DTC115EKA_SOT23
4
PC39
8
7
5
PQ5
AO4407_SO8
12
PC40
4.7U_1206_25V6K
DC_IN
ACOFF <46>
12
12
PC41
4.7U_1206_25V6K
4.7U_1206_25V6K
CC=0.4~3A
CV=16.8V(8 CELLS LI-ION)
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
CHARGER
星期三
07, 2004
七月
D
50 65,
BATT+
0.1
Page 51
A
B
C
D
B+
1
1 1
2 2
3 3
PJP23
1
JUMP_43X118
2
2
B++++
12
12
PC50
PC51
2200P_0402_50V7K
10U_SPC-1204P-100_4.5A_20%
+3VALWP
1
+
PC69
PC70
2
150U_D2_6.3VM
1 2
B++++
12
PC56
DH51DH5
SI4810DY_SO8
PC75
PC47
2200P_0402_50V7K
PQ15
LX5
PC57
1 2
PR96
PR100
470P_0805_100V7K
12
12
PC58
4.7U_1206_25V6K
PR80
0_0402_5%
DL5
PR243
698_0402_1%
1 2
12
12
4.7U_1206_25V6K
12
100P_0402_50V8J
PC48
1 2
0.1U_0805_25V7K
5
PQ12
12
1 2
47P_0402_50V8J
PR91
PR97
D8D7D6D
S1S2S3G
D8D7D6D
S1S2S3G
1 2
3.32K_0603_1%
1 2
SI4800DY-T1_SO8
4
5
PQ14
SI4810DY_SO8
4
1 2
1.27K_0603_1%
PR241
1.27K_0603_1%
PR85
1 2
0_0402_5%
12
PC71
100P_0402_50V8J
PR81
DH31
1 2
ACIN<27,46,50>
1 2
0_0402_5%
LX3
DL3
12
PC52
4.7U_1206_25V6K
4.7U_1206_25V6K
12
PL6
PC63
PR83
1M_0402_1%
1
+
2
@150U_D2_6.3VM
PD17
2 1
SKUL30-02AT_SMA
10K_0402_1%
BST31
PR74
PC67
12
0.47U_0603_16V7K
1 2
620_0402_5%
1 2
PR89
10K_0402_5%
@300K_0402_5%
VS
12
PR99
47K_0402_5%
12
PC79
@0.047U_0603_16V7K
PR92
DH3
PR242
12
12
PR75
0_0402_5%
1SS355_SOD323
12
PC60
0.1U_0805_25V7K
25
27
26
24
1
2
3
10
23
7
28
12
PC73
680P_0402_50V7K
PU6
BST3
DH3
LX3
DL3
CSH3
CSL3
FB3
SKIP#
SHDN#
TIME/ON5
RUN/ON3
2
3
1
12
PD16
DAP202U_SOT323
PC54
4.7U_1206_10V7K
ACIN
VL
VS
PD19
1 2
2N7002_SOT23
22
21
4
12OUT
VL
V+
GND
8
VL
5
VDD
18
BST5
16
DH5
17
LX5
19
DL5
20
PGND
14
CSH5
13
CSL5
12
FB5
15
SEQ
9
REF
6
SYNC
11
RST#
MAX1902EAI_SSOP28
PR94
1 2
@0_0402_5%
VL
12
PR101
806K_0603_1%
PQ51
2
G
+12VALWP
12
PR239
13
D
S
1 2
BST51
2.7K_1206_5%
PR95
0_0402_5%
PC61
12
12
4.7U_1206_25V6K
2.5VREF
PC72
4.7U_1206_10V7K
PC53
1 2
0.1U_0805_25V7K
PR77
0_0402_5%
1 2
PC68
12
0.47U_0603_16V7K
10.2K_0603_1%
10K_0402_1%
PR73
22_1206_5%
5
4
5
4
EC11FS2_SOD106
FLYBACKSNB
12
PQ13
D8D7D6D
SI4800DY-T1_SO8
S1S2S3G
D8D7D6D
PC65
S1S2S3G
PR82
PD15
12
12
PC46
4.7U_1206_25V6K
12
1 4
12
PR78
1.54K_0603_1%
47P_0402_50V8J
2M_0402_1%
PD18
2 1
12
PT1
9U_SDT-1204P-9R0-120_4.5A_20%
3 2
12
PR79
0_0402_5%
+5VALWP
1
+
PC76
2
SKS10-04AT_TSMA
150U_D2_6.3VM
MAINPWON <7,50,51>
12
PC80
0.47U_0603_16V7K
4 4
THIS SHEET OF EN GINE ERI NG DR AWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION I T CONTA INS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
A
B
INC.
C
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
星期三
07, 2004
七月
5V/3.3V/12V
D
of
51 65,
0.1
Page 52
5
D D
PQ16
SI4800DY_SO8
PC93
PD21
220U_D2_4VM
2 1
PL8
12
1
+
12
2
PC94
4.7U_SPC-1204P4R7_5.7A_20%
+1.5VSP +2.5VALWP
C C
SKS10-04AT_TSMA
4.7U_0805_6.3V6K
B B
+2.5VALWP
+1.25VSP
+VCCVIDP
PJP1
JUMP_43X118
112
PJP2
JUMP_43X118
112
PJP4
JUMP_43X118
112
PJP6
112
JUMP_43X39
2
PJP3
+2.5VALW
2
2
+1.25VS
2
+VCCVID
+5VALWP
+3VALWP
JUMP_43X118
112
PJP5
JUMP_43X118
112
2
2
D8D7D6D
S1S2S3G
+5VALW
+3VALW
3 6
241
4
12
578
5
PQ18
SI4810DY_SO8
4
PC81
2200P_0402_50V7K
12
PC83
4.7U_1206_25V6K
DAP202U_SOT323
0.1U_0805_25V7K
+5VALWP
12
PC89
PC183
4.7U_1206_25V6K
PD20
1 2
3
1 2
12
PR107
0_0603_5%
1
2
PR105
0_0603_5%
12
0_0603_5%
PR236
VCC_MAX1845
0_0603_5%
4.7U_1206_25V6K
PC84
PC90
0.1U_0805_25V7K
25
BST1
26
DH1
27
LX1
24
DL1
28
CS1
1
OUT1
2
FB1
11
ON1
PR248
1 2
@0_0402_5%
3
PR102
1 2
12
VCC_MAX1845
12
12
4
1U_0805_16V7K
V+
MAX1845EEI_QSOP28
GND
OVP
8
23
PR249
0_0402_5%
SKIP
6
12
PC91
22
VCC
PC99
PR103
0_0603_5%
12
9
VDD
UVP
BST2
DH2
LX2
DL2
CS2
OUT2
FB2
ON2
PGOOD
TON
ILIM2
ILIM1
REF
PR114
10
16.9K_0603_1%
PR115
12
15.4K_0603_1%
100K_0603_1%
0.22U_0603_16V7K
+5VALWP
1 2
PR104
20_0603_1%
PU7
21
19
18
17
20
16
15
14
12
7
5
13
3
12
12
PR116
12
PR106
0_0603_5%
1 2
12
PC88
4.7U_0805_10V4Z
0_0603_5%
1 2
12
PR117
100K_0603_1%
PC92
0.1U_0805_25V7K
12
PR108
2
SI4800DY_SO8
+5VALWP
PQ17
578
3 6
5
4
241
D8D7D6D
S1S2S3G
PQ19
SI4810DY_SO8
12
PJP24
JUMP_43X118
2
112
12
PC85
12
PC87
PC184
2200P_0402_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
PL9
4.7U_SPC-1204P4R7_5.7A_20%
1 2
12
PC211
@100P_0402_50V8K
12
12
1
PR267
@0_0603_5%
PR268
0_0603_5%
B+
1
12
PC96
4.7U_0805_6.3V6K
PC95
+
PD23
2 1
220U_D2_4VM
2
SKS10-04AT_TSMA
PJP8
2
+12VALWP
A A
112
JUMP_43X39
+12VALW
+1.8VSP
+1.2VS_VGA
5
PJP10
JUMP_43X118
112
PJP21
JUMP_43X118
112
PJP22
JUMP_43X118
112
2
+1.8VS
2
+VGA_CORE
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Compal Electronics, Inc.
Title
DDR POWER 2.5V & 1.5V
Size Document Number Rev
B
Date: Sheet
星期三 七月
1
of
52 65, 07, 2004
0.1
Page 53
A
B
C
D
E
PR262
1 2
10_0603_1%
12
PC203
1U_0603_6.3V6M
13
D
S
12
470P_0402_50V7K
PQ59
2N7002_SOT23
3.4K_0603_1%
PC207
PR266
PU31
7
OCSET
6
FB
3
GND
APW7057KC-TR_SOP8
1 2
PC210
0.1U_0402_16V7K
PR263
1 1
8.45K_0603_1%
1 2
SUSP
2 2
PR264
0_0402_5%
1 2
@0.1U_0402_16V7K
PC209
2
G
1 2
5
VCC
BOOT
UGATE
PHASE
LGATE
PR265
1.74K_0603_1%
1 2
1 2
1
2
8
4
PD43
1N4148_SOD80
1 2
12
PC208
0.1U_0402_16V7K
5
D8D7D6D
PQ58
S1S2S3G
SI4800DY-T1_SO8
4
2.2UH_SPC-1205P-2R2B_13A_30%
1 2
5
D8D7D6D
PQ60
SI4810DY_SO8
S1S2S3G
4
PL16
PC204
22U_1206_6.3V
12
12
PC205
PC206
22U_1206_6.3V
1
+
PC187
2
@220U_D2_4VM
M11P: 1.2V--> PR265=1.74K ohm
M9-X: 1.5V-->PR265=3K ohm
12
22U_1206_6.3V
1
+
2
PC188
220U_D2_4VM_R25
PJP20
2
JUMP_43X118
12
PC189
112
+1.2VS_VGA
10U_1206_25VAK
+3VALWP
VR_ON<46>
+5VALW
PR217
0_0603_5%
4.7U_0805_10V4Z
VID_PWRGD<5,56>
12
PC172
PR123
0_0603_5%
12
12
1 2
1
4
3
PR218
100K_0402_1%
PU27
IN
PG
EN
MIC5258_SOT23-5
OUT
GND
5
2
+VCCVIDP
12
PC171
4.7U_0805_10V4Z
+2.5V
2
PJP18
2
JUMP_43X118
3 3
PJP19
JUMP_43X118
+3VS
112
2
PC196
4.7U_0805_6.3V6K
1 2
100P_0402_50V8J
4 4
A
3
PC198
PU30
APL1085UC-TR_TO252
VIN
VOUT
ADJUST
1
1 2
2
12
PR258
100_0402_1%
12
PR261
44.2_0402_1%
+1.8VSP
12
PC195
10U_1206_6.3V7K
B
SUSP37,42
10U_1206_6.3V7K
PR259
0_0402_5%
1 2
PC200
@0.1U_0402_16V7K
1
1
PC193
12
PR257
1K_0402_1%
12
13
D
PQ57
2
2N7002_SOT23
G
S
12
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
12
PR260
1K_0402_1%
12
PC197
0.1U_0402_16V7K
PU29
VIN1VCNTL
2
GND
3
VREF
4
VOUT
APL5331KAC-TR_SO8
12
PC201
10U_1206_6.3V7K
6
5
NC
7
NC
8
NC
9
TP
12
PC194
1U_0603_6.3V6M
+1.25VSP
1
+
2
PC199
@150U_D2_6.3VM
D
+3VALW
Compal Electronics, Inc.
Title
VGA/1.8V/VCCVID/1.25V
Size Document Number Rev
B
Date: Sheet
星期三 七月
E
0.1
of
53 65, 07, 2004
Page 54
CORE_REF<57>
VID_PWRGD<5,55>
100K_0402_1%
61.9K_0402_1%
+5VS_CORE
PR147
1 2
10_0603_1%
PR246
PR170
0_0402_5%
1 2
@0_0402_5%
PC126
1000P_0402_50V7K
FB
2200P_0402_50V7K
12
PC139
12
PJP14
112
JUMP_43X79
VSSSENSE<5>
+5VS +5VS_CORE
1U_0603_16V6K
12
12
VCCSENSE<5>
12
2
12
PR140
12
PR144
PC123
PR149
0_0402_5%
PC136
470P_0402_50V7K
@1.74K_0402_1%
PR158
2.87K_0603_1%
OAIN-
@100P_0603_50V8G
CORE_REF
12
12
1 2
PR152
OAIN+
VCORE_PWRGD<48>
PC142
1 2
1 2
30.1K_0603_1%
PR138
@0_0402_5%
PR139
0_0402_5%
12
0.22U_0603_16V7K
PC114
+VCCVID
@100K_0402_1%
VID5
<5>
VID4
<5>
VID3
<5>
VID2
<5>
VID1
<5>
VID0
<5>
12
PR137
1 2
270P_0402_50V7K
12
PC122
PR109
1 2
1 2
PR2200_0402_5%
1 2
PR2210_0402_5%
1 2
PR2220_0402_5%
1 2
PR2230_0402_5%
1 2
PR2240_0402_5%
1 2
PR2250_0402_5%
1 2
PC180
12
100P_0402_50V8J
PR160
1 2
20K_0402_1%
PQ33
PU9
1
TIME
2
TON
6
SHDN#
8
REF
9
ILIM
10
VCC
12
CCV
11
GND
13
GNDS
14
CCI
15
FB
17
OAIN+
16
OAIN-
19
D5
20
D4
21
D3
22
D2
23
D1
24
D0
25
VROK
7
OFS
PR15
0_0402_5%
1 2
PR165
100K_0402_1%
1 2
1 2
13
D
2
G
S
2N7002_SOT23
MAX1546
PR161
150K_0402_1%
PR168
9.31K_0603_1%
PR132
1 2
0_0402_5%
PR227
1 2
0_0402_5%
CORE_REF <57>
FB
SKIP
SUS
BSTM
LXM
DHM
DLM
VDD
BSTS
DHS
LXS
DLS
PGND
CSP
CSN
CMN
CMP
12
100K_0402_1%
2
G
OAIN+
PL12
PR146
PC124
1 2
0.47U_0603_16V7K
+CPU_B+
OAIN+
PL13
1 2
PR162
1K_0603_1%
PC141
1 2
0.47U_0603_16V7K
+5VS_CORE
13
12
PR136
100K_0402_1%
13
D
2N7002_SOT23
S
PQ45
2N7002_SOT23
+CPU_B+
12
12
PC116
PC117
10U_1206_25VAK
PR145
12
CM-
<57>
PC131
0.001_2512_5%
1 2
H_BOOTSELECT<4>
12
PR110
22.6_0402_1%
PR111
1 2
150_0402_1%
12
PR153
499_0402_1%
OAIN+
12
12
PC132
10U_1206_25VAK
Title
Size Document Number Rev
A3
Date: Sheet
D
PQ20
2
G
2N7002_SOT23
S
PR171
1 2
1K_0603_1%
2.87K_0603_1%
13
D
2
G
PQ40
S
1 2
PR173
1K_0603_1%
12
12
PC118
10U_1206_25VAK
1 3
D
PQ43
PC133
10U_1206_25VAK
1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
10U_1206_25VAK
2
G
2N7002_SOT23
S
12
OAIN-
12
10U_1206_25VAK
PC119
2200P_0402_50V7K
PR164
499_0402_1%
12
PC134
H_BOOTSELECT=1
H_BOOTSELECT=0
CPU_CORE(1)
星期三
07, 2004
七月
12
PR180
1 2
FBM-L18-453215-900LMA90T_1812
12
PC120
0.1U_0805_25V7K
+VCC_CORE
PD27
SKS30-04AT_TSMA
2 1
12
PC135
2200P_0402_50V7K
0.1U_0805_25V7K
+VCC_CORE
PRESCOTT
NORTHWOOD
@0_0402_5%
PR245
PL11
FB
OAIN-
OAIN+
PC182
12
1000P_0402_50V7K
PR244
0_0402_5%
1 2
12
1
+
PC212
PC130
100U_25V_M
2
of
54 65,
+VCC_CORE
VCCSENSE <5>
1
+
PC202
100U_25V_M
2
1
+
100U_25V_M
2
0.1
B+
For Prescott: Pop PR167
SKIP#
4
S0
5
S1
18
3
36
V+
1 2
26
0_0402_5%
27
28
29
30
DAP202U_SOT323
35
33
34
32
31
40
39
38
37
100P_0603_50V8J
PC140
12
PR141
1 2
PC115
1
PD28
0_0402_5%
PR148
3
1 2
12
PC128
0.22U_0603_16V7K
100P_0603_50V8J
1 2
12
0_0402_5%
PC138
1 2
0_0402_5%
PR157
1 2
12
0_0402_5%
PR163
1 2
0_0402_5%
PR166
CPUCLK_STP# <5,11,26>
+5VS_CORE
12
PR135
100K_0402_1%
1
PQ26
E3B
MMBT3904_SOT23
PC181
470P_0402_50V7K
0.22U_0603_16V7K
DLM<57>
+5VS_CORE
2.2U_0805_16V4Z
12
PC125
2
BSTM
12
PC129
@4700P_0402_25V7K
DLS<57>
CS+ <57>
PR156
CS- <4,5,6,7,8,26,57>
CM-
CM+
For Northwood: Pop PR269
DPRSLPVR
1 2
PR155
0_0603_5%
1 2
<26>
PR133
10K_0402_5%
PR143
0_0603_5%
5
3
241
C
2
BSTM
CORE_REF
12
PR269
1 2
PQ28
SI7886DP_SO8
3 5
5
3
241
PQ31
SI7886DP_SO8
3 5
5
3
241
PQ27
SI7392DP_SO8
241
241
PQ29
PQ30
SI7392DP_SO8
5
3
241
PQ44
2N7002_SOT23
SI7886DP_SO8
PQ32
PR167
@100K_0402_1%
13
D
2
G
S
SKIP#
PR154
1 2
100K_0402_1%
0.5U_CXZM1350-R50_35A_20%
PD26
SKS30-04AT_TSMA
12
1K_0603_1%
2 1
CM+
<57>
PR159
1 2
100K_0402_1%
0.5U_CXZM1350-R50_35A_20%
12
2 1
PD29
SKS30-04AT_TSMA
SI7886DP_SO8
Page 55
DLM<56>
CORE_REF
>
200K_0603_1%
PC170
100P_0603_50V8J
12
PC156
100P_0603_50V8J
PR207
12
+VCC_CORE
12
PR184
2200P_0402_50V7K
200K_0603_1%
12
PR189
49.9K_0402_1%
0_0603_5%
+VCC_CORE
12
2200P_0402_50V7K
12
PR210
49.9K_0402_1%
+5VS_CORE
12
2.2U_0805_16V4Z
PR187
0_0603_5%
@1SS355_SOD323
1 2
PC153
DLS<56>
+5VS_CORE
1 2
12
PC158
2.2U_0805_16V4Z
PR188
PC165
0.22U_0603_16V7K
1 2
@1SS355_SOD323
1 2
PC167
PR172
1 2
0_0603_5%
12
10_0603_1%
PR176
PC149
1 2
12
0_0603_5%
PC151
0.22U_0603_16V7K
1 2
PD35
1 2
1 2
PR183
20K_0402_1%
PR196
0_0603_5%
12
PR198
10_0603_1%
PR201
1 2
12
0_0603_5%
PD41
1 2
1 2
PR206
20K_0402_1%
PD33
1SS355_SOD323
11
18
12
PR178
7
3
6
19
8
PD39
1SS355_SOD323
11
18
12
7
3
6
19
8
VDD
LIMIT
VCC
POL
TON
COMP
ILIM
GND
12
VDD
LIMIT
VCC
POL
TON
COMP
ILIM
GND
12
20
PU10
17
V+
TRIG
BST
DH
LX
DL
PGND
CS+
CS-
CM+
CM-
DD/
13
20
PU11
V+
TRIG
BST
DH
LX
DL
PGND
CS+
CS-
CM+
CM-
DD/
13
MAX1980
SKIP#
MAX1980
16
14
15
10
9
5
4
1
2
17
16
14
15
10
9
5
4
1
2
PR177
1 2
0_0603_5%
PR199
1 2
0_0603_5%
12
PC150
0.22U_0603_16V7K
12
PC154
1000P_0603_16V7K
12
PC155
1000P_0603_16V7K
12
PC164
0.22U_0603_16V7K
12
PC168
1000P_0603_16V7K
12
PC169
1000P_0603_16V7K
CM+ <56>
CM- <56>
CS+ <56>
CS- <4,5,6,7,8,26,56>
PR174
0_0603_5%
1 2
PR200
0_0603_5%
1 2
5
3
241
5
3
241
PQ38
PQ35
SI7886DP_SO8
3 5
SI7886DP_SO8
3 5
241
241
PQ34
SI7392DP_SO8
5
3
241
PQ37
SI7392DP_SO8
5
3
241
PQ39
SI7886DP_SO8
2 1
PQ36
SI7886DP_SO8
SKS30-04AT_TSMA
2 1
PD36
SKS30-04AT_TSMA
0.5U_CXZM1350-R50_35A_20%
PD42
PL14
0.5U_CXZM1350-R50_35A_20%
1 2
12
PC152
PR181
1 2
1K_0603_1%
0.47U_0603_16V7K
PL15
PR204
1 2
PC166
12
12
1K_0603_1%
0.47U_0603_16V7K
12
PC145
10U_1206_25VAK
12
PC159
10U_1206_25VAK
+CPU_B+
12
PC148
2200P_0402_50V7K
12
PC162
2200P_0402_50V7K
12
PC144
+VCC_CORE
12
0.1U_0805_25V7K
PC163
0.1U_0805_25V7K
+VCC_CORE
12
12
PC147
PC146
12
PC160
10U_1206_25VAK
10U_1206_25VAK
+CPU_B+
12
PC161
10U_1206_25VAK
10U_1206_25VAK
SKIP# <56>
Compal Electronics, Inc.
Title
+CPU_CORE(2)
Size Document Number Rev
Date: Sheet
星期三
07, 2004
七月
of
55 65,
0.1
Page 56
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
1 0.2
54,55,
56,57
2
Title
wrong layout
pad
DPRSLPVR56 03/25/2003
03/25/2003 Compal
Owner
Compal
wrong layout pad
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
3
4
57 Compal Change Netname of +5VS_CORE
CPU VR-Cont.
5 51 RTC charger Add PR230
C C
6 re-located both PL10 and PQ21, PQ23
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
03/25/2003
Compal
Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
Add PJP14
as well as 1.2VS_VGA related power circitry
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal
and add PR236 for SUSP# signal
Solution Description Rev.Page#
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Request
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期三 七月
LA-2411
1
56 65, 07, 2004
0.1
of
Page 57
1
2
3
4
5
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)
2.Modify the A udio r ela ted s chem atic for C usto mer request . <Page 37> 92.03.17.
-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
3.Change the USB 2. 0 C ont rol ler c hip from ATI to NEC and modify the net for Custom er request .
1 1
<Page 26,27, 36,44> 92.03.18.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,
U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
4.Modify the A udio r ela ted s chem atic for C usto mer request . <Page 37,38> 92.03.20.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)
-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.
-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)
-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
6.Modify the US B2. 0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) .
(Modify CKT,BOM&Layout)
2 2
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net .
(Modify CKT,BOM&Layout)
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request .
<Page 10> 92.03.21.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.
-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)
9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
10. Modify the ON1 r elat ed to spee d up th e pow er se que nce for ATI request . <Page 48,54> 92.03.23.
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);
Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify p owe r s our ce CAP .'s value by Brian . <Page 26,49> 92.03.24.
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348
3 3
from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
12. Del Via Hole on sc hema tic f or M E modify . <Page 41> 92.03.24.
-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
13.Modify t he Mi niP CI and BlueTooth conn related for Custom er request . <Page 43,44> 92.03.24.
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)
-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
14.Swap the U SB2 0*P 3* and USB20*P5* for Customer request . <Page 44> 92.03.24.
-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
A-TEST SMT BUILT
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;
Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;
R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;
R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
16.Modify th e s che ma ti c H _BOO TS ELECT related by Power Team . <Page 04> 92.03.25.
-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) .
4 4
(Modify CKT,BOM&Layout)
-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% .
(Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.
-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),
C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
1
2
18. Modify powe r s our ce Re sis tor an d CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K
to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)
-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 r elat ed to spee d up t he pow er se quen ce for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.
-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.
-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change th e R esi sto r' s value for ATI recommend . <Page 17 > 92.03.26.
-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.
-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.
-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
24. Change the p ower s eque nce r elat ed pa rt's powe r sour ce by Brian . <Page 5,37,48> 92.03.27.
-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.
-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K .
(Modify CKT&BOM)
-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify t he SPD IF rel ate d s che matic for Custom er request . <Page 37,41> 92.03.28.
-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify t he NEC US B2. 0 C ont rol ler Ch ip rel a ted schematic for Customer request . <Page 36> 92.03.28.
-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) .
(Modify CKT,BOM&Layout)
-Add R1104(@0_0402_5%) . (Modify CKT&Layout)
-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.
-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the rela ted s chem ati c aft er B rian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.
-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the rela ted s chem ati c aft er Lay out c heck <Page 44> 92.03.31.
-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.
-Update JP40 . (Modify CKT&Layout)
32. Modify the schem ati c for cost down . <Pa ge 10,12,26,37,> 92.04.04.
-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(1)
星期三 七月
LA-2411
5
of
57 65, 07, 2004
0.1
Page 58
1
2
3
4
5
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connect or JP38 PCB Footprint error. <Page 40> 92.04.09.
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE
Circuit)
2.LED Circui t t o P ower Button(PRES)modify . <Page 42, Page 46> 92.04.09.
-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)
1 1
-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_V GA Di scha rge Ci rcui t. < Pag e 49> 92.04.09.
-Add +1.2VS_ V GA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.
-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
5.PCMCIA U37 N ET S1 _CE 2# & S1_CE1# Sweep. <Page 31> 92.04.09.
6. MDC(JP17) N et AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.
-Update BOM add R326. (Modify EE Circuit)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.
-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)
BHR60 from DB-2 to SI -1 S TEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switc h U 53 PCB Footprint error. <Page 12> 92.04.09.
-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.
-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.
-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES
85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
5. Change BOM & L ayout LED D57 Footprint . <Page 42> 92.04.15.
-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
6. Change Lay out Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.
-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change Lay out Fr ontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.
-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
2 2
9. Add SUSP# pull Down. <Page 46> 92.04.14.
-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_S TP# pu ll Hi gh C ircuit. <Page 26, 5> 92.04.14.
-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)
-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
-Add CPUCLK_STP# s eria l resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
12. SIO Circu it All P ower Plan +3V -> +3VS. <Page 39> 92.04.15.
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.
-Add USB Const ra l or U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)
-Update BOM R1046 -> @. (Modify EE Circuit)
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
3 3
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
17. Change BO M D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
18. Change BOM C 191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BO M C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
25. Change BOM C 966 22U -> 0.1U. <Page 18> 92.04.18.
4 4
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.
1
2
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期三 七月
LA-2411
5
of
58 65, 07, 2004
0.1
Page 59
1
2
3
4
5
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
BHR60 from DB-2 to SI -1 S TEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->
AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
1 1
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull
High +3V. <Page 41> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
2 2
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R 40 @ - > Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI ad d R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI chan ge D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R 623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.
3 3
2. Change C963 -> @. <Page 41> 92.04.28.
3. Change C974 -> @. <Page 17> 92.04.28.
4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.
5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.
6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.
7. DEL R761,R762 <Page 37> 92.04.28.
4 4
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(3)
星期三 七月
LA-2411
5
0.1
of
59 65, 07, 2004
Page 60
1
2
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR
<92.05.07.~92.05.30. >
1 Prevent CPUCLK_STP# abnormal state happened 5 Ch ange R1125 from 4.7K to 12K
3
Reason for change PAGE Modify ListFixed IssueItem
4
5
M.B. Ver.
0.5
26 Delete R1126
29 Change R40 from 10K to 1K
1 1
2
3
Prevent power leakage
Power saving 7 Change the power of Fans from +5VALW to +5VS 0. 5
7 Change the power of U8 from +3VS to +3VALW
0.5
ATI recommendation 8 Add C974 0.54
Add VGA DRAM size detect function5 17 A dd R 1149 for 128MB VGA DRAM (un-populate for 64MB) 0.5
6 Add CS1# for Hynix 8Mx32 VGA DRA M
18, 19,
22, 23
0.5Add Nets: NMCSA1# and NMCSB1#
7 Change M9+X VGA_CO RE from +1.5VS to individual power source 2 1 De lete JOPEN3 0.5
8
2 2
Update with Item23
10 Prevent DPRSLPVR abnormal state happened Change R1001 from 100K to 47K, R1002 from 0 to 47K 0. 5
11 Using rechargeable RTC battery for HP's request Delete D66, D7 1 and D72; Add D 91 (BAS40-04, the same as LA-1761 D30); Change
12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798
13 Enhance brightness of blue LEDs 0.5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,
3 3
Delete useless components
5 Delete R538
25 Delete C96
27 Delete Q114, Add R1145
25
Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5Solve power leakage from CRT9
26
BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)
from 22u to @10u; Change C801 from 1000p to @1000p
42, 45
R885, R888, R889, R890, R925 and R1136 to 220
44
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;
Change JP42.12 from PAV_GND to PAV_LEDVCC; Cha nge JP42.13 from PMLED_1 to
PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to
PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
0.5
0.526
0.5
14 Solve PWR_ACTIVE LED function fail issue 4 2 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0.5
46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change
U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to
PWR_ACTIVE_PAV#
15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5
16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0. 5
17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0 . 5
18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5
19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5
4 4
1
20 Decrease Audio AMP Ga in 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(4)
星期三 七月
LA-2411
5
of
60 65, 07, 2004
0.1
Page 61
BHR60 from SI-1 to DB( 15 .4") LA-1811 REV:0.4 -> 0.5
1
HW PIR <92.05.07.~92.05.30. >
21 RTL8101L no need transistor for 3.3V to 2.5V anymore 3 4 Delete Q55, R944 and C668
2
Reason for change PAGE Modify ListFixed IssueItem
3
4
5
M.B. Ver.
0.5
Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation
Change PC B Footprint from SUYIN_020167MR004SX01ZR_4P to
22
1 1
23
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0 . 5
44
suyin_020167mr004s511zu_4p for JP18, JP19 and JP20
0.5Connector Sp ec. cha nge for ME's re quest
Delete useless components with BOM 1 0 Delete R574, R1086 and C952 0.524
24 Delete R210 for UMA only
Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.525
Add components for EMI 37 Add R1152 0.526
40 Add L65 ~ L78
40 Add L79 ~ L97
Solve DOS cold-boot shunt down issue 7 Delete C256 0.527
BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6
HW PIR <92.06.20.~92.07.03. >
2 2
Decrease overshoot & undershoot 2 5 Add R1153 a nd R1154 0.628
Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.629
Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0. 630
40The pin-de finit ion o f FDD conn. was error on rev0.5 M/B31 0.6Correct the pin-definition for JP38
32 0.6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation
33 0.6Change R880 from 10K to 470Enhance brightness of Docking LEDs
40
41
44To support wak e-up function with TP Change TP power from +5VS to +5V
5Delete useless components Delete R535, R536, R991 and R992
0.634
0.635
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251
3 3
20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
38 Delete R1142
39 Delete RP 153 and R1132
36 To improve RTC accuracy 2 6 Change Y1 from +/-20ppm to +/-10ppm
37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST#
0.6
0.6
Add components for EMI38 37 Add L98 and L99 0.6
40 Add C975, C976, CP15~CP17
4 4
39 Improve Audio quality
Delete C753~C756; Add R1165~R1168 and C97937
38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3
0.6
41 Add R1161
40 42 Add D92
41 Change R904 from 91K to 47K49Mod ify +5V pow er-up timing to lead + 3V
1
2
Add components for ID & ME
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(5)
星期三 七月
LA-2411
5
of
61 65, 07, 2004
0.1
Page 62
BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7
1
HW PIR <92.07.03.~92.08.08. >
42 Correct Y1 a nd Y3 pin-out 26 Using pin-1 and pin-2 of these crystals
2
Reason for change PAGE Modify ListFixed IssueItem
3
4
5
M.B. Ver.
0.7
46
Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
43
1 1
44
ATI Product Advisory, refer to PA_218IXP0T1
Solve CD-ROM audio noise issue 3 0 Del ete C11 0.7
44
0.7
Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0.745
For EMI 38 Add L100, L101, L102 and L103 0.746
For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.747
ATI recommendation 2 7 Change RP12 from 10K to 2.2K 0.748
46 Add R1 175
Delete useless components 46 Delete D69 and D70 0.749
To support wake-up function with TP 4 6 Delete RP154; Add R1169, R1170, R1171 and R1172 0. 750
2 2
Solve M10 can't power up issue 49 Delete C844 0.751
Change R901 from 27K to 6.8K
Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0.752
Modify brightness of LED s 42 Change Transistors from BJT to PMOS and R esister s value for Pav; Change Resisters value for Pre. 0 . 753
45
Fast power on for battery only 4 5 Change R306 from 100K to 470; Delete Q112 0 .754
Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.755
Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.756
Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0 . 757
Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0.758 37
3 3
Improve USB2.0 signal quality Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 0.759
Reserve VRAM detect function for ATI recommendation Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 1.060
For EMI Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A)1.061 38
Reduce GHI# "LOW" voltage level Change R527 to 300 ohm 1.062
36
17
Delete C110~C11548
36 Change L89, R1079 & R1080 to CHB1608U301
7 A dd C855, C856, C907 and C908
24 Change L11 & L12 to MBV2012301YZT
26 Change PCI clock damping resisters to 39 ohm
28 Add C873~C881, C980~C983; Change R60~R62 to MBV2012301YZT
37 Delete R769 & R770; Add C984~C992 & L104
41 Add L105
25 Add C993 & C994
5
Fix "Pop" sound during boot up 1.0Add C97963 37
For PCBA skew red ucing 1.064 42 Change R885, R888, R890, R1136 and R925 to 130
45
TI recommendation 1.065 32 Add R1177
4 4
Solve aud io L/ R swa p issue 1.066 3 7 Change R750 & R753 to 27 ohm
44 Delete R327 & C305
67 Improve NIC transmit return loss 34 Change U41 to NS0019 1.0
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(6)
星期三 七月
LA-2411
5
0.1
of
62 65, 07, 2004
Page 63
BHR60 LA-1811 REV:1.0 ->1A
1
HW PIR
2
Reason for change PAGE Modify ListFixed IssueItem
67
reserve Hynix DDR blue screen issue when boot to Win XP
3
4
5
M.B. Ver.
16 Add R1180
1A
For EMI
43 Connect MiniPCI cla mp (pin1 27 and pin128) to GND
1A
68
1 1
69
70
71
72
Delete unnecessary component
Reserve for when you connect the dock station cable in unit playing an audio
occur a speaker switch
The region is ME height limited zero 1A
Add D94 and R117846For EC NS97551 +3VALW undershoot issue 1A
46 Delete JP21
1A
47 Delete JP22
46 Add R1179 and C995 1A
54 Dele te PJP10 tha n short it directly
73
74
75
2 2
76
77
78
79
80
81
82
83
3 3
84
85
86
87
88
89
90
4 4
1
91
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期三 七月
LA-2411
5
0.1
of
63 65, 07, 2004
Page 64
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
1 0.2
54,55,
56,57
2
Title
wrong layout
pad
DPRSLPVR56 03/25/2003
03/25/2003 Compal
Owner
Compal
wrong layout pad
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
3
4
57 Compal Change Netname of +5VS_CORE
CPU VR-Cont.
5 51 RTC charger Add PR230
C C
6 re-located both PL10 and PQ21, PQ23
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
03/25/2003
Compal
Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
Add PJP14
as well as 1.2VS_VGA related power circitry
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal
10 54 +1.5VALWP
04/16/2003 Compal
change 1.5V time sequence
and add PR236 for SUSP# signal
Change power time-sequence of 1.5VSP input power
Solution Description Rev.Page#
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.4
Request
11 04/16/2003 Compal
56 CPU DPRSLPVR
B B
12 Change power JUMP SIZE to follow new jump role
13 CPU DPRSLPVR56
14
15
16 04/30/2003 Compal
17
56
5554
PWR JUMP
04/16/2003
Compal
04/18/2003 Compal
50
Vin DETECTOR 04/30/2003 Compal
50 Precharge 04/30/2003 Compal
51
Battery OTP
51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N
18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71
19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2
A A
5
04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V
Change DPRSLPVR design
For DFX issuse
Change DPRSLPVR design
to make ACIN to enable to pull low
BOM error
To change feekbeck time
4
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode
0.4
0.4
Reserve DPRSLPVR function
and add a PR136 for +5VS_CORE signal
Change PR8 form 10k_0603 to 0K_0603
Change PR1 from 10k_0603 to 100k_0603
Change PC20 from .22u to 1u ;PR40&PR42 from 100k to
150k; PC80 from 1u to .47u
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Title
Size Document Number Rev
3
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期三 七月
LA-2411
1
64 65, 07, 2004
0.1
of
Page 65
5
_S
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
21
Title
Owner
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors
Add
Precharge
22 50
23 51
detector
Colok THROTTLING
24 56,57 CPU_CORE(1&2) 05/16/2003 Compal
25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5
C C
26 55
27
53 3V/5V/12V
1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA
05/16/2003 Compal System can't power on by battery
05/16/2003 Compal
To modify the circuit
Change the freqeuce 300k to 200k
07/4/2003 Compal
To modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)
Add PR194(1K)
,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
Change PR5 from 150k to 180k
Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form
84.5K to 11.5K
delet PR138 ; add PR187(0_0603)&PR188(0_0603)
add PR124(11.5k_0603) 0.5
,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet
PR86,PR88,PR90,PR93
28
29 56,57
30
56 CPU_CORE
CPU_CORE(1&2) 07/4/2003
07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/A
Compal
To improve the CPU_CORE effecient
Change PR158,PR180 from 2k to 3.4k 0.6
Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6
50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)
Solution Description Rev.Page#
0.4
0.5
0.5
0.5
0.6
0.7
Request
31
B B
32
52
53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issue
Charger 08/4/2003 Compal
To modify the Precharge circuit
33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to
-1.5mV/A, and senes CPU VCC and VSS
34 52 Charger 08/4/2003 Compal
35
A A
52
5
To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7
change 2.5V from fix to adjust Add pr267, PR268 and PC2112004.05.31
4
3
Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA
0.7
change PR81(1.27k) ,PR78(1.54K),PR79(0_0402)
,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add
PR241(1.24k),PR242(620 ohm),PR243(698 ohm)
0.7
Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)
and PR245(0 ohm)
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期三 七月
LA-2411
1
0.7
65 65, 07, 2004
0.1
of
Page 66
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