Compal LA-2362 EAL50, Aspire 3500, Smart 300S, Tin Yat 80A, LA-2362 EAL51 Schematic
5
D D
C C
4
3
2
1
Sonoma Dothan EAL50_1
LA2362 Schematic
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2006/03/01
3
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
152
5
4
3
2
1
Compal confidential
Block Diagram
Dothan
D D
uFCPGA CPU
Clock Generator
ICS
Memory
BUS(DDR)
Dual Channel
2.5V 333MHz
Channel A
SO-DIMM X 1
BANK 0, 1
SO-DIMM X 1
BANK 2, 3
Fan Control X1
LED/B
VGA
Board
CRT CONN.
& TV-OUT
HA#(3..31)
System Bus
400 / 533MHz
Alviso Intel 915 PM/GM
GMCH-M
HD#(0..63)
Internal GM
ATI VGA
C C
VGA CONN.
PCI-E 16X
External PM
1257 FC-BGA
SW LED BD
T/P
DMI
1.5V
MINI PCI
IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)
VIA6301
1394
B B
1394
CONN.
CardBus
Controller
ENE CB712
SDIO
CONN.
3.3V 33MHz
PCI BUS
Slot 0
3.3V 33MHz
RTL 8110SBL
/ G 8100CL /
100
Transformer
& RJ45
LPC BUS
3.3V 33MHz
X BUS
SIO
LPC47N217D
A A
FIR
PIO
SST39VF080
Touch Pad
100MHz
KB910
ICH6
609 BGA
Int.KBD
48MHz / 480Mb
3.3V 24.576MHz
ATA100
HDD
USB2.0
USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
CDROM
JUSBP2
JUSBP3
JUSBP1
JUSBP1
RESERVED
RESERVED
RESERVED
BT+MDC
AC-LINK
AC97 CODEC
RTL 250
AMP &
Phone/ MIC
Jack
BT
DC IN
BATT IN/+2.5V
1.5V/1.05V(+VCCP)
5V/3.3V/15V
1.8V / 0.9V
VCORE
CHARGER
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
252
5
4
3
2
1
I2C / SMBUS ADDRESSING
External PCI Devices
IDSEL # PIRQREQ/GNT #DEVICE
LAN
CARD BUS
D D
Cardreader
1394
Wireless LAN(MINI PCI)
AD17
AD20
AD16 2
AD18
0
1
3
@ Depop
1@ EAL51
2@ EAL50
1@ EAL51 VALUE (DELETE SIO/1394)
C C
F
A
B
E
G,H
Power Managment table
Signal
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
Ceramic Capacitor Spec
Guide:
Temperature Characteristics:
0
Symbol
CODE
8
NP0 SH
H
UJ
Z5U
Z5V
9
C0G
I
J
UK
SL
1
A
+12VALW +3V
+3VALW
+5VALW
ON
ON ON ON
ON ON
ON OFF
OFF OFF OFF
2
Z5P
Y5U
B
BJ
3
C
CH
+2.5V
+5V
+12V
ON ON
5
4
Y5V Y5P
E
D
CK
CJ
+CPU_CORE
+VCCP
+5VS
+3VS
+2.5VS
+1.8VS
+1.25VS
+1.5VS
OFF
OFF
6
X5R
F
X7R
SJ
Bringup-Build
SST-Build
PT-Build
ST-Build
QT-Build
SCHEMATICS VERSION LIST
VERSION ISSUE DATE REMARK
0.0A
7
G
PCB Rev
0.1
Tolerance:
+-2%
G
X
H
+-3%
Z
+80,-20%
J
+-5%
A
B
Symbol
CODE
B B
+-0.05PF
KQ
M
+-10%
+-20%
+-0.1PF
N
+-30%
C
+-0.25PF
P
+100,-0%
+-0.5PF +-1PF
+30,-10%
F
D
V
+20,-10%
+40,-20%
Data
First Release
SMBUS Control Table
THERMAL
THERMAL
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
ICH_SMBCLK
ICH_SMBDATA
A A
LCD_DDCCLK
LCD_DDCDATA
5
PC87591L
PC87591L
ICH6-M
Alviso
GM-GP
INVERTER BATT
SERIAL SENSOR
EEPROM
(CPU)
4
SENSOR
(LM75)
SODIMM CLK CHIP
MINI PCI
VGA Thermal
LCD
ADM1032
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
2
Title
<Title>
Size Document Number Rev
LA-2362 1
C
Friday, March 11, 2005
Date: Sheet
1
of
352
ACIN
5
4
3
2
1
+3/5/12VALW
D D
32ms
ON/OFF#
8.5/2.44/3.792ms
t<=10 ms
EC_ON#
t=100 ms
PWRBTN_OUT#
438ms
364us
t=109 ms
SYSON
3/5V 400us 2.5V(1.8ms)
+12/2.5/3/5V
C C
RSMRST#
7.856ms
t<110 ms
117ms
SLP_S3/4/5#
92.88ms
SUSP#
+1.25/1.5/1.8/2.5/3/5VS
+VCCP
VR_ON#
1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)
t>0
2.166ms
1.3ms PGD
5.6ms
B B
CPU_VID
+CPU_CORE
Vgate
SYSPOK
PCIRST/PLTRST#
726us
815.2us
t<110 ms
99ms
t<100 us
1.036ms
2<t<3 RTCCLK
61us
CPU_RST#
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2006/03/01
3
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
452
5
4
3
2
1
H_A#[3..31]<8>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
CLK_CPU_BCLK
CLK_CPU_BCLK#
ITP_DBRESET#
H_PROCHOT#
R530
1 2
1K_0402_5%@
R464
1 2
1K_0402_5%@
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CPU_CK_ITP
CPU_CK_ITP#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
H_DBSY#
H_DPSLP#
H_DPRSLP#
ITP_BPM#4
ITP_BPM#5
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
D D
H_REQ#[0..4]<8>
CLK_ITP_R#
R110 0_0402_5%
1 2
CLK_ITP_R
R112 0_0402_5%
1 2
@
CLK_ITP<18>
CLK_ITP#<18>
+VCCP
@
1 2
CLK_ITP
CLK_ITP#
R7856_0402_5%
H_RS#[0..2]<8>
C C
B B
A A
H_ADSTB#0<8>
H_ADSTB#1<8>
R111 0_0402_5%@
1 2
R109 0_0402_5%@
1 2
CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>
H_ADS#<8>
H_BNR#<8>
H_BPRI#<8>
H_BR0#<8>
H_DEFER#<8>
H_DRDY#<8>
H_HIT#<8>
H_HITM#<8>
H_LOCK#<8>
H_RESET#<8>
H_TRDY#<8>
H_DBSY#<8>
H_DPSLP#<20>
H_DPRSLP#<20>
H_DPWR#<8>
H_PWRGOOD<20>
H_CPUSLP#<8,20>
T5 PAD
T39 PAD
H_THERMDA<34>
H_THERMDC<34>
H_THERMTRIP#<8,20>
TEST2
TEST1
JCPU1A
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
ADDR GROUP
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
U3
ADSTB0#
AE5
ADSTB1#
A16
ITP_CLK0
A15
ITP_CLK1
B15
BCLK0
B14
BCLK1
N2
ADS#
L1
BNR#
J3
BPRI#
N4
BR0#
L4
DEFER#
H2
DRDY#
K3
HIT#
K4
HITM#
A4
IERR#
J2
LOCK#
B11
RESET#
H1
RS0#
K1
RS1#
L2
RS2#
M3
TRDY#
C8
BPM0#
B8
BPM1#
A9
BPM2#
C9
BPM3#
A7
DBR#
M2
DBSY#
B7
DPSLP#
G1
DPRSTP#
C19
DPWR#
A10
PRDY#
B10
PREQ#
B17
PROCHOT#
E4
PWRGOOD
A6
SLP#
A13
TCK
C12
TDI
A12
TDO
C5
TEST1
F23
TEST2
C11
TMS
B13
TRST#
B18
THERMDA
A18
THERMDC
C17
THERMTRIP#
TYCO_1612365-1_Dothan
Dothan
DATA GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>
H_STPCLK# <20>
H_SMI# <20>
H_D#0
A19
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_D#[0..63] <8>
Test pad as closed as posible
ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1
Place near JITP 0.5"
22.6_0402_1%
H_RESET#
22.6_0402_1%
ITP_TDO
R74
1 2
R87
1 2
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_ITP_R
ITP_TRST#
ITP_TMS
ITP_TDI
Check ITP connector.
R123
56_0402_5%
H_DSTBN#[0..3] <8>
H_DSTBP#[0..3] <8>
R458
200_0402_5%
H_PWRGOOD
1 2
+VCCP
2005/03/01 2006/03/01
Compal Secret Data
Add pullups for PWRGOOD and THERMTRIP per INTEL
Deciphered Date
2
T7PAD
T6PAD
T8PAD
T10PAD
T9PAD
T12PAD
T11PAD
T4PAD
T17PAD
T19PAD
T15PAD
T16PAD
T13PAD
T14PAD
+VCCP
12
R124
56_0402_5%
12
H_PROCHOT#
+3V
R79
150_0402_5%
1 2
+VCCP
54.9_0603_1%
1 2
R745 56_0402_5%
+VCCP
37.4_0402_1%
1 2
150_0402_5%
1 2
680_0402_5%
1 2
27.4_0402_1%
1 2
+VCCP
1
2
R90
R76
54.9_0603_1%
1 2
1 2
39.4
R479
R85
This shall place near CPU
R100
R106
C359
0.1U_0402_10V6K
ITP_DBRESET#
H_RESET#
ITP_BPM#5
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
Place near JITP
+3VS
12
R132
1K_0402_5%
1
PROCHOT# <32>
of
552
1
C
Q6
2
B
2SC2411K_SC59
E
3
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
Date: Sheet
5
4
3
2
1
R470
+VCCA_PROC
2 1
PAD-OPEN 2x2m@
R422
0_0402_5%
1 2
@
J2
1
1
C516
C150
2
2
10U_1206_6.3V6M
0.01U_0402_16V7K
VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>
@
1 2
+1.5VS
SHORT
R423
0_0402_5%
D D
For test only ,Cmos output
R427
0_0402_5%
+VCCP
1 2
@
R412 10K_0402_5%
@
12
12
R426
0_0402_5%
R411 10K_0402_5%
@
@
12
R410 10K_0402_5%
12
1 2
@
R409 10K_0402_5%
@
12
R425
0_0402_5%
R408 10K_0402_5%
@
12
R413 10K_0402_5%
@
1 2
@
R424
0_0402_5%
CPU Voltage ID
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
C C
R433 0_0402_5%
R434 0_0402_5%
R435 0_0402_5%
R436 0_0402_5%
R437 0_0402_5%
R438 0_0402_5%
12
12
12
12
12
12
1 2
@
54.9_0402_1%@
54.9_0402_1%@
+CPU_CORE
1 2
1 2
R465
+VCCP
VCCSENSE
VSSSENSE
OPEN OPEN OPEN OPEN OPEN OPEN
T3 PAD
T2 PAD
T20 PAD
T31 PAD
T29 PAD
H_PSI#
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
CPU_BSEL0
CPU_BSEL1
COMP0
COMP1
COMP2
COMP3
PSI#<45>
+VCCP
R_A
12
+V_CPU_GTLREF
B B
12
R155
1K_0402_1%
R_B
R153
2K_0402_1%
Layout close CPU
Layout Note:
500 mil max length
27.4_0402_1%
R156
20 mils
12
54.9_0402_1%
R157
5 mils
12
27.4_0402_1%
R416
20 mils
12
5 mils
12
54.9_0402_1%
R417
+V_CPU_GTLREF
CPU_BSEL0<18>
CPU_BSEL1<18>
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
JCPU1B
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
TYCO_1612365-1_Dothan
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
Dothan
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
POWER, GROUNG, RESERVED SIGNALS AND NC
+CPU_CORE
JCPU1C
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
AA11
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AB6
VCC
AB8
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AC9
VCC
AC11
VCC
AC13
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AD8
VCC
AD10
VCC
AD12
VCC
AD14
VCC
AD16
VCC
AD18
VCC
AE9
VCC
AE11
VCC
AE13
VCC
AE15
VCC
AE17
VCC
AE19
VCC
AF8
VCC
AF10
VCC
AF12
VCC
AF14
VCC
AF16
VCC
AF18
VCC
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS
TYCO_1612365-1_Dothan
Dothan
POWER, GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
652
5
4
3
2
1
+CPU_CORE
1
C482
10U_0805_6.3V6M
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
C430
10U_0805_6.3V6M
C100
10U_0805_6.3V6M
C512
10U_0805_6.3V6M
D D
C C
1
C483
10U_0805_6.3V6M
2
1
C421
10U_0805_6.3V6M
2
1
C105
10U_0805_6.3V6M
2
1
C507
10U_0805_6.3V6M
2
1
C460
10U_0805_6.3V6M
2
1
C415
10U_0805_6.3V6M
2
1
C109
10U_0805_6.3V6M
2
1
C502
10U_0805_6.3V6M
2
1
C446
10U_0805_6.3V6M
2
1
C416
10U_0805_6.3V6M
2
1
C114
10U_0805_6.3V6M
2
1
C469
10U_0805_6.3V6M
2
1
C431
10U_0805_6.3V6M
2
1
C480
10U_0805_6.3V6M
2
1
C91
10U_0805_6.3V6M
2
1
C442
10U_0805_6.3V6M
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
C422
10U_0805_6.3V6M
C481
10U_0805_6.3V6M
C92
10U_0805_6.3V6M
1
C518
10U_0805_6.3V6M
2
1
C113
10U_0805_6.3V6M
2
1
C121
10U_0805_6.3V6M
2
10uF 1206 X5R -> 85 degree
1
C470
10U_0805_6.3V6M
2
1
C108
10U_0805_6.3V6M
2
1
C120
10U_0805_6.3V6M
2
1
C459
10U_0805_6.3V6M
2
1
C104
10U_0805_6.3V6M
2
1
C383
10U_0805_6.3V6M
2
X7R
High Frequence Decoupling
1
C445
10U_0805_6.3V6M
2
1
C99
10U_0805_6.3V6M
2
1
C522
10U_0805_6.3V6M
2
Near VCORE regulator.
+CPU_CORE
330U_D2E_2.5VM_R9
1
C358
B B
+
2
330U_D2E_2.5VM_R9
C378
1
1
C377
+
2
2
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1
C357
+
+
2
ESR <= 3m ohm
Capacitor > 880 uF
+VCCP
1
C664
0.1U_0402_10V6K
2
+VCCP
1
+
C525
150U_D2_6.3VM
2
A A
1
C498
0.1U_0402_10V6K
2
5
1
C665
0.1U_0402_10V6K
2
1
C499
0.1U_0402_10V6K
2
1
C666
0.1U_0402_10V6K
2
1
C504
0.1U_0402_10V6K
2
1
2
1
2
4
C667
0.1U_0402_10V6K
C500
0.1U_0402_10V6K
1
C668
0.1U_0402_10V6K
2
1
C503
0.1U_0402_10V6K
2
1
C669
0.1U_0402_10V6K
2
1
C463
0.1U_0402_10V6K
2
1
C670
0.1U_0402_10V6K
2
1
C441
0.1U_0402_10V6K
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C671
0.1U_0402_10V6K
2
1
C424
0.1U_0402_10V6K
2
2005/03/01 2006/03/01
1
C672
0.1U_0402_10V6K
2
1
C450
0.1U_0402_10V6K
2
Compal Secret Data
Deciphered Date
1
C673
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
752
5
D D
C C
Layout Guide will show
these signals routed
differentially.
B B
A A
H_A#[3..31]<5>
H_REQ#[0..4]<5>
H_DSTBN#[0..3]<5>
H_DSTBP#[0..3]<5>
H_RS#[0..2]<5>
H_CPUSLP#<5,20>
T1 PAD
CLK_MCH_BCLK#<18>
CLK_MCH_BCLK<18>
H_HITM#<5>
H_HIT#<5>
H_LOCK#<5>
H_CPUSLP# H_R_CPUSLP#
Note:
"Do not install R for Dothan-A,
Install R97 for Dothan-B"
H_ADSTB#0<5>
H_ADSTB#1<5>
H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>
H_RESET#<5>
H_ADS#<5>
H_TRDY#<5>
H_DPWR#<5>
H_DRDY#<5>
H_DEFER#<5>
H_BR0#<5>
H_BNR#<5>
H_BPRI#<5>
H_DBSY#<5>
5
T27 PAD
R418
0_0402_5%
1 2
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_RESET#
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
@
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_R_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
U5A
G9
HA3#
C9
HA4#
E9
HA5#
B7
HA6#
A10
HA7#
F9
HA8#
D8
HA9#
B10
HA10#
E10
HA11#
G10
HA12#
D9
HA13#
E11
HA14#
F10
HA15#
G11
HA16#
G13
HA17#
C10
HA18#
C11
HA19#
D11
HA20#
C12
HA21#
B13
HA22#
A12
HA23#
F12
HA24#
G12
HA25#
E12
HA26#
C13
HA27#
B11
HA28#
D13
HA29#
A13
HA30#
F13
HA31#
A11
HPCREQ#
A7
HREQ#0
D7
HREQ#1
B8
HREQ#2
C7
HREQ#3
A8
HREQ#4
B9
HADSTB#0
E13
HADSTB#1
AB1
HCLKN
AB2
HCLKP
G4
HDSTBN#0
K1
HDSTBN#1
R3
HDSTBN#2
V3
HDSTBN#3
G5
HDSTBP#0
K2
HDSTBP#1
R2
HDSTBP#2
W4
HDSTBP#3
H8
HDINV#0
K3
HDINV#1
T7
HDINV#2
U5
HDINV#3
H10
HCPURST#
F8
HADS#
B5
HTRDY#
G6
HDPWR#
F7
HDRDY#
E6
HDEFER#
F6
HEDRDY#
D6
HHITM#
D4
HHIT#
B3
HLOCK#
E7
HBREQ0#
A5
HBNR#
D5
HBPRI#
C6
HDBSY#
G8
HCPUSLP#
A4
HRS0#
C5
HRS1#
B4
HRS2#
ALVISO_BGA1257
Alviso
HOST
H_SWNG0
C362
0.1U_0402_16V4Z
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
1
2
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
12
R397
221_0603_1%
12
R388
100_0402_1%
4
4
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
J11
C1
C2
T1
L1
D1
P1
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
H_SWNG1
C385
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1
2
0.1U_0402_16V4Z
+VCCP+VCCP
R67
R73
R77
24.9_0402_1%
12
221_0603_1%
12
100_0603_1%
12
R44
24.9_0402_1%
R41
12
H_D#[0..63] <5>
Layout Note:
Rote as short
as possible
12
R477
40.2_0402_1%
@
+VCCP
12
R66
54.9_0402_1%
54.9_0402_1%
10/20 mils
3
Layout Guide
will show these
signals routed
differentially.
DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>
DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>
DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>
DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>
DDR_CLK0<13>
DDR_CLK1<13>
DDR_CLK3<14>
DDR_CLK4<14>
DDR_CLK0#<13>
DDR_CLK1#<13>
DDR_CLK3#<14>
DDR_CLK4#<14>
DDR_CKE0<13>
DDR_CKE1<13>
DDR_CKE2<14>
DDR_CKE3<14>
DDR_SCS#0<13>
DDR_SCS#1<13>
DDR_SCS#2<14>
DDR_SCS#3<14>
R484 80.6_0402_1%
1 2
12
R489
80.6_0402_1%
+SDREF_DIMM
CFG[2:0]
CFG5
CFG6
12
12
R476
40.2_0402_1%
@
C379
0.1U_0402_16V7K
M_OCDOCMP0
M_OCDOCMP1
1
2
+VCCP
12
R372
100_0402_1%
12
R376
200_0402_1%
+2.5V
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DDR_CLK0
DDR_CLK1
DDR_CLK3
DDR_CLK4
DDR_CLK0#
DDR_CLK1#
DDR_CLK3#
DDR_CLK4#
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
M_OCDOCMP0
M_OCDOCMP1
SMRCOMPN
SMRCOMPP
1
1
C419
C428
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Refer to sheet 6 for FSB
frequency select
Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
Compal Secret Data
Deciphered Date
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
*
Y31
Y33
*
*
2
U5B
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO_BGA1257
*
*
*
*
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
DMIDDR MUXING
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
CFG/RSVD
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
CLK
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC
NC11
*
1
Alviso CFG[17:3] has internal pull-up
CFG0
G16
MCH_CLKSEL1
H13
MCH_CLKSEL0
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
D37
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CFG[17:3] have internal pull-up
3.5 k reserve for choose
Title
Size Document Number Rev
Custom
Date: Sheet
T25PAD
T26PAD
CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
H_THERMTRIP#
PM_EXTTS#0
PM_EXTTS#1
PLTRST_R#
R384 10K_0402_5%
@
R387 10K_0402_5%
@
CFG0
CFG6
CFG5
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
12
12
<Title>
LA-2362 1
Friday, March 11, 2005
MCH_CLKSEL1 <18>
MCH_CLKSEL0 <18>
@
@
R57
56_0402_5%
1 2
@
1 2
R492 100_0402_1%
12
12
PM_EXTTS#0
PM_EXTTS#1
R367 10K_0402_5%
R369 2.2K_0402_5%
R370 2.2K_0402_5%
R368 2.2K_0402_5%
R394 2.2K_0402_5%@
R374 2.2K_0402_5%@
R375 2.2K_0402_5%@
R430 2.2K_0402_5%@
R36 1K_0402_5%@
R37 1K_0402_5%@
R352.2K_0402_5%@
CFG[19:18] have internal pull-down
R382.2K_0402_5%@
+VCCP
PM_BMBUSY# <21>
H_THERMTRIP# <5,20>
VGATE <18,21,45>
DREFCLK# <18>
DREFCLK <18>
SSC_DREFCLK <18>
SSC_DREFCLK# <18>
10K_0402_5%
10K_0402_5%
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3.5 k reserve for choose
1 2
1 2
1
PLTRST_MCH# <19>
R366
12
R365
12
852
+2.5VS
+VCCP
+2.5VS
of
5
D D
4
3
2
1
DDR_A_BS#0<13>
DDR_A_BS#1<13>
T38 PAD
DDR_A_DM[0..7]<13>
DDR_A_DQS[0..7]<13>
C C
DDR_A_MA[0..13]<13>
DDR_A_CAS#<13>
DDR_A_RAS#<13>
T36 PAD T33 PAD
T35 PAD
DDR_A_WE#<13>
B B
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
DDR_A_WE#
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AK36
AP33
AN29
AP23
AK35
AP34
AN30
AN23
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
AP9
AP4
AD3
AM8
AM4
AE5
AN8
AM5
AH1
AE4
AJ2
AJ1
U5C
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
ALVISO_BGA1257
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
DDR MEMORY SYSTEM A
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D0
AG35
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
DDR_A_D[0..63] <13>
T34 PAD
DDR_B_BS#0<14>
DDR_B_BS#1<14>
T37 PAD
DDR_B_MA[0..13]<14>
DDR_B_CAS#<14>
DDR_B_RAS#<14>
DDR_B_WE#<14>
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
DDR_B_WE#
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
U5D
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
ALVISO_BGA1257
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
SBDQ27
AH24
SBDQ28
AH23
SBDQ29
AG22
SBDQ30
AJ21
SBDQ31
AG10
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
AH11
SBDQ36
AH10
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR SYSTEM MEMORY B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
952
5
4
3
2
1
+2.5VS
R29 3K_0402_5%@
1 2
R30
1 2
12
R428
1 2
CLK_DDC2
DAT_DDC2
3K_0402_5%@
1@
R392
0_0402_5%
1@
R32
150_0402_1%
12
1@
CLK_DDC2<17>
DAT_DDC2<17>
CRT_BLU<17>
CLK_MCH_3GPLL#<18>
CLK_MCH_3GPLL<18>
12
R33
150_0402_1%
1@
R34
150_0402_1%
12
4.99K_0603_1%
D D
Y/G<17>
COMP/B<17>
C/R<17>
CRT_GRN<17>
CRT_RED<17>
VSYNC<17>
HSYNC<17>
BIA<16,32>
1 2
R429
255_0402_1%
BK_EN<16>
C C
B B
R396 100K_0402_1%
1 2
1 2
R404100K_0402_1%
LCD_CLK<16>
LCD_DAT<16>
EN_LCDVDD<16>
R3781.5K_0402_1%
LVDS_AC-<16>
LVDS_AC+<16>
LVDS_BC-<16>
LVDS_BC+<16>
LVDS_A0-<16>
LVDS_A1-<16>
LVDS_A2-<16>
LVDS_A0+<16>
LVDS_A1+<16>
LVDS_A2+<16>
LVDS_B0-<16>
LVDS_B1-<16>
LVDS_B2-<16>
LVDS_B0+<16>
LVDS_B1+<16>
LVDS_B2+<16>
BIA
BK_EN
LCTLA_CLK
LCTLB_DAT
LCD_CLK
LCD_DAT
12
EN_LCDVDD
LVDS_ACLVDS_AC+
LVDS_BCLVDS_BC+
LVDS_A0LVDS_A1LVDS_A2-
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_B0LVDS_B1LVDS_B2-
LVDS_B0+
LVDS_B1+
LVDS_B2+
U5G
H24
H25
AB29
AC29
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
ALVISO_BGA1257
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
EXP_COMPI
EXP_ICOMPO
EXP_RXN0/SDVO_TVCLKIN#
EXP_RXN1/SDVO_INT#
MISCTVVGALVDS
EXP_RXN2/SDVO_FLDSTALL#
EXP_RXP0/SDVO_TVCLKIN
EXP_RXP2/SDVO_FLDSTALL
EXP_TXN1/SDVOB_GREEN#
EXP_TXN2/SDVOB_BLUE#
EXP_TXN5/SDVOC_GREEN#
EXP_TXN6/SDVOC_BLUE#
PCI - EXPRESS GRAPHICS
EXP_TXP1/SDVOB_GREEN
EXP_TXP5/SDVOC_GREEN
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP1/SDVO_INT
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0/SDVOB_RED#
EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#
EXP_TXN7/SDVOC_CLKN
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0/SDVOB_RED
EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP
EXP_TXP4/SDVOC_RED
EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
PEGCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
24.9_0603_1%
1 2
PEG_RXN[0..15]
PEG_RXP[0..15]
PEG_TXN[0..15]
PEG_TXP[0..15]
R40
+1.5VS_PCIE
PEG_RXN[0..15] <16>
PEG_RXP[0..15] <16>
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
PEG_TXN[0..15] <16>
PEG_TXP[0..15] <16>
+2.5VS
1 2
1 2
1 2
1 2
1 2
1 2
LCD_CLK
R362 2.2K_0402_5%
LCD_DAT
R363 2.2K_0402_5%
LCTLA_CLK
R385 2.2K_0402_5%
LCTLB_DAT
R364 2.2K_0402_5%
CLK_DDC2
R360 2.2K_0402_5%
DAT_DDC2
R361 2.2K_0402_5%
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
2
Date: Sheet
1
of
10 52
5
U5F
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
POWER
VTT8
N11
VTT9
M11
D D
+VCCP
1
C391
C392
2
2.2U_0805_10V6K
4.7U_0805_6.3V6K
1
C29
C C
0.47U_0603_16V7K
2
1
1
C74
C28
2
2
0.47U_0603_16V7K
B B
0.1U_0402_16V4Z
1
C674
C675
2
VTT10
L11
VTT11
K11
VTT12
W10
VTT13
V10
VTT14
U10
VTT15
T10
VTT16
R10
VTT17
P10
VTT18
N10
VTT19
M10
VTT20
K10
VTT21
J10
1
VTT22
Y9
VTT23
W9
VTT24
U9
VTT25
2
R9
VTT26
P9
VTT27
N9
VTT28
M9
VTT29
L9
VTT30
J9
VTT31
N8
VTT32
M8
VTT33
N7
VTT34
M7
VTT35
N6
VTT36
M6
VTT37
A6
VTT38
N5
VTT39
M5
VTT40
N4
VTT41
M4
VTT42
N3
VTT43
M3
VTT44
N2
VTT45
M2
VTT46
B2
VTT47
V1
VTT48
N1
VTT49
M1
VTT50
G1
VTT51
1
C52
2
0.22U_0603_10V7K
0.22U_0603_10V7K
ALVISO_BGA1257
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C676
2
0.1U_0402_16V4Z
1
1
C678
C677
2
2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
0.1U_0402_16V4Z
1
2
V1.8_DDR_CAP1
AM37
V1.8_DDR_CAP2
AH37
V1.8_DDR_CAP5
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
Note: Place near chip.
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
V1.8_DDR_CAP6
AP8
V1.8_DDR_CAP4
AM1
V1.8_DDR_CAP3
AE1
C413
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
Note : All VCCSM pin
shorted internally.
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
10U_1206_6.3V6M
C135
C127
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C412
2
2
C429
10U_1206_6.3V6M
C408
+2.5V
4
W=20 mils
U5E
+VCCP
0.1U_0402_16V7K
0.1U_0402_16V4Z
C468
+2.5V+VCCP
0.1U_0402_16V7K
C420
C393
0.1U_0402_16V4Z
1
2
1
2
10U_1206_6.3V6M
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
C388
0.1U_0402_16V4Z
1
2
0.1U_0402_16V7K
1
2
1
C130
+
2
0.1U_0402_16V4Z
1
2
1
1
C478
C443
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C475
C465
1
1
2
2
330U_D2E_2.5VM
0.1U_0402_16V4Z
1
1
C418
C411
2
2
T29
VCC0
R29
VCC1
N29
VCC2
M29
VCC3
K29
VCC4
J29
1
2
VCC5
V28
VCC6
U28
VCC7
T28
VCC8
R28
VCC9
P28
VCC10
N28
VCC11
M28
VCC12
L28
VCC13
K28
VCC14
J28
VCC15
H28
VCC16
G28
VCC17
V27
VCC18
U27
VCC19
T27
VCC20
R27
VCC21
P27
VCC22
N27
VCC23
M27
VCC24
L27
VCC25
K27
VCC26
J27
VCC27
H27
VCC28
K26
VCC29
H26
VCC30
K25
VCC31
J25
VCC32
K24
VCC33
K23
VCC34
K22
VCC35
K21
VCC36
W20
VCC37
U20
VCC38
T20
VCC39
K20
VCC40
V19
VCC41
U19
VCC42
K19
VCC43
W18
VCC44
V18
VCC45
T18
VCC46
K18
VCC47
K17
VCC48
AC1
VCCD_HMPLL1
AC2
VCCD_HMPLL2
B23
VCCA_DPLLA
C35
VCCA_DPLLB
AA1
VCCA_HPLL
AA2
VCCA_MPLL
ALVISO_BGA1257
VCC_SYNC
1
C30
2
10U_1206_6.3V6M
3
POWER
+2.5VS
12
12
1
C371
2
0.1U_0402_16V4Z
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCHV0
VCCHV1
VCCHV2
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
R28
0_0402_5%
R31
0_0402_5%@
1
C355
F17
E17
D18
C18
F18
E18
H18
G18
D19
H17
B26
B25
A25
A35
B22
B21
A21
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
H20
F19
E19
G19
2
0.1U_0402_16V4Z
1@
R736 0_0603_5%
1 2
R739 0_0603_5%
1 2
1@
+2.5VS
R740 0_0603_5% 1@
1 2
4.7U_0805_6.3V6K
1
C473
C131
2
0.1U_0402_16V4Z
VCC_SYNC
C367
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C681
C680
2
2
+3VS
1
2
C366
0.022U_0402_16V7K
1
C372
2
0.1U_0402_16V4Z
+1.5VS_PM
+2.5VS_PM
C329
+1.5VS_PCIE
1
+
2
100U_D2_6.3VM
1
1
2
2
C363
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C682
2
2
+1.5VS
1
2
C353
1
2
C452
220U_D2_4VM
+2.5VS
Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.
1
C683
2
0.022U_0402_16V7K
+1.5VS
+2.5VS
1
+
2
0.1U_0402_16V4Z
C341
1
2
C684
1
1
2
2
0.1U_0402_16V4Z
C339 0.022U_0402_16V7K
R737 0_0603_5%2@
1 2
R738 0_0603_5%2@
1 2
+2.5VS_LVDSPM
C340
0.1U_0402_16V4Z
1
C433
C380
2
10U_1206_6.3V6M
+VCCP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C685
2
2
1
1
2
2
C349
0.1U_0402_16V4Z
+2.5VS
1
2
10U_1206_6.3V6M
C399
0.1U_0402_16V4Z
Close B26,B25,A25
+1.5VS_PM
0.1U_0402_16V4Z
1
C354
2
C336 0.022U_0402_16V7K
R741
0_0603_5%
2@
1 2
R134
0.5_0805_1%
1 2
1
1
C126
2
2
10U_1206_6.3V6M
10U_1206_6.3V6M
1
2
3GRLL_R
1
C365
0.1U_0402_16V4Z
2
C346
CHB1608U301_0603
+2.5VS_PM
1
2
0.01U_0402_16V7K
0_0603_5%
L14
L26
L9
C352
L13
1
2
0.1U_0402_16V4Z
12
0_0603_5%
12
0_0603_5%
12
+1.5VS+1.5VS_3GPLL
12
C128
C334
10U_1206_6.3V6M
1
2
0.1U_0402_16V4Z
+2.5VS+2.5VS_3GBG
+2.5VS
1
C342
2
0.1U_0402_16V4Z
+1.5VS
C438
0.1U_0402_16V4Z
1
C31
0.1U_0402_16V4Z
2
1
1
2
+1.5VS+1.5VS_DDRDLL
1
C140
2
1
2
0.1U_0402_16V4Z
L19
CHB1608U301_0603
+1.5VS
A A
1 2
+VCCP +VCCP+2.5VS +3VS
R805
1 2
10K_0402_5%
@
1
C348
+
2
5
330U_D2E_2.5VM
0.1U_0402_16V4Z
C347
1
2
D21
1N4148_SOD80
@
12
+1.5VS
CHB1608U301_0603
1 2
L11
R806
1 2
10K_0402_5%
@
+1.5VS_HPLL
1
C81
+
2
330U_D2E_2.5VM
C404
1
2
D22
1N4148_SOD80
@
CHB1608U301_0603
0.1U_0402_16V4Z
+1.5VS
12
1 2
4
+1.5VS_MPLL
L23
1
1
+
C403
C409
2
2
0.1U_0402_16V4Z
330U_D2E_2.5VM
+1.5VS
CHB1608U301_0603
1 2
+1.5VS_DPLLA+1.5VS_DPLLB
L20
330U_D2E_2.5VM
0.1U_0402_16V4Z
1
C330
C345
1
+
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
2
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
Date: Sheet
1
of
11 52
5
4
3
2
1
+VCCP
W12
W13
AA12
AA13
W14
AA14
AB14
W15
AA15
AB15
W16
AA16
AB16
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
AA21
AB21
AA22
AB22
AA23
AB23
AA24
AB24
AA25
AB25
AA26
AB26
W25
W26
L12
M12
N12
P12
R12
T12
U12
V12
L13
M13
N13
P13
R13
T13
U13
V13
Y12
Y13
L14
M14
N14
P14
R14
T14
U14
V14
Y14
L15
M15
N15
P15
R15
T15
U15
V15
Y15
L16
M16
N16
P16
R16
T16
U16
V16
Y16
R17
Y17
R21
Y21
Y22
Y23
Y24
Y25
Y26
V25
L26
M26
N26
P26
R26
T26
U26
V26
5
U5H
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
ALVISO_BGA1257
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
NCTF
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
D D
C C
B B
A A
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+2.5V
C686
C692
1
2
+VCCP
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C687
C688
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C693
C694
2
C698
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C689
C690
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C695
C696
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C702
C699
2
2
4
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C691
2
2
U5I
Y1
VSS271
D2
VSS270
G2
VSS269
J2
VSS268
L2
VSS260
P2
VSS259
T2
VSS258
V2
VSS257
AD2
VSS256
AE2
VSS255
AH2
VSS254
AL2
VSS253
AN2
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS
Security Classification
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
+VCCP
0.1U_0402_10V6K
1
1
C697
2
2
+VCCP
0.1U_0402_10V6K
1
1
C703
2
2
Y11
0.1U_0402_10V6K
0.1U_0402_10V6K
ALVISO_BGA1257
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
B36
VSSALVDS
AA11
VSS195
AF11
VSS194
AG11
VSS193
AJ11
VSS192
AL11
VSS191
AN11
VSS190
B12
VSS189
D12
VSS188
J12
VSS187
A14
VSS186
B14
VSS185
F14
VSS184
J14
VSS183
K14
VSS182
AG14
VSS181
AJ14
VSS180
AL14
VSS179
AN14
VSS178
C15
VSS177
K15
VSS176
A16
VSS175
D16
VSS174
H16
VSS173
K16
VSS172
AL16
VSS171
C17
VSS170
G17
VSS169
AF17
VSS168
AJ17
VSS167
AN17
VSS166
A18
VSS165
B18
VSS164
U18
VSS163
AL18
VSS162
C19
VSS161
H19
VSS160
J19
VSS159
T19
VSS158
W19
VSS157
AG19
VSS156
AN19
VSS155
A20
VSS154
D20
VSS153
E20
VSS152
F20
VSS151
G20
VSS150
V20
VSS149
AK20
VSS148
C21
VSS147
F21
VSS146
AF21
VSS145
AN21
VSS144
A22
VSS143
D22
VSS142
E22
VSS141
J22
VSS140
AH22
VSS139
AL22
VSS138
H23
VSS137
AF23
VSS136
B24
VSS135
D24
VSS134
F24
VSS133
J24
VSS132
AG24
VSS131
AJ24
VSS130
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
U5J
AL24
VSS267
AN24
VSS266
A26
VSS265
E26
VSS264
G26
VSS263
J26
VSS262
B27
VSS261
E27
VSS129
G27
VSS128
W27
VSS127
AA27
VSS126
AB27
VSS125
AF27
VSS124
AG27
VSS123
AJ27
VSS122
AL27
VSS121
AN27
VSS120
E28
VSS119
W28
VSS118
AA28
VSS117
AB28
VSS116
AC28
VSS115
A29
VSS114
D29
VSS113
E29
VSS112
F29
VSS111
G29
VSS110
H29
VSS109
L29
VSS108
P29
VSS107
U29
VSS106
V29
VSS105
W29
VSS104
AA29
VSS103
AD29
VSS102
AG29
VSS101
AJ29
VSS100
AM29
VSS99
C30
VSS98
Y30
VSS97
AA30
VSS96
AB30
VSS95
AC30
VSS94
AE30
VSS93
AP30
VSS92
D31
VSS91
E31
VSS90
F31
VSS89
G31
VSS88
H31
VSS87
J31
VSS86
K31
VSS85
L31
VSS84
M31
VSS83
N31
VSS82
P31
VSS81
R31
VSS80
T31
VSS79
U31
VSS78
V31
VSS77
W31
VSS76
AD31
VSS75
AG31
VSS74
AL31
VSS73
A32
VSS72
C32
VSS71
Y32
VSS70
AA32
VSS69
AB32
VSS68
ALVISO_BGA1257
2
VSS
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
Date: Sheet
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
of
1
12 52
A
B
C
D
E
F
G
H
DDR_A_MA[0..13]<9>
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA9
DDR_A_MA7
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA10
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
DDR_A_MA5
DDR_A_WE#
DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_BS#1
DDR_CKE0
DDR_CKE1
DDR_SCS#1
DDR_SCS#0
C
DDR_A_D4
DDR_A_D1
DDR_A_D5
DDR_A_D2
DDR_A_DM0
DDR_A_D3
DDR_A_DQS0
DDR_A_D0
DDR_A_D7
DDR_A_D6
DDR_A_D13
DDR_A_D11
DDR_A_D10
DDR_A_D8
DDR_A_D9
DDR_A_DM1
DDR_A_D12
DDR_A_DQS1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D16
DDR_A_D17
DDR_A_DQS2
DDR_A_D18
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D19
DDR_A_D28
DDR_A_D24
DDR_A_D29
DDR_A_DQS3
DDR_A_D25
DDR_A_DM3
DDR_A_D31
DDR_A_D26
DDR_A_D30
DDR_A_D27
DDR_A_D36
DDR_A_D37
DDR_A_D33
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D38
DDR_A_D39
DDR_A_DQS4
DDR_A_DM4
DDR_A_D44
DDR_A_D41
DDR_A_D40
DDR_A_D45
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D46
DDR_A_D47
DDR_A_DM5
DDR_A_D53
DDR_A_D48
DDR_A_D52
DDR_A_D49
DDR_A_D55
DDR_A_D54
DDR_A_D50
DDR_A_D51
DDR_A_DM6
DDR_A_DQS6
DDR_A_D58
DDR_A_D63
DDR_A_D61
DDR_A_D57
DDR_A_D56
DDR_A_DM7
DDR_A_D59
DDR_A_D62
DDR_A_D60
DDR_A_DQS7
A
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
1 2
R647 10_0402_5%
1 2
R257 10_0402_5%
1 2
R256 10_0402_5%
1 2
R650 10_0402_5%
1 2
R255 10_0402_5%
1 2
R253 10_0402_5%
1 2
R648 10_0402_5%
1 2
R646 10_0402_5%
1 2
R254 10_0402_5%
1 2
R649 10_0402_5%
1 2
R252 10_0402_5%
1 2
R248 10_0402_5%
1 2
R655 10_0402_5%
1 2
R651 10_0402_5%
1 2
R251 10_0402_5%
1 2
R250 10_0402_5%
1 2
R652 10_0402_5%
1 2
R653 10_0402_5%
1 2
R654 10_0402_5%
1 2
R249 10_0402_5%
1 2
R657 10_0402_5%
1 2
R246 10_0402_5%
1 2
R656 10_0402_5%
1 2
R247 10_0402_5%
1 2
R658 10_0402_5%
1 2
R659 10_0402_5%
1 2
R245 10_0402_5%
1 2
R660 10_0402_5%
1 2
R243 10_0402_5%
1 2
R244 10_0402_5%
1 2
R662 10_0402_5%
1 2
R661 10_0402_5%
1 2
R241 10_0402_5%
1 2
R663 10_0402_5%
1 2
R242 10_0402_5%
1 2
R240 10_0402_5%
1 2
R238 10_0402_5%
1 2
R664 10_0402_5%
1 2
R665 10_0402_5%
1 2
R239 10_0402_5%
1 2
R666 10_0402_5%
1 2
R237 10_0402_5%
1 2
R667 10_0402_5%
1 2
R236 10_0402_5%
1 2
R233 10_0402_5%
1 2
R669 10_0402_5%
1 2
R234 10_0402_5%
1 2
R670 10_0402_5%
1 2
R668 10_0402_5%
1 2
R235 10_0402_5%
1 2
R274 10_0402_5%
1 2
R679 10_0402_5%
1 2
R273 10_0402_5%
1 2
R680 10_0402_5%
1 2
R681 10_0402_5%
1 2
R271 10_0402_5%
1 2
R683 10_0402_5%
1 2
R682 10_0402_5%
1 2
R270 10_0402_5%
1 2
R272 10_0402_5%
1 2
R685 10_0402_5%
1 2
R268 10_0402_5%
1 2
R684 10_0402_5%
1 2
R269 10_0402_5%
1 2
R266 10_0402_5%
1 2
R687 10_0402_5%
1 2
R688 10_0402_5%
1 2
R265 10_0402_5%
1 2
R267 10_0402_5%
1 2
R686 10_0402_5%
1 2
R690 10_0402_5%
1 2
R261 10_0402_5%
1 2
R264 10_0402_5%
1 2
R692 10_0402_5%
1 2
R263 10_0402_5%
1 2
R262 10_0402_5%
1 2
R693 10_0402_5%
1 2
R260 10_0402_5%
1 2
R689 10_0402_5%
1 2
R691 10_0402_5%
B
DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS[0..7]
DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_DM0
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6
DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19
DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27
DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4
DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5
DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6
DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7
DDR_D[0..63] <14>
DDR_DM[0..7] <14>
DDR_DQS[0..7] <14>
+1.25VS
1 2
R673 56_0402_5%
1 2
R296 56_0402_5%
1 2
R282 56_0402_5%
1 2
R674 56_0402_5%
1 2
R675 56_0402_5%
1 2
R281 56_0402_5%
1 2
R280 56_0402_5%
1 2
R676 56_0402_5%
1 2
R677 56_0402_5%
1 2
R278 56_0402_5%
1 2
R294 56_0402_5%
1 2
R288 56_0402_5%
1 2
R279 56_0402_5%
1 2
R295 56_0402_5%
1 2
R293 56_0402_5%
1 2
R286 56_0402_5%
1 2
R276 56_0402_5%
1 2
R287 56_0402_5%
1 2
R277 56_0402_5%
1 2
R283 56_0402_5%
1 2
R672 56_0402_5%
1 2
R275 56_0402_5%
1 2
R678 56_0402_5%
DDR_A_D[0..63]<9>
DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>
1 1
2 2
3 3
4 4
DDR_A_MA[0..13]
+2.5V
JDIMM2
1
VREF
3
DDR_D0
DDR_D4
DDR_DQS0
DDR_D6
DDR_D2
DDR_D8
DDR_D12
DDR_DQS1
DDR_D14
DDR_D10
DDR_CLK0<8>
DDR_CLK0#<8>
DDR_D16
DDR_D20
DDR_DQS2
DDR_D18
DDR_D22
DDR_D24
DDR_D28
DDR_DQS3
DDR_D26
DDR_D30
DDR_CKE1<8>
DDR_A_BS#0<9>
DDR_A_WE#<9>
DDR_SCS#0<8>
CK_SDATA<14,18>
CK_SCLK<14,18>
DDR_CKE1 DDR_CKE0
DDR_A_MA13
DDR_A_MA12
DDR_A_MA9
DDR_A_MA7
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_SCS#0 DDR_SCS#1
DDR_D36
DDR_D33
DDR_DQS4
DDR_D35
DDR_D39
DDR_D41
DDR_D45
DDR_DQS5
DDR_D46
DDR_D42
DDR_D52
DDR_D53
DDR_DQS6
DDR_D54
DDR_D50
DDR_D60
DDR_D56
DDR_DQS7
DDR_D57
DDR_D59
CK_SDATA
CK_SCLK
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU/A13
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
TYCO_1612560-1
2005/03/01 2006/03/01
E
Compal Secret Data
Deciphered Date
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
VSS
VDD
BA1
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
DU
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
F
+2.5V
DDR_D1
DDR_D5
DDR_DM0
DDR_D7
DDR_D3
DDR_D13
DDR_D9
DDR_DM1
DDR_D15
DDR_D11
DDR_D17
DDR_D21
DDR_DM2
DDR_D19
DDR_D23
DDR_D25
DDR_D29
DDR_DM3
DDR_D27
DDR_D31
DDR_A_MA11
DDR_A_MA8
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_A_CAS#
DDR_D37
DDR_D32
DDR_DM4
DDR_D38
DDR_D34
DDR_D44
DDR_D40
DDR_DM5
DDR_D43
DDR_D47
DDR_D49
DDR_D48
DDR_DM6
DDR_D55
DDR_D51
DDR_D61
DDR_D58
DDR_DM7
DDR_D63
DDR_D62
+SDREF_DIMM
R227
12
0_0402_5%
+SDREF
1
C237
0.1U_0402_16V4Z
2
DDR_CKE0 <8>
DDR_A_BS#1 <9>
DDR_A_RAS# <9>
DDR_A_CAS# <9>
DDR_SCS#1 <8>
DDR_CLK1# <8>
DDR_CLK1 <8>
Title
<Title>
Size Document Number Rev
LA-2362 1
B
Friday, March 11, 2005
Date: Sheet
G
13 52
H
of
A
DDR_D[0..63]
DDR_DM[0..7]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DDR_DQS[0..7]
+1.25VS
DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_DM0
1 1
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6
DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15
DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19
DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
2 2
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27
DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4
1 2
R597 56_0402_5%
1 2
R596 56_0402_5%
1 2
R215 56_0402_5%
1 2
R600 56_0402_5%
1 2
R598 56_0402_5%
1 2
R599 56_0402_5%
1 2
R214 56_0402_5%
1 2
R216 56_0402_5%
1 2
R212 56_0402_5%
1 2
R213 56_0402_5%
1 2
R211 56_0402_5%
1 2
R210 56_0402_5%
1 2
R602 56_0402_5%
1 2
R601 56_0402_5%
1 2
R209 56_0402_5%
1 2
R603 56_0402_5%
1 2
R208 56_0402_5%
1 2
R605 56_0402_5%
1 2
R207 56_0402_5%
1 2
R604 56_0402_5%
1 2
R607 56_0402_5%
1 2
R205 56_0402_5%
1 2
R606 56_0402_5%
1 2
R206 56_0402_5%
1 2
R204 56_0402_5%
1 2
R203 56_0402_5%
1 2
R608 56_0402_5%
1 2
R202 56_0402_5%
1 2
R610 56_0402_5%
1 2
R609 56_0402_5%
1 2
R200 56_0402_5%
1 2
R201 56_0402_5%
1 2
R612 56_0402_5%
1 2
R199 56_0402_5%
1 2
R611 56_0402_5%
1 2
R613 56_0402_5%
1 2
R197 56_0402_5%
1 2
R198 56_0402_5%
1 2
R614 56_0402_5%
1 2
R615 56_0402_5%
1 2
R195 56_0402_5%
1 2
R584 56_0402_5%
1 2
R196 56_0402_5%
1 2
R583 56_0402_5%
1 2
R194 56_0402_5%
1 2
R193 56_0402_5%
1 2
R587 56_0402_5%
1 2
R586 56_0402_5%
1 2
R192 56_0402_5%
1 2
R585 56_0402_5%
R183 56_0402_5%
R574 56_0402_5%
R182 56_0402_5%
R573 56_0402_5%
R181 56_0402_5%
R179 56_0402_5%
R577 56_0402_5%
R180 56_0402_5%
R576 56_0402_5%
R575 56_0402_5%
R579 56_0402_5%
R178 56_0402_5%
R176 56_0402_5%
R582 56_0402_5%
R174 56_0402_5%
R578 56_0402_5%
R177 56_0402_5%
R175 56_0402_5%
R581 56_0402_5%
R580 56_0402_5%
R169 56_0402_5%
R591 56_0402_5%
R173 56_0402_5%
R595 56_0402_5%
R172 56_0402_5%
R170 56_0402_5%
R171 56_0402_5%
R594 56_0402_5%
R592 56_0402_5%
R593 56_0402_5%
+1.25VS
1 2
R189 56_0402_5%
1 2
R565 56_0402_5%
1 2
R188 56_0402_5%
1 2
R168 56_0402_5%
1 2
R566 56_0402_5%
1 2
R567 56_0402_5%
3 3
1 2
R167 56_0402_5%
1 2
R185 56_0402_5%
1 2
R569 56_0402_5%
1 2
R186 56_0402_5%
1 2
R568 56_0402_5%
1 2
R562 56_0402_5%
1 2
R187 56_0402_5%
1 2
R190 56_0402_5%
1 2
R184 56_0402_5%
1 2
R166 56_0402_5%
1 2
R571 56_0402_5%
1 2
R572 56_0402_5%
1 2
R570 56_0402_5%
1 2
R191 56_0402_5%
1 2
R564 56_0402_5%
1 2
R165 56_0402_5%
1 2
R563 56_0402_5%
DDR_B_MA12
DDR_B_MA11
DDR_B_MA9
DDR_B_MA7
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA10
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA4
DDR_B_MA5
DDR_B_MA13
DDR_B_WE#
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_BS#1
DDR_CKE3
DDR_CKE2
DDR_SCS#2
DDR_SCS#3
DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5
DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6
DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7
B
DDR_D[0..63] <13>
DDR_DM[0..7] <13>
DDR_DQS[0..7] <13>
C
DDR_B_MA[0..13]<9>
DDR_B_MA[0..13]
DDR_CLK3<8>
DDR_CLK3#<8>
DDR_CKE3<8>
DDR_B_BS#0<9>
DDR_B_WE#<9>
DDR_SCS#2<8>
CK_SDATA<13,18>
CK_SCLK<13,18>
DDR_B_MA13
DDR_B_MA12
DDR_B_MA9
DDR_B_MA7
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_SCS#2
DDR_D0
DDR_D4
DDR_DQS0
DDR_D6
DDR_D2
DDR_D8
DDR_D12
DDR_DQS1
DDR_D14
DDR_D10
DDR_D16
DDR_D20
DDR_DQS2
DDR_D18
DDR_D22
DDR_D24
DDR_D28
DDR_DQS3
DDR_D26
DDR_D30
DDR_CKE3
DDR_D36
DDR_D33
DDR_DQS4
DDR_D35
DDR_D39
DDR_D41
DDR_D45
DDR_DQS5
DDR_D46
DDR_D42
DDR_D52
DDR_D53
DDR_DQS6
DDR_D54
DDR_D50
DDR_D60
DDR_D58
DDR_DQS7
DDR_D57
DDR_D59
CK_SDATA
CK_SCLK
+3VS
+2.5V
JDIMM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDR_CKE2
DDR_B_BS#1
DDR_B_RAS#DDR_B_BS#0
DDR_B_CAS#DDR_B_WE#
DDR_SCS#3
DDR_D1
DDR_D5
DDR_DM0
DDR_D7
DDR_D3
DDR_D13
DDR_D9
DDR_DM1
DDR_D15
DDR_D11
DDR_D17
DDR_D21
DDR_DM2
DDR_D19
DDR_D23
DDR_D25
DDR_D29
DDR_DM3
DDR_D27
DDR_D31
DDR_B_MA11
DDR_B_MA8
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_D37
DDR_D32
DDR_DM4
DDR_D38
DDR_D34
DDR_D44
DDR_D40
DDR_DM5
DDR_D43
DDR_D47
DDR_D49
DDR_D48
DDR_DM6
DDR_D55
DDR_D51
DDR_D61
DDR_D56
DDR_DM7
DDR_D63
DDR_D62
+3VS
+SDREF_DIMM
1
2
DDR_CKE2 <8>
DDR_SCS#3 <8>
DDR_CLK4# <8>
DDR_CLK4 <8>
C188
0.1U_0402_16V4Z
DDR_B_BS#1 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
E
KLINK_5763-2-111
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
<Title>
Size Document Number Rev
LA-2362 1
B
Friday, March 11, 2005
D
Date: Sheet
E
of
14 52
A
Layout note :
Distribute as close as possible
to DDR-SODIMM.
+2.5V
B
C
D
E
1 1
1
C190
0.1U_0402_16V4Z
2
+2.5V +2.5V
1
C227
0.1U_0402_16V4Z
2
1
C191
0.1U_0402_16V4Z
2
1
C267
0.1U_0402_16V4Z
2
1
C189
0.1U_0402_16V4Z
2
1
C266
0.1U_0402_16V4Z
2
1
C193
0.1U_0402_16V4Z
2
1
C263
0.1U_0402_16V4Z
2
1
C218
0.1U_0402_16V4Z
2
1
C262
0.1U_0402_16V4Z
2
1
C217
0.1U_0402_16V4Z
2
1
C214
0.1U_0402_16V4Z
2
1
C216
0.1U_0402_16V4Z
2
1
+
C163
150U_D2_6.3VM
2
1
C215
0.1U_0402_16V4Z
2
1
+
C238
150U_D2_6.3VM
2
1
C230
0.1U_0402_16V4Z
2
1
C229
0.1U_0402_16V4Z
2
1
C228
0.1U_0402_16V4Z
2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2 2
3 3
+1.25VS
1
C253
0.1U_0402_16V4Z
2
+1.25VS
1
C243
0.1U_0402_16V4Z
2
+1.25VS
1
C250
0.1U_0402_16V4Z
2
1
C252
0.1U_0402_16V4Z
2
1
C242
0.1U_0402_16V4Z
2
1
C249
0.1U_0402_16V4Z
2
1
C251
0.1U_0402_16V4Z
2
1
C578
0.1U_0402_16V4Z
2
1
C248
0.1U_0402_16V4Z
2
1
C590
0.1U_0402_16V4Z
2
1
C579
0.1U_0402_16V4Z
2
1
C576
0.1U_0402_16V4Z
2
1
C589
0.1U_0402_16V4Z
2
1
C580
0.1U_0402_16V4Z
2
1
C585
0.1U_0402_16V4Z
2
1
C588
0.1U_0402_16V4Z
2
1
C256
0.1U_0402_16V4Z
2
1
C583
0.1U_0402_16V4Z
2
1
C247
0.1U_0402_16V4Z
2
1
C255
0.1U_0402_16V4Z
2
1
C584
0.1U_0402_16V4Z
2
1
C246
0.1U_0402_16V4Z
2
1
C254
0.1U_0402_16V4Z
2
1
C575
0.1U_0402_16V4Z
2
1
C245
0.1U_0402_16V4Z
2
1
C582
0.1U_0402_16V4Z
2
1
C586
0.1U_0402_16V4Z
2
1
C244
0.1U_0402_16V4Z
2
1
C581
0.1U_0402_16V4Z
2
1
C587
0.1U_0402_16V4Z
2
+1.25VS
1
C544
0.1U_0402_16V4Z
2
1
C653
0.1U_0402_16V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C536
0.1U_0402_16V4Z
2
1
C654
0.1U_0402_16V4Z
2
C
1
C208
0.1U_0402_16V4Z
2
1
C655
0.1U_0402_16V4Z
2
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
D
Title
<Title>
Size Document Number Rev
LA-2362 1
Custom
Friday, March 11, 2005
Date: Sheet
E
of
15 52
B
1
C529
0.1U_0402_16V4Z
2
1
C651
0.1U_0402_16V4Z
2
1
C535
0.1U_0402_16V4Z
2
1
C652
0.1U_0402_16V4Z
2
1
C200
0.1U_0402_16V4Z
2
+1.25VS
1
C646
0.1U_0402_16V4Z
2
4 4
1
C201
0.1U_0402_16V4Z
2
1
C647
0.1U_0402_16V4Z
2
A
1
C202
0.1U_0402_16V4Z
2
1
C648
0.1U_0402_16V4Z
2
1
C531
0.1U_0402_16V4Z
2
1
C649
0.1U_0402_16V4Z
2
1
C530
0.1U_0402_16V4Z
2
1
C650
0.1U_0402_16V4Z
2
5
PEG_TXN15 PEG_A_TXN_15
PEG_TXP15
PEG_TXN14
PEG_TXP14
D D
C C
B B
PEG_TXN13
PEG_TXP13
PEG_TXN12
PEG_TXP12
PEG_TXN11
PEG_TXP11
PEG_TXN10
PEG_TXP10
PEG_TXN9
PEG_TXP9 PEG_A_TXP_9
PEG_TXN7
PEG_TXP7
PEG_TXN6
PEG_TXP6
PEG_TXN5
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXN2
PEG_TXP2
PEG_TXN1
PEG_TXP1
PEG_TXN0
PEG_TXP0
B+I
FBM-L11-160808-800LMT_0603
FBM-L11-160808-800LMT_0603
+3VS
+2.5V
2@
1
C704
2
Modify for 1.8vs move to VGA BD
A A
R328
2@
1 2
1 2
R329
2@
0.1U_0402_16V4Z
2@
1
C705
2
+3VS
C97 0.1U_0402_16V4Z2@
1 2
C94 0.1U_0402_16V4Z2@
C93 0.1U_0402_16V4Z2@
1 2
C88 0.1U_0402_16V4Z2@
C87 0.1U_0402_16V4Z2@
1 2
C83 0.1U_0402_16V4Z2@
C82 0.1U_0402_16V4Z2@
1 2
C80 0.1U_0402_16V4Z2@
C79 0.1U_0402_16V4Z2@
1 2
C77 0.1U_0402_16V4Z2@
C76 0.1U_0402_16V4Z2@
1 2
C73 0.1U_0402_16V4Z2@
C72 0.1U_0402_16V4Z2@
1 2
C71 0.1U_0402_16V4Z2@
C70 0.1U_0402_16V4Z2@
1 2
C67 0.1U_0402_16V4Z2@
C66 0.1U_0402_16V4Z2@
1 2
C65 0.1U_0402_16V4Z2@
C64 0.1U_0402_16V4Z2@
1 2
C61 0.1U_0402_16V4Z2@
C59 0.1U_0402_16V4Z2@
1 2
C57 0.1U_0402_16V4Z2@
C56 0.1U_0402_16V4Z2@
1 2
C55 0.1U_0402_16V4Z2@
C54 0.1U_0402_16V4Z2@
1 2
C51 0.1U_0402_16V4Z2@
C50 0.1U_0402_16V4Z2@
1 2
C49 0.1U_0402_16V4Z2@
C48 0.1U_0402_16V4Z2@
1 2
C44 0.1U_0402_16V4Z2@
C43 0.1U_0402_16V4Z2@
1 2
C39 0.1U_0402_16V4Z2@
B+P
0.1U_0402_16V4Z
10
B+P B+I
2
2
C307
1
C309
C313
1
2@
2@
0.1U_0603_50V4Z
0.1U_0603_50V4Z
1
1
C310
2
2
0.047U_0402_16V4Z
0.047U_0402_16V4Z
5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SMB_EC_CK2<32,34>
SMB_EC_DA2<32,34>
JVGAP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
ACES_85205-10002@
2
C308
1
2@
0.1U_0603_50V4Z
1
C311
2
0.047U_0402_16V4Z
SUSP#<24,32,33,37,42>
C/R_VGA<17>
COMP/B_VGA<17>
Y/G_VGA<17>
VSYNC_VGA<17>
HSYNC_VGA<17>
VGA_BLU<17>
VGA_GRN<17>
VGA_RED<17>
SMBCLK_VGA<17>
SMBDAT_VGA<17>
2
C314
1
2@
0.1U_0603_50V4Z
BK_EN<10>
BKOFF#<32>
BIA<10,32>
PEG_A_TXP_15
PEG_A_TXN_14
PEG_A_TXP_14
PEG_A_TXN_13
PEG_A_TXP_13
PEG_A_TXN_12
PEG_A_TXP_12
PEG_A_TXN_11
PEG_A_TXP_11
PEG_A_TXN_10
PEG_A_TXP_10
PEG_A_TXN_9
PEG_A_TXN_8PEG_TXN8
PEG_A_TXP_8PEG_TXP8
PEG_A_TXN_7
PEG_A_TXP_7
PEG_A_TXN_6
PEG_A_TXP_6
PEG_A_TXN_5
PEG_A_TXP_5
PEG_A_TXN_4PEG_TXN4
PEG_A_TXP_4
PEG_A_TXN_3PEG_TXN3
PEG_A_TXP_3
PEG_A_TXN_2
PEG_A_TXP_2
PEG_A_TXN_1
PEG_A_TXP_1
PEG_A_TXN_0
PEG_A_TXP_0
SMB_EC_CK2
SMB_EC_DA2
VSYNC_VGA
HSYNCVGA
VGA_BLU
VGA_GRN
VGA_RED
SMBCLK_VGA
SMBDAT_VGA
4
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
U1
1
A
2
B
1@
2
@
4
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
FOX_QTS0140A-30212@
+5VS
5
P
O
G
3
NC7ST08P5X_SC70-5
+3VS
5
U2
P
A
Y
G
NC7SZ14M5X_SOT23-5
3
R7
@
1 2
0_0402_5%
JVGA1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
DISPLAYOFF#
4
INVT_PWM<32>
4
3
1
1
3
3
5
5
7
7
9
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
PEG_RXN15
PEG_RXP15
PEG_RXN14
PEG_RXP14
PEG_RXN13
PEG_RXP13
PEG_RXN12
PEG_RXP12
PEG_RXN11
PEG_RXP11
PEG_RXN10
PEG_RXP10
PEG_RXN9
PEG_RXP9
PEG_RXN8
PEG_RXP8
PEG_RXN7
PEG_RXP7
PEG_RXN6
PEG_RXP6
PEG_RXN5
PEG_RXP5
PEG_RXN4
PEG_RXP4
PEG_RXN3
PEG_RXP3
PEG_RXN2
PEG_RXP2
PEG_RXN1
PEG_RXP1
PEG_RXN0
PEG_RXP0
RUNPWROK
PLTRST_VGA#
THERMATRIP_VGA#
SUSP
CLK_PCIE_VGA#
CLK_PCIE_VGA
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
1@
1 2
R3
1 2
0_0402_5%
R4
0_0402_5%
LCD_CLK<10>
LCD EEPROM
LCD_DAT<10>
RUNPWROK
PLTRST_VGA# <19,21>
THERMATRIP_VGA# <32>
SUSP <37,43,44>
CLK_PCIE_VGA# <18>
CLK_PCIE_VGA <18>
DAC_BRIG <32>
BKOFF# <32>
INVT_PWM <32>
+5VS
+5VALW
+12VALW
PEG_TXP[0..15]
PWM
2.2K_0402_5%
Q20
BSS138_SOT23
+2.5VS
Q21
BSS138_SOT23
B+ B+I
FBM-L11-201209-121LMA05T_0805
C716
0.1U_0603_50V4Z
PEG_TXP[0..15] <10>
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2006/03/01
3
LVDS_A0+<10>
LVDS_A0-<10>
LVDS_A1+<10>
LVDS_A1-<10>
LVDS_A2-<10>
LVDS_A2+<10>
LVDS_AC-<10>
LVDS_AC+<10>
LVDS_B0-<10>
LVDS_B0+<10>
LVDS_B2-<10>
LVDS_B2+<10>
LVDS_B1-<10>
LVDS_B1+<10>
LVDS_BC-<10>
LVDS_BC+<10>
+3VS
12
1@
R336
D
S
13
G
2
1@
G
2
13
D
S
1@
EN_LCDVDD<10>
FBM-201209-121LMA40T
L33
1 2
10U_1206_25V6M
PEG_RXN[0..15]
C717
Compal Secret Data
Deciphered Date
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2LVDS_A2+
LVDS_ACLVDS_AC+
LVDS_B0LVDS_B0+
LVDS_B2LVDS_B2+
LVDS_B1LVDS_B1+
LVDS_BCLVDS_BC+
12
1@
R335
2.2K_0402_5%
LCDP_CLK
1@
LCDP_DAT
Q22
2N7002_SOT23
1@
1
2
C27
0.1U_0603_50V4Z
PEG_RXN[0..15] <10> PEG_TXN[0..15]<10>
+LCDVDD
R344
470_0402_5%
13
D
S
R27
100K_0402_5%
1@
R357
2
1@
2
G
2
1@
75K_0402_5%
1@
2
ACES_88328-4000
42
GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1@
R356
100K_0402_5%
1@
1@
2
Q24
DTC124EK_SC59
4
Q25
D
1 3
1@
2
G
0.1U_0603_50V4Z
S
G
+5VS
13
Q1
FDS4435_SO8
1
2
3 6
1@
2N7002_SOT23
1
41
GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
JLVDS1
0.1U_0402_16V4Z
+12VALW +LCDVDD +3VS
R355
100K_0402_5%
13
D
Q23
2N7002_SOT23
S
INVPWR_B+
8
7
5
C23
1@
Title
Size Document Number Rev
Custom
Date: Sheet
+3VS
LCDP_CLK
LCDP_DAT
R722
1 2
C318
D
13
1@
R354
150K_0402_5%
1
DAC_BRIG <32>
INVPWR_B+
1@
C323
0.1U_0402_16V4Z
PEG_RXP[0..15] <10>
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
of
16 52
PWM
DISPLAYOFF#
INVPWR_B+++
KC FBM-L11-201209-221LMAT_0805
1
1
1@
1@
2
1@
0.1U_0402_16V4Z
2
SI2302DS_SOT23
S
1@
C321
0.1U_0402_16V4Z
1@
PEG_RXP[0..15]
Q26
G
2
PEG_TXN[0..15]
C320
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
<Title>
LA-2362 1
Friday, March 11, 2005
+LCDVDD
Inverter
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