Compal LA-2362 EAL50, Aspire 3500, Smart 300S, Tin Yat 80A, LA-2362 EAL51 Schematic

5

D D

C C

4

3

2

1

Sonoma Dothan EAL50_1
LA2362 Schematic

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

152

5

4

3

2

1

Compal confidential

Block Diagram

Dothan

D D

uFCPGA CPU

Clock Generator

ICS

Memory
BUS(DDR)
Dual Channel

2.5V 333MHz

Channel A

SO-DIMM X 1

BANK 0, 1

SO-DIMM X 1

BANK 2, 3

Fan Control X1

LED/B

VGA
Board

CRT CONN.

& TV-OUT

HA#(3..31)

System Bus

400 / 533MHz

Alviso Intel 915 PM/GM

GMCH-M

HD#(0..63)

Internal GM

ATI VGA

C C

VGA CONN.

PCI-E 16X

External PM

1257 FC-BGA

SW LED BD

T/P

DMI

1.5V

MINI PCI

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

VIA6301
1394

B B

1394
CONN.

CardBus
Controller

ENE CB712

SDIO
CONN.

3.3V 33MHz

PCI BUS

Slot 0

3.3V 33MHz

RTL 8110SBL
/ G 8100CL /
100

Transformer

& RJ45

LPC BUS

3.3V 33MHz

X BUS

SIO
LPC47N217D

A A

FIR

PIO

SST39VF080

Touch Pad

100MHz

KB910

ICH6

609 BGA

Int.KBD

48MHz / 480Mb

3.3V 24.576MHz

ATA100

HDD

USB2.0

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

CDROM

JUSBP2

JUSBP3

JUSBP1

JUSBP1
RESERVED
RESERVED
RESERVED

BT+MDC

AC-LINK

AC97 CODEC

RTL 250

AMP &

Phone/ MIC
Jack

BT

DC IN

BATT IN/+2.5V

1.5V/1.05V(+VCCP)

5V/3.3V/15V

1.8V / 0.9V

VCORE

CHARGER

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

252

5

4

3

2

1

I2C / SMBUS ADDRESSING

External PCI Devices

IDSEL # PIRQREQ/GNT #DEVICE

LAN
CARD BUS

D D

Cardreader
1394
Wireless LAN(MINI PCI)

AD17
AD20

AD16 2
AD18

0
1

3

@ Depop
1@ EAL51
2@ EAL50
1@ EAL51 VALUE (DELETE SIO/1394)

C C

F
A
B
E
G,H

Power Managment table

Signal

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

Ceramic Capacitor Spec
Guide:

Temperature Characteristics:

0

Symbol

CODE

8

NP0 SH

H

UJ

Z5U

Z5V

9

C0G

I

J

UK

SL

1

A

+12VALW +3V
+3VALW
+5VALW

ON

ON ON ON

ON ON

ON OFF

OFF OFF OFF

2

Z5P

Y5U

B

BJ

3

C

CH

+2.5V

+5V
+12V

ON ON

5

4

Y5V Y5P

E

D

CK

CJ

+CPU_CORE
+VCCP
+5VS

+3VS
+2.5VS
+1.8VS
+1.25VS
+1.5VS

OFF

OFF

6

X5R

F

X7R

SJ

Bringup-Build

SST-Build

PT-Build

ST-Build

QT-Build

SCHEMATICS VERSION LIST

VERSION ISSUE DATE REMARK

0.0A

7

G

PCB Rev

0.1

Tolerance:

+-2%

G

X

H

+-3%

Z

+80,-20%

J

+-5%

A

B

Symbol

CODE

B B

+-0.05PF

KQ

M

+-10%

+-20%

+-0.1PF

N

+-30%

C

+-0.25PF

P

+100,-0%

+-0.5PF +-1PF

+30,-10%

F

D

V

+20,-10%

+40,-20%

Data

First Release

SMBUS Control Table

THERMAL

THERMAL

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

ICH_SMBCLK
ICH_SMBDATA

A A

LCD_DDCCLK
LCD_DDCDATA

5

PC87591L

PC87591L

ICH6-M

Alviso
GM-GP

INVERTER BATT

SERIAL SENSOR
EEPROM

(CPU)

4

SENSOR
(LM75)

SODIMM CLK CHIP

MINI PCI

VGA Thermal

LCD

ADM1032

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

2

Title

<Title>

Size Document Number Rev

LA-2362 1

C

Friday, March 11, 2005

Date: Sheet

1

of

352

ACIN

5

4

3

2

1

+3/5/12VALW

D D

32ms

ON/OFF#

8.5/2.44/3.792ms

t<=10 ms

EC_ON#

t=100 ms

PWRBTN_OUT#

438ms

364us

t=109 ms

SYSON

3/5V 400us 2.5V(1.8ms)

+12/2.5/3/5V

C C

RSMRST#

7.856ms

t<110 ms

117ms

SLP_S3/4/5#

92.88ms

SUSP#

+1.25/1.5/1.8/2.5/3/5VS

+VCCP

VR_ON#

1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)

t>0

2.166ms

1.3ms PGD

5.6ms

B B

CPU_VID

+CPU_CORE

Vgate

SYSPOK

PCIRST/PLTRST#

726us

815.2us

t<110 ms

99ms

t<100 us

1.036ms

2<t<3 RTCCLK

61us

CPU_RST#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

452

5

4

3

2

1

H_A#[3..31]<8>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

ITP_DBRESET#

H_PROCHOT#

R530

1 2

1K_0402_5%@

R464

1 2

1K_0402_5%@

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_CK_ITP
CPU_CK_ITP#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

H_DBSY#
H_DPSLP#
H_DPRSLP#

ITP_BPM#4
ITP_BPM#5

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

D D

H_REQ#[0..4]<8>

CLK_ITP_R#

R110 0_0402_5%

1 2

CLK_ITP_R

R112 0_0402_5%

1 2

@

CLK_ITP<18>
CLK_ITP#<18>

+VCCP

@

1 2

CLK_ITP
CLK_ITP#

R7856_0402_5%

H_RS#[0..2]<8>

C C

B B

A A

H_ADSTB#0<8>
H_ADSTB#1<8>

R111 0_0402_5%@

1 2

R109 0_0402_5%@

1 2

CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>

H_ADS#<8>
H_BNR#<8>
H_BPRI#<8>
H_BR0#<8>
H_DEFER#<8>
H_DRDY#<8>
H_HIT#<8>
H_HITM#<8>

H_LOCK#<8>
H_RESET#<8>

H_TRDY#<8>

H_DBSY#<8>
H_DPSLP#<20>
H_DPRSLP#<20>
H_DPWR#<8>

H_PWRGOOD<20>

H_CPUSLP#<8,20>

T5 PAD
T39 PAD

H_THERMDA<34>
H_THERMDC<34>
H_THERMTRIP#<8,20>

TEST2

TEST1

JCPU1A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>

H_STPCLK# <20>
H_SMI# <20>

H_D#0

A19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

H_D#[0..63] <8>

Test pad as closed as posible

ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1

Place near JITP 0.5"

22.6_0402_1%

H_RESET#

22.6_0402_1%

ITP_TDO

R74

1 2

R87

1 2

ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK

CLK_ITP_R

ITP_TRST#
ITP_TMS
ITP_TDI

Check ITP connector.

R123
56_0402_5%

H_DSTBN#[0..3] <8>

H_DSTBP#[0..3] <8>

R458
200_0402_5%

H_PWRGOOD

1 2

+VCCP

2005/03/01 2006/03/01

Compal Secret Data

Add pullups for PWRGOOD and THERMTRIP per INTEL

Deciphered Date

2

T7PAD
T6PAD
T8PAD
T10PAD
T9PAD
T12PAD
T11PAD

T4PAD
T17PAD

T19PAD
T15PAD

T16PAD
T13PAD
T14PAD

+VCCP

12

R124
56_0402_5%

12

H_PROCHOT#

+3V

R79

150_0402_5%

1 2

+VCCP

54.9_0603_1%

1 2

R745 56_0402_5%

+VCCP

37.4_0402_1%

1 2

150_0402_5%

1 2

680_0402_5%

1 2

27.4_0402_1%

1 2

+VCCP

1

2

R90

R76

54.9_0603_1%

1 2
1 2

39.4

R479

R85

This shall place near CPU

R100

R106

C359

0.1U_0402_10V6K

ITP_DBRESET#

H_RESET#
ITP_BPM#5

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near JITP

+3VS

12

R132
1K_0402_5%

1

PROCHOT# <32>

of

552

1

C

Q6

2

B

2SC2411K_SC59

E

3

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

5

4

3

2

1

R470

+VCCA_PROC

2 1

PAD-OPEN 2x2m@

R422
0_0402_5%

1 2

@

J2

1

1

C516

C150

2

2

10U_1206_6.3V6M

0.01U_0402_16V7K

VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>

@

1 2

+1.5VS

SHORT

R423
0_0402_5%

D D

For test only ,Cmos output

R427
0_0402_5%

+VCCP

1 2

@

R412 10K_0402_5%

@

12

12

R426
0_0402_5%

R411 10K_0402_5%

@

@

12

R410 10K_0402_5%

12

1 2

@

R409 10K_0402_5%

@

12

R425
0_0402_5%

R408 10K_0402_5%

@

12

R413 10K_0402_5%

@

1 2

@

R424
0_0402_5%

CPU Voltage ID

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

C C

R433 0_0402_5%
R434 0_0402_5%
R435 0_0402_5%
R436 0_0402_5%
R437 0_0402_5%
R438 0_0402_5%

12
12
12
12
12
12

1 2

@

54.9_0402_1%@

54.9_0402_1%@

+CPU_CORE

1 2
1 2

R465

+VCCP

VCCSENSE
VSSSENSE

OPEN OPEN OPEN OPEN OPEN OPEN

T3 PAD
T2 PAD
T20 PAD
T31 PAD
T29 PAD

H_PSI#
H_VID0

H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

PSI#<45>

+VCCP

R_A

12

+V_CPU_GTLREF

B B

12

R155
1K_0402_1%

R_B

R153
2K_0402_1%

Layout close CPU

Layout Note:

500 mil max length

27.4_0402_1%

R156

20 mils

12

54.9_0402_1%

R157

5 mils

12

27.4_0402_1%

R416

20 mils

12

5 mils

12

54.9_0402_1%

R417

+V_CPU_GTLREF

CPU_BSEL0<18>
CPU_BSEL1<18>

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

JCPU1B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JCPU1C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

652

5

4

3

2

1

+CPU_CORE

1

C482
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C430
10U_0805_6.3V6M

C100
10U_0805_6.3V6M

C512
10U_0805_6.3V6M

D D

C C

1

C483
10U_0805_6.3V6M

2

1

C421
10U_0805_6.3V6M

2

1

C105
10U_0805_6.3V6M

2

1

C507
10U_0805_6.3V6M

2

1

C460
10U_0805_6.3V6M

2

1

C415
10U_0805_6.3V6M

2

1

C109
10U_0805_6.3V6M

2

1

C502
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C416
10U_0805_6.3V6M

2

1

C114
10U_0805_6.3V6M

2

1

C469
10U_0805_6.3V6M

2

1

C431
10U_0805_6.3V6M

2

1

C480
10U_0805_6.3V6M

2

1

C91
10U_0805_6.3V6M

2

1

C442
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C422
10U_0805_6.3V6M

C481
10U_0805_6.3V6M

C92
10U_0805_6.3V6M

1

C518
10U_0805_6.3V6M

2

1

C113
10U_0805_6.3V6M

2

1

C121
10U_0805_6.3V6M

2

10uF 1206 X5R -> 85 degree

1

C470
10U_0805_6.3V6M

2

1

C108
10U_0805_6.3V6M

2

1

C120
10U_0805_6.3V6M

2

1

C459
10U_0805_6.3V6M

2

1

C104
10U_0805_6.3V6M

2

1

C383
10U_0805_6.3V6M

2

X7R

High Frequence Decoupling

1

C445
10U_0805_6.3V6M

2

1

C99
10U_0805_6.3V6M

2

1

C522
10U_0805_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

330U_D2E_2.5VM_R9

1

C358

B B

+

2

330U_D2E_2.5VM_R9

C378

1

1

C377

+

2

2

@

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

C357

+

+

2

ESR <= 3m ohm

Capacitor > 880 uF

+VCCP

1

C664

0.1U_0402_10V6K

2

+VCCP

1

+

C525
150U_D2_6.3VM

2

A A

1

C498

0.1U_0402_10V6K

2

5

1

C665

0.1U_0402_10V6K

2

1

C499

0.1U_0402_10V6K

2

1

C666

0.1U_0402_10V6K

2

1

C504

0.1U_0402_10V6K

2

1

2

1

2

4

C667

0.1U_0402_10V6K

C500

0.1U_0402_10V6K

1

C668

0.1U_0402_10V6K

2

1

C503

0.1U_0402_10V6K

2

1

C669

0.1U_0402_10V6K

2

1

C463

0.1U_0402_10V6K

2

1

C670

0.1U_0402_10V6K

2

1

C441

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C671

0.1U_0402_10V6K

2

1

C424

0.1U_0402_10V6K

2

2005/03/01 2006/03/01

1

C672

0.1U_0402_10V6K

2

1

C450

0.1U_0402_10V6K

2

Compal Secret Data

Deciphered Date

1

C673

0.1U_0402_10V6K

2

1

C398

0.1U_0402_10V6K

2

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

752

5

D D

C C

Layout Guide will show
these signals routed
differentially.

B B

A A

H_A#[3..31]<5>

H_REQ#[0..4]<5>

H_DSTBN#[0..3]<5>

H_DSTBP#[0..3]<5>

H_RS#[0..2]<5>

H_CPUSLP#<5,20>

T1 PAD

CLK_MCH_BCLK#<18>
CLK_MCH_BCLK<18>

H_HITM#<5>
H_HIT#<5>
H_LOCK#<5>

H_CPUSLP# H_R_CPUSLP#

Note:
"Do not install R for Dothan-A,
Install R97 for Dothan-B"

H_ADSTB#0<5>
H_ADSTB#1<5>

H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>

H_RESET#<5>
H_ADS#<5>

H_TRDY#<5>
H_DPWR#<5>
H_DRDY#<5>
H_DEFER#<5>

H_BR0#<5>
H_BNR#<5>
H_BPRI#<5>
H_DBSY#<5>

5

T27 PAD

R418
0_0402_5%

1 2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#

@

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U5A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

Alviso

HOST

H_SWNG0

C362

0.1U_0402_16V4Z

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING

HYSWING

1

2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

12

R397

221_0603_1%

12

R388

100_0402_1%

4

4

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

H_SWNG1

C385

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1

2

0.1U_0402_16V4Z

+VCCP+VCCP

R67

R73

R77

24.9_0402_1%

12

221_0603_1%

12

100_0603_1%

12

R44

24.9_0402_1%

R41

12

H_D#[0..63] <5>

Layout Note:
Rote as short
as possible

12

R477

40.2_0402_1%

@

+VCCP

12

R66

54.9_0402_1%

54.9_0402_1%

10/20 mils

3

Layout Guide
will show these
signals routed
differentially.

DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>

DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>

DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>

DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>

DDR_CLK0<13>
DDR_CLK1<13>

DDR_CLK3<14>
DDR_CLK4<14>

DDR_CLK0#<13>
DDR_CLK1#<13>

DDR_CLK3#<14>
DDR_CLK4#<14>

DDR_CKE0<13>
DDR_CKE1<13>
DDR_CKE2<14>
DDR_CKE3<14>

DDR_SCS#0<13>
DDR_SCS#1<13>
DDR_SCS#2<14>
DDR_SCS#3<14>

R484 80.6_0402_1%

1 2

12

R489

80.6_0402_1%

+SDREF_DIMM

CFG[2:0]

CFG5

CFG6

12

12

R476

40.2_0402_1%

@

C379

0.1U_0402_16V7K

M_OCDOCMP0
M_OCDOCMP1

1

2

+VCCP

12

R372

100_0402_1%

12

R376

200_0402_1%

+2.5V

CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DDR_CLK0
DDR_CLK1

DDR_CLK3
DDR_CLK4

DDR_CLK0#
DDR_CLK1#

DDR_CLK3#
DDR_CLK4#

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

M_OCDOCMP0
M_OCDOCMP1

SMRCOMPN
SMRCOMPP

1

1

C419

C428

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Refer to sheet 6 for FSB
frequency select

Low = DMI x 2

High = DMI x 4

Low = DDR-II

High = DDR-I

Low = DT/Transportable CPU

High = Mobile CPU

Low = Reverse Lane

High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled

High = Enabled

Low = 1.05V (Default)

High = 1.5V

Low = 1.05V (Default)

High = 1.2V

Compal Secret Data

Deciphered Date

AA31
AB35
AC31
AD35

AA35
AB31
AC35

AA33
AB37
AC33
AD37

AA37
AB33
AC37

AM33

AL1

AE11

AJ34

AF6

AC10
AN33

AK1

AE10

AJ33

AF5

AD10
AP21

AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14

AL15
AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9
AF10

*

Y31

Y33

*

*

2

U5B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

*

*

*

*

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13

DMIDDR MUXING

CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

*

1

Alviso CFG[17:3] has internal pull-up

CFG0

G16

MCH_CLKSEL1

H13

MCH_CLKSEL0

G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG[17:3] have internal pull-up

3.5 k reserve for choose

Title

Size Document Number Rev

Custom

Date: Sheet

T25PAD
T26PAD

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

H_THERMTRIP#

PM_EXTTS#0
PM_EXTTS#1

PLTRST_R#

R384 10K_0402_5%

@

R387 10K_0402_5%

@

CFG0
CFG6
CFG5
CFG7
CFG9

CFG12
CFG13
CFG16

CFG18
CFG19

12
12

<Title>

LA-2362 1

Friday, March 11, 2005

MCH_CLKSEL1 <18>
MCH_CLKSEL0 <18>

@
@

R57
56_0402_5%

1 2

@

1 2

R492 100_0402_1%

12

12

PM_EXTTS#0

PM_EXTTS#1

R367 10K_0402_5%
R369 2.2K_0402_5%
R370 2.2K_0402_5%
R368 2.2K_0402_5%
R394 2.2K_0402_5%@

R374 2.2K_0402_5%@
R375 2.2K_0402_5%@
R430 2.2K_0402_5%@

R36 1K_0402_5%@
R37 1K_0402_5%@

R352.2K_0402_5%@

CFG[19:18] have internal pull-down

R382.2K_0402_5%@

+VCCP

PM_BMBUSY# <21>

H_THERMTRIP# <5,20>
VGATE <18,21,45>

DREFCLK# <18>

DREFCLK <18>
SSC_DREFCLK <18>
SSC_DREFCLK# <18>

10K_0402_5%

10K_0402_5%

12
1 2
1 2
1 2
1 2

1 2
1 2
1 2

3.5 k reserve for choose

1 2
1 2

1

PLTRST_MCH# <19>

R366

12

R365

12

852

+2.5VS

+VCCP

+2.5VS

of

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>

T38 PAD

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_MA[0..13]<13>

DDR_A_CAS#<13>
DDR_A_RAS#<13>

T36 PAD T33 PAD
T35 PAD

DDR_A_WE#<13>

B B

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4

AD3

AM8
AM4

AE5

AN8
AM5
AH1
AE4

AJ2

AJ1

U5C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

ALVISO_BGA1257

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG35

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_A_D[0..63] <13>

T34 PAD

DDR_B_BS#0<14>
DDR_B_BS#1<14>

T37 PAD

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>
DDR_B_RAS#<14>

DDR_B_WE#<14>

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

U5D

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

ALVISO_BGA1257

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

952

5

4

3

2

1

+2.5VS

R29 3K_0402_5%@

1 2

R30

1 2

12

R428

1 2

CLK_DDC2
DAT_DDC2

3K_0402_5%@

1@

R392

0_0402_5%

1@

R32

150_0402_1%

12

1@

CLK_DDC2<17>
DAT_DDC2<17>
CRT_BLU<17>

CLK_MCH_3GPLL#<18>
CLK_MCH_3GPLL<18>

12

R33

150_0402_1%

1@

R34

150_0402_1%

12

4.99K_0603_1%

D D

Y/G<17>
COMP/B<17>
C/R<17>

CRT_GRN<17>
CRT_RED<17>
VSYNC<17>

HSYNC<17>

BIA<16,32>

1 2

R429

255_0402_1%

BK_EN<16>

C C

B B

R396 100K_0402_1%

1 2
1 2

R404100K_0402_1%

LCD_CLK<16>
LCD_DAT<16>
EN_LCDVDD<16>

R3781.5K_0402_1%

LVDS_AC-<16>
LVDS_AC+<16>
LVDS_BC-<16>
LVDS_BC+<16>

LVDS_A0-<16>
LVDS_A1-<16>
LVDS_A2-<16>

LVDS_A0+<16>
LVDS_A1+<16>
LVDS_A2+<16>

LVDS_B0-<16>
LVDS_B1-<16>
LVDS_B2-<16>

LVDS_B0+<16>
LVDS_B1+<16>
LVDS_B2+<16>

BIA
BK_EN

LCTLA_CLK
LCTLB_DAT
LCD_CLK
LCD_DAT

12

EN_LCDVDD

LVDS_AC­LVDS_AC+
LVDS_BC­LVDS_BC+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

U5G

H24
H25

AB29
AC29

A15
C16
A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

ALVISO_BGA1257

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

EXP_COMPI

EXP_ICOMPO

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

PCI - EXPRESS GRAPHICS

EXP_TXP1/SDVOB_GREEN

EXP_TXP5/SDVOC_GREEN

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP1/SDVO_INT

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0/SDVOB_RED#

EXP_TXN3/SDVOB_CLKN

EXP_TXN4/SDVOC_RED#

EXP_TXN7/SDVOC_CLKN

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0/SDVOB_RED

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

24.9_0603_1%

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_TXN[0..15]

PEG_TXP[0..15]

R40

+1.5VS_PCIE

PEG_RXN[0..15] <16>

PEG_RXP[0..15] <16>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

PEG_TXN[0..15] <16>

PEG_TXP[0..15] <16>

+2.5VS

1 2
1 2
1 2
1 2
1 2
1 2

LCD_CLK

R362 2.2K_0402_5%

LCD_DAT

R363 2.2K_0402_5%

LCTLA_CLK

R385 2.2K_0402_5%

LCTLB_DAT

R364 2.2K_0402_5%

CLK_DDC2

R360 2.2K_0402_5%

DAT_DDC2

R361 2.2K_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

10 52

5

U5F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

C391

C392

2

2.2U_0805_10V6K

4.7U_0805_6.3V6K

1

C29

C C

0.47U_0603_16V7K

2

1

1

C74

C28

2

2

0.47U_0603_16V7K

B B

0.1U_0402_16V4Z

1

C674

C675

2

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C52

2

0.22U_0603_10V7K

0.22U_0603_10V7K

ALVISO_BGA1257

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C676

2

0.1U_0402_16V4Z

1

1

C678

C677

2

2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

0.1U_0402_16V4Z

1

2

V1.8_DDR_CAP1

AM37

V1.8_DDR_CAP2

AH37

V1.8_DDR_CAP5

AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13

Note: Place near chip.

AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9

V1.8_DDR_CAP6

AP8

V1.8_DDR_CAP4

AM1

V1.8_DDR_CAP3

AE1

C413

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

10U_1206_6.3V6M

C135

C127

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C412

2

2

C429

10U_1206_6.3V6M

C408

+2.5V

4

W=20 mils

U5E

+VCCP

0.1U_0402_16V7K

0.1U_0402_16V4Z

C468

+2.5V+VCCP

0.1U_0402_16V7K

C420

C393

0.1U_0402_16V4Z

1

2

1

2

10U_1206_6.3V6M

+1.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

C388

0.1U_0402_16V4Z

1

2

0.1U_0402_16V7K

1

2

1

C130

+

2

0.1U_0402_16V4Z

1

2

1

1

C478

C443

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
C475

C465

1

1

2

2

330U_D2E_2.5VM

0.1U_0402_16V4Z

1

1

C418

C411

2

2

T29

VCC0

R29

VCC1

N29

VCC2

M29

VCC3

K29

VCC4

J29

1

2

VCC5

V28

VCC6

U28

VCC7

T28

VCC8

R28

VCC9

P28

VCC10

N28

VCC11

M28

VCC12

L28

VCC13

K28

VCC14

J28

VCC15

H28

VCC16

G28

VCC17

V27

VCC18

U27

VCC19

T27

VCC20

R27

VCC21

P27

VCC22

N27

VCC23

M27

VCC24

L27

VCC25

K27

VCC26

J27

VCC27

H27

VCC28

K26

VCC29

H26

VCC30

K25

VCC31

J25

VCC32

K24

VCC33

K23

VCC34

K22

VCC35

K21

VCC36

W20

VCC37

U20

VCC38

T20

VCC39

K20

VCC40

V19

VCC41

U19

VCC42

K19

VCC43

W18

VCC44

V18

VCC45

T18

VCC46

K18

VCC47

K17

VCC48

AC1

VCCD_HMPLL1

AC2

VCCD_HMPLL2

B23

VCCA_DPLLA

C35

VCCA_DPLLB

AA1

VCCA_HPLL

AA2

VCCA_MPLL

ALVISO_BGA1257

VCC_SYNC

1

C30

2

10U_1206_6.3V6M

3

POWER

+2.5VS

12

12

1

C371

2

0.1U_0402_16V4Z

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG

VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

R28
0_0402_5%

R31

0_0402_5%@

1

C355

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

2

0.1U_0402_16V4Z

1@

R736 0_0603_5%

1 2

R739 0_0603_5%

1 2

1@

+2.5VS

R740 0_0603_5% 1@

1 2

4.7U_0805_6.3V6K

1

C473

C131

2

0.1U_0402_16V4Z

VCC_SYNC

C367

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C681

C680

2

2

+3VS

1

2

C366

0.022U_0402_16V7K

1

C372

2

0.1U_0402_16V4Z

+1.5VS_PM
+2.5VS_PM

C329

+1.5VS_PCIE

1

+

2

100U_D2_6.3VM

1

1

2

2

C363

0.022U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C682

2

2

+1.5VS

1

2

C353

1

2

C452

220U_D2_4VM

+2.5VS

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

1

C683

2

0.022U_0402_16V7K

+1.5VS

+2.5VS

1

+

2

0.1U_0402_16V4Z

C341

1

2

C684

1

1

2

2

0.1U_0402_16V4Z
C339 0.022U_0402_16V7K

R737 0_0603_5%2@

1 2

R738 0_0603_5%2@

1 2

+2.5VS_LVDSPM

C340

0.1U_0402_16V4Z

1

C433

C380

2

10U_1206_6.3V6M

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C685

2

2

1

1

2

2

C349

0.1U_0402_16V4Z

+2.5VS

1

2

10U_1206_6.3V6M

C399

0.1U_0402_16V4Z

Close B26,B25,A25

+1.5VS_PM

0.1U_0402_16V4Z

1

C354

2

C336 0.022U_0402_16V7K

R741
0_0603_5%

2@

1 2

R134

0.5_0805_1%

1 2

1

1

C126

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

3GRLL_R

1

C365

0.1U_0402_16V4Z

2

C346

CHB1608U301_0603

+2.5VS_PM

1

2

0.01U_0402_16V7K

0_0603_5%

L14

L26

L9

C352

L13

1

2

0.1U_0402_16V4Z

12

0_0603_5%

12

0_0603_5%

12

+1.5VS+1.5VS_3GPLL

12

C128

C334

10U_1206_6.3V6M

1

2

0.1U_0402_16V4Z

+2.5VS+2.5VS_3GBG

+2.5VS

1

C342

2

0.1U_0402_16V4Z

+1.5VS

C438

0.1U_0402_16V4Z

1

C31

0.1U_0402_16V4Z

2

1

1

2

+1.5VS+1.5VS_DDRDLL

1

C140

2

1

2

0.1U_0402_16V4Z

L19

CHB1608U301_0603

+1.5VS

A A

1 2

+VCCP +VCCP+2.5VS +3VS

R805

1 2

10K_0402_5%

@

1

C348

+

2

5

330U_D2E_2.5VM

0.1U_0402_16V4Z

C347

1

2

D21

1N4148_SOD80

@

12

+1.5VS

CHB1608U301_0603

1 2

L11

R806

1 2

10K_0402_5%

@

+1.5VS_HPLL

1

C81

+

2

330U_D2E_2.5VM

C404

1

2

D22

1N4148_SOD80

@

CHB1608U301_0603

0.1U_0402_16V4Z

+1.5VS

12

1 2

4

+1.5VS_MPLL

L23

1

1

+

C403

C409

2

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

+1.5VS

CHB1608U301_0603

1 2

+1.5VS_DPLLA+1.5VS_DPLLB

L20

330U_D2E_2.5VM

0.1U_0402_16V4Z

1

C330

C345

1

+

2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

2

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

1

of

11 52

5

4

3

2

1

+VCCP

W12

W13

AA12
AA13

W14

AA14
AB14

W15

AA15
AB15

W16

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25

W26

L12
M12
N12

P12

R12

T12

U12

V12

L13
M13
N13

P13
R13

T13
U13

V13

Y12

Y13

L14
M14
N14

P14
R14

T14
U14

V14

Y14

L15
M15
N15

P15
R15

T15
U15

V15

Y15

L16
M16
N16

P16
R16

T16
U16

V16

Y16

R17

Y17

R21

Y21

Y22

Y23

Y24

Y25

Y26

V25

L26
M26
N26

P26
R26

T26
U26

V26

5

U5H

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO_BGA1257

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

D D

C C

B B

A A

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+2.5V

C686

C692

1

2

+VCCP

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C687

C688

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C693

C694

2

C698

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C689

C690

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C695

C696

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C702

C699

2

2

4

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C691

2

2

U5I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSS

Security Classification

A3

C3
AA3
AB3

AC3

AJ3

C4

H4

L4
P4
U4

Y4

AF4

AN4

E5

W5
AL5
AP5

B6

J6
L6

P6

T6

AA6

AC6

AE6

AJ6

G7
V7

AA7

AG7

AK7

AN7

C8
E8

L8

P8

Y8

AL8

A9
H9
K9

T9

V9

AA9

AC9

AE9

AH9
AN9

D10

L10

Y10

AA10

F11
H11

+VCCP

0.1U_0402_10V6K

1

1

C697

2

2

+VCCP

0.1U_0402_10V6K

1

1

C703

2

2

Y11

0.1U_0402_10V6K

0.1U_0402_10V6K

ALVISO_BGA1257

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

B36

VSSALVDS

AA11

VSS195

AF11

VSS194

AG11

VSS193

AJ11

VSS192

AL11

VSS191

AN11

VSS190

B12

VSS189

D12

VSS188

J12

VSS187

A14

VSS186

B14

VSS185

F14

VSS184

J14

VSS183

K14

VSS182

AG14

VSS181

AJ14

VSS180

AL14

VSS179

AN14

VSS178

C15

VSS177

K15

VSS176

A16

VSS175

D16

VSS174

H16

VSS173

K16

VSS172

AL16

VSS171

C17

VSS170

G17

VSS169

AF17

VSS168

AJ17

VSS167

AN17

VSS166

A18

VSS165

B18

VSS164

U18

VSS163

AL18

VSS162

C19

VSS161

H19

VSS160

J19

VSS159

T19

VSS158

W19

VSS157

AG19

VSS156

AN19

VSS155

A20

VSS154

D20

VSS153

E20

VSS152

F20

VSS151

G20

VSS150

V20

VSS149

AK20

VSS148

C21

VSS147

F21

VSS146

AF21

VSS145

AN21

VSS144

A22

VSS143

D22

VSS142

E22

VSS141

J22

VSS140

AH22

VSS139

AL22

VSS138

H23

VSS137

AF23

VSS136

B24

VSS135

D24

VSS134

F24

VSS133

J24

VSS132

AG24

VSS131

AJ24

VSS130

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

U5J

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125

AF27

VSS124

AG27

VSS123

AJ27

VSS122

AL27

VSS121

AN27

VSS120

E28

VSS119

W28

VSS118

AA28

VSS117

AB28

VSS116

AC28

VSS115

A29

VSS114

D29

VSS113

E29

VSS112

F29

VSS111

G29

VSS110

H29

VSS109

L29

VSS108

P29

VSS107

U29

VSS106

V29

VSS105

W29

VSS104

AA29

VSS103

AD29

VSS102

AG29

VSS101

AJ29

VSS100

AM29

VSS99

C30

VSS98

Y30

VSS97

AA30

VSS96

AB30

VSS95

AC30

VSS94

AE30

VSS93

AP30

VSS92

D31

VSS91

E31

VSS90

F31

VSS89

G31

VSS88

H31

VSS87

J31

VSS86

K31

VSS85

L31

VSS84

M31

VSS83

N31

VSS82

P31

VSS81

R31

VSS80

T31

VSS79

U31

VSS78

V31

VSS77

W31

VSS76

AD31

VSS75

AG31

VSS74

AL31

VSS73

A32

VSS72

C32

VSS71

Y32

VSS70

AA32

VSS69

AB32

VSS68

ALVISO_BGA1257

2

VSS

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

of

1

12 52

A

B

C

D

E

F

G

H

DDR_A_MA[0..13]<9>

DDR_A_MA13
DDR_A_MA12
DDR_A_MA11

DDR_A_MA9
DDR_A_MA7
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3

DDR_A_MA10

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
DDR_A_MA5

DDR_A_WE#

DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#

DDR_A_BS#1

DDR_CKE0

DDR_CKE1

DDR_SCS#1

DDR_SCS#0

C

DDR_A_D4
DDR_A_D1
DDR_A_D5
DDR_A_D2
DDR_A_DM0
DDR_A_D3
DDR_A_DQS0
DDR_A_D0
DDR_A_D7
DDR_A_D6

DDR_A_D13
DDR_A_D11
DDR_A_D10
DDR_A_D8
DDR_A_D9
DDR_A_DM1
DDR_A_D12
DDR_A_DQS1
DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21
DDR_A_D16
DDR_A_D17
DDR_A_DQS2
DDR_A_D18
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D19

DDR_A_D28
DDR_A_D24

DDR_A_D29

DDR_A_DQS3

DDR_A_D25

DDR_A_DM3

DDR_A_D31
DDR_A_D26
DDR_A_D30
DDR_A_D27

DDR_A_D36
DDR_A_D37
DDR_A_D33
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D38

DDR_A_D39
DDR_A_DQS4
DDR_A_DM4

DDR_A_D44

DDR_A_D41

DDR_A_D40

DDR_A_D45
DDR_A_DQS5

DDR_A_D43

DDR_A_D42

DDR_A_D46

DDR_A_D47
DDR_A_DM5

DDR_A_D53

DDR_A_D48

DDR_A_D52

DDR_A_D49

DDR_A_D55

DDR_A_D54

DDR_A_D50

DDR_A_D51
DDR_A_DM6
DDR_A_DQS6

DDR_A_D58
DDR_A_D63
DDR_A_D61
DDR_A_D57
DDR_A_D56
DDR_A_DM7

DDR_A_D59

DDR_A_D62

DDR_A_D60
DDR_A_DQS7

A

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]

1 2

R647 10_0402_5%

1 2

R257 10_0402_5%

1 2

R256 10_0402_5%

1 2

R650 10_0402_5%

1 2

R255 10_0402_5%

1 2

R253 10_0402_5%

1 2

R648 10_0402_5%

1 2

R646 10_0402_5%

1 2

R254 10_0402_5%

1 2

R649 10_0402_5%

1 2

R252 10_0402_5%

1 2

R248 10_0402_5%

1 2

R655 10_0402_5%

1 2

R651 10_0402_5%

1 2

R251 10_0402_5%

1 2

R250 10_0402_5%

1 2

R652 10_0402_5%

1 2

R653 10_0402_5%

1 2

R654 10_0402_5%

1 2

R249 10_0402_5%

1 2

R657 10_0402_5%

1 2

R246 10_0402_5%

1 2

R656 10_0402_5%

1 2

R247 10_0402_5%

1 2

R658 10_0402_5%

1 2

R659 10_0402_5%

1 2

R245 10_0402_5%

1 2

R660 10_0402_5%

1 2

R243 10_0402_5%

1 2

R244 10_0402_5%

1 2

R662 10_0402_5%

1 2

R661 10_0402_5%

1 2

R241 10_0402_5%

1 2

R663 10_0402_5%

1 2

R242 10_0402_5%

1 2

R240 10_0402_5%

1 2

R238 10_0402_5%

1 2

R664 10_0402_5%

1 2

R665 10_0402_5%

1 2

R239 10_0402_5%

1 2

R666 10_0402_5%

1 2

R237 10_0402_5%

1 2

R667 10_0402_5%

1 2

R236 10_0402_5%

1 2

R233 10_0402_5%

1 2

R669 10_0402_5%

1 2

R234 10_0402_5%

1 2

R670 10_0402_5%

1 2

R668 10_0402_5%

1 2

R235 10_0402_5%

1 2

R274 10_0402_5%

1 2

R679 10_0402_5%

1 2

R273 10_0402_5%

1 2

R680 10_0402_5%

1 2

R681 10_0402_5%

1 2

R271 10_0402_5%

1 2

R683 10_0402_5%

1 2

R682 10_0402_5%

1 2

R270 10_0402_5%

1 2

R272 10_0402_5%

1 2

R685 10_0402_5%

1 2

R268 10_0402_5%

1 2

R684 10_0402_5%

1 2

R269 10_0402_5%

1 2

R266 10_0402_5%

1 2

R687 10_0402_5%

1 2

R688 10_0402_5%

1 2

R265 10_0402_5%

1 2

R267 10_0402_5%

1 2

R686 10_0402_5%

1 2

R690 10_0402_5%

1 2

R261 10_0402_5%

1 2

R264 10_0402_5%

1 2

R692 10_0402_5%

1 2

R263 10_0402_5%

1 2

R262 10_0402_5%

1 2

R693 10_0402_5%

1 2

R260 10_0402_5%

1 2

R689 10_0402_5%

1 2

R691 10_0402_5%

B

DDR_D[0..63]

DDR_DM[0..7]

DDR_DQS[0..7]

DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_DM0
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6

DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15

DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19

DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27

DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4

DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5

DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6

DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7

DDR_D[0..63] <14>
DDR_DM[0..7] <14>
DDR_DQS[0..7] <14>

+1.25VS

1 2

R673 56_0402_5%

1 2

R296 56_0402_5%

1 2

R282 56_0402_5%

1 2

R674 56_0402_5%

1 2

R675 56_0402_5%

1 2

R281 56_0402_5%

1 2

R280 56_0402_5%

1 2

R676 56_0402_5%

1 2

R677 56_0402_5%

1 2

R278 56_0402_5%

1 2

R294 56_0402_5%

1 2

R288 56_0402_5%

1 2

R279 56_0402_5%

1 2

R295 56_0402_5%

1 2

R293 56_0402_5%

1 2

R286 56_0402_5%

1 2

R276 56_0402_5%

1 2

R287 56_0402_5%

1 2

R277 56_0402_5%

1 2

R283 56_0402_5%

1 2

R672 56_0402_5%

1 2

R275 56_0402_5%

1 2

R678 56_0402_5%

DDR_A_D[0..63]<9>
DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>

1 1

2 2

3 3

4 4

DDR_A_MA[0..13]

+2.5V

JDIMM2

1

VREF

3

DDR_D0
DDR_D4

DDR_DQS0
DDR_D6

DDR_D2
DDR_D8

DDR_D12
DDR_DQS1

DDR_D14
DDR_D10

DDR_CLK0<8>
DDR_CLK0#<8>

DDR_D16
DDR_D20

DDR_DQS2
DDR_D18

DDR_D22
DDR_D24

DDR_D28
DDR_DQS3

DDR_D26
DDR_D30

DDR_CKE1<8>

DDR_A_BS#0<9>
DDR_A_WE#<9>

DDR_SCS#0<8>

CK_SDATA<14,18>
CK_SCLK<14,18>

DDR_CKE1 DDR_CKE0
DDR_A_MA13
DDR_A_MA12
DDR_A_MA9

DDR_A_MA7
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_SCS#0 DDR_SCS#1

DDR_D36
DDR_D33

DDR_DQS4
DDR_D35

DDR_D39
DDR_D41

DDR_D45
DDR_DQS5

DDR_D46
DDR_D42

DDR_D52
DDR_D53

DDR_DQS6
DDR_D54

DDR_D50
DDR_D60

DDR_D56
DDR_DQS7

DDR_D57
DDR_D59

CK_SDATA
CK_SCLK

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU/A13

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

TYCO_1612560-1

2005/03/01 2006/03/01

E

Compal Secret Data

Deciphered Date

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

VSS

VDD
BA1

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD
CK1

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD
SA0
SA1
SA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

DU

100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

F

+2.5V

DDR_D1
DDR_D5

DDR_DM0
DDR_D7

DDR_D3
DDR_D13

DDR_D9
DDR_DM1

DDR_D15
DDR_D11

DDR_D17
DDR_D21

DDR_DM2
DDR_D19

DDR_D23
DDR_D25

DDR_D29
DDR_DM3

DDR_D27
DDR_D31

DDR_A_MA11
DDR_A_MA8

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_A_CAS#

DDR_D37
DDR_D32

DDR_DM4
DDR_D38

DDR_D34
DDR_D44

DDR_D40
DDR_DM5

DDR_D43
DDR_D47

DDR_D49
DDR_D48

DDR_DM6
DDR_D55

DDR_D51
DDR_D61

DDR_D58
DDR_DM7

DDR_D63
DDR_D62

+SDREF_DIMM

R227

12

0_0402_5%

+SDREF

1

C237

0.1U_0402_16V4Z

2

DDR_CKE0 <8>

DDR_A_BS#1 <9>
DDR_A_RAS# <9>
DDR_A_CAS# <9>

DDR_SCS#1 <8>

DDR_CLK1# <8>
DDR_CLK1 <8>

Title

<Title>

Size Document Number Rev

LA-2362 1

B

Friday, March 11, 2005

Date: Sheet

G

13 52

H

of

A

DDR_D[0..63]

DDR_DM[0..7]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

DDR_DQS[0..7]

+1.25VS

DDR_D4
DDR_D1
DDR_D5
DDR_D2

DDR_DM0

1 1

DDR_D3

DDR_DQS0

DDR_D0
DDR_D7
DDR_D6

DDR_D13
DDR_D11
DDR_D10

DDR_D8
DDR_D9

DDR_DM1

DDR_D12

DDR_DQS1

DDR_D14
DDR_D15

DDR_D20
DDR_D21
DDR_D16
DDR_D17

DDR_DQS2

DDR_D18

DDR_DM2

DDR_D22
DDR_D23
DDR_D19

DDR_D28
DDR_D24
DDR_D29

DDR_DQS3

2 2

DDR_D25

DDR_DM3

DDR_D31
DDR_D26
DDR_D30
DDR_D27

DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38

DDR_D39
DDR_DQS4
DDR_DM4

1 2

R597 56_0402_5%

1 2

R596 56_0402_5%

1 2

R215 56_0402_5%

1 2

R600 56_0402_5%

1 2

R598 56_0402_5%

1 2

R599 56_0402_5%

1 2

R214 56_0402_5%

1 2

R216 56_0402_5%

1 2

R212 56_0402_5%

1 2

R213 56_0402_5%

1 2

R211 56_0402_5%

1 2

R210 56_0402_5%

1 2

R602 56_0402_5%

1 2

R601 56_0402_5%

1 2

R209 56_0402_5%

1 2

R603 56_0402_5%

1 2

R208 56_0402_5%

1 2

R605 56_0402_5%

1 2

R207 56_0402_5%

1 2

R604 56_0402_5%

1 2

R607 56_0402_5%

1 2

R205 56_0402_5%

1 2

R606 56_0402_5%

1 2

R206 56_0402_5%

1 2

R204 56_0402_5%

1 2

R203 56_0402_5%

1 2

R608 56_0402_5%

1 2

R202 56_0402_5%

1 2

R610 56_0402_5%

1 2

R609 56_0402_5%

1 2

R200 56_0402_5%

1 2

R201 56_0402_5%

1 2

R612 56_0402_5%

1 2

R199 56_0402_5%

1 2

R611 56_0402_5%

1 2

R613 56_0402_5%

1 2

R197 56_0402_5%

1 2

R198 56_0402_5%

1 2

R614 56_0402_5%

1 2

R615 56_0402_5%

1 2

R195 56_0402_5%

1 2

R584 56_0402_5%

1 2

R196 56_0402_5%

1 2

R583 56_0402_5%

1 2

R194 56_0402_5%

1 2

R193 56_0402_5%

1 2

R587 56_0402_5%

1 2

R586 56_0402_5%

1 2

R192 56_0402_5%

1 2

R585 56_0402_5%

R183 56_0402_5%
R574 56_0402_5%
R182 56_0402_5%
R573 56_0402_5%
R181 56_0402_5%
R179 56_0402_5%
R577 56_0402_5%
R180 56_0402_5%
R576 56_0402_5%
R575 56_0402_5%

R579 56_0402_5%
R178 56_0402_5%
R176 56_0402_5%
R582 56_0402_5%
R174 56_0402_5%
R578 56_0402_5%
R177 56_0402_5%
R175 56_0402_5%
R581 56_0402_5%
R580 56_0402_5%

R169 56_0402_5%
R591 56_0402_5%
R173 56_0402_5%
R595 56_0402_5%
R172 56_0402_5%
R170 56_0402_5%
R171 56_0402_5%
R594 56_0402_5%
R592 56_0402_5%
R593 56_0402_5%

+1.25VS

1 2

R189 56_0402_5%

1 2

R565 56_0402_5%

1 2

R188 56_0402_5%

1 2

R168 56_0402_5%

1 2

R566 56_0402_5%

1 2

R567 56_0402_5%

3 3

1 2

R167 56_0402_5%

1 2

R185 56_0402_5%

1 2

R569 56_0402_5%

1 2

R186 56_0402_5%

1 2

R568 56_0402_5%

1 2

R562 56_0402_5%

1 2

R187 56_0402_5%

1 2

R190 56_0402_5%

1 2

R184 56_0402_5%

1 2

R166 56_0402_5%

1 2

R571 56_0402_5%

1 2

R572 56_0402_5%

1 2

R570 56_0402_5%

1 2

R191 56_0402_5%

1 2

R564 56_0402_5%

1 2

R165 56_0402_5%

1 2

R563 56_0402_5%

DDR_B_MA12
DDR_B_MA11
DDR_B_MA9
DDR_B_MA7
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA10
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA4
DDR_B_MA5
DDR_B_MA13

DDR_B_WE#
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_BS#1

DDR_CKE3
DDR_CKE2
DDR_SCS#2
DDR_SCS#3

DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5

DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6

DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7

B

DDR_D[0..63] <13>
DDR_DM[0..7] <13>
DDR_DQS[0..7] <13>

C

DDR_B_MA[0..13]<9>

DDR_B_MA[0..13]

DDR_CLK3<8>
DDR_CLK3#<8>

DDR_CKE3<8>

DDR_B_BS#0<9>
DDR_B_WE#<9>
DDR_SCS#2<8>

CK_SDATA<13,18>
CK_SCLK<13,18>

DDR_B_MA13
DDR_B_MA12
DDR_B_MA9

DDR_B_MA7
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_SCS#2

DDR_D0
DDR_D4

DDR_DQS0
DDR_D6

DDR_D2
DDR_D8

DDR_D12
DDR_DQS1

DDR_D14
DDR_D10

DDR_D16
DDR_D20

DDR_DQS2
DDR_D18

DDR_D22
DDR_D24

DDR_D28
DDR_DQS3

DDR_D26
DDR_D30

DDR_CKE3

DDR_D36
DDR_D33

DDR_DQS4
DDR_D35

DDR_D39
DDR_D41

DDR_D45
DDR_DQS5

DDR_D46
DDR_D42

DDR_D52
DDR_D53

DDR_DQS6
DDR_D54

DDR_D50
DDR_D60

DDR_D58
DDR_DQS7

DDR_D57
DDR_D59

CK_SDATA

CK_SCLK

+3VS

+2.5V

JDIMM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

D

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DDR_CKE2

DDR_B_BS#1
DDR_B_RAS#DDR_B_BS#0
DDR_B_CAS#DDR_B_WE#
DDR_SCS#3

DDR_D1
DDR_D5

DDR_DM0
DDR_D7

DDR_D3
DDR_D13

DDR_D9
DDR_DM1

DDR_D15
DDR_D11

DDR_D17
DDR_D21

DDR_DM2
DDR_D19

DDR_D23
DDR_D25

DDR_D29
DDR_DM3

DDR_D27
DDR_D31

DDR_B_MA11
DDR_B_MA8

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_D37
DDR_D32

DDR_DM4
DDR_D38

DDR_D34
DDR_D44

DDR_D40
DDR_DM5

DDR_D43
DDR_D47

DDR_D49
DDR_D48

DDR_DM6
DDR_D55

DDR_D51
DDR_D61

DDR_D56
DDR_DM7

DDR_D63
DDR_D62

+3VS

+SDREF_DIMM

1

2

DDR_CKE2 <8>

DDR_SCS#3 <8>

DDR_CLK4# <8>
DDR_CLK4 <8>

C188

0.1U_0402_16V4Z

DDR_B_BS#1 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>

E

KLINK_5763-2-111

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

B

Friday, March 11, 2005

D

Date: Sheet

E

of

14 52

A

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

B

C

D

E

1 1

1

C190

0.1U_0402_16V4Z

2

+2.5V +2.5V

1

C227

0.1U_0402_16V4Z

2

1

C191

0.1U_0402_16V4Z

2

1

C267

0.1U_0402_16V4Z

2

1

C189

0.1U_0402_16V4Z

2

1

C266

0.1U_0402_16V4Z

2

1

C193

0.1U_0402_16V4Z

2

1

C263

0.1U_0402_16V4Z

2

1

C218

0.1U_0402_16V4Z

2

1

C262

0.1U_0402_16V4Z

2

1

C217

0.1U_0402_16V4Z

2

1

C214

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

1

+

C163
150U_D2_6.3VM

2

1

C215

0.1U_0402_16V4Z

2

1

+

C238
150U_D2_6.3VM

2

1

C230

0.1U_0402_16V4Z

2

1

C229

0.1U_0402_16V4Z

2

1

C228

0.1U_0402_16V4Z

2

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

3 3

+1.25VS

1

C253

0.1U_0402_16V4Z

2

+1.25VS

1

C243

0.1U_0402_16V4Z

2

+1.25VS

1

C250

0.1U_0402_16V4Z

2

1

C252

0.1U_0402_16V4Z

2

1

C242

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C578

0.1U_0402_16V4Z

2

1

C248

0.1U_0402_16V4Z

2

1

C590

0.1U_0402_16V4Z

2

1

C579

0.1U_0402_16V4Z

2

1

C576

0.1U_0402_16V4Z

2

1

C589

0.1U_0402_16V4Z

2

1

C580

0.1U_0402_16V4Z

2

1

C585

0.1U_0402_16V4Z

2

1

C588

0.1U_0402_16V4Z

2

1

C256

0.1U_0402_16V4Z

2

1

C583

0.1U_0402_16V4Z

2

1

C247

0.1U_0402_16V4Z

2

1

C255

0.1U_0402_16V4Z

2

1

C584

0.1U_0402_16V4Z

2

1

C246

0.1U_0402_16V4Z

2

1

C254

0.1U_0402_16V4Z

2

1

C575

0.1U_0402_16V4Z

2

1

C245

0.1U_0402_16V4Z

2

1

C582

0.1U_0402_16V4Z

2

1

C586

0.1U_0402_16V4Z

2

1

C244

0.1U_0402_16V4Z

2

1

C581

0.1U_0402_16V4Z

2

1

C587

0.1U_0402_16V4Z

2

+1.25VS

1

C544

0.1U_0402_16V4Z

2

1

C653

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C536

0.1U_0402_16V4Z

2

1

C654

0.1U_0402_16V4Z

2

C

1

C208

0.1U_0402_16V4Z

2

1

C655

0.1U_0402_16V4Z

2

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

D

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

E

of

15 52

B

1

C529

0.1U_0402_16V4Z

2

1

C651

0.1U_0402_16V4Z

2

1

C535

0.1U_0402_16V4Z

2

1

C652

0.1U_0402_16V4Z

2

1

C200

0.1U_0402_16V4Z

2

+1.25VS

1

C646

0.1U_0402_16V4Z

2

4 4

1

C201

0.1U_0402_16V4Z

2

1

C647

0.1U_0402_16V4Z

2

A

1

C202

0.1U_0402_16V4Z

2

1

C648

0.1U_0402_16V4Z

2

1

C531

0.1U_0402_16V4Z

2

1

C649

0.1U_0402_16V4Z

2

1

C530

0.1U_0402_16V4Z

2

1

C650

0.1U_0402_16V4Z

2

5

PEG_TXN15 PEG_A_TXN_15
PEG_TXP15

PEG_TXN14
PEG_TXP14

D D

C C

B B

PEG_TXN13
PEG_TXP13

PEG_TXN12
PEG_TXP12

PEG_TXN11
PEG_TXP11

PEG_TXN10
PEG_TXP10

PEG_TXN9
PEG_TXP9 PEG_A_TXP_9

PEG_TXN7
PEG_TXP7

PEG_TXN6
PEG_TXP6

PEG_TXN5
PEG_TXP5

PEG_TXP4

PEG_TXP3
PEG_TXN2

PEG_TXP2
PEG_TXN1

PEG_TXP1

PEG_TXN0
PEG_TXP0

B+I

FBM-L11-160808-800LMT_0603

FBM-L11-160808-800LMT_0603

+3VS

+2.5V

2@

1

C704

2

Modify for 1.8vs move to VGA BD

A A

R328

2@

1 2
1 2

R329

2@

0.1U_0402_16V4Z

2@

1

C705

2

+3VS

C97 0.1U_0402_16V4Z2@

1 2

C94 0.1U_0402_16V4Z2@

C93 0.1U_0402_16V4Z2@

1 2

C88 0.1U_0402_16V4Z2@

C87 0.1U_0402_16V4Z2@

1 2

C83 0.1U_0402_16V4Z2@

C82 0.1U_0402_16V4Z2@

1 2

C80 0.1U_0402_16V4Z2@

C79 0.1U_0402_16V4Z2@

1 2

C77 0.1U_0402_16V4Z2@

C76 0.1U_0402_16V4Z2@

1 2

C73 0.1U_0402_16V4Z2@

C72 0.1U_0402_16V4Z2@

1 2

C71 0.1U_0402_16V4Z2@

C70 0.1U_0402_16V4Z2@

1 2

C67 0.1U_0402_16V4Z2@

C66 0.1U_0402_16V4Z2@

1 2

C65 0.1U_0402_16V4Z2@

C64 0.1U_0402_16V4Z2@

1 2

C61 0.1U_0402_16V4Z2@

C59 0.1U_0402_16V4Z2@

1 2

C57 0.1U_0402_16V4Z2@

C56 0.1U_0402_16V4Z2@

1 2

C55 0.1U_0402_16V4Z2@

C54 0.1U_0402_16V4Z2@

1 2

C51 0.1U_0402_16V4Z2@

C50 0.1U_0402_16V4Z2@

1 2

C49 0.1U_0402_16V4Z2@

C48 0.1U_0402_16V4Z2@

1 2

C44 0.1U_0402_16V4Z2@

C43 0.1U_0402_16V4Z2@

1 2

C39 0.1U_0402_16V4Z2@

B+P

0.1U_0402_16V4Z

10

B+P B+I

2

2

C307

1

C309

C313

1

2@

2@

0.1U_0603_50V4Z

0.1U_0603_50V4Z

1

1

C310

2

2

0.047U_0402_16V4Z

0.047U_0402_16V4Z

5

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

SMB_EC_CK2<32,34>
SMB_EC_DA2<32,34>

JVGAP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10

ACES_85205-10002@

2

C308

1

2@

0.1U_0603_50V4Z

1

C311

2

0.047U_0402_16V4Z

SUSP#<24,32,33,37,42>
C/R_VGA<17>
COMP/B_VGA<17>
Y/G_VGA<17>

VSYNC_VGA<17>
HSYNC_VGA<17>

VGA_BLU<17>
VGA_GRN<17>
VGA_RED<17>

SMBCLK_VGA<17>
SMBDAT_VGA<17>

2

C314

1

2@

0.1U_0603_50V4Z

BK_EN<10>
BKOFF#<32>

BIA<10,32>

PEG_A_TXP_15
PEG_A_TXN_14

PEG_A_TXP_14
PEG_A_TXN_13

PEG_A_TXP_13

PEG_A_TXN_12
PEG_A_TXP_12

PEG_A_TXN_11
PEG_A_TXP_11

PEG_A_TXN_10
PEG_A_TXP_10

PEG_A_TXN_9

PEG_A_TXN_8PEG_TXN8
PEG_A_TXP_8PEG_TXP8

PEG_A_TXN_7
PEG_A_TXP_7

PEG_A_TXN_6
PEG_A_TXP_6

PEG_A_TXN_5
PEG_A_TXP_5

PEG_A_TXN_4PEG_TXN4
PEG_A_TXP_4

PEG_A_TXN_3PEG_TXN3
PEG_A_TXP_3

PEG_A_TXN_2
PEG_A_TXP_2

PEG_A_TXN_1
PEG_A_TXP_1

PEG_A_TXN_0
PEG_A_TXP_0

SMB_EC_CK2
SMB_EC_DA2

VSYNC_VGA
HSYNCVGA

VGA_BLU
VGA_GRN
VGA_RED

SMBCLK_VGA
SMBDAT_VGA

4

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140

U1

1

A

2

B

1@

2

@

4

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140

FOX_QTS0140A-30212@

+5VS

5

P

O

G

3

NC7ST08P5X_SC70-5

+3VS

5

U2

P

A

Y

G

NC7SZ14M5X_SOT23-5

3

R7

@

1 2

0_0402_5%

JVGA1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139

DISPLAYOFF#

4

INVT_PWM<32>

4

3

1

1

3

3

5

5

7

7

9

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12
PEG_RXP12

PEG_RXN11
PEG_RXP11

PEG_RXN10
PEG_RXP10

PEG_RXN9
PEG_RXP9

PEG_RXN8
PEG_RXP8

PEG_RXN7
PEG_RXP7

PEG_RXN6
PEG_RXP6

PEG_RXN5
PEG_RXP5

PEG_RXN4
PEG_RXP4

PEG_RXN3
PEG_RXP3

PEG_RXN2
PEG_RXP2

PEG_RXN1
PEG_RXP1

PEG_RXN0
PEG_RXP0

RUNPWROK

PLTRST_VGA#
THERMATRIP_VGA#
SUSP

CLK_PCIE_VGA#
CLK_PCIE_VGA

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

1@

1 2

R3

1 2

0_0402_5%

R4

0_0402_5%

LCD_CLK<10>

LCD EEPROM

LCD_DAT<10>

RUNPWROK
PLTRST_VGA# <19,21>
THERMATRIP_VGA# <32>
SUSP <37,43,44>

CLK_PCIE_VGA# <18>
CLK_PCIE_VGA <18>

DAC_BRIG <32>
BKOFF# <32>

INVT_PWM <32>
+5VS
+5VALW

+12VALW

PEG_TXP[0..15]

PWM

2.2K_0402_5%

Q20

BSS138_SOT23

+2.5VS

Q21

BSS138_SOT23

B+ B+I

FBM-L11-201209-121LMA05T_0805

C716

0.1U_0603_50V4Z

PEG_TXP[0..15] <10>

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

3

LVDS_A0+<10>
LVDS_A0-<10>
LVDS_A1+<10>
LVDS_A1-<10>
LVDS_A2-<10>
LVDS_A2+<10>

LVDS_AC-<10>
LVDS_AC+<10>

LVDS_B0-<10>
LVDS_B0+<10>
LVDS_B2-<10>
LVDS_B2+<10>
LVDS_B1-<10>
LVDS_B1+<10>

LVDS_BC-<10>
LVDS_BC+<10>

+3VS

12

1@

R336

D

S

13

G

2

1@

G

2

13

D

S

1@

EN_LCDVDD<10>

FBM-201209-121LMA40T

L33

1 2

10U_1206_25V6M

PEG_RXN[0..15]

C717

Compal Secret Data

Deciphered Date

LVDS_A0+
LVDS_A0­LVDS_A1+
LVDS_A1­LVDS_A2­LVDS_A2+

LVDS_AC­LVDS_AC+

LVDS_B0­LVDS_B0+
LVDS_B2­LVDS_B2+
LVDS_B1­LVDS_B1+

LVDS_BC­LVDS_BC+

12

1@

R335

2.2K_0402_5%

LCDP_CLK

1@

LCDP_DAT

Q22

2N7002_SOT23

1@

1

2

C27

0.1U_0603_50V4Z

PEG_RXN[0..15] <10> PEG_TXN[0..15]<10>

+LCDVDD

R344
470_0402_5%

13

D

S

R27
100K_0402_5%

1@

R357

2

1@

2

G

2

1@

75K_0402_5%

1@

2

ACES_88328-4000

42

GND
40

38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

1@

R356
100K_0402_5%

1@

1@

2

Q24
DTC124EK_SC59

4

Q25

D

1 3

1@

2

G

0.1U_0603_50V4Z

S

G

+5VS

13

Q1
FDS4435_SO8

1
2
3 6

1@

2N7002_SOT23

1

41

GND

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

JLVDS1

0.1U_0402_16V4Z

+12VALW +LCDVDD +3VS

R355
100K_0402_5%

13

D

Q23
2N7002_SOT23

S

INVPWR_B+

8
7

5

C23

1@

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS

LCDP_CLK
LCDP_DAT

R722

1 2

C318

D

13

1@

R354
150K_0402_5%

1

DAC_BRIG <32>

INVPWR_B+

1@

C323

0.1U_0402_16V4Z

PEG_RXP[0..15] <10>

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

of

16 52

PWM
DISPLAYOFF#

INVPWR_B+++

KC FBM-L11-201209-221LMAT_0805

1

1

1@

1@

2

1@

0.1U_0402_16V4Z

2

SI2302DS_SOT23

S

1@

C321

0.1U_0402_16V4Z

1@

PEG_RXP[0..15]

Q26

G

2

PEG_TXN[0..15]

C320

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

<Title>

LA-2362 1

Friday, March 11, 2005

+LCDVDD

Inverter

5

4

3

2

1

1@

R25 0_0402_5%

C/R<10>

C/R_VGA<16>

D D

COMP/B<10>

COMP/B_VGA<16>

Y/G<10>

Y/G_VGA<16>

C C

B B

HSYNC_VGA<16>

HSYNC<10>

VSYNC_VGA<16>

VSYNC<10>

A A

R340 0_0402_5%

R341 0_0402_5%

1 2

R26 0_0402_5%

1 2

2@

1@

R23 0_0402_5%

1 2

R24 0_0402_5%

1 2

2@

1@

R21 0_0402_5%

1 2

R22 0_0402_5%

1 2

2@

VGA_RED<16>

VGA_GRN<16>

VGA_BLU<16>

CRT_RED<10>

CRT_GRN<10>

CRT_BLU<10>

2@

R342 0_0402_5%

1 2

R343 0_0402_5%

1 2

R16 0_0402_5%

R14 0_0402_5%

R12 0_0402_5%

R11 0_0402_5%

R13 0_0402_5%

R15 0_0402_5%

1@

2@

1 2

1 2

1@

2@

1 2

2@

1 2

2@

1 2

1 2

1@

1 2

1@

1 2

1@

CRT_HSYNC

CRT_VSYNC

C/R_C

150_0402_1%

COMP/B_C

150_0402_1%

Y/G_C

150_0402_1%

+5VS

12

R19

12

R18

12

R17

CRT_R

CRT_G

CRT_B

5

1

P

4

OE#

A2Y

G

U25

3

SN74AHCT1G125GW_SOT353-5

5

1

P

4

OE#

A2Y

G

U24

3

SN74AHCT1G125GW_SOT353-5

1

2

1

2

1

2

1K_0402_5%

1 2

1 2

L8
FLM1608081R8K_0603

C22
82P_0402_50V8J

1 2

L7
FLM1608081R8K_0603

C21
82P_0402_50V8J

1 2

L6
FLM1608081R8K_0603

C20
82P_0402_50V8J

DDC_MONID0

MSEN#<32>

3.3P_0603_50V8J

R339

75_0603_1%

C14

@

R10

MSEN#

3.3P_0603_50V8J

1

2

12

+5VS

1

2

2

C17
82P_0603_50V8J

1

2

C16
82P_0603_50V8J

1

2

C15
82P_0603_50V8J

1

@

1

1

C13

2

2

75_0603_1%

12

12

R9

C305

0.1U_0402_16V4Z

C12

@

3.3P_0603_50V8J

L3

1 2

FBM-11-160808-121-T_0603

L4

1 2

FBM-11-160808-121-T_0603

L5

1 2

FBM-11-160808-121-T_0603

R8
75_0603_1%

FBM-11-160808-121-T_0603

FBM-11-160808-121-T_0603

SVIDEO_C

SVIDEO_CVBS

SVIDEO_Y

1

D9

DAN217_SC59

2

@

CRTR

CRTG

CRTB

1

C8

3.3P_0603_50V8J

2

1 2

L1

1 2

L2

3

D12

DAN217_SC59@

1

2

3

D8

DAN217_SC59

@

1

2

1

C5

27P_0402_50V8J

2

D11

2

DAN217_SC59@

0.1U_0402_16V4Z

1

2

3

C9

3.3P_0603_50V8J

1

3

C304

1

D7

DAN217_SC59

2

@

1

C6

27P_0402_50V8J

2

100P_0402_50V8J

D10

+5VS

1

2

3

1

2

1

2

3

+3VS

DAN217_SC59@

2K_0402_5%

C306

0.1U_0402_16V4Z

+2.5VS

C10

3.3P_0603_50V8J

1

C3

2

100P_0402_50V8J

+5VS

R321

1

2

RB751V_SOD323

1

C303

2

100P_0402_50V8J

12

D20

1

C4

2

12

R325
2K_0402_5%

+5VS

21

1

C302
100P_0402_50V8J

2

0_0402_5%

2

G

1 3

D

Q18
2N7002_SOT23

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

FOX_DZ11A91-L7

+3VS

R330

S

1 3

D

16
17

12

2

JTV1

7
6
5
4
3
2
1

SUYIN_33007SR-07T1-C

+2.5VS

2.7K_0402_5%

R331

1 2

G

Q19

S

2N7002_SOT23

CRT Connector

12

R334

2.7K_0402_5%

R322

0_0402_5% 2@

1 2

R333

0_0402_5%

1 2

R326

0_0402_5% 2@

1 2

R332

0_0402_5%

1 2

SMBDAT_VGA <16>

1@

DAT_DDC2 <10>

SMBCLK_VGA <16>

1@

CLK_DDC2 <10>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

17 52

5

+3VS

R119

+3VS

ICH_SMBDATA

ICH_SMBCLK

G

2

ICH_SMBDATA<21>

D D

ICH_SMBCLK<21>

D

S

1 3

Q4
2N7002_SOT23

G

2

2

G

Q5
2N7002_SOT23

1 3

D

S

D

1

3

S

CK_VDD_A CK_VDD_REF

2N7002

12

10K_0402_5%

C139

R121

10K_0402_5%

1

2

4.7U_0805_6.3V6K

12

CK_SDATA

CK_SCLK

0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

C C

*

0

0

0

1

1

1

00

0

1

0

1

11

0

0

0

1

0

1

0

11

Table : ICS 954201 / Cypress CY28411

+VCCP

CLKSEL0

CLKSEL1

R486

1 2

1 2

R482
10K_0402_5%

@

1 2

5

10K_0402_5%@

R488
1K_0402_5%

+VCCP

1 2

1 2

R531
10K_0402_5%

@

R533
1K_0402_5%

1 2

R524
10K_0402_5%

@

B B

CPU_BSEL0<6>

A A

CPU_BSEL1<6>

MHz

266

133

200

166

333

100

400

SRC
MHz

100 33.30

100

100

100

100

100

100

RESERVED

MCH_CLKSEL0 <8>

PCI
MHz

33.3

33.3

CLK_14M_CODEC<29>

33.3

33.3

33.3

33.3

MCH_CLKSEL1 <8>

CLK_48M_ICH<21>

CLK_33M_1394<27>
CLK_33M_CBS<26>
CLK_33M_LPCSIO<31>
CLK_33M_MPCI<28>
CLK_33M_LAN<24>
CLK_33M_ICH<19>
CLK_33M_LPCEC<32>

4

CK_SDATA <13,14>

CK_SCLK <13,14>

CK_VDD_48

1

2

C508

0.047U_0402_16V7K

+3VS

R513
10K_0402_5%

1 2

R512
10K_0402_5%

@

1 2

1

2

C134

4.7U_0805_6.3V6K

33P_0402_50V8J

33P_0402_50V8J

CLK_14M_CODEC

CLKSEL2

4

1

2

C133

C476

12

X3 14.318MHZ_20P_1BX14318CC1A

C487

12

CLKSEL1
CLKSEL0

CLK_33M_CBS
CLK_33M_LPCSIO
CLK_33M_MPCI
CLK_33M_LAN
CLK_33M_ICH
CLK_33M_LPCEC

C456

0.1U_0402_16V4Z

0.047U_0402_16V7K

Place crystal within
500 mils of CK410

12

+3VS

+3VS

1 2

L25

CHB1608U301_0603

1

2

CHB1608U301_0603

R511 33_0402_5%

L24

C123

0.047U_0402_16V7K

12

R49333_0402_1%

+CK_VDD_MAIN2

12

12
12
12
12
12
12
12

1 2

R131 475_0603_1%

1 2

1

2

CK_XTAL_IN

CK_XTAL_OUT

R501 12.1_0402_1%
R502 12.1_0402_1%
R497 33_0402_5%
R498 33_0402_5%
R491 33_0402_5%
R508 33_0402_5%
R506 33_0402_5%

1 2

R509 10K_0402_5%

3

+CK_VDD_MAIN

2

C457
10U_0805_10V4Z

1

1

C137

0.047U_0402_16V7K

2

1

C523

0.047U_0402_16V7K

2

2

1

C511

0.047U_0402_16V7K

2

1

2

Place near each pin
W>40 mil

2

C444
10U_0805_10V4Z

1

U31

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

1 2

R126
1_0603_5%

1 2

R128

2.2_0603_5%

PCICLKF0

CK_VDD_REF

CK_VDD_48

CLKSEL2CLK_48M_ICH

PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1

CK_SCLK

CK_SDATA

CLKIREF

VDD_CPU

48

VDD_REF

11

VDD_48

50

XTAL_IN

49

XTAL_OUT

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

5

PCI5

4

PCI4

3

PCI3

56

PCI2

9

PCIF1

8

PCIF0/ITP_EN

46

SCLOCK

47

SDATA

39

IREF

13

VSS_48

29

VSS_SRC

2

VSS_PCI0

45

VSS_CPU

51

VSS_REF

6

VSS_PCI1

ICS954206AG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C479

0.047U_0402_16V7K

2

2005/03/01 2006/03/01

1

C466

0.047U_0402_16V7K

2

R145

2.2_0603_5%

VDD_A

VSS_A

PCI_STOP#

CPU_STOP#

CPU1

CPU1#

CPU0

CPU0#

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

DOT96

DOT96#

VTT_PWRGD#/PD

REF

CK_VDD_A

1 2

CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#

Compal Secret Data

Deciphered Date

Place near CK410M

37
38

H_STP_PCI#

55

H_STP_CPU#

54

CK_CPU1

41
40

44
43

36
35

33
32

31
30

26
27

24
25

22
23

19
20

17
18

14
15

10
52

1 2

R527 33_0402_5%

CK_CPU1#

1 2

R534 33_0402_5%

CK_CPU0
CK_CPU0#

CK_CPU2
CK_CPU2#

SCR5
SRC5#

SRC4
SRC4#

SRC1
SRC1# CLK_PCIE_ICH#

SRC0
SRC0# SSC_DREFCLK#

CLKREF

1 2

R514 33_0402_5%

1 2

R521 33_0402_5%

1 2

R539 33_0402_5%

1 2

R544 33_0402_5%

1 2

R549 33_0402_5%

1 2

R554 33_0402_5%

1 2

R553 33_0402_5%

1 2

R558 33_0402_5%

1 2

R543 33_0402_5%

1 2

R548 33_0402_5%

1 2

R142 33_0402_5%1@

1 2

R538 33_0402_5%1@

1 2

R520 33_0402_5%

1 2

R526 33_0402_5%

1@
1@

1 2

R499 12.1_0402_1%

1 2

R503 12.1_0402_1%

2

1

C505

0.047U_0402_16V7K

H_STP_PCI# <21>
H_STP_CPU# <21,45>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_ITP
CLK_ITP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH

SSC_DREFCLK

DREFCLK
DREFCLK#

CLK_14M_ICH

CLK_14M_SIO

Title

Size Document Number Rev

Custom

Date: Sheet

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_ITP
CLK_ITP#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

SSC_DREFCLK
SSC_DREFCLK#
DREFCLK
DREFCLK#

CLK_PCIE_ICH <21>
CLK_PCIE_ICH# <21>

SSC_DREFCLK <8>
SSC_DREFCLK# <8>

DREFCLK <8>
DREFCLK# <8>

10K_0402_5%

CLK_14M_ICH <21>

CLK_14M_SIO <31>

<Title>

LA-2362 1

Friday, March 11, 2005

R528 49.9_0402_1%
R535 49.9_0402_1%
R515 49.9_0402_1%
R522 49.9_0402_1%
R540 49.9_0402_1%
R545 49.9_0402_1%

1 2

R552 49.9_0402_1%

1 2

R557 49.9_0402_1%

1 2

R542 49.9_0402_1%

1 2

R547 49.9_0402_1%

1 2

R550 49.9_0402_1%

1 2

R555 49.9_0402_1%

1 2

R146 49.9_0402_1%

1 2

1@

R537 49.9_0402_1%

1 2

1@

R519 49.9_0402_1%

1 2

1@

R525 49.9_0402_1%

1@

CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>

CLK_ITP <5>
CLK_ITP# <5>

CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>

CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>

+3VS

12

R742

13

D

2

G

Q45 2N7002_SOT23

S

0.047U_0402_16V4Z

1

12
12
12
12
12
12

R744

1 2

10K_0402_5%

C635

1

2

of

18 52

VGATE <8,21,45>

5

4

3

2

1

RP4

+3VS

D D

+3VS

+3VS

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

+3VS

C C

+3VS

+3VALW

B B

PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_IRDY#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#

PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQH#
PCI_PIRQC#

R4808.2K_0402_5%

1 2

R4758.2K_0402_5%

1 2

R848.2K_0402_5%

1 2

R728.2K_0402_5%

1 2

R4478.2K_0402_5%

1 2

R708.2K_0402_5%

1 2

R888.2K_0402_5%

1 2

R4738.2K_0402_5%

1 2

R4488.2K_0402_5%

1 2

R4788.2K_0402_5%

1 2

R868.2K_0402_5%

1 2
1 2

R724 10K_0402_1%

ICH_PME#

PCI_PIRQE#
PCI_PIRQF#

PCI_PIRQA#

PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#

PCI_REQ2#
PCI_REQ5#
PCI_REQ6#

BATT1

PCI_AD[0..31]<24,26,27,28>

PCI_FRAME#<24,26,27,28>

CHGRTC

2

+RTCVCC

1

12

PCI_PIRQA#<26>
PCI_PIRQB#<26>

3

BAS40-04_SOT23
D16

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27PCI_PIRQG#
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PLTRST#

U7B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

+3V

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]
PIRQ[H]#/GPI[5]

RESERVED

14

1

P

A

2

B

G

7

@

+3V

14

4

P

A

5

B

G

7

@

L5

REQ[0]#

C1

GNT[0]#

B5

REQ[1]#

B6

GNT[1]#

M5

REQ[2]#

F1

GNT[2]#

B8

REQ[3]#

C8

GNT[3]#

F7
E7
E8
F6
B7
D8

J6

C/BE[0]#

H6

C/BE[1]#

G4

C/BE[2]#

G2

C/BE[3]#

A3

IRDY#

E1

PAR

R2

PCIRST#

C3

DEVSEL#

E3

PERR#

C5

PLOCK#

G5

SERR#

J1

STOP#

J2

TRDY#

R5

PLTRST#

G6

PCICLK

P6

PME#

D9
C7
C6
M3

U29A

PCIRSTB1#

3

O

74VHC08MTC_TSSOP14

R774

0_0402_5%

1 2

R775

0_0402_5%

1 2

U29B

PCIRSTB2#

6

O

74VHC08MTC_TSSOP14

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#

PCI_REQ6#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLTRST#
CLK_33M_ICH

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

C350

0.1U_0402_16V4Z

12

R443

33_0402_5%

1 2

R446

33_0402_5%

1 2

R445

33_0402_5%

1 2

PCI_REQ0# <24>

PCI_GNT0# <24>

PCI_REQ1# <26>

PCI_GNT1# <26>

PCI_REQ2# <27>

PCI_GNT2# <27>

PCI_REQ3# <28>

PCI_GNT3# <28>

PCI_C_BE0# <24,26,27,28>
PCI_C_BE1# <24,26,27,28>
PCI_C_BE2# <24,26,27,28>
PCI_C_BE3# <24,26,27,28>

PCI_IRDY# <24,26,27,28>
PCI_PAR <24,26,27,28>

PCI_DEVSEL# <24,26,27,28>
PCI_PERR# <24,26,27,28>

PCI_SERR# <24,26,28>

PCI_STOP# <24,26,27,28>
PCI_TRDY# <24,26,27,28>

PLTRST# <21>
CLK_33M_ICH <18>

PCI_PIRQE# <27>
PCI_PIRQF# <24>
PCI_PIRQG# <28>
PCI_PIRQH# <28>

PLTRST_VGA# <16,21>

PLTRST_SIO# <31>

PLTRST_MCH# <8>

R756

1 2

0_0402_5%

Q46

2N7002_SOT23

D

S

13

G

2

R757

12

10K_0402_5%

@

@

ICH_PME#

+3V

13

A

12

B

@

ICH_PME# <24,26,27,28,31,32>

+3V

14

U29D

P

11

O

G

74VHC08MTC_TSSOP14

7

CLK_33M_ICH

1 2

CLK_ICH_TERM

1

2

R472
10_0402_5%

@

C410

8.2P_0402_50V8J~D@

ML1220T13RE

PCI_PCIRST#

A A

5

4

R758

0_0402_5%

1 2

+3V

10

A

9

B

@

14

U29C

P

8

O

G

74VHC08MTC_TSSOP14

7

R389

PCIRSTB3#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

33_0402_5%

1 2

2005/03/01 2006/03/01

3

PCIRST# <24,26,27,28,32>

Compal Secret Data

Deciphered Date

2

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

1

of

19 52

5

C62

10P_0603_50V8J

12

32.768KHZ_12.5P_MC-306

1 2

12

+RTCVCC

IAC_RST#<29>

10P_0402_50V8J@

X1

Package

D D

+RTCVCC

12

R469
1M_0402_5%

INTRUDER#

IAC_BITCLK<29,35>

C C

IAC_SDATO_MDC<35>

B B

IAC_SYNC_MDC<35>

IAC_RST#_MDC<35>

9.6X4.06 mm

R96
33_0402_5%

1 2

R92
33_0402_5%

1 2

R105
33_0402_5%

1 2

+3VS +3VS

12

C68

10P_0603_50V8J

INTRUDER#

IAC_SYNC<29>

R483
10_0402_5%

@

1 2

IAC_SDATO<29>

ICH_AC_BITCLK_TERM

2

C458

1

ICH_AC_SDOUT_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

R114

4.7K_0402_5%

IDE_HDIORDY IDE_HIRQ

R467
180K_0402_5%

CMOS_CLR1
SHORT PADS~D

1

1

@

C400

0.1U_0402_16V4Z

1 2

12

R504
10K_0402_5%

ICH_RTCX1

ICH_RTCX2

1 2

2

IAC_SDATAI1<29>
IAC_SDATAI2<35>

IDE_HIORDY<23>
IDE_HIRQ<23>

IDE_HDACK#<23>
IDE_HDIOW#<23>
IDE_HDIOR#<23>

R68

2

1 2
1 2

1 2

12

10M_0402_5%

R474 0_0402_5%

1 2

R95

33_0402_5%

@

R9133_0402_5%
R10433_0402_5%

4

R471

0_0402_5%

ICH_RTCRST#
INTRUDER#

1 2

12

ICH_AC_SYNC_R
ICH_AC_RST_R#
IAC_SDATAI1

IAC_SDATAI2

ICH_AC_SDOUT_R

R101

24.9_0603_1%

IDE_HDIORDY
IDE_HIRQ
IDE_HDDACK#
IDE_HDIOW#
IDE_HDIOR#

AA2
AA3

AA5

D12
D11

C13
C12

C11

C10

AC19

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

AG11
AF11

AF16
AB16
AB15
AC14
AE16

B12
F13
F12
B11
E12

E11

E13

B9
A10
F11

F10
B10

C9

U7A

Y1

RTCX1

Y2

RTCX2
RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH6_BGA609

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

A20GATE

A20M#

LAN

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

RCIN#

STPCLK#

THRMTRIP#

DCS1#
DCS3#

SATAAC-97/AZALIA

PIDE

DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

INIT#

INTR

SMI#

DA[0]
DA[1]
DA[2]

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]

3

LPC_LAD0

P2

LPC_LAD1

N3

LPC_LAD2

N5

LPC_LAD3

N4

LPC_LDRQ0#

N6

LPC_LDRQ1#

P4

LPC_LFRAME#

P3

GATEA20

AF22

A20M#

AF23

CPUSLP#

AE27
AE24

DPSLP#

AD27

FERR#

AF24

H_PWRGOOD

AG25

IGNNE#

AG26
AE22

ICH4_INIT#

AF27

INTR

AG24

KBRST#

AD23

NMI

AF25

NMI

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

SMI#
STPCLK#
THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

R135 0_0402_5%
R161 0_0402_5%
R551 0_0402_5%

R162 0_0402_5%
R144 56_0402_5%

R148 0_0402_5%
R159 0_0402_5%

R139 0_0402_5%

R147 0_0402_5%
R151 0_0402_5%

R160 0_0402_5%

R496
0_0402_5%

LPC_LAD[0..3] <31,32>

LPC_LDRQ0#
LPC_LDRQ1# <31>

LPC_LFRAME# <31,32>

12
12
12

12
12

12
12

12

12
12

12

1 2

IDE_HDA0 <23>
IDE_HDA1 <23>
IDE_HDA2 <23>

IDE_HDCS1# <23>
IDE_HDCS3# <23>

IDE_HDD[0..15] <23>

1 2

C461

Note : R169 Do not populate for
Dothan-A, Populte for Dothan-B.

H_THERMTRIP#

R541
56_0402_5%

IDE_HDREQIDE_DDREQ

2

1

33P_0402_50V8J

H_A20M#
H_CPUSLP#
H_DPRSLP#DPRSLP#

H_DPSLP#

H_IGNNE#
H_INIT#

H_INTR

H_NMI
H_SMI#

H_STPCLK#

2

GATEA20 <32>

H_INIT# <5>

KBRST# <32>

IDE_HDREQ <23>

H_A20M# <5>
H_CPUSLP# <5,8>
H_DPRSLP# <5>

H_DPSLP# <5>
H_FERR# <5>
H_PWRGOOD <5>
H_IGNNE# <5>

H_INTR <5>

H_NMI <5>
H_SMI# <5>

H_STPCLK# <5>

+CPU_CORE

+VCCP

+VCCP

H_THERMTRIP#<5,8>

R143

H_FERR#

H_DPRSLP#

56_0402_5%

R546

56_0402_5%

Note : R423 must be stuff for
Dothan-A, no-stuff for Dothan-B.

Note : R168 populate 56 ohm for
Dothan-A, Populte zero ohm for
Dothan-B.

R762
47K_0402_5%

1 2

R561
47K_0402_5%@

1 2

1 2

C526

@

0.68U_0603_10V6K

1 2

R494
75_0402_5%

2

B

1

C

Q39
2SC2411K_SC59

E

3

H_THERMTRIP#

1

+VCCP

12

12

MAINPWRON <39,41,44>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

20 52

5

D D

+3VSUS

2.2K_0402_5%

R461

ICH_SMBDATA<18>
ICH_SMBCLK<18>

C C

+3VSUS

2.2K_0402_5%
10K_0402_5%

R460

1 2

1 2

10K_0402_5%

R449

R450

1 2

1 2

ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK0
ICH_SMLINK1

ACIN<32,40,41>

+3V

R761 10K_0402_5%

1 2

+3VS

(PCI Express Wake Event)

B B

CLK_14M_ICH<18>

CLK_48M_ICH<18>

+3VS

R516

1 2

1K_0402_5%

@

PM_DPRSLPVR

5

R523

100K_0402_5%

12

@

A A

May need pulldown for DPRSLPVR in case
the ICH6m does not set this value in time
for boot.

CLKRUN#

CLK_14M_ICH

CLK_48M_ICH

R487

@

C455

1 2

CK_14M_ICH_TERM

2

1

@

10_0402_5%

@

1 2

CK_48M_ICH_TERM

2

1

4.7P_0402_50V8C

R556

10_0402_5%

C520

4.7P_0402_50V8C

@

R729 0_0402_5%@

12

4

1 2

D

1 3

Q47

G

2

PLTRST_VGA#<16,19>

R125
10K_0402_5%

+3VSUS

+3VSUS

+3VSUS

+3VSUS

+3VSUS

4

S

2N7002_SOT23

1 2

1 2

1 2

1 2

1 2

+3V

SIRQ<26,31,32>

R457
10K_0402_5%

R69
10K_0402_5%

R456
10K_0402_5%

R455
10K_0402_5%

R451
680_0402_5%

SPKR<30>

PM_BMBUSY#<8>

+3VS

EC_SMI#<32>

LID_SWOUT#<32>
EC_SCI#<32>

H_STP_PCI#<18>

H_STP_CPU#<18,45>

R507 10K_0402_5%@

1 2
1 2

R536 0_0402_5%@

IDE_HRESET#<23>
IDE_DRESET#<23>

EC_FLASH#<33>

CLKRUN#<24,26,28,31,32>

VGATE<8,18,45>

SLP_S3#<32>
SLP_S4#<32>
SLP_S5#<32>

ICH_PWRGD<32>
PM_DPRSLPVR<45>
ICH_BATLOW#<32>
PWRBTN_OUT#<32>

PLTRST#<19>
RSMRST#<32>

LINKALERT#

SYS_RESET#

ACINA

ICH_BATLOW#

ICH_PCIE_WAKE#

+3VS

12

R117

10K_0402_5%

R120 33_0402_5%@

SIRQ

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR

T30

SYS_RESET#
PM_BMBUSY#

R510 10K_0402_5%

1 2

EC_SMI#

EC_SCI#
H_STP_PCI#

H_STP_CPU#

CLKRUN#

ICH_PCIE_WAKE#

R746 0_0402_5%

1 2

SIO_THRM#
VGATE
CLK_14M_ICH
CLK_48M_ICH

T32

ICH_SUSCLK

PAD

@

SLP_S3#
SLP_S4#
SLP_S5#

ICH_PWRGD
PM_DPRSLPVR
ICH_BATLOW#
PWRBTN_OUT#
PLTRST#
RSMRST#

3

+3VSUS

12

R71

10K_0402_5%

ICH_RI#

PAD

@

12

10K_0402_5%

R75

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ACINA

3

12

T2

AF17
AE18
AF18
AG18

Y4

W5

Y5

W4

U6

AG21

F8

W3

U2
AD19
AE19

R1

W6

M2

R6
AC21
AB21
AD22

AD20
AD21

V3

P5

R3

T3
AF19
AF20
AC18

U5
AB20
AC20
AF21

E10
A27

V6

T4

T5

T6

AA1

AE20

V2

U1

V5

Y3

10K_0402_5%

R459

U7C

RI#
SATA[0]GP/GPI[26]

SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

SUS_STAT#/LPCPD#
SYS_RESET#
BM_BUSY#/GPI[6]
GPI[7]

GPI[8]
SMBALERT#/GPI[11]
GPI[12]

GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]

GPO[21]
GPO[23]

GPIO[24]
GPIO[25]

GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
RSMRST#

ICH6_BGA609

+3VS

+3VS

+3VS

GPIO

DMI_IRCOMP

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

CLOCK

USB

POWER MGT

R529

8.2K_0402_5%

1 2

R130

10K_0402_5%

1 2

R518

10K_0402_5%

1 2

2005/03/01 2006/03/01

H25

PERn[1]

H24

PERp[1]

G27

PETn[1]

G26

PETp[1]

K25

PERn[2]

K24

PERp[2]

J27

PETn[2]

J26

PETp[2]

M25

PERn[3]

M24

PERp[3]

L27

PETn[3]

L26

PETp[3]

P24

PERn[4]

P23

PERp[4]

N27

PETn[4]

N26

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETp[4]

T25

DMI[0]RXN

T24

DMI[0]RXP

R27

DMI[0]TXN

R26

DMI[0]TXP

V25

DMI[1]RXN

V24

DMI[1]RXP

U27

DMI[1]TXN

U26

DMI[1]TXP

Y25

DMI[2]RXN

Y24

DMI[2]RXP

W27

DMI[2]TXN

W26

DMI[2]TXP

AB24

DMI[3]RXN

AB23

DMI[3]RXP

AA27

DMI[3]TXN

AA26

DMI[3]TXP

AD25

DMI_CLKN

AC25

DMI_CLKP

F24

DMI_ZCOMP

F23
C23

D23
C25
C24

C27

OC[0]#

B27

OC[1]#

B26

OC[2]#

C26

OC[3]#

C21

USBP[0]N

D21

USBP[0]P

A20

USBP[1]N

B20

USBP[1]P

D19

USBP[2]N

C19

USBP[2]P

A18

USBP[3]N

B18

USBP[3]P

E17

USBP[4]N

D17

USBP[4]P

B16

USBP[5]N

A16

USBP[5]P

C15

USBP[6]N

D15

USBP[6]P

A14

USBP[7]N

B14

USBP[7]P

A22

USBRBIAS#

B22

USBRBIAS

SIO_THRM#

MCH_SYNC#

SIRQ

Compal Secret Data

Deciphered Date

@
@
@
@

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP

OVCUR#4
OVCUR#5
OVCUR#6
OVCUR#7

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3

USBP0­USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

2 1

RB751V_SOD323

R725 39K_0402_5%

2

DMI_RXN0 <8>
DMI_RXP0 <8>

DMI_RXN1 <8>
DMI_RXP1 <8>

DMI_RXN2 <8>
DMI_RXP2 <8>

DMI_RXN3 <8>
DMI_RXP3 <8>

R517 24.9_0603_1%

22.6_0603_1%

D15

1 2

2

T21PAD
T40PAD
T23PAD
T22PAD

DMI_TXN0 <8>
DMI_TXP0 <8>

DMI_TXN1 <8>
DMI_TXP1 <8>

DMI_TXN2 <8>
DMI_TXP2 <8>

DMI_TXN3 <8>
DMI_TXP3 <8>

1 2

OVCUR#4 <36>

OVCUR#0 <36>
OVCUR#1 <36>

OVCUR#3 <36>

1 2

R141

CLK_PCIE_ICH# <18>
CLK_PCIE_ICH <18>

1

OVCUR#0

R781 10K_0402_5%

OVCUR#1
OVCUR#2
OVCUR#3

OVCUR#4
OVCUR#5
OVCUR#6
OVCUR#7

+1.5VS

closed to 500 mils

USBP0- <36>
USBP0+ <36>
USBP1- <36>
USBP1+ <36>
USBP2- <35>
USBP2+ <35>
USBP3- <36>
USBP3+ <36>
USBP4- <36>
USBP4+ <36>
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

EC_THRM# <32>

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

1 2

R782 10K_0402_5%

1 2

R783 10K_0402_5%

1 2

R784 10K_0402_5%

1 2

R785 10K_0402_5%

1 2

R786 10K_0402_5%

1 2

R787 10K_0402_5%

1 2

R788 10K_0402_5%

1 2

1

+3VSUS

of

21 52

5

Near PIN F27(C968),

C524

0.1U_0402_16V4Z

1

C707

2

Near PIN
E26, E27

1

+

2

220U_D2_4VM

0.1U_0402_16V4Z

C708

Near PIN AG5

Near PIN AG9

2

C514

1

0.1U_0402_16V4Z

+3VSUS

P27(C949), AB27(C950)

0.1U_0402_16V4Z

1

2

+1.5VS

+1.5VS

+1.5VS

Near PIN A17

+3VS

+5VS

D4

RB751V_SOD323

1 2

R129

1 2

21

2

C115
1U_0603_10V4Z

1

+3VSUS+5VALW

D5

21

RB751V_SOD323

2

1

R103

10_0402_5%

D D

10_0402_5%

C C

C136
1U_0603_10V4Z

+1.5VS

ICH_V5REF_RUN

2

C485

0.1U_0402_16V4Z

1

2

1

1 2

ICH_V5REF_SUS

C506

0.1U_0402_16V4Z

L27 0_0603_5%

+1.5VRUN_L

2

C439

0.1U_0402_16V4Z

1

1

C706

2

Replacing by this circuit?

Note: Intel will update design guide.

R97
10_0402_5%

@

R127
10_0402_5%

@

U8 APL5301-15DC_3P

Vin2Vout

CHB1608U301_0603

5

ICH_V5REF_RUN

ICH_V5REF_SUS

3

GND

1

L28

1 2

+1.5VR

1

2

2

C517

1

0.1U_0402_16V4Z

C110

0.1U_0402_16V4Z

ICH6_VCCPLL

1

C519

2

0.01U_0402_16V7K

Near PIN
AC27

+3VS

+3V

R779
0_0805_5%

@

1

C111

0.1U_0402_16V4Z

2

R559

1 2

1_0402_5%

1 2

1 2

+5V

B B

+5VALW

+3VALW

+3VSUS

R778
0_0805_5%

+1.5VS

A A

2

2

C513

C521

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C709

C710

2

2

2

C395

1

0.1U_0402_16V4Z

Near PIN AE1

2

C490

1

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C405

1

2

C426

1

+3VS

+3VS

0.1U_0402_16V4Z

4

2

C501

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C711

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

ICH6_VCCPLL

+3VSUS

2

C489

1

0.1U_0402_16V4Z

U7E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

ICH6_BGA609

COREIDE

PCIE

PCIUSB

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

SATA

USB CORE

PCI/IDE RBP

V5REF_SUS

VCCUSBPLL

VCCSUS3_3[20]

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]

VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]
V5REF[1]

VCCRTC

3

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VS

2

C462

1

2

C396

1

+1.5VR

1

2

C488

0.1U_0402_16V4Z

+1.5VS

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VS

1

2

C509

C484

0.1U_0402_16V4Z

C394

0.1U_0402_16V4Z

+RTCVCC

+1.5VS

+VCCP

0.1U_0402_16V4Z

+3VSUS

+3VS

2

Near PIN

1

AG13, AG16

0.1U_0402_16V4Z

2

2

C425

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VR

2

1

1

2

C440

0.1U_0402_16V4Z

Near PIN U7

+2.5VS

Near PIN AB18

Near PIN AG23

+3VS

+3VS

Near PIN
A2-A6, D1-H1

C435

0.1U_0402_16V4Z

1

2

C486

0.1U_0402_16V4Z

C467

0.1U_0402_16V4Z

1 2

C447

1 2

0.1U_0402_16V4Z

+1.5VS

2

C497

0.1U_0402_16V4Z

1 2

C477

0.1U_0402_16V4Z

1 2

C471

0.1U_0402_16V4Z

1 2

C491

0.1U_0402_16V4Z

1 2

C492

0.1U_0402_16V4Z

1 2

C474

0.1U_0402_16V4Z

1 2

C454

0.1U_0402_16V4Z

1 2

C453

0.1U_0402_16V4Z

1 2

C464

0.1U_0402_16V4Z

1 2

C434

0.1U_0402_16V4Z

1 2

C515

0.01U_0402_16V7K

1 2

Near PIN A25

C493

0.01U_0402_16V7K

1 2

Near PIN AA19

+3VSUS

C660

0.1U_0402_16V4Z

1 2

C661

0.1U_0402_16V4Z

1 2

C397

0.1U_0402_16V4Z

1 2

C436

0.1U_0402_16V4Z

1 2

C472

0.1U_0402_16V4Z

1 2

C510

0.1U_0402_16V4Z

1 2

Near PIN A24

Near PIN AG10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

2

1

U7D

E27

VSS[172]

Y6

VSS[171]

Y27

VSS[170]

Y26

VSS[169]

Y23

VSS[168]

W7

VSS[167]

W25

VSS[166]

W24

VSS[165]

W23

VSS[164]

W1

VSS[163]

V4

VSS[162]

V27

VSS[161]

V26

VSS[160]

V23

VSS[159]

U25

VSS[158]

U24

VSS[157]

U23

VSS[156]

U15

VSS[155]

U13

VSS[154]

T7

VSS[153]

T27

VSS[152]

T26

VSS[151]

T23

VSS[150]

T16

VSS[149]

T15

VSS[148]

T14

VSS[147]

T13

VSS[146]

T12

VSS[145]

T1

VSS[144]

R4

VSS[143]

R25

VSS[142]

R24

VSS[141]

R23

VSS[140]

R17

VSS[139]

R16

VSS[138]

R15

VSS[137]

R14

VSS[136]

R13

VSS[135]

R12

VSS[134]

R11

VSS[133]

P22

VSS[132]

P16

VSS[131]

P15

VSS[130]

P14

VSS[129]

P13

VSS[128]

P12

VSS[127]

N7

VSS[126]

N17

VSS[125]

N16

VSS[124]

N15

VSS[123]

N14

VSS[122]

N13

VSS[121]

N12

VSS[120]

N11

VSS[119]

N1

VSS[118]

M4

VSS[117]

M27

VSS[116]

M26

VSS[115]

M23

VSS[114]

M16

VSS[113]

M15

VSS[112]

M14

VSS[111]

M13

VSS[110]

M12

VSS[109]

L25

VSS[108]

L24

VSS[107]

L23

VSS[106]

L15

VSS[105]

L13

VSS[104]

K7

VSS[103]

K27

VSS[102]

K26

VSS[101]

K23

VSS[100]

K1

VSS[99]

J4

VSS[98]

J25

VSS[97]

J24

VSS[96]

J23

VSS[95]

H27

VSS[94]

H26

VSS[93]

H23

VSS[92]

G9

VSS[91]

G7

VSS[90]

G21

VSS[89]

G12

VSS[88]

G1

VSS[87]

ICH6_BGA609

Title

Size Document Number Rev

Date: Sheet

GROUND

+RTCVCC

1

2

C401

0.1U_0402_16V4Z

<Title>

LA-2362 1

Custom

Friday, March 11, 2005

1

2

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

C417

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

0.1U_0402_16V4Z

1

of

22 52

A

IDE_HDD0
IDE_HDD1
IDE_HDD2

1 1

IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8

IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

+5VHDD

2 2

IDE_HDD[0..15] <20>

IDE_HRESET#<21>

IDE_HDREQ<20>
IDE_HDIOW#<20>
IDE_HDIOR#<20>

IDE_HIORDY<20>
IDE_HDACK#<20>

IDE_HIRQ<20>
IDE_HDA1<20>
IDE_HDA0<20>
IDE_HDCS1#<20>

1 2

R318 10K_0402_5%

IDE_HRESET#

IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDREQ

IDE_HDIOW#

IDE_HDIOR#

IDE_HIORDY

IDE_HDACK#

IDE_HIRQ

IDE_HDA1
IDE_HDA0
IDE_DCS1#
HDD_ACT#

B

HDD Connector

JHDD1

2
4
6
8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

46

ALLTOP_C17866-14405

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND45GND

IDE_HDD8

3

IDE_HDD9

5

IDE_HDD10

7

IDE_HDD11

9

IDE_HDD12

11

IDE_HDD13

13

IDE_HDD14

15

IDE_HDD15

17
19
21
23
25

R308 470_0402_5%

27
29

R310 10K_0402_5%@

31
33

IDE_HDA2

35

IDE_HCS3#

37
39
41
43

1 2
1 2

C

PDIAG#

IDE_HDA2 <20>
IDE_HDCS3# <20>

+5VHDD

R315

@

10K_0402_5%

1 2

D

+3VS

12

21

IDE_DRESET#<21>

IDE_DRESET#

R813
0_0402_5%

@

@

RB751V_SOD323
D27

C593 47P_0402_50V8J

+5VS

E

F

G

H

CD-ROM Connector

C594

1 2

47P_0402_25V8K

IDE_HDD8
IDE_HDD9
IDE_HDD10

IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
IDE_HDREQ
IDE_HDIOR#

IDE_HDACK#
PDIAG#

IDE_HDA2
IDE_HDCS3#

INT_CD_R <29>

+5VMOD

Layout Note: W=80 mils

1 2

CD_GNA<29>

R702

4.7K_0402_5%

1 2

SEC_CSEL

INT_CD_L<29>

12

+5VMOD

R703

1 2

R8140_0402_5%

10K_0402_5%

Q48
2N7002_SOT23

D

1 3

G

2

HDD_ACT#

+5VMOD

C595

1 2

47P_0402_25V8K

IDE_HDD7

S

IDE_HDD6
IDE_HDD5 IDE_HDD11
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDIOW#
IDE_HIORDY

IDE_HIRQ
IDE_HDA1
IDE_HDA0
IDE_DCS1#

JCDR1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

OCTEK_CDR-50JE2

IRQ how to assign

+5VHDD Source

1U_0603_10V4Z

+5VS

C657

+12VALW

3 3

+5VS

1 2

R317
470_0402_5%

2

G

1

2

12

13

D

S

C656

1

2

R314
100K_0402_5%

Q16
2N7002_SOT23

0.1U_0402_16V4Z

+5VMOD Source

+5VS

1

C659

2

4 4

A

C292

12

0.01U_0402_16V7K

R316

150K_0603_5%

1U_0603_10V4Z

C658

B

R815

@

1 2

0_0805_5%
Q17

AO3413_SOT23

S

G

2

1

2

0.1U_0402_16V4Z

1

2

+5VHDD

D

13

10U_0805_10V4Z

G

2

13

D

S

AO3413_SOT23
Q14

R816

1 2

0_0805_5%

@

Layout Note: Place close to HDD CONN.

1000P_0402_50V7K

0.1U_0402_16V4Z

1

2

1U_0603_10V4Z

C296

+5VMOD

C293

1

1

C301

2

1

C294

2

2

Layout Note: Place close to CD-ROM CONN.

1000P_0402_50V7K

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

1

C279

2

C281

1

1

C278

2

2

C

HDD_ACT#

1

C280

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/03/01 2006/03/01

E

HDD_ACT# <33>

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

F

Date: Sheet

G

of

23 52

H

5

2

C75

0.1U_0402_10V6K

+3VALW

D D

C33

1U_0603_10V6K

C C

B B

CLK_PCI_LAN

A A

2

C63

1

1

0.1U_0402_10V6K

1 2

1

0_0805_5%
L10

2

1 2

KC FBM_L11-201209-601LMT 0805

PCI_AD[0..31]<19,26,27,28>

12

R45
10_0402_5%

1

C34

4.7P_0402_50V8B

2

5

R39

@

PCI_AD17

PCIRST#<19,26,27,28,32>

CLK_33M_LAN<18>

CLKRUN#<21,26,28,31,32>

@

LAN_IO

2

C37

0.1U_0402_10V6K

1

LAN_IO

1

2

PCI_AD[0..31]

PCI_C_BE0#<19,26,27,28>
PCI_C_BE1#<19,26,27,28>
PCI_C_BE2#<19,26,27,28>
PCI_C_BE3#<19,26,27,28>

R65 0_0402_5%

PCI_PAR<19,26,27,28>
PCI_FRAME#<19,26,27,28>
PCI_IRDY#<19,26,27,28>
PCI_TRDY#<19,26,27,28>
PCI_DEVSEL#<19,26,27,28>
PCI_STOP#<19,26,27,28>

PCI_PERR#<19,26,27,28>

PCI_SERR#<19,26,28>
PCI_REQ0#<19>

PCI_GNT0#<19>
PCI_PIRQF#<19>

ICH_PME#<19,26,27,28,31,32>

@

LAN_IO

C40
1U_0603_10V6K

1 2

PCIRST#
CLK_PCI_LAN

0_0402_5% @

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R80

LAN_IO

12

1

C85

0.1U_0402_10V6K

2

U4

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100CL_LQFP128

4

closed to chip about 200 mils

1

C86

0.1U_0402_10V6K

2

EEDO

AUX/EEDI

EESK

EECS

LED0
LED1
LED2

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/SMBDATA

NC/M66EN
NC/AVDDH

NC/HV

PCI I/F

NC/HSDAC+

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

NC/GND

CTRL25

RTT3/CRTL18

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

4

3

1

C84

0.1U_0402_10V6K

2

108
109
111
106

117
115
114
113

1
2
5
6

14
15
18
19

121

X1

122

X2

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

0.1U_0402_10V6K

32
54
78
99

24
45
64
110
116

1

C69

0.1U_0402_10V6K

2

LAN_IO

12

R82

3.6K_0402_5%

LAN_ACT# CLKOUT XTALFB
SPD_10_100_G#

LAN_TX0+
LAN_TX0­LAN_RX1+
LAN_RX1-

LAN_TX2+
LAN_TX2­LAN_TX3+
LAN_TX3-

XTALFB
CLKOUT

R421 2.49K_0603_1%

1 2

closed to chip

R81 1K_0402_1%

1 2

@

2@

R420 0_0402_5%

1 2

R64 0_0402_5%

1 2

R59 0_0402_5%

1 2

R58 0_0402_5%

1 2

2@

CTL25
CTL12

R386

0_0603_5%

2

C36

1

R399
0_0603_5%2@

1 2

0.1U_0402_10V6K

1

C53

0.1U_0402_10V6K

2

4
3
2
1

LAN_ACT# <25>
SPD_10_100_G# <25>

LAN_TX0+ <25>
LAN_TX0- <25>
LAN_RX1+ <25>
LAN_RX1- <25>

LAN_TX2+ <25>
LAN_TX2- <25>
LAN_TX3+ <25>
LAN_TX3- <25>

5.6k for 8100C

R721
0_0402_5%

1 2

LAN_IO

1@

R379

2@

0_0603_5%

1 2

1 2

2

C38

0.1U_0402_10V6K

1

2

C89

1

12

R48 0_0402_5%

1 2

2@

R47 0_0402_5%

1 2

1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C35

0.1U_0402_10V6K

1

U6

DO

GND

DI

NC

SK

NC

CS

VCC

AT93C46-10SI-2.7_SO8

+3VS

LAN_IO

+1.2V_LAN

CTL25

CTL12

1@

R390

0_0603_5%

1 2

2

C90

0.1U_0402_10V6K

1

+2.5V_LAN

LAN_IO

3

2

C103

0.1U_0402_10V6K

5

1

6
7
8

LAN_IO

12

R43
1K_0402_1%

R46

@

15K_0402_1% @

1 2

SUSP# <16,32,33,37,42>

+3VALW

3

Q32

1

2SB1188_SOT89

2

0.1U_0402_10V6K

3

Q33

1

2SB1188_SOT89

2

0.1U_0402_10V6K

+2.5V_LAN

+1.2V_LAN

2@

12

R395 0_0603_5%

2005/03/01 2006/03/01

1 2

L21 0_0805_5%

2

1

C328

1

2

1

2

C335

C333

10U_1206_6.3V6M

2

1

Compal Secret Data

C332
10U_1206_6.3V6M

1 2

L22 0_0805_5%

Deciphered Date

2

Y1

1 2

25MHZ_20P_1BX25000CK1A

1

C58
27P_0402_50V8J

2

0.1U_0402_10V6K

0.1U_0402_10V6K

2

+2.5V_LAN

2

C356

1

1

C364

2

2

C60
27P_0402_50V8J

1

1

+1.2V_LAN

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

1

of

24 52

5

4

3

2

1

C375 0.1U_0402_16V4Z

1 2

2@

LAN_TX3+<24>

D D

C C

Termination plane should be copled to chassis ground
and also depends on safety concern

B B

LAN_TX3-<24>

C374 0.1U_0402_16V4Z

1 2

2@

LAN_TX2+<24>

LAN_TX2-<24>

C373 0.1U_0402_16V4Z

1 2

LAN_RX1+<24>

LAN_RX1-<24>

C370 0.1U_0402_16V4Z

1 2

LAN_TX0+<24>

LAN_TX0-<24>

RTL8110SBL used the 24HST1041A-3_24P

RTL8100CL used the 24ST0023-3_24P

Layout Note
24HST1041A-3 pls close to conn.

LAN_TX0­LAN_TX0+

V_DAC

LAN_RX1­LAN_RX1+

V_DAC

LAN_TX3+

LAN_TX3-

V_DAC

LAN_TX2+

LAN_TX2-

V_DAC

LAN_RX1+

LAN_RX1-

V_DAC

LAN_TX0+

LAN_TX0-

1 2

V_DAC

T28

1

TCT1
TD1+

TD1­TCT2
TD21+

TD2­TCT3
TD3+

TD3­TCT4
TD4+

TD4-

1:1

1:1

1:1

1:1

T41

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

1@

1:1

TX+

RX­RX+

24HST1041A-3_24P2@

RJ45_TX0-

9

RJ45_TX0+

10
11

CT

14

CT

RJ45_RX1-

15

RJ45_RX1+

16

2

3
4
5

6
7
8

9
10
11

12

0_0402_5%

R811

1@

MCT1
MX1+

MX1­MCT2
MX2+

MX2­MCT3
MX3+

MX3­MCT4
MX4+

MX4-

24

RJ45_TX3+

23

RJ45_TX3-

22
21

RJ45_TX2+

20

RJ45_TX2-

19
18

RJ45_RX1+

17

RJ45_RX1-

16
15

RJ45_TX0+

14

RJ45_TX0-

13

75_0402_1%

12

R759

1@

12

1@

R789 75_0402_1%2@
R790 75_0402_1%2@
R791 75_0402_1%2@
R792 75_0402_1%2@

R760
75_0402_1%

1 2
1 2
1 2
1 2

C32
1000P_1206_2KV7K

12

JLAN1

SPD_10_100_G#<24>

LAN_IO

LAN_ACT#<24>

LAN_IO

1 2

R5

RJ45_TX3-

300_0603_5%

RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

1 2

R20 300_0603_5%

V_DAC

LAN_TX0+

LAN_TX0-

LAN_RX1+

LAN_RX1-

LAN_TX2+

LAN_TX2-

LAN_TX3+

LAN_TX3-

R405 0_0402_5%

R50 49.9_0402_1%

1 2

R49 49.9_0402_1%

1 2

R52 49.9_0402_1%

1 2

R51 49.9_0402_1%

1 2

R54 49.9_0402_1%

1 2

R53 49.9_0402_1%

1 2

2@

R56 49.9_0402_1%

1 2

2@

R55 49.9_0402_1%

1 2

2@

2@

1 2

2@

T=10mil

T=10mil

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_1566597-1

C45 0.01U_0402_16V7K

1 2

C46 0.01U_0402_16V7K

1 2

C47 0.01U_0402_16V7K

1 2

2@

C42 0.01U_0402_16V7K

1 2

2@

+2.5V_LAN

SHLD4
SHLD3

SHLD2
SHLD1

16
15

14
13

C1

1 2

0.1U_0402_16V4Z
C2

1 2

Termination plane should be copled
to chassis ground and also depends
on safety concern

Please close to LAN IC

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

2

0.1U_0402_16V4Z
C19

1 2

0.1U_0402_16V4Z

C11

1 2

0.1U_0402_16V4Z

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

1

of

25 52

5

VPPEN0
VPPEN1
CBS_VCCD0#
CBS_VCCD1#

C2
C1
D4
D2
D1

E4
E3
E2
F2

F1
G2
G3
H3
H4

J1

J2
N2
M3
N3

K4
M4

K5

L5
M5

K6
M6
N6
M7
N7

L7

K7
N8

E1

J3
N1
N5

G4

J4

K1

K3

L1

L2

L3
M1
M2

A1

B1
H1

L8

L11

F4

K8
N9

K9

N10

L10
N11
M11

M10

J9

E7

G5

E8

H7

MSCLK
SDCLK
SDCMD
SDWP#

U28

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CBE3#
CBE2#
CBE1#
CBE0#

PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK

RIOUT#_PME#
SUSPEND#

IDSEL
MFUNC0

MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

GRST#

MFUNC7

VCC_SD
GND_SD

SDCD#
MSINS#

1 2

D D

PCI_AD[0..31]<19,24,27,28>

Place close to JCBUS

C437

1 2

PCI_AD20

PCI_PIRQA#<19>
PCI_PIRQB#<19>

CR_LED#<33>
CLKRUN#<21,24,28,31,32>

+CBS_VCC

0.01U_0402_16V7K

10U_0805_10V4Z

1

1

C432

2

2

PCI_C_BE3#<19,24,27,28>
PCI_C_BE2#<19,24,27,28>
PCI_C_BE1#<19,24,27,28>
PCI_C_BE0#<19,24,27,28>

PCIRST#<19,24,27,28,32>
PCI_FRAME#<19,24,27,28>
PCI_IRDY#<19,24,27,28>
PCI_TRDY#<19,24,27,28>
PCI_DEVSEL#<19,24,27,28>
PCI_STOP#<19,24,27,28>
PCI_PERR#<19,24,27,28>
PCI_SERR#<19,24,28>
PCI_PAR<19,24,27,28>

PCI_REQ1#<19>

PCI_GNT1#<19>

CLK_33M_CBS<18>

ICH_PME#<19,24,27,28,31,32>

1 2

SIRQ<21,31,32>

R442

+3V

100K_0402_5%

+SD_VCC

12

R441

CBS_GRST#

1U_0603_10V4Z

1

C384

2

5

+CBS_VPP

0.01U_0402_16V7K

1

C423

2

C C

+3V

B B

R42

A A

C41

cardbus

1394

CBS_RST#

CLK_33M_CBS

@

10_0402_5%

12

@

4.7P_0402_50V8C

CK33M_CBS_TERM

2

1

R406 10K_0402_5%

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCIRST#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_REQ1#
PCI_GNT1#

CBS_IDSEL

R382100_0402_5%

R747 0_0402_5%

1 2

R748 0_0402_5%

1 2

R750 0_0402_5%

1 2

0_0402_5%@

12

CBS_GRST#

SDCD#
MSINS#

R751 0_0402_5%@

1 2

+CBS_VCC

G13

A7

N13

M13

N12

M12

VPPD0

VPPD1

VCCA1

VCCA2

VCCD0#

VCCD1#

MSCLKE9SDCLKF6SDCMDE5SDWPF8SDCLKIH5MSBSH8MSPWREN#J8SDPWREN33#G7MSDATA3F9MSDATA2G8MSDATA1H9MSDATA0

R39143K_0402_5%

MSBS

C8

H11

D12

B4

VCC9

VCC7

VCC8

VCC10

CARDBUS

CSTSCHG/BVD1_STSHG#

CCLKRUN#/WP_IOIS16#

SD

SD_EN#

MS_EN#

4

+3V

G1

K2

N4

F3

L6

L9

VCC2

VCC3

VCC4

VCC1

VCC5

VCC6

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE3#/REG#

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CRST#/RESET

CFRAME#/A23

CIRDY#/A15

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CPAR/A13

CREQ#/INPACK#

CGNT#/WE#

CCLK/A16

CBLOCK#/A19

CINT#/READY_IREQ#

SPKROUT

CAUDIO/BVD2_SPKR#

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#
CVS1/VS1#

GND1
GND2
GND3
GND4
GND5
GND6
GND7

GND8
CRSV1/D14
CRSV2/A18

CRSV3/D2

RSVD4
RSVD3
RSVD2
RSVD1

SDDAT0
SDDAT1
SDDAT2
SDDAT3

CB712_LFBGA169

G9

MSDATA0
MSDATA1
MSDATA2
MSDATA3

4

CBS_CAD31

B2

CBS_CAD30

C3

CBS_CAD29

B3

CBS_CAD28

A3

CBS_CAD27

C4

CBS_CAD26

A6

CBS_CAD25

D7

CBS_CAD24

C7

CBS_CAD23

A8

CBS_CAD22

D8

CBS_CAD21

A9

CBS_CAD20

C9

CBS_CAD19

A10

CBS_CAD18

B10

CBS_CAD17

D10

CBS_CAD16

E12

CBS_CAD15

F10

CBS_CAD14

E13

CBS_CAD13

F13

CBS_CAD12

F11

CBS_CAD11

G10

CBS_CAD10

G11

CBS_CAD9

G12

CBS_CAD8

H12

CBS_CAD7

H10

CBS_CAD6

J11

CBS_CAD5

J12

CBS_CAD4

K13

CBS_CAD3

J10

CBS_CAD2

K10

CBS_CAD1

K12

CBS_CAD0

L13

CBS_CC/BE3#

B7

CBS_CC/BE2#

A11

CBS_CC/BE1#

E11

CBS_CC/BE0#

H13

CBS_CRST#

B9

CBS_CFRAME#

B11

CBS_CIRDY#

A12

CBS_CTRDY#

A13

CBS_CDEVSEL#

B13

CBS_CSTOP#

C12

CBS_CPERR#

C13

CBS_CSERR#

A5

CBS_CPAR

D13

CBS_CREQ#

B8

CBS_CGNT#

C11

CBS_CCLK

B12

CBS_CSTSCHNG

C5

CBS_CCLKRUN#

D5

CBS_CCLK_INTERNAL

D11

CBS_CINT#

D6
M9

B5

CBS_CCD2#_INTERNAL

A4

CBS_CCD1#_INTERNAL

L12

CBS_CVS2

D9

CBS_CVS1

C6

D3
H2
L4
M8
K11
F12
C10
B6

CBS_RSVD/D14

J13

CBS_RSVD/A18

E10

CBS_RSVD/D2

A2

H6
J7
J6
J5

SDDAT0

E6

SDDAT1

F7

SDDAT2

F5

SDDAT3

G6

R377 47_0402_5%

CBS_SPK#

CBS_CAUDIO

3

+3V

12

12

R60

8.2K_0402_5%

SD_EN#

MS_EN#

+3V

10U_0805_10V4Z

2

1

1

2

C344

C351

CBS_CBLOCK#

12

R440100K_0402_5%

12

CBS_SPK# <30>

0.1U_0402_16V4Z

MSDATA0
MSDATA3
MSDATA2
MSDATA1

D2

RB751V_SOD323

D3

RB751V_SOD323

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

2

2

C376

C324

+3V

@

MSBS

R432 43K_0402_5%
R419 43K_0402_5%
R402 43K_0402_5%
R414 43K_0402_5%
R431 43K_0402_5%

CBS_CCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3V

R61

8.2K_0402_5%

1

2

C381

R358

C322

12

21

21

+CBS_VCC

+CBS_VPP +CBS_VPP

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

2

2

C325

C382

CBS_CCD2#
CBS_CCD1#

0_0402_5%

R400
0_0402_5%

1 2

1 2

@

270P_0402_50V7K

C361

270P_0402_50V7K

2

2

1

1

12
12
12
12
12

12

R83
0_0402_5%

1

@

C95
10P_0402_25V8K

2

@

2005/03/01 2006/03/01

+12VALW

12

R62

8.2K_0402_5%

+CBS_VCC

R116

@

0.01U_0402_16V7K

1

2

C360

C368
10P_0402_25V8K

R63

8.2K_0402_5%

13

D

Q2

2

AO3400_SOT23

G

S

12

12

47K_0402_5%

R122

47K_0402_5%

0.01U_0402_16V7K

1

2

C338

+SD_VCC

CBS_CCD2# CBS_CCD1#

1

2

@

Compal Secret Data

2

G

1

C78

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

1

C143
10P_0402_25V8K

2

@

Deciphered Date

2

+3V

13

D

Q3
AO3400_SOT23

S

+SD_VCC

1

C96

2

JCBS1

1

GND

2

D3

3

D4

4

D5

5

D6

6

D7

7

CE1#

8

A10

9

OE#

10

A11

11

A9

12

A8

13

A13

14

A14

15

WE#

16

IREQ#

17

VCC

18

VPP1

19

A16

20

A15

21

A12

22

A7

23

A6

24

A5

25

A4

26

A3

27

A2

28

A1

29

A0

30

D0

31

D1

32

D2

33

IOIS16#

34

GND

SUPER_AC4-3000-250-3_RT

1 2
1 2
1 2
1 2
1 2

SDDAT2
SDCMD

R45443K_0402_5%

SDDAT0

R46843K_0402_5%

SDDAT3

R49543K_0402_5%

SDDAT1

R46343K_0402_5%
R50043K_0402_5%

Footprint need to change for #3 <-->#13

+3V

2

+12V

1

C407

0.1U_0603_50V4Z

1

2

GND

CD1#

CE2#

VS1#
IORD#
IOWR#

VCC

VPP2

VS2#

RESET

WAIT#

REG#

SPKR#

CD2#

GND

2

0.1U_0402_16V4Z

+3V

0.1U_0402_16V4Z

C389

1

2

35
36
37

D11

38

D12

39

D13

40

D14

41

D15

42
43
44
45
46

A17

47

A18

48

A19

49

A20

50

A21

51
52
53

A22

54

A23

55

A24

56

A25

57
58
59
60
61
62
63
64

D8

65

D9

66

D10

67
68

12
12

+5V

C386

INPACK#

STSCHG#

R505 43K_0402_5%
R439 43K_0402_5%

1

U30

9

12V

5

5V

6

5V

3

3.3V

4

3.3V
GND

7

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#

SDDAT1
SDDAT0

SDCLK

SDCMD
SDDAT2

MSBS
MSDATA1
MSDATA0
MSDATA2
MSINS#
MSDATA3
MSCLK
SDDAT3

SDWP#
SDCD#

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

VCCD0
VCCD1

VPPD0
VPPD1

SHDN

16

+SD_VCC

13

VCC

12

VCC

11

VCC

10

VPP

1
2
15
14

8

OC

CP2211C1_SSOP16

+3V

+CBS_VCC

SDCLK

MSCLK

CBS_VCCD0#
CBS_VCCD1#
VPPEN0
VPPEN1

R481

1 2

0_0402_5%

@

R466

1 2

0_0402_5%

@

SD_8
SD_7
SD_6
SD_5
SD_4
SD_3
SD_2
SD_1
SD_9

MS_1
MS_2
MS_3
MS_4
MS_5
MS_6
MS_7
MS_8
MS_9

MS_10

SD_WP

SD_CD

1

+CBS_VPP

R490

+CBS_VCC

C427

0.1U_0402_16V4Z

C414

1

2

+CBS_VCC

12

12

R462

47K_0402_5%

47K_0402_5%

@

C451

1 2

10P_0402_25V8K

@

C402

1 2

10P_0402_25V8K

@

SD/ MMC/ MS

JSD1

SD_8
SD_7
SD_6
SD_5
SD_4
SD_3
SD_2
SD_1
SD_9

MS_1

22

GND

MS_2

23

GND

MS_3
MS_4
MS_5
MS_6
MS_7
MS_8
MS_9
MS_10

SD_WP
SD_CD

PROCO_MDR019-20-1000

of

26 52

0.1U_0402_16V4Z

1

2

5

+3VS

0.1U_0402_16V7K

1

1

C129

2

2

0.1U_0402_16V7K

D D

1

C149

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C138

2

1

C146

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C147

C125

2

1

C142

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C117

2

4

1

C148

0.1U_0402_16V7K

2

+3VS

3

2

U11

1

A0

2
3
4

VCC

A1

WP

SCL

A2

SDA

GND

AT24C02N-10SI-2.7_SO8

8
7

1394SCL

6

1394SDA

5

+3VS

R150

1

510_0402_5%

12

1 2

1 2

TPB0-

TPB0+

TPA0-

TPA0+

54.9_0402_1%
R94

+3VS

R108
2K_0402_5%

@

1 2

XCPS

12

R113
1K_0402_5%

C101

J139A1
SUYIN_020204FR004S506ZL

1
2
3
4

1
2
3
4

GND15GND26GND37GND4

8

CLK_33M_1394

C C

B B

12

R102
22_0402_5%

@

1

C102
15P_0402_50V8D

2

@

PCI_AD[0..31]<19,24,26,28>

PCI_C_BE0#<19,24,26,28>
PCI_C_BE1#<19,24,26,28>
PCI_C_BE2#<19,24,26,28>

PCI_AD16

PCI_C_BE3#<19,24,26,28>

R115 100_0402_5%

1 2

PCI_FRAME#<19,24,26,28>
PCI_IRDY#<19,24,26,28>
PCI_TRDY#<19,24,26,28>
PCI_DEVSEL#<19,24,26,28>
PCI_STOP#<19,24,26,28>
PCI_PERR#<19,24,26,28>
PCI_PAR<19,24,26,28>
PCI_REQ2#<19>
PCI_GNT2#<19>
PCI_PIRQE#<19>
PCIRST#<19,24,26,28,32>
CLK_33M_1394<18>

46

110

122

111

21

VCC

VCC5VCC17VCC32VCC

VCC

30

VCC

+3VS

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

1394_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_REQ2#
PCI_GNT2#

U12

25

AD0

24

AD1

20

AD2

19

AD3

18

AD4

16

AD5

15

AD6

14

AD7

11

AD8

10

AD9

9

AD10

8

AD11

7

AD12

4

AD13

3

AD14

2

AD15

117

AD16

116

AD17

115

AD18

114

AD19

113

AD20

109

AD21

107

AD22

106

AD23

103

AD24

102

AD25

101

AD26

98

AD27

97

AD28

96

AD29

95

AD30

94

AD31

12

CBE0#

1

CBE1#

119

CBE2#

104

CBE3#

105

IDSEL

120

FRAME#

121

IRDY#

123

TRDY#

124

DEVSEL#

125

STOP#

127

PERR#

128

PAR

93

REQ#

92

GNT#

88

INTA#

89

PCIRST#

90

PCICLK

PCI Bus

NC45NC48NC49NC50NC37NC51NC52NC53NC54NC40NC39NC35NC74NC75NC76NC77NC78NC64NC81NC82NC83NC84NC85I2CEN43CARDEN

NC41NC

42

PVD36PVD

VCC99VCC

Power

IEEE 1394

VT6301S

NC

31

GND47GND

44

R133

4.7K_0402_5%

1 2

100

108

GND91GND

GND

118

126

112

38

GND

GND

GND6GND13GND23GND33GND

GND22GND

59

PVA

62

PVA

72

PVA

73

PVA

86

PVA

87

PVA

61

GND

65

GND

66

GND

79

GND

80

GND

56

GND

26

EECS

EEPROM
I/F

PM & Test

OSC

57

PHYRESET#

XO

XI

58

1394 Differential Pairs

27

EEDO

28

EEDI/SDA

29

EECK/SCL

34

PME#

60

XCPS

63

XREXT

67

TPB0M

68

TPB0P

69

TPA0M

70

TPA0P

71

TPBIAS0

55

C122

VT6301S-CD_LQFP128

24.576MHz_16P_3XG-24576-43E1

1394SDA
1394SCL

Y2

1 2

0.1U_0402_10V6K

XCPS

R107

6.34K_0603_1%

12

0.1U_0402_10V6K

12

R118
1M_0402_5%

1

C107

2

0.1U_0402_10V6K

+3VS

R723

@

1 2

4.7K_0402_5%

ICH_PME# <19,24,26,28,31,32>

1 2

1 2

C118

1 2

10P_0402_50V8J

C124

1 2

10P_0402_50V8J

0.1U_0402_10V6K

1

C119

2

C112

47P_0402_25V8K

+3VS

L12
0_0805_5%

1 2

1

1

2

C106

C116

0.1U_0402_10V6K

2

1 2

54.9_0402_1%

1 2

R93

54.9_0402_1%
R98

1 2

54.9_0402_1%
R99

1 2

1 2

270P_0402_50V7K

4.99K_0402_1%
R89

0.33U_0603_10V7K

C98

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

27 52

5

D D

C C

B B

CLK_33M_MPCI

R319
10_0402_5%@

1 2

CK_33M_MINPCI_TERM

2

C295

4.7P_0402_50V8C

@

1

A A

+3VS

2

C297

0.047U_0402_16V4Z

1

2

C298

0.047U_0402_16V4Z

1

HW_RADIO_DIS#<32,33,35>

2

1

4

COEX2_WLAN_ACTIVE<35>

C290

0.047U_0402_16V4Z

HW_RADIO_DIS#

PCI_PIRQH#<19>

CLK_33M_MPCI<18>
PCI_REQ3#<19>

PCI_C_BE3#<19,24,26,27>

PCI_C_BE2#<19,24,26,27>
PCI_IRDY#<19,24,26,27>

CLKRUN#<21,24,26,31,32>
PCI_SERR#<19,24,26>

PCI_PERR#<19,24,26,27>
PCI_C_BE1#<19,24,26,27>

2

C299

0.047U_0402_16V4Z

1

R320
0_0402_5%

+5VS

+5VS

WLAN_ACT1

R801 0_0402_5%

1 2

2

C300

0.047U_0402_16V4Z

1

1 2

PCI_PIRQH#

CLK_33M_MPCI
PCI_REQ3#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

2

C607

0.1U_0402_16V4Z

1

3

+3VS

2

C289

0.047U_0402_16V4Z

1

JMPCI1

112

KEY KEY

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100

101

101

102

103

103

104

105

105

106

107

107

108

109

109

110

111

111

112

113

113

114

115

115

116

117

117

118

119

119

120

121

121

122

123

123

124

QTC_C102A-056B11-01

2

C288

0.047U_0402_16V4Z

1

2

1

+3VS

2
4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

WLAN_ACT2

PCI_PIRQG#

PCIRST#
PCI_GNT3#
SYS_PME#

R312 0_0402_5%

1 2

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3V

2

C291

0.1U_0402_16V4Z

1

2

C287

0.047U_0402_16V4Z

1

PCI_PIRQG# <19>

PCIRST# <19,24,26,27,32>
PCI_GNT3# <19>

ICH_PME# <19,24,26,27,31,32>

R311

10K_0402_5%

12

1 2

100_0402_5%

PCI_AD18

R313

PCI_PAR <19,24,26,27>

PCI_FRAME# <19,24,26,27>
PCI_TRDY# <19,24,26,27>
PCI_STOP# <19,24,26,27>

PCI_DEVSEL# <19,24,26,27>

PCI_C_BE0# <19,24,26,27>

R780

2

C286

0.1U_0402_16V4Z

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8

PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

1

COEX1_BT_ACTIVE <35>

0_0402_5%

+3V

2

C285

0.1U_0402_16V4Z

1

PCI_AD[0..31] <19,24,26,27>

+5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

28 52

A

B

C

D

E

AC97 Codec

1 1

2 2

INT_CD_L<23>
INT_CD_R<23>

3 3

MD_SPK<35>

XTLSEL

LOW

*

Floating

R633
20K_0402_5%

1 2

12

R632

4 4

0_0402_5%@

A

12

R638

6.8K_0402_5%

10U_0805_10V4Z

1 2

R639 6.8K_0402_5%

1 2

R642 6.8K_0402_5%

1 2

R640 20K_0402_5%

1 2

R641 20K_0402_5%

1 2

1 2

R229 2.4K_0402_5%

1 2

R230 10K_0402_5%

CD_GNA

+5VS

U14

4

C574

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

1

1

C240
10U_0805_10V4Z

2

2

C192

1

1

2

2

C210

0.1U_0402_16V4Z

0.1U_0402_16V4Z

For ALC250 disable HW EQ when Headphone plug-in.

R228

0_0402_5%

1 2

C233 0.1U_0402_16V4Z@

C232 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

CD_L_R
CD_R_R
CD_GNA

MIC

1 2

C235 1U_0603_10V4Z

C236

0.01U_0402_16V7K

MONO_IN<30>

IAC_RST#<20>
IAC_SYNC<20>
IAC_SDATO<20>

NBA_PLUG<30>

CD_GNA<23>
MIC<30>

MODE

14.318MHz External

24.576MHz Crystal
or External Colck

12

R299
0_0402_5%

EAPD<30>

B

5

VOUT

6
1
3

GND

C209

0.1U_0402_16V4Z

+VDDA

HP_SENSE

1 2

1 2

C569 1U_0603_10V4Z

1 2

C570 1U_0603_10V4Z

1 2

C568 1U_0603_10V4Z

C_MIC

1 2

C234 1U_0603_10V4Z

C_MD_SPK

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

L18

1 2

0_0805_5%

Issued Date

12

12

+AVDD_AC97

U16

14

AUX_L

15

AUX_R

16

JD2

17

JD1

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

PHONE

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

NC

46

XTLSEL

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC250_LQFP48

+VDDA

1

R222
150K_0603_1%

2

R223
51K_0603_1%

38

AVDD125AVDD2

MONO_OUT/VREFOUT3

(+VDDA~=4.79V)

+VDDA

C219
10U_0805_10V4Z

12
12

XTL_IN

1M_0402_5%@

XTL_OUT

+3VS

12

R292

1

C241

0.1U_0402_16V4Z

2

SHUT DOWN

LEFT
RIGHT

0

0

1

1

C271

C258

10U_0805_10V4Z

2

C276 1000P_0402_50V7K
C268 1000P_0402_50V7K

1 2

C269 4.7U_0805_10V4Z

1 2

C275 4.7U_0805_10V4Z

C577 1U_0805_25V4Z

1 2

R285 22_0402_5%

1 2

R284 22_0402_5%

1 2

12

C259 1000P_0402_50V7K

12

C265 1000P_0402_50V7K

12

R643

0_0402_5%@

If Project need to implement Realtek Power Off CD play function.
It must be supplied power for AVDD(Pin25 & 38) &
VAUX(Pin34) & power off for DVDD(Pin1 & 9).
When AVDD & VAUX powered and DVDD without power,
it will bypass CD_L & CD_R to LINE_OUT_L & LINE_OUT_R.

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

HP_OUT_L
HP_OUT_R

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

AFILT1
AFILT2

VREFOUT

VREF

DCVOL

VREFOUT2

VAUX

SCK
SDA

AVSS1
AVSS2

9

NC

NC

2

0.1U_0402_16V4Z

LINEL

35

LINER

36
37
39
41

6
8
2

3
29
30
28
27
32

31
33
34
43
44

40
26
42

MODE

DVDD(1/9)

VAUX(34)

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

+AUD_VREF

1

C571

4.7U_0805_10V4Z

2

POWER OFF
CD Play

D

When Project need implement Headphone channel output from
Audio Codec pin 39 & 41, it must have another driver to support JD
function to change signal path from LINE_OUT_L & LINE_OUT_R to
HP_OUT_L & HP_OUT_R when headphone insert.

LEFT <30>
RIGHT <30>
MD_MIC <35>

IAC_BITCLK <20,35>
IAC_SDATAI1 <20>

0

1

14.318MHz External

24.576MHz Crystal
or External Colck

1 2

R298
0_0402_5%

NORMAL NORMAL

1

1

0

1

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Date: Sheet

Ra stuff, Rb, Cb, and Xb empty.

Rb, Cb, and Xb stuff, Ra empty.

1 2

R763
0_0402_5%

CLK_14M_CODEC

RaRb

0.1U_0402_16V4Z

Friday, March 11, 2005

12

R297

10_0402_5%@

1

C277

15P_0402_50V8J@

2

1

C257

2

R164 0_0805_5%

R217 0_0805_5%

R694 0_0805_5%

+AUD_VREF

1 2

1 2

1 2

E

CLK_14M_COMPAL <38>

CLK_14M_CODEC <18>

1

C573

4.7U_0805_10V4Z

2

of

29 52

A

1 1

LEFT<29>
RIGHT<29>

+5VAMP

12

R219

10K_0402_5%

2 2

+3V

12

BEEP#<32>

+3V

14

P

I2O

G

SN74LVC125APWLE_TSSOP14

3 3

7

+3V POWER

R258
100K_0402_5%

1

U15A

OE#

3

CBS_SPK#<26>

R232

8.2K_0402_5%

1 2

VOL_AMP

(0.65V -> 10dB )

12

R625

1.5K_0402_1%

+3V

14

1

1

+3V POWER

C567

7

0.22U_0603_10V7K

2

+3V

1 2

C554

0.1U_0402_16V4Z
U35A
SN74LVC14APWLE_TSSOP14

P

O2I

G

1 2

C566
1U_0603_10V4Z

1 2

C565
1U_0603_10V4Z

14

P

SPKR<21>

4 4

3

4

O

I

G

+3V POWER

7

U35B
SN74LVC14APWLE_TSSOP14

1 2

C563
1U_0603_10V4Z

B

Pin 2

NBA_PLUG<29>

0.47U_0603_16V4Z

LEFT
RIGHT

0.47U_0603_16V4Z

fo=1/(2*3.14*R*C)=260Hz
R=1.3K / C=0.47U

R635

560_0402_5%

1 2

R630

560_0402_5%

1 2

R628

560_0402_5%

1 2

R627
10K_0402_5%

2

B

12

+5VS

HIGH

PIN 6,20 ACTIVE

LOW PIN 5,23 ACTIVE

INTSPK_L1
INTSPK_R1

1 2
1 2

C556

+VDDA

12

R231
10K_0402_5%

12

R225

10K_0402_5%

1

C

Q10
2SC2411K_SC59

E

3

D19
RB751V_SOD323

2 1

LEFT_1
RIGHT_1

12

1

2

12

C557

R624

1.3K_0603_5%

L16

1 2

0_0805_5%

NBA_PLUG
VOL_AMP

C553

0.47U_0603_16V4Z

1 2
1 2

C552

1 2
1 2

1 2

R226

2.4K_0402_5%

0.47U_0603_16V4Z

HP_L
HP_R

1

2

MONO_IN

C239
1U_0603_10V4Z

C212 0.47U_0603_16V4Z

C213 0.47U_0603_16V4Z

R623

1.3K_0603_5%

C224
10U_0805_10V4Z

1 2

C

LEFT_2
RIGHT_2

C558

0.1U_0402_16V4Z

INTSPK_R1

INTSPK_L1

+5VAMP

W=40Mil

1

C548

0.1U_0402_16V4Z

2

18
19

21
23
20
17

1

C546

0.047U_0603_16V7K

2

C555
150U_D2_6.3VM

1 2

+

1 2

+

C564
150U_D2_6.3VM

C547

1

4.7U_0805_10V4Z

2

U34

7

PVDD

SHUTDOWN#

PVDD

SE/BTL#

VDD

PC-BEEP

2
3
4

5
6

INTSPK_R1-2
INTSPK_L1-2

MONO_IN <29>

BYPASS
HP/LINE#
VOLUME
LOUT+
ROUT+
LLINEIN
RLINEIN
LHPIN
RHPIN

CLK

TPA0232PWP_TSSOP24

1 2
1 2

LOUT-

ROUT-

LIN

RIN

GND
GND
GND
GND

R218
47_0402_5%

R221
47_0402_5%

MIC<29>

22
15
14
11
9
16
10
8

1
12
13
24

INTSPK_R1-3
INTSPK_L1-3

SHUTDOWN#

2

C561
1U_0603_10V4Z

1

(0.47U~1U)

L15
FBM-11-160808-700T_0603
L17

FBM-11-160808-700T_0603

MIC

D

+5VAMP

12

R617
100K_0402_5%

Q40

13

D

2N7002_SOT23

2

G

+5VAMP

S

NBA_PLUG

INTSPK_L2
INTSPK_R2

2

C559

1

0.47U_0603_16V4Z

1 2
1 2

1 2

L29
FBM-11-160808-700T_0603

1 2

1 2

C549 0.1U_0402_16V4Z

2

C560

1

0.47U_0603_16V4Z

INTSPK_R1-4
INTSPK_L1-4

C226

330P_0402_50V7K

2.2K_0402_5%

R220
100K_0402_5%

NBA_PLUG

1

2

R645

INTSPK_L1
INTSPK_L2
INTSPK_R1
INTSPK_R2

1

C211
330P_0402_50V7K

2

12

12

R671

2.2K_0402_5%

1

C572
220P_0402_50V7K

2

EAPD <29>

1

C162

2

22P_0402_25V8K

@

AMP_1-1470184-2

CS
CN

1
3
4
5

JHP1

1 2

R644 0_0402_5%

AMP_1-1470184-2

CS
CN

1
3
4
5

JMIC1

C161

@

1

2

E

1

C160

C159

2

22P_0402_25V8K

22P_0402_25V8K

@

@

+AUD_VREF

JSPK1

1

1

2

2

3

3

4

4

ACES_85205-0400

1

2

22P_0402_25V8K

EXT.
MICPHONE

JACK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

D

Date: Sheet

E

of

30 52

A

B

C

D

E

FIR Module

CLK_14M_SIOCLK_PCI_SIO

12

R403
10_0402_5%

@

1 1

LPC_LAD[0..3]<20,32>

LPC_LFRAME#<20,32>

+3VS

2 2

GPIO11 1= 4E 0=2E

3 3

4 4

LPC_LDRQ1#<20>
PLTRST_SIO#<19>

CLKRUN#<21,24,26,28,32>

CLK_33M_LPCSIO<18>

SIRQ<21,26,32>

+3VS +3VS

ICH_PME#<19,24,26,27,28,32>
CLK_14M_SIO<18>

12

R398
10K_0402_5%

12

R401
10K_0402_5%

SIRQ

@

SIO_GPIO11

R383
10K_0402_5%

R415

LPC_LAD[0..3]

SIO_PD#

+5V_PRN

FD7
FD6
FD5
FD4

U27

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

LPC I/F

GPIO

POWER

SERIAL I/F

FIR

IRMODE/IRRX3

PARALLEL I/F

109876

12345

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ1#

PLTRST_SIO#

10K_0402_5%

PM_CLKRUN#

CLK_PCI_SIO

SIO_PME#

CLK_14M_SIO

12

R393
10K_0402_5%

SIO_SMI#

12

+5V_PRN +5V_PRN

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

RP9

109876

12345

2.7K_1206_10P8R_5%

RXD1
TXD1

DSR1#

RTS1#
CTS1#
DTR1#

RI1#

DCD1#

IRRX2

IRTX2

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE

BUSY

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

RP8

2.7K_1206_10P8R_5%

@

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

1

2

+5V_PRN

AFD#/3M#
FD0
LPTERR#
FD1

FD3
LPTSLCTIN#
FD2
LPTINIT#

C369
18P_0402_50V8K

IRRX
IRTXOUT
IRMODE

INIT#
SLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

12

@

1

@

2

C331
1U_0603_10V4Z

1

1

2

2

C326
1U_0603_10V4Z

R380
10_0402_5%

C343
10P_0402_25V8K

+3VS

INIT# LPTINIT#

1 2

R323 33_0402_5%

18
27
36
45

LPTSLCTIN#SLCTIN#

RP7

18
27
36
45

33_0804_8P4R_5%

1 2

R324 33_0402_5%

RP1

LPD0 FD0
LPD1 FD1
LPD2 FD2
LPD3

33_0804_8P4R_5%

LPD4
LPD5
LPD6
LPD7 FD7

Parallel Port

FD3

FD4
FD5
FD6

+5VS

LPTSTB#
AFD#/3M#

LPTAFD#
FD0

LPTERR#
FD1
LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

1

C145

2

10U_0805_10V4Z

D1

2 1

RB420D_SOT23

R1
33_0402_5%

1 2

R327
33_0402_5%

1 2

+3VS

1 2
1

2

+5V_PRN

R152
47_1206_5%

+IR_3VS

(30mil)

C144

0.1U_0402_16V4Z

R2

2.2K_0402_5%

FOX_DZ11391-H7

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

JP1

IRRX

12

R381
10K_0402_5%

C7
220P_0402_25V8K

27
26

(60mil)

+3VS

1

C337
1U_0603_10V4Z

2

2
4
6
8

R138

4.7_1206_5%

1 2
1 2

R137

4.7_1206_5%

U10

IRED_C
RXD
VCC
GND

IR_VISHAY_TFDU6101E-TR4_8P

PCB Footprint : TFDU6101E

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

AFD#/3M#

C611 220P_0402_25V8K

FD0
LPTERR#

C613 220P_0402_25V8K

FD1

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7

1

IRED_A

3

TXD

5

SD/MODE

7

MODE

1 2

C612 220P_0402_25V8K

1 2

1 2

C614 220P_0402_25V8K

1 2

C615 220P_0402_25V8K

1 2

C616 220P_0402_25V8K

1 2

C617 220P_0402_25V8K

1 2

C618 220P_0402_25V8K

1 2

C619 220P_0402_25V8K

1 2

C620 220P_0402_25V8K

1 2

C621 220P_0402_25V8K

1 2

C622 220P_0402_25V8K

1 2

C623 220P_0402_25V8K

1 2

C624 220P_0402_25V8K

1 2

C625 220P_0402_25V8K

1 2

C626 220P_0402_25V8K

1 2

+IR_ANODE

(60mil)

IRTXOUT
IRMODE

1 2

R154 0_0402_5%

Reserved

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

D

Date: Sheet

E

of

31 52

A

+3VALW

12

L31
0_0603_5%

+EC_AVCC

1 1

+3VALW

1 2

C591

0.1U_0402_16V4Z

12

R720
47K_0402_5%

ECRST#

1

C610

0.1U_0402_16V4Z

2

ECAGND

Reserved for 87591L

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

R793

R712

4.7K_0402_5%

10

E&T_96212-1011S

@

+5VS

+5VALW

12

12

R794
0_0402_5%

@

10K_0402_5%

GATEA20<20>

KBRST#<20>

+5VALW

12

R713

4.7K_0402_5%

R714

12

4.7K_0402_5%

2 2

0_0402_5%

3 3

4 4

L30

1 2

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

ECDEBUG

SCROLLLOCK#

EN_WOL#

PSCLK1<33>
PSDAT1<33>

12
12
12
12

1 2

R696 10K_0402_5%

1 2

R695 10K_0402_5%

+3VS

R715
10K_0402_5%

1 2

1 2

GATEA20

12

12

R709

A

0_0603_5%

@

+3VS

R79510K_0402_5% @
R79610K_0402_5% @
R79710K_0402_5%
R79810K_0402_5%

PSCLK3
PSDAT3

R710

4.7K_0402_5%

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

1 2

R718 10K_0402_5%

CLK_33M_LPCEC<18>

C609

1 2

15P_0402_50V8D

@

+3VALW

R730 0_0402_5%@

1 2

R731 0_0402_5%@

1 2

PSCLK2

R732 0_0402_5%
R733 0_0402_5%

PSDAT1T HW_RADIO_LED#
PSCLK2
PSDAT2

PSDAT2

1 2
1 2

1 2

R803 0_0402_5%

1 2

R706

@

Y3

1

32.768KHZ_12.5PF_6HT3

C602

10P_0402_50V8J

2

LFRAME#

1 2

R719 33_0402_5%

@

HW_RADIO_DIS#PSCLK1T

R80210K_0402_5%

12

20M_0402_5%

12

1

2

R708

C601
10P_0402_50V8J

PSCLK1T
PSDAT1T
PSCLK2
PSDAT2
PSCLK3
PSDAT3

CRY1

CRY2

0_0603_5%

SIRQ<21,26,31>

12

B

R753 0_0402_5%

1 2

KSI[0..7]<33>
KSO[0..15]<33>

HW_RADIO_DIS# <28,33,35>

HW_RADIO_LED# <33>

PAD_LOCK#<33>

SLP_S3#<21>
LID_SWOUT#<21>
SLP_S5#<21>

LID_SW#<33>

ICH_PME#<19,24,26,27,28,31>

Close to RTC pad

B

PCIRST#<19,24,26,27,28>

SMB_EC_DA2<16,34>
SMB_EC_CK2<16,34>
SMB_EC_DA1<33,38,39>
SMB_EC_CK1<33,38,39>

SCROLLLOCK#<33>
PWR_LED#<33>
NUMLOCK#<33>
CHARGE_LED#<33>
BATT_LED#<33>
CAPLOCK#<33>

SYSON<37,42>
RSMRST#<21>

BKOFF#<16>

EC_SMI#<21>

SUSP#<16,24,33,37,42>
PWRBTN_OUT#<21>

+3VALW

LPC_LAD[0..3]<20,31>

LPC_LFRAME#<20,31>

EC_SCI#<21>
CLKRUN#<21,24,26,28,31>

0.1U_0402_16V4Z

1

C604

2

0.1U_0402_16V4Z

ECRST#

PROPRIETARY NOTE

1

C608

2

C

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

LPC_LAD[0..3]

GATEA20
KBRST#

LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

PCIRST#
ECRST#
EC_SCI#
PM_CLKRUN#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
EC_TCK

EC_TDO

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

ECDEBUG
SCROLLLOCK#

EC_SMI#

CRY1
CRY2

1

C596

2

U37

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C592

1000P_0402_50V7K

1

C606

2

Host

INTERFACE

key Matrix

scan

C

+EC_AVCC

26

105

75

127

141

11

VCC/ EC VCC

SM BUS

GND

129

139

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

VCC

VCC

VCC / EC VCC

GND

AD BID0/AD3/GPIO3B

VCC / EC VCC37VCC / EC VCC

EC_AVCC / AVCC
DAC_BRIG/DA0/GPIO3D

PWR

EN DFAN1/DA1/GPIO3D
EN DFAN2/DA3/ GPIO3F

DA output or GPO

FAN/PWM

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Data
BUS

Address

BUS

ECTHERM#/GPIO11

GND13GND28GND39GND

AGND

77

103

ADP_I/AD2/GPIO3A

PCMRST#/GPIO1E

ECAGND

2005/03/01 2006/03/01

ECAGNDM/B_ID

C598

1 2

0.01U_0402_16V7K

ECAGNDBATT_TEMP

C600

1 2

0.01U_0402_16V7K

ECAGNDBATT_OVP

C597

1 2

0.01U_0402_16V7K

AD INtput or GPI

IREF2/DA2

PSCLK1

PSDAT1

PSCLK2

PSDAT2

PSCLK3

PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB3/ D3

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ONOFF/GPIO18

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

KB910L A1_LQFP144

Compal Secret Data

Deciphered Date

BATT_TEMP

71

BATT_OVP

72

M/B_ID

73
74

76
78
79

ICH_PWRGD

80

25
27

ICH_BATLOW#

30
31
32
33

PSCLK1T

91

PSDAT1T

92

PSCLK2

93

PSDAT2

94

PSCLK3

95

PSDAT3

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98
84

97
135
136
144

41
43
29
36

SLP_S4#

45
46

MSEN#

81
82
83

THERMATRIP_VGA#

137
142
143

D

D

+3VALW

12

R704
100K_0603_5%

M/B_ID

12

R705
13K_0603_5%

BATT_TEMP <39>
BATT_OVP <40>
M/B_ID
USER_BTN2# <33>

DAC_BRIG <16>
EN_FAN1 <34>

IREF <40>

ICH_PWRGD <21>

INVT_PWM <16>

BEEP# <30>

ICH_BATLOW# <21>

ACOFF <40>

FAN1SPD <34>

BIA <10,16>

ADB[0..7]
KBA[0..19]

+VCCP_PWRGD <42>

COMPAL_INT# <38>
FRD# <33>
FWR# <33>
FSEL# <33>

EC_ON <33>

ACIN <21,40,41>

EC_THRM# <21>

ON/OFF <33>

SLP_S4# <21>

USER_BTN1# <33>

MSEN# <17>
FSTCHG <40>
VR_ON <37,45>

PROCHOT# <5>

Pin8, 22, 54, 82, 84, 89 and 172 is diffrence define with 87591
R181, R191, R192 and R193 are reserved for KB910.
R187 & R176 are reserced for 87591L
BTDIS# signal is reservedfor BT modula,
BTON# signal is reserved for MDC\BT module

1

2

0.1U_0402_16V4Z

ADB[0..7] <33>
KBA[0..19] <33>

THERMATRIP_VGA# <16>

Title

Size Document Number Rev

Custom

Date: Sheet

C599

M/B Ver.

Voltage

BORAD ID

USER_BTN2#
USER_BTN1#

0.1

0.0 0.4 0.8 1.2

R734 10K_0402_5%

1 2

R735 10K_0402_5%

1 2

KBA1
KBA2
KBA3
KBA5

MSEN#

FSEL#
FRD#

R300 10K_0402_5%
R302 10K_0402_5%

EC_SMI#

R707 10K_0402_5%

For KB910

PCIRST#

EC_TINIT#

R701 100K_0402_5%

<Title>

LA-2362 1

Friday, March 11, 2005

E

0.2

1 2

R700 10K_0402_5%

1 2

R699 10K_0402_5%

1 2

R698 10K_0402_5%

1 2

R697 10K_0402_5%

For NS 87591L

R259

1 2

100K_0402_5%

+3VALW

1 2
1 2

1 2

R711

1 2

100K_0402_5%

1 2

32 52

E

1.6

+3VALW

@
@
@

of

+3VALW

+3VALW

A

KSI[0..7]<32>
KSO[0..15]<32>

JP2

KSI1

1

KSI7

2

KSI6

3

KSO9

4

KSI4

5

KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6

KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ACES_85203-2402

1 1

KSI[0..7]
KSO[0..15]

KeyBoard

25

2

26

3

27

4

28

5

29

6

30

7

31

8

32

9

33

10

34

11

35

12

36

13

37

14

38

15

39

16

40

17

41

18

42

19

43

20

44

21

45

22

46

23

47

24

48

KSI7

26

KSI6

27

KSO9

28

KSI4

29

KSI5

30

KSO0

31

KSI2

32

KSI3

33

KSO5

34

KSO1

35

KSI0

36

KSO2

37

KSO4

38

KSO7

39

KSO8

40

KSO6

41

KSO3

42

KSO12

43

KSO13

44

KSO14

45

KSO11

46

KSO10

47

KSO15

48

KSI1

25

1

100P_0402_25V8K

1 2

C164

C165 100P_0402_25V8K

1 2

C166 100P_0402_25V8K

100P_0402_25V8K

1 2

C169 100P_0402_25V8K

C168

1 2

C170 100P_0402_25V8K

100P_0402_25V8K

1 2

C172

C173 100P_0402_25V8K

1 2

C174 100P_0402_25V8K

100P_0402_25V8K

1 2

C177 100P_0402_25V8K

C176

1 2

C178 100P_0402_25V8K

100P_0402_25V8K

1 2

C181 100P_0402_25V8K

C180

1 2

C182 100P_0402_25V8K

100P_0402_25V8K

1 2

C185 100P_0402_25V8K

C184

1 2

C186 100P_0402_25V8K

1 2

C167 100P_0402_25V8K

1 2

1 2

C171 100P_0402_25V8K

1 2

1 2

C175 100P_0402_25V8K

1 2

1 2

C179 100P_0402_25V8K

1 2

1 2

C183 100P_0402_25V8K

1 2

1 2

C187 100P_0402_25V8K

1 2

B

Killer switch

DS-1208_3P

3

+3V

12

R306

100K_0402_5%

SW2

11223

DAN217_SC59

C

+3V

2

3

@

D6

1

HW_RADIO_DIS#

HW_RADIO_DIS# <28,32,35>

1

SPPB530600_4P

EC_ON<32>

SW1

D

2
43

EC_ON

LID_SW#

ON/OFFBTN#

+3VALW

12

R347

22K_0402_5%

R726 10K_0402_1%

1 2

D14

1

DAN202U_SC70

R349
22K_0402_5%

1 2

2

LID_SW# <32>

+3VALW

12

ON/OFF

3
2

Q27
DTC124EK_SC59

13

R346
100K_0402_5%

1

2

C319

1000P_0402_50V7K

E

Power BTN

ON/OFF <32>
51ON# <44>

12

D13

RLZ20A_LL34

+5VS +5VS

2 2

PSDAT1<32>
PSCLK1<32>

SMB_EC_CK1<32,38,39>
SMB_EC_DA1<32,38,39>

3 3

4 4

T/P

JTP1

1 7
2 8
3 9
4
5
6

ACES_85203-0602

+5VALW

1 2

+3VALW

1 2

R304 0_0603_5%

10
11
12

C284

0.1U_0402_16V4Z

U19

8

VCC

7

WP

6

SCL

5

SDA

GND

AT24C16N-10SI-2.7_SO8

+3VBIOS

1

A0

2

A1

3

A2

4

1

2

C282

0.1U_0402_16V4Z

+5VALW

12

R309
100K_0402_5%

12

R305
100K_0402_5%

C283
10U_1206_10V4Z

1

2

PSDAT1 <32>
PSCLK1 <32>

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5

+3VALW

+3VS

ADB[0..7]
KBA[0..19]

U38

1

A11

2

A9

3

A8

4

A13

5

A14

6

A17

7

WE#

8

VCC

9

A18

10

A16

11

A15

12

A12

13

A7

14

A6

15

A5

16

A4

SST39VF040-70-4C-WH_TSOP32

SW Board

JPSWP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20

SUYIN_80065AR-020G2T

ADB[0..7] <32>
KBA[0..19] <32>

FRD#

32

OE#
CE#

DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0

A10

KBA10

31

FSEL#

30

ADB7

29

ADB6

28

ADB5

27

ADB4

26

ADB3

25
24

ADB2

23

ADB1

22

ADB0

21

KBA0

20

A0

KBA1

19

A1

KBA2

18

A2

KBA3KBA4

17

A3

ON/OFFBTN#
NUM_LED#
SCROL_LED#
CAPS_LED#

R359

FRD# <32>
FSEL# <32>

0_0402_5%

1 2

USER_BTN1# <32>
USER_BTN2# <32>

NUMLOCK# <32>
SCROLLLOCK# <32>
CAPLOCK# <32>
HDD_ACT# <23>

CR_LED# <26>

PAD_LOCK# <32>

+5VALW

PWR_LED#<32>
CHARGE_LED#<32>
BATT_LED#<32>

HW_RADIO_LED#<32>

FWE#

4

TC7SH32FU_SSOP5

HW_RADIO_LED#

U17

+3VALW

O

5

2

P

I0

1

I1

G

3

LED Board

+3VALW

+3VALW

12

R301
100K_0402_5%

JLED1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACES_85205-0800

2

1 3

D

Q15
2N7002_SOT23

9

9

10

10

G

S

FWR# <32>

SUSP# <16,24,32,37,42>

EC_FLASH# <21>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

D

Date: Sheet

E

of

33 52

5

D D

C C

4

3

+3VS

+3VALW

H_THERMDA

H_THERMDC

R799 0_0402_5% @

1 2

R800 0_0402_5%

1 2

1

C141
2200P_0402_50V7K

2

SMB_EC_CK2
SMB_EC_DA2

8.2K_0402_5%

R136

12

12

R140

8.2K_0402_5%

H_THERMDA<5>

H_THERMDC<5>

SMB_EC_CK2<16,32>
SMB_EC_DA2<16,32>

2

U9

2

D+

3

D-

8

SCLK

7

SDATA

ADM1032ARM_RM8

0.1U_0603_25V7M

1

VDD1

6

ALERT#

4

THERM#

5

GND

C132

+3VS

1

1

12

2

R149
10K_0402_5%

+5VS

+5VALW

12

12

R808
0_0603_5%

@

6

2

1

D

Q41

G

S

SI3456DV-T1_TSOP6

4 5

1

C537

2

22U_1206_16V4Z_V1

2

FAN1_VOUT

1

C155

2

1000P_0402_50V7K

1

0_0603_5%

FAN1_ON

RB751V_SOD323

R807

3

D17

2 1

B B

C

B

E3

2222 SYMBOL(SOT23-NEW)

+5VS

SMB_EC_DA2<16,32>
SMB_EC_CK2<16,32>

A A

SMB_EC_DA2
SMB_EC_CK2

5

U32

1

SDA

2

SCL

3

OS#

4

GND

LM75CIMMX-5_MSOP8

@

VCC

8
7

A0

6

A1

5

A2

1

2

1

C527

0.1U_0402_16V4Z

2

@

1 2

R560 1K_0402_5%

@

4

R622

100K_0402_5%

EN_FAN1<32>

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FAN1VREF
FAN1_VFB

1

C551

2

1U_0603_10V4Z

R616

1 2

150K_0402_5%

2005/03/01 2006/03/01

+12VALW

8

U33A

P

3

+IN

OUT

2

-IN
G

LM358A_SO8

4

C545

2200P_0402_50V7K

1 2

R590

100K_0402_5%

12

Compal Secret Data

Deciphered Date

FAN1 Control and Tachometer

+3VS

+3V

12

R809

10K_0402_5%

12

R810
0_0402_5%

@

FAN1SPDC <38>

R812 0_0402_5%@

1 2

JFAN1

1
2
3

ACES_85205-0300

FAN1

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

Date: Sheet

12

R163

1

C156

0.01U_0402_16V7K

2

FAN1_VOUTC <38>

1

10K_0402_5%@

FAN1SPD <32>

of

34 52

5

4

+3VS

3

12

L32
0_0603_5%

2

1

D D

0.1U_0402_16V4Z

USBP2+<21>

T24

USBP2-<21>

PAD@

COEX1_BT_ACTIVE<28>

HW_RADIO_DIS#<28,32,33>

HW_RADIO_DIS#

COEX2_WLAN_ACTIVE<28>

R804

USB2+

USB2­COEX3
COEX1_BT_ACTIVE

1 2

COEX2_WLAN_ACTIVE

BT_ACTIVE

C C

JP3 ACES_88021-3001

MD_MIC<29>

+3V

IAC_SDATO_MDC<20>

IAC_RST#_MDC<20>

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

AUDIO_PWDN

MONO_PHONE

Bluetooth Enable

GND

USB Data+

USB Data-

PRIMARY DN

GND

AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0

GND

AC97_BITCLK

+5V

5Vd

C605

10K_0402_5% @

2
4
6
8
10
12
14

Definition

16
18
20
22
24
26
28
30

1

2

BT_PWR

JBTP1

1
2
3
4
5
6
7
8
9
10

JST_BM10B-SRSS-TB

@

C562

@

MD_SPK <29>

1 2

R629 10K_0402_5%

1 2

R631 0_0402_5%

R637

1 2

22_0402_5%

11
12

1 2

1 2

R63422_0402_5%

1 2

R6260_0402_5%@

12

0.1U_0402_16V4Z

@

R63622_0402_5%

IAC_BITCLK <20,29>

+5VS

+3V

IAC_SYNC_MDC <20>
IAC_SDATAI2 <20>

1

1

1

H23
HOLEA

1

H6
HOLEA

1

1

1

FM3

@

CF1

@

CF5

@

@

@

1

1

1

H22
HOLEA

1

H5
HOLEA

1

H16
HOLEA

1

H14
HOLEA

1

FM5

@

CF7

@

CF13

@

@

1

1

1

H25
HOLEA

1

H12
HOLEA

1

H15
HOLEA

1

FM4

@

CF4

@

CF12

@

@

@

1

1

1

H24
HOLEA

1

H11
HOLEA

1

H19
HOLEA

1

M1
HOLEA

1

FM6

@

CF10

@

CF16

@

@

1

1

1

H13
HOLEA

H1
HOLEA

H18
HOLEA

1

CF11

@

CF15

@

1

1

CF2

@

1

1

CF14

@

1

1

H3

H4
HOLEA

@

1

H2

HOLEA

HOLEA

@

@

1

1

FM1

FM2

@

@

1

CF9

CF3

@

@

1

CF6

CF8

@

@

1

H10
HOLEA

@

@

1

H7
HOLEA

1

H9

H8

HOLEA

HOLEA

1

H17

H21

HOLEA

HOLEA

@

@

1

H20
HOLEA

@

1

GND131GND232GND333GND434GND535GND6

B B

MDC CONN.

36

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

35 52

A

B

C

D

E

+USB_CS

2

3

1

470P_0402_50V7K

1

+

2

PSOT24C_SOT23
D23

150U_D2_6.3VM

2

@

150U_D2_6.3VM

@

1

C316

@

2

C157

3

PSOT24C_SOT23
D25

1

C24

2

3

1

JUSBP1

1

VCC

2

D0-

3

D0+

4

VSS
G210G1

12

G4

SUYIN_020122MR008S540ZU

470P_0402_50V7K

1

+

2

470P_0402_50V7K

1

+

2

PSOT24C_SOT23
D26

+5VS

U3

1

GND

2

IN

12

12

R345
100K_0402_5%

3

IN

4

EN#

TPS2061IDGN_MSOP8

U13

1

GND

2

IN

3

IN

4

EN#

TPS2061IDGN_MSOP8
R158
100K_0402_5%

U26

1

GND

2

IN

3

IN

4

EN#

TPS2061IDGN_MSOP8

1

1 1

2 2

3 3

C18

0.1U_0402_16V4Z

2

+5VS

1

C154

0.1U_0402_16V4Z

2

+5VS

1

C315

0.1U_0402_16V4Z

2

12

R6
100K_0402_5%

OUT
OUT
OUT
OC#

OUT
OUT
OUT

OC#

OUT
OUT
OUT

OC#

8
7
6

R754 0_0402_5%

5

R755 0_0402_5%

+USB_AS

8
7
6
5

8
7
6
5

1 2
1 2

OVCUR#0 <21> USBP0-<21>

+USB_BS

OVCUR#1 <21>

OVCUR#3 <21>
OVCUR#4 <21>

USBP4-<21>
USBP4+<21>

10P_0402_25V8K

USBP0+<21>

USBP1-<21>
USBP1+<21>

1

C629

2

@

10P_0402_25V8K

10P_0402_25V8K

1

2

@

C627

C26
150U_D2_6.3VM @

C630
10P_0402_25V8K

1

1

2

2

@

@

1

C633

2

@

@

@

C628
10P_0402_25V8K

1

C634
10P_0402_25V8K

2

VCC

D1+
VSS

D1-

G3

1

2

5
6
7
8

9
11

+USB_AS

C528

+USB_BS

1

C312

2

+USB_CS

470P_0402_50V7K

1

C317

2

@

JUSBP2

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

SUYIN_2569AR-04G5T

JUSBP3

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

SUYIN_020173MR004S512ZL

2

3

1

1

+

150U_D2_6.3VM

2

10P_0402_25V8K

PSOT24C_SOT23
D24

C25

C631

USBP3- <21>

1

1

C632
10P_0402_25V8K

2

2

@

@

USBP3+ <21>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01 2006/03/01

C

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

D

Date: Sheet

E

of

36 52

5

4

3

2

1

+3VALW +3VS

Q8

8

S

D

7

S

C221
22U_1206_10V4Z

D D

C222
22U_1206_10V4Z

D

6

D

5

D

AO4422_SO8
C223
10U_1206_10V4Z

S
G

+3VALW to +3V Transfer

Q38

D
D
D
D

AO4422_SO8

@

1

C712

2

10U_1206_10V4Z

1

S

2

S

3

S

4

G

+5VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

1

C713

2

C260

0.01U_0402_16V7K

8
7

R291
100K_0402_5%

R289
1M_0402_5%

Q12
2N7002_SOT23

6
5

C496
10U_1206_10V4Z

C274

C494

10U_1206_10V4Z

C C

SUSP

B B

C495

10U_1206_10V4Z

C273

10U_1206_10V4Z

+12VALW

12

13

D

2

G

S

+3VALW to +3VS Transfer

1
2
3
4

+3V+3VALW

SUSON

C220

22U_1206_10V4Z

RUNON

C449
22U_1206_10V4Z

C225

0.1U_0402_16V4Z

C448

0.1U_0402_16V7K

+5VALW to +5VS Transfer

+5VS

Q13

S

D

S

D

S

D

G

D

AO4422_SO8

RUNON

1
2

0.1U_0402_16V7K

3
4

C264

8
7
6
5

D

S

R407
470_0402_5%

13

D

S

1

2

R224
470_0402_5%

Q9

13

2

2N7002_SOT23

G

SYSON#

Q34

2

G

2N7002_SOT23

C272
22U_1206_10V4Z

SUSP

D

S

R290
470_0402_5%

13

Q11

G

2N7002_SOT23

+3VALW +CPU_CORE

R373

2

G

R619
47K_0402_5%

SUSON

Q43
2N7002_SOT23

R621
1M_0402_5%

S

330_0603_5%

@

13

D

Q30
2N7002_SOT23

@

S

12

1

2

C663

10U_1206_10V4Z

C550

0.01U_0402_16V7K

1

C390

0.1U_0402_16V4Z

2

+5VALW

12

R618
10K_0402_1%

SUSP#

SUSON

Q36

2N7002_SOT23

2

1

2

G

SUSP

13

D

2

G

S

12

R452
100K_0402_5%

R453
51K_0402_5%

13

D

S

Q42
2N7002_SOT23

+12VALW+12VALW

Q37
NDS352AP P-CHANNEL_SOT23

S

G

2

D

1 3

1

C406

4.7U_1206_16V6K

2

+12V

SUSP<16,43,44>

SUSP#<16,24,32,33,42>

+5V

C387

0.1U_0402_16V4Z

R371

@

100K_0402_5%

13

2

G

12

R620
47K_0402_5%

13

D

Q44
2N7002_SOT23

S

SYSON#

SUSON

D

Q31
2N7002_SOT23

@

S

+12VALW

2

G

Q35
AO3400_SOT23

D

1 3

12

13

D

S

G

2

@

2

1

2

3

1

0.1U_0402_16V4Z

2

G

D18
SM05_SOT23

@

@

1

C715

2

VR_ON

+12VALW

0.1U_0402_16V4Z

VR_ON<32,45>

SYSON<32,42>

SUSP

2

C662

10U_1206_10V4Z

+5VALW

C714

+2.5VS+2.5V

Q7

8

S

D

7

S

D

6

S

D

5

G

D

AO4422_SO8
C158
10U_1206_10V4Z

A A

5

+2.5V to +2.5VS Transfer

1
2
3
4

C152
22U_1206_10V4Z

RUNON

C153

0.1U_0402_16V7K

C151

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

Title

<Title>

Size Document Number Rev

LA-2362 1

Custom

Friday, March 11, 2005

2

Date: Sheet

1

of

37 52

5

+5VS

VIN_FAN2

12

1

R764

R767

@

+5VS

@

+5VS
+5VS
+5VS

@

12

C636
1U_0603_10V4Z

2

FAN2_GATE

VIN_FAN1

1

C638

1U_0603_10V4Z

2

FAN1_GATE

@

CLK_14M_COMPAL<29>

R771
R772
R773

FAN2_VOUT1 PAD

1 2

4.7K_0402_5%

1 2

@

4.7K_0402_5%

1 2

@

4.7K_0402_5%

@

FAN1_VOUTC<34>

SMB_EC_CK1<32,33,39>
SMB_EC_DA1<32,33,39>

VIN_LDO1

LDO1EN1 PAD

LDO1EN2 PAD

LDO2EN1 PAD

C641 22U_1206_10V4Z@

12

@

22U_1206_10V4Z

RESET#
SCL
SDA

C642

PAD

@

@
@

@

FAN1SPDC<34>

@

1 2

1

2

C643

0.1U_0402_16V4Z

@

D D

100K_0402_5%

100K_0402_5%

C C

VIN_LDO1
LDO1_FB

LDO1EN
LDO2_FB

FAN1_GATE

VIN_FAN2

FAN2_GATE

RESET#

SCL
SDA

4

U39

1

LDO1_VINA

48

LDO1_VINB

5

LDO1_FB

2

LDO1_EN

12

LDVO2_VINA

13

LDVO2_VINB

8

LDO2_FB

11

LDO2_EN

26

FAN1_VINA

25

FAN1_VINB

24

FAN1_VOUTA

23

FAN1_VOUTB

27

FAN1_GATE

46

FAN1_TACHFB/GPIO8

35

FAN2_VINA

36

FAN2_VINB

37

FAN2_OUTA

38

FAN2_OUTB

34

FAN2_GATE

47

FAN2_TACHFB/GPIO9

45

RESET#

39

CLK14M

40

SCL

41

SDA

@

+5VS

18

6

VCC2/5V

VCC2/5V32VCC2/5V

AVCC1/5V

LDO1

LDO2

charge pump

0.1U_0402_16V4Z

42

LDO1_VOUTB
LDO1_VOUTA

LDO2_VOUTB
LDO2_VOUTA

FAN

VSS1/AGND

CP_OUT

CP_EN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

VSS2(GND)
VSS2(GND)
VSS2(GND)

C644

@

CPP

CPN

INT#

1

2

4

LDO1_VOUT

3

9

LDO2_VOUT

10

29
28
30

@
@

33

14
15
16
17
20
21
22

44
19

31
43
7

+5VS

1

C645

0.1U_0402_16V4Z

2

@

1

C639
1U_0603_10V4Z

2

@

12

R770

4.7K_0402_5%

@

CP_OUTPAD
CP_EN1PAD

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

COMPAL_INT# <32>

+5VS

LDO1_VOUT

R765

LDO1_FB

R766

LDO2_VOUT

R768

LDO2_FB

R769

3

VOUT_LDO1PAD

1

12

12

@

@

C637
22U_1206_10V4Z

2

@

2

1

@

12

12

@

@

C640
22U_1206_10V4Z

2

@

VOUT_LDO2PAD

1

@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/01 2006/03/01

Compal Secret Data

Deciphered Date

2

Title

<Title>

Size Document Number Rev

LA-2362 1

C

Friday, March 11, 2005

Date: Sheet

1

of

38 52

A

1 1

B

C

D

BATT+

12

PC4

560P_0402_50V7K

VIN

12

PR5
10_1206_5%

12

PD30
RLZ24B_LL34

BATT+

12

PC7

0.01U_0402_25V7Z

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

PJPD1

1

2

G
G

3

SINGA_2DC-S756B200

2 2

P1

12

PC1

560P_0402_50V7K

VL

FBM-L18-453215-900LMA90T_1812

1 2

12

PC2

12P_0402_50V8J

PR14

2.2M_0402_5%

VS

PL1

12

12

PC3

12P_0402_50V8J

PL2

HCB4532K-800T90_1812

1 2

12

PJP1

9

G

8

G

SUYIN_200275MR007G113ZL

BATT++

BATT++P1

PC8
1000P_0402_50V7K

1

BATT+

2

ID

3

B/I

4

TS

5

SMD

6

SMC

7

GND

PR18

1K_0402_5%

BATT_TEMP

1 2

PR15

1K_0402_5%

12

1 2

PR21

25.5K_0402_1%

1 2

PR22

100_0402_5%

1 2

PR25

100_0402_5%

BATT_TEMP <32>

+3VALWP

SMB_EC_DA1 <32,33,38>

SMB_EC_CK1 <32,33,38>

B+

3 3

MAINPWRON

0,41,44>

ACON<40>

100K_0402_1%

PD2

2
3

RB715F_SOT323

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

4 4

BATT ONLY

PR16

1

12

12

PC11

0.1U_0603_25V7K

VL

1

O

PR23

34K_0402_1%

LM393M_SO8

8

3

P

+

2

-

G

4

12

66.5K_0402_1%

PU1A

12

PC12

1000P_0402_50V7K

PR26

12

PR17
499K_0402_1%

12

12

PR19

191K_0402_1%

PRG++

RHU002N06_SOT323

PQ1

13

D

2

G

S

13

12

47K_0402_5%

PR24

12

PQ2
DTC115EUA_SC70

2

PR20
499K_0402_1%

PACIN

12

PC10
1000P_0402_50V7K

PACIN <40>

+5VALWP

VIN

PD1

1N4148_SOD80

VIN+

12

PR10

1.5K_1206_5%

1 2

PR11

1.5K_1206_5%

1 2

PR12

1.5K_1206_5%

1 2

PR13

1.5K_1206_5%

1 2

B+

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

SECRET INFORMATION. THIS SHEET MAY NOT BE
TRANSFERRED FROM THE

C

Compal Electronics, Inc.

Title

DCIN & DETECTOR & Precharge

Size Document Number Rev

B

LA-2362

Date: Sheet

D

of

39 52Friday, March 11, 2005

1

A

B

C

D

E

Charger

Iadp=0~3A(65W)

PQ31

AO4407_SO8

47K

2

47K

13

PQ35

DTC115EUA_SC70

1SS355_SOD323

1 2

ACON

22K_0402_5%

1 2

12

8
7

5

1 3

PR162

150K_0402_5%

RHU002N06_SOT323

PQ39

2

G

PD28

PR171

PD31

RLZ4.3B_LL34

VIN

1 1

DTA144EUA_SC70

12

PR158

47K_0402_5%

13

D

2

G

S

PQ37

RHU002N06_SOT323

2 2

PQ34

2

ACOFF#

ACON<39>

PACIN<39>

ACIN <21,32,41>

ACIN

1 2

PR4

3 3

10K_0402_5%

P2

1
2
36

4

12

12

PC141

0.1U_0603_25V7K

12

13

D

PR167

100K_0402_1%

S

PACIN

PR175

158K_0603_1%@

2P4S:4300mAH/cell

0.7C=3.0A

OVP voltage :

LI-3S :17.8V----BATT-OVP=1.9758V

BATT-OVP=0.111*BATT+

4 4

+SDREF

A

PU14B

LM358A_SO8

7

PQ32

AO4407_SO8

1
2
3 6

4

PR159

200K_0402_1%

PC142

1U_0603_10V6K

150K_0402_1%

PR164

12

12

12

PC144

0.1U_0402_16V7K

IREF<32>

PR172

10K_0402_5%

12

PQ40

DTC115EUA_SC70

VS

5

+

0

6

-

12

1908LDO

12

13

8
7

5

9.31K_0402_1%

0_0402_5%@

PR190

+2.5V

12

12

VIN

PR166

12

1908LDO

2

FSTCHG<32>

PACIN

PR191
10K_0402_1%

PR192
10K_0402_1%

B

P3

@

1SS355_SOD323

PD25

12

0_0402_5%

PR168

12

PR173

100K_0402_1%

150K_0402_1%

1 2

PR194

681K_0603_1%

12

PC158

0.1U_0603_25V7K

12

15K_0402_1%

12

0_0402_5%

1 2

100K_0402_5%

PR180

PR157

231
4

0.01_2512_1%

PR184

12

PC149

0.01U_0402_16V7K

PR177

PR193

VIN

12

12

12

12

1 2

PR182
20K_0402_1%

PROPRIETARY NOTE

B+

1

+

12

PC143

0.1U_0603_25V7K
0_0402_5%

0_0402_5%

PR178

1 2

10K_0402_5%

PC14

220U_25V_M

2

PC159

0.1U_0603_25V7K

@

MAX1908ETI_QFN28

1

PR163

12

17

4
3

12

15
13

11

8

10

12

9

PR169

28

7

PR174

1K_0402_1%

1 2

12

PC152

PC154

0.1U_0402_16V7K

12

PC155

0.1U_0402_16V7K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HCB4532K-800T90_1812

1 2

PU13

DCIN

CELLS

REF
CLS

REFIN

VCTL
ICTL

ACOK#
SHDN#
ACIN
ICHG

IINP
CCV

CCI

CCS

6

5

MAX1908-CCS

12

1 2

1000P_0402_50V7K

BATT_OVP<32>

C

PL16

PC153

12

PC138

CSSP

CSSN

DLO

BST

DLOV

LDO

CSIP
CSIN
BATT

PU14A

12

PC139

PC140

4.7U_1206_25V6K

4.7U_1206_25V6K

DHI

LX

1

4.7U_1206_25V6K

ACOFF#

27

26

25

23

21

24

22
2

1908LDO
19
18
16

8

0

4

PC151
1U_0603_10V6K

1 2

BATT+

VS

12

PC156

0.01U_0402_25V7Z

3

P

+

2

-

G

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

1000P_0402_50V7K

1 2

PR1 0_0402_5%

BATT+

12

PR179
845K_0603_1%

12

PR181
300K_0603_0.1%

12

PR183
143K_0402_1%

PQ38

D2
D2
G1

S1/A

12

PC18

12

PR170

33_1206_5%

D

1
2
3
4

12

1 2

0.1U_0603_25V7K

12

PC150
1U_0805_25V4Z

1 2

PC157

0.01U_0402_25V7Z

12

PGND

GND

20

14

1000P_0402_50V7K

LM358A_SO8

PQ33

AO4407_SO8

1
2
3 6

PR161

10K_0402_5%

1 2

16UH_D104C-919AS-160M_3.7A_20%
PC145

PD27
1SS355_SOD323

4

47K_0402_5%

1 2

1 2
13

10K

10K

PQ36

DTC114EKA_SC59

PL17

PR160

2

8
7

5

VIN

12

RLZ22B_LL34@

PD24

1SS355_SOD323@

1 2

1 2

PD26

1SS355_SOD323

PR165

0.015_2512_1%

1 2

PD32

ACOFF<32>

12

PC146

Charge voltage

4S CC-CV MODE : 16.8V

Compal Electronics, Inc.

Title

Charger

Size Document Number Rev

B

LA-2362

Date: Sheet

E

BATT+

4.7U_1206_25V6K

12

12

PC148

PC147

4.7U_1206_25V6K

4.7U_1206_25V6K

1

of

40 52Friday, March 11, 2005

A

B

C

D

E

+3.3V/+5V/+12V

B+

+3VALWP Choke DCR = 26.5mΩ.

Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A
OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A

1 1

PL8

FBM-L18-453215-900LMA90T_1812

1 2

B+++

12

12

PC74

4.7U_1206_25V6K

PC73

2200P_0402_50V7K@

2 2

12

PC81
47P_0402_50V8J

1 2

12

10UH_D104C-919AS-100M_4.5A_20%

+3VALWP

PC85

1

3 3

+

2

150U_D2_6.3VM_R45

PL10

12

1 2

3.57K_0402_1%

1 2

PC84
100P_0402_50V8J

PR104

10K_0402_1%

PD17

PR101

SKUL30-02AT_SMA

2 1

PR94

1M_0402_1%

1.27K_0402_1%

1.27K_0402_1%

1 2

PQ17

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

PR92

PR93

ACIN<21,32,40>

PC71

0.1U_0603_25V7K

1 2

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

LX3

12

0.47U_0603_16V7K
PC82

619_0402_1%

1 2

1 2

PR98

10K_0402_5%

300K_0402_5%@

PR105

0_0402_5%

PR97

VS

12

PR100

12

12

@

DL3

12

PC91
1U_0805_25V4Z

12

PR89
0_0402_5%

DH3

0.1U_0603_25V7K

12

PC86
1000P_0402_50V7K

DAP202U_SOT323

PD15

1SS355_SOD323

PR2

33_1206_5%

12

PC78

PU6

25

BST3

27

DH3

26

LX3

24

DL3

MAX1902EAI_SSOP28

1

CSH3

2

CSL3

3

FB3

10

SKIP#

23

SHDN#

7

TIME/ON5

28

RUN/ON3

12

PC90

2.2U_0805_10V6K

PD14

VS

VL

1 2
12

22

V+

GND

8

MAINPWRON <20,39,44>

2

1

12

ACIN

21

12OUT

VL

BST5

PGND

CSH5
CSL5

SYNC

RST#

3

PC75

4.7U_0805_6.3V6K

PQ41

RHU002N06_SOT323@

4
5

VDD

18
16

DH5

17

LX5

19

DL5

20
14
13
12

FB5

15

SEQ

9

REF

6
11

PR102

0_0402_5%

BST51BST31

0.1U_0603_25V7K
PC72

1 2

+12VALWP

12

PR187

2.7K_1206_5%@

12

D

S

PC162

4.7U_1206_25V6K

12

PC87

4.7U_0805_6.3V6K

13

2

G

1 2

BST5

2.5VREF

PR91

1 2

0_0402_5%

DH5

DL5

PC83

0.47U_0603_16V7K

PQ18

8

G2

D2

7

D2

D1/S2/K

6

G1

D1/S2/K

5

D1/S2/K

S1/A

AO4912_SO8

LX5

12

12

PR99
698_0402_1%

12

PR103

10.2K_0402_1%

12

PR106
10K_0402_1%

PC161
470P_0805_100V7K

@

1 2

12

PR186
22_1206_5%@

B+++

1
2
3
4

12

12

PC76

PC77

2200P_0402_50V7K@

4.7U_1206_25V6K

12

PR96

1.54K_0402_1%

12

PC89
100P_0402_50V8J

SKS10-04AT_TSMA

+5VALWP Choke DCR = 40mΩ.
Current limit Threshold Min.=80 mV Mx.=120mV.

OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A

4 4

OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A
RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

B

Date: Sheet

10U_1210_25V6M

1 2

12

PD29
EC11FS2_SOD106

FLYBACKSNB

1 4

12

PC79
47P_0402_50V8J

12

PR95
2M_0402_1%

PD18

2 1

Compal Electronics, Inc.

3.3V / 5V / 12V

LA-2362

PC160

PL9
10uH_SDT-1205P-100-118_5A_20%

3 2

1

+

2

150U_D2_6.3VM_R45

E

PC88

+5VALWP

41 52Friday, March 11, 2005

0.1

of

5

4

3

2

1

Vin=19V,Vo=2.5V,Io=4.5A,Fs=345KHZ,L=4.7UH
Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =0.6118A
Iimit=ILIM(V)/10/Rds(on)+1/2 delta I
Iimit Min=1.98V*100K/(100K+15K)/10/31.2mΩ+0.3059=5.824A
Iimit Max=2.02V*100K/(100K+15K)/10/19.7mΩ+0.3059=9.821A

D D

+VCCPP = 5.824A ~ 9.821A

12

12

D2
D2
G1
S1/A

D1/S2/K
D1/S2/K
D1/S2/K

PC36

4.7U_1206_25V6K

1

PD7
DAP202U_SOT323

8

G2

7
6
5

12

PC46

0.1U_0603_25V7K

SUSP#<16,24,32,33,37>

4

3

1 2

0_0402_5%

0.01U_0402_25V8K @

2

PR54

0_0402_5%

PR68

PC54

12

0.1U_0603_25V7K

25
26
27

24
28

11

12

PC38

1
2

PU4

12

BST1
DH1
LX1

DL1
CS1

OUT1
FB1

ON1

0.22U_0603_10V7K

1U_0805_25V4Z

PC44

12

4

22

V+

VCC

MAX8743EEI_QSOP28

SKIP

GND

OVP

6

8

23

PC45

PC34

C C

+VCCPP

1

+

PC50

2

B B

10K_0402_1%

A A

4.7UH_D104C-919AS_4R7N_5.2A_20%

12

PC51

12

4.7U_0805_6.3V6K

@

150U_D2_6.3VM_R45

PR64

12

5

PR61
499_0402_1%

PL5

1 2

PC35

1 2

0.1U_0603_25V7K
2200P_0402_50V7K

@

PQ12

1
2
3
4

AO4912_SO8

PR53

20_0603_5%

1 2

9

VDD

UVP

BST2

DH2

LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR58

10

33K_0402_1%

PR59

15K_0402_1%

12

+5VALW

12

PC39

4.7U_0805_6.3V6K

BST2.5B

PR55

0_0402_5%

1 2

BST2.5A

21
19

DH2.5

18
17
20
16

15
14
12

7
5

13
3

12
12

12

PR65

100K_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

SUSP#

PR66

100K_0402_1%

PC47

0.1U_0603_25V7K

12

PD3

RB751V_SOD323

1 2

PC17

1000P_0402_50V7K@

1 2

PR67

0_0402_5%

+3VALWP

1 2

12

PR69
10K_0402_5%

Vin=19V,Vo=2.5V,Io=4.5A,Fs=255KHZ,L=4.7UH
Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =1.8115A
Iimit=ILIM(V)/10/Rds(on)+1/2 delta I
Iimit Min=1.98V*100K/(100K+33K)/10/31.2mΩ+0.905=5.6765A
Iimit Max=2.02V*100K/(100K+33K)/10/19.7mΩ+0.905=8.614A
+2.5VP = 5.6765A ~ 8.614A

PQ13

8
7
6
5

AO4912_SO8

LX2.5

G2
D1/S2/K
D1/S2/K
D1/S2/K

SYSON <32,37>

1

D2

2

D2

3

G1

4

S1/A

DL2.5

+VCCP_PWRGD <32>

2

MAX8743_B+

0.1U_0603_25V7K@

12

PC40

2200P_0402_50V7K

@

PL6

4.7UH_D104C-919AS_4R7N_5.2A_20%

1 2

PL3

FBM-L18-453215-900LMA90T_1812

1 2

PC5

1 2

12

12

PC43

4.7U_1206_25V6K

Title

Size Document Number Rev

B

Date: Sheet

B+

PC6

1U_0805_50V4Z @

1 2

PC42

PC41

1 2

0.1U_0603_25V7K

4.7U_1206_25V6K

+2.5VP

1

12

+

PC48

PC49

2

4.7U_0805_6.3V6K

@

150U_D2_6.3VM_R45

COMPAL ELECTRONICS, INC

+2.5VP & +VCCPP

LA-2362

1

1

of

42 52Friday, March 11, 2005

5

D D

4

3

2

1

PJP2

3MM

21

+5VALWP

C C

PJP4

3MM

+3VALWP +3VALW

PJP6

3MM

+2.5VP

PJP8

3MM

+1.25VSP

PJP10

3MM

+1.5VSP

B B

+5VALW

21

21

+2.5V

+1.25VS

21

21

+1.5VS

+12VALWP

+VCCPP +VCCP

PJP3

2MM

PJP7

3MM

+2.5VP

21

+12VALW

12

PC93
10U_1206_6.3V7K

12

PR107

1K_0402_1%

21

12

PR108

1K_0402_1%

13

D

PQ20

SUSP<16,37,44>

1 2

PR109

0_0402_5%

2

G

RHU002N06_SOT323

S

150U_D2_6.3VM

@

PC98

12

1

+

2

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

PC97

0.1U_0603_25V7K

12

PC99

4.7U_0805_6.3V6K

+1.25VSP

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC92
1U_0603_16V6K

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+1.25VSP

Size Document Number Rev

B

LA-2362

Date: Sheet

1

of

43 52Friday, March 11, 2005

1

A

B

C

D

PH2 under CPU botten side :

CPU thermal protection at 80 degree C
Recovery at 44(45) degree C

1 1

VL

12

PR74

2.15K_0402_1%
PR73

16.9K_0402_1%

1 2

TM_REF1

PC57

1000P_0402_50V7K

2 2

3 3

12

BATT+

PR80

200_0805_5%

12

PH1

10KB_0603_1%_TH11-3H103FT

PD10

RB751V_SOD323

12

100K_0402_5%

1U_0805_16V7K

12

PR81

PC56

12

1 2

150K_0402_1%

12

PR76
150K_0402_1%

12

PC65

0.22U_1206_25V7K

47K_0402_1%

1 2

VS

5

+

6

-

12

PR75

TP0610K_SOT23

PQ16

2

PR72

8

PU1B

P

O

G

LM393M_SO8

4

VL

13

12

7

VIN

1 2
12

12

PC55

0.1U_0603_25V7K

PD9
1N4148_SOD80

PR79
33_1206_5%

VS

PC63

0.1U_0603_25V7K

VL

PR71
47K_0402_1%

1 2

MAINPWRON <20,39,41>

12

12

PR77

2

G

4.12K_0402_1%

13

D

S

PC59

470P_0402_50V7K

PR189

0_0402_5%

SUSP<16,37,43>

12

PQ42

RHU002N06_SOT323

Ipeak=Iocset*Rocset/RDS(ON)high side
Iocset=40uA, Pocset=4.12K RDS(on)=25.5mΩ
Ipeak min=40uA*4.12/(25.5*1.3)=4.97A
Ipeak max=40uA*4.12/25.5=6.46A

PC60

0.1U_0402_16V7K

12

PU8

7

OCSET

6

FB

3

GND

APW7057KC-TR_SOP8

2.2_0402_5%

5

VCC

BOOT

UGATE

PHASE

LGATE

12

PR78

1SS355_SOD323

1

2

8

4

PD12

1 2

12

PC61

0.1U_0402_16V7K

4.7UH_D104C-919AS_4R7N_5.2A_20%

PQ15

8

G1

7

S1/D2

6

S1/D2

5

S1/D2

SI4814DY_SO8

1 2

1

D1

2

D1

3

G2

4

S2

PL7

0.1U_0402_16V7K

+5VALW

8.87K_0603_1%

PC66

12

PC58

4.7U_0805_6.3V6K

PR82

12

PR84

10K_0402_1%

12

12

12

1

+

PC62
150U_D2_6.3VM_R45

2

PC64

4.7U_0805_6.3V6K

@

+1.5VSP

51ON#<33>

4 4

CHGRTCP

1 2

PR83

22K_0402_5%

12

PC67
1U_0805_25V4Z

A

PU7

G920AT24U_SOT89

2

IN

GND

1

OUT

RTCVREF

3

12

1 2

PR85

300_0402_5%

PC68

4.7U_0805_6.3V6K

1 2

PR86

300_0402_5%

CHGRTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

C

Compal Electronics, Inc.

Title

RTC Battery & OTP & +1.5VP

Size Document Number Rev

B

LA-2362

Date: Sheet

D

of

44 52Friday, March 11, 2005

1

5

4

3

2

1

1 2

1U_0805_50V4Z

+CPU_CORE

CPU VCC SENSE

1 2

1 2

3K_0603_1%

B+

PC13

0.1U_0603_25V7K

@

PC125

1000P_0402_50V7K

@

578

3 6

241

578

3 6

241

PR141 909_0402_1%

1 2

+5VS

578

3 6

241

578

3 6

241

CPU_B+

PQ23
AO4408_SO8

4.7K_1206_5%

PQ24
AO4410_SO8

12

PD21

EC31QS04

@

PC132

2200P_0402_50V7K

12

PC114

4.7U_1206_25V6K

PR3

1 2
12

PC15

680P_0603_50V7K

12

12

PC133

12

PD23

EC31QS04

@

12

12

PC115

4.7U_1206_25V6K

0.56UH_ETQP4LR56WFC_21A_20%

12

PC116

0.01U_0402_25V7Z

PL14

1 2

12

1 2

PC124

1 2

PR134 909_0402_1%

PR132 100K_0402_1%@

0.47U_0603_16V7K

1 2

CPU_B+

12

12

PC135

4.7U_1206_25V6K

PC134

4.7U_1206_25V6K

0.01U_0402_25V7Z

0.56UH_ETQP4LR56WFC_21A_20%

1 2

12

PR8

PR155

4.7K_1206_5%
909_0402_1%

1 2

12

PC16
680P_0603_50V7K

0.47U_0603_16V7K

FBM-L18-453215-900LMA90T_1812

PL13

1 2

PC117
2200P_0402_50V7K

1 2

0.001_2512_5%

12

PR135 499_0402_1%

1 2

PR143

3K_0603_1%

PC129

0.022U_0402_16V7K

PR150
100K_0402_1%

@

1 2

PL15

1 2

0_0402_5%

1 2

PC137

PR129

PR146

1

+

2

PR136 499_0402_1%

PC118

68U_25V_M

@

12

PC9

1 2

@

PR137

+5VS

+3V

12

D D

PR139

PR123 0_0402_5%

PR124 0_0402_5%
PR126 0_0402_5%
PR128 0_0402_5%
PR130 0_0402_5%
PR131 0_0402_5%

PR133 0_0402_5%

1 2

VID0<6>
VID1<6>
VID2<6>
VID3<6>
VID4<6>
VID5<6>

VGATE<8,18,21>

PR138

C C

VR_ON <32,37>

0_0402_5%

1 2

100K_0402_5%@

1 2

1 2

13

D

PR147

S

PR149

0_0402_5%

1 2

PR142

470K_0402_5%

1 2

10.7K_0402_1%

+5VS

PR154

100K_0402_1%

12

PC130
100P_0402_50V8J

PR144

78.7K_0603_1%

1 2

FB

PR145 100K_0402_1%

H_STP_CPU#

18,21>

RHU002N06_SOT323

B B

PM_DPRSLPVR<21>

1 2

PQ25

2

G

1 2

1

C

PSI#<6>

2

B

E

3

12

PR122

33K_0402_5%

12
12
12
12
12
12

PR140 30.1K_0402_1%

1 2

1 2

13

D

2

G

S

PQ26

1 2

PR151

20K_0402_1%

PQ29

2

G

PQ30

HMBT2222A_SOT23

PR121 10_0402_5%

PC121
1U_0603_16V6K

1 2

12

PC126
270P_0402_50V7K

PC128

0.22U_0603_16V7K

1 2

27P_0402_50V8J

RHU002N06_SOT323

PR153

10K_0402_1%

1 2
13

D

RHU002N06_SOT323

S

VCC

VCC

PC131

PU12

10

VCC

24

D0

23

D1

22

D2

21

D3

20

D4

19

D5

25

VROK

4

S0

5

S1

6

SHDN#

1

TIME

12

CCV

2

TON

8

REF

9

ILIM

7

OFS

3

SUS

18

SKIP

11

GND

MAX1532AETL_TQFN40

<BOM Structure>

PC120

2.2U_0603_6.3V6K

VDD

V+

BSTM

DHM
LXM
DLM

PGND

CMP
CMN

OAIN+

OAIN-

FB

CCI

BSTS

DHS

LXS

DLS
CSP
CSN

GNDS

OAIN+

1000P_0402_50V7K

OAIN+

1000P_0402_50V7K

30
36
26
28
27
29
31
37
38
17
16
15
14
35
33
34
32
40
39
13

PC19

PC20

1 2

12

12

EP10QY03

2 1

12

1 2

PR125 2_0402_5%

FB

1 2

470P_0402_50V7K

PD20

PC122

0.01U_0402_25V7Z

OAIN+
OAIN-

PC127

PR148

12

1 2

12

2_0402_5%

PC123

0.22U_0603_16V7K

PR6 0_0402_5%

AO4408_SO8

PR7 0_0402_5%

PC136

0.22U_0603_16V7K

AO4410_SO8

12

PD22

EP10QY03

PQ27

12

PQ28

21

Vin=19V,Vo=1.484V,Io=12.5A,Fs=300KHZ,L=0.56UH
Current sense tpy.=1mΩ Max=1.1mΩ,Delta I =8.12A

A A

Iimit=ILIM(V)/20/DCR+1/2 delta I
Iimit Min={1.99V*78.7K/(78.7K+470K)/20/1.01mΩ+4.22A}*2=36.69A

1 2

PR156

909_0402_1%

Iimit Max={2.01V*78.7K/(78.7K+470K)/20/0.99mΩ+4.22A}*2=37.56A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Title

+CPU_CORE

Size Document Number Rev

B

LA-2362

Date: Sheet

1

of

45 52Friday, March 11, 2005

1

5

4

3

2

Version change list (P.I.R. List) Page 1 of 2

1

D D

1

2

3

4

5

6

C C

7

8

9

10

11

12

13

14

B B

15

16

17

18

19

20

21

22

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

ICH_PME# pull up +3VALW add R 10K

LID_SW# pull up +3VALW add R 10K

SB +1.5V regulator footprint error

SB +1.5V regulator footprint error U8 need to reverse

R76 take off

PR191 power plane 2.5vref change to +2.5V

R398 remove to R401

H_DPRSLP# add pull up to +vccp power plane POP R546

POP U9 for lose and foot print error

U3 pin6 & pin 7 need to swap

Add R476/7 40.2 Ohm for memory

R259 short

PR122 chang power plane to +3V for EC voltage leakage

Add R224/R290/R407 470ohm and Q34/9/11 2N7002

ADD R 39K//220p to GND at R518 for modify SIRQ

Reverse the JHP1 & JMIC1 Symble error

Modify NB FSB speed select for Dothan

Modify ACIN for SB

CardReader pin swap for flash memory

Reverse the JHP1 & JMIC1 Symbl

Add VCCP noise cap. at CPU C664/5/6/7/8/9 C670/1/2

Change R362/3 2.2K to 10K for Panel select

0.1 DVT-2

0.1 DVT-2

0.2 DVT-3

0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT0.2

DVT-20.1

DVT-20.1

DVT-20.1

DVT-20.1

DVT-20.1

DVT-3

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PIR

Size Document Number Rev

LA-2362

Date: Sheet

1

of

46 52Friday, March 11, 2005

1

5

4

3

2

Version change list (P.I.R. List) Page 2 of 2

1

D D

23

24

25

26

27

28

C C

29

30

31

32

33

34

35

36

B B

37

38

39

40

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

Add C674/5/6/7/8 C680/1/2/3/4/5 C686/7/8/9
C690/1/2/3/4/5/6/7/8/9 C702/3 for NB VCCP
noise cap.

ADD C646/7/8/9 C650/1/2/3/4/5 for DDR RAM

1.25V noise cap

ADD C704/5 for JVGAP1 2.5V for noise

Change R17/8/9 from 75 to 150 OHM for TV-out signal

ADD R774/5 for cost down U29 parts

Change SB(U5) sus power from V plane to Always power plane and
R457 R69 R456 R455 R456 R451 U7.T2 +1.5VR

R154 remove for FIR function
ADD C656/7 C659/8 for +5VS HDD CDROM power

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

DVT-30.2

noise
U9 replace the new package to RM8 and remove to TOP

ADD C706/7/8/9/10/11 for SB 1.5Vrun noise

R129 change to +5VALW

Q3 cahnge to AO3400 for current rating not enough

JMPCI1 P.24 change to +3V for wireless power

Remove KB910 & 39VF080 ROM

R705 change to 13K for MB ID
Change the Killer switch circuit for EC detect method

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

0.2 DVT-3

then light on the LED
Move U32 to near NB

ADD 5VALW noise cap. C714/5/2/3,

0.2 DVT-3

0.2 DVT-3

41

42

43

44

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PIR

Size Document Number Rev

LA-2362

Date: Sheet

1

of

47 52Friday, March 11, 2005

1

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 2

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

1

Delete the charge circuit.

Change the CPU OTP circuit from active H

2

to active L. to active L.

For cost down solution.

3

2 2

For cost down solution.

4

Delete the charge circuit.

Change the CPU OTP circuit from active H

To cost down for +1.5VP.

To cost down for RTC charge circuit..

0.2

0.2

0.2

1.Delete the PU5 IC LM393M (SM).

2.Delete PD1 S DIO 1N4148 (SM).

3.Delete PR10,PR11,PR12,PR13 S RES 1/4W 1.5K +-5% 1206.

1.Delete PQ14 S TR DTC115EUA NPN (UMT3).

2..Delete PD8 S DIO 1SS355.

3.Change PR75 and PR76 from S RES 1/16W 100K +-1% 0402 to
S RES 1/16W 150K +-1% 0402.

4.Change PR73 from S RES 1/16W 15K +-1% 0402 to S RES

43

1/16W 16.9K +-1% 0402.

5.Change PC56 from S CER CAP .22U 16V K X7R 0603 to
S CER CAP 1U 16V K X7R 0805

6.Change PR74 from S RES 1/16W 3.4K +-1% 0402 to S

S RES 1/16W 2.15K +-1% 0402.

43

1.Change the PD12 from DIO 1N4148 (SM) to DIO 1SS355.

1.Delete the PD33 S ZEN DIO RLZ4.3B (LL-34).

43

0.2

0.2

0.2

DVT0.20.2 38

DVT

DVT

DVT

To prevent the KB-910 damag.

5

To prevent the KB-910 damag.

0.2 40

1.Change the PD17 from SCH DIO SKS10-04AT TSMA to

0.2

DVT

SCH DIO SKUL30-02AT THIN SMA.

For cost down solution.

6

For cost down solution.

7

For cost down solution.

8

3 3

For cost down solution.

9

10

Don't has pull high resister on VGATE pin.

10

10

11.

4 4

VCCPP output voltage has error. Adjustment resistor divider.

Choke Rating not enough for +1.5VP. Choke Rating not enough for +1.5VP.

A

To cost down for +1.5VP for +12VALWP circuit. 1.Delete PR187 S RES 1/8W 2.7K +-5% 1206 S7.

To cost down for DDR 2.5V.

To cost down for CPU_CORE.

To cost down for snubber circuit.

To cost down for EMI capacitor.For cost down solution.

Add pull high resister on VGATE pin.

0.2

0.2

0.2

0.2 40 0.2 DVT

0.2 0.2 DVT

0.2

0.2

0.2 0.2 DVT43

1.Delete PR62 S RES 1/16W 0 +-5% 0402.

41

1.Delete PR127 and PR152 S RES 1/16W 0 +-5% 0402.

44

1.Deete PR127 and PR152 S RES 1/16W 0 +-5% 0402.

2.Delete the PC161 S CER CAP 470P 100V K X7R 0805.

39

1.Delete PC41,PC158 and PC159 S CER CAP .1U 25V K X7R 0603.

40

2.Delete PC40,PC73 and PC76 CER CAP 2200P 50V K X7R 0402.

41

1.Add the S RES 1/16W 100K +-5% 0402.

44

1.Change the PR60 from S RES 1/16W 681 +-1% 0402 to

41

S RES 1/16W 1.69K +-1% 0603.

1.Change PL7 from 4.7UH_FDV0630-4.7UH_5.5A_20%

to 4.7UH_D104C-919AS_4R7N_5.2A_20%.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

0.2 DVT40

0.2 DVT

DVT0.2

0.2

0.2

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

LA-2362

Date: Sheet

DVT

E

DVT

of

48 52Friday, March 11, 2005

1

A

B

C

D

E

Version change list (P.I.R. List)

Page 2 of 4

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

2 2

3 3

Don't has pull down resister on SHDN#

1

pin for charger.

Change the Vin Detector from LM393 to

2

charger ACOK#.

For ACIN pin, 1.Add PR4 the 10K +-5% 0402ACIN pin don't have connect to system.

3

+1.8VSP power rating not enough.

4

VCCP's transients cannot meet spec.

5

Change the Vin Detector from LM393 to
charger ACOK#.

+1.8VSP power rating isnot enough.

VCCP's transients cannot meet spec.

1.Add PR193 the S RES 1/16W 100K +-5% 0402.Add pull down resister on SHDN# pin.

1.Add the PQ40 S TR DTC115EUA NPN (UMT3).

2.Delete the PR3,PR4,PR8 and PR9 RES 1/16W 10K +-1% 0402.

3.Add the PR193,PR172 and PR173 RES 1/16W 100K +-5% 0402.

4.Delete PR6 the S RES 1/16W 22K +-1% 0402.

5.Delete PR1 the S RES 1/16W 1M +-1% 0402.

6.Change PR182 from S RES 1/16W 150K +-1% 0402 to S

0.2 DVT0.2

38,39

S RES 1/16W 20K +-1% 0402.

7.Delete the PR7 S RES 1/16W 20K +-1% 0402.

8.Delete the PR2 S RES 1/16W 84.5K +-1% 0402.

9.Add the PR175 S RES 1/16W 158K +-1% 0402.

10.Add the PR175 S RES 1/16W 681K +-1% 0402.

11.Delete PC6 from S CER CAP .1U 25V K X7R 0603.

12..Delete PC5 from S CER CAP 1000P 50V +-10% X7R 0402.

1.Change PU10 from S IC G965-18P1U SOP-8L REG to S IC

APW7057KC-TR SOP-8 PWM.

2.Add PR197 S RES 1/16W 12.7K +-1% 0402.

3.Add the PQ44 S TR RHU002N06 1N SOT323

4.Delete PQ43 the S TR AO4912 2N SO8 W/D

5.Add PD33 the S DIO 1SS355.

6.Add PR195 the S RES 1/16W 2.2 +-5% 0402

0.2 DVT0.2

7.Add PR198 the S RES 1/16W 10K +-1% 0402.

42

8.Add PR196 the S RES 1/16W 4.12K +-1% 0402

9.Add the PC167 the S CER CAP 4.7U 10V Z Y5V 0805.

10.Add the PC164 S CER CAP 470P 50V +-10% X7R 0402.

11.Add the PC163,PC165 and PC168 S CER CAP .1U 16V +-10%

X7R 0402

12.Delete PC96 the S CER CAP 10U 6.3V K X7R 1206.

13.Add the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.

14.Add PL18 the S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.

1.Change PC50 from S POLY CAP 150U 6.3V M V(D2) T520 LESR

0.2

to S POLY C 220U 4V M V(D2) T520 LESR.

41

2.Change PL6 from S COIL 4.7UH +-20% D104C-919AS-4R7M 5.2A

to S COIL 1.8UH +-30% D104C-919AS-1R8N 9.5A.

0.2 DVT

DVT0.20.2 39

DVT0.20.2 39

For CPU_CORE's EMI,

6

4 4

A

For CPU_CORE's EMI,

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1.Change the PR125 and PR148 from S RES 1/16W 0 +-5% 0402S

to RES 1/16W 2 +-5% 0402.

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

LA-2362

D

Date: Sheet

DVT0.20.2 44

1

of

49 52Friday, March 11, 2005

E

A

B

C

D

E

Version change list (P.I.R. List) Page 3 of 3

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

CPU's transients cannot meet spec.

1.

PACIN pin's high level is only 2.3V. To adjust PACIN pin's level.

2.

The 5VALWP rising time is faster than

3.

PACIN's.

Add one current sense on phase 2.

To delay timer of 5VALWP.

0.2 44

0.3

1.Delete PC124 and PC137 the S CER CAP 0.47U 16V +-10% X7R

0603.

2.Delete PR134,PR141,PR155 and PR156 the S RES 1/16W

909+-1% 0402.

0.2 DVT

3.Add PR134 S RES 1W 0.01 +-1%2512.

1.Delete PR175 the S RES 1/16W 158K+-1% 0402.

2.Change the PR172 from S RES 1/16W 100K +-1% 0402 S

to RES 1/16W 10K +-1% 0402.

1.Change the PR105 from S RES 1/16W 47K +-1% 0402 S

to RES 1/16W 100K +-1% 0402.

40 0.3 DVT2

2.Change the PC91 from S CER CAP .047U 25V M X7R 0603

to CAP 1U 25V Z F Y5V 0805..

DVT0.2390.2

The charge has error on change mode.

4.

2 2

5.

For cost down solution.

The charger has EMI issue. Add a resistor on charger's boost for EMI.

6.

Change the current limit's from sense

7.

DRC to resister.

8.

MAX1902.

To adjust input and output current
regulation loop compensation.

For cost down solution. 1.Change PC58,PC68,PC95 and PC99 from the S CER CAP 4.7U

0.3

0.3

0.3

To adjust current limit point for CPU_CORE. 1.Change the PR142 from S RES 1/16W 200K +-5% 0402

To preven in-rush current for B+ of
MAX1902.

0.3

0.3 DVT2

39

1.Change PC152 and PC153 from the S CER CAP 0.01U 16V +-10%

X7R to CER CAP 0.001U 16V +-10% X7R.

42
43

25V K X5R 1206 to CAP 4.7U 10V K X7R 0805.

39

1.Add the PR1 S RES 1/16W 0 +-5% 0402.

44 DVT2

to S RES 1/16W 470K +-5% 0402.

40

1.Add PR2 S RES 1/8W 33 +-5% 1206.To preven in-rush current for B+ of

0.3

0.3

0.3

0.3

0.3

DVT2

DVT2

DVT2

1.Add PQ26 SB502060000 S TR RHU002N06 1N SOT323.

2.Add PR134,PR141,PR155,PR156 S RES 1/16W 909 +-1% 0402.

The CPU's dual choke will shortage. Change to single choke.

9.

3 3

0.3

3.Delete PL14 S COIL .5UH +-30% CXZT1050-R50 28A.

44

4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.

5.Add the PC124,PC137 0.47U 16V +-10% X7R 0603 S8.

4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.

DVT20.3

1.Delete the PU10 S IC APW7057KC-TR SOP-8 PWM.

2.Delete the PQ43 S TR AO4912 2N SO8 W/D.

3.Delete the PR188 S RES 1/16W 0 +-5% 0402.

4.Delete the PR195 S RES 1/16W 2.2 +-5% 0402

5.Delete the PR196 S RES 1/16W 4.12K +-1% 0402

6.Delete the PR198 S RES 1/16W 10K +-1% 0402

Delete the +1.8VSP on M/B. Delete the +1.8VSP on M/B.

10.

0.3

7.Delete the PR197 S RES 1/16W 12.7K +-1% 0402.

42

8.Delete the PL18 S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.

9.Delete the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.

10.Change the PC75 and PC87 from S CER CAP 4.7U 10V Z Y5V

0805 to S CER CAP 4.7U 6.3V +-10% X5R 0805

0.3 DVT2

11.Delete PC95 S CER CAP 4.7U 10V Z Y5V 0805.

12.Delete PC163,PC165,PC168 .1U 16V +-10% X7R 0402.

4 4

13.Delete PC164 S CER CAP 470P 50V +-10% X7R 0402.

14.Delete PD33 S DIO 1SS355.

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

LA-2362

Date: Sheet

E

of

50 52Friday, March 11, 2005

1

A

B

C

D

E

Version change list (P.I.R. List) Page 4 of 4

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

Max1902 protect When power cord fast

1.

plug-out and plug-in.

2 2

The 5VALWP choke rating is not enough.

2.

TP0610T will EOL. Change the part.

3.

Add the pre-chagre circuit.

Change the choke.

0.3

0.3

1.Add PQ1 SB502060000 S TR RHU002N06 1N SOT323.

2.Add PQ2 S TR DTC115EUA NPN (UMT3).

3.Add PD2 S SCH DIO RB715F UMD3.

4.Add PD1 S DIO 1N4148 (SM)

5.Add PR10,PR11,PR12 and PR13 S RES 1/4W 1.5K +-5% 1206.

6.Add PR16 S RES 1/16W 100K +-1% 0402.

7.Add PR17 and PR20 S RES 1/16W 499K +-1% 0402.

38

8.Add PR19 S RES 1/16W 191K +-1% 0402.

9.Add PR23 S RES 1/16W 34K +-1% 0402.

10.Add PR26 S RES 1/16W 66.5K +-1% 0402.

11.Add PR14 S RES 1/16W 2.2M +-5% 0402.

12.Add PR24 S RES 1/16W 47K +-5% 0402.

13.Add PC10 and PC12 S CER CAP 1000P 50V +-10% X7R 0402.

14.Add PC11 S CER CAP .1U 25V K X7R 0603.

40

1.Change the PL9 from S COIL 10UH +-30% SDT-1050P-100-

118 3.5A to S COIL 10uH +-20% SDT-1205P-100-118.

43

1.Change the PQ16 S TR TP0610T 1P SOT-23 to.S TR TP0610K

1P SOT-23

0.3

0.3

DVT2

DVT2

DVT20.30.3

3 3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

LA-2362

Date: Sheet

E

of

51 52Friday, March 11, 2005

1

A

B

C

D

E

Version change list (P.I.R. List) Page 5 of 5

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

To adjust sequence for +5VALWP and +3VALWP. To adjust sequence for +5VALWP and +3VALWP.

1.

1 1

Change the pull-high resistor for VGTE pin. For HW request.

2.

The system has re-boot issue when running

3.

the 3D mark.

The CPU's B+ has nosie issue when system

4.

into C3/C4.

The HW has noise by interference from B+.

The CPU's B+ has nosie issue when system
into C3/C4.

LA-2362-0.2

LA-2362-0.2

LA-2362-0.2

LA-2362-0.2

41 DVT3

1.Change PC90 from .47U 16V X7R 0603 to 2.2U 10V X5R 0805.

45

1.Change PR122 from 100K 0402 to 10K 0402.

1.Add the PL3 FBL-18-453215-900LM90T_1812.

42

2.Add the PC35 and PC41 0.1U 25V X7R 0603,

1.Add the PC14 220U 25V.

45

LA-2362-0.2

LA-2362-0.2

LA-2362-0.2

LA-2362-0.2

DVT3

DVT3

DVT3

To cost down for 150uf/6.3V. To cost down for 150uf/6.3V.

5.

Change the IC solution from ISL6227 to

6.

MAX8743 for +2.5V and +VCCPP.

2 2

3 3

The ISL6227 has shut down issue when windows idle.

LA-2362-0.2 LA-2362-0.2

LA-2362-0.2 42 LA-2362-0.2 DVT3

41,45

1.Change the vendor form KEMET to EPCOS.

DVT3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

LA-2362

Date: Sheet

E

of

52 52Friday, March 11, 2005

1