Compal LA-2361, Smart 300S Schematic

5

4

3

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1

Project Code : AL50/1

D D

Date : 2004-06-02
Revision : 0.2

C C

AL50/1 Intel Sonoma plateform Used the Alvisio and ICH6-M

B B

A A

Title

Size Document Number Rev

5

4

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Date: Sheet

Compal Electronics, Inc.

Function

LA-2361

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Compal confidential

Block Diagram

Dothan

D D

uFCPGA CPU

Clock Generator

ICS

Memory
BUS(DDR)
Dual Channel

2.5V 333MHz

Channel A

SO-DIMM X 1

BANK 0, 1

SO-DIMM X 1

BANK 2, 3

Fan Control X1

LED/B

VGA
Board

CRT CONN.

& TV-OUT

HA#(3..31)

System Bus

400 / 533MHz

Alviso Intel 915 PM/GM

GMCH-M

HD#(0..63)

Internal GM

ATI VGA

C C

VGA CONN.

PCI-E 16X

External PM

1257 FC-BGA

SW LED BD

T/P

DMI

1.5V

MINI PCI

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

VIA6301
1394

B B

1394
CONN.

CardBus
Controller

ENE CB712

SDIO
CONN.

3.3V 33MHz

PCI BUS

Slot 0

3.3V 33MHz

RTL 8110SBL
/ G 8100CL /
100

Transformer

& RJ45

LPC BUS

3.3V 33MHz

100MHz

ICH6

609 BGA

3.3V 24.576MHz

ATA100

HDD

BT+MDC

AC-LINK

AC97 CODEC

RTL 250

CDROM

AMP &

Phone/ MIC
Jack

USBPORT 0
USBPORT 1

X BUS

SIO
LPC47N217D

A A

FIR

PIO

5

SST39VF080

Touch Pad

4

KB910

Int.KBD

48MHz / 480Mb

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

USB2.0

3

USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

JUSBP2

JUSBP3

BT
JUSBP1
JUSBP1

RESERVED
RESERVED
RESERVED

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-2361

DC IN

BATT IN/+2.5V

1.5V/1.05V(+VCCP)

5V/3.3V/15V

1.8V / 0.9V

VCORE

CHARGER

Block Diagram

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I2C / SMBUS ADDRESSING

External PCI Devices

D D

LAN
CARD BUS
Cardreader
1394
Wireless LAN(MINI PCI)

IDSEL # PIRQREQ/GNT #DEVICE

AD17
AD20

AD16 2
AD18

0
1

F
A
B
E

3

G,H

@ Depop
1@ EAL51

C C

2@ EAL50
1@ EAL51 VALUE (DELETE SIO/1394)

Power Managment table

Signal

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

Ceramic Capacitor Spec
Guide:

+12VALW +3V
+3VALW
+5VALW

ON

+2.5V

+5V
+12V

ON ON

ON ON ON

ON ON

ON OFF

OFF OFF OFF

+CPU_CORE
+VCCP
+5VS

+3VS
+2.5VS
+1.8VS
+1.25VS
+1.5VS

OFF

OFF

Bringup-Build

SST-Build

PT-Build

ST-Build

QT-Build

PCB Rev

0.1

Data

SCHEMATICS VERSION LIST

VERSION ISSUE DATE REMARK

0.0A

First Release

Temperature Characteristics:

3

2

Y5U X7R

C

B

CH

4

Y5V Y5P

CJ

5

E

D

CK

Z5V

1

Z5P

A

BJ

Symbol

CODE

0

Z5U

8

NP0 SH

9

C0G

6

X5R

7

F

G

SJ

I

H

UJ

B B

Tolerance:

Symbol

CODE

+-0.05PF

KQ

+-20%

+-10%

J

SL

UK

A

M

B

+-0.1PF

N

+-30%

C

+-0.25PF

P

+100,-0%

D

+-0.5PF +-1PF

+30,-10%

F

V

+20,-10%

G

+-2%

X

+40,-20%

H

+-3%

Z

+80,-20%

J

+-5%

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

A A

ICH_SMBCLK
ICH_SMBDATA

LCD_DDCCLK
LCD_DDCDATA

PC87591L

PC87591L

ICH6-M

Alviso
GM-GP

5

INVERTER BATT

SERIAL SENSOR
EEPROM

THERMAL
(CPU)

4

THERMAL
SENSOR
(LM75)

SODIMM CLK CHIP

MINI PCI

3

LCD

VGA Thermal

ADM1032

Title

<Title>

Size Document Number Rev

LA-2361 0.0

Custom

2

Date: Sheet

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+5VALW

D D

PWR_SRC

ADAPTER

+3VALW

BATTERY

C C

SUS_ON

+5V

B B

A A

PL9

+15V

VDDA

RUN_ON

(Option)

AUDIO_AVDD_ON

+3VS

L10

SUS_ON

+3VSRC

RUN_ON

V3P3LAN

SUSPWROK_5V

+3V

RUN_ON_D

+2.5VS

RUNPWROK

+VCC_CORE

+1.5V

RUN_ON SUSPWROK_1.5V

+1.5VS

RUNPWROK

+VCCP

SUSPWROK_5V

SUSPWROK_5V

+1.8VSUSP +2.5V_DDR_VTT

PJP11,PJP12

+1.8V

RUN_ON

+1.8VS

+5VHDD +5VMOD +5VS

Title

<Title>

Size Document Number Rev

LA-2361 0.0

Custom

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Date: Sheet

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1

+3VS

C

2

B

E

LA-2361

+3V

R79

150_0402_5%

1 2

+VCCP

54.9_0603_1%

1 2

R745 56_0402_5%

+VCCP

37.4_0402_1%

1 2

150_0402_5%

1 2

680_0402_5%

1 2

27.4_0402_1%

1 2

+VCCP

1

2

R90

R76

54.9_0603_1%

1 2
1 2

39.4

R479

R85

This shall place near CPU

R100

R106

C359

0.1U_0402_10V6K

ITP_DBRESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near JITP

12

R132
1K_0402_5%

1

Q6
2SC2411K_SC59

3

Compal Electronics, Inc.

Dothan Processor(1/2)

1

H_RESET#
ITP_BPM#5

PROCHOT# <32,34>

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H_A#[3..31]<8>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

ITP_DBRESET#

H_PROCHOT#

R530

1 2

1K_0402_5%@

R464

1 2

1K_0402_5%@

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_CK_ITP
CPU_CK_ITP#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

H_DBSY#
H_DPSLP#
H_DPRSLP#

ITP_BPM#4
ITP_BPM#5

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

D D

H_REQ#[0..4]<8>

CLK_ITP_R#

R110 0_0402_5%

1 2

CLK_ITP_R

R112 0_0402_5%

1 2

@

CLK_ITP<18>
CLK_ITP#<18>

+VCCP

@

1 2

CLK_ITP
CLK_ITP#

R7856_0402_5%

H_RS#[0..2]<8>

C C

B B

A A

H_ADSTB#0<8>
H_ADSTB#1<8>

R111 0_0402_5%@

1 2

R109 0_0402_5%@

1 2

CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>

H_ADS#<8>
H_BNR#<8>
H_BPRI#<8>
H_BR0#<8>
H_DEFER#<8>
H_DRDY#<8>
H_HIT#<8>
H_HITM#<8>

H_LOCK#<8>
H_RESET#<8>

H_TRDY#<8>

H_DBSY#<8>
H_DPSLP#<20>
H_DPRSLP#<20>
H_DPWR#<8>

H_PWRGOOD<20>

H_CPUSLP#<8,20>

T5 PAD
T39 PAD

H_THERMDA<34>
H_THERMDC<34>
H_THERMTRIP#<8,20>

TEST2

TEST1

5

JCPU1A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612365-1_Dothan

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#

FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_A20M# <20>
H_FERR# <20>
H_IGNNE# <20>
H_INIT# <20>
H_INTR <20>
H_NMI <20>

H_STPCLK# <20>
H_SMI# <20>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

H_D#0

A19

H_D#[0..63] <8>

H_RESET#

ITP_TDO

H_DSTBN#[0..3] <8>

H_DSTBP#[0..3] <8>

+VCCP

Test pad as closed as posible

ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1

Place near JITP 0.5"

R74

22.6_0402_1%

1 2

R87

22.6_0402_1%

1 2

ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK

CLK_ITP_R#
CLK_ITP_R

ITP_TRST#
ITP_TMS
ITP_TDI

Check ITP connector.

R458
200_0402_5%

1 2

H_PWRGOOD

Add pullups for PWRGOOD and THERMTRIP per INTEL

2

R123
56_0402_5%

T7PAD
T6PAD
T8PAD
T10PAD
T9PAD
T12PAD
T11PAD

T4PAD
T17PAD

T18PAD
T19PAD
T15PAD

T16PAD
T13PAD
T14PAD

+VCCP

12

R124
56_0402_5%

12

H_PROCHOT#

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

1

R470

+VCCA_PROC

2 1

PAD-OPEN 2x2m@

R422
0_0402_5%

1 2

@

J2

SHORT

1

C516

2

0.01U_0402_16V7K

VID0 <45>
VID1 <45>
VID2 <45>
VID3 <45>
VID4 <45>
VID5 <45>

1

C150

2

10U_1206_6.3V6M

D D

+1.5VS

For test only ,Cmos output

R427
0_0402_5%

+VCCP

1 2

@

R412 10K_0402_5%

@

12

12

R426
0_0402_5%

R411 10K_0402_5%

@

@

12

R410 10K_0402_5%

12

1 2

@

R409 10K_0402_5%

@

12

R425
0_0402_5%

R408 10K_0402_5%

@

12

R413 10K_0402_5%

@

1 2

@

R424
0_0402_5%

@

1 2

R423
0_0402_5%

CPU Voltage ID

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

C C

R433 0_0402_5%
R434 0_0402_5%
R435 0_0402_5%
R436 0_0402_5%
R437 0_0402_5%
R438 0_0402_5%

12
12
12
12
12
12

1 2

@

54.9_0402_1%@

54.9_0402_1%@

+CPU_CORE

1 2
1 2

R465

+VCCP

VCCSENSE
VSSSENSE

OPEN OPEN OPEN OPEN OPEN OPEN

T3 PAD
T2 PAD
T20 PAD
T31 PAD
T29 PAD

H_PSI#
H_VID0

H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

PSI#<45>

+VCCP

R_A

12

+V_CPU_GTLREF

B B

12

R155
1K_0402_1%

R_B

R153
2K_0402_1%

Layout close CPU

Layout Note:

500 mil max length

27.4_0402_1%

R156

20 mils

12

54.9_0402_1%

R157

5 mils

12

27.4_0402_1%

R416

20 mils

12

R417

5 mils

12

Resistor placed within

54.9_0402_1%

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

CPU_BSEL0<18>
CPU_BSEL1<18>

+V_CPU_GTLREF

JCPU1B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612365-1_Dothan

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JCPU1C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612365-1_Dothan

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Processor(2/2)

LA-2361

650Monday, October 04, 2004

1

0.0

of

5

4

3

2

1

+CPU_CORE

1

C482
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C430
10U_0805_6.3V6M

C100
10U_0805_6.3V6M

C512
10U_0805_6.3V6M

D D

C C

1

C483
10U_0805_6.3V6M

2

1

C421
10U_0805_6.3V6M

2

1

C105
10U_0805_6.3V6M

2

1

C507
10U_0805_6.3V6M

2

1

C460
10U_0805_6.3V6M

2

1

C415
10U_0805_6.3V6M

2

1

C109
10U_0805_6.3V6M

2

1

C502
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C416
10U_0805_6.3V6M

2

1

C114
10U_0805_6.3V6M

2

1

C469
10U_0805_6.3V6M

2

1

C431
10U_0805_6.3V6M

2

1

C480
10U_0805_6.3V6M

2

1

C91
10U_0805_6.3V6M

2

1

C442
10U_0805_6.3V6M

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C422
10U_0805_6.3V6M

C481
10U_0805_6.3V6M

C92
10U_0805_6.3V6M

1

C518
10U_0805_6.3V6M

2

1

C113
10U_0805_6.3V6M

2

1

C121
10U_0805_6.3V6M

2

10uF 1206 X5R -> 85 degree

1

C470
10U_0805_6.3V6M

2

1

C108
10U_0805_6.3V6M

2

1

C120
10U_0805_6.3V6M

2

1

C459
10U_0805_6.3V6M

2

1

C104
10U_0805_6.3V6M

2

1

C383
10U_0805_6.3V6M

2

X7R

High Frequence Decoupling

1

C445
10U_0805_6.3V6M

2

1

C99
10U_0805_6.3V6M

2

1

C522
10U_0805_6.3V6M

2

Near VCORE regulator.

+CPU_CORE

@

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

C378

C358

B B

+

2

1

1

C377

+

+

2

2

330U_D2E_2.5VM_R9

1

C357

+

2

ESR <= 3m ohm

Capacitor > 880 uF

+VCCP

1

+

C525
150U_D2_6.3VM

2

A A

1

C498

0.1U_0402_10V6K

2

5

1

C499

0.1U_0402_10V6K

2

1

C504

0.1U_0402_10V6K

2

1

2

4

C500

0.1U_0402_10V6K

1

C503

0.1U_0402_10V6K

2

1

C463

0.1U_0402_10V6K

2

1

C441

0.1U_0402_10V6K

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

C424

0.1U_0402_10V6K

2

1

C450

0.1U_0402_10V6K

2

1

C398

0.1U_0402_10V6K

2

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Bypass

LA-2361

750Monday, October 04, 2004

1

of

0.0

5

D D

C C

Layout Guide will show
these signals routed
differentially.

B B

A A

H_A#[3..31]<5>

H_REQ#[0..4]<5>

CLK_MCH_BCLK#<18>
CLK_MCH_BCLK<18>

H_DSTBN#[0..3]<5>

H_DSTBP#[0..3]<5>

H_HITM#<5>
H_HIT#<5>
H_LOCK#<5>

H_RS#[0..2]<5>

H_CPUSLP#<5,20>

H_CPUSLP# H_R_CPUSLP#

Note:
"Do not install R for Dothan-A,
Install R97 for Dothan-B"

T1 PAD

H_ADSTB#0<5>
H_ADSTB#1<5>

H_DINV#0<5>
H_DINV#1<5>
H_DINV#2<5>
H_DINV#3<5>

H_RESET#<5>
H_ADS#<5>

H_TRDY#<5>
H_DPWR#<5>
H_DRDY#<5>
H_DEFER#<5>

H_BR0#<5>
H_BNR#<5>
H_BPRI#<5>
H_DBSY#<5>

5

T27 PAD

R418
0_0402_5%

1 2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#

@

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

U5A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

Alviso

HOST

H_SWNG0

C362

0.1U_0402_16V4Z

HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING

HYSWING

1

2

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF

12

R397

221_0603_1%

12

R388

100_0402_1%

4

4

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

J11
C1
C2
T1
L1
D1
P1

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

H_SWNG1

C385

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1

2

0.1U_0402_16V4Z

+VCCP+VCCP

R67

221_0603_1%

R73

100_0603_1%

12

12

12

R77

24.9_0402_1%

R44

24.9_0402_1%

+VCCP

R41

12

H_D#[0..63] <5>

Layout Note:
Rote as short
as possible

12

R477

40.2_0402_1%

12

12

R66

54.9_0402_1%

54.9_0402_1%

10/20 mils

3

Layout Guide
will show these
signals routed
differentially.

DMI_TXN0<21>
DMI_TXN1<21>
DMI_TXN2<21>
DMI_TXN3<21>

DMI_TXP0<21>
DMI_TXP1<21>
DMI_TXP2<21>
DMI_TXP3<21>

DMI_RXN0<21>
DMI_RXN1<21>
DMI_RXN2<21>
DMI_RXN3<21>

DMI_RXP0<21>
DMI_RXP1<21>
DMI_RXP2<21>
DMI_RXP3<21>

DDR_CLK0<13>
DDR_CLK1<13>

DDR_CLK3<14>
DDR_CLK4<14>

DDR_CLK0#<13>
DDR_CLK1#<13>

DDR_CLK3#<14>
DDR_CLK4#<14>

DDR_CKE0<13>
DDR_CKE1<13>
DDR_CKE2<14>
DDR_CKE3<14>

DDR_SCS#0<13>
DDR_SCS#1<13>
DDR_SCS#2<14>
DDR_SCS#3<14>

R484 80.6_0402_1%

1 2

12

R489

80.6_0402_1%

+SDREF_DIMM

CFG[2:0]

CFG5

CFG6

12

R476

40.2_0402_1%

C379

0.1U_0402_16V7K

M_OCDOCMP0
M_OCDOCMP1

1

2

+VCCP

12

R372

100_0402_1%

12

R376

200_0402_1%

+2.5V

CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DDR_CLK0
DDR_CLK1

DDR_CLK3
DDR_CLK4

DDR_CLK0#
DDR_CLK1#

DDR_CLK3#
DDR_CLK4#

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

M_OCDOCMP0
M_OCDOCMP1

SMRCOMPN
SMRCOMPP

1

1

C428

C419

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Refer to sheet 6 for FSB
frequency select

Low = DMI x 2

High = DMI x 4

Low = DDR-II

High = DDR-I

Low = DT/Transportable CPU

High = Mobile CPU

Low = Reverse Lane

High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled

High = Enabled

Low = 1.05V (Default)

High = 1.5V

Low = 1.05V (Default)

High = 1.2V

AA31
AB35
AC31
AD35

Y31
AA35
AB31
AC35

AA33
AB37
AC33
AD37

Y33
AA37
AB33
AC37

AM33

AL1
AE11

AJ34

AF6
AC10

AN33

AK1

AE10

AJ33

AF5

AD10
AP21

AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14

AL15
AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9
AF10

*

2

U5B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO_BGA1257

*

*

*

2

*

*

*

CFG10
CFG11
CFG12
CFG13

DMIDDR MUXING

CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

CFG20
RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC

*

1

Alviso CFG[17:3] has internal pull-up

CFG0

G16

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

NC10
NC11

MCH_CLKSEL1

H13

MCH_CLKSEL0

G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37

NC1

AN37

NC2

AP36

NC3

AP2

NC4

AP1

NC5

AN1

NC6

B1

NC7

A2

NC8

B37

NC9

A36
A37

CFG[17:3] have internal pull-up

3.5 k reserve for choose

Title

Size Document Number Rev

Date: Sheet

T25PAD
T26PAD

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

H_THERMTRIP#

PM_EXTTS#0
PM_EXTTS#1

PLTRST_R#

R384 10K_0402_5%

@

R387 10K_0402_5%

@

CFG0
CFG6
CFG5
CFG7
CFG9

CFG12
CFG13
CFG16

CFG18
CFG19

12
12

LA-2361

MCH_CLKSEL1 <18>
MCH_CLKSEL0 <18>

@
@

R57
56_0402_5%

1 2

@

1 2

R492 100_0402_1%

12

12

PM_EXTTS#0

PM_EXTTS#1

R367 10K_0402_5%
R369 2.2K_0402_5%
R370 2.2K_0402_5%
R368 2.2K_0402_5%
R394 2.2K_0402_5%@

R374 2.2K_0402_5%@
R375 2.2K_0402_5%@
R430 2.2K_0402_5%@

R36 1K_0402_5%@
R37 1K_0402_5%@

R352.2K_0402_5%@

CFG[19:18] have internal pull-down

R382.2K_0402_5%@

+VCCP

PM_BMBUSY# <21>

H_THERMTRIP# <5,20>
VGATE <18,21,45>

DREFCLK# <18>

DREFCLK <18>
SSC_DREFCLK <18>
SSC_DREFCLK# <18>

R366

10K_0402_5%

R365

10K_0402_5%

12
1 2
1 2
1 2
1 2

1 2
1 2
1 2

3.5 k reserve for choose

1 2
1 2

Compal Electronics, Inc.

Alviso(1 of 5)

1

PLTRST_MCH# <19>

+2.5VS

12

12

850Monday, October 04, 2004

of

+VCCP

+2.5VS

0.0

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>

T38 PAD

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_MA[0..13]<13>

DDR_A_CAS#<13>
DDR_A_RAS#<13>

T36 PAD T33 PAD
T35 PAD

DDR_A_WE#<13>

B B

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4

AD3

AM8
AM4

AE5

AN8
AM5
AH1
AE4

AJ2

AJ1

U5C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

ALVISO_BGA1257

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D0

AG35

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_A_D[0..63] <13>

T34 PAD

DDR_B_BS#0<14>
DDR_B_BS#1<14>

T37 PAD

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>
DDR_B_RAS#<14>

DDR_B_WE#<14>

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AF34
AK32

AJ28
AK23
AM10

AH6

AF35
AK33
AK28

AJ23

AL10

AH7

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

AK5
AE7
AB7

AF8
AB4

AF7
AB5

U5D

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

ALVISO_BGA1257

AE31

SBDQ0

AE32

SBDQ1

AG32

SBDQ2

AG36

SBDQ3

AE34

SBDQ4

AE33

SBDQ5

AF31

SBDQ6

AF30

SBDQ7

AH33

SBDQ8

AH32

SBDQ9

AK31

SBDQ10

AG30

SBDQ11

AG34

SBDQ12

AG33

SBDQ13

AH31

SBDQ14

AJ31

SBDQ15

AK30

SBDQ16

AJ30

SBDQ17

AH29

SBDQ18

AH28

SBDQ19

AK29

SBDQ20

AH30

SBDQ21

AH27

SBDQ22

AG28

SBDQ23

AF24

SBDQ24

AG23

SBDQ25

AJ22

SBDQ26

AK22

SBDQ27

AH24

SBDQ28

AH23

SBDQ29

AG22

SBDQ30

AJ21

SBDQ31

AG10

SBDQ32

AG9

SBDQ33

AG8

SBDQ34

AH8

SBDQ35

AH11

SBDQ36

AH10

SBDQ37

AJ9

SBDQ38

AK9

SBDQ39

AJ7

SBDQ40

AK6

SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR SYSTEM MEMORY B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

LA-2361

950Monday, October 04, 2004

1

0.0

of

5

+2.5VS

R29 3K_0402_5%@

1 2

R30

1 2

12

BIA
BK_EN

3K_0402_5%@

R428

0_0402_5%

1 2

CLK_DDC2
DAT_DDC2

1 2

R429

255_0402_1%

LCTLA_CLK
LCTLB_DAT
LCD_CLK
LCD_DAT
EN_LCDVDD

LVDS_AC­LVDS_AC+
LVDS_BC­LVDS_BC+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

1@

R392

D D

Y/G<17>
COMP/B<17>
C/R<17>

C C

B B

R396 100K_0402_1%

R404100K_0402_1%

CLK_MCH_3GPLL#<18>
CLK_MCH_3GPLL<18>

12

1@

1@

R32

R33

150_0402_1%

150_0402_1%

CLK_DDC2<17>
DAT_DDC2<17>
CRT_BLU<17>

CRT_GRN<17>
CRT_RED<17>
VSYNC<17>

HSYNC<17>

BIA<16,32,34>

BK_EN<16>

1 2
1 2

LCD_CLK<16>
LCD_DAT<16>
EN_LCDVDD<16>

12

R3781.5K_0402_1%

LVDS_AC-<16>
LVDS_AC+<16>
LVDS_BC-<16>
LVDS_BC+<16>

LVDS_A0-<16>
LVDS_A1-<16>
LVDS_A2-<16>

LVDS_A0+<16>
LVDS_A1+<16>
LVDS_A2+<16>

LVDS_B0-<16>
LVDS_B1-<16>
LVDS_B2-<16>

LVDS_B0+<16>
LVDS_B1+<16>
LVDS_B2+<16>

12

1@

12

R34

150_0402_1%

4.99K_0603_1%

U5G

H24
H25

AB29
AC29

A15
C16
A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

ALVISO_BGA1257

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

4

EXP_COMPI

EXP_ICOMPO

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

PCI - EXPRESS GRAPHICS

EXP_TXP1/SDVOB_GREEN

EXP_TXP5/SDVOC_GREEN

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP1/SDVO_INT

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0/SDVOB_RED#

EXP_TXN3/SDVOB_CLKN

EXP_TXN4/SDVOC_RED#

EXP_TXN7/SDVOC_CLKN

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0/SDVOB_RED

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

R40

24.9_0603_1%

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_TXN[0..15]

PEG_TXP[0..15]

3

+1.5VS_PCIE

PEG_RXN[0..15] <16>

PEG_RXP[0..15] <16>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

PEG_TXN[0..15] <16>

PEG_TXP[0..15] <16>

+2.5VS

2

1 2
1 2
1 2
1 2
1 2
1 2

LCD_CLK

R3622.2K_0402_5%

LCD_DAT

R3632.2K_0402_5%

LCTLA_CLK

R3852.2K_0402_5%

LCTLB_DAT

R3642.2K_0402_5%

CLK_DDC2

R3602.2K_0402_5%

DAT_DDC2

R3612.2K_0402_5%

1

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

LA-2361

10 50Monday, October 04, 2004

1

0.0

of

5

U5F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

C392

C391

2

2.2U_0805_10V6K

4.7U_0805_6.3V6K

1

C29

C C

0.47U_0603_16V7K

2

1

1

C74

C28

2

2

0.47U_0603_16V7K

CHB1608U301_0603

+1.5VS

B B

1 2

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C52

2

0.22U_0603_10V7K

0.22U_0603_10V7K

ALVISO_BGA1257

+1.5VS_DPLLA

L20

330U_D2E_2.5VM

1

C345

C330

1

+

2

2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

0.1U_0402_16V4Z

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C413

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

Note: Place near chip.

10U_1206_6.3V6M

C135

C127

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C412

2

2

C429

10U_1206_6.3V6M

C408

+2.5V

4

W=20 mils

U5E

+VCCP

0.1U_0402_16V7K

0.1U_0402_16V4Z

C468

+2.5V

0.1U_0402_16V7K

C420

C393

+1.5VS_DPLLA
+1.5VS_DPLLB

0.1U_0402_16V4Z

1

2

1

C388

2

10U_1206_6.3V6M

+1.5VS

+1.5VS_HPLL
+1.5VS_MPLL

0.1U_0402_16V4Z

1

2

1

2

C130

1

2

C443

C478

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
C465

C475

1

1

2

2

330U_D2E_2.5VM

1

+

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C418

C411

2

2

1

1

T29

VCC0

R29

VCC1

N29

VCC2

M29

VCC3

K29

VCC4

J29

1

2

VCC5

V28

VCC6

U28

VCC7

T28

VCC8

R28

VCC9

P28

VCC10

N28

VCC11

M28

VCC12

L28

VCC13

K28

VCC14

J28

VCC15

H28

VCC16

G28

VCC17

V27

VCC18

U27

VCC19

T27

VCC20

R27

VCC21

P27

VCC22

N27

VCC23

M27

VCC24

L27

VCC25

K27

VCC26

J27

VCC27

H27

VCC28

K26

VCC29

H26

VCC30

K25

VCC31

J25

VCC32

K24

VCC33

K23

VCC34

K22

VCC35

K21

VCC36

W20

VCC37

U20

VCC38

T20

VCC39

K20

VCC40

V19

VCC41

U19

VCC42

K19

VCC43

W18

VCC44

V18

VCC45

T18

VCC46

K18

VCC47

K17

VCC48

AC1

VCCD_HMPLL1

AC2

VCCD_HMPLL2

B23

VCCA_DPLLA

C35

VCCA_DPLLB

AA1

VCCA_HPLL

AA2

VCCA_MPLL

ALVISO_BGA1257

VCC_SYNC

1

C30

2

10U_1206_6.3V6M

3

POWER

+2.5VS

12

12

1

C371

2

0.1U_0402_16V4Z

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

R28
0_0402_5%

R31

0_0402_5%@

1

C355

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

2

0.1U_0402_16V4Z

1@

R736 0_0603_5%

1 2

R739 0_0603_5%

1 2

1@

+2.5VS

R740 0_0603_5% 1@

1 2

4.7U_0805_6.3V6K

1

C473

C131

2

0.1U_0402_16V4Z

VCC_SYNC

C367

0.1U_0402_16V4Z

+3VS

1

2

C366

0.022U_0402_16V7K

1

1

C372

2

2

0.1U_0402_16V4Z

+1.5VS_PM
+2.5VS_PM

C329

+1.5VS_PCIE

1

+

2

100U_D2_6.3VM

+2.5VS

1

1

2

2

C363

0.022U_0402_16V7K

1

1

2

2

0.022U_0402_16V7K

+1.5VS

+2.5VS

1

+

2

C341

1

2

0.1U_0402_16V4Z

R737 0_0603_5%2@

1 2

R738 0_0603_5%2@

1 2

+2.5VS_LVDSPM

C340

0.1U_0402_16V4Z

1

C380

2

10U_1206_6.3V6M

C353

1

2

C452

220U_D2_4VM

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

2

1

Close B26,B25,A25

+1.5VS

1

1

2

2

C349

C339 0.022U_0402_16V7K

0.1U_0402_16V4Z

+2.5VS

1

C433

2

10U_1206_6.3V6M

C399

+1.5VS_PM

0.1U_0402_16V4Z

1

C354

2

C336 0.022U_0402_16V7K

R741
0_0603_5%

2@

1 2

R134

0.5_0805_1%

1 2

1

1

C126

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

C346

3GRLL_R

1

C365

0.1U_0402_16V4Z

2

0.01U_0402_16V7K

CHB1608U301_0603

+2.5VS_PM

1

C352

2

0.1U_0402_16V4Z

L14

L26

L13

L9

0_0603_5%

1

2

12

0_0603_5%

12

0_0603_5%

+1.5VS+1.5VS_3GPLL

12

C128

12

C334

10U_1206_6.3V6M

1

2

0.1U_0402_16V4Z

+2.5VS+2.5VS_3GBG

+2.5VS

1

C342

2

0.1U_0402_16V4Z

+1.5VS

C438

0.1U_0402_16V4Z

1

C31

0.1U_0402_16V4Z

2

1

2

+1.5VS+1.5VS_DDRDLL

1

C140

2

1

2

0.1U_0402_16V4Z

CHB1608U301_0603

+1.5VS

A A

1 2

330U_D2E_2.5VM

0.1U_0402_16V4Z

1

C348

C347

1

+

2

2

5

+1.5VS

CHB1608U301_0603

1 2

+1.5VS_DPLLB

L19

+1.5VS_HPLL

L11

C81

0.1U_0402_16V4Z

330U_D2E_2.5VM

1

C404

+

2

+1.5VS

1

2

4

CHB1608U301_0603

1 2

+1.5VS_MPLL

L23

1

1

+

C403

C409

2

2

0.1U_0402_16V4Z

330U_D2E_2.5VM

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(4 of 5)

LA-2361

11 50Monday, October 04, 2004

1

0.0

of

5

4

3

2

1

+VCCP

AA12
AA13

AA14
AB14

AA15
AB15

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

M12
N12

R12
U12
W12
M13

N13
R13
U13
W13

M14
N14

R14
U14
W14

M15
N15

R15
U15
W15

M16
N16

R16
U16
W16

R17

R21

W25
M26

N26
R26
U26
W26

L12

P12
T12
V12
L13

P13
T13
V13

Y12
Y13
L14

P14
T14
V14
Y14

L15

P15
T15
V15
Y15

L16

P16
T16
V16
Y16

Y17

Y21

Y22

Y23

Y24

Y25

Y26

V25
L26

P26
T26
V26

5

U5H

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO_BGA1257

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

D D

C C

B B

A A

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+2.5V

+VCCP

U5I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257

AD2

VSS256

AE2

VSS255

AH2

VSS254

AL2

VSS253

AN2

VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

A3

C3
AA3
AB3
AC3

AJ3

C4

H4

L4
P4
U4
Y4

AF4
AN4

E5

W5
AL5

AP5

B6

J6

L6
P6
T6

AA6
AC6
AE6

AJ6

G7

V7

AA7
AG7
AK7
AN7

C8
E8

L8
P8
Y8

AL8

A9
H9
K9
T9
V9

AA9
AC9
AE9
AH9
AN9
D10

L10
Y10

AA10

F11

H11

Y11

ALVISO_BGA1257

4

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

U5J

AL24

VSS267

AN24

VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128

W27

VSS127

AA27

VSS126

AB27

VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

VSS

Title

Size Document Number Rev

LA-2361

Date: Sheet

AF27

AG27

AJ27
AL27

AN27

E28

W28
AA28
AB28
AC28

A29
D29
E29
F29

G29

H29

L29
P29
U29
V29

W29
AA29
AD29
AG29

AJ29

AM29

C30

Y30
AA30
AB30
AC30
AE30
AP30

D31

E31

F31

G31

H31

J31

K31

L31

M31

N31

P31

R31

T31

U31

V31

W31
AD31
AG31

AL31

A32
C32

Y32
AA32
AB32

ALVISO_BGA1257

2

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

VSS58

K33

VSS57

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

B35

VSS37

D35

VSS36

E35

VSS35

F35

VSS34

G35

VSS33

H35

VSS32

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

VSS8

H37

VSS7

K37

VSS6

M37

VSS5

P37

VSS4

T37

VSS3

V37

VSS2

Y37

VSS1

AG37

VSS0

Compal Electronics, Inc.

Alviso(5 of 5)

12 50Monday, October 04, 2004

1

0.0

of

A

B

C

D

E

F

G

H

DDR_A_MA[0..13]<9>

DDR_A_MA13
DDR_A_MA12
DDR_A_MA11

DDR_A_MA9
DDR_A_MA7
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3

DDR_A_MA10

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
DDR_A_MA5

DDR_A_WE#

DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#

DDR_A_BS#1

DDR_CKE0

DDR_CKE1

DDR_SCS#1

DDR_SCS#0

C

DDR_A_D4
DDR_A_D1
DDR_A_D5
DDR_A_D2
DDR_A_DM0
DDR_A_D3
DDR_A_DQS0
DDR_A_D0
DDR_A_D7
DDR_A_D6

DDR_A_D13
DDR_A_D11
DDR_A_D10
DDR_A_D8
DDR_A_D9
DDR_A_DM1
DDR_A_D12
DDR_A_DQS1
DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21
DDR_A_D16
DDR_A_D17
DDR_A_DQS2
DDR_A_D18
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D19

DDR_A_D28
DDR_A_D24
DDR_A_D29
DDR_A_DQS3
DDR_A_D25
DDR_A_DM3
DDR_A_D31
DDR_A_D26
DDR_A_D30
DDR_A_D27

DDR_A_D36
DDR_A_D37
DDR_A_D33
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D38
DDR_A_D39
DDR_A_DQS4
DDR_A_DM4

DDR_A_D44
DDR_A_D41
DDR_A_D40
DDR_A_D45
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D46
DDR_A_D47
DDR_A_DM5

DDR_A_D53
DDR_A_D48
DDR_A_D52
DDR_A_D49
DDR_A_D55
DDR_A_D54
DDR_A_D50
DDR_A_D51
DDR_A_DM6
DDR_A_DQS6

DDR_A_D58
DDR_A_D63
DDR_A_D61
DDR_A_D57
DDR_A_D56
DDR_A_DM7
DDR_A_D59
DDR_A_D62
DDR_A_D60
DDR_A_DQS7

A

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]

1 2

R647 10_0402_5%

1 2

R257 10_0402_5%

1 2

R256 10_0402_5%

1 2

R650 10_0402_5%

1 2

R255 10_0402_5%

1 2

R253 10_0402_5%

1 2

R648 10_0402_5%

1 2

R646 10_0402_5%

1 2

R254 10_0402_5%

1 2

R649 10_0402_5%

1 2

R252 10_0402_5%

1 2

R248 10_0402_5%

1 2

R655 10_0402_5%

1 2

R651 10_0402_5%

1 2

R251 10_0402_5%

1 2

R250 10_0402_5%

1 2

R652 10_0402_5%

1 2

R653 10_0402_5%

1 2

R654 10_0402_5%

1 2

R249 10_0402_5%

1 2

R657 10_0402_5%

1 2

R246 10_0402_5%

1 2

R656 10_0402_5%

1 2

R247 10_0402_5%

1 2

R658 10_0402_5%

1 2

R659 10_0402_5%

1 2

R245 10_0402_5%

1 2

R660 10_0402_5%

1 2

R243 10_0402_5%

1 2

R244 10_0402_5%

1 2

R662 10_0402_5%

1 2

R661 10_0402_5%

1 2

R241 10_0402_5%

1 2

R663 10_0402_5%

1 2

R242 10_0402_5%

1 2

R240 10_0402_5%

1 2

R238 10_0402_5%

1 2

R664 10_0402_5%

1 2

R665 10_0402_5%

1 2

R239 10_0402_5%

1 2

R666 10_0402_5%

1 2

R237 10_0402_5%

1 2

R667 10_0402_5%

1 2

R236 10_0402_5%

1 2

R233 10_0402_5%

1 2

R669 10_0402_5%

1 2

R234 10_0402_5%

1 2

R670 10_0402_5%

1 2

R668 10_0402_5%

1 2

R235 10_0402_5%

1 2

R274 10_0402_5%

1 2

R679 10_0402_5%

1 2

R273 10_0402_5%

1 2

R680 10_0402_5%

1 2

R681 10_0402_5%

1 2

R271 10_0402_5%

1 2

R683 10_0402_5%

1 2

R682 10_0402_5%

1 2

R270 10_0402_5%

1 2

R272 10_0402_5%

1 2

R685 10_0402_5%

1 2

R268 10_0402_5%

1 2

R684 10_0402_5%

1 2

R269 10_0402_5%

1 2

R266 10_0402_5%

1 2

R687 10_0402_5%

1 2

R688 10_0402_5%

1 2

R265 10_0402_5%

1 2

R267 10_0402_5%

1 2

R686 10_0402_5%

1 2

R690 10_0402_5%

1 2

R261 10_0402_5%

1 2

R264 10_0402_5%

1 2

R692 10_0402_5%

1 2

R263 10_0402_5%

1 2

R262 10_0402_5%

1 2

R693 10_0402_5%

1 2

R260 10_0402_5%

1 2

R689 10_0402_5%

1 2

R691 10_0402_5%

B

DDR_D[0..63]

DDR_DM[0..7]

DDR_DQS[0..7]

DDR_D4
DDR_D1
DDR_D5
DDR_D2
DDR_DM0
DDR_D3
DDR_DQS0
DDR_D0
DDR_D7
DDR_D6

DDR_D13
DDR_D11
DDR_D10
DDR_D8
DDR_D9
DDR_DM1
DDR_D12
DDR_DQS1
DDR_D14
DDR_D15

DDR_D20
DDR_D21
DDR_D16
DDR_D17
DDR_DQS2
DDR_D18
DDR_DM2
DDR_D22
DDR_D23
DDR_D19

DDR_D28
DDR_D24
DDR_D29
DDR_DQS3
DDR_D25
DDR_DM3
DDR_D31
DDR_D26
DDR_D30
DDR_D27

DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38
DDR_D39
DDR_DQS4
DDR_DM4

DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5

DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6

DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7

DDR_D[0..63] <14>
DDR_DM[0..7] <14>
DDR_DQS[0..7] <14>

+1.25VS

1 2

R673 56_0402_5%

1 2

R296 56_0402_5%

1 2

R282 56_0402_5%

1 2

R674 56_0402_5%

1 2

R675 56_0402_5%

1 2

R281 56_0402_5%

1 2

R280 56_0402_5%

1 2

R676 56_0402_5%

1 2

R677 56_0402_5%

1 2

R278 56_0402_5%

1 2

R294 56_0402_5%

1 2

R288 56_0402_5%

1 2

R279 56_0402_5%

1 2

R295 56_0402_5%

1 2

R293 56_0402_5%

1 2

R286 56_0402_5%

1 2

R276 56_0402_5%

1 2

R287 56_0402_5%

1 2

R277 56_0402_5%

1 2

R283 56_0402_5%

1 2

R672 56_0402_5%

1 2

R275 56_0402_5%

1 2

R678 56_0402_5%

DDR_A_D[0..63]<9>
DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>

1 1

2 2

3 3

4 4

DDR_A_MA[0..13]

DDR_CLK0<8>
DDR_CLK0#<8>

DDR_CKE1<8>

DDR_A_BS#0<9>
DDR_A_WE#<9>

DDR_SCS#0<8>

CK_SDATA<14,18>
CK_SCLK<14,18>

D

+2.5V

JDIMM2

1

VREF

3

DDR_D0
DDR_D4

DDR_DQS0
DDR_D6

DDR_D2
DDR_D8

DDR_D12
DDR_DQS1

DDR_D14
DDR_D10

DDR_D16
DDR_D20

DDR_DQS2
DDR_D18

DDR_D22
DDR_D24

DDR_D28
DDR_DQS3

DDR_D26
DDR_D30

DDR_CKE1 DDR_CKE0
DDR_A_MA13
DDR_A_MA12
DDR_A_MA9

DDR_A_MA7
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_SCS#0 DDR_SCS#1

DDR_D36
DDR_D33

DDR_DQS4
DDR_D35

DDR_D39
DDR_D41

DDR_D45
DDR_DQS5

DDR_D46
DDR_D42

DDR_D52
DDR_D53

DDR_DQS6
DDR_D54

DDR_D50
DDR_D60

DDR_D56
DDR_DQS7

DDR_D57
DDR_D59

CK_SDATA
CK_SCLK

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

A11

A8
A6

A4
A2
A0

S1#

DU

DU

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_D1
DDR_D5

DDR_DM0
DDR_D7

DDR_D3
DDR_D13

DDR_D9
DDR_DM1

DDR_D15
DDR_D11

DDR_D17
DDR_D21

DDR_DM2
DDR_D19

DDR_D23
DDR_D25

DDR_D29
DDR_DM3

DDR_D27
DDR_D31

DDR_A_MA11
DDR_A_MA8

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_A_CAS#

DDR_D37
DDR_D32

DDR_DM4
DDR_D38

DDR_D34
DDR_D44

DDR_D40
DDR_DM5

DDR_D43
DDR_D47

DDR_D49
DDR_D48

DDR_DM6
DDR_D55

DDR_D51
DDR_D61

DDR_D58
DDR_DM7

DDR_D63
DDR_D62

+SDREF_DIMM

KLINK_5763-3-111

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

F

R227

12

0_0402_5%

+SDREF

1

C237

0.1U_0402_16V4Z

2

DDR_CKE0 <8>

DDR_A_BS#1 <9>
DDR_A_RAS# <9>
DDR_A_CAS# <9>

DDR_SCS#1 <8>

DDR_CLK1# <8>
DDR_CLK1 <8>

Dell-Compal Confidential

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT0

LA-2361

G

of

13 50Monday, October 04, 2004

H

0.0

A

DDR_D[0..63]

DDR_DM[0..7]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

DDR_DQS[0..7]

+1.25VS

DDR_D4
DDR_D1
DDR_D5
DDR_D2

DDR_DM0

1 1

DDR_D3

DDR_DQS0

DDR_D0
DDR_D7
DDR_D6

DDR_D13
DDR_D11
DDR_D10

DDR_D8
DDR_D9

DDR_DM1

DDR_D12

DDR_DQS1

DDR_D14
DDR_D15

DDR_D20
DDR_D21
DDR_D16
DDR_D17

DDR_DQS2

DDR_D18

DDR_DM2

DDR_D22
DDR_D23
DDR_D19

DDR_D28
DDR_D24
DDR_D29

DDR_DQS3

2 2

DDR_D25

DDR_DM3

DDR_D31
DDR_D26
DDR_D30
DDR_D27

DDR_D36
DDR_D37
DDR_D33
DDR_D32
DDR_D34
DDR_D35
DDR_D38

DDR_D39
DDR_DQS4
DDR_DM4

1 2

R597 56_0402_5%

1 2

R596 56_0402_5%

1 2

R215 56_0402_5%

1 2

R600 56_0402_5%

1 2

R598 56_0402_5%

1 2

R599 56_0402_5%

1 2

R214 56_0402_5%

1 2

R216 56_0402_5%

1 2

R212 56_0402_5%

1 2

R213 56_0402_5%

1 2

R211 56_0402_5%

1 2

R210 56_0402_5%

1 2

R602 56_0402_5%

1 2

R601 56_0402_5%

1 2

R209 56_0402_5%

1 2

R603 56_0402_5%

1 2

R208 56_0402_5%

1 2

R605 56_0402_5%

1 2

R207 56_0402_5%

1 2

R604 56_0402_5%

1 2

R607 56_0402_5%

1 2

R205 56_0402_5%

1 2

R606 56_0402_5%

1 2

R206 56_0402_5%

1 2

R204 56_0402_5%

1 2

R203 56_0402_5%

1 2

R608 56_0402_5%

1 2

R202 56_0402_5%

1 2

R610 56_0402_5%

1 2

R609 56_0402_5%

1 2

R200 56_0402_5%

1 2

R201 56_0402_5%

1 2

R612 56_0402_5%

1 2

R199 56_0402_5%

1 2

R611 56_0402_5%

1 2

R613 56_0402_5%

1 2

R197 56_0402_5%

1 2

R198 56_0402_5%

1 2

R614 56_0402_5%

1 2

R615 56_0402_5%

1 2

R195 56_0402_5%

1 2

R584 56_0402_5%

1 2

R196 56_0402_5%

1 2

R583 56_0402_5%

1 2

R194 56_0402_5%

1 2

R193 56_0402_5%

1 2

R587 56_0402_5%

1 2

R586 56_0402_5%

1 2

R192 56_0402_5%

1 2

R585 56_0402_5%

R183 56_0402_5%
R574 56_0402_5%
R182 56_0402_5%
R573 56_0402_5%
R181 56_0402_5%
R179 56_0402_5%
R577 56_0402_5%
R180 56_0402_5%
R576 56_0402_5%
R575 56_0402_5%

R579 56_0402_5%
R178 56_0402_5%
R176 56_0402_5%
R582 56_0402_5%
R174 56_0402_5%
R578 56_0402_5%
R177 56_0402_5%
R175 56_0402_5%
R581 56_0402_5%
R580 56_0402_5%

R169 56_0402_5%
R591 56_0402_5%
R173 56_0402_5%
R595 56_0402_5%
R172 56_0402_5%
R170 56_0402_5%
R171 56_0402_5%
R594 56_0402_5%
R592 56_0402_5%
R593 56_0402_5%

+1.25VS

1 2

R189 56_0402_5%

1 2

R565 56_0402_5%

1 2

R188 56_0402_5%

1 2

R168 56_0402_5%

1 2

R566 56_0402_5%

1 2

R567 56_0402_5%

3 3

1 2

R167 56_0402_5%

1 2

R185 56_0402_5%

1 2

R569 56_0402_5%

1 2

R186 56_0402_5%

1 2

R568 56_0402_5%

1 2

R562 56_0402_5%

1 2

R187 56_0402_5%

1 2

R190 56_0402_5%

1 2

R184 56_0402_5%

1 2

R166 56_0402_5%

1 2

R571 56_0402_5%

1 2

R572 56_0402_5%

1 2

R570 56_0402_5%

1 2

R191 56_0402_5%

1 2

R564 56_0402_5%

1 2

R165 56_0402_5%

1 2

R563 56_0402_5%

DDR_B_MA12
DDR_B_MA11
DDR_B_MA9
DDR_B_MA7
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA10
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA4
DDR_B_MA5
DDR_B_MA13

DDR_B_WE#
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_BS#1

DDR_CKE3
DDR_CKE2
DDR_SCS#2
DDR_SCS#3

DDR_D44
DDR_D41
DDR_D40
DDR_D45
DDR_DQS5
DDR_D43
DDR_D42
DDR_D46
DDR_D47
DDR_DM5

DDR_D53
DDR_D48
DDR_D52
DDR_D49
DDR_D55
DDR_D54
DDR_D50
DDR_D51
DDR_DM6
DDR_DQS6

DDR_D58
DDR_D63
DDR_D61
DDR_D57
DDR_D56
DDR_DM7
DDR_D59
DDR_D62
DDR_D60
DDR_DQS7

B

DDR_D[0..63] <13>
DDR_DM[0..7] <13>
DDR_DQS[0..7] <13>

C

DDR_B_MA[0..13]<9>

DDR_B_MA[0..13]

DDR_CLK3<8>
DDR_CLK3#<8>

DDR_CKE3<8>

DDR_B_BS#0<9>
DDR_B_WE#<9>

DDR_SCS#2<8>

CK_SDATA<13,18>
CK_SCLK<13,18>

DDR_B_MA13
DDR_B_MA12
DDR_B_MA9

DDR_B_MA7
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_SCS#2

DDR_D0
DDR_D4

DDR_DQS0
DDR_D6

DDR_D2
DDR_D8

DDR_D12
DDR_DQS1

DDR_D14
DDR_D10

DDR_D16
DDR_D20

DDR_DQS2
DDR_D18

DDR_D22
DDR_D24

DDR_D28
DDR_DQS3

DDR_D26
DDR_D30

DDR_CKE3

DDR_D36
DDR_D33

DDR_DQS4
DDR_D35

DDR_D39
DDR_D41

DDR_D45
DDR_DQS5

DDR_D46
DDR_D42

DDR_D52
DDR_D53

DDR_DQS6
DDR_D54

DDR_D50
DDR_D60

DDR_D58
DDR_DQS7

DDR_D57
DDR_D59

CK_SDATA

CK_SCLK

+3VS

+2.5V

JDIMM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

D

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DDR_CKE2

DDR_B_BS#1
DDR_B_RAS#DDR_B_BS#0
DDR_B_CAS#DDR_B_WE#
DDR_SCS#3

DDR_D1
DDR_D5

DDR_DM0
DDR_D7

DDR_D3
DDR_D13

DDR_D9
DDR_DM1

DDR_D15
DDR_D11

DDR_D17
DDR_D21

DDR_DM2
DDR_D19

DDR_D23
DDR_D25

DDR_D29
DDR_DM3

DDR_D27
DDR_D31

DDR_B_MA11
DDR_B_MA8

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_D37
DDR_D32

DDR_DM4
DDR_D38

DDR_D34
DDR_D44

DDR_D40
DDR_DM5

DDR_D43
DDR_D47

DDR_D49
DDR_D48

DDR_DM6
DDR_D55

DDR_D51
DDR_D61

DDR_D56
DDR_DM7

DDR_D63
DDR_D62

+3VS

+SDREF_DIMM

1

2

DDR_CKE2 <8>

DDR_SCS#3 <8>

DDR_CLK4# <8>
DDR_CLK4 <8>

C188

0.1U_0402_16V4Z

DDR_B_BS#1 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>

E

KLINK_5763-2-111

4 4

Dell-Compal Confidential

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-2361

0.0

of

14 50Monday, October 04, 2004

E

A

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

B

C

D

E

1 1

1

C190

0.1U_0402_16V4Z

2

+2.5V +2.5V

1

C227

0.1U_0402_16V4Z

2

1

C191

0.1U_0402_16V4Z

2

1

C267

0.1U_0402_16V4Z

2

1

C189

0.1U_0402_16V4Z

2

1

C266

0.1U_0402_16V4Z

2

1

C193

0.1U_0402_16V4Z

2

1

C263

0.1U_0402_16V4Z

2

1

C218

0.1U_0402_16V4Z

2

1

C262

0.1U_0402_16V4Z

2

1

C217

0.1U_0402_16V4Z

2

1

C214

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

1

+

C163
150U_D2_6.3VM

2

1

C215

0.1U_0402_16V4Z

2

1

+

C238
150U_D2_6.3VM

2

1

C230

0.1U_0402_16V4Z

2

1

C229

0.1U_0402_16V4Z

2

1

C228

0.1U_0402_16V4Z

2

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

3 3

+1.25VS

1

C253

0.1U_0402_16V4Z

2

+1.25VS

1

C243

0.1U_0402_16V4Z

2

+1.25VS

1

C250

0.1U_0402_16V4Z

2

1

C252

0.1U_0402_16V4Z

2

1

C242

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C578

0.1U_0402_16V4Z

2

1

C248

0.1U_0402_16V4Z

2

1

C590

0.1U_0402_16V4Z

2

1

C579

0.1U_0402_16V4Z

2

1

C576

0.1U_0402_16V4Z

2

1

C589

0.1U_0402_16V4Z

2

1

C580

0.1U_0402_16V4Z

2

1

C585

0.1U_0402_16V4Z

2

1

C588

0.1U_0402_16V4Z

2

1

C256

0.1U_0402_16V4Z

2

1

C583

0.1U_0402_16V4Z

2

1

C247

0.1U_0402_16V4Z

2

1

C255

0.1U_0402_16V4Z

2

1

C584

0.1U_0402_16V4Z

2

1

C246

0.1U_0402_16V4Z

2

1

C254

0.1U_0402_16V4Z

2

1

C575

0.1U_0402_16V4Z

2

1

C245

0.1U_0402_16V4Z

2

1

C582

0.1U_0402_16V4Z

2

1

C586

0.1U_0402_16V4Z

2

1

C244

0.1U_0402_16V4Z

2

1

C581

0.1U_0402_16V4Z

2

1

C587

0.1U_0402_16V4Z

2

+1.25VS

1

C200

0.1U_0402_16V4Z

2

4 4

1

C201

0.1U_0402_16V4Z

2

A

1

C202

0.1U_0402_16V4Z

2

1

C531

0.1U_0402_16V4Z

2

1

C530

0.1U_0402_16V4Z

2

B

1

C529

0.1U_0402_16V4Z

2

1

C535

0.1U_0402_16V4Z

2

1

C544

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C536

0.1U_0402_16V4Z

2

C

1

C208

0.1U_0402_16V4Z

2

D

Compal Electronics, Inc.

Title

DDR SODIMM Decoupling

Size Document Number Rev

Custom

LA-2361

Date: Sheet

E

of

15 50Monday, October 04, 2004

0.0

5

PEG_TXN15 PEG_A_TXN_15
PEG_TXP15

PEG_TXN14
PEG_TXP14

D D

C C

B B

A A

PEG_TXN13
PEG_TXP13

PEG_TXN12
PEG_TXP12

PEG_TXN11
PEG_TXP11

PEG_TXN10
PEG_TXP10

PEG_TXN9
PEG_TXP9 PEG_A_TXP_9

PEG_TXN7
PEG_TXP7

PEG_TXN6
PEG_TXP6

PEG_TXN5
PEG_TXP5

PEG_TXP4

PEG_TXP3
PEG_TXN2

PEG_TXP2
PEG_TXN1

PEG_TXP1

PEG_TXN0
PEG_TXP0

B+

+3VS

+2.5V

Modify for 1.8vs move to VGA BD

0_0603_5%2@

1 2
1 2

0_0603_5%2@

+3VS

R329
R328

C97 0.1U_0402_16V4Z2@

C93 0.1U_0402_16V4Z2@

C87 0.1U_0402_16V4Z2@

C82 0.1U_0402_16V4Z2@

C79 0.1U_0402_16V4Z2@

C76 0.1U_0402_16V4Z2@

C72 0.1U_0402_16V4Z2@

C70 0.1U_0402_16V4Z2@

C66 0.1U_0402_16V4Z2@

C64 0.1U_0402_16V4Z2@

C59 0.1U_0402_16V4Z2@

C56 0.1U_0402_16V4Z2@

C54 0.1U_0402_16V4Z2@

C50 0.1U_0402_16V4Z2@

C48 0.1U_0402_16V4Z2@

C43 0.1U_0402_16V4Z2@

2

1

C309

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

B+P

B+P

2

C307

1

2@

2@

0.1U_0603_50V4Z

0.1U_0603_50V4Z

1

1

C310

2

2

0.047U_0402_16V4Z

0.047U_0402_16V4Z

5

C94 0.1U_0402_16V4Z2@

1 2

C88 0.1U_0402_16V4Z2@

1 2

C83 0.1U_0402_16V4Z2@

1 2

C80 0.1U_0402_16V4Z2@

1 2

C77 0.1U_0402_16V4Z2@

1 2

C73 0.1U_0402_16V4Z2@

1 2

C71 0.1U_0402_16V4Z2@

1 2

C67 0.1U_0402_16V4Z2@

1 2

C65 0.1U_0402_16V4Z2@

1 2

C61 0.1U_0402_16V4Z2@

1 2

C57 0.1U_0402_16V4Z2@

1 2

C55 0.1U_0402_16V4Z2@

1 2

C51 0.1U_0402_16V4Z2@

1 2

C49 0.1U_0402_16V4Z2@

1 2

C44 0.1U_0402_16V4Z2@

1 2

C39 0.1U_0402_16V4Z2@

1 2

JVGAP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

ACES_85205-10002@

2

C313

1

0.1U_0603_50V4Z

1

C311

2

0.047U_0402_16V4Z

C308

2@

SMB_EC_CK2<32,34>
SMB_EC_DA2<32,34>

SMBCLK_VGA<17>
SMBDAT_VGA<17>

2

1

SUSP#<24,32,33,34,37,42>
C/R_VGA<17>
COMP/B_VGA<17>
Y/G_VGA<17>

VSYNC_VGA<17>
HSYNC_VGA<17>

VGA_BLU<17>

VGA_GRN<17>

VGA_RED<17>

BK_EN<10>
BKOFF#<32,34>

C314

2@

0.1U_0603_50V4Z

BIA<10,32,34>

PEG_A_TXP_15
PEG_A_TXN_14

PEG_A_TXP_14
PEG_A_TXN_13

PEG_A_TXP_13

PEG_A_TXN_12
PEG_A_TXP_12

PEG_A_TXN_11
PEG_A_TXP_11

PEG_A_TXN_10
PEG_A_TXP_10

PEG_A_TXN_9

PEG_A_TXN_8PEG_TXN8
PEG_A_TXP_8PEG_TXP8

PEG_A_TXN_7
PEG_A_TXP_7

PEG_A_TXN_6
PEG_A_TXP_6

PEG_A_TXN_5
PEG_A_TXP_5

PEG_A_TXN_4PEG_TXN4
PEG_A_TXP_4

PEG_A_TXN_3PEG_TXN3
PEG_A_TXP_3

PEG_A_TXN_2
PEG_A_TXP_2

PEG_A_TXN_1
PEG_A_TXP_1

PEG_A_TXN_0
PEG_A_TXP_0

SMB_EC_CK2
SMB_EC_DA2

VSYNC_VGA
HSYNCVGA

VGA_BLU
VGA_GRN
VGA_RED

SMBCLK_VGA
SMBDAT_VGA

4

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140

U1

1

A

2

B

1@

2

@

4

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140

FOX_QTS0140A-30212@

+5VS

5

P

O

G

3

NC7ST08P5X_SC70-5

+3VS

5

U2

P

A

Y

G

NC7SZ14M5X_SOT23-5

3

R7

@

1 2

0_0402_5%

JVGA1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139

DISPLAYOFF#

4

INVT_PWM<32,34>

4

3

12

1@

R335

2.2K_0402_5%

LCDP_CLK

2N7002_SOT23

B+

1@

LVDS_A0+
LVDS_A0­LVDS_A1+
LVDS_A1­LVDS_A2­LVDS_A2+

LVDS_AC­LVDS_AC+

LVDS_B0­LVDS_B0+
LVDS_B2­LVDS_B2+
LVDS_B1­LVDS_B1+

LVDS_BC­LVDS_BC+

+LCDVDD

1@

D

Q22

S

1@

R27
100K_0402_5%

1@

R357

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

1

1

3

3

5

5

7

7

9

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12
PEG_RXP12

PEG_RXN11
PEG_RXP11

PEG_RXN10
PEG_RXP10

PEG_RXN9
PEG_RXP9

PEG_RXN8
PEG_RXP8

PEG_RXN7
PEG_RXP7

PEG_RXN6
PEG_RXP6

PEG_RXN5
PEG_RXP5

PEG_RXN4
PEG_RXP4

PEG_RXN3
PEG_RXP3

PEG_RXN2
PEG_RXP2

PEG_RXN1
PEG_RXP1

PEG_RXN0
PEG_RXP0

RUNPWROK

PLTRST_VGA#
THERMATRIP_VGA#
SUSP

CLK_PCIE_VGA#
CLK_PCIE_VGA

1@

1 2

R3

1 2

0_0402_5%

R4

0_0402_5%

LCD_CLK<10>

LCD EEPROM

LCD_DAT<10>

RUNPWROK <32>
PLTRST_VGA# <19,21>
THERMATRIP_VGA# <32,34>
SUSP <37,43,44>

CLK_PCIE_VGA# <18>
CLK_PCIE_VGA <18>

DAC_BRIG <32,34>
BKOFF# <32,34>

INVT_PWM <32,34>
+5VS
+5VALW

+12VALW

PWM

3

+2.5VS

2.2K_0402_5%

2N7002_SOT23

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

LVDS_A0+<10>
LVDS_A0-<10>
LVDS_A1+<10>
LVDS_A1-<10>
LVDS_A2-<10>
LVDS_A2+<10>

LVDS_AC-<10>
LVDS_AC+<10>

LVDS_B0-<10>
LVDS_B0+<10>
LVDS_B2-<10>
LVDS_B2+<10>
LVDS_B1-<10>
LVDS_B1+<10>

LVDS_BC-<10>
LVDS_BC+<10>

1@

R336

Q20

2N7002_SOT23

D

S

13

1@

G

2

G

2

13

D

S

1@

Q21

EN_LCDVDD<10>

C27

0.1U_0603_50V4Z

PEG_TXP[0..15]

+3VS

12

LCDP_DAT

2

R344
470_0402_5%

1@

13

2

G

2

1@

1
2
3 6

2N7002_SOT23

75K_0402_5%

1@

+5VS

PEG_TXP[0..15] <10>

PEG_RXN[0..15]

2

ACES_88328-4000

42

R356
100K_0402_5%

13

Q24
DTC124EK_SC59

Q1
FDS4435_SO8

1@

4

Q25

D

1 3

1@

2

1

41

GND

GND
40

38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

1@

0.1U_0402_16V4Z

+12VALW +LCDVDD +3VS

1@

13

D

1@

2

G

S

8
7

5

C23

0.1U_0603_50V4Z

S

G

PEG_RXN[0..15] <10>

Title

Size Document Number Rev

Date: Sheet

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11

9
7
5
3
1

JLVDS1

R355
100K_0402_5%

Q23
2N7002_SOT23

INVPWR_B+

1@

<Title>

LA-2361

Custom

SMB_EC_CK1
SMB_EC_DA1

+3VS

INVPWR_B+++

1

1@

C320

2

1@

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN[0..15]<10>

LCDP_CLK
LCDP_DAT

PWM
DISPLAYOFF#

1

1@

0.1U_0402_16V4Z

2

SI2302DS_SOT23

C321

0.1U_0402_16V4Z

SMB_EC_CK1 <32,33,34,38,39>
SMB_EC_DA1 <32,33,34,38,39>

R722

1 2

0_0805_5%1@

C318

Q26

D

S

13

1@

G

1@

2

R354
150K_0402_5%

1@

PEG_RXP[0..15]

PEG_TXN[0..15]

1

16 50Monday, October 04, 2004

Inverter

DAC_BRIG <32,34>

INVPWR_B+

+LCDVDD

C323

0.1U_0402_16V4Z

PEG_RXP[0..15] <10>

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

0.0

of

5

4

3

2

1

1@

R25 0_0402_5%

C/R<10>

C/R_VGA<16>

D D

COMP/B<10>

COMP/B_VGA<16>

Y/G<10>

Y/G_VGA<16>

C C

B B

HSYNC_VGA<16>

HSYNC<10>

VSYNC_VGA<16>

VSYNC<10>

A A

R340 0_0402_5%

R341 0_0402_5%

1 2

R26 0_0402_5%

1 2

2@

1@

R23 0_0402_5%

1 2

R24 0_0402_5%

1 2

2@

1@

R21 0_0402_5%

1 2

R22 0_0402_5%

1 2

2@

VGA_RED<16>

VGA_GRN<16>

VGA_BLU<16>

CRT_RED<10>

CRT_GRN<10>

CRT_BLU<10>

2@

R342 0_0402_5%

1 2

R343 0_0402_5%

1 2

1@

2@

1 2

1 2

1@

R16 0_0402_5%

R14 0_0402_5%

R12 0_0402_5%

R11 0_0402_5%

R13 0_0402_5%

R15 0_0402_5%

2@

1 2

2@

1 2

2@

1 2

1 2

1@

1 2

1@

1 2

1@

CRT_HSYNC

CRT_VSYNC

C/R_C

75_0603_1%

COMP/B_C

75_0603_1%

Y/G_C

75_0603_1%

+5VS

12

R19

12

R18

12

R17

CRT_R

CRT_G

CRT_B

5

1

P

4

OE#

A2Y

G

U25

3

SN74AHCT1G125GW_SOT353-5

5

1

P

4

OE#

A2Y

G

U24

3

SN74AHCT1G125GW_SOT353-5

1

2

1

2

1

2

1K_0402_5%

1 2

1 2

L8
FLM1608081R8K_0603

C22
82P_0402_50V8J

1 2

L7
FLM1608081R8K_0603

C21
82P_0402_50V8J

1 2

L6
FLM1608081R8K_0603

C20
82P_0402_50V8J

DDC_MONID0

MSEN#<32,34>

3.3P_0603_50V8J

R339

75_0603_1%

C14

@

R10

MSEN#

3.3P_0603_50V8J

1

2

12

+5VS

1

2

2

C17
82P_0603_50V8J

1

2

C16
82P_0603_50V8J

1

2

C15
82P_0603_50V8J

1

@

1

1

C13

2

2

75_0603_1%

12

12

R9

C305

0.1U_0402_16V4Z

C12

@

3.3P_0603_50V8J

L3

1 2

FBM-11-160808-121-T_0603

L4

1 2

FBM-11-160808-121-T_0603

L5

1 2

FBM-11-160808-121-T_0603

R8
75_0603_1%

FBM-11-160808-121-T_0603

FBM-11-160808-121-T_0603

SVIDEO_C

SVIDEO_CVBS

SVIDEO_Y

1

D9

DAN217_SC59

2

@

CRTR

CRTG

CRTB

1

C8

3.3P_0603_50V8J

2

1 2

L1

1 2

L2

3

D12

DAN217_SC59@

1

2

3

D8

DAN217_SC59

@

1

2

1

C5

27P_0402_50V8J

2

D11

2

DAN217_SC59@

0.1U_0402_16V4Z

1

2

3

C9

3.3P_0603_50V8J

1

3

C304

1

D7

DAN217_SC59

2

@

1

C6

27P_0402_50V8J

2

100P_0402_50V8J

D10

+5VS

1

2

3

1

2

1

2

3

+3VS

DAN217_SC59@

2K_0402_5%

C306

0.1U_0402_16V4Z

+2.5VS

C10

3.3P_0603_50V8J

1

C3

2

100P_0402_50V8J

+5VS

R321

1

2

RB751V_SOD323

1

C303

2

100P_0402_50V8J

12

D20

1

C4

2

12

R325
2K_0402_5%

+5VS

21

1

C302
100P_0402_50V8J

2

0_0402_5%

2

G

1 3

D

Q18
2N7002_SOT23

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

FOX_DZ11A91-L7

+3VS

R330

S

1 3

D

16
17

12

2

JTV1

7
6
5
4
3
2
1

SUYIN_33007SR-07T1-C

+2.5VS

2.7K_0402_5%

R331

1 2

G

Q19

S

2N7002_SOT23

CRT Connector

12

R334

2.7K_0402_5%

R322

0_0402_5% 2@

1 2

R333

0_0402_5%

1 2

R326

0_0402_5% 2@

1 2

R332

0_0402_5%

1 2

SMBDAT_VGA <16>

1@

1@

DAT_DDC2 <10>

SMBCLK_VGA <16>

CLK_DDC2 <10>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

TV_OUT and CRT connector

LA-2361

1

17 50Monday, October 04, 2004

0.0

of

5

+3VS

ICH_SMBDATA<21>

D D

ICH_SMBCLK<21>

ICH_SMBDATA

+3VS

ICH_SMBCLK

D

1 3

1 3

D

D

1

3

G

S

2

2N7002

12

12

R119

10K_0402_5%

S

Q4
2N7002_SOT23

G

2

2

G

Q5
2N7002_SOT23

S

CK_VDD_A CK_VDD_REF

C139

R121

10K_0402_5%

1

2

4.7U_0805_6.3V6K

CK_SDATA

CK_SCLK

0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

C C

*

0

0

0

1

1

1

00

0

1

0

1

11

0

0

0

1

0

1

0

11

Table : ICS 954201 / Cypress CY28411

+VCCP

CLKSEL0

CLKSEL1

R486

1 2

1 2

R482
10K_0402_5%

@

1 2

5

10K_0402_5%@

R488
1K_0402_5%

+VCCP

1 2

1 2

R531
10K_0402_5%

@

R533
1K_0402_5%

1 2

R524
10K_0402_5%

@

B B

CPU_BSEL0<6>

A A

CPU_BSEL1<6>

MHz

266

133

200

166

333

100

400

SRC
MHz

100 33.30

100

100

100

100

100

100

RESERVED

MCH_CLKSEL0 <8>

PCI
MHz

33.3

33.3

CLK_14M_CODEC<29>

33.3

33.3

33.3

33.3

MCH_CLKSEL1 <8>

CLK_48M_ICH<21>

CLK_33M_1394<27>
CLK_33M_CBS<26>
CLK_33M_LPCSIO<31>
CLK_33M_MPCI<28>
CLK_33M_LAN<24>
CLK_33M_ICH<19>
CLK_33M_LPCEC<32,34>

4

CK_SDATA <13,14>

CK_SCLK <13,14>

CK_VDD_48

1

1

2

C508

0.047U_0402_16V7K

+3VS

R513
10K_0402_5%

1 2

R512
10K_0402_5%

@

1 2

2

C134

4.7U_0805_6.3V6K

33P_0402_50V8J

33P_0402_50V8J

CLK_14M_CODEC

CLKSEL2

4

1

2

C133

C476

12

X3 14.318MHZ_20P_1BX14318CC1A

C487

12

CLKSEL1
CLKSEL0

CLK_33M_CBS
CLK_33M_LPCSIO
CLK_33M_MPCI
CLK_33M_LAN
CLK_33M_ICH
CLK_33M_LPCEC

+3VS

C456

0.1U_0402_16V4Z

0.047U_0402_16V7K

Place crystal within
500 mils of CK410

12

+3VS

1 2

L25

CHB1608U301_0603

1

2

CHB1608U301_0603

R511 33_0402_5%

L24

C123

0.047U_0402_16V7K

12

R49333_0402_1%

+CK_VDD_MAIN2

12

12
12
12
12
12
12
12

1 2

R131 475_0603_1%

1 2

1

2

CK_XTAL_IN

CK_XTAL_OUT

R501 12.1_0402_1%
R502 12.1_0402_1%
R497 33_0402_5%
R498 33_0402_5%
R491 33_0402_5%
R508 33_0402_5%
R506 33_0402_5%

1 2

R509 10K_0402_5%

3

+CK_VDD_MAIN

2

C457
10U_0805_10V4Z

1

1

C137

0.047U_0402_16V7K

2

1

C523

0.047U_0402_16V7K

2

2

1

C511

0.047U_0402_16V7K

2

Place near each pin
W>40 mil

R145

2.2_0603_5%

1 2

CPU_STOP#

CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#

VTT_PWRGD#/PD

1

C466

0.047U_0402_16V7K

2

CK_VDD_A

37

VDD_A

38

VSS_A

55

PCI_STOP#

54

41

CPU1

40

CPU1#

44

CPU0

43

CPU0#

36
35

33

SRC6

32

SRC6#

31

SRC5

30

SRC5#

26

SRC4

27

SRC4#

24

SRC3

25

SRC3#

22

SRC2

23

SRC2#

19

SRC1

20

SRC1#

17

SRC0

18

SRC0#

14

DOT96

15

DOT96#

10
52

REF

Place near CK410M

H_STP_PCI#
H_STP_CPU#

CK_CPU1

1 2

R527 33_0402_5%

CK_CPU1#

1 2

R534 33_0402_5%

CK_CPU0
CK_CPU0#

CK_CPU2
CK_CPU2#

SCR5
SRC5#

SRC4
SRC4#

SRC1
SRC1# CLK_PCIE_ICH#

SRC0
SRC0# SSC_DREFCLK#

CLKREF

1 2

R514 33_0402_5%

1 2

R521 33_0402_5%

1 2

R539 33_0402_5%

1 2

R544 33_0402_5%

1 2

R549 33_0402_5%

1 2

R554 33_0402_5%

1 2

R553 33_0402_5%

1 2

R558 33_0402_5%

1 2

R543 33_0402_5%

1 2

R548 33_0402_5%

1 2

R142 33_0402_5%1@

1 2

R538 33_0402_5%1@

1 2

R520 33_0402_5%

1 2

R526 33_0402_5%

1@
1@

1 2

R499 12.1_0402_1%

1 2

R503 12.1_0402_1%

2

2

C444
10U_0805_10V4Z

1

U31

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

CK_VDD_REF

1 2

R126
1_0603_5%

CK_VDD_48

1 2

R128

2.2_0603_5%

CLKSEL2CLK_48M_ICH

PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1

PCICLKF0

CK_SCLK

CK_SDATA

CLKIREF

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

VDD_CPU

48

VDD_REF

11

VDD_48

50

XTAL_IN

49

XTAL_OUT

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

5

PCI5

4

PCI4

3

PCI3

56

PCI2

9

PCIF1

8

PCIF0/ITP_EN

46

SCLOCK

47

SDATA

39

IREF

13

VSS_48

29

VSS_SRC

2

VSS_PCI0

45

VSS_CPU

51

VSS_REF

6

VSS_PCI1

ICS954206AG

1

C479

0.047U_0402_16V7K

2

1

C505

0.047U_0402_16V7K

2

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH

SSC_DREFCLK

CLK_14M_ICH

CLK_14M_SIO

1

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_ITP
CLK_ITP#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

SSC_DREFCLK
SSC_DREFCLK#

H_STP_PCI# <21>
H_STP_CPU# <21,45>

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_ITP
CLK_ITP#

DREFCLK
DREFCLK#

Title

Size Document Number Rev

Date: Sheet

DREFCLK
DREFCLK#

CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>

CLK_ITP <5>
CLK_ITP# <5>

CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>

CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>

CLK_PCIE_ICH <21>
CLK_PCIE_ICH# <21>

SSC_DREFCLK <8>
SSC_DREFCLK# <8>

DREFCLK <8>

+3VS

DREFCLK# <8>

R742

10K_0402_5%

CLK_14M_ICH <21>

Q45 2N7002_SOT23

CLK_14M_SIO <31>

Compal Electronics, Inc.

Clock Generator

LA-2361

12

R528 49.9_0402_1%

12

R535 49.9_0402_1%

12

R515 49.9_0402_1%

12

R522 49.9_0402_1%

12

R540 49.9_0402_1%

12

R545 49.9_0402_1%

1 2

R552 49.9_0402_1%

1 2

R557 49.9_0402_1%

1 2

R542 49.9_0402_1%

1 2

R547 49.9_0402_1%

1 2

R550 49.9_0402_1%

1 2

R555 49.9_0402_1%

1 2

R146 49.9_0402_1%

1 2

1@

R537 49.9_0402_1%

1 2

1@

R519 49.9_0402_1%

1 2

1@

R525 49.9_0402_1%

1@

12

13

D

S

R744

1 2

2

G

10K_0402_5%

0.047U_0402_16V4Z

1

C635

18 50Monday, October 04, 2004

1

2

VGATE <8,21,45>

0.0

of

5

+3VS

D D

C C

B B

+3VS

+3VS

+3VS

+3VS

+3VALW

RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_IRDY#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#

PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQH#
PCI_PIRQC#

R4808.2K_0402_5%

1 2

R4758.2K_0402_5%

1 2

R848.2K_0402_5%

1 2

R728.2K_0402_5%

1 2

R4478.2K_0402_5%

1 2

R708.2K_0402_5%

1 2

R888.2K_0402_5%

1 2

R4738.2K_0402_5%

1 2

R4488.2K_0402_5%

1 2

R4788.2K_0402_5%

1 2

R868.2K_0402_5%

1 2
1 2

R724 10K_0402_1%

ICH_PME#

PCI_PIRQE#
PCI_PIRQF#

PCI_PIRQA#

PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#

PCI_REQ2#
PCI_REQ5#
PCI_REQ6#

BATT1

PCI_AD[0..31]<24,26,27,28>

PCI_FRAME#<24,26,27,28>

CHGRTC

2

12

PCI_PIRQA#<26>
PCI_PIRQB#<26>

+RTCVCC

3

1

BAS40-04_SOT23
D16

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27PCI_PIRQG#
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PLTRST#

U7B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

+3V

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

14

1

P

A

2

B

G

7

+3V

14

4

P

A

5

B

G

7

L5

REQ[0]#

C1

GNT[0]#

B5

REQ[1]#

B6

GNT[1]#

M5

REQ[2]#

F1

GNT[2]#

B8

REQ[3]#

C8

GNT[3]#

F7
E7
E8
F6
B7
D8

J6

C/BE[0]#

H6

C/BE[1]#

G4

C/BE[2]#

G2

C/BE[3]#

A3

IRDY#

E1

PAR

R2

PCIRST#

C3

DEVSEL#

E3

PERR#

C5

PLOCK#

G5

SERR#

J1

STOP#

J2

TRDY#

R5

PLTRST#

G6

PCICLK

P6

PME#

D9
C7
C6
M3

U29A

PCIRSTB1#

3

O

74VHC08MTC_TSSOP14

U29B

O

74VHC08MTC_TSSOP14

PCIRSTB2#

6

3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#

PCI_REQ6#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLTRST#
CLK_33M_ICH

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

C350

0.1U_0402_16V4Z

12

R443

33_0402_5%

1 2

R446

33_0402_5%

1 2

R445

33_0402_5%

1 2

PCI_REQ0# <24>

PCI_GNT0# <24>

PCI_REQ1# <26>

PCI_GNT1# <26>

PCI_REQ2# <27>

PCI_GNT2# <27>

PCI_REQ3# <28>

PCI_GNT3# <28>

PCI_C_BE0# <24,26,27,28>
PCI_C_BE1# <24,26,27,28>
PCI_C_BE2# <24,26,27,28>
PCI_C_BE3# <24,26,27,28>

PCI_IRDY# <24,26,27,28>
PCI_PAR <24,26,27,28>

PCI_DEVSEL# <24,26,27,28>
PCI_PERR# <24,26,27,28>

PCI_SERR# <24,26,28>

PCI_STOP# <24,26,27,28>
PCI_TRDY# <24,26,27,28>

PLTRST# <21>
CLK_33M_ICH <18>

PCI_PIRQE# <27>
PCI_PIRQF# <24>
PCI_PIRQG# <28>
PCI_PIRQH# <28>

PLTRST_VGA# <16,21>

PLTRST_SIO# <31>

PLTRST_MCH# <8>

R756

1 2

0_0402_5%

Q46

2N7002_SOT23

D

S

13

@

G

2

R757

12

10K_0402_5%

@

ICH_PME#

+3V

2

ICH_PME# <24,26,27,28,31,32,34>

+3V

14

U29D

13

P

A

11

O

12

B

G

74VHC08MTC_TSSOP14

7

1

CLK_33M_ICH

1 2

CLK_ICH_TERM

1

2

R472
10_0402_5%

@

C410

8.2P_0402_50V8J~D@

R758

ML1220T13RE

PCI_PCIRST#

A A

5

4

@

0_0402_5%

1 2

+3V

10

A

9

B

14

U29C

P

8

O

G

74VHC08MTC_TSSOP14

7

R389

PCIRSTB3#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

33_0402_5%

1 2

3

PCIRST# <24,26,27,28,32,34>

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(1/4)

LA-2361

19 50Monday, October 04, 2004

1

of

0.0

5

C62

12P_0603_50V8J

12

32.768KHZ_12.5P_MC-306

1 2

12

+RTCVCC

IAC_RST#<29>

10P_0402_50V8J@

X1

Package

D D

+RTCVCC

12

R469
1M_0402_5%

INTRUDER#

IAC_BITCLK<29,35>

C C

IAC_SDATO_MDC<35>

B B

IAC_SYNC_MDC<35>

IAC_RST#_MDC<35>

9.6X4.06 mm

R96
33_0402_5%

1 2

R92
33_0402_5%

1 2

R105
33_0402_5%

1 2

+3VS +3VS

12

<BOM Structure>

C68

12P_0603_50V8J

INTRUDER#

IAC_SYNC<29>

R483
10_0402_5%

@

1 2

IAC_SDATO<29>

ICH_AC_BITCLK_TERM

2

C458

1

ICH_AC_SDOUT_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

R114

4.7K_0402_5%

IDE_HDIORDY IDE_HIRQ

R467
180K_0402_5%

CMOS_CLR1
SHORT PADS~D

1

1

C400

0.1U_0402_16V4Z

1 2

12

R504
10K_0402_5%

ICH_RTCX1

ICH_RTCX2

1 2

2

IAC_SDATAI1<29>
IAC_SDATAI2<35>

IDE_HIORDY<23>
IDE_HIRQ<23>

IDE_HDACK#<23>
IDE_HDIOW#<23>
IDE_HDIOR#<23>

2

1 2
1 2

12

R68

10M_0402_5%

R474 0_0402_5%

1 2

R95

1 2

33_0402_5%

@

R9133_0402_5%
R10433_0402_5%

4

R471

0_0402_5%

ICH_RTCRST#
INTRUDER#

1 2

12

ICH_AC_SYNC_R
ICH_AC_RST_R#
IAC_SDATAI1

IAC_SDATAI2

ICH_AC_SDOUT_R

R101

24.9_0603_1%

IDE_HDIORDY
IDE_HIRQ
IDE_HDDACK#
IDE_HDIOW#
IDE_HDIOR#

AA2
AA3

AA5

D12
D11

C13
C12

C11

C10

AC19

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

AG11
AF11

AF16
AB16
AB15
AC14
AE16

Y1
Y2

B12
F13
F12
B11
E12

E11

E13

B9
A10
F11

F10
B10

C9

U7A

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH6_BGA609

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

A20GATE

A20M#

LAN

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

RCIN#

STPCLK#

THRMTRIP#

DCS1#
DCS3#

SATAAC-97/AZALIA

PIDE

DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

INIT#
INTR

NMI

SMI#

DA[0]
DA[1]
DA[2]

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]

P2
N3
N5
N4

N6
P4

P3

AF22
AF23

AE27
AE24

AD27
AF24
AG25
AG26

AE22
AF27
AG24

AD23
AF25

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

3

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ0#
LPC_LDRQ1#

LPC_LFRAME#

GATEA20
A20M#

CPUSLP#

DPSLP#
FERR#
H_PWRGOOD
IGNNE#
ICH4_INIT#

INTR

KBRST#
NMI

SMI#
STPCLK#
THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

LPC_LAD[0..3] <31,32,34>

Note : R169 Do not populate for
Dothan-A, Populte for Dothan-B.

LPC_LDRQ0#
LPC_LDRQ1# <31>

LPC_LFRAME# <31,32,34>

R135 0_0402_5%
R161 0_0402_5%
R551 0_0402_5%

R162 0_0402_5%
R144 56_0402_5%

R148 0_0402_5%
R159 0_0402_5%

R139 0_0402_5%

R147 0_0402_5%
R151 0_0402_5%

R160 0_0402_5%

R496
0_0402_5%

12
12
12

12
12

12
12

12

12
12

12

1 2

IDE_HDA0 <23>
IDE_HDA1 <23>
IDE_HDA2 <23>

IDE_HDCS1# <23>
IDE_HDCS3# <23>

IDE_HDD[0..15] <23>

1 2

C461

R541
56_0402_5%

2

1

33P_0402_50V8J

H_THERMTRIP#

IDE_HDREQIDE_DDREQ

H_A20M#
H_CPUSLP#
H_DPRSLP#DPRSLP#

H_DPSLP#

H_IGNNE#
H_INIT#

H_INTR

H_NMI
H_SMI#

H_STPCLK#

2

GATEA20 <32,34>

H_INIT# <5>

KBRST# <32,34>

IDE_HDREQ <23>

H_A20M# <5>
H_CPUSLP# <5,8>
H_DPRSLP# <5>

H_DPSLP# <5>
H_FERR# <5>
H_PWRGOOD <5>
H_IGNNE# <5>

H_INTR <5>

H_NMI <5>
H_SMI# <5>

H_STPCLK# <5>

+CPU_CORE

+VCCP

+VCCP

H_THERMTRIP#<5,8>

R143

H_FERR#

H_DPRSLP#

56_0402_5%

R546

56_0402_5%

Note : R423 must be stuff for
Dothan-A, no-stuff for Dothan-B.

Note : R168 populate 56 ohm for
Dothan-A, Populte zero ohm for
Dothan-B.

R762
47K_0402_5%

1 2

R561
47K_0402_5%@

1 2

1 2

C526

@

0.68U_0603_10V6K

1 2

R494
75_0402_5%

2

B

1

C

Q39
2SC2411K_SC59

E

3

H_THERMTRIP#

1

+VCCP

12

12

MAINPWRON <39,41,44>

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ICH6(2/4)

LA-2361

20 50Monday, October 04, 2004

1

0.0

of

5

D D

+3V

+3V

leakage

2.2K_0402_5%

2.2K_0402_5%
R460

R461

1 2

1 2

ICH_SMBDATA<18>
ICH_SMBCLK<18>

C C

B B

CLK_14M_ICH<18>

CLK_48M_ICH<18>

+3VS

R516

1 2

1K_0402_5%

@

PM_DPRSLPVR

5

R523

100K_0402_5%

12

A A

May need pulldown for DPRSLPVR in case
the ICH6m does not set this value in time
for boot.

10K_0402_5%

10K_0402_5%

R450

R449

1 2

1 2

ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK0
ICH_SMLINK1

ACIN<32,34,40,41>

+3V

(PCI Express Wake Event)

R761 10K_0402_5%

1 2

CLKRUN#

CLK_14M_ICH

CLK_48M_ICH

R487

@

C455

1 2

CK_14M_ICH_TERM

2

1

@

10_0402_5%

@

1 2

CK_48M_ICH_TERM

2

1

4.7P_0402_50V8C

R556

10_0402_5%

C520

4.7P_0402_50V8C

@

+3VS

R729 0_0402_5%@

12

4

1 2

D

1 3

Q47

G

2

PLTRST_VGA#<16,19>

R125
10K_0402_5%

+3V

+3V

+3V

+3V

+3V

4

S

2N7002_SOT23

1 2

1 2

1 2

1 2

1 2

+3V

SIRQ<26,31,32>

R457
10K_0402_5%

R69
10K_0402_5%

R456
10K_0402_5%@

R455
10K_0402_5%

R451
680_0402_5%

SPKR<30>

PM_BMBUSY#<8>

+3VS

EC_SMI#<32,34>

LID_SWOUT#<32,34>
EC_SCI#<32,34>

H_STP_PCI#<18>

H_STP_CPU#<18,45>

R507 10K_0402_5%@

1 2
1 2

R536 0_0402_5%

IDE_HRESET#<23>
IDE_DRESET#<23>

EC_FLASH#<33>

CLKRUN#<24,26,28,31,32,34>

VGATE<8,18,45>

SLP_S3#<32,34>
SLP_S4#<32,34>
SLP_S5#<32,34>

ICH_PWRGD<32,34>
PM_DPRSLPVR<45>
ICH_BATLOW#<32,34>
PWRBTN_OUT#<32,34>

PLTRST#<19>
RSMRST#<32,34>

LINKALERT#

SYS_RESET#

ACINA

ICH_BATLOW#

ICH_PCIE_WAKE#

+3VS

12

R117

10K_0402_5%

R120 33_0402_5%@

SIRQ

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR

T30

SYS_RESET#
PM_BMBUSY#

R510 10K_0402_5%

1 2

EC_SMI#

EC_SCI#
H_STP_PCI#

H_STP_CPU#

CLKRUN#

ICH_PCIE_WAKE#

R746 0_0402_5%

1 2

SIO_THRM#
VGATE
CLK_14M_ICH
CLK_48M_ICH

T32

ICH_SUSCLK

PAD

@

SLP_S3#
SLP_S4#
SLP_S5#

ICH_PWRGD
PM_DPRSLPVR
ICH_BATLOW#
PWRBTN_OUT#
PLTRST#
RSMRST#

3

+3V

12

R71

10K_0402_5%

ICH_RI#

PAD

@

12

10K_0402_5%

R75

+3VS

+3VS

+3VS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ACINA

3

T2

AF17
AE18
AF18
AG18

Y4

W5

Y5

W4

U6

AG21

F8

W3

U2
AD19
AE19

R1

W6

M2

R6
AC21
AB21
AD22

AD20
AD21

V3

P5

R3

T3
AF19
AF20
AC18

U5
AB20
AC20
AF21

E10
A27

V6

T4

T5

T6

AA1

AE20

V2

U1

V5

Y3

12

10K_0402_5%

R459

R529

8.2K_0402_5%

1 2

R130
10K_0402_5%

1 2

R518
10K_0402_5%

1 2

U7C

RI#
SATA[0]GP/GPI[26]

SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

SUS_STAT#/LPCPD#
SYS_RESET#
BM_BUSY#/GPI[6]
GPI[7]

GPI[8]
SMBALERT#/GPI[11]
GPI[12]

GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]

GPO[21]
GPO[23]

GPIO[24]
GPIO[25]

GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
RSMRST#

ICH6_BGA609

SIO_THRM#

MCH_SYNC#

SIRQ

H25

PERn[1]

H24

PERp[1]

G27

PETn[1]

G26

PETp[1]

K25

PERn[2]

K24

PERp[2]

J27

PETn[2]

J26

PETp[2]

M25

PERn[3]

M24

PERp[3]

L27

PETn[3]

L26

PETp[3]

GPIO

DMI_ZCOMP

DMI_IRCOMP

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

CLOCK

USB

POWER MGT

D15

2 1

RB751V_SOD323

R725 39K_0402_5%

P24

PERn[4]

P23

PERp[4]

N27

PETn[4]

N26

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETp[4]

T25

DMI[0]RXN

T24

DMI[0]RXP

R27

DMI[0]TXN

R26

DMI[0]TXP

V25

DMI[1]RXN

V24

DMI[1]RXP

U27

DMI[1]TXN

U26

DMI[1]TXP

Y25

DMI[2]RXN

Y24

DMI[2]RXP

W27

DMI[2]TXN

W26

DMI[2]TXP

AB24

DMI[3]RXN

AB23

DMI[3]RXP

AA27

DMI[3]TXN

AA26

DMI[3]TXP

AD25

DMI_CLKN

AC25

DMI_CLKP

F24
F23
C23

D23
C25
C24

C27

OC[0]#

B27

OC[1]#

B26

OC[2]#

C26

OC[3]#

C21

USBP[0]N

D21

USBP[0]P

A20

USBP[1]N

B20

USBP[1]P

D19

USBP[2]N

C19

USBP[2]P

A18

USBP[3]N

B18

USBP[3]P

E17

USBP[4]N

D17

USBP[4]P

B16

USBP[5]N

A16

USBP[5]P

C15

USBP[6]N

D15

USBP[6]P

A14

USBP[7]N

B14

USBP[7]P

A22

USBRBIAS#

B22

USBRBIAS

1 2

@
@
@
@

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP

OVCUR#4
OVCUR#5
OVCUR#6
OVCUR#7

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3

USBP0­USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

EC_THRM# <32,34>

2

DMI_RXN0 <8>
DMI_RXP0 <8>

DMI_RXN1 <8>
DMI_RXP1 <8>

DMI_RXN2 <8>
DMI_RXP2 <8>

DMI_RXN3 <8>
DMI_RXP3 <8>

R517 24.9_0603_1%

1 2

22.6_0603_1%

2

1 2

T21PAD
T40PAD
T23PAD
T22PAD

DMI_TXN0 <8>
DMI_TXP0 <8>

DMI_TXN1 <8>
DMI_TXP1 <8>

DMI_TXN2 <8>
DMI_TXP2 <8>

DMI_TXN3 <8>
DMI_TXP3 <8>

CLK_PCIE_ICH# <18>
CLK_PCIE_ICH <18>

OVCUR#4 <36>

OVCUR#0 <36>
OVCUR#1 <36>

OVCUR#3 <36>

R141

1

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3

OVCUR#4
OVCUR#5
OVCUR#6
OVCUR#7

+1.5VS

closed to 500 mils

USBP0- <36>
USBP0+ <36>
USBP1- <36>
USBP1+ <36>
USBP2- <35>
USBP2+ <35>
USBP3- <36>
USBP3+ <36>
USBP4- <36>
USBP4+ <36>
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-2361

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

ICH6(3/4)

1

RP6

10K_0804_8P4R_5%

RP10

10K_0804_8P4R_5%

+3V

21 50Monday, October 04, 2004

0.0

of

5

Near PIN F27(C968),

L27 0_0603_5%

+1.5VRUN_L

ICH_V5REF_RUN

2

C485

0.1U_0402_16V4Z

1

ICH_V5REF_SUS

2

C506

0.1U_0402_16V4Z

1

1 2

2

C439

0.1U_0402_16V4Z

1

+1.5VS

D D

+3VS

+5VS

D4

RB751V_SOD323

1 2

+3V+5V

D5

RB751V_SOD323

1 2

21

2

C115
1U_0603_10V4Z

1

21

2

C136
1U_0603_10V4Z

1

R103

10_0402_5%

R129

10_0402_5%

C C

Replacing by this circuit?

Note: Intel will update design guide.

R97
10_0402_5%

@

R127
10_0402_5%

@

U8 APL5301-15DC_3P

Vin2Vout

CHB1608U301_0603

5

ICH_V5REF_RUN

ICH_V5REF_SUS

3

GND

1

L28

1 2

+1.5VR

1

2

2

C517

1

0.1U_0402_16V4Z

C110

0.1U_0402_16V4Z

ICH6_VCCPLL

1

C519

2

0.01U_0402_16V7K

Near PIN
AC27

+3VS

+3V

1

C111

0.1U_0402_16V4Z

2

R559

1 2

1_0402_5%

1 2

1 2

+5V

B B

+5VALW

+1.5VS

A A

P27(C949), AB27(C950)

1

+

2

C524

220U_D2_4VM

+1.5VS

Near PIN AG5

+1.5VS

Near PIN AG9

2

C514

1

0.1U_0402_16V4Z

Near PIN
E26, E27

+3V

Near PIN A17

+1.5VS

4

2

2

C521

C513

1

1

0.1U_0402_16V4Z

C405

C426

2

C395

1

0.1U_0402_16V4Z

Near PIN AE1

2

C490

1

0.1U_0402_16V4Z

4

2

C501

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

ICH6_VCCPLL

+3VS

+3VS

+3V

2

C489

1

3

+1.5VS

U7E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

ICH6_BGA609

PCIE

SATA

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

PCI/IDE RBP

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]

COREIDE

VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]

PCIUSB

VCC3_3[3]
VCC3_3[2]

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]

USB CORE

VCC1_5[68]
VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]
V5REF[1]

V5REF_SUS

VCCUSBPLL

VCCSUS3_3[20]

VCCRTC

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VS

2

C462

1

2

C396

1

+1.5VR

1

2

C488

0.1U_0402_16V4Z

+1.5VS

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VS
+3V

1

2

C509

C484

0.1U_0402_16V4Z

C394

0.1U_0402_16V4Z

+RTCVCC

+1.5VS

+VCCP

0.1U_0402_16V4Z

+3VS

2

Near PIN

1

AG13, AG16

0.1U_0402_16V4Z

2

2

C425

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VR

2

1

1

2

C440

0.1U_0402_16V4Z

Near PIN U7

+2.5VS

Near PIN AB18

Near PIN AG23

+3VS

+3VS

Near PIN
A2-A6, D1-H1

C435

0.1U_0402_16V4Z

1

2

C486

0.1U_0402_16V4Z

C467

0.1U_0402_16V4Z

1 2

C447

1 2

0.1U_0402_16V4Z

Near PIN AG10

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

C497

0.1U_0402_16V4Z

1 2

C477

0.1U_0402_16V4Z

1 2

C471

0.1U_0402_16V4Z

1 2

C491

0.1U_0402_16V4Z

1 2

C492

0.1U_0402_16V4Z

1 2

C474

0.1U_0402_16V4Z

1 2

C454

0.1U_0402_16V4Z

1 2

C453

0.1U_0402_16V4Z

1 2

C464

0.1U_0402_16V4Z

1 2

C434

0.1U_0402_16V4Z

1 2

C515

0.01U_0402_16V7K

1 2

Near PIN A25

C493

0.01U_0402_16V7K

1 2

Near PIN AA19

+3V

C397

0.1U_0402_16V4Z

1 2

C436

0.1U_0402_16V4Z

1 2

C472

0.1U_0402_16V4Z

1 2

C510

0.1U_0402_16V4Z

1 2

Near PIN A24

2

1

U7D

E27

VSS[172]

Y6

VSS[171]

Y27

VSS[170]

Y26

VSS[169]

Y23

VSS[168]

W7

VSS[167]

W25

VSS[166]

W24

VSS[165]

W23

VSS[164]

W1

VSS[163]

V4

VSS[162]

V27

VSS[161]

V26

VSS[160]

V23

VSS[159]

U25

VSS[158]

U24

VSS[157]

U23

VSS[156]

U15

VSS[155]

U13

VSS[154]

T7

VSS[153]

T27

VSS[152]

T26

VSS[151]

T23

VSS[150]

T16

VSS[149]

T15

VSS[148]

T14

VSS[147]

T13

VSS[146]

T12

VSS[145]

T1

VSS[144]

R4

VSS[143]

R25

VSS[142]

R24

VSS[141]

R23

VSS[140]

R17

VSS[139]

R16

VSS[138]

R15

VSS[137]

R14

VSS[136]

R13

VSS[135]

R12

VSS[134]

R11

VSS[133]

P22

VSS[132]

P16

VSS[131]

P15

VSS[130]

P14

VSS[129]

P13

VSS[128]

P12

VSS[127]

N7

VSS[126]

N17

VSS[125]

N16

VSS[124]

N15

VSS[123]

N14

VSS[122]

N13

VSS[121]

N12

VSS[120]

N11

VSS[119]

N1

VSS[118]

M4

VSS[117]

M27

VSS[116]

M26

VSS[115]

M23

VSS[114]

M16

VSS[113]

M15

VSS[112]

M14

VSS[111]

M13

VSS[110]

M12

VSS[109]

L25

VSS[108]

L24

VSS[107]

L23

VSS[106]

L15

VSS[105]

L13

VSS[104]

K7

VSS[103]

K27

VSS[102]

K26

VSS[101]

K23

VSS[100]

K1

VSS[99]

J4

VSS[98]

J25

VSS[97]

J24

VSS[96]

J23

VSS[95]

H27

VSS[94]

H26

VSS[93]

H23

VSS[92]

G9

VSS[91]

G7

VSS[90]

G21

VSS[89]

G12

VSS[88]

G1

VSS[87]

ICH6_BGA609

Title

Size Document Number Rev

Date: Sheet

GROUND

+RTCVCC

1

2

C401

0.1U_0402_16V4Z

LA-2361

F4

VSS[86]

F22

VSS[85]

F19

VSS[84]

F17

VSS[83]

E25

VSS[82]

E19

VSS[81]

E18

VSS[80]

E15

VSS[79]

E14

VSS[78]

D7

VSS[77]

D22

VSS[76]

D20

VSS[75]

D18

VSS[74]

D14

VSS[73]

D13

VSS[72]

D10

VSS[71]

D1

VSS[70]

C4

VSS[69]

C22

VSS[68]

C20

VSS[67]

C18

VSS[66]

C14

VSS[65]

B25

VSS[64]

B24

VSS[63]

B23

VSS[62]

B21

VSS[61]

B19

VSS[60]

B15

VSS[59]

B13

VSS[58]

AG7

VSS[57]

AG3

VSS[56]

AG22

VSS[55]

AG20

VSS[54]

AG17

VSS[53]

AG14

VSS[52]

AG12

VSS[51]

AG1

VSS[50]

AF7

VSS[49]

AF3

VSS[48]

AF26

VSS[47]

AF12

VSS[46]

AF10

VSS[45]

AF1

VSS[44]

AE7

VSS[43]

AE6

VSS[42]

AE25

VSS[41]

AE21

VSS[40]

AE2

VSS[39]

AE12

VSS[38]

AE11

VSS[37]

AE10

VSS[36]

AD6

VSS[35]

AD24

VSS[34]

AD2

VSS[33]

AD18

VSS[32]

AD15

VSS[31]

AD10

VSS[30]

AD1

VSS[29]

AC6

VSS[28]

AC3

VSS[27]

AC26

VSS[26]

AC24

VSS[25]

AC23

VSS[24]

AC22

VSS[23]

AC12

VSS[22]

AC10

VSS[21]

AB9

VSS[20]

AB7

VSS[19]

AB2

VSS[18]

AB19

VSS[17]

AB10

VSS[16]

AB1

VSS[15]

AA4

VSS[14]

AA16

VSS[13]

AA13

VSS[12]

AA11

VSS[11]

A9

VSS[10]

A7

VSS[9]

A4

VSS[8]

A26

VSS[7]

A23

VSS[6]

A21

VSS[5]

A19

VSS[4]

A15

VSS[3]

A12

VSS[2]

A1

VSS[1]

1

2

C417

0.1U_0402_16V4Z

Compal Electronics, Inc.

ICH6(4/4)

22 50Monday, October 04, 2004

1

0.0

of

A

B

C

D

E

F

G

H

IDE_HDD0
IDE_HDD1
IDE_HDD2

1 1

IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8

IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

+5VHDD

2 2

IDE_HDD[0..15] <20>

IDE_HRESET#<21>

IDE_HDREQ<20>
IDE_HDIOW#<20>
IDE_HDIOR#<20>

IDE_HIORDY<20>
IDE_HDACK#<20>

IDE_HIRQ<20>
IDE_HDA1<20>
IDE_HDA0<20>
IDE_HDCS1#<20>

1 2

R318 10K_0402_5%

HDD Connector

IDE_HRESET#

IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDREQ

IDE_HDIOW#

IDE_HDIOR#

IDE_HIORDY

IDE_HDACK#

IDE_HIRQ

IDE_HDA1
IDE_HDA0
IDE_DCS1#
HDD_ACT#

ALLTOP_C17866-14405

JHDD1

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

GND45GND

INT_CD_L<29>

CD_GNA<29>

1 2

1

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

IDE_HDD8

3

IDE_HDD9

5

IDE_HDD10

7

IDE_HDD11

9

IDE_HDD12

11

IDE_HDD13

13

IDE_HDD14

15

IDE_HDD15

17
19
21
23
25

R308 470_0402_5%

27
29
31
33
35
37
39
41
43

1 2

R310 10K_0402_5%@

1 2

IDE_HDA2
IDE_HCS3#

PDIAG#

IDE_HDA2 <20>
IDE_HDCS3# <20>

+5VHDD

C593 47P_0402_50V8J

R315

@

10K_0402_5%

1 2

R702

4.7K_0402_5%

1 2

SEC_CSEL

IDE_DRESET#<21>

+5VMOD

R703

1 2

10K_0402_5%

IDE_DRESET#

HDD_ACT#

CD-ROM Connector

C595

1 2

47P_0402_25V8K

IDE_HDD7
IDE_HDD6
IDE_HDD5 IDE_HDD11
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDIOW#
IDE_HIORDY

IDE_HIRQ
IDE_HDA1
IDE_HDA0
IDE_DCS1#

+5VMOD

JCDR1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

OCTEK_CDR-50JE2

C594

1 2

47P_0402_25V8K

IDE_HDD8
IDE_HDD9
IDE_HDD10

IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
IDE_HDREQ
IDE_HDIOR#

IDE_HDACK#
PDIAG#

IDE_HDA2
IDE_HDCS3#

INT_CD_R <29>

+5VMOD

Layout Note: W=80 mils

IRQ how to assign

+5VHDD Source

Q17
AO3413_SOT23

+5VS

+12VALW

12

3 3

+5VS

R314
100K_0402_5%

S

+5VHDD

D

13

G

2

Layout Note: Place close to HDD CONN.

1000P_0402_50V7K

0.1U_0402_16V4Z

C293

1

C294

2

1U_0603_10V4Z

1

1

C301

2

C296

2

10U_0805_10V4Z

1

2

HDD_ACT#

HDD_ACT# <33>

R317
470_0402_5%

1 2

13

D

2

G

S

+5VMOD Source

+5VS

4 4

A

Q16
2N7002_SOT23

150K_0603_5%

B

C292

12

0.01U_0402_16V7K

R316

1

2

G

2

S

AO3413_SOT23
Q14

+5VMOD

13

D

Layout Note: Place close to CD-ROM CONN.

1000P_0402_50V7K

0.1U_0402_16V4Z

C281

1

1

C280

2

C278

2

C

10U_0805_10V4Z

1U_0603_10V4Z

1

1

C279

2

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D

E

Title

SATA to PATA BRIDGE & CD-ROM CONN.

Size Document Number Rev

F

Date: Sheet

Compal Electronics, Inc.

LA-2361

G

23 50Monday, October 04, 2004

H

0.0

of

5

2

C75

0.1U_0402_10V6K

+3VALW

D D

C33

1U_0603_10V6K

C C

B B

CLK_PCI_LAN

A A

2

C63

1

1

0.1U_0402_10V6K

1 2

1

0_0805_5%
L10

2

1 2

KC FBM_L11-201209-601LMT 0805

PCI_AD[0..31]<19,26,27,28>

12

R45
10_0402_5%

1

C34

4.7P_0402_50V8B

2

5

R39

@

PCI_AD17

PCIRST#<19,26,27,28,32,34>

CLK_33M_LAN<18>

CLKRUN#<21,26,28,31,32,34>

@

LAN_IO

2

C37

0.1U_0402_10V6K

1

LAN_IO

1

2

PCI_AD[0..31]

PCI_C_BE0#<19,26,27,28>
PCI_C_BE1#<19,26,27,28>
PCI_C_BE2#<19,26,27,28>
PCI_C_BE3#<19,26,27,28>

R65 0_0402_5%

PCI_PAR<19,26,27,28>
PCI_FRAME#<19,26,27,28>
PCI_IRDY#<19,26,27,28>
PCI_TRDY#<19,26,27,28>
PCI_DEVSEL#<19,26,27,28>
PCI_STOP#<19,26,27,28>

PCI_PERR#<19,26,27,28>

PCI_SERR#<19,26,28>
PCI_REQ0#<19>

PCI_GNT0#<19>
PCI_PIRQF#<19>

ICH_PME#<19,26,27,28,31,32,34>

@

LAN_IO

C40
1U_0603_10V6K

1 2

PCIRST#
CLK_PCI_LAN

0_0402_5% @

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R80

LAN_IO

12

1

C85

0.1U_0402_10V6K

2

U4

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100CL_LQFP128

4

closed to chip about 200 mils

1

C86

0.1U_0402_10V6K

2

EEDO

AUX/EEDI

EESK

EECS

LED0
LED1
LED2

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/SMBDATA

NC/M66EN
NC/AVDDH

NC/HV

PCI I/F

NC/HSDAC+

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

NC/GND

CTRL25

RTT3/CRTL18

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

4

3

1

C84

0.1U_0402_10V6K

2

108
109
111
106

117
115
114
113

1
2
5
6

14
15
18
19

121

X1

122

X2

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

0.1U_0402_10V6K

32
54
78
99

24
45
64
110
116

1

C69

0.1U_0402_10V6K

2

LAN_IO

12

R82

3.6K_0402_5%

LAN_ACT# CLKOUT XTALFB
SPD_10_100_G#

LAN_TX0+
LAN_TX0­LAN_RX1+
LAN_RX1-

LAN_TX2+
LAN_TX2­LAN_TX3+
LAN_TX3-

XTALFB
CLKOUT

R421 2.49K_0603_1%

1 2

closed to chip

R81 1K_0402_1%

1 2

@

2@

R420 0_0402_5%

1 2

R64 0_0402_5%

1 2

R59 0_0402_5%

1 2

R58 0_0402_5%

1 2

2@

CTL25
CTL12

R386

0_0603_5%

2

C36

1

R399
0_0603_5%2@

1 2

0.1U_0402_10V6K

1

C53

0.1U_0402_10V6K

2

4
3
2
1

LAN_ACT# <25>
SPD_10_100_G# <25>

LAN_TX0+ <25>
LAN_TX0- <25>
LAN_RX1+ <25>
LAN_RX1- <25>

LAN_TX2+ <25>
LAN_TX2- <25>
LAN_TX3+ <25>
LAN_TX3- <25>

5.6k for 8100C

R721
0_0402_5%

1 2

LAN_IO

1@

R379

2@

0_0603_5%

1 2

1 2

2

C38

0.1U_0402_10V6K

1

2

C89

1

12

R48 0_0402_5%

1 2

2@

R47 0_0402_5%

1 2

1@

2

C35

0.1U_0402_10V6K

1

GND

VCC

NC
NC

1@

+3VS

CTL25

CTL12

1 2

+2.5V_LAN

2

C103

0.1U_0402_10V6K

5

1

6
7
8

LAN_IO

12

R43
1K_0402_1%

R46

@

15K_0402_1% @

1 2

SUSP# <16,32,33,34,37,42>

+3VALW

1

0.1U_0402_10V6K

1

0.1U_0402_10V6K

+2.5V_LAN

2@

R395 0_0603_5%

3

2

3

2

12

Q32

2SB1188_SOT89

C328

Q33
2SB1188_SOT89

C333

+1.2V_LAN

1

2

2

1

2

1

1

2

1 2

L21 0_0805_5%

C332
10U_1206_6.3V6M

C335
10U_1206_6.3V6M

1 2

L22 0_0805_5%

U6

DO
DI
SK
CS

AT93C46-10SI-2.7_SO8

LAN_IO

+1.2V_LAN

R390

0_0603_5%

2

C90

0.1U_0402_10V6K

1

LAN_IO

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Y1

1 2

25MHZ_20P_1BX25000CK1A

1

C58
27P_0402_50V8J

2

0.1U_0402_10V6K

0.1U_0402_10V6K

2

+2.5V_LAN

2

C356

1

1

C364

2

1

2

C60
27P_0402_50V8J

1

+1.2V_LAN

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LAN CONTROLLER

LA-2361

1

24 50Monday, October 04, 2004

0.0

of

5

4

3

2

1

RP2

1 8
2 7
3 6
4 5

75_1206_8P4R_5%

C32
1000P_1206_2KV7K

12

JLAN1

SPD_10_100_G#<24>

LAN_IO

LAN_ACT#<24>

LAN_IO

1 2

R5

RJ45_TX3-

300_0603_5%

RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+
RJ45_RX1+
RJ45_TX0­RJ45_TX0+

1 2

R20 300_0603_5%

V_DAC

LAN_TX0+

LAN_TX0-

LAN_RX1+

LAN_RX1-

LAN_TX2+

LAN_TX2-

LAN_TX3+

LAN_TX3-

R405 0_0402_5%

R50 49.9_0402_1%

1 2

R49 49.9_0402_1%

1 2

R52 49.9_0402_1%

1 2

R51 49.9_0402_1%

1 2

R54 49.9_0402_1%

1 2

R53 49.9_0402_1%

1 2

2@

R56 49.9_0402_1%

1 2

2@

R55 49.9_0402_1%

1 2

2@

2@

1 2

2@

T=10mil

T=10mil

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_1566597-1

C45 0.01U_0402_16V7K

1 2

C46 0.01U_0402_16V7K

1 2

C47 0.01U_0402_16V7K

1 2

2@

C42 0.01U_0402_16V7K

1 2

2@

+2.5V_LAN

SHLD4
SHLD3

SHLD2
SHLD1

16
15

14
13

V_DAC

T28

1

TCT1
TD1+

TD1­TCT2
TD21+

TD2­TCT3
TD3+

TD3­TCT4
TD4+

TD4-

1:1

1:1

1:1

1:1

T41

TD-8TX-

7

TD+

6

CT

3

CT

2

RD-

1

RD+

NS0013_16P

@

1:1

TX+

RX-

RX+

9
10
11

CT

14

CT

15
16

24HST1041A-3_24P

2

3
4
5

6
7
8

9
10
11

12

MCT1
MX1+

MX1­MCT2
MX2+

MX2­MCT3
MX3+

MX3­MCT4
MX4+

MX4-

RJ45_TX0­RJ45_TX0+

RJ45_RX1­RJ45_RX1+

24

RJ45_TX3+

23

RJ45_TX3-

22
21

RJ45_TX2+

20

RJ45_TX2-

19
18

RJ45_RX1+

17

RJ45_RX1-

16
15

RJ45_TX0+

14

RJ45_TX0-

13

75_0402_1%

R759

12

12

R760
75_0402_1%

@

@

C375 0.1U_0402_16V4Z

1 2

LAN_TX3+<24>

D D

C C

Termination plane should be copled to chassis ground
and also depends on safety concern

B B

LAN_TX3-<24>

C374 0.1U_0402_16V4Z

1 2

LAN_TX2+<24>

LAN_TX2-<24>

C373 0.1U_0402_16V4Z

1 2

LAN_RX1+<24>

LAN_RX1-<24>

C370 0.1U_0402_16V4Z

1 2

LAN_TX0+<24>

LAN_TX0-<24>

RTL8110SBL used the 24HST1041A-3_24P

RTL8100CL used the 24ST0023-3_24P

Layout Note
24HST1041A-3 pls close to conn.

LAN_TX0­LAN_TX0+

LAN_RX1­LAN_RX1+

V_DAC

LAN_TX3+

LAN_TX3-

V_DAC

LAN_TX2+

LAN_TX2-

V_DAC

LAN_RX1+

LAN_RX1-

V_DAC

LAN_TX0+

LAN_TX0-

V_DAC

C1

1 2

0.1U_0402_16V4Z
C2

1 2

Termination plane should be copled
to chassis ground and also depends
on safety concern

Please close to LAN IC

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

0.1U_0402_16V4Z
C19

1 2

0.1U_0402_16V4Z

C11

1 2

0.1U_0402_16V4Z

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LAN CONTROLLER

LA-2361

25 50Monday, October 04, 2004

1

of

0.0

5

VPPEN0
VPPEN1
CBS_VCCD0#
CBS_VCCD1#

C2
C1
D4
D2
D1

G2
G3
H3
H4

N2
M3
N3

M4

M5
M6

N6
M7
N7

N8

N1
N5

G4

M1
M2

H1

L11

N9

N10

L10
N11
M11

M10

G5

H7

E4
E3
E2
F2
F1

J1
J2

K4
K5

L5
K6

L7
K7

E1
J3

J4
K1
K3
L1
L2
L3

A1
B1

L8

F4
K8
K9

J9

E7

E8

MSCLK
SDCLK
SDCMD
SDWP#

U28

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CBE3#
CBE2#
CBE1#
CBE0#

PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK

RIOUT#_PME#
SUSPEND#

IDSEL
MFUNC0

MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

GRST#

MFUNC7

VCC_SD
GND_SD

SDCD#
MSINS#

1 2

D D

PCI_AD[0..31]<19,24,27,28>

Place close to JCBUS

C437

1 2

PCI_AD20

PCI_PIRQA#<19>
PCI_PIRQB#<19>

CR_LED#<33>
CLKRUN#<21,24,28,31,32,34>

SIRQ<21,31,32>

1

2

PCI_C_BE3#<19,24,27,28>
PCI_C_BE2#<19,24,27,28>
PCI_C_BE1#<19,24,27,28>
PCI_C_BE0#<19,24,27,28>

PCI_FRAME#<19,24,27,28>
PCI_IRDY#<19,24,27,28>
PCI_TRDY#<19,24,27,28>
PCI_DEVSEL#<19,24,27,28>
PCI_STOP#<19,24,27,28>
PCI_PERR#<19,24,27,28>
PCI_SERR#<19,24,28>
PCI_PAR<19,24,27,28>

ICH_PME#<19,24,27,28,31,32,34>

+CBS_VCC

0.01U_0402_16V7K

CLK_33M_CBS<18>

1 2

+3V

12

R441

1

C384

2

C432

PCIRST#<19,24,27,28,32,34>

PCI_REQ1#<19>
PCI_GNT1#<19>

100K_0402_5%

1U_0603_10V4Z

10U_0805_10V4Z

1

2

R442

+SD_VCC

CBS_GRST#

5

+CBS_VPP

0.01U_0402_16V7K

1

C423

2

C C

+3V

B B

R42

A A

C41

cardbus

1394

CBS_RST#<32>

CLK_33M_CBS

@

10_0402_5%

12

@

4.7P_0402_50V8C

CK33M_CBS_TERM

2

1

R406 10K_0402_5%

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCIRST#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_REQ1#
PCI_GNT1#

CBS_IDSEL

R382100_0402_5%

R747 0_0402_5%

1 2

R748 0_0402_5%

1 2

R750 0_0402_5%

1 2

0_0402_5%@

12

CBS_GRST#

SDCD#
MSINS#

R751 0_0402_5%@

1 2

+CBS_VCC

G13

A7

N13

M13

N12

M12

VPPD0

VPPD1

VCCA1

VCCA2

VCCD0#

VCCD1#

MSCLKE9SDCLKF6SDCMDE5SDWPF8SDCLKIH5MSBSH8MSPWREN#J8SDPWREN33#G7MSDATA3F9MSDATA2G8MSDATA1H9MSDATA0

R39143K_0402_5%

MSBS

C8

H11

D12

B4

VCC9

VCC7

VCC8

VCC10

CARDBUS

CSTSCHG/BVD1_STSHG#

CCLKRUN#/WP_IOIS16#

CAUDIO/BVD2_SPKR#

SD

SD_EN#

MS_EN#

4

+3V

G1

K2

N4

F3

L6

L9

VCC2

VCC3

VCC4

VCC1

VCC5

VCC6

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CCBE3#/REG#

CCBE2#/A12

CCBE1#/A8

CCBE0#/CE1#

CRST#/RESET

CFRAME#/A23

CIRDY#/A15

CTRDY#/A22

CDEVSEL#/A21

CSTOP#/A20
CPERR#/A14

CSERR#/WAIT#

CPAR/A13

CREQ#/INPACK#

CGNT#/WE#

CCLK/A16

CBLOCK#/A19

CINT#/READY_IREQ#

SPKROUT

CCD2#/CD2#
CCD1#/CD1#

CVS2/VS2#
CVS1/VS1#

GND1
GND2
GND3
GND4
GND5
GND6
GND7

GND8
CRSV1/D14
CRSV2/A18

CRSV3/D2

RSVD4
RSVD3
RSVD2
RSVD1

SDDAT0
SDDAT1
SDDAT2
SDDAT3

CB712_LFBGA169

G9

MSDATA0
MSDATA1
MSDATA2
MSDATA3

4

CBS_CAD31

B2

CBS_CAD30

C3

CBS_CAD29

B3

CBS_CAD28

A3

CBS_CAD27

C4

CBS_CAD26

A6

CBS_CAD25

D7

CBS_CAD24

C7

CBS_CAD23

A8

CBS_CAD22

D8

CBS_CAD21

A9

CBS_CAD20

C9

CBS_CAD19

A10

CBS_CAD18

B10

CBS_CAD17

D10

CBS_CAD16

E12

CBS_CAD15

F10

CBS_CAD14

E13

CBS_CAD13

F13

CBS_CAD12

F11

CBS_CAD11

G10

CBS_CAD10

G11

CBS_CAD9

G12

CBS_CAD8

H12

CBS_CAD7

H10

CBS_CAD6

J11

CBS_CAD5

J12

CBS_CAD4

K13

CBS_CAD3

J10

CBS_CAD2

K10

CBS_CAD1

K12

CBS_CAD0

L13

CBS_CC/BE3#

B7

CBS_CC/BE2#

A11

CBS_CC/BE1#

E11

CBS_CC/BE0#

H13

CBS_CRST#

B9

CBS_CFRAME#

B11

CBS_CIRDY#

A12

CBS_CTRDY#

A13

CBS_CDEVSEL#

B13

CBS_CSTOP#

C12

CBS_CPERR#

C13

CBS_CSERR#

A5

CBS_CPAR

D13

CBS_CREQ#

B8

CBS_CGNT#

C11

CBS_CCLK

B12

CBS_CSTSCHNG

C5

CBS_CCLKRUN#

D5

CBS_CCLK_INTERNAL

D11

CBS_CINT#

D6
M9

B5

CBS_CCD2#_INTERNAL

A4

CBS_CCD1#_INTERNAL

L12

CBS_CVS2

D9

CBS_CVS1

C6

D3
H2
L4
M8
K11
F12
C10
B6

CBS_RSVD/D14

J13

CBS_RSVD/A18

E10

CBS_RSVD/D2

A2

H6
J7
J6
J5

SDDAT0

E6

SDDAT1

F7

SDDAT2

F5

SDDAT3

G6

R377 47_0402_5%

CBS_SPK#

CBS_CAUDIO

3

+3V

12

12

R60

8.2K_0402_5%

SD_EN#

MS_EN#

+3V

0.1U_0402_16V4Z

10U_0805_10V4Z

2

1

1

2

C344

C351

CBS_CBLOCK#

12

R440100K_0402_5%

12

CBS_SPK# <30>

MSDATA0
MSDATA3
MSDATA2
MSDATA1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D2

RB751V_SOD323

D3

RB751V_SOD323

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

2

2

C381

C376

C324

R358

+3V

@

C322

MSBS

R432 43K_0402_5%
R419 43K_0402_5%
R402 43K_0402_5%
R414 43K_0402_5%
R431 43K_0402_5%

CBS_CCLK

3

+3V

R61

8.2K_0402_5%

1

2

12

21

21

+CBS_VCC

+CBS_VPP +CBS_VPP

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

2

2

C325

C382

CBS_CCD2#
CBS_CCD1#

0_0402_5%

R400
0_0402_5%

1 2

1 2

@

270P_0402_50V7K

C361

270P_0402_50V7K

2

2

1

1

12
12
12
12
12

12

R83
0_0402_5%

1

@

C95
10P_0402_25V8K

2

@

+12VALW

12

R62

8.2K_0402_5%

+CBS_VCC

R116

@

0.01U_0402_16V7K

1

2

C360

C368
10P_0402_25V8K

R63

8.2K_0402_5%

13

D

Q2

2

AO3400_SOT23

G

S

12

12

47K_0402_5%

R122

47K_0402_5%

0.01U_0402_16V7K

1

2

C338

+SD_VCC

CBS_CCD2# CBS_CCD1#

1

2

@

2

G

1

C78

2

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

1

C143
10P_0402_25V8K

2

@

+3V

13

D

S

1

C96

2

1 2
1 2
1 2
1 2
1 2

Q3
2N7002_SOT23

2

+12V

9

1

C407

0.1U_0603_50V4Z

1

2

GND

CD1#

CE2#

VS1#
IORD#
IOWR#

VCC

VPP2

VS2#

RESET

WAIT#

REG#

SPKR#

CD2#

GND

2

0.1U_0402_16V4Z

+3V

C389

1

2

35
36
37

D11

38

D12

39

D13

40

D14

41

D15

42
43
44
45
46

A17

47

A18

48

A19

49

A20

50

A21

51
52
53

A22

54

A23

55

A24

56

A25

57
58
59
60
61
62
63
64

D8

65

D9

66

D10

67
68

5
6

3

0.1U_0402_16V4Z

4

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#

12
12

Title

Size Document Number Rev

Date: Sheet

+5V

C386

+SD_VCC

JCBS1

1

GND

2

D3

3

D4

4

D5

5

D6

6

D7

7

CE1#

8

A10

9

OE#

10

A11

11

A9

12

A8

13

A13

14

A14

15

WE#

16

IREQ#

17

VCC

18

VPP1

19

A16

20

A15

21

A12

22

A7

23

A6

24

A5

25

A4

26

A3

INPACK#

27

A2

28

A1

29

A0

STSCHG#

30

D0

31

D1

32

D2

33

IOIS16#

34

GND

SUPER_AC4-3000-250-3_RT

SDDAT2
SDCMD

R45443K_0402_5%

SDDAT0

R46843K_0402_5%

SDDAT3

R49543K_0402_5%

SDDAT1

R46343K_0402_5%
R50043K_0402_5%

Footprint need to change for #3 <-->#13

+3V

R505 43K_0402_5%
R439 43K_0402_5%

2

U30

12V

5V
5V

3.3V

3.3V
GND

7

SDDAT1
SDDAT0

SDCLK

SDCMD
SDDAT2

MSBS
MSDATA1
MSDATA0
MSDATA2
MSINS#
MSDATA3
MSCLK
SDDAT3

SDWP#
SDCD#

VCCD0
VCCD1

SHDN

16

+SD_VCC

VCC
VCC
VCC

VPP

VPPD0
VPPD1

SDCLK

MSCLK

OC

+3V

13
12
11

10

CBS_VCCD0#

1

CBS_VCCD1#

2

VPPEN0

15

VPPEN1

14

8

CP2211C1_SSOP16

+CBS_VCC

R481

1 2

0_0402_5%

@

R466

1 2

0_0402_5%

@

SD_WP

SD_CD

Compal Electronics, Inc.

CardBus Controller(R5C841)

LA-2361

1

+CBS_VPP

C414

1

2

+CBS_VCC

12

R462

R490

47K_0402_5%

@

1 2

1 2

JSD1

SD_8

SD_8

SD_7

SD_7

SD_6

SD_6

SD_5

SD_5

SD_4

SD_4

SD_3

SD_3

SD_2

SD_2

SD_1

SD_1

SD_9

SD_9

MS_1

MS_1

MS_2

MS_2

MS_3

MS_3

MS_4

MS_4

MS_5

MS_5

MS_6

MS_6

MS_7

MS_7

MS_8

MS_8

MS_9

MS_9

MS_10

MS_10
SD_WP

SD_CD

PROCO_MDR019-20-1000

1

+CBS_VCC

0.1U_0402_16V4Z

C427

0.1U_0402_16V4Z

1

2

12

47K_0402_5%

C451

10P_0402_25V8K

@

C402

10P_0402_25V8K

@

SD/ MMC/ MS

22

GND

23

GND

26 50Monday, October 04, 2004

of

0.0

5

+3VS

0.1U_0402_16V7K

1

1

C129

2

2

0.1U_0402_16V7K

D D

1

C149

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C138

2

1

C146

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C125

C147

2

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

C142

2

C117

4

1

C148

0.1U_0402_16V7K

2

+3VS

3

2

U11

1

A0

2
3
4

VCC

A1

WP

SCL

A2

SDA

GND

AT24C02N-10SI-2.7_SO8

8
7

1394SCL

6

1394SDA

5

+3VS

R150

1

510_0402_5%

12

1 2

1 2

TPB0-

TPB0+

TPA0-

TPA0+

54.9_0402_1%
R94

+3VS

R108
2K_0402_5%

@

1 2

XCPS

12

R113
1K_0402_5%

C101

J139A1
SUYIN_020204FR004S506ZL

1
2
3
4

1
2
3
4

GND15GND26GND37GND4

8

CLK_33M_1394

C C

B B

12

R102
22_0402_5%

@

1

C102
15P_0402_50V8D

2

@

PCI_AD[0..31]<19,24,26,28>

PCI_C_BE0#<19,24,26,28>
PCI_C_BE1#<19,24,26,28>
PCI_C_BE2#<19,24,26,28>

PCI_AD16

PCI_C_BE3#<19,24,26,28>

R115 100_0402_5%

1 2

PCI_FRAME#<19,24,26,28>
PCI_IRDY#<19,24,26,28>
PCI_TRDY#<19,24,26,28>
PCI_DEVSEL#<19,24,26,28>
PCI_STOP#<19,24,26,28>
PCI_PERR#<19,24,26,28>
PCI_PAR<19,24,26,28>
PCI_REQ2#<19>
PCI_GNT2#<19>
PCI_PIRQE#<19>
PCIRST#<19,24,26,28,32,34>
CLK_33M_1394<18>

46

110

122

111

21

VCC

VCC5VCC17VCC32VCC

VCC

30

VCC

+3VS

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

1394_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_REQ2#
PCI_GNT2#

U12

25

AD0

24

AD1

20

AD2

19

AD3

18

AD4

16

AD5

15

AD6

14

AD7

11

AD8

10

AD9

9

AD10

8

AD11

7

AD12

4

AD13

3

AD14

2

AD15

117

AD16

116

AD17

115

AD18

114

AD19

113

AD20

109

AD21

107

AD22

106

AD23

103

AD24

102

AD25

101

AD26

98

AD27

97

AD28

96

AD29

95

AD30

94

AD31

12

CBE0#

1

CBE1#

119

CBE2#

104

CBE3#

105

IDSEL

120

FRAME#

121

IRDY#

123

TRDY#

124

DEVSEL#

125

STOP#

127

PERR#

128

PAR

93

REQ#

92

GNT#

88

INTA#

89

PCIRST#

90

PCICLK

PCI Bus

NC45NC48NC49NC50NC37NC51NC52NC53NC54NC40NC39NC35NC74NC75NC76NC77NC78NC64NC81NC82NC83NC84NC85I2CEN43CARDEN

NC41NC

42

PVD36PVD

VCC99VCC

Power

IEEE 1394

VT6301S

NC

31

GND47GND

44

R133

4.7K_0402_5%

1 2

100

108

GND91GND

GND

118

126

112

38

GND

GND

GND6GND13GND23GND33GND

GND22GND

59

PVA

62

PVA

72

PVA

73

PVA

86

PVA

87

PVA

61

GND

65

GND

66

GND

79

GND

80

GND

56

GND

26

EECS

EEPROM
I/F

PM & Test

OSC

XI

57

PHYRESET#

XO

58

1394 Differential Pairs

27

EEDO

28

EEDI/SDA

29

EECK/SCL

34

PME#

60

XCPS

63

XREXT

67

TPB0M

68

TPB0P

69

TPA0M

70

TPA0P

71

TPBIAS0

55

C122

VT6301S-CD_LQFP128

24.576MHz_16P_3XG-24576-43E1

1394SDA
1394SCL

Y2

1 2

0.1U_0402_10V6K

XCPS

R107

6.34K_0603_1%

12

0.1U_0402_10V6K

12

R118
1M_0402_5%

1

C107

2

0.1U_0402_10V6K

+3VS

R723

@

1 2

4.7K_0402_5%

ICH_PME# <19,24,26,28,31,32,34>

1 2

1 2

1 2

1 2

47P_0402_25V8K

C118
10P_0402_50V8J

C124
10P_0402_50V8J

0.1U_0402_10V6K

1

C119

2

C112

+3VS

L12
0_0805_5%

1 2

1

1

C106

C116

2

0.1U_0402_10V6K

2

1 2

54.9_0402_1%

1 2

R93

54.9_0402_1%
R98

1 2

54.9_0402_1%
R99

1 2

270P_0402_50V7K

4.99K_0402_1%
R89

0.33U_0603_10V7K

1 2

C98

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

VIA 6301S 1394 chip

LA-2361

27 50Monday, October 04, 2004

1

0.0

of

5

D D

C C

B B

CLK_33M_MPCI

R319
10_0402_5%@

1 2

CK_33M_MINPCI_TERM

2

C295

4.7P_0402_50V8C

@

1

A A

+3VS

2

C297

0.047U_0402_16V4Z

1

2

C298

0.047U_0402_16V4Z

1

4

2

C290

0.047U_0402_16V4Z

1

3

2
4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

126

+3VS

WLAN_ACT2

R312 0_0402_5%

2

1

2

C287

0.047U_0402_16V4Z

1

+3VS

JMPCI1

1

1

3

3

5

5

7

7

9

WLAN_ACT1

HW_RADIO_DIS#<33,35>
PCI_PIRQH#<19>

CLK_33M_MPCI<18>
PCI_REQ3#<19>

R320
0_0402_5%

COEX2_WLAN_ACTIVE<35>

2

C299

0.047U_0402_16V4Z

1

PCI_C_BE3#<19,24,26,27>

PCI_C_BE2#<19,24,26,27>
PCI_IRDY#<19,24,26,27>

CLKRUN#<21,24,26,31,32,34>
PCI_SERR#<19,24,26>

PCI_PERR#<19,24,26,27>
PCI_C_BE1#<19,24,26,27>

+5VS

+5VS

HW_RADIO_DIS#

1 2

2

C300

0.047U_0402_16V4Z

1

PCI_PIRQH#

CLK_33M_MPCI
PCI_REQ3#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

2

C607

0.1U_0402_16V4Z

1

2

C289

0.047U_0402_16V4Z

1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123

125

AMP_1470484-1

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

GND

2
4

6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124

GND

2

C288

0.047U_0402_16V4Z

1

WLAN_ACT1
WLAN_ACT2

TC7SH32FU_SSOP5

PCI_PIRQG#

PCIRST#
PCI_GNT3#
SYS_PME#

1 2

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3V

C291

0.1U_0402_16V4Z

2

2
1

PCIRST# <19,24,26,27,32,34>
PCI_GNT3# <19>

+5VS

5

U22

P

I0

4

O

I1

G

BT_ACTIVE<35>

3

PCI_PIRQG# <19>

ICH_PME# <19,24,26,27,31,32,34>

R311

10K_0402_5%

12

1 2

100_0402_5%

PCI_AD18

R313

PCI_PAR <19,24,26,27>

PCI_FRAME# <19,24,26,27>
PCI_TRDY# <19,24,26,27>
PCI_STOP# <19,24,26,27>

PCI_DEVSEL# <19,24,26,27>

PCI_C_BE0# <19,24,26,27>

PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

2
1

COEX1_BT_ACTIVE <35>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9

+5VS

5

P

I0
I1

G

3

2

C286

0.1U_0402_16V4Z

1

1

U21

4

O

TC7SH32FU_SSOP5

+3VALW

PCI_AD[0..31] <19,24,26,27>

2

C285

0.1U_0402_16V4Z

1

WL_BT_LED <33>

+5VS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

MINIPCI

LA-2361

28 50Monday, October 04, 2004

1

0.0

of

A

B

C

D

E

AC97 Codec

1 1

2 2

INT_CD_L<23>
INT_CD_R<23>

3 3

MD_SPK<35>

XTLSEL

LOW

*

Floating

R633
20K_0402_5%

1 2

12

R632

4 4

0_0402_5%@

12

R638

6.8K_0402_5%

10U_0805_10V4Z

1 2

R639 6.8K_0402_5%

1 2

R642 6.8K_0402_5%

1 2

R640 20K_0402_5%

1 2

R641 20K_0402_5%

1 2

1 2

R229 2.4K_0402_5%

1 2

R230 10K_0402_5%

CD_GNA

+5VS

U14

4

C574

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

1

1

C240
10U_0805_10V4Z

2

2

C192

1

1

2

2

C210

0.1U_0402_16V4Z

0.1U_0402_16V4Z

For ALC250 disable HW EQ when Headphone plug-in.

R228

0_0402_5%

1 2

C233 0.1U_0402_16V4Z@

C232 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

CD_L_R
CD_R_R
CD_GNA

MIC

1 2

C235 1U_0603_10V4Z

C236

0.01U_0402_16V7K

MONO_IN<30>

IAC_RST#<20>
IAC_SYNC<20>
IAC_SDATO<20>

NBA_PLUG<30>

CD_GNA<23>
MIC<30>

MODE

14.318MHz External

24.576MHz Crystal
or External Colck

12

R299
0_0402_5%

EAPD<30>

5

VOUT

6
1
3

+VDDA

HP_SENSE

C_MD_SPK

1

2

C209

0.1U_0402_16V4Z

0_0805_5%

C_MIC

GND

1 2

1 2

C569 1U_0603_10V4Z

1 2

C570 1U_0603_10V4Z

1 2

C568 1U_0603_10V4Z

1 2

C234 1U_0603_10V4Z

L18

1 2

U16

12

12

+AVDD_AC97

14

AUX_L

15

AUX_R

16

JD2

17

JD1

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

PHONE

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

NC

46

XTLSEL

47

SPDIFI/EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC250_LQFP48

+VDDA

1

R222
150K_0603_1%

2

R223
51K_0603_1%

38

AVDD125AVDD2

MONO_OUT/VREFOUT3

(+VDDA~=4.79V)

+VDDA

C219
10U_0805_10V4Z

9

DVDD11DVDD2

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

AFILT1
AFILT2

VREFOUT

VREF

DCVOL

VAUX

SCK
SDA

AVSS1
AVSS2

35
36
37
39
41

6
8
2

3
29
30
28
27
32

31

NC

33
34
43
44

40

NC

26
42

LINE_OUT_L

LINE_OUT_R

HP_OUT_L
HP_OUT_R

VREFOUT2

1

1

C271

C258

10U_0805_10V4Z

2

2

0.1U_0402_16V4Z

LINEL
LINER

12

C276 1000P_0402_50V7K

12

C268 1000P_0402_50V7K

1 2

C269 4.7U_0805_10V4Z

1 2

C275 4.7U_0805_10V4Z

C577 1U_0805_25V4Z

1 2

R285 22_0402_5%

1 2

R284 22_0402_5%

1 2

XTL_IN

1M_0402_5%@

XTL_OUT

12

C259 1000P_0402_50V7K

12

C265 1000P_0402_50V7K

12

R643

0_0402_5%@

If Project need to implement Realtek Power Off CD play function.
It must be supplied power for AVDD(Pin25 & 38) &
VAUX(Pin34) & power off for DVDD(Pin1 & 9).
When AVDD & VAUX powered and DVDD without power,
it will bypass CD_L & CD_R to LINE_OUT_L & LINE_OUT_R.

MODE

DVDD(1/9)

VAUX(34)

+3VS

12

R292

1

C241

0.1U_0402_16V4Z

2

SHUT DOWN

Rb

0

0

LEFT
RIGHT

LEFT <30>
RIGHT <30>
MD_MIC <35>

IAC_BITCLK <20,35>
IAC_SDATAI1 <20>

X2

1 2

24.576MHz_16P_3XG-24576-43E1@

1

C261

22P_0402_50V8J@

2

Cb Cb

+AUD_VREF

1

C571

4.7U_0805_10V4Z

2

POWER OFF
CD Play

0

1

When Project need implement Headphone channel output from
Audio Codec pin 39 & 41, it must have another driver to support JD
function to change signal path from LINE_OUT_L & LINE_OUT_R to
HP_OUT_L & HP_OUT_R when headphone insert.

Xb

NORMAL NORMAL

14.318MHz External

24.576MHz Crystal
or External Colck

1 2

R298
0_0402_5%

1

C270

22P_0402_50V8J@

2

1

1

0

1

Ra stuff, Rb, Cb, and Xb empty.

Rb, Cb, and Xb stuff, Ra empty.

1 2

R763
0_0402_5%

CLK_14M_CODEC

12

Ra

1

2

C257

0.1U_0402_16V4Z

R297

10_0402_5%@

C277

15P_0402_50V8J@

1

2

1 2

R164 0_0805_5%

1 2

R217 0_0805_5%@

1 2

R694 0_0805_5%@

CLK_14M_COMPAL <38>

CLK_14M_CODEC <18>

+AUD_VREF

1

C573

4.7U_0805_10V4Z

2

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

AC97 Codec

Size Document Number Rev

Custom

LA-2361

Date: Sheet

E

of

29 50Monday, October 04, 2004

0.0

A

1 1

LEFT<29>
RIGHT<29>

+5VAMP

12

R219

10K_0402_5%

2 2

+3V

12

BEEP#<32,34>

+3V

14

P

I2O

G

SN74LVC125APWLE_TSSOP14

3 3

7

+3V POWER

R258
100K_0402_5%

1

U15A

OE#

3

CBS_SPK#<26>

R232

8.2K_0402_5%

1 2

VOL_AMP

(0.65V -> 10dB )

12

R625

1.5K_0402_1%

+3V

14

1

1

+3V POWER

C567

7

0.22U_0603_10V7K

2

+3V

1 2

C554

0.1U_0402_16V4Z
U35A
SN74LVC14APWLE_TSSOP14

P

O2I

G

1 2

C566
1U_0603_10V4Z

1 2

C565
1U_0603_10V4Z

14

P

SPKR<21>

4 4

3

4

O

I

G

+3V POWER

7

U35B
SN74LVC14APWLE_TSSOP14

1 2

C563
1U_0603_10V4Z

B

Pin 2

0.47U_0603_16V4Z

LEFT
RIGHT

0.47U_0603_16V4Z

fo=1/(2*3.14*R*C)=260Hz
R=1.3K / C=0.47U

R635

560_0402_5%

1 2

R630

560_0402_5%

1 2

R628

560_0402_5%

1 2

R627
10K_0402_5%

2

B

12

HIGH

PIN 6,20 ACTIVE

LOW PIN 5,23 ACTIVE

NBA_PLUG<29>

C557

R624

1.3K_0603_5%

1 2
1 2

C556

+VDDA

12

R231
10K_0402_5%

12

R225

10K_0402_5%

1

C

Q10
2SC2411K_SC59

E

3

D19
RB751V_SOD323

2 1

INTSPK_L1
INTSPK_R1
LEFT_1

RIGHT_1

12

+5VS

L16

1 2

NBA_PLUG
VOL_AMP

1 2
1 2

C552

1 2
1 2

0.47U_0603_16V4Z

HP_L
HP_R

C212 0.47U_0603_16V4Z

C213 0.47U_0603_16V4Z

12

R623

1.3K_0603_5%

1

C224
10U_0805_10V4Z

2

1 2

C239
1U_0603_10V4Z

R226

2.4K_0402_5%

1 2

C

0_0805_5%

C553

0.47U_0603_16V4Z

LEFT_2
RIGHT_2

1

C558

2

0.1U_0402_16V4Z

INTSPK_R1

INTSPK_L1

MONO_IN

+5VAMP

W=40Mil

1

C548

0.1U_0402_16V4Z

2

18
19

21
23
20
17

1

C546

0.047U_0603_16V7K

2

C555
150U_D2_6.3VM

1 2

+

1 2

+

C564
150U_D2_6.3VM

C547

1

4.7U_0805_10V4Z

2

U34

7

PVDD

SHUTDOWN#

PVDD

SE/BTL#

VDD

PC-BEEP

2
3
4

5
6

INTSPK_R1-2
INTSPK_L1-2

MONO_IN <29>

BYPASS
HP/LINE#
VOLUME
LOUT+
ROUT+
LLINEIN
RLINEIN
LHPIN
RHPIN

CLK

TPA0232PWP_TSSOP24

1 2

1 2

R221
47_0402_5%

LOUT-

ROUT-

LIN

RIN

GND
GND
GND
GND

R218
47_0402_5%

MIC<29>

22
15
14
11
9
16
10
8

1
12
13
24

INTSPK_R1-3
INTSPK_L1-3

SHUTDOWN#

2

C561
1U_0603_10V4Z

1

(0.47U~1U)

L15
FBM-11-160808-700T_0603
L17

FBM-11-160808-700T_0603

MIC

D

+5VAMP

12

R617
100K_0402_5%

Q40

13

D

2N7002_SOT23

2

G

+5VAMP

S

NBA_PLUG

INTSPK_L2
INTSPK_R2

2

C559

1

0.47U_0603_16V4Z

1 2
1 2

1 2

L29
FBM-11-160808-700T_0603

1 2

1 2

C549 0.1U_0402_16V4Z

2

C560

1

0.47U_0603_16V4Z

INTSPK_R1-4
INTSPK_L1-4

C226

330P_0402_50V7K

2.2K_0402_5%

R220
100K_0402_5%

NBA_PLUG

1

2

R645

INTSPK_L1
INTSPK_L2
INTSPK_R1
INTSPK_R2

1

C211
330P_0402_50V7K

2

12

12

R671

2.2K_0402_5%

1

C572
220P_0402_50V7K

2

EAPD <29>

1

C162

2

22P_0402_25V8K

@

AMP_1-1470184-2

CS
CN

1
3
4
5

JHP1

1 2

R644 0_0402_5%

AMP_1-1470184-2

CS
CN

1
3
4
5

JMIC1

C161

@

1

2

E

1

C159

C160

2

22P_0402_25V8K

22P_0402_25V8K

@

@

+AUD_VREF

JSPK1

1

1

2

2

3

3

4

4

ACES_85205-0400

1

2

22P_0402_25V8K

EXT.
MICPHONE

JACK

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Power OK/Reset/RTC battery/Lid Switch/Int. KB

Size Document Number Rev

Custom

LA-2361

Date: Sheet

E

of

30 50Monday, October 04, 2004

0.0

A

B

C

D

E

FIR Module

CLK_14M_SIOCLK_PCI_SIO

12

R403
10_0402_5%

@

1 1

LPC_LAD[0..3]<20,32,34>

LPC_LFRAME#<20,32,34>

+3VS

,24,26,27,28,32,34>

2 2

GPIO11 1= 4E 0=2E

3 3

4 4

LPC_LDRQ1#<20>
PLTRST_SIO#<19>

CLKRUN#<21,24,26,28,32,34>

CLK_33M_LPCSIO<18>

SIRQ<21,26,32>

+3VS +3VS

ICH_PME#
CLK_14M_SIO<18>

12

R398
10K_0402_5%

12

R401
10K_0402_5%

SIRQ

@

SIO_GPIO11

R383
10K_0402_5%

R415

LPC_LAD[0..3]

SIO_PD#

+5V_PRN

FD7
FD6
FD5
FD4

U27

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

LPC I/F

GPIO

POWER

FIR

IRMODE/IRRX3

SERIAL I/F

PARALLEL I/F

109876

12345

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ1#

PLTRST_SIO#

10K_0402_5%

PM_CLKRUN#

CLK_PCI_SIO

SIO_PME#

CLK_14M_SIO

12

R393
10K_0402_5%

SIO_SMI#

12

+5V_PRN +5V_PRN

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

RP9

109876

12345

2.7K_1206_10P8R_5%

RXD1
TXD1

DSR1#

RTS1#
CTS1#
DTR1#

RI1#

DCD1#

IRRX2
IRTX2

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE

BUSY

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

RP8

2.7K_1206_10P8R_5%

@

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

1

2

+5V_PRN

AFD#/3M#
FD0
LPTERR#
FD1

FD3
LPTSLCTIN#
FD2
LPTINIT#

C369
18P_0402_50V8K

IRRX
IRTXOUT
IRMODE

INIT#
SLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

12

@

@

C331
1U_0603_10V4Z

1

2

C326
1U_0603_10V4Z

R380
10_0402_5%

1

C343
10P_0402_25V8K

2

+3VS

1

2

INIT# LPTINIT#

1 2

R323 33_0402_5%

18
27
36
45

LPTSLCTIN#SLCTIN#

RP7

33_0804_8P4R_5%

1 2

R324 33_0402_5%

RP1

LPD0 FD0
LPD1 FD1
LPD2 FD2
LPD3

33_0804_8P4R_5%

LPD4
LPD5
LPD6
LPD7 FD7

FD3

FD4

18

FD5

27

FD6

36
45

+5VS

Parallel Port

LPTSTB#
AFD#/3M#

LPTAFD#
FD0

LPTERR#
FD1
LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

1

C145

2

10U_0805_10V4Z

D1

2 1

RB420D_SOT23

R1
33_0402_5%

1 2

R327
33_0402_5%

1 2

+3VS

1 2
1

2

+5V_PRN

R152
47_1206_5%

+IR_3VS

(30mil)

C144

0.1U_0402_16V4Z

R2

2.2K_0402_5%

FOX_DZ11391-H7

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

JP1

IRRX

12

R381
10K_0402_5%

C7
220P_0402_25V8K

27
26

(60mil)

+3VS

1

C337
1U_0603_10V4Z

2

2
4
6
8

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

R138

4.7_1206_5%

1 2
1 2

R137

4.7_1206_5%

U10

IRED_C
RXD
VCC
GND

IR_VISHAY_TFDU6101E-TR4_8P

PCB Footprint : TFDU6101E

AFD#/3M#

C611 220P_0402_25V8K

FD0
LPTERR#

C613 220P_0402_25V8K

FD1

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7

1

IRED_A

3

TXD

5

SD/MODE

7

MODE

1 2

C612 220P_0402_25V8K

1 2

1 2

C614 220P_0402_25V8K

1 2

C615 220P_0402_25V8K

1 2

C616 220P_0402_25V8K

1 2

C617 220P_0402_25V8K

1 2

C618 220P_0402_25V8K

1 2

C619 220P_0402_25V8K

1 2

C620 220P_0402_25V8K

1 2

C621 220P_0402_25V8K

1 2

C622 220P_0402_25V8K

1 2

C623 220P_0402_25V8K

1 2

C624 220P_0402_25V8K

1 2

C625 220P_0402_25V8K

1 2

C626 220P_0402_25V8K

1 2

+IR_ANODE

(60mil)

IRTXOUT
IRMODE

1 2

R154 0_0402_5%

Reserved

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SUPER I/O LPC47N217

Size Document Number Rev

Custom

LA-2361

Date: Sheet

E

of

31 50Monday, October 04, 2004

0.0

A

+3VALW

12

L31
0_0603_5%

+EC_AVCC

1 1

+3VALW

1 2

C591

0.1U_0402_16V4Z

12

R720
47K_0402_5%

ECRST#

1

C610

0.1U_0402_16V4Z

2

ECAGND

L30

1 2

LPC_LAD[0..3]<20,31,34>

CLK_33M_LPCEC<18,34>

C609

1 2

15P_0402_50V8D

@

0_0603_5%

+3VALW

SIRQA<34>
SIRQ<21,26,31>

LPC_LAD[0..3]

1 2

R719 33_0402_5%

@

KSI[0..7]<33,34>
KSO[0..15]<33,34>

0.1U_0402_16V4Z

1

1

C604

2

0.1U_0402_16V4Z

LPC_LFRAME#<20,31,34>

C608

2

+3VS

R753 0_0402_5%

1 2

ECRST#<34>

KSI[0..7]
KSO[0..15]

1

2

1000P_0402_50V7K

1 2

R718 10K_0402_5%

@

Reserved for 87591L

JP4

1

1
2
3
4
5
6
7
8
9

PSCLK1<33>
PSDAT1<33>

R712

4.7K_0402_5%

10

E&T_96212-1011S

@

+5V

GATEA20<20,34>

KBRST#<20,34>

+5VALW

12

4.7K_0402_5%

2 2

3 3

4 4

EC_TINIT#

2

EC_TCK

3

EC_TDO

4

EC_TDI

5

EC_TMS

6
7
8

SCROLLLOCK#

9

EN_WOL#

10

RP11

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2

R696 10K_0402_5%

1 2

R695 10K_0402_5%

R714

10K_0402_5%

1 2

12

R709

R713

4.7K_0402_5%

R730 0_0402_5%@
R731 0_0402_5%@

R732 0_0402_5%
R733 0_0402_5%

+3VS

12

A

PSCLK1T
PSDAT1T
PSCLK2
PSDAT2

PSCLK3
PSDAT3

1 2

1 2
1 2

1 2
1 2

R715
10K_0402_5%

GATEA20

KBRST#

12

R710

4.7K_0402_5%

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

+3VALW

TDO <34>

PSCLK1T<34>
PSDAT1T<34>

PSCLK3<34>
PSDAT3<34>

ECDEBUG <34>

+VCCP_PWRGD<34,42>

SLP_S4#<21,34>
PAD_LOCK#<33,34>
CLKRUN#<21,24,26,28,31,34>

BKOFF#<16,34>
SCROLLLOCK#<33,34>

FSTCHG<34,40>
CAPLOCK#<33,34>
NUMLOCK#<33,34>
EC_SMI#<21,34>
MSEN#<17,34>

COMPAL_INT#<34,38>

PROCHOT#<5,34>

1

2

PSCLK2<34>
PSDAT2<34>

RSMRST#<21,34>

EC_SCI#<21,34>

+3VALW

For NS 87591L

@
@
@

1 2

20M_0402_5%

R706

@

Y3

12

32.768KHZ_12.5PF_6HT3

C602

10P_0402_50V8J

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14

KSO15
KSO16
KSO17

R70010K_0402_5%
R69910K_0402_5%
R69810K_0402_5%
R69710K_0402_5%

R708

1

C601
10P_0402_50V8J

2

0.1U_0402_16V4Z

C596

LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

ECRST#

GATEA20
KBRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

PSCLK1T
PSDAT1T
PSCLK2
PSDAT2
PSCLK3
PSDAT3

CRY1
CRY2

EC_SCI#

SLP_S4#

PM_CLKRUN#

SCROLLLOCK#

EC_SMI#

12
12
12
12

CRY1

CRY2

12

0_0603_5%

B

1

2

1000P_0402_50V7K

1

C592

2

U36

7

SERIRQ

9

LFRAME#

15

LAD0/FWH0

14

LAD1/FWH1

13

LAD2/FWH2

10

LAD3/FWH3

18

LCLK

19

ECRST#

31

ECSCI#

5

GPIO02/GA20

6

GPIO03/KBRST#

71

KSI0/GPIK0

72

KSI1/GPIK1

73

KSI2/GPIK2

74

KSI3/GPIK3

77

KSI4/GPIK4

78

KSI5/GPIK5

79

KSI6/GPIK6

80

KSI7/GPIK7

49

KSO0/GPOK0

50

KSO1/GPOK1

51

KSO2/GPOK2

52

KSO3/GPOK3

53

KSO4/GPOK4

56

KSO5/GPOK5

57

KSO6/GPOK6

58

KSO7/GPOK7

59

KSO8/GPOK8

60

KSO9/GPOK9

61

KSO10/GPOK10

64

KSO11/GPOK11

65

KSO12/GPOK12

66

KSO13/GPOK13

67

KSO14/GPOK14

68

KSO15/GPOK15

153

KSO16/GPOK16

154

KSO17/GPOK17

110

PSCLK1

111

PSDAT1

114

PSCLK2

115

PSDAT2

116

PSCLK3

117

PSDAT3

158

XCLKI

160

XCLKO

3

GPIO00/E51IT0

4

GPIO01/E51IT1

8

GPIO04

20

GPIO07

21

GPIO08

22

GPIO09

23

NUMLOCK#/GPIO0A

24

GPIO0B

25

CLKRUN#/GPIO0C

27

GPIO0D

28

GPIO0E

41

SCROLLLOCK#/GPIO0F

48

GPIO10

54

CAPLOCK#/GPIO11

55

FNLOCK#/GPIO12

62

GPIO13

63

GPIO14

69

GPIO15

70

GPIO16

75

GPIO17

CRY1 <34>

CRY2 <34>

C606

Close to RTC pad

B

GPIO1

A0

124

KBA0

KBA1

VCC016VCC134VCC245VCC3

Host interface

Key matrix scan

PS2 interface

A1/XIOP_TP

A4/DMRP_TP

A5/EMWB_TP

125A2126A3127

128

131A6132A7133

KBA5

KBA4

KBA2

KBA3

KBA6

KBA7

PROPRIETARY NOTE

123

136

GPIO0

143A9142

KBA8

C

+EC_AVCC

ECAGND

C603

1U_0805_25V4Z

122

167

157

VCC4

A8

KBA9

166

VCC5

135

KBA10

VCC6

A10

134

KBA11

PWR/GND

A12

A11

130

KBA12

129

KBA13

137

GND117GND235GND346GND4

GND6

GND7

FAN/PWM

BIOS I/F

A13

A14

A15

A16

A17

A18

A19

120

KBA15

113

112

KBA17

KBA16

138D1139D2140D3141D4144D5145D6146D7147

104

103

ADB0

KBA19

KBA18

121

KBA14

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

159

161

96

95

VCCA

AGND

VCCBAT

AD Input or GPI

DA output or GPO

PWM
or GPOW

PWM2/GPOW2/FAN1PWM
PWM7/GPOW7/FAN2PWM

GPIO05/FAN3PWM/TEST_TP

FANFB1/TOUT1/GPIO2E

GPIO06/FANFB3/DPLL_TP

SM BUS

GPIO20/E51CS#/ISPEN_TP

GPIO21/E51RXD/ISPCLK
GPIO22/E51TXD/ISPDAT

GPIO2

GPWU or GPI

D0

ADB4

ADB7

ADB3

ADB1

ADB6

ADB5

ADB2

C

AD0/GPIAD0
AD1/GPIAD1

BATGND

AD2/GPIAD2
AD3/GPIAD3
AD4/GPIAD4
AD5/GPIAD5
AD6/GPIAD6
AD7/GPIAD7

DA0/GPODA0
DA1/GPODA1
DA2/GPODA2
DA3/GPODA3
DA4/GPODA4
DA5/GPODA5
DA6/GPODA6
DA7/GPODA7

PWM0/GPOW0
PWM1/GPOW1
PWM3/GPOW3
PWM4/GPOW4
PWM5/GPOW5
PWM6/GPOW6

GPWU7/TIN2/FANFB2

LRST#/GPIO2C
TOUT2/GPIO2F

GPWU6/TIN1

GPIO18/XIO8CS#

GPIO19/XIO9CS#
GPIO1A/XIOACS#
GPIO1B/XIOBCS#

GPIO1C/XIOCCS#
GPIO1D/XIODCS#

GPIO1E/XIOECS#
GPIO1F/XIOFCS#

RD#

WR#

150

151

152

ADB[0..7]
KBA[0..19]

12

SCL1

SDA1

SCL2

SDA2

A20/GPIO23

GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B

GPIO2D

GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5

IOCS#

MEMCS#

173

OPEN

12

J3 JOPEN

12

J4 JOPEN

SHORT

BATT_TEMP

81

M/B_ID

82

BATT_OVP

83
84
87
88
89
90

99
100
101
102

ICH_PWRGD

1
42
47
174

32
33
37

ICH_BATLOW#

38
39
40

36
43

TEST_TP

11
171
176

DPLL_TP

12

SMB_EC_CK1

163

SMB_EC_DA1

164

SMB_EC_CK2

169

SMB_EC_DA2

170

EC_TINIT#

105

EC_TCK

106

EC_TDO

107

EC_TDI

108

EC_TMS

109
118

THERMATRIP_VGA#

119
148
149
155

G_RST#

156

RUNPWROK

162

PCIRST#

165
168
175

2
26
29
30
44
76
172

85
86
91
92
93
94
97
98

R734 10K_0402_5%
R735 10K_0402_5%

KB910_LQFP176

FSEL# <33,34>
FWR# <33,34>

FRD# <33,34>

ADB[0..7] <33,34>
KBA[0..19] <33,34>

+RTCVCC

+3VALW

1 2
1 2

+3VALW

12

12

R704
100K_0603_5%

M/B_ID

R705
0_0603_5%

D

1 2
1 2
1 2

ECAGND

BATT_TEMP <34,39>

M/B_ID <34>

BATT_OVP <34,40>

DAC_BRIG <16,34>

IREF <34,40>

EN_FAN1 <34>

ICH_PWRGD <21,34>

INVT_PWM <16,34>

BEEP# <30,34>
ACOFF <34,40>

ICH_BATLOW# <21,34>

EC_ON <33,34>

LID_SWOUT# <21,34>TCK <34>

FAN1SPD <34>
BIA <10,16,34>

SMB_EC_CK1 <16,33,34,38,39>
SMB_EC_DA1 <16,33,34,38,39>
SMB_EC_CK2 <16,34>
SMB_EC_DA2 <16,34>

LID_SW# <33,34>
THERMATRIP_VGA# <16,34>

SYSON <34,37,42>
SUSP# <16,24,33,34,37,42>
VR_ON <34,37,45>

RUNPWROK <16>
PCIRST# <19,24,26,27,28,34>
PWRBTN_OUT# <21,34>
EC_THRM# <21,34>

ON/OFF <33,34>
ACIN <21,34,40,41>

SLP_S3# <21,34>
SLP_S5# <21,34>

ICH_PME# <19,24,26,27,28,31,34>
PWR_LED# <33,34>

CHARGE_LED# <33,34>

BATT_LED# <33,34>
USER_BTN1# <33,34>

USER_BTN2# <33,34>

0.1U_0402_16V4Z

+3VALW

Pin8, 22, 54, 82, 84, 89 and 172 is diffrence define with 87591
R181, R191, R192 and R193 are reserved for KB910.
R187 & R176 are reserced for 87591L

1

2

BTDIS# signal is reservedfor BT modula,
BTON# signal is reserved for MDC\BT module

C599

D

ECAGNDM/B_ID

C598

0.01U_0402_16V7K

ECAGNDBATT_TEMP

C600

0.01U_0402_16V7K

ECAGNDBATT_OVP

C597

0.01U_0402_16V7K

ECAGND <34>

M/B Ver.

Voltage

BORAD ID

+3VALW

12

G_RST#

PCIRST#<19,24,26,27,28,34>

@

FSEL#
FRD#

EC_SMI#

E

0.1

0.0 0.4 0.8 1.2

+3VALW

R307
100K_0402_5%

5

U18

2
1

NC7ST32P5X_SC70

@

1 2

R300 10K_0402_5%

1 2

R302 10K_0402_5%

1 2

R707 10K_0402_5%

For KB910

PCIRST#

1 2

EC_TINIT#

1 2

R701 100K_0402_5%

TEST_TP

1 2

R716 100K_0402_5%

DPLL_TP

1 2

R717 100K_0402_5%

Compal Electronics, Inc.

Title

ENE KB910

Size Document Number Rev

LA-2361

Date: Sheet

E

4

+3VALW

R711
100K_0402_5%

32 50Monday, October 04, 2004

1.6

CBS_RST# <26>

+3VALW

0.0

of

A

KSI[0..7]<32,34>
KSO[0..15]<32,34>

JP2

KSI1

1

KSI7

2

KSI6

3

KSO9

4

KSI4

5

KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6

KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

PSDAT1<32>
PSCLK1<32>

6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ACES_85203-2402

SMB_EC_CK1<16,32,34,38,39>
SMB_EC_DA1<16,32,34,38,39>

+3VBIOS

1 1

2 2

3 3

4 4

KSI[0..7]
KSO[0..15]

KeyBoard

25

2

26

3

27

4

28

5

29

6

30

7

31

8

32

9

33

10

34

11

35

12

36

13

37

14

38

15

39

16

40

17

41

18

42

19

43

20

44

21

45

22

46

23

47

24

48

+5VS +5VS

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5

A

KSI7
KSI6

KSO9

KSI4
KSI5

KSO0

KSI2

KSI3
KSO5
KSO1

KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3

KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

KSI1

25

1

100P_0402_25V8K

1 2

C164

C165 100P_0402_25V8K

1 2

C166 100P_0402_25V8K

100P_0402_25V8K

1 2

C168

C169 100P_0402_25V8K

1 2

C170 100P_0402_25V8K

100P_0402_25V8K

1 2

C172

C173 100P_0402_25V8K

1 2

C174 100P_0402_25V8K

100P_0402_25V8K

1 2

C176

C177 100P_0402_25V8K

1 2

C178 100P_0402_25V8K

100P_0402_25V8K

1 2

C180

C181 100P_0402_25V8K

1 2

C182 100P_0402_25V8K

100P_0402_25V8K

1 2

C185 100P_0402_25V8K

C184

1 2

C186 100P_0402_25V8K

T/P

JTP1

1 7
2 8
3 9
4

10

5

11

6

12

ACES_85203-0602

+5VALW

C284

0.1U_0402_16V4Z

1 2

U19

8

VCC

7

WP

6

SCL

5

SDA

AT24C16N-10SI-2.7_SO8

U38

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

SST39VF040-70-4C-WH_TSOP32@

OE#
CE#

DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0

A10

A0
A1
A2
A3

1 2

C167 100P_0402_25V8K

1 2

C171 100P_0402_25V8K

1 2

C175 100P_0402_25V8K

1 2

C179 100P_0402_25V8K

1 2

C183 100P_0402_25V8K

1 2

C187 100P_0402_25V8K

A0
A1
A2

GND

FRD#

32

KBA10

31

FSEL#

30

ADB7

29

ADB6

28

ADB5

27

ADB4

26

ADB3

25
24

ADB2

23

ADB1

22

ADB0

21

KBA0

20

KBA1

19

KBA2

18

KBA3KBA4

17

1 2

1 2

1 2

1 2

1 2

1 2

1
2
3
4

+5VALW

12

R309
100K_0402_5%

12

R305
100K_0402_5%

B

Killer switch

+3V

12

R306

100K_0402_5%

PSDAT1 <32>
PSCLK1 <32>

KBA0<32,34>
KBA1<32,34>
KBA2<32,34>
KBA3<32,34>
KBA4<32,34>
KBA5<32,34>
KBA6<32,34>
KBA7<32,34>
KBA8<32,34>
KBA9<32,34>
KBA10<32,34>
KBA11<32,34>
KBA12<32,34>
KBA13<32,34>
KBA14<32,34>
KBA15<32,34>
KBA16<32,34>
KBA17<32,34>
KBA18<32,34>
KBA19<32,34>

FSEL#<32,34>

FRD#<32,34>

B

3

+3VALW

+5VALW

DS-1208_3P

SW2

12

+3VS

CR_LED#<26>

11223

DAN217_SC59

R727
0_0402_5%

0_0402_5%

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
FRD#
FWE#

C

+3V

+5VS

2

3

@

D6

1

5

P

2

A

G

3

HW_RADIO_DIS#

U23

HW_RADIO_DIS

4

Y

NC7SZ14M5X_SOT23-5

HW_RADIO_DIS# <28,35>

1

SPPB530600_4P

D

2
43

SW1

SW Board

JPSWP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20

SUYIN_80065AR-020G2T

12

R359

U20

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

B

+3VALW

+12VALW

E

VCC0
VCC1

RP#

NC

NC0
NC1

GND0
GND1

12

C

3 1

D0
D1
D2
D3
D4
D5
D6
D7

ON/OFFBTN#
NUM_LED#
SCROL_LED#
CAPS_LED#

R348

8.2K_0402_5%

@

13

D

2

G

BIOS_RST#

C

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

S

Q29
MMBT3904_SOT23

@

1 2

R304 0_0603_5%

31
30

25
26
27
28
32
33
34
35

10
11
12
29
38

23
39

Q28
2N7002_SOT23

@

+3VBIOS

C282

0.1U_0402_16V4Z

R303

1 2

USER_BTN1# <32,34>
USER_BTN2# <32,34>

NUMLOCK# <32,34>
SCROLLLOCK# <32,34>
CAPLOCK# <32,34>
HDD_ACT# <23>

PAD_LOCK# <32,34>

C283
10U_1206_10V4Z

1

1

2

2

ADB0 <32,34>
ADB1 <32,34>
ADB2 <32,34>
ADB3 <32,34>
ADB4 <32,34>
ADB5 <32,34>
ADB6 <32,34>
ADB7 <32,34>

+3VBIOS

10K_0402_5%

BIOS_RST# <34>

EC_ON<32,34>

PWR_LED#<32,34>
CHARGE_LED#<32,34>
BATT_LED#<32,34>
WL_BT_LED<28>

EC_ON

TC7SH32FU_SSOP5

D

LID_SW#

ON/OFFBTN#

+3VALW

22K_0402_5%

FWE#

R726 10K_0402_1%

1 2

12

R349
22K_0402_5%

1 2

R347

+3VALW

5

P

4

O

G

U17

3

+3VALW

HW_RADIO_DIS

E

LID_SW# <32,34>

Power BTN

+3VALW

12

R346

3
2

+3VALW

12

100K_0402_5%

ON/OFF

Q27
DTC124EK_SC59

13

1000P_0402_50V7K

R301
100K_0402_5%

1 3

D

1

2

C319

2

G

S

Q15
2N7002_SOT23

FWR# <32,34>

ON/OFF <32,34>
51ON# <44>

12

D13

RLZ20A_LL34

SUSP# <16,24,32,34,37,42>

EC_FLASH# <21>

D14

1

DAN202U_SC70

2

I0

1

I1

2

LED Board

JLED1

1
2
3
4
5
6
7
8

Compal Electronics, Inc.

Title

BIOS & EXT. I/O PORT

Size Document Number Rev

Custom

LA-2361

Date: Sheet

9

1

9
2
3
4
5
6
7

10

8

10

ACES_85205-0800

33 50Monday, October 04, 2004

E

0.0

of

5

LPC_LAD[0..3]<20,31,32>

D D

GATEA20<20,32>
KBRST#<20,32>
SIRQA<32>
LPC_LFRAME#<20,31,32>

CLK_33M_LPCEC<18,32>
PCIRST#26,27,28,32>

ECRST#<32>

EC_SCI#<21,32>

KSI[0..7]<32,33>
KSO[0..15]<32,33>

PAD_LOCK#<32,33>

SLP_S3#<21,32>
LID_SWOUT#<21,32>
SLP_S5#<21,32>

LID_SW#<32,33>

ICH_PME#,28,31,32>

CLKRUN#

TCK<32>
TDO<32>

SMB_EC_DA2<16,32>
SMB_EC_CK2<16,32>
SMB_EC_DA1,32,33,38,39>
SMB_EC_CK1,32,33,38,39>

ECDEBUG<32>
SCROLLLOCK#<32,33>
PWR_LED#<32,33>
NUMLOCK#<32,33>
CHARGE_LED#<32,33>
BATT_LED#<32,33>
CAPLOCK#<32,33>

SYSON<32,37,42>
RSMRST#<21,32>

BKOFF#<16,32>

EC_SMI#<21,32>

SUSP#
PWRBTN_OUT#<21,32>

CRY1<32>
CRY2<32>

4,26,28,31,32>

C C

B B

32,33,37,42>

A A

LPC_LAD[0..3]

GATEA20
KBRST#

LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

PCIRST#
ECRST#
EC_SCI#
PM_CLKRUN#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

TCK
TDO

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

SCROLLLOCK#

EC_SMI#

CRY1
CRY2

U37

1

GA20/ GPIO00/GA20

2

KBRST#/GPIO01/KBRST#

3

SERIRQ

5

LPC_FRAME# / LFRAME#

6

LPC AD3/LAD3

9

LPC AD2/LAD2

10

LPC AD1/LAD1

12

LPC AD0/LAD0

14

CLK_PCI_EC/PCICLK

15

PCIRST#

42

EC RST#/ ECRST#

24

EC SCI#/SCI#/GPIO0E

44

PM_CLKRUN#/ CLKRUN#

63

KSI0/GPIO30

64

KSI1/GPIO31

65

KSI2/GPI032

66

KSI3/GPIO33

67

KSI4/GPIO34

68

KSI5/GPI035

69

KSI6/GPIO36

70

KSI7/GPIO37

47

KSO0/GPIO20

48

KSO1/GPIO21

49

KSO2/GPIO22

50

KSO3/GPIO23

51

KSO4/GPIO24

52

KSO5/GPIO25

53

KSO6/GPIO26

54

KSO7/GPIO27

55

KSO8/GPIO28

56

KSO9/GPIO29

57

KSO10/GPIO2A

58

KSO11/GPIO2B

59

KSO12/GPIO2C

60

KSO13/GPIO2D

61

KSO14/GPIO2E

62

KSO15/GPIO2F

89

EC URXD/KSO16/GPIO48

90

EC UTXD/KSO17/GPIO49

88

EC SMD2/ GPIO47/SDA2

87

EC SMC2/GPIO46/SCL2

86

EC SMD1/GPIO44/SDA1

85

EC SMC1/GPIO44/SCL1

34

PCM_SPK#/EMAIL_LED#/ GPIO16

35

SB_SPKR/PWR_SUSP_LED#/ GPIO17

38

PWRLED#/ GPIO19

40

NUMLED#/ GPIO1A

99

BATT CHGI LED#/ E51CS#

101

BATT LOW LED#/ E51MR0

100

CAPS LED#/ E51TMR1

102

ARROW LED#/ E51 INT0

104

SYSON/GPIO56/ E51 INT1

4

EC_RSMRST#/ GPIO02

7

BKOFF#/GPIO03

8

PM SLP S3#/GPIO04

16

EC LID OUT#/GPIO06

17

PM SLP S05#/ GPIO07

18

EC SMI#/GPIO08

19

EC SWI#/GPIO09

20

LID SW#/ GPIO0A

21

SUSP#/GPIO0B

22

PBTN_OUT#/GPIO0C

23

EC PME#/GPIO0D

140

XCLKO

138

XCLKI

Host

INTERFACE

key Matrix

scan

+3VALW

11

139

26

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

SM BUS

GND

GND

103

129

+EC_AVCC

105

75

127

141

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

VCC

VCC

AD BID0/AD3/GPIO3B

EC_AVCC / AVCC

DAC_BRIG/DA0/GPIO3D

PWR

EN DFAN1/DA1/GPIO3D

EN DFAN2/DA3/ GPIO3F

FAN/PWM

INVT_PWM/GPIO0F/PWM1

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4
FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Data
BUS

Address

BUS

GND13GND28GND39GND

AGND

77

4

ADP_I/AD2/GPIO3A

AD INtput or GPI

IREF2/DA2

DA output or GPO

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1
ADB2/D2

ADB3/ D3

ADB4/D4
ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8

KBA9/A9
KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

KB910L_LQFP144@

ECAGND

BATT_TEMP

71

BATT_OVP

72

M/B_ID

73
74

76
78
79

ICH_PWRGD

80

25
27

ICH_BATLOW#

30
31
32
33

PSCLK1T

91

PSDAT1T

92

PSCLK2

93

PSDAT2

94

PSCLK3

95

PSDAT3

96

ADB0

125

ADB1

126

ADB2

128

ADB3

130

ADB4

131

ADB5

132

ADB6

133

ADB7

134

KBA0

111

KBA1

112

KBA2

113

KBA3

114

KBA4

115

KBA5

116

KBA6

117

KBA7

118

KBA8

119

KBA9

120

KBA10

121

KBA11

122

KBA12

123

KBA13

124

KBA14

110

KBA15

109

KBA16

108

KBA17

107

KBA18

106

KBA19

98
84

97
135
136
144

41
43
29
36

SLP_S4#

45
46

81
82
83

THERMATRIP_VGA#

137
142
143

ECAGND <32>

BATT_TEMP <32,39>
BATT_OVP <32,40>
M/B_ID <32>
USER_BTN2# <32,33>

DAC_BRIG <16,32>
EN_FAN1 <32>

IREF <32,40>

ICH_PWRGD <21,32>

INVT_PWM <16,32>

BEEP# <30,32>

ICH_BATLOW# <21,32>

ACOFF <32,40>

FAN1SPD <32>

BIA <10,16,32>

PSCLK1T <32>
PSDAT1T <32>
PSCLK2 <32>
PSDAT2 <32>
PSCLK3 <32>
PSDAT3 <32>

+VCCP_PWRGD <32,42>

COMPAL_INT# <32,38>
FRD# <32,33>
FWR# <32,33>
FSEL# <32,33>

EC_ON <32,33>

ACIN <21,32,40,41>

EC_THRM# <21,32>

ON/OFF <32,33>

SLP_S4# <21,32>

USER_BTN1# <32,33>

MSEN# <17,32>
FSTCHG <32,40>
VR_ON <32,37,45>

PROCHOT# <5,32>

EN_FAN1<32>

THERMATRIP_VGA# <16,32>

3

R622

100K_0402_5%

1 2

2

ADB[0..7]
KBA[0..19]

ADB[0..7] <32,33>
KBA[0..19] <32,33>

C

+3VALW

BIOS_RST#<33>

FWR#<32,33>
FRD#<32,33>
FSEL#<32,33>

FAN1VREF
FAN1_VFB

1

C551

2

1U_0603_10V4Z

R616

1 2

150K_0402_5%

BIOS_RST#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

H_THERMDA<5>

H_THERMDC<5>

+12VALW

8

3

+IN

2

-IN

4

C545

2200P_0402_50V7K

1 2

R590

100K_0402_5%

ELCO_00-6278-034-001-800@

SMB_EC_CK2<16,32>
SMB_EC_DA2<16,32>

U33A

P

OUT
G

LM358A_SO8

12

1

JDBUG1

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

H_THERMDA

H_THERMDC

FAN1_ON

RB751V_SOD323

+3VS

+5VS

1

G

3

D17

2 1

22U_1206_16V4Z_V1

SMB_EC_DA2<16,32>
SMB_EC_CK2<16,32>

2

4 5

1

2

SMB_EC_CK2
SMB_EC_DA2

6

D

S

C537

SMB_EC_DA2
SMB_EC_CK2

1

C141
2200P_0402_50V7K

2

R136

8.2K_0402_5%

Q41

SI3456DV-T1_TSOP6

1

C155

2

1000P_0402_50V7K

12

B

2222 SYMBOL(SOT23-NEW)

U32

1

SDA

VCC

SCL

A0
A1

OS#

A2

GND

LM75CIMMX-5_MSOP8

@

0.1U_0603_25V7M

U9

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032AR_SO8

12

R140

8.2K_0402_5%

2
3
4

2
3
8
7

FAN1 Control and Tachometer

FAN1_VOUT

JFAN1

1
2
3

ACES_85205-0300

FAN1

1

1

E3

+5VS

8
7
6
5

R560 1K_0402_5%

+3VS

C132

1
6
4
5

+3VS

2

1

C527

0.1U_0402_16V4Z

2

@

1 2

@

1

2

12

R163
10K_0402_5%

1

C156

0.01U_0402_16V7K

2

12

R149
10K_0402_5%

FAN1SPD <32>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Thermal sensor and Fan

LA-2361

34 50Monday, October 04, 2004

1

0.0

of

5

4

+3VS

3

12

L32
0_0603_5%

2

1

D D

0.1U_0402_16V4Z

USBP2+<21>

T24

USBP2-<21>

PAD@

COEX1_BT_ACTIVE<28>

HW_RADIO_DIS#<28,33>

COEX2_WLAN_ACTIVE<28>

BT_ACTIVE<28>

C C

JP3 ACES_88021-3001

MD_MIC<29>

+3V

IAC_SDATO_MDC<20>

IAC_RST#_MDC<20>

B B

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

MDC CONN.

AUDIO_PWDN
MONO_PHONE
Bluetooth Enable

AC97_SDATA_IN1
AC97_SDATA_IN0

AC97_BITCLK

GND131GND232GND333GND434GND535GND6

COEX3
COEX1_BT_ACTIVE
HW_RADIO_DIS#
COEX2_WLAN_ACTIVE

GND

+5V

USB Data+

USB Data-

PRIMARY DN

5Vd

GND

AC97_SYNC

GND

36

USB2+
USB2-

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

1

C605

2

Definition

R631 0_0402_5%

BT_PWR

MD_SPK <29>

1 2

R629 10K_0402_5%

1 2

R637

1 2

22_0402_5%

JBTP1

1
2
3
4
5

11

6

12
7
8
9
10

JST_BM10B-SRSS-TB

R6260_0402_5%@

12

0.1U_0402_16V4Z

C562

1 2

@

1 2

R63422_0402_5%

1 2

R63622_0402_5%

IAC_BITCLK <20,29>

1

1

1

H22
HOLEA

1

H5
HOLEA

1

H16
HOLEA

1

H14
HOLEA

1

FM5

@

CF7

@

CF13

@

@

1

1

1

H25
HOLEA

1

H12
HOLEA

1

H15
HOLEA

1

FM4

@

CF4

@

CF12

@

@

@

1

1

1

H24
HOLEA

1

H11
HOLEA

1

H19
HOLEA

1

M1
HOLEA

1

FM6

@

CF10

@

CF16

@

@

1

1

1

H13
HOLEA

H1
HOLEA

H18
HOLEA

1

CF11

@

CF15

@

1

1

CF2

@

1

1

CF14

@

1

1

H4
HOLEA

@

1

H2

H3

HOLEA

HOLEA

@

@

1

1

FM2

FM1

@

CF3

@

CF8

@

H10
HOLEA

@

H7
HOLEA

+5VS

H8
HOLEA

H21

HOLEA

@

+3V

@

IAC_SYNC_MDC <20>
IAC_SDATAI2 <20>

@

H20
HOLEA

FM3

@

@

1

1

CF9

CF1

@

@

1

1

CF5

CF6

@

@

1

1

H23
HOLEA

@

@

1

1

H6
HOLEA

1

1

H9
HOLEA

1

1

H17
HOLEA

@

1

1

@

1

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SUBWOOFER,BT PORT and MDC

LA-2361

35 50Monday, October 04, 2004

1

0.0

of

A

B

C

D

E

+USB_CS

+5VS

U3

1

GND

2

IN

1

1 1

2 2

C18

0.1U_0402_16V4Z

2

+5VS

1

C154

0.1U_0402_16V4Z

2

12

R6
100K_0402_5%

3

IN

4

EN#

TPS2061IDGN_MSOP8

1
2
3
4

12

R158
100K_0402_5%

U13

GND
IN
IN
EN#

TPS2061IDGN_MSOP8

OUT
OUT
OUT
OC#

OUT
OUT
OUT

OC#

8
7
6

R754 0_0402_5%

5

R755 0_0402_5%

+USB_AS

8
7
6
5

1 2
1 2

OVCUR#0 <21> USBP0-<21>

OVCUR#3 <21>
OVCUR#4 <21>

USBP4-<21>
USBP4+<21>

10P_0402_25V8K

C26
150U_D2_6.3VM @

1

C629

2

@

USBP0+<21>

470P_0402_50V7K

1

+

2

1

C630
10P_0402_25V8K

2

@

10P_0402_25V8K

1

C316

@

2

C157

150U_D2_6.3VM

1

C627

2

@

JUSBP1

1

VCC

2

D0-

3

D0+

4

VSS
G210G1

12

G4

SUYIN_020122MR008S540ZU

470P_0402_50V7K

1

+

2

1

C628
10P_0402_25V8K

2

@

VCC

D1+
VSS

D1-

G3

1

2

5
6
7
8

9
11

+USB_AS

C528

+USB_CS

470P_0402_50V7K

1

C317

2

10P_0402_25V8K

JUSBP2

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

SUYIN_2569AR-04G5T

1

+

150U_D2_6.3VM

2

1

C631

2

@

C25

1

2

@

C632
10P_0402_25V8K

USBP3- <21>
USBP3+ <21>

+USB_BS

470P_0402_50V7K

1

2

@

D

1

2

1

C634
10P_0402_25V8K

2

C312

JUSBP3

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

SUYIN_020173MR004S512ZL

Compal Electronics, Inc.

Title

USB / FIR / TPM

Size Document Number Rev

Custom

LA-2361

Date: Sheet

E

of

36 50Monday, October 04, 2004

0.0

+

C24

3 3

+5VS

U26

1

GND

2

IN

R345
100K_0402_5%

3

IN

4

EN#

TPS2061IDGN_MSOP8

1

C315

0.1U_0402_16V4Z

2

4 4

A

12

OUT
OUT
OUT

OC#

8
7
6
5

+USB_BS

B

OVCUR#1 <21>

USBP1-<21>
USBP1+<21>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

150U_D2_6.3VM

10P_0402_25V8K

1

C633

2

@

5

4

3

2

1

+3VALW +3VS

Q8

8

S

D

7

S

C221
22U_1206_10V4Z

D D

C222
22U_1206_10V4Z

D

6

D

5

D

AO4422_SO8
C223
10U_1206_10V4Z

S
G

+3VALW to +3V Transfer

Q38

S

D

S

D

S

D

G

D

AO4422_SO8

10U_1206_10V4Z

C260

0.01U_0402_16V7K

+2.5VS+2.5V

1

S

2

S

3

S

4

G

C274

1
2
3
4

+5VALW

8
7

R291
100K_0402_5%

R289
1M_0402_5%

D

Q12
2N7002_SOT23

S

6
5

C496
10U_1206_10V4Z

C273

10U_1206_10V4Z

Q7

8

D

7

D

6

D

5

D

AO4422_SO8
C158
10U_1206_10V4Z

C494

10U_1206_10V4Z

C C

SUSP

B B

A A

C495

10U_1206_10V4Z

+12VALW

12

13

2

G

+3VALW to +3VS Transfer

1
2
3
4

+3V+3VALW

SUSON

C220

22U_1206_10V4Z

RUNON

C449
22U_1206_10V4Z

C225

0.1U_0402_16V4Z

C448

0.1U_0402_16V7K

+5VALW to +5VS Transfer

+5VS

Q13

S

D

S

D

S

D

G

D

AO4422_SO8

RUNON

1
2

0.1U_0402_16V7K

3
4

C264

8
7
6
5

+2.5V to +2.5VS Transfer

C151
C152
22U_1206_10V4Z

RUNON

C153

0.1U_0402_16V7K

0.1U_0402_16V7K

D

S

R407
470_0402_5%

13

D

S

1

2

R224
470_0402_5%

Q9

13

2

2N7002_SOT23

G

SYSON#

Q34

2

G

2N7002_SOT23

C272
22U_1206_10V4Z

SUSP

D

S

R290
470_0402_5%

13

Q11

G

2N7002_SOT23

+3VALW +CPU_CORE

R373

2

G

R619
47K_0402_5%

SUSON

Q43
2N7002_SOT23

R621
1M_0402_5%

S

330_0603_5%

@

13

D

Q30
2N7002_SOT23

@

S

12

1

C390

0.1U_0402_16V4Z

2

1

C550

0.01U_0402_16V7K

2

SUSP<16,43,44>

SUSP#<16,24,32,33,34,42>

0.1U_0402_16V4Z

C387

SUSP#

SUSON

Q36

2N7002_SOT23

2

SUSP

2

1

G

+5VALW

12

13

D

2

G

S

12

R452
100K_0402_5%

R453
51K_0402_5%

13

D

S

R618
10K_0402_1%

Q42
2N7002_SOT23

+12VALW+12VALW

Q37
NDS352AP P-CHANNEL_SOT23

S

G

2

D

1 3

1

C406

4.7U_1206_16V6K

2

+12V

R371

@

100K_0402_5%

13

D

Q31

2

2N7002_SOT23

G

@

S

+12VALW

12

12

R620
47K_0402_5%

13

SYSON#

13

D

Q44
2N7002_SOT23

S

+5VALW +5V

SUSON

D

2

G

S

Q35
AO3400_SOT23

D

1 3

G

2

2

3

1

VR_ON

+12VALW

2

G

D18
SM05_SOT23

@

VR_ON<32,34,45>

SYSON<32,34,42>

SUSP

2

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

POWER CONTROL

LA-2361

37 50Monday, October 04, 2004

1

0.0

of

5

VIN_FAN1
PAD

VIN_FAN2

12

1

R764

R767

VIN_FAN2
PAD

12

+5VS
+5VS
+5VS

C636
1U_0603_10V4Z

2

FAN2_GATE

VIN_FAN1

1

C638
1U_0603_10V4Z

2

FAN1_GATE

CLK_14M_COMPAL<29>

R771
R772
R773

VIN_LDO1

PAD

LDO1EN1 PAD

LDO1EN2 PAD

LDO2EN1 PAD

FAN1_VOUT1 PAD C639

22U_1206_10V4Z

FAN2_VOUT1 PAD

22U_1206_10V4Z

SMB_EC_CK1<16,32,33,34,39>
SMB_EC_DA1<16,32,33,34,39>

RESET#

1 2

4.7K_0402_5%

SCL

1 2

4.7K_0402_5%

SDA

1 2

@

4.7K_0402_5%

@

C641

C642

1 2

1

2

1

2

C643

0.1U_0402_16V4Z

D D

100K_0402_5%

100K_0402_5%

C C

VIN_LDO1
LDO1_FB

LDO1EN
LDO2_FB

VIN_FAN1

FAN1_GATE

VIN_FAN2

FAN2_GATE

RESET#

SCL
SDA

4

U39

1

LDO1_VINA

48

LDO1_VINB

5

LDO1_FB

2

LDO1_EN

12

LDVO2_VINA

13

LDVO2_VINB

8

LDO2_FB

11

LDO2_EN

26

FAN1_VINA

25

FAN1_VINB

24

FAN1_VOUTA

23

FAN1_VOUTB

27

FAN1_GATE

46

FAN1_TACHFB/GPIO8

35

FAN2_VINA

36

FAN2_VINB

37

FAN2_OUTA

38

FAN2_OUTB

34

FAN2_GATE

47

FAN2_TACHFB/GPIO9

45

RESET#

39

CLK14M

40

SCL

41

SDA

@

+5VS

18

6

VCC2/5V

VCC2/5V32VCC2/5V

AVCC1/5V

LDO1

LDO2

charge pump

0.1U_0402_16V4Z

42

LDO1_VOUTB
LDO1_VOUTA

LDO2_VOUTB
LDO2_VOUTA

FAN

CP_OUT

CP_EN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

VSS2(GND)
VSS2(GND)
VSS2(GND)

VSS1/AGND

C644

CPP

CPN

INT#

1

2

4

LDO1_VOUT

3

9

LDO2_VOUT

10

29
28
30

33

14
15
16
17
20
21
22

44
19

31
43
7

+5VS

1

C645

0.1U_0402_16V4Z

2

CP_OUTPAD
CP_EN1PAD

1

1U_0603_10V4Z

2

12

R770

4.7K_0402_5%

LDO1_VOUT

10K_0402_1%

LDO1_FB

10K_0402_1%

LDO2_VOUT

10K_0402_1%

LDO2_FB

10K_0402_1%

COMPAL_INT# <32,34>

+5VS

R765

R766

R768

R769

3

VOUT_LDO1PAD

1

12

C637
22U_1206_10V4Z

2

2

1

12

VOUT_LDO2PAD

1

12

C640
22U_1206_10V4Z

2

12

B B

A A

Title

<Title>

Size Document Number Rev

<Doc> <RevCode>

C

5

4

3

2

Date: Sheet

1

of

38 50Monday, October 04, 2004

A

1 1

B

C

D

BATT+

12

PC4

560P_0402_50V7K

VIN

12

12

PR5
10_1206_5%

PD30
RLZ24B_LL34

BATT+

12

PC7

0.01U_0402_25V7K

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

PJPD1

1

2

G
G

3

SINGA_2DC-S756B200

2 2

P1

12

PC1

560P_0402_50V7K

VL

FBM-L18-453215-900LMA90T_1812

1 2

12

PC2

12P_0402_50V8J

PR14

2.2M_0402_5%

VS

PL1

12

12

PC3

12P_0402_50V8J

PL2

HCB4532K-800T90_1812

1 2

PC8

1000P_0402_50V7K

SUYIN 200275MR007G113ZL 7P

12

PJP1

BATT++

BATT++P1

1 2

1
2
3
4
5
6
7

PR18

1K_0402_5%

12

1 2

1 2

PR22

100_0402_5%

1 2

PR25

100_0402_5%

BATT_TEMP

PR15

1K_0402_5%

PR21

25.5K_0402_1%

BATT_TEMP <32,34>

+3VALWP

SMB_EC_DA1 <16,32,33,34,38>

SMB_EC_CK1 <16,32,33,34,38>

B+

3 3

MAINPWRON

0,41,44>

ACON<40>

100K_0402_1%

PD2

2
3

RB715F_SOT323

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

4 4

BATT ONLY

PR16

1

12

12

PC11

0.1U_0603_25V7K

VL

1

O

PR23

34K_0402_1%

LM393M_SO8

8

3

P

+

2

-

G

4

12

66.5K_0402_1%

PU1A

12

PC12

1000P_0402_50V7K

PR26

12

PR17
499K_0402_1%

12

PR19

191K_0402_1%

PRG++

RHU002N06_SOT323

PQ1

13

D

2

G

S

12

13

12

47K_0402_5%

PR24

12

PQ2
DTC115EUA_SC70

2

PR20
499K_0402_1%

PACIN

12

PC10
1000P_0402_50V7K

PACIN <40>

+5VALWP

VIN

PD1

1N4148_SOD80

VIN+

12

PR10

1.5K_1206_5%

1 2

PR11

1.5K_1206_5%

1 2

PR12

1.5K_1206_5%

1 2

PR13

1.5K_1206_5%

1 2

B+

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

SECRET INFORMATION. THIS SHEET MAY NOT BE
TRANSFERRED FROM THE

C

Compal Electronics, Inc.

Title

DCIN & DETECTOR & Precharge

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

D

of

39 50Monday, October 04, 2004

0.1

A

B

C

D

E

Charger

Iadp=0~3A(65W)

PQ31

AO4407_SO8

47K

2

47K

13

PQ35

DTC115EUA_SC70

1SS355_SOD323

1 2

ACON

22K_0402_5%

1 2

12

8
7

5

1 3

PR162

150K_0402_5%

RHU002N06_SOT323

PQ39

2

G

PD28

PR171

PD31

RLZ4.3B_LL34

VIN

1 1

DTA144EUA_SC70

12

PR158

47K_0402_5%

13

D

2

G

S

PQ37

RHU002N06_SOT323

2 2

PQ34

2

ACOFF#

ACON<39>

PACIN<39>

ACIN <21,32,34,41>

ACIN

1 2

PR4

3 3

10K_0402_5%

P2

1
2
36

4

12

12

PC141

0.1U_0603_25V7K

12

13

D

PR167

100K_0402_1%

S

PACIN

PR175

158K_0603_1%@

PQ32

AO4407_SO8

1
2
3 6

4

PR159

200K_0402_1%

150K_0402_1%

PR164

12

12

12

PC144

0.1U_0402_16V7K

IREF<32,34>

PR172

10K_0402_5%

12

PQ40

DTC115EUA_SC70

PC142

1U_0603_10V6K

1908LDO

8
7

5

12

0_0402_5%@

12

13

PR166

9.31K_0402_1%

PR190

1908LDO

2

VIN

12

0_0402_5%

12

12

FSTCHG<32,34>

P3

12

PC158

0.1U_0603_25V7K

@

1SS355_SOD323

PD25

12

PR168

PR173

100K_0402_1%

2P4S:4300mAH/cell

0.7C=3.0A

PR180

PACIN

PR191
10K_0402_1%

PR192
10K_0402_1%

B

150K_0402_1%

1 2

PR194

681K_0603_1%

OVP voltage :

LI-3S :17.8V----BATT-OVP=1.9758V

BATT-OVP=0.111*BATT+

+2.5V

12

12

4 4

+SDREF

A

PU14B

LM358A_SO8

7

VS

5

+

0

6

-

0.01_2512_1%

12

PR184

15K_0402_1%

12

PC149

PR177

0_0402_5%

1 2

PR193

100K_0402_5%

VIN

12

12

PR157

2

4

3

1

12

PC143

0.1U_0603_25V7K

12

0.01U_0402_16V7K

1 2

PR178

PR182
20K_0402_1%

PROPRIETARY NOTE

B+

1 2

PL16

HCB4532K-800T90_1812

12

PC159

0.1U_0603_25V7K

@

MAX1908ETI_QFN28

1

PR163

0_0402_5%

12

17

0_0402_5%

1 2

10K_0402_5%

4
3

12

15
13

11

8

12

10

9

PR169

28

7

PR174

1K_0402_1%

1 2

12

PC154

PC152

0.1U_0402_16V7K

12

PC155

0.1U_0402_16V7K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PU13

DCIN

CELLS

REF
CLS

REFIN

VCTL
ICTL

ACOK#
SHDN#
ACIN
ICHG

IINP
CCV

0.001U_0402_50V7M

BATT_OVP<32,34>

6

12

CCI

C

CCS

5

MAX1908-CCS

1 2

14

PC153

0.001U_0402_50V7M

GND

12

PC138

4.7U_1206_25V6K

CSSP

CSSN

DHI

LX

DLO

BST

DLOV

LDO

CSIP
CSIN
BATT

PGND

20

PU14A

LM358A_SO8

1

12

0

12

PC140

PC139

4.7U_1206_25V6K

4.7U_1206_25V6K

PQ38

1 2

BATT+

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

1 2

PR1 0_0402_5%

PC151

1U_0603_10V6K

BATT+

12

PR179
845K_0603_1%

12

PC156

PR181
300K_0603_0.1%

0.01U_0402_25V7K

12

PR183
143K_0402_1%

27

26

25

23

21

24

22
2

1908LDO
19
18
16

VS

12

8

3

P

+

2

-

G

4

AO4912_SO8

PR170

33_1206_5%

S1/A

12

D2
D2
G1

D

1
2
3
4

1 2

12

PC157

0.01U_0402_25V7K

PC150

1
2
3 6

PR161

10K_0402_5%

ACOFF#

16UH_D104C-919AS-160M_3.7A_20%
PC145

1 2

0.1U_0603_25V7K

12

PD27
1SS355_SOD323

1U_0805_25V4Z

PQ33

AO4407_SO8

8
7

5

4

PR160

47K_0402_5%

1 2

1 2
13

10K

10K

DTC114EKA_SC59

1 2

PL17

PQ36

2

12

RLZ22B_LL34

PD24

1SS355_SOD323

1 2

1 2

1SS355_SOD323

PR165

0.015_2512_1%

1 2

VIN

PD26

PD32

ACOFF<32,34>

BATT+

12

12

PC146

4.7U_1206_25V6K

12

PC148

PC147

4.7U_1206_25V6K

4.7U_1206_25V6K

Charge voltage

4S CC-CV MODE : 16.8V

Compal Electronics, Inc.

Title

Charger

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

E

of

40 50Monday, October 04, 2004

0.1

A

B

C

D

E

+3.3V/+5V/+12V

B+

+3VALWP Choke DCR = 26.5mΩ.

Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A
OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A

1 1

PL8

FBM-L18-453215-900LMA90T_1812

1 2

B+++

12

12

PC74

PC73

2200P_0402_50V7K@

4.7U_1206_25V6K

2 2

12

PC81
47P_0402_50V8J

12

10UH_D104C-919AS-100M_4.5A_20%

+3VALWP

PC85

1

3 3

+

2

2 1

150U_D2_6.3VM

PL10

SKUL30-02AT_SMA

PR101

3.57K_0402_1%

12

PC84

1 2

100P_0402_50V8J

PR104

1 2

10K_0402_1%

PD17

2 1

PD16

SKS10-04AT_TSMA

@

PR94

1M_0402_1%

1.27K_0402_1%

1.27K_0402_1%

1 2

PQ17

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

1 2

PR92

PR93

ACIN<21,32,34,40>

PC71

0.1U_0603_25V7K

1 2

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

LX3

12

PC82

0.47U_0603_16V7K

619_0402_1%

1 2

1 2

PR98

10K_0402_5%

@300K_0402_5%

PR105

100K_0402_5%

12

PR97

PR100

VS

12

12

DL3

12

PC91
1U_0805_25V4Z

12

PR89
0_0402_5%

DH3

12

PC86

1000P_0402_50V7K

DAP202U_SOT323

PD15

1SS355_SOD323

33_1206_5%

PC78

0.1U_0603_25V7K

PU6

25
27
26

24

1
2

3
10
23

7
28

12

PC90

0.47U_0603_16V7K

PD14

PR2

12

BST3
DH3
LX3

DL3

CSH3
CSL3
FB3
SKIP#
SHDN#

TIME/ON5
RUN/ON3

2

VL

V+

1

12

ACIN

21

12OUT

VL

BST5

PGND

CSH5

CSL5

SYNC

RST#

GND

MAX1902EAI_SSOP28

8

VS

1 2
12

22

MAINPWRON <20,39,44>

VDD

SEQ

DH5

REF

LX5
DL5

FB5

RHU002N06_SOT323@

3

PC75

4.7U_0805_10V4Z

PQ41

4
5
18
16
17
19
20
14
13
12
15
9
6
11

PR102

0_0402_5%

BST51BST31

PC72

0.1U_0603_25V7K

1 2

+12VALWP

12

PR187

13

D

2

G

S

1 2

2.7K_1206_5%@

12

12

PC87

4.7U_0805_10V4Z

PR91
0_0402_5%

1 2

PC162

4.7U_1206_25V6K

BST5

DH5

DL5

2.5VREF

0.47U_0603_16V7K

LX5

PC83

8
7
6
5

12

PQ18

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4912_SO8

12

PR99
698_0402_1%

12

PR103

10.2K_0402_1%

12

D2
D2
G1

S1/A

PR106
10K_0402_1%

PC161
470P_0805_100V7K

@

1 2

FLYBACKSNB

12

PR186
22_1206_5%@

B+++

1
2
3
4

PR96

1.54K_0402_1%

12

PC89

100P_0402_50V8J

12

PC76

12

12

PC77

2200P_0402_50V7K@

SKS10-04AT_TSMA

4.7U_1206_25V6K

PD18

+5VALWP Choke DCR = 40mΩ.
Current limit Threshold Min.=80 mV Mx.=120mV.

OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A

4 4

OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A
RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

3.3V / 5V / 12V

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

PC160

4.7U_1206_25V6K

1 2

12

PD29
EC11FS2_SOD106

PL9
10uH_SDT-1205P-100-118_5A_20%

1 4

3 2

12

PC79
47P_0402_50V8J

12

PR95
2M_0402_1%

1

+

2

2 1

150U_D2_6.3VM

Compal Electronics, Inc.

E

PC88

+5VALWP

41 50Monday, October 04, 2004

0.1

of

5

D D

4

12

12

PC35

PC34

1 2

2200P_0402_50V7K

@

@

12

PC36

PC37

4.7U_1206_25V6K

0.1U_0603_25V7K

4.7U_1206_25V6K

1 2

3

PR51
51_1206_5%

+5VALWP

2

1

B+

+VCCPP

12

12

12

12

10
15
11

PR65
91K_0402_1%

PU4

6

5
4

7
2

3

9
8

PC38

0.1U_0603_25V7K

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

14

VIN

ISL6227

GND

1

1

PD7

PQ12

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

SYSON<32,34,37>

AO4912_SO8

1000P_0402_25V8K@

PC54

PR68

0_0402_5%

+2.5VPGD

C C

+2.5VP

1

+

12

PC49

4.7U_0805_6.3V6K@

B B

2

PR61

18.2K_0402_1%

PR64

10K_0402_1%

PL5

4.7UH_D104C-919AS_4R7N_5.2A_20%

1 2

PC48

220U_D2_4VM

12

12

PC53

0.01U_0402_25V7K

12

DAP202U_SOT323

8
7
6
5

0.1U_0603_25V7K
PC46

1 2

PR56

0_0402_5%

12

12

+3VALWP

12

PR70
10K_0402_5%

3

12

2

PC44

0.01U_0402_25V7K

1 2

PR54

0_0402_5%

PR58

2.74K_0402_1%

12

PR52

2.2_0402_5%

1 2

28

SOFT2

VCC

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

OCSET2

DDR

13

ISL6225CA_SSOP28

PC39

12

17

PC45

0.01U_0402_25V7K

1 2

23

PR55

0_0402_5%

24
25

PR59

2.74K_0402_1%

22
27

26

20
19
21
16

18

12

2.2U_0805_10V6K

12

0_0402_5%

1 2

12

PR66
91K_0402_1%

PR53

1K_0402_5%@

PC47

0.1U_0603_25V7K

12

PR57

12

+3VALWP

1 2

PR69
10K_0402_5%

SUSP# <16,24,32,33,34,37>

PQ13

8

G2

D2

7

D2

D1/S2/K

6

G1

D1/S2/K

5

D1/S2/K

S1/A

AO4912_SO8

+VCCP_PWRGD <32,34>

12

PC40

1
2
3
4

1.8UH_D104C-919AS-1R8N_9.5A_20%

PR67

0_0402_5%

Iimit=10.3/RILIM*(140+Rsense)/Rds(on) Delta I=1.84A
Isen=2.74K,OCSET=91K,Rds(on) tpy.=19.7mΩ,Max=24mΩ.

1 2

2200P_0402_50V7K

@

PL6

1 2

12

12

12

PC41

PC42

0.1U_0603_25V7K

4.7U_1206_25V6K

@

SUSP# <16,24,32,33,34,37>

PC43

4.7U_1206_25V6K

PC52

0.01U_0402_25V7K

PR63

10K_0402_1%

+VCCPP

1

+

12

12

PR60

220U_D2_4VM

1.69K_0603_1%

12

PC51

PC50

1 2

2

4.7U_0805_6.3V6K

@

Iimit Min=10.3/91K*(140+2.74K)/(24mΩ*1.3)-1/2 Delta I=9.53A

A A

Iimit=10.3/RILIM*(140+Rsense)/Rds(on) Delta I=1.54A

Iimit Max=10.3/91K*(140+2.74K)/19.7mΩ-1/2 Delta=15.73A

Isen=2.74K,OCSET=91K,Rds(on) tpy.=19.7mΩ,Max=24mΩ.
Iimit Min=10.3/91K*(140+2.74K)/(24mΩ*1.3)-1/2 Delta I=9.67A
Iimit Max=10.3/91K*(140+2.74K)/19.7mΩ-1/2 Delta=15.77A

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

COMPAL ELECTRONICS, INC

Title

+2.5VP & +VCCPP

Size Document Number Rev

B

Date: Sheet

AL50 La-2361

1

of

42 50Monday, October 04, 2004

0.1

5

D D

4

3

2

1

PJP2
3MM

21

+5VALWP

C C

PJP4
3MM

+3VALWP +3VALW

PJP6
3MM

+2.5VP

PJP8
3MM

+1.25VSP

PJP10
3MM

+1.5VSP

B B

+5VALW

21

21

+2.5V

+1.25VS

21

21

+1.5VS

+12VALWP

+VCCPP +VCCP

PJP3

2MM

PJP7

3MM

+2.5VP

21

+12VALW

12

PC93
10U_1206_6.3V7K

12

PR107

1K_0402_1%

21

PC98

12

PC97

0.1U_0603_25V7K

1

+

2

12

PR108

1K_0402_1%

13

D

SUSP<16,37,44>

1 2

PR109

0_0402_5%

2

G

PQ20

RHU002N06_SOT323

S

150U_D2_6.3VM

@

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

+1.25VSP

12

PC99

4.7U_0805_6.3V6K

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC92
1U_0603_16V6K

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+1.8VSP & +1.25VSP

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

1

of

43 50Monday, October 04, 2004

0.1

A

B

C

D

PH2 under CPU botten side :

CPU thermal protection at 80 degree C
Recovery at 44(45) degree C

1 1

VL

12

PR74

2.15K_0402_1%
PR73

16.9K_0402_1%

1 2

TM_REF1

12

PC57

2 2

3 3

1000P_0402_50V7K

BATT+

PR80

200_0805_5%

12

PH1

10KB_0603_1%_TH11-3H103FT

PD10

RB751V_SOD323

12

100K_0402_5%

1U_0805_16V7K

12

PR81

PC56

12

150K_0402_1%

12

PR76
150K_0402_1%

12

1 2

PC65

0.22U_1206_25V7K

47K_0402_1%

1 2

5
6

12

PR75

TP0610T_SOT23

S

G

PR72

VS

8

+

-

4

PQ16

2

PU1B

P

O

G

LM393M_SO8

VL

D

13

12

7

VIN

1 2
12

12

PC55

0.1U_0603_25V7K

PD9
1N4148_SOD80

PR79
33_1206_5%

VS

PC63

0.1U_0603_25V7K

VL

PR71
47K_0402_1%

1 2

MAINPWRON <20,39,41>

12

PR77

12

2

G

4.12K_0402_1%

13

D

S

PC59

470P_0402_50V7K

PR189

0_0402_5%

SUSP<16,37,43>

12

PQ42

RHU002N06_SOT323

Ipeak=Iocset*Rocset/RDS(ON)high side
Iocset=40uA, Pocset=4.12K RDS(on)=25.5mΩ
Ipeak min=40uA*4.12/(25.5*1.3)=4.97A
Ipeak max=40uA*4.12/25.5=6.46A

12

PC60

0.1U_0402_16V7K

PU8

7

OCSET

6

FB

3

GND

APW7057KC-TR_SOP8

2.2_0402_5%

5

VCC

BOOT

UGATE

PHASE

LGATE

12

PR78

1SS355_SOD323

1

2

8

4

PD12

1 2

12

PC61

0.1U_0402_16V7K

PQ15

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

AO4912_SO8

4.7UH_D104C-919AS_4R7N_5.2A_20%

1 2

1

D2

2

D2

3

G1

4

S1/A

PL7

PC66

0.1U_0402_16V7K

+5VALW

8.87K_0603_1%

12

PC58

4.7U_0805_6.3V6K

PR82

12

PR84

10K_0402_1%

12

12

12

1

+

PC62
150U_D2_6.3VM

2

PC64

4.7U_0805_6.3V6K

@

+1.5VSP

51ON#<33>

4 4

CHGRTCP

1 2

22K_0402_5%

12

PC67
1U_0805_25V4Z

A

PR83

G920AT24U_SOT89

2

IN

PU7

GND

RTCVREF

12

PC68

4.7U_0805_6.3V6K

1 2

PR85

300_0402_5%

3

OUT

1

1 2

PR86

300_0402_5%

CHGRTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

C

Compal Electronics, Inc.

Title

RTC Battery & OTP & +1.5VP

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

D

of

44 50Monday, October 04, 2004

0.1

5

4

3

2

1

+CPU_CORE

CPU VCC SENSE

1 2

1 2

B+

PC125

1000P_0402_50V7K

@

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

PQ24

S1S3G

S

4

2

PR141 909_0402_1%

1 2

+5VS

5

S

4

2

5

S

4

2

CPU_B+

PQ23

AO4408_SO8

D8D7D6D

PC132

S1S3G

D8D7D6D

S1S3G

12

12

PC114

4.7U_1206_25V6K

12

PD21

PR132

1 2

EC31QS04

@

12

12

PC133

2200P_0402_50V7K

4.7U_1206_25V6K

12

PD23

EC31QS04

@

12

12

PC117

PC116

PC115

4.7U_1206_25V6K

0.56UH_ETQP4LR56WFC_21A_20%

0.01U_0402_25V7Z

PL14

1 2

12

PR134 909_0402_1%

0.47U_0603_16V7K

PC124

1 2

100K_0402_1%@

1 2

PC129

0.022U_0402_16V7K

CPU_B+

12

12

PC134

4.7U_1206_25V6K

PC135

0.01U_0402_25V7Z

0.56UH_ETQP4LR56WFC_21A_20%

1 2

12

PR155

909_0402_1%

1 2

PC137

0.47U_0603_16V7K

FBM-L18-453215-900LMA90T_1812

2200P_0402_50V7K

PL13

1 2

1 2

0.001_2512_5%

PR129

12

PR135 499_0402_1%

1 2

PR143

3K_0603_1%

1 2

PR146

0_0402_5%

PR150
100K_0402_1%

@

1 2

PL15

1

+

PC118

68U_25V_M

2

@

12

PR136 499_0402_1%

PR137

3K_0603_1%

+5VS

+3V

12

D D

PR139

PR123 0_0402_5%

PR124 0_0402_5%
PR126 0_0402_5%
PR128 0_0402_5%
PR130 0_0402_5%
PR131 0_0402_5%

PR133 0_0402_5%

1 2

VID0<6>
VID1<6>
VID2<6>
VID3<6>
VID4<6>
VID5<6>

VGATE<8,18,21>

PR138

C C

VR_ON <32,34,37>

0_0402_5%

1 2

100K_0402_5%@

1 2

1 2

13

D

PR147

S

PR149

0_0402_5%

1 2

PR142

470K_0402_5%

1 2

10.7K_0402_1%

+5VS

PR154

100K_0402_1%

PC128 0.22U_0603_16V7K

12

PC130

100P_0402_50V8J

PR144

78.7K_0603_1%

1 2

FB

PR145 100K_0402_1%

H_STP_CPU#

18,21>

RHU002N06_SOT323

B B

PM_DPRSLPVR<21>

1 2

PQ25

2

G

1 2

1

C

PSI#<6>

2

B

E

3

12

PR122

100K_0402_5%

12
12
12
12
12
12

PR140 30.1K_0402_1%

PC126

1 2

270P_0402_50V7K

1 2

13

D

2

G

S

PQ26

1 2

PR151

20K_0402_1%

PQ29

2

G

PQ30

HMBT2222A_SOT23

PR121 10_0402_5%

1 2

12

1 2

PC131

RHU002N06_SOT323

<BOM Structure>

PR153

10K_0402_1%

1 2
13

D

RHU002N06_SOT323

S

PC121
1U_0603_16V6K

VCC

10
24
23
22
21
20
19
25

4

VCC

5
6
1

12

2
8
9
7

3
18
11

27P_0402_50V8J

PU12

2.2U_0603_6.3V6K

VCC
D0
D1
D2
D3
D4
D5
VROK
S0
S1
SHDN#
TIME
CCV
TON
REF
ILIM
OFS
SUS
SKIP
GND

MAX1532AETL_TQFN40

PC120

BSTM

PGND

OAIN+

OAIN-

BSTS

GNDS

VDD

DHM

LXM
DLM

CMP
CMN

DHS

LXS
DLS
CSP
CSN

2

1

30
36

V+

26
28
27
29
31
37
38
17
16
15

FB

14

CCI

PC127 470P_0402_50V7K

35
33
34
32
40
39
13

EP10QY03

2 1

12

PC122

1 2

PR125 2_0402_5%

FB

1 2

PD20

0.01U_0402_25V7K

12

PC123

0.22U_0603_16V7K

PR148

2_0402_5%

1 2

12

PC136

0.22U_0603_16V7K

PD22

EP10QY03

PQ27

AO4408_SO8

PQ28

AO4410_SO8

AO4410_SO8

21

Vin=19V,Vo=1.484V,Io=12.5A,Fs=300KHZ,L=0.56UH
Current sense tpy.=1mΩ Max=1.1mΩ,Delta I =8.12A

A A

Iimit=ILIM(V)/20/DCR+1/2 delta I
Iimit Min={1.99V*78.7K/(78.7K+470K)/20/1.01mΩ+4.22A}*2=36.69A
Iimit Max={2.01V*78.7K/(78.7K+470K)/20/0.99mΩ+4.22A}*2=37.56A

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

PR156

909_0402_1%

2

Compal Electronics, Inc.

Title

+CPU_CORE

Size Document Number Rev

B

AL50 La-2361

Date: Sheet

1

of

45 50Monday, October 04, 2004

0.1

5

4

3

2

Version change list (P.I.R. List) Page 1 of 1

1

D D

1

2

3

4

5

6

C C

7

8

9

10

11

12

13

14

B B

15

16

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

ICH_PME# pull up +3VALW add R 10K

DVT0.2

LID_SW# pull up +3VALW add R 10K

SB +1.5V regulator footprint error

SB +1.5V regulator footprint error U8 need to reverse

R76 take off

PR191 power plane 2.5vref change to +2.5V

R398 remove to R401

H_DPRSLP# add pull up to +vccp power plane POP R546

POP U9 for lose and foot print error

U3 pin6 & pin 7 need to swap

Add R476/7 40.2 Ohm for memory

R259 short

PR122 chang power plane to +3V for EC voltage leakage

Add R224/R290/R407 470ohm and Q34/9/11 2N7002

ADD R 39K//220p to GND at R518 for modify SIRQ

Reverse the JHP1 & JMIC1 Symble error

17

18

19

20

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PIR

Size Document Number Rev

LA-2361

Date: Sheet

1

of

46 50Monday, October 04, 2004

0.0

A

B

C

D

E

Version change list (P.I.R. List) Page 1 of 2

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

1

Delete the charge circuit.

Change the CPU OTP circuit from active H

2

to active L. to active L.

For cost down solution.

3

2 2

For cost down solution.

4

Delete the charge circuit.

Change the CPU OTP circuit from active H

To cost down for +1.5VP.

To cost down for RTC charge circuit..

0.2

0.2

0.2

1.Delete the PU5 IC LM393M (SM).

2.Delete PD1 S DIO 1N4148 (SM).

3.Delete PR10,PR11,PR12,PR13 S RES 1/4W 1.5K +-5% 1206.

1.Delete PQ14 S TR DTC115EUA NPN (UMT3).

2..Delete PD8 S DIO 1SS355.

3.Change PR75 and PR76 from S RES 1/16W 100K +-1% 0402 to
S RES 1/16W 150K +-1% 0402.

4.Change PR73 from S RES 1/16W 15K +-1% 0402 to S RES

43

1/16W 16.9K +-1% 0402.

5.Change PC56 from S CER CAP .22U 16V K X7R 0603 to
S CER CAP 1U 16V K X7R 0805

6.Change PR74 from S RES 1/16W 3.4K +-1% 0402 to S

S RES 1/16W 2.15K +-1% 0402.

43

1.Change the PD12 from DIO 1N4148 (SM) to DIO 1SS355.

1.Delete the PD33 S ZEN DIO RLZ4.3B (LL-34).

43

0.2

0.2

0.2

DVT0.20.2 38

DVT

DVT

DVT

To prevent the KB-910 damag.

5

To prevent the KB-910 damag.

0.2 40

1.Change the PD17 from SCH DIO SKS10-04AT TSMA to

0.2

DVT

SCH DIO SKUL30-02AT THIN SMA.

For cost down solution.

6

For cost down solution.

7

For cost down solution.

8

3 3

For cost down solution.

9

10

Don't has pull high resister on VGATE pin.

10

10

11.

4 4

VCCPP output voltage has error. Adjustment resistor divider.

Choke Rating not enough for +1.5VP. Choke Rating not enough for +1.5VP.

A

To cost down for +1.5VP for +12VALWP circuit. 1.Delete PR187 S RES 1/8W 2.7K +-5% 1206 S7.

To cost down for DDR 2.5V.

To cost down for CPU_CORE.

To cost down for snubber circuit.

To cost down for EMI capacitor.For cost down solution.

Add pull high resister on VGATE pin.

0.2

0.2

0.2

0.2 40 0.2 DVT

0.2 0.2 DVT

0.2

0.2

0.2 0.2 DVT43

1.Delete PR62 S RES 1/16W 0 +-5% 0402.

41

1.Delete PR127 and PR152 S RES 1/16W 0 +-5% 0402.

44

1.Deete PR127 and PR152 S RES 1/16W 0 +-5% 0402.

2.Delete the PC161 S CER CAP 470P 100V K X7R 0805.

39

1.Delete PC41,PC158 and PC159 S CER CAP .1U 25V K X7R 0603.

40

2.Delete PC40,PC73 and PC76 CER CAP 2200P 50V K X7R 0402.

41

44

41

1.Add the S RES 1/16W 100K +-5% 0402.

1.Change the PR60 from S RES 1/16W 681 +-1% 0402 to
S RES 1/16W 1.69K +-1% 0603.

1.Change PL7 from 4.7UH_FDV0630-4.7UH_5.5A_20%

to 4.7UH_D104C-919AS_4R7N_5.2A_20%.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

0.2 DVT40

0.2 DVT

DVT0.2

0.2

0.2

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

AL50 La-2361

Date: Sheet

DVT

E

DVT

of

47 50Monday, October 04, 2004

0.2

A

B

C

D

E

Version change list (P.I.R. List)

Page 2 of 4

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

2 2

3 3

Don't has pull down resister on SHDN#

1

pin for charger.

Change the Vin Detector from LM393 to

2

charger ACOK#.

For ACIN pin, 1.Add PR4 the 10K +-5% 0402ACIN pin don't have connect to system.

3

+1.8VSP power rating not enough.

4

VCCP's transients cannot meet spec.

5

Change the Vin Detector from LM393 to
charger ACOK#.

+1.8VSP power rating isnot enough.

VCCP's transients cannot meet spec.

1.Add PR193 the S RES 1/16W 100K +-5% 0402.Add pull down resister on SHDN# pin.

1.Add the PQ40 S TR DTC115EUA NPN (UMT3).

2.Delete the PR3,PR4,PR8 and PR9 RES 1/16W 10K +-1% 0402.

3.Add the PR193,PR172 and PR173 RES 1/16W 100K +-5% 0402.

4.Delete PR6 the S RES 1/16W 22K +-1% 0402.

5.Delete PR1 the S RES 1/16W 1M +-1% 0402.

6.Change PR182 from S RES 1/16W 150K +-1% 0402 to S

0.2 DVT0.2

38,39

S RES 1/16W 20K +-1% 0402.

7.Delete the PR7 S RES 1/16W 20K +-1% 0402.

8.Delete the PR2 S RES 1/16W 84.5K +-1% 0402.

9.Add the PR175 S RES 1/16W 158K +-1% 0402.

10.Add the PR175 S RES 1/16W 681K +-1% 0402.

11.Delete PC6 from S CER CAP .1U 25V K X7R 0603.

12..Delete PC5 from S CER CAP 1000P 50V +-10% X7R 0402.

1.Change PU10 from S IC G965-18P1U SOP-8L REG to S IC

APW7057KC-TR SOP-8 PWM.

2.Add PR197 S RES 1/16W 12.7K +-1% 0402.

3.Add the PQ44 S TR RHU002N06 1N SOT323

4.Delete PQ43 the S TR AO4912 2N SO8 W/D

5.Add PD33 the S DIO 1SS355.

6.Add PR195 the S RES 1/16W 2.2 +-5% 0402

0.2 DVT0.2

7.Add PR198 the S RES 1/16W 10K +-1% 0402.

42

8.Add PR196 the S RES 1/16W 4.12K +-1% 0402

9.Add the PC167 the S CER CAP 4.7U 10V Z Y5V 0805.

10.Add the PC164 S CER CAP 470P 50V +-10% X7R 0402.

11.Add the PC163,PC165 and PC168 S CER CAP .1U 16V +-10%

X7R 0402

12.Delete PC96 the S CER CAP 10U 6.3V K X7R 1206.

13.Add the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.

14.Add PL18 the S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.

1.Change PC50 from S POLY CAP 150U 6.3V M V(D2) T520 LESR

0.2

to S POLY C 220U 4V M V(D2) T520 LESR.

41

2.Change PL6 from S COIL 4.7UH +-20% D104C-919AS-4R7M 5.2A

to S COIL 1.8UH +-30% D104C-919AS-1R8N 9.5A.

0.2 DVT

DVT0.20.2 39

DVT0.20.2 39

For CPU_CORE's EMI,

6

4 4

A

For CPU_CORE's EMI,

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1.Change the PR125 and PR148 from S RES 1/16W 0 +-5% 0402S

to RES 1/16W 2 +-5% 0402.

Compal Electronics, Inc.

Title

PIR

Size Document Number Rev

AL50 La-2361

D

Date: Sheet

DVT0.20.2 44

0.2

of

48 50Monday, October 04, 2004

E

A

B

C

D

E

Version change list (P.I.R. List) Page 3 of 3

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

CPU's transients cannot meet spec.

1.

PACIN pin's high level is only 2.3V. To adjust PACIN pin's level.

2.

The 5VALWP rising time is faster than

3.

PACIN's.

Add one current sense on phase 2.

To delay timer of 5VALWP.

0.2 44

0.3

1.Delete PC124 and PC137 the S CER CAP 0.47U 16V +-10% X7R

0603.

2.Delete PR134,PR141,PR155 and PR156 the S RES 1/16W

909+-1% 0402.

0.2 DVT

3.Add PR134 S RES 1W 0.01 +-1%2512.

1.Delete PR175 the S RES 1/16W 158K+-1% 0402.

2.Change the PR172 from S RES 1/16W 100K +-1% 0402 S

to RES 1/16W 10K +-1% 0402.

1.Change the PR105 from S RES 1/16W 47K +-1% 0402 S

to RES 1/16W 100K +-1% 0402.

40 0.3 DVT2

2.Change the PC91 from S CER CAP .047U 25V M X7R 0603

to CAP 1U 25V Z F Y5V 0805..

DVT0.2390.2

The charge has error on change mode.

4.

2 2

5.

For cost down solution.

The charger has EMI issue. Add a resistor on charger's boost for EMI.

6.

Change the current limit's from sense

7.

DRC to resister.

8.

MAX1902.

To adjust input and output current
regulation loop compensation.

For cost down solution. 1.Change PC58,PC68,PC95 and PC99 from the S CER CAP 4.7U

0.3

0.3

0.3

To adjust current limit point for CPU_CORE. 1.Change the PR142 from S RES 1/16W 200K +-5% 0402

To preven in-rush current for B+ of
MAX1902.

0.3

0.3 DVT2

39

1.Change PC152 and PC153 from the S CER CAP 0.01U 16V +-10%

X7R to CER CAP 0.001U 16V +-10% X7R.

42
43

25V K X5R 1206 to CAP 4.7U 10V K X7R 0805.

39

1.Add the PR1 S RES 1/16W 0 +-5% 0402.

44 DVT2

to S RES 1/16W 470K +-5% 0402.

40

1.Add PR2 S RES 1/8W 33 +-5% 1206.To preven in-rush current for B+ of

0.3

0.3

0.3

0.3

0.3

DVT2

DVT2

DVT2

1.Add PQ26 SB502060000 S TR RHU002N06 1N SOT323.

2.Add PR134,PR141,PR155,PR156 S RES 1/16W 909 +-1% 0402.

The CPU's dual choke will shortage. Change to single choke.

9.

3 3

0.3

3.Delete PL14 S COIL .5UH +-30% CXZT1050-R50 28A.

44

4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.

5.Add the PC124,PC137 0.47U 16V +-10% X7R 0603 S8.

4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.

DVT20.3

1.Delete the PU10 S IC APW7057KC-TR SOP-8 PWM.

2.Delete the PQ43 S TR AO4912 2N SO8 W/D.

3.Delete the PR188 S RES 1/16W 0 +-5% 0402.

4.Delete the PR195 S RES 1/16W 2.2 +-5% 0402

5.Delete the PR196 S RES 1/16W 4.12K +-1% 0402

6.Delete the PR198 S RES 1/16W 10K +-1% 0402

Delete the +1.8VSP on M/B. Delete the +1.8VSP on M/B.

10.

0.3

7.Delete the PR197 S RES 1/16W 12.7K +-1% 0402.

42

8.Delete the PL18 S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.

9.Delete the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.

10.Change the PC75 and PC87 from S CER CAP 4.7U 10V Z Y5V

0805 to S CER CAP 4.7U 6.3V +-10% X5R 0805

0.3 DVT2

11.Delete PC95 S CER CAP 4.7U 10V Z Y5V 0805.

12.Delete PC163,PC165,PC168 .1U 16V +-10% X7R 0402.

4 4

13.Delete PC164 S CER CAP 470P 50V +-10% X7R 0402.

14.Delete PD33 S DIO 1SS355.

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

AL50 La-2361

Date: Sheet

E

of

49 50Monday, October 04, 2004

0.2

A

B

C

D

E

Version change list (P.I.R. List) Page 4 of 4

Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem

1 1

Max1902 protect When power cord fast

1.

plug-out and plug-in.

2 2

The 5VALWP choke rating is not enough.

2.

TP0610T will EOL. Change the part.

3.

Add the pre-chagre circuit.

Change the choke.

0.3

0.3

38

40

43

1.Add PQ1 SB502060000 S TR RHU002N06 1N SOT323.

2.Add PQ2 S TR DTC115EUA NPN (UMT3).

3.Add PD2 S SCH DIO RB715F UMD3.

4.Add PD1 S DIO 1N4148 (SM)

5.Add PR10,PR11,PR12 and PR13 S RES 1/4W 1.5K +-5% 1206.

6.Add PR16 S RES 1/16W 100K +-1% 0402.

7.Add PR17 and PR20 S RES 1/16W 499K +-1% 0402.

8.Add PR19 S RES 1/16W 191K +-1% 0402.

9.Add PR23 S RES 1/16W 34K +-1% 0402.

10.Add PR26 S RES 1/16W 66.5K +-1% 0402.

11.Add PR14 S RES 1/16W 2.2M +-5% 0402.

12.Add PR24 S RES 1/16W 47K +-5% 0402.

13.Add PC10 and PC12 S CER CAP 1000P 50V +-10% X7R 0402.

14.Add PC11 S CER CAP .1U 25V K X7R 0603.

1.Change the PL9 from S COIL 10UH +-30% SDT-1050P-100-

118 3.5A to S COIL 10uH +-20% SDT-1205P-100-118.

1.Change the PQ16 S TR TP0610T 1P SOT-23 to.S TR TP0610K

1P SOT-23

0.3

0.3

DVT2

DVT2

DVT20.30.3

3 3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

PIR

Size Document Number Rev

AL50 La-2361

Date: Sheet

E

of

50 50Monday, October 04, 2004

0.2