Compal LA-2351, Aspire 9100 Schematic
5
4
COMPAL CONFIDENTIAL
3
2
1
MODEL NAME :
D D
COMPAL P/N :
EDL70/71
PCB NO :
Revision :
1B
EDL70/71 Schematics Document
C C
uFCBGA/uFCPGA Mobile Dothan
Intel Alviso + ICH6M
2005-02-25
REV : 1B
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
EDL71 LA2351
159Wednesday, March 02, 2005
1
1B
5
Compal confidential
4
3
2
1
Model : EDL71
FAN
+5VS
D D
TV OUT
CRT CONN
LVDS CONN
page 25
page 25
page 24
CRT Signal
Internal LVDS
Frame Buffer
C C
64/128
page 22,23
IDSEL:AD18
(PIRQG#,PIRQH#,GNT#1,REQ#1)
IDSEL:AD19
(PIRQH#,PIRQG#,GNT#4,REQ#4)
Minipci CONN X2
WIRELESS
TV Turner
page 37,38
IDSEL:AD16
(PIRQE#,GNT#0,REQ#0)
VT6301S
1394 Controller
+3VS
page 34
1394
B B
CONN
page 34
page 8
CardBus Controller
+S1_VCC
+3VS
Card
Reader
+VCC_5IN1 +S1_VCC
page 33
Thermal(CPU)
+3VS
+1.5VS
+1.8VS
+VGA_CORE
+3VS
+2.5VS
+1.2VS
G781
ATI M24P
page 18,19,20,21
Thermal(VGA)
+3VS
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2),SIRQ
ENE CB712
G781-1
page 32
page 26
PCMCIA
Slot
+S1_VPP
page 33
page 8
PCI BUS
IDSEL:AD17
(PIRQF#,GNT#3,REQ#3)
RTL8110SBL
/8100CL
+3VALW
RJ45
page 36
PCI-E 16X
+3VALW 33MHz
page 35
X BUS
+VCCP (1.05V)
+CPU_CORE
H_A#(3..31) H_D#(0..63)
+1.5VS
+2.5V
+VCCP
+3VS
+2.5VS
+3VS
+3V
+1.5VS
+1.5V
+2.5VS
Port DEBUG
+5VS
+3VS
+1.5VS/+VCCP
page 53
+1.8VS/
+VGA_CORE
page 54
DC IN
RTC BATT
page 50
page 48
SST39VF040
page 42
Power On/Off
CPU_CORE
page 55
A A
CHARGER
page 49
5
2.5V/+1.2VS/
+1.25VS
page 52
3V/5V/12V
page 51
SW & LED
page 43
DC/DC Interface
page 47
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Pentium-M
Dothan
uFCPGA CPU
478pin
System Bus
+VCCP 400/533 MHz
INTEL
Alviso
1257BGA
DMI
+1.5VS
100MHz
INTEL
ICH6-M
609 BGA
page 43
KB910
+5VS
+3VALW
Touch Pad &
LID SW
+5VS
3
page 5,6,7
page 9,10,11,12,13
page 27,28,29,30
LPC BUS
+3VALW
33MHz
page 41
Int.KBD
page 43
page 43
Memory BUS
(DDRI)
48MHz
24.576MHz
ATA100
2
2.5V 333 MHz
USB[0,2,4,6]
AC-LINK
Parallel ATA
+5VS
page 31
IDE
CD-ROM
+5VCD
page 31
AMP & INT.
Speaker
+5VAMP +5VAMP
Title
Size Document Number Rev
Date: Sheet of
Clock Generator
ICS954226
+3VS
DDRI-DIMM X2
BANK 0, 1, 2, 3
+1.25VS
+2.5V
page 14,15
USB Ports X4
+5VALW
AC97 Codec
ALC250
+5VAMP
+3VS
page 44
HeadPhone &
MIC CONN
page 45
Compal Electronics, Inc.
Cover Sheet
EDL71 LA-2351
1
page 45
259Wednesday, March 02, 2005
+5VS
+3VS
+3V
page 17
page 40
MDC
page 39
Cable
RJ11
page 36
1B
5
D D
4
3
2
1
AC
Adapter
in
C C
BATT+
51_ON#
VMB
P48
ADPPWR
VIN
SWITCH
MB3887
Charger
TPO610T
SWITCH
VS
P49
P50
P50
CHGRTC
G920
RTC BATT
Charger
B B
P50
CHG/DIS
BATT+
VS
LM393
BATT OVP
P49
BATT_OVP
MAINPWON
B+ B+
VS
RUN
MAX1902
DC/DC
(3V/5V/12V)
SHDN#
Battery A
8 Cell
LM358
Thermal
Protector
P50
P52
2.5VREF
VS_ON1/VS_ON2
VL
+5VALWP
+3VALWP
+12VALWP
B+
MAX8743
DC/DC
(1.5V/VCCP)
ON1/ON2
FAN5234
DC/DC
(2.5V)
P53
Vcc
+1.5VP 5A
P54
+2.5V 7.106A
SUSP
2.5VP
3VALW
+VCCP 6.420A
+1.25V 1A
ALP5331
DC/DC
(1.25V)
P53
EN
+5VS
VCC SHDN#
MAX1532
DC/DC
(CPU_CORE)
P55
SUSP
B+
Battery
Connector
A
SWITCH
P48
BATT
P48
VR_ON
CPU_CORE
(+1.308V 25A)
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Power Rail
EDL71 LA-2351
359Wednesday, March 02, 2005
1
1B
5
4
3
2
1
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+PCIE_1.2VS +PCIE_1.2VS power rail for VGA PCIExpress
+1.5VS
+1.8VS
+3VALW
+3V
+5VALW
+5VS
+12VALW
+RTCVCC
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9VS for DDR2 Termination+0.9VS
1.8V switched power rail
2.5VS switched power rail+2.5VS
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
12V always on power rail
RTC power
S0-S1 S3 S5
N/A N/A N/A
ON OFF
ONVGA Core Power+VGA_CORE
OFF
ON
OFF
ON
ON
ON
ON
OFF
ON+3VS
ON
ON
OFF
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFFOFFON
OFFOFFON
OFFOFF
OFFOFFONMCH & ICH Core Power
OFF
OFF
ON*ON
OFF
OFF
ON*ON
OFF
ON*
Board ID
0
1
2
3
4
5
6
7 NC
Board ID
*
100K +/- 5%Ra
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0
1
2
3
4
5
6
7
Rb V min
0
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
PCB Revision
0.1
0.2
0.3
0.4
0.5
0.6
1.0
1.B
Vtyp
AD_BID
V
AD_BID
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
max
SKU ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
VGA
B B
1394 PIRQE
LAN
CardBus
Mini-PCI
Mini-PCI II for TV Turnner
AD16
AD17
AD20
AD18
AD19
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
G781-1
Address
0001 011X b
1010 000X b
1001 101X b
0
3PIRQF
2
1
4
EC SM Bus2 address
ICH6 SM Bus address
Device
Clock Generator
A A
( ICS954206)
DDRII DIMM0
DDRII DIMM1
Address
1101 001Xb
1010 000Xb
1010 001Xb
Device
G781
PIRQA
PIRQA,B
PIRQG/PIRQH
PIRQH/PIRQG
Address
1001 100X b
NOTE1:
SWDJ@ : SWDJ
NOSWDJ@ : W/O SWDJ
@XX : Depop component
1@XX : Pop for Integrated Graphic
2@XX : Pop for External Graphic
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Vcc 3.3V +/- 5%
100K +/- 5%Ra
Board ID
0
1
2
3
4
5
6
Rb V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
7 NC
SKU ID
0
*
1
2
3
4
5
6
7
EDL71 10/100 LAN WO/TV TUNER
EDL71 GIGA LAN W/TV TURNER
EDL71 10/100LAN W/TV TUNER
EDL71 GIGA WO/TV TUNER
EDL71 10/100 LAN WO/TV TUNER
EDL71 10/100LAN W/TV TUNER
EDL71 GIGA WO/TV TUNER
EDL71 GIGA LAN W/TV TURNER
AD_BID
0 V
Vtyp
AD_BID
0 V 0 V
V
AD_BID
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
EDL71 SKU
TV@ : TV Tunner
100@ : 10/100M LAN
GIGA@ : 10/100M/1000M LAN
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Notes List
EDL71 LA-2351
max
1
1B
459Wednesday, March 02, 2005
5
H_A#[3..31]9
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
D D
H_REQ#[0..4]9
H_ADSTB#09
H_RS#[0..2]9
H_THERMTRIP#
H_CPUPWRGD
5
H_ADSTB#19
R801 0_0402_5%@
R802 0_0402_5%@
CLK_CPU_BCLK17
CLK_CPU_BCLK#17
H_ADS#9
H_BNR#9
H_BPRI#9
H_BR0#9
H_DEFER#9
H_DRDY#9
H_HIT#9
H_HITM#9
H_LOCK#9
H_RESET#9
H_TRDY#9
H_DBSY#9
H_DPSLP#28
H_DPRSLP#28
H_DPWR#9
H_CPUSLP#9,28
H_THERMDA8
H_THERMDC8
H_THERMTRIP#8,9,28
C C
B B
A A
CLK_CPU_ITP17
CLK_CPU_ITP#17
R72
56_0402_5%
+VCCP
H_CPUPWRGD28
+VCCP
+VCCP
1 2
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
R88 75_0402_5%
1 2
R74
200_0402_5%
1 2
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CPU_ITTP
12
CPU_ITTP#
12
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSLP#
H_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDC
75ohm pull-up of H_THERMTRIP#
should be within 2" from the
series resistor
Add pullups for PWRGOOD and THERMTRIP per INTEL
JP1A
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
R2
P3
T2
P1
T1
U3
AE5
A16
A15
B15
B14
N2
L1
J3
N4
L4
H2
K3
K4
A4
J2
B11
H1
K1
L2
M3
C8
B8
A9
C9
A7
M2
B7
G1
C19
A10
B10
B17
E4
A6
A13
C12
A12
C5
F23
C11
B13
B18
A18
C17
TYCO_1612365-1_Dothan
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
ADDR GROUP
A25#
A26#
A27#
A28#
A29#
A30#
A31#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
ITP_CLK0
ITP_CLK1
BCLK0
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMDA
THERMDC
THERMTRIP#
4
Dothan
DATA GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
4
LEGACY CPU
3
H_D#[0..63] 9
A19
D0#
A25
D1#
A22
D2#
B21
D3#
A24
D4#
B26
D5#
A21
D6#
B20
D7#
C20
D8#
B24
D9#
D24
D10#
E24
D11#
C26
D12#
B23
D13#
E23
D14#
C25
D15#
H23
D16#
G25
D17#
L23
D18#
M26
D19#
H24
D20#
F25
D21#
G24
D22#
J23
D23#
M23
D24#
J25
D25#
L26
D26#
N24
D27#
M25
D28#
H26
D29#
N25
D30#
K25
D31#
Y26
D32#
AA24
D33#
T25
D34#
U23
D35#
V23
D36#
R24
D37#
R26
D38#
R23
D39#
AA23
D40#
U26
D41#
V24
D42#
U25
D43#
V26
D44#
Y23
D45#
AA26
D46#
Y25
D47#
AB25
D48#
AC23
D49#
AB24
D50#
AC20
D51#
AC22
D52#
AC25
D53#
AD23
D54#
AE22
D55#
AF23
D56#
AD24
D57#
AF20
D58#
AE21
D59#
AD21
D60#
AF25
D61#
AF22
D62#
AF26
D63#
D25
DINV0#
J26
DINV1#
T24
DINV2#
AD20
DINV3#
C23
DSTBN0#
K24
DSTBN1#
W25
DSTBN2#
AE24
DSTBN3#
C22
DSTBP0#
L24
DSTBP1#
W24
DSTBP2#
AE25
DSTBP3#
C2
A20M#
D3
FERR#
A3
IGNNE#
B5
INIT#
D1
LINT0
D4
LINT1
C6
STPCLK#
B4
SMI#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#H_THERMDA
H_SMI#
3
H_DINV#0 9
H_DINV#1 9
H_DINV#2 9
H_DINV#3 9
H_A20M# 28
H_FERR# 28
H_IGNNE# 28
H_INIT# 28
H_INTR 28
H_NMI 28
H_STPCLK# 28
H_SMI# 28
H_DSTBN#[0..3] 9
H_DSTBP#[0..3] 9
2
R147
56_0402_5%
2
1
+3V
R63
150_0603_1%
1 2
+VCCP
R64
54.9_0603_1%@
1 2
R65
54.9_0603_1%@
1 2
+VCCP
R66
39.2_0603_1%
1 2
R68
150_0603_1%
1 2
R70
680_0402_5%
1 2
R71
27.4_0603_1%
1 2
+3VS
+VCCP
12
R730
56_0402_5%
12
H_PROCHOT#
TEST2
TEST1
R149
1 2
1K_0402_5%@
R148
1 2
1K_0402_5%@
Title
Size Document Number Rev
Date: Sheet of
12
R731
1K_0402_5%
1
C
Q67
2
B
2SC2411K_SC59
E
3
Compal Electronics, Inc.
Dothan Processor in mFCPGA479
EDL71 LA-2351
ITP_DBRESET#
This shall place near CPU
1
ITP_TDO
H_RESET#
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
PROCHOT# 41
1B
559Wednesday, March 02, 2005
5
D D
C C
B B
+VCCP
R_A
12
V_CPU_GTLREF
R79
1K_0603_1%
R_B
12
R84
2K_0603_1%
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
27.4_0603_1%
R80
4
+VCCA_PROC
R78
0_0603_5%
1 2
+1.5VS
12
54.9_0603_1%
R81
1
1
C18
C19
2
2
10U_0805_10V4Z
0.01U_0402_16V7K
PSI#55
CPU_VID055
CPU_VID155
CPU_VID255
CPU_VID355
CPU_VID455
CPU_VID555
CPU_BSEL017
14.5 mil
4 mil
14.5 mil
4 mil
12
54.9_0603_1%
R83
12
12
27.4_0603_1%
R82
CPU_BSEL117
3
R75
54.9_0603_1%@
1 2
1 2
R76
54.9_0603_1%@
+VCCP
+CPU_CORE
V_CPU_GTLREF
VCCSENSE
VSSSENSE
H_PSI#
VID0
VID1
VID2
VID3
VID4
VID5
CPU_BSEL0
CPU_BSEL1
COMP0
COMP1
COMP2
COMP3
JP1B
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
TYCO_1612365-1_Dothan
2
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
Dothan
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
POWER, GROUNG, RESERVED SIGNALS AND NC
+CPU_CORE
JP1C
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
AA11
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AB6
VCC
AB8
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AC9
VCC
AC11
VCC
AC13
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AD8
VCC
AD10
VCC
AD12
VCC
AD14
VCC
AD16
VCC
AD18
VCC
AE9
VCC
AE11
VCC
AE13
VCC
AE15
VCC
AE17
VCC
AE19
VCC
AF8
VCC
AF10
VCC
AF12
VCC
AF14
VCC
AF16
VCC
AF18
VCC
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS
TYCO_1612365-1_Dothan
Dothan
POWER, GROUND
1
T26
VSS
U2
VSS
U6
VSS
U22
VSS
U24
VSS
V1
VSS
V4
VSS
V5
VSS
V21
VSS
V25
VSS
W3
VSS
W6
VSS
W22
VSS
W23
VSS
W26
VSS
Y2
VSS
Y5
VSS
Y21
VSS
Y24
VSS
AA1
VSS
AA4
VSS
AA6
VSS
AA8
VSS
AA10
VSS
AA12
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA20
VSS
AA22
VSS
AA25
VSS
AB3
VSS
AB5
VSS
AB7
VSS
AB9
VSS
AB11
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB26
VSS
AC2
VSS
AC5
VSS
AC8
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC21
VSS
AC24
VSS
AD1
VSS
AD4
VSS
AD7
VSS
AD9
VSS
AD11
VSS
AD13
VSS
AD15
VSS
AD17
VSS
AD19
VSS
AD22
VSS
AD25
VSS
AE3
VSS
AE6
VSS
AE8
VSS
AE10
VSS
AE12
VSS
AE14
VSS
AE16
VSS
AE18
VSS
AE20
VSS
AE23
VSS
AE26
VSS
AF2
VSS
AF5
VSS
AF9
VSS
AF11
VSS
AF13
VSS
AF15
VSS
AF17
VSS
AF19
VSS
AF21
VSS
AF24
VSS
A A
Layout close CPU
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Dothan Processor in mFCPGA479
EDL71 LA-2351
659Wednesday, March 02, 2005
1
of
1B
5
4
3
2
1
+CPU_CORE
1
C20
10U_1206_6.3V6M
2
D D
C C
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
C30
10U_1206_6.3V6M
C40
10U_1206_6.3V6M
C50
10U_1206_6.3V6M
1
C21
10U_1206_6.3V6M
2
1
C31
10U_1206_6.3V6M
2
1
C41
10U_1206_6.3V6M
2
1
C51
10U_1206_6.3V6M
2
1
C22
10U_1206_6.3V6M
2
1
C32
10U_1206_6.3V6M
2
1
C42
10U_1206_6.3V6M
2
1
C52
10U_1206_6.3V6M
2
1
C23
10U_1206_6.3V6M
2
1
C33
10U_1206_6.3V6M
2
1
C43
10U_1206_6.3V6M
2
1
C53
10U_1206_6.3V6M
2
1
C24
10U_1206_6.3V6M
2
1
C34
10U_1206_6.3V6M
2
1
C44
10U_1206_6.3V6M
2
1
C54
10U_1206_6.3V6M
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
C25
10U_1206_6.3V6M
C35
10U_1206_6.3V6M
C45
10U_1206_6.3V6M
1
2
1
2
1
2
10uF 1206 X5R -> 85 degree
C26
10U_1206_6.3V6M
C36
10U_1206_6.3V6M
C46
10U_1206_6.3V6M
High Frequence Decoupling
1
C27
10U_1206_6.3V6M
2
1
C37
10U_1206_6.3V6M
2
1
C47
10U_1206_6.3V6M
2
1
C28
10U_1206_6.3V6M
2
1
C38
10U_1206_6.3V6M
2
1
C48
10U_1206_6.3V6M
2
1
C29
10U_1206_6.3V6M
2
1
C39
10U_1206_6.3V6M
2
1
C49
10U_1206_6.3V6M
2
Near VCORE regulator.
+CPU_CORE
+
+
C59
150U_C_4VM
C56
330U_D2E_2.5VM_R9
9mOhm
7343
PS CAP
1
2
5
1
@
C55
2
B B
A A
330U_D2E_2.5VM_R9
9mOhm
7343
PS CAP
+VCCP
1
2
1
+
C57
2
330U_D2E_2.5VM_R9
9mOhm
7343
PS CAP
1
2
+
C58
330U_D2E_2.5VM_R9
9mOhm
7343
PS CAP
C60
0.1U_0402_16V4Z
1
+
2
1
2
ESR <= 3m ohm
Capacitor > 880uF
C61
0.1U_0402_16V4Z
1
C62
0.1U_0402_16V4Z
2
1
C63
0.1U_0402_16V4Z
2
4
1
C64
0.1U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C65
0.1U_0402_16V4Z
2
3
1
C66
0.1U_0402_16V4Z
2
1
C67
0.1U_0402_16V4Z
2
1
C68
0.1U_0402_16V4Z
2
2
1
C69
0.1U_0402_16V4Z
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
CPU Bypass
EDL71 LA-2351
759Wednesday, March 02, 2005
1
1B
5
4
3
2
1
Fan Control circuit
+12VALW
1
D D
C140
1U_0603_10V4Z
EN_FAN1
1
2
EN_FAN141
C C
0.1U_0402_16V4Z
12
R150
150K_0402_5%
C73
2
8
U3A
P
3
+IN
2
-IN
4
C143
2200P_0402_50V7K
1 2
R162
100K_0402_5%
1 2
OUT
G
LM358A_SO8
FAN1
1
D23
RB751V_SOD323
+5VS
6
2
1
D
+
22U_A_4VM
Q31
S
SI3456DV-T1_TSOP6
4 5
1
C72
2
2
C17
1
0.001U_0402_50V7M
FANVOUT1
JP2
ACES_85205-0300
G
3
2 1
+3VS
12
R163
10K_0402_5%
1
C145
0.01U_0402_16V7K
2
1
2
3
FANSPEED1 41
Thermal Sensor G781
+3VS
2
C147
1
12
R146
10K_0402_5%@
Title
Size Document Number Rev
Date: Sheet
0.1U_0402_16V4Z
Compal Electronics, Inc.
FAN & Thermal Sensor
EDL71 LA-2351
1
859Wednesday, March 02, 2005
of
1B
EC_SMC_241
EC_SMD_241
+3VALW
H_THERMDA
H_THERMDC
1
C148
2
8.2K_0402_5%
R513
R145 300_0402_5%
+VCCP
B B
+2.5V
12
R1018
10K_0402_1%
A A
10K_0402_1%
5
R1019
12
1 2
H_THERMTRIP#
+12VALW
5
+IN
6
-IN
@
U3B
OUT
LM358A_SO8
7
C146 1U_0603_10V4Z
2
Q8
CBE
2SC2411K_SC59
1
3
@
1 2
@
4
MAINPWON 48,50,51H_THERMTRIP#5,9,28
+V_DDR_MCH_REF
2200P_0402_25V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_THERMDA 5
H_THERMDC 5
H_THERMDA
H_THERMDC
12
12
U4
2
D+
3
D-
8
SCLK
7
SDATA
G781_SOP8
R512
8.2K_0402_5%
VDD1
ALERT#
THERM#
GND
W=15mil
1
6
4
5
2
5
H_A#[3..31]5 H_D#[0..63] 5
D D
H_REQ#[0..4]5
C C
H_DSTBN#[0..3]5
H_DSTBP#[0..3]5
Layout Guide
will show these
signals routed
differentially.
B B
H_RS#[0..2]5
T5 PAD
H_ADSTB#05
H_ADSTB#15
CLK_MCH_BCLK#17
CLK_MCH_BCLK17
H_DINV#05
H_DINV#15
H_DINV#25
H_DINV#35
H_RESET#5
H_ADS#5
H_TRDY#5
H_DPWR#5
H_DRDY#5
H_DEFER#5
T6 PAD
H_HITM#5
H_HIT#5
H_LOCK#5
H_BR0#5
H_BNR#5
H_BPRI#5
H_DBSY#5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_RESET#
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_R_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
G10
G11
G13
G12
AB1
AB2
A10
B10
E10
E11
F10
C10
C11
D11
C12
B13
A12
F12
E12
C13
B11
D13
A13
F13
A11
E13
H10
G9
C9
E9
B7
F9
D8
D9
A7
D7
B8
C7
A8
B9
G4
K1
R3
V3
G5
K2
R2
W4
H8
K3
T7
U5
F8
B5
G6
F7
E6
F6
D6
D4
B3
E7
A5
D5
C6
G8
A4
C5
B4
HA3#
Alviso
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#
HOST
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
ALVISO_BGA1257
U2A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
HXSWING
HYSWING
4
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
J11
C1
C2
T1
L1
D1
P1
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
R97
24.9_0603_1%
12
H_SWNG1
H_SWNG0
R98
24.9_0603_1%
C70
C71
0.1U_0402_16V4Z
+VCCP
12
R91
54.9_0603_1%
12
R85
1
R86
2
0.1U_0402_16V4Z
R87
1
R89
2
12
R92
54.9_0603_1%
+VCCP
12
221_0603_1%
12
100_0603_1%
+VCCP
12
221_0603_1%
12
100_0603_1%
1
C74
2
0.1U_0402_16V4Z
3
+VCCP
R94
100_0603_1%
R96
200_0603_1%
2
U2B
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DDR_CLK0
DDR_CLK1
DDR_CLK3
DDR_CLK4
DDR_CLK0#
DDR_CLK1#
DDR_CLK3#
DDR_CLK4#
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
M_OCDOCMP0
M_OCDOCMP1
1
C900
2
0.1U_0402_16V4Z
SMRCOMPN
SMRCOMPP
C901
DMI_TXN029
DMI_TXN129
DMI_TXN229
DMI_TXN329
DMI_TXP029
DMI_TXP129
DMI_TXP229
DMI_TXP329
DMI_RXN029
DMI_RXN129
DMI_RXN229
DMI_RXN329
DMI_RXP029
DMI_RXP129
DMI_RXP229
DMI_RXP329
DDR_CLK014
DDR_CLK114
DDR_CLK315
DDR_CLK415
DDR_CLK0#14
DDR_CLK1#14
DDR_CLK3#15
DDR_CLK4#15
DDR_CKE014
DDR_CKE114
DDR_CKE215
DDR_CKE315
DDR_SCS#014
DDR_SCS#114
DDR_SCS#215
DDR_SCS#315
+2.5V
R760
12
R761
80.6_0603_1%
Layout Note:
Route as short
as possible
1 2
80.6_0603_1%
+V_DDR_MCH_REF
12
12
1
2
0.1U_0402_16V4Z
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
ALVISO_BGA1257
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
DMIDDR MUXING
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
CFG/RSVD
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
CLK
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC
NC11
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
D37
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
MCH_CLKSEL1
MCH_CLKSEL0
PM_EXTTS#0
PM_EXTTS#1
VGATE
PLTRST_R#
1
Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown
CFG0
CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
1 2
R90 100_0402_5%
CFG0 11
MCH_CLKSEL1 17
MCH_CLKSEL0 17
T3PAD
T4PAD
CFG5 11
CFG6 11
CFG7 11
CFG9 11
CFG12 11
CFG13 11
CFG16 11
CFG18 11
CFG19 11
PM_BMBUSY# 29
H_THERMTRIP# 5,8,28
DREFCLK# 17
DREFCLK 17
DREF_SSCLK 17
DREF_SSCLK# 17
1 2
R1054 0_0402_5%
1 2
R1055 0_0402_5%
2@
2@
VGATE 17,29,55
PLTRST# 27,29,35,39,41,46
+1.5VS
M_OCDOCMP0
M_OCDOCMP1
R99
H_CPUSLP#5,28
A A
H_CPUSLP# H_R_CPUSLP#
Note:
"Do not install R99 for Dothan-A,
Install R99 for Dothan-B"
5
0_0402_5%
1 2
Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
12
@
@
R100
R101
40.2_0402_1%
40.2_0402_1%
3
PM_EXTTS#0
PM_EXTTS#1
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Alviso(1 of 5)
R102
10K_0402_5%
R103
10K_0402_5%
EDL71 LA-2351
+2.5VS
12
12
1B
959Wednesday, March 02, 2005
1
5
4
3
2
1
D D
C C
T20 PAD
T22 PAD
B B
DDR_A_BS#014
DDR_A_BS#114
T18 PAD
DDR_A_DM[0..7]15
DDR_A_DQS[0..7]15
DDR_A_MA[0..13]14
DDR_A_CAS#14
DDR_A_RAS#14
DDR_A_WE#14
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
DDR_A_WE#
U2C
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
ALVISO_BGA1257
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
DDR MEMORY SYSTEM A
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D0
AG35
DDR_A_D[0..63] 15
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
T21 PAD
T23 PAD
DDR_B_BS#015
DDR_B_BS#115
T19 PAD
DDR_B_MA[0..13]15
DDR_B_CAS#15
DDR_B_RAS#15
DDR_B_WE#15
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
DDR_B_WE#
U2D
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
ALVISO_BGA1257
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
SBDQ27
AH24
SBDQ28
AH23
SBDQ29
AG22
SBDQ30
AJ21
SBDQ31
AG10
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
AH11
SBDQ36
AH10
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR SYSTEM MEMORY B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(2 of 5)
EDL71 LA-2351
10 59Wednesday, March 02, 2005
1
1B
5
AB29
AC29
12
U2G
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
GCLKN
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCCLK
E23
DDCDATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
E25
LBKLT_CTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
F26
LVDD_EN
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
B30
LACLKN
B29
LACLKP
C25
LBCLKN
C24
LBCLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
MISCTVVGALVDS
EXP_RXN2/SDVO_FLDSTALL#
EXP_RXP2/SDVO_FLDSTALL
PCI - EXPRESS GRAPHICS
SDVO_CTRLDATA
12
12
1@
R110
150_0603_1%
R1113 0_0402_5%1@
12
R93
SDVO_CTRLCLK
12
1@
1@
R111
R112
150_0603_1%
150_0603_1%
R117
255_0603_1%
1 2
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
L_IBG
1.5K_0603_5%
TVIREF
12
12
BIA_PWM
R120
4.99K_0603_1%
CLK_MCH_3GPLL#17
CLK_MCH_3GPLL17
COMP/B25
Y/G25
C/R25
D D
1@
R109
INT_CLK_DDC225
INT_DAT_DDC225
INTCRT_B25
INTCRT_G25
INTCRT_R25
INT_VSYNC25
INT_HSYNC25
BIA_PWM24
BACKLITE_ON18,24,41
C C
100K_0402_5%
GM_ENVDD24
LCD_ACLK-24
LCD_ACLK+24
LCD_BCLK-24
LCD_BCLK+24
LCD_A0-24
LCD_A1-24
LCD_A2-24
LCD_A0+24
LCD_A1+24
LCD_A2+24
LCD_B0-24
LCD_B1-24
B B
LCD_B2-24
LCD_B0+24
LCD_B1+24
LCD_B2+24
4
EXP_COMPI
EXP_ICOMPO
EXP_RXN0/SDVO_TVCLKIN#
EXP_RXN1/SDVO_INT#
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0/SDVO_TVCLKIN
EXP_RXP1/SDVO_INT
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0/SDVOB_RED#
EXP_TXN1/SDVOB_GREEN#
EXP_TXN2/SDVOB_BLUE#
EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#
EXP_TXN5/SDVOC_GREEN#
EXP_TXN6/SDVOC_BLUE#
EXP_TXN7/SDVOC_CLKN
EXP_TXP1/SDVOB_GREEN
EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP
EXP_TXP5/SDVOC_GREEN
EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0/SDVOB_RED
EXP_TXP4/SDVOC_RED
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
PEGCOMP
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
R104
24.9_0603_1%
1 2
EXP_RXN[0..15]
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
EXP_RXP[0..15]
EXP_TXN[0..15]
EXP_TXP[0..15]
+1.5VS_PCIE
EXP_RXN[0..15] 21
EXP_RXP[0..15] 21
EXP_TXN[0..15] 21
EXP_TXP[0..15] 21
3
Strap Table
CFG5
CFG6
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
SDVO_CTRLDATA
Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
(Default)
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
Low = No SDVO Device Present
(Default)
High = SDVO Device Present
2
CFG09
*
*
*
*
CFG59
CFG79
CFG69
CFG99
CFG129
CFG139
CFG169
*
*
CFG189
CFG199
*
R105 10K_0402_5%
R106 2.2K_0402_5%@
R108 2.2K_0402_5%@
R107 2.2K_0402_5%@
R113 2.2K_0402_5%@
R114 2.2K_0402_5%@
R115 2.2K_0402_5% @
R116 2.2K_0402_5%@
CFG[3:17] have internal pullup
R118 1K_0402_5%
R119 1K_0402_5%@
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+VCCP
12
+2.5VS
@
CFG[18:19] have internal pulldown
*
+2.5VS
*
SDVO_CTRLCLK
SDVO_CTRLDATA
R1180 3K_0402_5%@
1 2
R121 3K_0402_5%@
1 2
Have internal pulldown
+2.5VS
1@
1 2
R127 2.2K_0402_5%
1@
1 2
R128 2.2K_0402_5%
A A
1@
1 2
R133 100K_0402_5%
5
LCTLA_CLK
LCTLB_DATA
12
R122150_0603_1% 1@
12
R123150_0603_1% 1@
12
R124150_0603_1% 1@
BIA_PWM
INTCRT_R
INTCRT_G
INTCRT_B
ALVISO_BGA1257
1@
R129
LDDC_CLK
LDDC_DATA
+2.5VS
12
2.2K_0402_5%
4
12
1@
2N7002_SOT23
+2.5VS
2N7002_SOT23
R130
2.2K_0402_5%
+3VS
12
12
R132
2.2K_0402_5%
1@
D
S
Q4
Q6
13
1@
G
2
G
2
13
D
S
1@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R131
2.2K_0402_5%
1@
LCD_DDCCLK
LCD_DDCDATA
LCD_DDCCLK 24
LCD_DDCDATA 24
3
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
Alviso(3 of 5)
EDL71 LA-2351
11 59Wednesday, March 02, 2005
1
1B
5
U2F
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
N11
M11
1
2
2.2U_0805_16V4Z
1
C113
2
0.22U_0402_10V4Z
CHB1608U301_0603
1 2
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
W9
M9
M8
M7
M6
M5
M4
M3
M2
M1
G1
1
C114
2
L14
1@
D D
+VCCP
1
C93
C94
2
4.7U_0805_10V4Z
C C
1
C103
0.47U_0603_16V4Z
2
1
C112
2
0.47U_0603_16V4Z
B B
+1.5VS
A A
+VCCP
1 2
R139
10_0402_5%1@
POWER
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
Y9
VTT23
VTT24
U9
VTT25
R9
VTT26
P9
VTT27
N9
VTT28
VTT29
L9
VTT30
J9
VTT31
N8
VTT32
VTT33
N7
VTT34
VTT35
N6
VTT36
VTT37
A6
VTT38
N5
VTT39
VTT40
N4
VTT41
VTT42
N3
VTT43
VTT44
N2
VTT45
VTT46
B2
VTT47
V1
VTT48
N1
VTT49
VTT50
VTT51
0.22U_0402_10V4Z
ALVISO_BGA1257
+1.5VS_DPLLA
1
1
+
C126
C128
2
0.1U_0402_16V4Z
+2.5VS
12
2
470U_D_2.5VM
Note : C126, C129 No stuff for Ext. VGA.
Stuff for Int. VGA.
D1
LL4148_SOD80
1@
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
Note : All VCCSM pin
shorted internally.
CHB1608U301_0603
+1.5VS
1 2
1 2
R140
10_0402_5%1@
+1.5VS
AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1
L16
V2.5_DDR_CAP1
V2.5_DDR_CAP2
V2.5_DDR_CAP5
V2.5_DDR_CAP6
V2.5_DDR_CAP4
V2.5_DDR_CAP3
C129
1@
470U_D_2.5VM
1
C110
C111
2
10U_0805_10V4Z
+1.5VS_DPLLB
1
+
C134
2
0.1U_0402_16V4Z
D2
12
LL4148_SOD80
1@
1
2
10U_0805_10V4Z
1
2
CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV
5
C75
0.1U_0402_16V4Z
1
C109
2
1
C121
2
+1.5VS
+3VS
4
1
1
C76
2
2
0.1U_0402_16V4Z
1
C86
C87
2
0.1U_0402_16V4Z
1
C95
C96
2
10U_0805_10V4Z
+2.5V
1
+
330U_D_4VM
2
1
C122
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CHB1608U301_0603
1 2
4
C77
0.1U_0402_16V4Z
1
C88
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C97
2
10U_0805_10V4Z
10U_0805_10V4Z
+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL
1
C123
2
0.1U_0402_16V4Z
L17
3
W=30 mils
U2E
+VCCP
1
2
1
2
C130
470U_D_2.5VM
0.1U_0402_16V4Z
1
C152
2
+1.5VS_HPLL
1
+
C135
2
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17
AC1
AC2
B23
C35
AA1
AA2
0.1U_0402_16V4Z
1
C141
2
+1.5VS
1
2
0.1U_0402_16V4Z
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
POWER
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
ALVISO_BGA1257
0.1U_0402_16V4Z
1
1
C150
C149
2
2
CHB1608U301_0603
1 2
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_CRTDAC0
VCCA_CRTDAC1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C151
2
L15
+2.5VS_CRT
VCC_SYNC
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
VSSA_CRTDAC
+2.5V
C153
C127
470U_D_2.5VM
VCCHV0
VCCHV1
VCCHV2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
0.1U_0402_16V4Z
1
2
+1.5VS_MPLL
1
+
C131
2
F17
+3VS_TVDACA
E17
D18
+3VS_TVDACB
C18
F18
+3VS_TVDACC
E18
+3VS_ATVBG
H18
VSSA_TVBG
G18
D19
+1.5VS_TVDAC
H17
+1.5VS_QTVDAC
B26
+1.5VS_DLVDS
B25
A25
A35
B22
B21
A21
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
H20
F19
E19
G19
1
2
0.1U_0402_16V4Z
R137
2@
0_0402_5%
1 2
R138
2@
0_0402_5%
1 2
+2.5VS_ALVDS
+2.5VS
+2.5VS_TXLVDS
C99
0.1U_0402_16V4Z
VCC_SYNC
+2.5VS_CRT
0.022U_0402_16V7K
CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.
+2.5VS_TXLVDS
1
C132
C133
2
4.7U_0805_10V4Z
+VCCP
+VCCP
1
2
1
2
0.1U_0402_16V4Z
Note : R137, R138 st uff for E xt. V GA.
R137, R138 no stuff for Int. VGA.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C82
2
0.022U_0402_16V7K
+1.5VS_DDRDLL
1
+
C98
2
100U_C_4VM
1 2
1@
1
C117
C118
2
R136
0_0402_5%
1
2
Route VSSA_TVBG GND
from GMCH to decoupling
cap ground lead and then
connect to the GND plane.
R5160_0603_5%1@
1 2
0_0603_5%
0.1U_0402_16V4Z
2
L5
1 2
0_0603_5%
1
C83
2
0.1U_0402_16V4Z
+1.5VS_PCIE +1.5VS
1
+
C101
C104
2
220U_D_4VM
10U_0805_10V4Z
L12
C119
22U_1206_6.3V6M
+2.5VS
12
+1.5VS+1.5VS_QTVDAC
1
1
C85
C84
2
0.1U_0402_16V4Z
0.022U_0402_16V7K
1
1
C105
2
2
10U_0805_10V4Z
1
1
C120
2
2
0.1U_0402_16V4Z
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
C136
0.022U_0402_16V7K
2
C78
2
0.022U_0402_16V7K
+3VS_TVDACB +3VS
C89
0.022U_0402_16V7K
+1.5VS_3GPLL
1
C106
2
0.1U_0402_16V4Z
+2.5VS
+1.5VS_TVDAC +1.5VS
1
1
C137
2
2
0.1U_0402_16V4Z
1 2
1
2
1
2
C107
1 2
0_0603_5%
0_0603_5%
1
C79
2
0.1U_0402_16V4Z
1 2
0_0603_5%
1
C90
2
0.1U_0402_16V4Z
R135
0.5_0805_1%
1 2
1
2
10U_0805_10V4Z
Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.
L18
Title
Size Document Number Rev
Date: Sheet of
+3VS+3VS_TVDACA
L3
L6
CHB1608U301_0603
CHB1608U301_0805
1 2
CHB1608U301_0603
3GRLL_R
CHB1608U301_0603
1 2
1
C115
0.1U_0402_16V4Z
2
VSSA_TVBG
L8
1 2
L9
L10
1 2
L11
+2.5VS_ALVDS
1
C80
2
0.022U_0402_16V7K
1
C91
2
0.022U_0402_16V7K
+1.5VS
1
C108
2
0.1U_0402_16V4Z
+2.5VS+2.5VS_3GBG
1
C124
C125
2
0.1U_0402_16V4Z
0.01U_0402_16V7K
+1.5VS_DLVDS +1.5VS
1
C138
C139
2
10U_0805_10V4Z
Compal Electronics, Inc.
Alviso(4 of 5)
EDL71 LA-2351
1
1
C81
2
0.1U_0402_16V4Z
1
C92
2
22U_1206_6.3V6M
C102
0.1U_0402_16V4Z
1
C116
0.1U_0402_16V4Z
2
1 2
0_0603_5%
1
2
1 2
0_0603_5%
1
2
0.01U_0402_16V7K
1
L4
1 2
0_0603_5%
L7
1 2
0_0603_5%
C100
1
2
L13
L19
12 59Wednesday, March 02, 2005
+3VS+3VS_TVDACC
+3VS+3VS_ATVBG
+1.5VS
1
2
0.1U_0402_16V4Z
+2.5VS
1B
5
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+2.5V
+VCCP
+VCCP
D D
C C
B B
A A
U2H
L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13
Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26
ALVISO_BGA1257
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
5
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
NCTF
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
4
U2I
Y1
VSS271
D2
VSS270
G2
VSS269
J2
VSS268
L2
VSS260
P2
VSS259
T2
VSS258
V2
VSS257
AD2
VSS256
AE2
VSS255
AH2
VSS254
AL2
VSS253
AN2
VSS252
A3
VSS251
C3
VSS250
AA3
VSS249
AB3
VSS248
AC3
VSS247
AJ3
VSS246
C4
VSS245
H4
VSS244
L4
VSS243
P4
VSS242
U4
VSS241
Y4
VSS240
AF4
VSS239
AN4
VSS238
E5
VSS237
W5
VSS236
AL5
VSS235
AP5
VSS234
B6
VSS233
J6
VSS232
L6
VSS231
P6
VSS230
T6
VSS229
AA6
VSS228
AC6
VSS227
AE6
VSS226
AJ6
VSS225
G7
VSS224
V7
VSS223
AA7
VSS222
AG7
VSS221
AK7
VSS220
AN7
VSS219
C8
VSS218
E8
VSS217
L8
VSS216
P8
VSS215
Y8
VSS214
AL8
VSS213
A9
VSS212
H9
VSS211
K9
VSS210
T9
VSS209
V9
VSS208
AA9
VSS207
AC9
VSS206
AE9
VSS205
AH9
VSS204
AN9
VSS203
D10
VSS202
L10
VSS201
Y10
VSS200
AA10
VSS199
F11
VSS198
H11
VSS197
Y11
VSS196
ALVISO_BGA1257
4
VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VSSALVDS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
3
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
2
U2J
AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
ALVISO_BGA1257
2
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
1
AC32
VSS67
AD32
VSS66
AJ32
VSS65
AN32
VSS64
D33
VSS63
E33
VSS62
F33
VSS61
G33
VSS60
H33
VSS59
J33
VSS58
K33
VSS
Title
Size Document Number Rev
Date: Sheet of
VSS57
L33
VSS56
M33
VSS55
N33
VSS54
P33
VSS53
R33
VSS52
T33
VSS51
U33
VSS50
V33
VSS49
W33
VSS48
AD33
VSS47
AF33
VSS46
AL33
VSS45
C34
VSS44
AA34
VSS43
AB34
VSS42
AC34
VSS41
AD34
VSS40
AH34
VSS39
AN34
VSS38
B35
VSS37
D35
VSS36
E35
VSS35
F35
VSS34
G35
VSS33
H35
VSS32
J35
VSS31
K35
VSS30
L35
VSS29
M35
VSS28
N35
VSS27
P35
VSS26
R35
VSS25
T35
VSS24
U35
VSS23
V35
VSS22
W35
VSS21
Y35
VSS20
AE35
VSS19
C36
VSS18
AA36
VSS17
AB36
VSS16
AC36
VSS15
AD36
VSS14
AE36
VSS13
AF36
VSS12
AJ36
VSS11
AL36
VSS10
AN36
VSS9
E37
VSS8
H37
VSS7
K37
VSS6
M37
VSS5
P37
VSS4
T37
VSS3
V37
VSS2
Y37
VSS1
AG37
VSS0
Compal Electronics, Inc.
Alviso(5 of 5)
EDL71 LA-2351
13 59Wednesday, March 02, 2005
1
1B
5
+2.5V
JDIM1
1
VREF
3
DDR_D0
DDR_D4
DDR_DQS0
DDR_D6
D D
DDR_CLK09
DDR_CLK0#9
C C
DDR_CKE19
DDR_A_BS#010
DDR_A_WE#10
DDR_SCS#09
B B
A A
CLK_SDATA15,17
CLK_SCLK15,17
DDR_D2
DDR_D8
DDR_D12
DDR_DQS1
DDR_D14
DDR_D10
DDR_D16
DDR_D20
DDR_DQS2
DDR_D18
DDR_D22
DDR_D24
DDR_D28
DDR_DQS3
DDR_D26
DDR_D30
DDR_CKE1 DDR_CKE0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA7
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_SCS#0 DDR_SCS#1
DDR_A_MA13
DDR_D36
DDR_D33
DDR_DQS4
DDR_D35
DDR_D39
DDR_D41
DDR_D45
DDR_DQS5
DDR_D46
DDR_D42
DDR_D52
DDR_D53
DDR_DQS6
DDR_D54
DDR_D50
DDR_D60
DDR_D58
DDR_DQS7
DDR_D57
DDR_D59
CK_SDATA
CK_SCLK
+3VS
5
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5763-3-111
DU/RESET#
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
VSS
VDD
BA1
RAS#
CAS#
S1#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
4
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
4
DDR_D1
DDR_D5
DDR_DM0
DDR_D7
DDR_D3
DDR_D13
DDR_D9
DDR_DM1
DDR_D15
DDR_D11
DDR_D17
DDR_D21
DDR_DM2
DDR_D19
DDR_D23
DDR_D25
DDR_D29
DDR_DM3
DDR_D27
DDR_D31
DDR_A_MA11
DDR_A_MA8
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_A_CAS#
DDR_D37
DDR_D32
DDR_DM4
DDR_D38
DDR_D34
DDR_D44
DDR_D40
DDR_DM5
DDR_D43
DDR_D47
DDR_D49
DDR_D48
DDR_DM6
DDR_D55
DDR_D51
DDR_D61
DDR_D56
DDR_DM7
DDR_D63
DDR_D62
+SDREF_DIMM
R1062
1
2
DDR_CKE0 9
DDR_A_BS#1 10
DDR_A_RAS# 10
DDR_A_CAS# 10
DDR_SCS#1 9
DDR_CLK1# 9
DDR_CLK1 9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
0_0402_5%
C976
0.1U_0402_16V4Z
3
+V_DDR_MCH_REF
DDR_D5
DDR_D1
DDR_D4
DDR_D0
DDR_D7
DDR_DM0
DDR_D6
DDR_DQS0
DDR_D13
DDR_D3
DDR_D8
DDR_D2
DDR_DM1
DDR_D9
DDR_DQS1
DDR_D12
DDR_D11
DDR_D15
DDR_D10
DDR_D14
DDR_D21
DDR_D17
DDR_D20
DDR_D16
DDR_D19
DDR_DM2
DDR_D18
DDR_DQS2
DDR_D25
DDR_D24
DDR_D23
DDR_D22
DDR_DQS3
DDR_DM3
DDR_D28
DDR_D29
DDR_D31
DDR_D27
DDR_D30
DDR_D26
3
DDR_D[0..63]15
DDR_DM[0..7]15
DDR_DQS[0..7]15
DDR_A_MA[0..13]10
RP58 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP61 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP64 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP67 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP70 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP73 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP75 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP77 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP79 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP81 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
+1.25VS
RP59 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP62 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP65 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP78 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP80 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP82 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS[0..7]
DDR_A_MA[0..13]
DDR_DM5
DDR_D40
DDR_DQS5
DDR_D45
DDR_D47
DDR_D43
DDR_D42
DDR_D46
DDR_D48
DDR_D49
DDR_D53
DDR_D52
RP6856_0804_8P4R_5%
DDR_D55
18
DDR_DM6
27
DDR_D54
36
DDR_DQS6
45
RP7156_0804_8P4R_5%
DDR_D61
18
DDR_D51
27
DDR_D60
36
DDR_D50
45
RP7456_0804_8P4R_5%
DDR_DM7
18
DDR_D56
27
DDR_DQS7
36
DDR_D58
45
RP7656_0804_8P4R_5%
DDR_D62
18
DDR_D63
27
DDR_D59
36
DDR_D57
45
DDR_D44
DDR_D34
DDR_D41
DDR_D39
DDR_D38
DDR_DM4
DDR_D35
DDR_D32
DDR_D37
DDR_D33
DDR_D36
2
DDR_DQS4
2
1
+1.25VS
RP5756_0804_8P4R_5%
DDR_CKE0
18
DDR_A_MA11
27
DDR_A_MA8
36
45
RP6056_0804_8P4R_5%
DDR_CKE1
18
DDR_A_MA12
27
DDR_A_MA13
36
DDR_A_MA9
45
RP6356_0804_8P4R_5%
DDR_A_MA7
18
DDR_A_MA5
27
DDR_A_MA3
36
DDR_A_MA1
45
RP6656_0804_8P4R_5%
DDR_A_MA10
18
DDR_A_BS#0
27
DDR_A_WE#
36
DDR_SCS#0
45
RP6956_0804_8P4R_5%
DDR_A_MA6
18
DDR_A_MA4
27
DDR_A_MA2
36
DDR_A_MA0
45
RP7256_0804_8P4R_5%
DDR_A_BS#1
18
DDR_A_RAS#
27
DDR_A_CAS#
36
DDR_SCS#1
45
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRI-SODIMM SLOT1
EDL71 LA-2351
14 59Wednesday, March 02, 2005
1
of
1B
5
D D
DDR_CLK39
DDR_CLK3#9
C C
DDR_CKE39
DDR_B_BS#010
DDR_B_WE#10
DDR_SCS#29
B B
A A
CLK_SDATA14,17
CLK_SCLK14,17
5
+2.5V
JDIM2
1
VREF
3
DDR_D0
DDR_D4
DDR_DQS0
DDR_D6
DDR_D2
DDR_D8
DDR_D12
DDR_DQS1
DDR_D14
DDR_D10
DDR_D16
DDR_D20
DDR_DQS2
DDR_D18
DDR_D22
DDR_D24
DDR_D28
DDR_DQS3
DDR_D26
DDR_D30
DDR_CKE3 DDR_CKE2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA7
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_SCS#2 DDR_SCS#3
DDR_B_MA13
DDR_D36
DDR_D33
DDR_DQS4
DDR_D35
DDR_D39
DDR_D41
DDR_D45
DDR_DQS5
DDR_D46
DDR_D42
DDR_D52
DDR_D53
DDR_DQS6
DDR_D54
DDR_D50
DDR_D60
DDR_D58
DDR_DQS7
DDR_D57
DDR_D59
CK_SDATA
CK_SCLK
+3VS
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5763-2-111
DU/RESET#
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
VSS
VDD
BA1
RAS#
CAS#
S1#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
4
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
4
DDR_D1
DDR_D5
DDR_DM0
DDR_D7
DDR_D3
DDR_D13
DDR_D9
DDR_DM1
DDR_D15
DDR_D11
DDR_D17
DDR_D21
DDR_DM2
DDR_D19
DDR_D23
DDR_D25
DDR_D29
DDR_DM3
DDR_D27
DDR_D31
DDR_B_MA11
DDR_B_MA8
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_B_CAS#
DDR_D37
DDR_D32
DDR_DM4
DDR_D38
DDR_D34
DDR_D44
DDR_D40
DDR_DM5
DDR_D43
DDR_D47
DDR_D49
DDR_D48
DDR_DM6
DDR_D55
DDR_D51
DDR_D61
DDR_D56
DDR_DM7
DDR_D63
DDR_D62
+3VS
+SDREF_DIMM
R1098
1
2
DDR_CKE2 9
DDR_B_BS#1 10
DDR_B_RAS# 10
DDR_B_CAS# 10
DDR_SCS#3 9
DDR_CLK4# 9
DDR_CLK4 9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
0_0402_5%
C1086
0.1U_0402_16V4Z
3
DDR_A_D[0..63]10
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_B_MA[0..13]10
DDR_D4
DDR_D1
DDR_D5
DDR_DM0
DDR_DQS0DDR_A_DQS0
DDR_D6
DDR_D7
DDR_D2
DDR_D3
DDR_D8
DDR_D13
DDR_D14
DDR_D15
DDR_D10
DDR_D11
DDR_D12
DDR_DM1
DDR_D9
DDR_DQS1
DDR_D16
DDR_D17
DDR_D20
DDR_D21
DDR_DM2
DDR_D18
DDR_D19
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D29
DDR_D28
DDR_DM3
DDR_DQS3
DDR_D26
DDR_D30
DDR_D31
DDR_D27
DDR_D36
DDR_D33
DDR_D32
DDR_D37
DDR_DM4
DDR_DQS4
DDR_D38
DDR_D39
DDR_D34
DDR_D35
DDR_D41
DDR_D44
DDR_D45
DDR_D40
DDR_DQS5
DDR_DM5
+V_DDR_MCH_REF
DDR_A_D0 DDR_D0
DDR_A_D4
DDR_A_D1
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_DM1
DDR_A_D9
DDR_A_DQS1
DDR_A_D16
DDR_A_D17
DDR_A_D20
DDR_A_D21
DDR_A_DQS2 DDR_DQS2
DDR_A_DM2
DDR_A_D18
DDR_A_D19
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D29
DDR_A_D28
DDR_A_DM3
DDR_A_DQS3
DDR_A_D26
DDR_A_D30
DDR_A_D31
DDR_A_D27
DDR_A_D36
DDR_A_D33
DDR_A_D32
DDR_A_D37
DDR_A_DM4
DDR_A_DQS4
DDR_A_D38
DDR_A_D39
DDR_A_D34
DDR_A_D35
DDR_A_D41
DDR_A_D44
DDR_A_D45
DDR_A_D40
DDR_A_DQS5
DDR_A_DM5
RP99 10_0804_8P4R_5%
RP100 10_0804_8P4R_5%
RP101 10_0804_8P4R_5%
RP102 10_0804_8P4R_5%
RP103 10_0804_8P4R_5%
RP104 10_0804_8P4R_5%
RP105 10_0804_8P4R_5%
RP108 10_0804_8P4R_5%
RP110 10_0804_8P4R_5%
RP112 10_0804_8P4R_5%
RP114 10_0804_8P4R_5%
RP116 10_0804_8P4R_5%
RP118 10_0804_8P4R_5%
RP119 10_0804_8P4R_5%
3
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
2
+1.25VS
RP83 56_0804_8P4R_5%
RP86 56_0804_8P4R_5%
RP89 56_0804_8P4R_5%
RP92 56_0804_8P4R_5%
RP95 56_0804_8P4R_5%
RP98 56_0804_8P4R_5%
2
1
DDR_D[0..63]14
DDR_DM[0..7]14
DDR_DQS[0..7]14
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
DDR_A_D46
DDR_A_D47
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D53
DDR_A_D49
DDR_A_D48
DDR_A_DM6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
DDR_A_D50 DDR_D50
DDR_A_D51 DDR_D51
DDR_A_D57
DDR_A_DM7
DDR_A_D56
DDR_A_D60
DDR_A_D61
DDR_A_DQS7
DDR_A_D63
DDR_A_D62
DDR_A_D58
DDR_A_D59
DDR_CKE2
DDR_B_MA11
DDR_B_MA8
DDR_CKE3
DDR_B_MA13
DDR_B_MA12
DDR_B_MA9
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_B_CAS#
DDR_SCS#3
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_SCS#2
DDR_B_MA7
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
RP107 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP109 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP111 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP113 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP115 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP117 10_0804_8P4R_5%
1 8
2 7
3 6
4 5
Title
Size Document Number Rev
Date: Sheet
DDR_D[0..63]
DDR_DM[0..7]
DDR_DQS[0..7]
DDR_D46
DDR_D47
DDR_D43
DDR_D42
DDR_D52
DDR_D53
DDR_D49
DDR_D48
DDR_DM6
DDR_DQS6
DDR_D54
DDR_D55
DDR_D57
DDR_DM7
DDR_D56
DDR_D60
DDR_D61
DDR_DQS7
DDR_D63
DDR_D62
DDR_D58
DDR_D59
Compal Electronics, Inc.
DDRI-SODIMM SLOT2
EDL71 LA-2351
1
1B
15 59Wednesday, March 02, 2005
of
5
Layout note :
Distribute as clo se as possible
to DDR-SODIMM.
+2.5V
4
3
2
1
1
C978
D D
0.1U_0402_16V4Z
2
+2.5V +2.5V
1
C989
0.1U_0402_16V4Z
2
1
C979
0.1U_0402_16V4Z
2
1
C990
0.1U_0402_16V4Z
2
1
C980
0.1U_0402_16V4Z
2
1
C991
0.1U_0402_16V4Z
2
1
C981
0.1U_0402_16V4Z
2
1
C992
0.1U_0402_16V4Z
2
1
C982
0.1U_0402_16V4Z
2
1
C993
0.1U_0402_16V4Z
2
1
C983
0.1U_0402_16V4Z
2
1
C994
0.1U_0402_16V4Z
2
1
C984
0.1U_0402_16V4Z
2
1
+
C995
150U_C_4VM
2
@
1
C985
0.1U_0402_16V4Z
2
1
+
C996
150U_C_4VM
2
1
C986
0.1U_0402_16V4Z
2
1
C987
0.1U_0402_16V4Z
2
1
C988
0.1U_0402_16V4Z
2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
C C
B B
+1.25VS
1
C997
0.1U_0402_16V4Z
2
+1.25VS
1
C1007
0.1U_0402_16V4Z
2
+1.25VS
1
C1017
0.1U_0402_16V4Z
2
+1.25VS
1
@
C998
0.1U_0402_16V4Z
2
1
C1008
0.1U_0402_16V4Z
2
1
C1018
0.1U_0402_16V4Z
2
1
@
C999
0.1U_0402_16V4Z
2
1
C1009
0.1U_0402_16V4Z
2
1
C1019
0.1U_0402_16V4Z
2
1
C1000
0.1U_0402_16V4Z
2
1
C1010
0.1U_0402_16V4Z
2
1
C1020
0.1U_0402_16V4Z
2
1
C1001
0.1U_0402_16V4Z
2
1
C1011
0.1U_0402_16V4Z
2
1
C1021
0.1U_0402_16V4Z
2
1
C1002
0.1U_0402_16V4Z
2
1
@
C1012
0.1U_0402_16V4Z
2
1
C1022
0.1U_0402_16V4Z
2
1
C1003
0.1U_0402_16V4Z
2
1
C1013
0.1U_0402_16V4Z
2
1
@
C1023
0.1U_0402_16V4Z
2
1
C1004
0.1U_0402_16V4Z
2
1
C1014
0.1U_0402_16V4Z
2
1
C1024
0.1U_0402_16V4Z
2
1
C1005
0.1U_0402_16V4Z
2
1
C1015
0.1U_0402_16V4Z
2
1
C1025
0.1U_0402_16V4Z
2
1
C1006
0.1U_0402_16V4Z
2
1
C1016
0.1U_0402_16V4Z
2
1
C1026
0.1U_0402_16V4Z
2
1
C1027
0.1U_0402_16V4Z
2
+1.25VS
1
C1037
0.1U_0402_16V4Z
2
+1.25VS
A A
1
C1047
0.1U_0402_16V4Z
2
1
C1028
0.1U_0402_16V4Z
2
1
C1038
0.1U_0402_16V4Z
2
1
C1048
0.1U_0402_16V4Z
2
5
1
C1029
0.1U_0402_16V4Z
2
1
C1039
0.1U_0402_16V4Z
2
1
@
C1049
0.1U_0402_16V4Z
2
1
C1030
0.1U_0402_16V4Z
2
1
C1040
0.1U_0402_16V4Z
2
1
C1050
0.1U_0402_16V4Z
2
1
C1031
0.1U_0402_16V4Z
2
1
C1041
0.1U_0402_16V4Z
2
1
C1051
0.1U_0402_16V4Z
2
4
1
C1032
0.1U_0402_16V4Z
2
1
C1042
0.1U_0402_16V4Z
2
1
C1052
0.1U_0402_16V4Z
2
1
C1033
0.1U_0402_16V4Z
2
1
@
C1043
0.1U_0402_16V4Z
2
1
@
C1053
0.1U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C1034
0.1U_0402_16V4Z
2
1
C1044
0.1U_0402_16V4Z
2
1
C1054
0.1U_0402_16V4Z
2
1
C1035
0.1U_0402_16V4Z
2
1
@
C1045
0.1U_0402_16V4Z
2
1
C1055
0.1U_0402_16V4Z
2
3
1
C1036
0.1U_0402_16V4Z
2
1
C1046
0.1U_0402_16V4Z
2
1
C1056
0.1U_0402_16V4Z
2
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
DDR Decoupling
EDL71 LA-2351
1
16 59Wednesday, March 02, 2005
1B
5
+3VS
1 2
D
1 3
Q1
2N7002_SOT23
G
2
2
G
1 3
D
1 2
R2
S
Q2
2N7002_SOT23
S
R11670_0402_5% @
R11660_0402_5% @
ICH_SMBDATA29,39
D D
+3VS
ICH_SMBCLK29,39
ICH_SMBCLK
D
1
3
G
S
2
12
2.2K_0402_5%
12
R3
2.2K_0402_5%
CLK_SDATAICH_SMBDATA
CLK_SCLK
1
1
2
2
C10
C11
4.7U_0805_10V4Z
2N7002
FSC FSB FSA CPU
CLKSEL0 CLKSEL2CLKSEL1
000
C C
*
0
0
1
1
1
00
1
0
1
11
00
1
0
1
0
111
B B
CPU_BSEL06
A A
CPU_BSEL16
1 2
R48
0_0402_5%
1 2
R61 0_0402_5%
5
MHz
266
133
200
166
333
100
400
RESERVED
Table :
+VCCP
R44
1K_0402_5%
@
1 2
R51
@
0_0402_5%
1 2
+VCCP
R56
1K_0402_5%
@
1 2
R62
@
0_0402_5%
1 2
SRC
MHz
100
100
100
100
100
100
100
PCI
MHz
33.3
33.3
12
12
CLK_EXT_SD4832
CLK_ICH_48M29
CLK_Compal_14M
CLK_SIO_14M43
CLK_PCI_PCM32
CLK_PCI_MINI138
CLK_PCI_139434
CLK_PCI_MINI37
CLK_PCI_LOM35
CLK_PCI_ICH27
CLK_PCI_EC41,43
CLKSEL0
CLKSEL1
33.3
33.3
Stuff R73 for Cypress clock gen
33.3
33.3
33.3
R67
0_0402_5%
R46
1K_0402_5%
R1181
1 2
0_0402_5%
1 2
R59
1K_0402_5%
4
C6
0.1U_0402_16V4Z
CLK_SDATA 14,15
CLK_SCLK 14,15
CK_VDD_48CK_VDD_A CK_VDD_REF
1
1
2
2
C12
0.047U_0402_16V4Z
C15
1 2
33P_0402_50V8J
C16
33P_0402_50V8J
1 2
MCH_CLKSEL0 9
MCH_CLKSEL1 9
C13
4.7U_0805_10V4Z
Place crystal within
500 mils of CK410
1 2
CLK_ICH_48M CLKSEL2
CLK_Compal_14M
CLKSEL0
CLK_SIO_14M
CLKSEL1
CLK_PCI_PCM PCI_PCM
CLK_PCI_1394
CLK_PCI_LOM
CLK_PCI_ICH PCI_ICH
+3VS
CLK_PCI_EC
4
1 2
L1
CHB2012U121_0805
1
2
0.047U_0402_16V4Z
X1
14.31818MHZ_20P_6X1430004201
1 2
L2
CHB2012U121_0805
1
2
C14
0.047U_0402_16V4Z
CLK_XTAL_IN
CLK_XTAL_OUT
R1026 22_0402_5%
1 2
R1025 22_0402_5%
1 2
12
12
1 2
R73 475_0603_1%@
R31 10_0402_5%
R1065 10_0402_5%
R32 33_0402_5%
R33 33_0402_5%
R34 33_0402_5%
R36 33_0402_5%
1 2
R38 10K_0402_5%
12
R69 33_0402_5%
+3VS
R53
10K_0402_5%
1 2
CLKSEL2
R55
10K_0402_5%
@
1 2
+CK_VDD_MAIN2
R104922_0402_5% @
R6022_0402_5% @
12
12
12
PCI_MINICLK_PCI_MINI
12
12
12
1 2
R41 475_0603_1%
3
+CK_VDD_MAIN+3VS
1 2
R22
1_0603_5%
1 2
R24
2.2_0603_5%
PCI_1394
PCI_LOM
PCICLKF0
CLK_SCLK
CLK_SDATA
CLKIREF
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CK_VDD_REF
CK_VDD_48
3
+CK_VDD_MAIN
2
C1
10U_0805_10V4Z
1
2
C7
10U_0805_10V4Z
1
U1
21
VDDPCIEX_0
28
VDDPCIEX_1
34
VDDPCIEX_2
1
VDDPCI_0
7
VDDPCI_1
42
VDDCPU
48
VDDREF
11
VDD48
50
X1
49
X2
12
FS_A/USB_48MHz
53
REF1/FSLC/TEST_SEL
16
FSLB/TEST_MODE
5
PCICLK5
4
PCICLK4
3
PCICLK3
56
PCICLK2/REQ_SEL
9
SELPCIEX_LCDCLK#/PCICLK_F1
8
ITP_EN/PCICLK_F0
46
SCLK
47
SDATA
39
IREF
13
GND_0
29
GND_1
2
GND_2
45
GND_3
51
GND_4
6
GND_5
ICS954226AGT_TSSOP56
1
C2
0.1U_0402_16V4Z
2
1
C8
0.1U_0402_16V4Z
2
1 2
R14
2.2_0603_5%
1
C3
0.1U_0402_16V4Z
2
1
C9
0.1U_0402_16V4Z
2
CK_VDD_A CLK_PCIE_VGA#
VDDA
GNDA
PCI/SRC_STOP#
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
PEREQ1#/PCIEXT5
PEREQ2#/PCIEXC5
PCIEXT4
PCIEXC4
SATACLKT
SATACLKC
PCIEXT3
PCIEXC3
PCIEXT2
PCIEXC2
PCIEXT1
PCIEXC1
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
DOTT_96MHz
DOTC_96MHz
VTT_PWRGD#/PD
REF0
1
2
37
38
PM_STP_PCI#
55
PM_STP_CPU#
54
MCH_BCLK
41
MCH_BCLK#
40
CPU_BCLK
44
CPU_BCLK#
43
36
CPU_ITP# CLK_CPU_ITP#
35
PEREQ1#
33
PEREQ2#
32
MCH_3GPLL
31
MCH_3GPLL# CLK_MCH_3GPLL#
30
26
PCIE_VGA#
27
PCIE_ICH CLK_PCIE_ICH
24
PCIE_ICH#
25
22
23
PCIE_CARD CLK_PCIE_CARD
19
PCIE_CARD#
20
17
18
14
15
CLK_ENABLE#
10
52
2
1
C4
0.1U_0402_16V4Z
C5
0.1U_0402_16V4Z
2
Place near each pin
W>40 mil
Place near CK410
PM_STP_PCI# 29
PM_STP_CPU# 29,55
1 2
R1041 10K_0402_5%
13
2
G
CLK_ICH_14M
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITPCPU_ITP
+3VS
CLK_MCH_3GPLL
CLK_PCIE_VGAPCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH#
CLK_PCIE_CARD#
DREF_SSCLK
DREFCLK#DOT96#
Title
Size Document Number Rev
Date: Sheet
1 2
R23 33_0402_5%
1 2
R25 33_0402_5%
1 2
R26 33_0402_5%
1 2
R27 33_0402_5%
1 2
R29 33_0402_5%@
1 2
R30 33_0402_5%@
R1152 10K_0402_5%@
1 2
R1153 0_0402_5%@
1 2
1 2
R35 33_0402_5%
1 2
R37 33_0402_5%
2@
1 2
R1107 33_0402_5%
1 2
R1108 33_0402_5%2@
1 2
R39 33_0402_5%
1 2
R40 33_0402_5%
1 2
R45 33_0402_5% @
1 2
R47 33_0402_5%@
PCIE_GM
PCIE_GM# DREF_SSCLK#
DOT96 DREFCLK
CLKREF
1@
1 2
R49 33_0402_5%
1@
1 2
R50 33_0402_5%
1 2
R52 33_0402_5%1@
1 2
R54 33_0402_5%1@
D
Q78 2N7002_SOT23
S
1 2
R57 22_0402_5%
1 2
R58 22_0402_5%
2
1
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_VGA
DREF_SSCLK
DREF_SSCLK#
DREFCLK
DREFCLK#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
CLK_CPU_ITP 5
CLK_CPU_ITP# 5
PCIECARD_CLKEN 39,41
CLK_MCH_3GPLL 11
CLK_MCH_3GPLL# 11
CLK_PCIE_VGA 18
CLK_PCIE_VGA# 18
CLK_PCIE_ICH 29
CLK_PCIE_ICH# 29
CLK_PCIE_CARD 39
CLK_PCIE_CARD# 39
DREF_SSCLK 9
DREF_SSCLK# 9
DREFCLK 9
DREFCLK# 9
+3VS
VGATE 9,29,55
CLK_ICH_14M 29
CLK_CODEC_14M 44
R1 49.9_0402_1%@
R4 49.9_0402_1%@
R5 49.9_0402_1%
R6 49.9_0402_1%
R7 49.9_0402_1%
R8 49.9_0402_1%
R9 49.9_0402_1%
R10 49.9_0402_1%
R16 49.9_0402_1%
R17 49.9_0402_1%
R1105 49.9_0402_1%2@
R1106 49.9_0402_1% 2@
R18 49.9_0402_1%1@
R19 49.9_0402_1%1@
R20 49.9_0402_1%1@
R21 49.9_0402_1%1@
R13 49.9_0402_1%@
R15 49.9_0402_1%@
Compal Electronics, Inc.
Clock Generator
EDL71 LA-2351
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
17 59Wednesday, March 02, 2005
12
12
12
12
12
12
1B
of
5
PEG_TXN[0..15]21
PEG_TXP[0..15]21
PEG_RXN[0..15]21
PEG_RXP[0..15]21
D D
FLASH ROM
(if no problem can be remove)
T25PAD
T26PAD
T27PAD
T28PAD
C C
SIN
SCLK
SOUT
PEG_TXN[0..15]
PEG_TXP[0..15]
PEG_RXN[0..15]
PEG_RXP[0..15]
SCS# 19
U60 UNMOUNT : VBIOS MUST COMBINE WITH SYSTEM BIOS
CLK_PCIE_VGA17
CLK_PCIE_VGA#17
B B
A A
R182
1K_0402_5% 2@
+3VS
+3VS
12
5
R171
1 2
R172 10K_0402_5%
1 2
2@
C202 0.1U_0402_16V4Z
PLTRST_ICH#27
1 2
2@
X2
4
VDD
1
OE
27MHZ_15P
2@
10K_0402_5%@
OSC_OUT26
OUT
GND
PLTRST_VGA#29
3
2
+1.2VS
@
1 2
R1116 0_0402_5%
TV_Y25
TV_C25
TV_CVBS25
SMBCLK26
SMBDATA26
OSC_OUT
1 2
R184
121_0603_1%
75_0603_1%
+3VS
+3VS
2@
12
R186
2@
4
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15
CLK_PCIE_VGA
CLK_PCIE_VGA#
R168 150_0402_1%
2@
1 2
R169 100_0402_1%
2@
1 2
R170 10K_0402_1%
2@
1 2
R1115 0_0402_5%
2@
1 2
2@
1 2
R173 1K_0402_5%
2@
R174 715_0402_1%
TV_Y
TV_C
TV_CVBS
R178 0_0402_5%
R179 0_0402_5%
1 2
R181 1K_0402_5%
R185 10K_0402_5%
12
2@
1 2
R392 4.7K_0402_5%
R762 0_0402_5%@
1 2
@
1 2
R391 0_0402_5%
2@
1 2
R393 4.7K_0402_5%
@
12
2@
12
2@
2@
12
4
3
U5A
AH30
PCIE_RX0P
AG30
PCIE_RX0N
AG29
PCIE_RX1P
AF29
PCIE_RX1N
AE29
PCIE_RX2P
AE30
PCIE_RX2N
AD30
PCIE_RX3P
AD29
PCIE_RX3N
AC29
PCIE_RX4P
AB29
PCIE_RX4N
AB30
PCIE_RX5P
AA30
PCIE_RX5N
AA29
PCIE_RX6P
Y29
PCIE_RX6N
W29
PCIE_RX7P
W30
PCIE_RX7N
V30
PCIE_RX8P
V29
PCIE_RX8N
U29
PCIE_RX9P
T29
PCIE_RX9N
T30
PCIE_RX10P
R30
PCIE_RX10N
R29
PCIE_RX11P
P29
PCIE_RX11N
N29
PCIE_RX12P
N30
PCIE_RX12N
M30
PCIE_RX13P
M29
PCIE_RX13N
L29
PCIE_RX14P
K29
PCIE_RX14N
K30
PCIE_RX15P
J30
PCIE_RX15N
AF26
PCIE_TX0P
AE26
PCIE_TX0N
AC25
PCIE_TX1P
AB25
PCIE_TX1N
AC27
PCIE_TX2P
AB27
PCIE_TX2N
AC26
PCIE_TX3P
AB26
PCIE_TX3N
Y25
PCIE_TX4P
W25
PCIE_TX4N
Y27
PCIE_TX5P
W27
PCIE_TX5N
Y26
PCIE_TX6P
W26
PCIE_TX6N
U25
PCIE_TX7P
T25
PCIE_TX7N
U27
PCIE_TX8P
T27
PCIE_TX8N
U26
PCIE_TX9P
T26
PCIE_TX9N
P25
PCIE_TX10P
N25
PCIE_TX10N
P27
PCIE_TX11P
N27
PCIE_TX11N
P26
PCIE_TX12P
N26
PCIE_TX12N
L25
PCIE_TX13P
K25
PCIE_TX13N
L27
PCIE_TX14P
K27
PCIE_TX14N
L26
PCIE_TX15P
K26
PCIE_TX15N
AF27
PCIE_REFCLKP
AE27
PCIE_REFCLKN
AC23
PCIE_CALRP
AB24
PCIE_CALRN
AB23
PCIE_CALI
AE25
PCIE_TESTIN
AD25
PWRGD
AD24
PWRGD_MASK
AH21
R2SET
AK21
Y_G
AJ22
C_R_PR
AK22
COMP_B_PB
AJ24
H2SYNC
AK24
V2SYNC
AG22
DDC3CLK
AG23
DDC3DATA
AJ23
SSIN
AH24
XTALIN
XTALOUT
SSOUT
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
E8
TEST_YCLK
B6
TEST_MCLK
AF25
PLLTEST
AH25
STEREOSYNC
M24P_BGA708
2@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Part 1 of 5
GPIO_PWRCNTL
GPIO_MEMSSIN
PCI EXPRESS
DAC2CLK
SS
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15
DVO / EXT TMDS / GPIOTMDSDAC1
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
LVDS
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
DDC2DATA
DDC1DATA
GPIO_AUXWIN
THERM
3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
DVOMODE
VREFG
TXCLK_LN
TXCLK_LP
TXCLK_UN
TXCLK_UP
DIGON
BLON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
HPD1
HSYNC
VSYNC
RSET
DDC1CLK
DPLUS
DMINUS
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
R151 0_0402_5%
1 2
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20
AE12
1 2
AG12
R1114 0_0402_5% 2@
AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12
AE13
AE14
AF12
AK27
R
AJ27
G
AJ26
B
AJ25
AK25
AH26
AG25
AF24
AG24
D+
AF11
D-
AE11
2@
R152 10K_0402_5%2@
MEMSEL0
MEMSEL1
1 2
R156 0_0402_5%@
10K_1206_8P4R_5%
4 5
3 6
2 7
1 8
RP28
2@
ENVDD
BACKLITE_ON
1 2
R177 100K_0402_5%2@
2@
1 2
R180 499_0402_1%
D+ 26
D- 26
1 2
SOUT
SIN
SCLK
12
2@
1 2
R763 0_0402_5%
R183
10K_0402_5%
0_0402_5%
@
GPIO0 26
GPIO1 26
GPIO2 26
GPIO3 26
GPIO4 26
GPIO5 26
GPIO6 26
ROM_ID4 26
ROM_ID1 26
ROM_ID2 26
ROM_ID3 26
POWER_SEL 54
OSC_SPREAD 26
R154 0_0402_5%@
1 2
R155 0_0402_5%@
1 2
ROM_ID4 26
12
12
R157
R158
0_0402_5%
2@
LVDSA0- 24
LVDSA0+ 24
LVDSA1- 24
LVDSA1+ 24
LVDSA2- 24
LVDSA2+ 24
LVDSAC- 24
LVDSAC+ 24
LVDSB0- 24
LVDSB0+ 24
LVDSB1- 24
LVDSB1+ 24
LVDSB2- 24
LVDSB2+ 24
LVDSBC- 24
LVDSBC+ 24
ENVDD 24
BACKLITE_ON 11,24,41
2
2
+3VS
R164 10K_0402_5% 2@
12
R167
2@
1K_0402_5%
VGA_RED 25
VGA_GRN 25
VGA_BLU 25
HSYNC 25
VSYNC 25
DAT_DDC2 25
CLK_DDC2 25
AUXWIN 26
1
MEM Type Selection
64M Samsung
64M Hynix
128M Samsung
128M Hynix
12
R1020
2.2K_0402_5%
2@
1 2
2@
1 2
R166 1K_0402_5%
+3VS
12
R1021
2.2K_0402_5%
2@
MEMSEL0
LOW
LOW
HI
HI HI
EDID_DAT 24
EDID_CLK 24
MEMSEL1
LOW
HI
LOW
+3VS
Note:
Keep toggling signals always from
RSET/RSET2 resistor and trace.
Layout wider in resistor to GND.
CRT I/F
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M24-P
EDL71 LA-2351
18 59Wednesday, March 02, 2005
1
of
1B
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