Compal LA-2271, Aspire 1800, Aspire 1804WSMi Schematic

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Compal Confidential

ECQ60 Schematics Document

Desktop LGA-775 Package with Grantsdale + ICH6 + ATI M24-P

3 3

2004-08-09-C

REV: 1.0

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Cover Sheet

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

154Monday, August 09, 2004

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of

1A

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Compal confidential

Block Diagram

Model Name : ECQ60
File Name : LA-2271 Rev:0.2
Part Number : DA8CQ60L000

1 1

Fan Control

VGA RAM

2 2

IDSEL: AD18
PIRQG#, PIRQH#
GNT#1, REQ#1
GNT#4, REQ#4

MINIPCI I/F

Slot 1

IDSEL: AD16
PIRQE#
GNT#0, REQ#0

1394 Controller

TI TSB43AB21A

page 40

4Mx32 *4

page 19,20

page 30page 33

LVDS, CRT,
TV-OUT CONN

page 21,22

ATI M24-P

page 15,16,17,18

IDSEL: AD17
PIRQF#
GNT#3, REQ#3

PCI BUS

LAN

BCM5788
/BCM4401

page 31

PCIExpress
x16-Lane

PIRQA#

IDSEL: AD20
PIRQA#
GNT#2, REQ#2
SERIRQ

CardBus

ENE CB1410

3.3V 33MHz

page 28

Desktop Prescott

LGA-775

775pin

System Bus

800MHz

page 4,5,6

Grantsdale

BGA-1210 Pin

page 7,8,9,10

Direct Med ia Interface

2GB/s point-to-point(1GB/s each direction)

ICH6

BGA-609 Pin

page 23,24,25,26

Thermal Se nsor

ADM1032ARM

page 5

HD#(0..63)HA#(3..31)

Clock Generator

ICS954101

page 14

Memory BUS
(DDR)

2.6V 333/400MHz

DDR SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12,13

USB port 3

TV-Tuner
(USB I/F)

page 34

3.3V 48MHz

3.3V 24.576MHz

3.3V ATA100

USB port 0, 2, 4, 6

USB conn

page 34

USBx4

AC-LINK

USB port 7

Card Reader
I/F

page 40

USB port 1

BlueTooth I/F

page 34

1394
Connector

3 3

DC/DC Interface

page 30

LED INDICATOR

RJ45

page 32

Suspend

page 43

Power Circuit
DC/DC

page
44,45,46,47,48
49,50,51,52

4 4

A

Power On/Off
Reset & RTC

page 39

page 39

Slot 0

page 29

SIO LPC47N217

Base I/O Address 2Eh

page 35

LPC BUS

3.3V 33MHz

ENE KB910

LPC to X-BUS
& KBC

page 37

HDD

page 27

CDROM

page 27

AC97 Codec

ALC250

page 41

MDC

page 36

FIR

page 34

Legacy I/O Option

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BIOS

page 38

Touch Pad

Int.KBD

C

page 37

page 37

CIR / LED /
CD-PLAY
CONN

page 40

Title

Size Document Number Rev

D

Date: Sheet

Amplifier /
Phone Jack/
Line In Jack/
Mic In Jack

page 42

Compal Electronics, Inc.

Block Diagram

Custom

ECQ60 LA-2271

1A

254Monday, August 09, 2004

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Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+
+CPU_CORE
+V_FSB_VTT ON OFF OFF1.2V rail for Processor I/O & GTL Termination
+PCIE_1.2VS
+1.3VS 1.3VS for DDR1 Termination
+VGA_CORE VGA Core Power ON

+1.8VS
+2.6V
+2.6VS 2.6VS switched power rail
+3VALW
+3V
+3VS
+5VALW
+5VS

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or batte ry power rail for power circuit.
Core voltage for CPU

+PCIE_1.2VS power rail for VGA PCIExpress

MCH & ICH Core Power ON O FF OFF+1.5VS

1.8V switched power rail

2.6V power rail for DDR1

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V switched power rail
12V always on power rail
RTC power

S0-S1 S3 S5

N/A N/A N/A

ON OFF

ON OFF
ON OFF OFF

OFF OFF

OFF

ON
ON

ON
OFF

ON
ON

ON ON*
ON

ON

OFF

ON
ON

ON
OFF

ON

ON

ON+12VALW
ON

ON

N/AN/AN/A
OFF

OFF

OFF
OFF
OFF

OFF
OFF
ON*
OFF
ON*
ON

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

Board ID

*

100K +/- 5%Ra

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

0
1
2
3
4

Rb V min

0

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

PCB Revision

0.1

0.2

0.3

0.4

Vtyp

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

5
6
7

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

VGA

CardBus

LAN

3 3

Mini-PCI

1394

AD20
AD17
AD18,AD22
AD16 0

2

3PIRQF

1

PIRQA
PIRQA

PIRQG/PIRQH
PIRQE

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

0001 011X b
1010 000X b
1011 000Xb

EC SM Bus2 address

Device

ADM1032

1001 100X b

ICH6 SM Bus address

Device

Clock Generator
( ICS954101)

4 4

DDR DIMM0
DDR DIMM1

A

Address

1101 001Xb
1010 000Xb
1010 010Xb

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Notes

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

354Monday, August 09, 2004

E

of

1A

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1 1

AB6

AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5

AJ5
AJ6

AD3
AB2

F28

G28

AA2

JP20A

L5
P6

M5

L4
M4
R4

T5
U6

T4
U5
U4

V5

V4

W5
W6

Y6

Y4

K4

J5
M6

K6

J6
D2

U2
U3

F3
G8
C2
C3

D4

E4
G7

Y1

V2

H_A#[3..31]7

2 2

H_REQ#[0..4]7

H_ADS#7

R141 62_0402_5%

+V_FSB_VTT

+VTT_OUT_LEFT

3 3

+VTT_OUT_RIGHT

1 2

R116 62_0402_5%

1 2

R138 @1K_0402_5%

H_BR0#7
H_BPRI#7
H_BNR#7
H_LOCK#7

CLK_BCLK14
CLK_BCLK#14

H_HIT#7
H_HITM#7

H_DEFER#7

1 2

H_BOOTSELECT

H_IERR#

H_BOOTSELECT

LL_ID0

(For Test Point)

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28

H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

+CPU_CORE

AG22

A03#

VCCP1
A04#
A05#
A06#
A07#
A08#
A09#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADS#

AP0#
AP1#
BINIT#
IERR#

BR0#
BPRI#
BNR#
LOCK#

BCLK0
BCLK1

HIT#
HITM#
DEFER#

BOOTSELECT
LL_ID0
LL_ID1

K29

U25

B

AM26

AL8

AE12

AE11

W23

W24

W25

T25

Y28

AL18

AC25

W30

Y30

AN14

AD28

Y26

AC29

M29

U24

J23

AC27

AM18

AM19

AB8

AC26

J28

VCCP2

VCCP3

VCCP4

VCCP5

VCCP6

VCCP7

VCCP8

VCCP9

VCCP10

VCCP11

VCCP12

VCCP13

VCCP14

VCCP15

VCCP16

VCCP17

VCCP18

VCCP19

VCCP20

VCCP21

VCCP22

VCCP23

VCCP24

VCCP25

VCCP26

VCCP27

VCCP28J8VCCP29

VCCP76

VCCP77Y8VCCP78

VCCP79

VCCP80

VCCP81

VCCP82

VCCP83

VCCP84

VCCP85

VCCP86

VCCP87U8VCCP88

VCCP89

VCCP90

VCCP91

VCCP92

VCCP93

VCCP94

VCCP95

VCCP96

VCCP97

VCCP98

VCCP99

VCCP100

VCCP101

VCCP102

VCCP103

AE9

J22

Y29

AK25

AK19

AG15

K28

U23

N27

U28

M23

AJ12

AD27

AG29

AD8

AK18

AM22

T29

K24

AK12

AH28

AH21

AH22

AM14

AM25

C

T30

AM9

AF15

AC8

AE14

N23

W29

U29

AC24

VCCP30

VCCP31

VCCP32

VCCP33

VCCP34

VCCP35

VCCP36

VCCP37

VCCP38

LGA-775

(1/4)

VCCP104

VCCP105

VCCP106

VCCP107

VCCP108

VCCP109

VCCP110

VCCP111

VCCP112

J25

U30

J19

AJ18

AL21

AG25

T24

AG21

AM21

D

AC23

Y23

AN26

AN25

AN11

AN18

Y27

Y25

AD24

AE23

AE22

AN19

AE21

AM30

AE19

AC30

AE15

M30

K27

M24

AN21

AC28

N25

AE18

W26

AD25

N30

AD26

AJ26

AM29

M25

M26

L8

H_D#0

VCCP39

VCCP40

VCCP41

VCCP42

VCCP43

VCCP44

VCCP45

VCCP46

VCCP47

VCCP48

VCCP49

VCCP50

VCCP51V8VCCP52K8VCCP53

VCCP54

VCCP55

VCCP56

VCCP57

VCCP58

VCCP59

VCCP60

VCCP61

VCCP62T8VCCP63

VCCP64

VCCP65

VCCP66

VCCP67

VCCP68M8VCCP69

VCCP70

VCCP71

VCCP72

VCCP73

VCCP74

VCCP113

VCCP114

VCCP115

VCCP116

VCCP117

VCCP118

VCCP119

VCCP120

VCCP121

VCCP122

VCCP123

VCCP124

VCCP125

VCCP126R8VCCP127

VCCP128

VCCP129

VCCP130

VCCP131

VCCP132

VCCP133

VCCP134

VCCP135

VCCP136

VCCP137

VCCP138

VCCP139

VCCP140

VCCP141

VCCP142

VCCP143

VCCP144

VCCP145

VCCP146

VCCP147

VCCP148

J15

J20

AJ22

AH30

AH18

AH26

AG12

W27

T23

U27

AN8

AL25

AH14

J10

AJ15

AK22

AK26

AN29

AG11

J26

J18

AN9

AG26

J21

AL15

AF18

AH15

AF8

AF11

AK15

AK21

AD23

AG27

AG30

AM15

B4

VCCP75

D00#

C5

D01#

A4

D02#

C6

D03#

A5

D04#

B6

D05#

B7

D06#

A7

D07#

A10

D08#

A11

D09#

B10

D10#

C11

D11#

D8

D12#

B12

D13#

C12

D14#

D11

D15#

G9

D16#

F8

D17#

F9

D18#

E9

D19#

D7

D20#

E10

D21#

D10

D22#

F11

D23#

F12

D24#

D13

D25#

E13

D26#

G13

D27#

F14

D28#

G14

D29#

F15

D30#

G15

D31#

G16

D32#

E15

D33#

E16

D34#

G18

D35#

G17

D36#

F17

D37#

F18

D38#

E18

D39#

E19

D40#

F20

D41#

E21

D42#

F21

D43#

G21

D44#

E22

D45#

D22

D46#

G22

D47#

D20

D48#

D17

D49#

A14

D50#

C15

D51#

C14

D52#

B15

D53#

C18

D54#

B16

D55#

A17

D56#

B18

D57#

C21

D58#

B21

D59#

B19

D60#

A19

D61#

A22

D62#

B22

D63#

FOX_PE077507-0741-01

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25H_A#29
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

E

H_D#[0..63] 7

+CPU_CORE

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

LGA-775(1/3)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

454Monday, August 09, 2004

E

of

1A

A

B

C

D

E

+V_FSB_VTT

+VTT_OUT_RIGHT

+VTT_OUT_LEFT

1 1

2 2

+V_FSB_VTT

L12 LQG21F4R7N00_0805

1 2

1 2

L11 LQG21F4R7N00_0805

3 3

4 4

Note: Please change to 10uH, DC current
of 120mA parts and close to cap
DC Voltage drop from VTT to VCCA should
be < 70mV

+VTT_OUT_LEFT

+VTT_OUT_RIGHT

1 2

R100 470_0402_5%

1 2

R98 470_0402_5%

1 2

R99 470_0402_5%

1 2

R110 62_0402_5%

1 2

R122 100_0402_5%

+VTT_OUT_RIGHT

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)

CPU_CLKSEL0
CPU_CLKSEL1
CPU_CLKSEL2

H_RESET#
H_PWRGD

H_RS#[0..2]7

H_TRDY#7

H_A20M#24

H_FERR#24

H_IGNNE#24

H_SMI#24

H_PWRGD24

H_STPCLK#24

H_INTR24

H_NMI24

H_INIT#24

H_RESET#7

H_DBSY#7

H_DRDY#7
CPU_CLKSEL07,14
CPU_CLKSEL17,14
CPU_CLKSEL27,14

H_THERMTRIP#24

R156 49.9_0402_1%

1 2

R157 49.9_0402_1%

1 2
1 2
1 2
1 2
1 2

(For Test Point)

T6 PAD
T5 PAD

+

RP1

1 8
2 7
3 6
4 5

1K_1206_8P4R_5%

Close to the CPU

(For Test Point)
(For Test Point)

12
12
12
12

ITP_TRST#
ITP_TCK
ITP_TDI
ITP_TMS

R142 49.9_0402_1%
R147 49.9_0402_1%
R144 49.9_0402_1%
R153 49.9_0402_1%

1 2

C42
33U_D2_8M_R35

R120 100_0402_1%
R129 100_0402_1%
R83 60.4_0402_1%
R132 60.4_0402_1%

A

H_RS#0
H_RS#1
H_RS#2

H_PWRGD

H_RESET#

CPU_CLKSEL0
CPU_CLKSEL1
CPU_CLKSEL2

H_THERMDA
H_THERMDC

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

H_VCCA

VCC_MB_REGULATION
VSS_MB_REGULATION

VCCSENSE
VSSSENSE

H_VSSA

Trace >= 25mils

CLK_ITP14
CLK_ITP#14

COMP2
COMP3
COMP0
COMP1

COMP0
COMP1
COMP2
COMP3

JP20B

B3

RS0#

F5

RS1#

A3

RS2#

H4

RSP#

E3

TRDY#

K3

A20M#

R3

FERR#/PBE#

N2

IGNNE#

P2

SMI#

N1

PWRGOOD

M3

STPCLK#

K1

LINT0

L1

LINT1

P3

INIT#

G23

RESET#

B2

DBSY#

C1

DRDY#

G29

BSEL0

H30

BSEL1

G30

BSEL2

AL1

THERMDA

AK1

THERMDC

M2

THERMTRIP#

AJ2

BPM0#

AJ1

BPM1#

AD2

BPM2#

AG2

BPM3#

AF2

BPM4#

AG3

BPM5#

AE1

TCK

AD1

TDI

AF1

TDO

AC1

TMS

AG1

TRST#

C23

VCCIOPLL

A23

VCCA

AN5

VCC_MB_REGULATION

AN6

VSS_MB_REGULATION

AN3

VCCSENSE

AN4

VSSSENSE

B23

VSSA

AK3

ITP_CLK0

AJ3

ITP_OUT1

A13

COMP0

T1

COMP1

G2

COMP2

R1

COMP3

H_THERMDA

1

H_THERMDC

C549

2

2200P_0402_50V7K

+CPU_CORE

AJ21

VCCP149

+3VS

AM11

VCCP150

B

AL11

AJ11

K30

AL14

AN30

AH25

AL12

AJ9

AK11

AG14

VCCP151

VCCP152

VCCP153

VCCP154

VCCP155

VCCP156

VCCP157

VCCP158

VCCP159

VCCP160

RSVD1N4RSVD2P5RSVD3

RSVD4

RSVD5

RSVD6

RSVD7D1RSVD8

D23

AE4

AC4

AM5

1 2

C550 0.1U_0402_16V4Z

U42

1

VDD

2
3

+VTT_OUT_LEFT

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ADM1032AR_SOP8

G781

N29

AL30

AJ25

VCCP161

VCCP162

VCCP163

RSVD9

RSVD10

E5

F29

AK6

R518

1 2

2.74K_0603_1%

22.1K_0603_1%

AH9

J29

VCCP164

VCCP165

RSVD11G6RSVD12

AH2

8
7
6
5

J11

K25

VCCP166

VCCP167

RSVD13N5RSVD14

AE6

R519

K23

AL19

AM8

VCCP168P8VCCP169

VCCP170

VCCP171

RSVD15C9RSVD16

RSVD17

RSVD18

A20

D16

G10

12

T26

N28

AH12

AL22

VCCP172

VCCP173

VCCP174

RSVD19

RSVD20

RSVD21

F23

E23

E24

10K_0402_5%

1

C658

2

AN15

AJ8

U26

AJ19

T27

AK8

VCCP175

VCCP176

VCCP177

VCCP178

VCCP179

VCCP180

LGA-775

RSVD22H2RSVD23J2RSVD24

RSVD26F6RSVD27T2RSVD28Y3RSVD29

RSVD25

J3

D14

EC_SMC2 37
EC_SMD2 37

+3VALW

12

R517

C

2

B

E

3 1

1U_0603_10V6K

AN12

AG9

N26

AF9

AF22

AH11

AJ14

AH19

AH29

AH27

AG28

AL26

AM12

J24

J13

T28

W28

J12

J27

AG19

AL9

AD30

AF21

Y24

AK14

M27

AF14

J30

AG18

AA8

AG8

AL29

AD29

AH8

N24

AN22

J14

K26

AF19

AF12

M28

AK9

VCCP181

VCCP182

VCCP183

VCCP184

VCCP185

VCCP186

VCCP187

VCCP188

VCCP189

VCCP190

VCCP191

VCCP192

VCCP193

VCCP194

VCCP195

VCCP196

VCCP197

VCCP198

VCCP199

VCCP200

VCCP201

VCCP202

VCCP203

VCCP204

VCCP205

VCCP206

VCCP207J9VCCP208

VCCP209

VCCP210

VCCP211

VCCP212

VCCP213

VCCP214

VCCP215

VCCP216W8VCCP217

VCCP218

VCCP219

VCCP220

VCCP221

VCCP222

VCCP223N8VCCP224

VCCP225

VCCP226

EDRDY#

PCREQ#

DP0#
DP1#
DP2#
DP3#

GTLREF
SKTOCC#
TESTHI00

TESTHI01
TESTHI02
TESTHI03
TESTHI04
TESTHI05
TESTHI06
TESTHI07
TESTHI08
TESTHI09
TESTHI10
TESTHI11

(2/4)

RSVD31E7RSVD32

RSVD30

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VTT23

VTT24

VTTPWRGD

VTT_OUT1

VTT_OUT2J1VTT_SEL

E6

B13

A29

B25

B29

B30

A26

B27

A25

A28

A27

A30

B26

C29

C28

C30

C25

AE3

+V_FSB_VTT

+VTT_OUT_LEFT

R159
680_0402_5%

1 2

Q48
MMBT3904_SOT23

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VTT_POWERGD

13

D

Q47

2

2N7002_SOT23

G

S

C26

B28

C27

D27

D28

D25

D26

D29

D30

AA1

AM6

VTT_POWERGD

TESTHI12

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#

DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

ADSTB0#
ADSTB1#

PROCHOT#

MCERR#

VID2

VID3

VID4

VID5

F27

AL5

AL6

AL4

AK4

AM3

1 2

R108 @1K_0402_5%

+VTT_OUT_LEFT
+VTT_OUT_RIGHT

D

DBI0#
DBI1#
DBI2#
DBI3#

DBR#

MS_ID0
MS_ID1

SLP#

VID0

VID1

FOX_PE077507-0741-01

AM2

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

+VTT_OUT_LEFT
+VTT_OUT_RIGHT

VTT_POWERGD 51

EDRDY# is not a feature of
the Pentium 4 processor in
the 775-land package.

F2
G5

J16
H15
H16
J17

H1
AE8
F26

W3
F25
G25
G27
G26
G24
F24
G3
G4
H5
P1
W2

C8
G12
G20
A16

B9
E12
G19
C17

R6
AD5

A8
G11
D19
C20

AC2
AL2
W1

V1
AB3
L2

+3VS

Width : Space = 10 :15(mil)

H_TESTHI0
H_TESTHI1

H_TESTHI2_7

H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_TESTHI12

ITP_DBR#

MCERR#

H_VID0 51
H_VID1 51
H_VID2 51
H_VID3 51
H_VID4 51
H_VID5 51

Title

Size Document Number Rev

Date: Sheet

H_EDRDY# 7

H_PCREQ# 7

+GTLREF

1

C91
220P_0402_50V7K

2

R102 62_0402_5%
R137 62_0402_5%

R103 62_0402_5%

R128 62_0402_5%
R123 62_0402_5%
R131 62_0402_5%
R125 62_0402_5%
R134 62_0402_5%

H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7

H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7

H_ADSTB#0 7
H_ADSTB#1 7

(For Test Point)

H_PROCHOT# 45,46

(For Test Point)

H_CPUSLP# 24

Compal Electronics, Inc.

LGA-775(2/3)

Custom

ECQ60 LA-2271

GTLREF Voltage
should be

0.67*VTT=0.8V

1U_0603_10V4Z

1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

MS_ID[0:1] are provided to indicate the Market
Segment for the processor and may be used
for future processor compatibility.

H_VID5
H_VID4

H_VID3
H_VID2
H_VID1
H_VID0

+VTT_OUT_LEFT

+GTLREF

1

C98

2

+VTT_OUT_LEFT

1 2

R422 680_0402_5%

1 2

R423 680_0402_5%

RP42

45
36
27
18

680_1206_8P4R_5%

E

12

R119

49.9_0402_1%

12

R118
100_0402_1%

+V_FSB_VTT
+VTT_OUT_LEFT

+V_FSB_VTT

+VTT_OUT_RIGHT

554Monday, August 09, 2004

1A

of

A

B

C

D

E

+CPU_CORE

1 1

JP20C

LGA-775

A12

VSS1

A15

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69

(3/4)

A18

A2
A21
A24

A6

A9

AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA3

AA30

AA6
AA7
AB1

2 2

3 3

AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AB7

AC3
AC6
AC7
AD4

AD7
AE10
AE13
AE16
AE17

AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30

AE5

AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29

AF3
AF30

AF6

AF7
AG10
AG13
AG16
AG17

VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138

AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3
AL7
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AM7
AN1
AN10
AN13
AN16

JP20D

LGA-775

AN17

VSS139

AN2

VSS140

AN20

VSS141

AN23

VSS142

AN24

VSS143

AN27

VSS144

AN28

VSS145

AN7

VSS146

B1

VSS147

B11

VSS148

B14

VSS149

B17

VSS150

B20

VSS151

B24

VSS152

B5

VSS153

B8

VSS154

C10

VSS155

C13

VSS156

C16

VSS157

C19

VSS158

C22

VSS159

C24

VSS160

C4

VSS161

C7

VSS162

D12

VSS163

D15

VSS164

D18

VSS165

D21

VSS166

D24

VSS167

D3

VSS168

D5

VSS169

D6

VSS170

D9

VSS171

E11

VSS172

E14

VSS173

E17

VSS174

E2

VSS175

E20

VSS176

E25

VSS177

E26

VSS178

E27

VSS179

E28

VSS180

E29

VSS181

E8

VSS182

F10

VSS183

F13

VSS184

F16

VSS185

F19

VSS186

F22

VSS187

F4

VSS188

F7

VSS189

G1

VSS190

H10

VSS191

H11

VSS192

H12

VSS193

H13

VSS194

H14

VSS195

H17

VSS196

H18

VSS197

H19

VSS198

H20

VSS199

H21

VSS200

H22

VSS201

H23

VSS202

H24

VSS203

H25

VSS204

H26

VSS205

H27

VSS206

H28

VSS207

(4/4)

VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276

H29
H3
H6
H7
H8
H9
J4
J7
K2
K5
K7
L23
L24
L25
L26
L27
L28
L29
L3
L30
L6
L7
M1
M7
N3
N6
N7
P23
P24
P25
P26
P27
P28
P29
P30
P4
P7
R2
R23
R24
R25
R26
R27
R28
R29
R30
R5
R7
T3
T6
T7
U1
U7
V23
V24
V25
V26
V27
V28
V29
V3
V30
V6
V7
W4
W7
Y2
Y5
Y7

+CPU_CORE

+CPU_CORE

SANYO OS-CON 820uF _ERS7m ohm* 5 H=13mm
SANYO OS-CON 220uF _ERS13m ohm*7 H=6mm

+CPU_CORE

+CPU_CORE

+CPU_CORE

Place all 22U_1206_6.3V6M inside CPU socket cavity

1

C512
22U_1206_6.3V6M

2

1

C527
22U_1206_6.3V6M

2

1

C157
22U_1206_6.3V6M

2

1

C519
22U_1206_6.3V6M

2

1

C530
22U_1206_6.3V6M

2

1

C109
22U_1206_6.3V6M

2

1

C528
22U_1206_6.3V6M

2

1

C108
22U_1206_6.3V6M

2

1

C118
22U_1206_6.3V6M

2

560U_E9_4V_M_R7 change to 820U_E9_2.5V_M_R7 (P/N:CB8200WM000)

1

+

C472
560U_E9_4V_M_R7

2

1

+

C551
220U_C6_6.3V_M_R15

2

1

+

C555
220U_C6_6.3V_M_R15

2

1

+

C495
560U_E9_4V_M_R7

2

1

+

C552

2

220U_C6_6.3V_M_R15

1

+

C556

2

220U_C6_6.3V_M_R15

1

+

C521
560U_E9_4V_M_R7

2

1

+

C553
220U_C6_6.3V_M_R15

2

1

+

C557
220U_C6_6.3V_M_R15

2

1

C531
22U_1206_6.3V6M

2

1

C117
22U_1206_6.3V6M

2

1

C131
22U_1206_6.3V6M

2

1

+

C536
560U_E9_4V_M_R7

2

1

+

C554

2

220U_C6_6.3V_M_R15

1

C511
22U_1206_6.3V6M

2

1

C130
22U_1206_6.3V6M

2

1

C143
22U_1206_6.3V6M

2

1

+

C540
560U_E9_4V_M_R7

2

1

C518
22U_1206_6.3V6M

2

1

C142
22U_1206_6.3V6M

2

1

C158
22U_1206_6.3V6M

2

FOX_PE077507-0741-01

4 4

A

FOX_PE077507-0741-01

B

Decoupling Reference Document:
Grantsdale Chipset Platform Design guide Rev1.0
(14652)Page269

Decoupling Reference Requirement:
560uF Polymer, ESR:6m ohm(each) * 10
22uF X5R * 18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Compal Electronics, Inc.

Title

LGA-775(3/3)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

654Monday, August 09, 2004

E

of

1A

A

B

C

D

E

H_A#[3..31]4

1 1

H_REQ#[0..4]4

2 2

3 3

4 4

H_ADSTB#05
H_ADSTB#15

H_DSTBN#05
H_DSTBN#15
H_DSTBN#25
H_DSTBN#35
H_DSTBP#05
H_DSTBP#15
H_DSTBP#25
H_DSTBP#35

H_DINV#05
H_DINV#15
H_DINV#25
H_DINV#35

H_RESET#5

H_ADS#4
H_BNR#4
H_BPRI#4
H_BR0#4
H_DBSY#5

H_DEFER#4

H_DRDY#5

H_EDRDY#5

H_HIT#4
H_HITM#4
H_LOCK#4

H_PCREQ#5

H_TRDY#5

H_RS#[0..2]5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

U35A

Grantsdale

H29

HA3#

G30
G32

M30

M28

M26

G31

G24

M31
M35

M32

K29
J29

K30
L29

L31
L28
J28
K27
K33

R29
L26
N26

N31
P26
N29
P28
R28
N33
T27
T31
U28
T26
T29

F33
E32
H31

F31
J31

N27
E35

F26
F19
C29
E33
H26
J19
B29

E34
J26
K19
B26

E30
R33
L35
J35

P33
L34
N35
L33
E31
N34

K34
P34
J32

(1/9)

HA4#
HA5#

DDR1

HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HADSTB0#
HADSTB1#

HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HDINV0#
HDINV1#
HDINV2#
HDINV3#

HCPURST#

HADS#
HBNR#
HBPRI#
HBREQ0#
HDBSY#
HDEFER#
HDRDY#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HTRDY#

HRS0#
HRS1#
HRS2#

GRANTSDALE-DDR1_BGA1210

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8

HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41

HOST

HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63

HSWING
HSCOMP
HRCOMP

HVREF
HCLKP

HCLKN

BSEL0
BSEL1
BSEL2

HSWING
Trace=10Mil
Space=7Mil

HSWING

0.01U_0402_16V7K

C70

J33
H33
J34
G35
H35
G34
F34
G33
D34
C33
D33
B34
C34
B33
C32
B32
E28
C30
D29
H28
G29
J27
F28
F27
E27
E25
G25
J25
K25
L25
L23
K23
J22
J24
K22
J21
M21
H23
M19
K21
H20
H19
M18
K18
K17
G18
H18
F17
A25
C27
C31
B30
B31
A31
B27
A29
C28
A28
C25
C26
D27
A27
E24
B25

A23
D24
B23
A24

M23
M22

H16
E15
D17

HSWING
HSCOMP
HRCOMP
MCH_GTLREF

BSEL0
BSEL1
BSEL2

1

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R67 10K_0402_5%
R68 10K_0402_5%
R66 10K_0402_5%

12

R64
301_0402_1%

12

R72
100_0402_1%

H_D#[0..63] 4

+V_FSB_VTT

R87 60.4_0402_1%

1 2

R65 20_0402_1%

1 2

CLK_HCLK 14
CLK_HCLK# 14

1 2
1 2
1 2

MCH_GTLREF
Trace=12Mil
Space=15Mil

PCIE_TXN[0..15]15

PCIE_TXP[0..15]15
VGA_PCIE_RXN[0..15]15
VGA_PCIE_RXP[0..15]15

CPU_CLKSEL0 5,14
CPU_CLKSEL1 5,14
CPU_CLKSEL2 5,14

MCH_GTLREF

C69

0.1U_0402_16V4Z

VGA_PCIE_RXN13
VGA_PCIE_RXN12
VGA_PCIE_RXN11
VGA_PCIE_RXN10
VGA_PCIE_RXN9
VGA_PCIE_RXN8
VGA_PCIE_RXN7
VGA_PCIE_RXN6
VGA_PCIE_RXN5
VGA_PCIE_RXN4
VGA_PCIE_RXN3
VGA_PCIE_RXN2
VGA_PCIE_RXN1
VGA_PCIE_RXN0

VGA_PCIE_RXP15
VGA_PCIE_RXP14
VGA_PCIE_RXP13
VGA_PCIE_RXP12
VGA_PCIE_RXP11
VGA_PCIE_RXP10
VGA_PCIE_RXP9
VGA_PCIE_RXP8
VGA_PCIE_RXP7
VGA_PCIE_RXP6
VGA_PCIE_RXP5
VGA_PCIE_RXP4
VGA_PCIE_RXP3
VGA_PCIE_RXP2
VGA_PCIE_RXP1
VGA_PCIE_RXP0

+V_FSB_VTT+V_FSB_VTT

1

2

PCIE_TXN[0..15]

PCIE_TXP[0..15]
VGA_PCIE_RXN[0..15]
VGA_PCIE_RXP[0..15]

C446 0.1U_0402_16V4Z

1 2

C458 0.1U_0402_16V4Z

1 2

C466 0.1U_0402_16V4Z

1 2

C471 0.1U_0402_16V4Z

1 2

C478 0.1U_0402_16V4Z

1 2

C490 0.1U_0402_16V4Z

1 2

C503 0.1U_0402_16V4Z

1 2

C510 0.1U_0402_16V4Z

1 2

C445 0.1U_0402_16V4Z

1 2

C452 0.1U_0402_16V4Z

1 2

C464 0.1U_0402_16V4Z

1 2

C473 0.1U_0402_16V4Z

1 2

C476 0.1U_0402_16V4Z

1 2

C488 0.1U_0402_16V4Z

1 2

C499 0.1U_0402_16V4Z

1 2

C508 0.1U_0402_16V4Z

1 2

12

R63

49.9_0402_1%

12

R71
100_0402_1%

C444 0.1U_0402_16V4Z

1 2

C447 0.1U_0402_16V4Z

1 2

C460 0.1U_0402_16V4Z

1 2

C467 0.1U_0402_16V4Z

1 2

C475 0.1U_0402_16V4Z

1 2

C487 0.1U_0402_16V4Z

1 2

C492 0.1U_0402_16V4Z

1 2

C507 0.1U_0402_16V4Z

1 2

C441 0.1U_0402_16V4Z

1 2

C450 0.1U_0402_16V4Z

1 2

C459 0.1U_0402_16V4Z

1 2

C469 0.1U_0402_16V4Z

1 2

C474 0.1U_0402_16V4Z

1 2

C484 0.1U_0402_16V4Z

1 2

C497 0.1U_0402_16V4Z

1 2

C504 0.1U_0402_16V4Z

1 2

+VCC_EXP_1.5VS

R73 1K_0402_5%

R133

24.9_0402_1%

12

EXP_SLR

GMCH's PCI Express lane numbers are reversed0

Normal operation1

PCIE_TXN15
PCIE_TXN14
PCIE_TXN13
PCIE_TXN12
PCIE_TXN11
PCIE_TXN10
PCIE_TXN9
PCIE_TXN8
PCIE_TXN7
PCIE_TXN6
PCIE_TXN5
PCIE_TXN4
PCIE_TXN3
PCIE_TXN2
PCIE_TXN1
PCIE_TXN0

PCIE_TXP15
PCIE_TXP14
PCIE_TXP13
PCIE_TXP12
PCIE_TXP11
PCIE_TXP10
PCIE_TXP9
PCIE_TXP8
PCIE_TXP7
PCIE_TXP6
PCIE_TXP5
PCIE_TXP4
PCIE_TXP3
PCIE_TXP2
PCIE_TXP1
PCIE_TXP0

PCIE_RXN15VGA_PCIE_RXN15
PCIE_RXN14VGA_PCIE_RXN14
PCIE_RXN13
PCIE_RXN12
PCIE_RXN11
PCIE_RXN10
PCIE_RXN9
PCIE_RXN8
PCIE_RXN7
PCIE_RXN6
PCIE_RXN5
PCIE_RXN4
PCIE_RXN3
PCIE_RXN2
PCIE_RXN1
PCIE_RXN0

PCIE_RXP15
PCIE_RXP14
PCIE_RXP13
PCIE_RXP12
PCIE_RXP11
PCIE_RXP10
PCIE_RXP9
PCIE_RXP8
PCIE_RXP7
PCIE_RXP6
PCIE_RXP5
PCIE_RXP4
PCIE_RXP3
PCIE_RXP2
PCIE_RXP1
PCIE_RXP0

EXP_SLR

U35B

F11

EXP_RXN0

H11

EXP_RXN1

E9

EXP_RXN2

E7

EXP_RXN3

B4

EXP_RXN4

E5

EXP_RXN5

G5

EXP_RXN6

H7

EXP_RXN7

J5

EXP_RXN8

K7

EXP_RXN9

L5

EXP_RXN10

R10

EXP_RXN11

M7

EXP_RXN12

N5

EXP_RXN13

P8

EXP_RXN14

R5

EXP_RXN15

E11

EXP_RXP0

J11

EXP_RXP1

F9

EXP_RXP2

F7

EXP_RXP3

B3

EXP_RXP4

D5

EXP_RXP5

G6

EXP_RXP6

H8

EXP_RXP7

J6

EXP_RXP8

K8

EXP_RXP9

L6

EXP_RXP10

P10

EXP_RXP11

M8

EXP_RXP12

N6

EXP_RXP13

P7

EXP_RXP14

R6

EXP_RXP15

C9

EXP_TXN0

A8

EXP_TXN1

C7

EXP_TXN2

A6

EXP_TXN3

C5

EXP_TXN4

D2

EXP_TXN5

F3

EXP_TXN6

G1

EXP_TXN7

H3

EXP_TXN8

J1

EXP_TXN9

K3

EXP_TXN10

L1

EXP_TXN11

M3

EXP_TXN12

N1

EXP_TXN13

P3

EXP_TXN14

R1

EXP_TXN15

C10

EXP_TXP0

A9

EXP_TXP1

C8

EXP_TXP2

A7

EXP_TXP3

C6

EXP_TXP4

C2

EXP_TXP5

E3

EXP_TXP6

F1

EXP_TXP7

G3

EXP_TXP8

H1

EXP_TXP9

J3

EXP_TXP10

K1

EXP_TXP11

L3

EXP_TXP12

M1

EXP_TXP13

N3

EXP_TXP14

P1

EXP_TXP15

K13

SDVO_CTRLDATA

J13

12

SDVO_CTRLCLK

W10

EXP_COMPI

Y10

EXP_COMPO

A16

EXP_SLR

GRANTSDALE-DDR1_BGA1210

(2/9)

PCI EXPRESS-G

DDR1

DMI

CLOCK

DAC

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

GCLKP
GCLKN

DREFCLKP
DREFCLKN

RED

GREEN

BLUE
RED#

GREEN#

BLUE#

HSYNC
VSYNC

DDC_DATA

DDC_CLK

REFSET

EXTTS#

RSTIN#

PWROK

ICH_SYNC#

DMI_RXN0

T3

DMI_RXN1

U1

DMI_RXN2

V3

DMI_RXN3

W5

DMI_RXP0

R3

DMI_RXP1

T1

DMI_RXP2

U3

DMI_RXP3

V5

DMI_TXN0

U6

DMI_TXN1

T8

DMI_TXN2

V8

DMI_TXN3

U10

DMI_TXP0

U5

DMI_TXP1

T9

DMI_TXP2

V7

DMI_TXP3

V10

CLK_PCIE_MCH

A11

CLK_PCIE_MCH#

B11

DOT_96M

M13
M12

F14
D14
H14
G14
E14
J14

E12
D12

L14
M15

A15

K16

AF7

AG7

M14

10P_0402_50V8K

R112 0_0402_5%

DOT_96M#

R113 0_0402_5%

R97 0_0402_5%

1 2

R84 0_0402_5%

1 2

R105 0_0402_5%

1 2

R101 0_0402_5%

1 2

R95 0_0402_5%

1 2

R106 0_0402_5%

1 2

R96 10K_0402_5%

1 2

R77 10K_0402_5%

1 2

R69 255_0402_1%

1 2

R111

10K_0402_5%

PLTRST#

PLTRST#

C664

DMI_RXN0 25
DMI_RXN1 25
DMI_RXN2 25
DMI_RXN3 25

DMI_RXP0 25
DMI_RXP1 25
DMI_RXP2 25
DMI_RXP3 25

DMI_TXN0 25
DMI_TXN1 25
DMI_TXN2 25
DMI_TXN3 25

DMI_TXP0 25
DMI_TXP1 25
DMI_TXP2 25
DMI_TXP3 25

CLK_PCIE_MCH 14
CLK_PCIE_MCH# 14

1 2
1 2

+DAC_2.5VS

12

PLTRST# 15,21,23,27,30,35,37

SYS_PW ROK 25,39

ICH_SYNC# 25

1

2

+1.5VS

+DAC_2.5VS

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Grantsdale(1/4)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

754Monday, August 09, 2004

E

of

1A

A

B

C

D

E

DDRA_SDQ[0..63]11,13
DDRA_SDQS[0..7]11,13

DDRA_SMA[0..13]11,13

1 1

2 2

DDRA_SBS011,13
DDRA_SBS111,13

DDRA_SWE#11,13
DDRA_SCAS#11,13
DDRA_SRAS#11,13

3 3

4 4

+2.6V

12

R148
1K_0402_1%

12

R145
1K_0402_1%

A

DDRA_SCS#011,13
DDRA_SCS#111,13

DDRA_CKE011,13
DDRA_CKE111,13

DDRA_CLK111
DDRA_CLK1#11
DDRA_CLK211
DDRA_CLK2#11

+MCH_VREF

DDRA_SDM[0..7]11,13

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13 DDRB_SMA13

DDRA_SCS#0
DDRA_SCS#1

DDRA_CKE0
DDRA_CKE1

AN7
AH16
AK29
AG34
AA33

AG1

AP7
AF17
AM30
AG35
AA34

AG2

AR7
AG17

AL29
AG33
AA35

AR24

AL24
AP23
AR23
AR29

AN22
AP22
AN21
AP21
AM21
AP19
AR20
AN16
AN18
AM15
AN23
AP15
AP13
AB33

AN28
AP26

AP31

AL34
AN29

AM34

AL35
AK34

AL33

AL12
AN11
AP11
AR11

AM24
AN25

AN2

AN3
AB34
AC33

AP25
AN26

AM2

AM3
AC35
AC34

AF2
AL1

U33

AL3

U34

AL2

U35

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]

DDRA_SMA[0..13]
DDRA_SDM[0..7]

U35C

(3/9)

SDM_A0

DDR1

SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7

SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7

RSV41
RSV42
RSV43
RSV44
RSV45
RSV46
RSV47
RSV48
RSV49
RSV50
RSV51
RSV52
RSV53

SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13

SBS_A0
SBS_A1

SWE_A#
SCAS_A#
SRAS_A#

SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#

SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3

SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#

SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#

GRANTSDALE-DDR1_BGA1210

SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47

DDR1 CHANNEL A

SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63

RSV_TP0
RSV_TP1

SM_SLEWIN0

SM_SLEWOUT0

B

SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9

SVREF0

MTYPE

DDRA_SDQ0

AE3

DDRA_SDQ1

AF3

DDRA_SDQ2

AH2

DDRA_SDQ3

AJ2

DDRA_SDQ4

AE2

DDRA_SDQ5

AE1

DDRA_SDQ6

AG3

DDRA_SDQ7

AH3

DDRA_SDQ8

AJ1

DDRA_SDQ9

AK2

DDRA_SDQ10

AN4

DDRA_SDQ11

AP4

DDRA_SDQ12

AJ3

DDRA_SDQ13

AK3

DDRA_SDQ14

AP2

DDRA_SDQ15

AP3

DDRA_SDQ16

AP5

DDRA_SDQ17

AR5

DDRA_SDQ18

AN8

DDRA_SDQ19

AP9

DDRA_SDQ20

AN5

DDRA_SDQ21

AP6

DDRA_SDQ22

AR8

DDRA_SDQ23

AN9

DDRA_SDQ24

AK16

DDRA_SDQ25

AL17

DDRA_SDQ26

AD17

DDRA_SDQ27

AF19

DDRA_SDQ28

AF16

DDRA_SDQ29

AJ17

DDRA_SDQ30

AE19

DDRA_SDQ31

AH18

DDRA_SDQ32

AH27

DDRA_SDQ33

AK27

DDRA_SDQ34

AN30

DDRA_SDQ35

AK31

DDRA_SDQ36

AL27

DDRA_SDQ37

AJ28

DDRA_SDQ38

AL30

DDRA_SDQ39

AL31

DDRA_SDQ40

AJ34

DDRA_SDQ41

AH35

DDRA_SDQ42

AG32

DDRA_SDQ43

AF34

DDRA_SDQ44

AJ33

DDRA_SDQ45

AH33

DDRA_SDQ46

AF33

DDRA_SDQ47

AE33

DDRA_SDQ48

AE35

DDRA_SDQ49

AE34

DDRA_SDQ50

Y33

DDRA_SDQ51

W34

DDRA_SDQ52

AD31

DDRA_SDQ53

AD35

DDRA_SDQ54

AA32

DDRA_SDQ55

Y35

DDRA_SDQ56

V34

DDRA_SDQ57

V33

DDRA_SDQ58

R32

DDRA_SDQ59

R34

DDRA_SDQ60

W35

DDRA_SDQ61

W33

DDRA_SDQ62

T33

DDRA_SDQ63

T35

AE16
AH15

12mil (minimum)

C167

AE7

AJ12
AK12

C15

+MCH_VREF

SM_SLEWIN0

0.1U_0402_16V4Z

1 2

SM_SLEWIN0 Width : Space = 5 : 10

1 2

R74 @1K_0402_5%

MTYPE

DDR20

DDR1

DDRB_SBS012,13
DDRB_SBS112,13

DDRB_SWE#12,13
DDRB_SCAS#12,13
DDRB_SRAS#12,13

DDRB_SCS#012,13
DDRB_SCS#112,13

DDRB_CKE012,13
DDRB_CKE112,13

DDRB_CLK112
DDRB_CLK1#12
DDRB_CLK212
DDRB_CLK2#12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

DDRB_SDQ[0..63]12,13
DDRB_SDQS[0..7]12,13

DDRB_SMA[0..13]12,13
DDRB_SDM[0..7]12,13

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDRB_SCS#0
DDRB_SCS#1

DDRB_CKE0
DDRB_CKE1

AH13
AG20
AG24
AH31
AD24

W31

AK10
AK13
AD20
AH25
AH28
AB31

W27

AP32
AR28
AN31
AP30
AN32
AP29
AP33

AH10

AL14
AF20
AG26
AH30

AM18
AP18
AN17
AR16
AR15
AN15
AP17

AL15
AP14
AN13
AN20
AR12
AM12
AD32

AM27
AR19

AR27
AN27
AP27

AP34
AN34
AN33
AM33

AN10

AM9

AP10

AR9

AH22
AG23

AL11

AJ11
AE26
AE25

AL23
AK22

AD29
AD28

AJ5
AH9

AK5

AL4

AK9
AL9

DDRB_SDQ[0..63]
DDRB_SDQS[0..7]

DDRB_SMA[0..13]
DDRB_SDM[0..7]

U35D

(4/9)

SDM_B0

DDR1

SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7

SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7

RSV54
RSV55
RSV56
RSV57
RSV58
RSV59
RSV60
RSV61
RSV62
RSV63
RSV64
RSV65
RSV66

SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13

SBS_B0
SBS_B1

SWE_B#
SCAS_B#
SRAS_B#

SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#

SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3

SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#

SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#

GRANTSDALE-DDR1_BGA1210

SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50

DDR1 CHANNEL B

SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63

RSV_TP2
RSV_TP3

SRCOMP1
SRCOMP0

SM_SLEWIN1

SM_SLEWOUT1

D

SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQ_B8
SDQ_B9

SVREF1

RSV69
RSV70

DDRB_SDQ0

AH7

DDRB_SDQ1

AJ6

DDRB_SDQ2

AL5

DDRB_SDQ3

AN6

DDRB_SDQ4

AG9

DDRB_SDQ5

AH4

DDRB_SDQ6

AM5

DDRB_SDQ7

AL6

DDRB_SDQ8

AJ7

DDRB_SDQ9

AL7

DDRB_SDQ10

AF11

DDRB_SDQ11

AE11

DDRB_SDQ12

AJ8

DDRB_SDQ13

AL8

DDRB_SDQ14

AG10

DDRB_SDQ15

AG11

DDRB_SDQ16

AE13

DDRB_SDQ17

AF13

DDRB_SDQ18

AG14

DDRB_SDQ19

AD14

DDRB_SDQ20

AD12

DDRB_SDQ21

AH12

DDRB_SDQ22

AF14

DDRB_SDQ23

AD15

DDRB_SDQ24

AD18

DDRB_SDQ25

AK19

DDRB_SDQ26

AE22

DDRB_SDQ27

AH21

DDRB_SDQ28

AL18

DDRB_SDQ29

AH19

DDRB_SDQ30

AF22

DDRB_SDQ31

AD21

DDRB_SDQ32

AF23

DDRB_SDQ33

AF25

DDRB_SDQ34

AL25

DDRB_SDQ35

AJ26

DDRB_SDQ36

AD23

DDRB_SDQ37

AF24

DDRB_SDQ38

AJ25

DDRB_SDQ39

AL26

DDRB_SDQ40

AJ29

DDRB_SDQ41

AJ31

DDRB_SDQ42

AG30

DDRB_SDQ43

AG31

DDRB_SDQ44

AK33

DDRB_SDQ45

AK32

DDRB_SDQ46

AG27

DDRB_SDQ47

AF28

DDRB_SDQ48

AE31

DDRB_SDQ49

AF27

DDRB_SDQ50

AB27

DDRB_SDQ51

AB26

DDRB_SDQ52

AE29

DDRB_SDQ53

AE27

DDRB_SDQ54

AC28

DDRB_SDQ55

AC26

DDRB_SDQ56

AA29

DDRB_SDQ57

W29

DDRB_SDQ58

U26

DDRB_SDQ59

V29

DDRB_SDQ60

Y26

DDRB_SDQ61

AA28

DDRB_SDQ62

W26

DDRB_SDQ63

V28

AN14
AK15

12mil (minimum)

+MCH_VREF

AE8

SMRCOMP_P

AG8

SMRCOMP_N

AG4
AE5
AF5

SM_SLEWIN1

AF9
AE10

C168 0.1U_0402_16V4Z

1 2

R151 80.6_0402_1%

1 2

R149 80.6_0402_1%

1 2

SMRCOMP_P & SMRCOMP_N Width : Space = 10 : 10

SM_SLEWIN1 Width : Space = 5 : 10

Compal Electronics, Inc.

Title

Grantsdale-DDR(2/4)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

Part Number Change to SD034806A00

+2.6V

of

854Monday, August 09, 2004

E

1A

A

Decoupling Reference Document:
Grantsdale Chipset Platform Design guide Rev1.0

A2
A34
A35
AA12
AB12
AC23
AC24
AD30
AG6
AH24
AJ14
AL28
AN19
AP1
AP35
AR1
AR2
AR34
AR35
B1
B35
C16
E16
F12
F24
G12
H12
H15
H17
J12
K12
L12
L19
N12
N22
N23
N24
P12
P23
P24
P30
R12
R24
T12
U12
V12
W12
Y12

(14652)Page287
VCC : 10uF *2

470U_D2_2.5VM

SANYO H=1.8,ESR=15m

1 1

U35E

RSV/NC
(5/9)

AA30
AA31
AB29
AC30
AC12
AC13
AC14
AC15
AC16
AC17
AC18

2 2

AC19
AC20
AC21
AC22

Y28
AJ18
AJ20
AJ21
AJ23
AJ24
AK18
AK21
AK24
AL20
AL21

B15
C14

F15
G16
K15
M16
R30
R31
R35
U30
V30
V31
V32
Y30

3 3

DDR1

RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
RSV10
RSV11
RSV12
RSV13
RSV14
RSV15
RSV16
RSV17
RSV18
RSV19
RSV20
RSV21
RSV22
RSV23
RSV24
RSV25
RSV26
RSV27
RSV28
RSV29
RSV30
RSV31
RSV32
RSV33
RSV34
RSV35
RSV36
RSV37
RSV38
RSV39
RSV40

GRANTSDALE-DDR1_BGA1210

Decoupling Reference Document:
Grantsdale Chipset Platform Design guide Rev1.0
(14652)Page287

NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

VTT : 10uF *3

R398
0_0805_5%

1 2

+1.5VS

(KC FBM-L11-201209-221LMAT_0805)

4 4

+1.5VS

(KC FBM-L11-201209-221LMAT_0805)

@470U_D2_2.5VM

SANYO H=1.8,ESR=15m

R53
0_0805_5%

1 2

@470U_D2_2.5VM

SANYO H=1.8,ESR=15m

A

C443

C63

+VCCA_SMPLL

1

+

2

+VCCA_HPLL

1

+

2

1

C75

0.1U_0402_16V4Z

2

1

C71

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

B

U35F

+1.5VS +1.5VS

C12010U_0805_10V4Z

12

C53410U_0805_10V4Z

12

C10710U_0805_10V4Z

12

C1210.47U_0603_16V4Z

12

C436

12

+

C6590.1U_0402_16V4Z

12

C6600.1U_0402_16V4Z

12

+V_FSB_VTT

C45410U_0805_10V4Z

12

C45510U_0805_10V4Z

12

C45610U_0805_10V4Z

12

C780.1U_0402_16V4Z

12

C800.1U_0402_16V4Z

12

C760.1U_0402_16V4Z

12

R395
@10K_0402_5%

1 2

+1.5VS

1

C661

2

B

AA13
AA14
AA16
AA18
AA20
AA21
AA22
AA23
AA24

AB1
AB10
AB11
AB13
AB14
AB15
AB16
AB17
AB18
AB19

AB2
AB20
AB21
AB22
AB23
AB24

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AC1

AC10
AC11

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

A19

A20

A21

A22

B19

B20

B21

B22

C19

C20

C21

C22

D19

D20

D21

D22

E19

E20

E21

E22

F20

F21

F22

G21

G22

H22

C435

@1U_0603_10V4Z

GRANTSDALE-DDR1_BGA1210

+3VALW

@10K_0402_5%

1

2

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26

R26

2

B

E

VCC

(6/9)

DDR1

1 2

R25

12

@10K_0402_5%

C

Q38

3 1

@MMBT3904_SOT23

AD1

VCC_44

AD10

VCC_45

AD2

VCC_46

AD3

VCC_47

AD4

VCC_48

AD5

VCC_49

AD6

VCC_50

AD7

VCC_51

AD8

VCC_52

AD9

VCC_53

L10

VCC_54

N13

VCC_55

N14

VCC_56

N15

VCC_57

N16

VCC_58

N18

VCC_59

N20

VCC_60

N21

VCC_61

P13

VCC_62

P14

VCC_63

P15

VCC_64

P17

VCC_65

P19

VCC_66

P21

VCC_67

P22

VCC_68

R13

VCC_69

R14

VCC_70

R15

VCC_71

R16

VCC_72

R18

VCC_73

R20

VCC_74

R22

VCC_75

R23

VCC_76

T13

VCC_77

T14

VCC_78

T15

VCC_79

T16

VCC_80

T17

VCC_81

T19

VCC_82

T20

VCC_83

T21

VCC_84

T23

VCC_85

T24

VCC_86

U13

VCC_87

U14

VCC_88

U16

VCC_89

U18

VCC_90

U20

VCC_91

U22

VCC_92

U24

VCC_93

V13

VCC_94

V14

VCC_95

V15

VCC_96

V17

VCC_97

V19

VCC_98

V21

VCC_99

V23

VCC_100

V24

VCC_101

W13

VCC_102

W14

VCC_103

W16

VCC_104

W18

VCC_105

W20

VCC_106

W22

VCC_107

W24

VCC_108

Y13

VCC_109

Y14

VCC_110

Y15

VCC_111

Y16

VCC_112

Y17

VCC_113

Y19

VCC_114

Y20

VCC_115

Y21

VCC_116

Y23

VCC_117

Y24

VCC_118

C29

@4.7U_0805_10V4Z

C

Q39

2

B

E

@MMBT3904_SOT23

3 1

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3VS

12

2004/0602

C

R396
0_0805_5%

1 2

+1.5VS

(KC FBM-L11-201209-221LMAT_0805)

R48
0_0805_5%

1 2

+1.5VS

(KC FBM-L11-201209-221LMAT_0805)

2004/0602

1 2

R533 0_0603_5%

Vout=1.242*(R2/R1+1)

+DAC_2.5VS

U8

1

IN

5

OUT

3

EN

4

ADJ

2

GND

@MIC5205BM5_SOT23-5

C34

@470P_0402_50V7K

220U_D2_4VM

220U_D2_4VM

+DAC_2.5VS+2.6VS

R1

1

R2

2

D

Decoupling Reference Document:
Grantsdale Chipset Platform Design guide Rev1.0
(14652)Page287

VCCSM : 2.2uF *6

+2.6V

C2222.2U_0805_10V6K

12

NEAR AK35

C2232.2U_0805_10V6K

12

NEAR AN35

C2212.2U_0805_10V6K

12

C2202.2U_0805_10V6K

12

C2192.2U_0805_10V6K

12

C2182.2U_0805_10V6K

12

NEAR AR31&AR33

C65

D

+VCC_EXP_1.5VS

12

+

12

12

1

1

+

C67

2

2

+1.5VS

+VCC_EXP_1.5VS

C137220U_D2_4VM

C51710U_0805_10V4Z

C52310U_0805_10V4Z

(1.4A)

+DAC_2.5VS

+VCCA_HPLL
+VCCA_SMPLL
+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_EXPPLL

1

C79

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

R397
0_0805_5%

1 2

(KC FBM-L11-201209-221LMAT_0805)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

L34

KC FBM-L11-201209-221LMAT_0805

1 2

+1.5VS

+VCCA_DPLLA

1

+

C453

2

+VCCA_DPLLB

1

+

C64

2

+DAC_2.5VS

@100U_D2_6.3VM

C35

10U_0805_10V4Z

1 2

12

R34
@10K_0402_1%

12

R43
@10.2K_0402_1%

NEAR AR21, AR17, AR13

1

C68
@0.1U_0402_16V4Z

2

1

C72
@0.1U_0402_16V4Z

2

U35G

AK35
AM10
AM11
AM13
AM14
AM16
AM17
AM19
AM20
AM22
AM23
AM25
AM26
AM28
AM32
AN35
AP12
AP16
AP20
AP24
AP28
AR10
AR14
AR18
AR22
AR26
AR31
AR33

W1
W2
W3
W4
W6
W7
W8
W9

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9

A13

A17
B17
A12
B13
A14

D13
E13

F13

+VCCA_EXPPLL_R

VCC/GND

VCCSM1

(7/9)

VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28

VCC_EXP1
VCC_EXP2
VCC_EXP3
VCC_EXP4
VCC_EXP5
VCC_EXP6
VCC_EXP7
VCC_EXP8
VCC_EXP9
VCC_EXP10
VCC_EXP11
VCC_EXP12
VCC_EXP13
VCC_EXP14
VCC_EXP15
VCC_EXP16
VCC_EXP17

VCC2

VCCA_HPLL
VCCA_SMPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL

VCCA_DAC1
VCCA_DAC2

VSSA_DAC

GRANTSDALE-DDR1_BGA1210

10U_0805_10V4Z

Grantsdale(3/4)

ECQ60 LA-2271

DDR1

R400

0.5_0805_1%

1 2

C457

E

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73

+VCCA_EXPPLL

1

2

E

A10
A18
A26
A3
A30
A33
A5
AA1
AA10
AA11
AA15
AA17
AA19
AA2
AA25
AA26
AA27
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AB25
AB28
AB30
AB32
AB35
AC25
AC27
AC29
AC31
AC32
AD11
AD13
AD16
AD19
AD22
AD25
AD26
AD27
AD34
AE12
AE14
AE15
AE17
AE18
AE20
AE21
AE23
AE24
AE28
AE30
AE32
AE4
AE6
AE9
AF1
AF10
AF12
AF15
AF18
AF21
AF26
AF29
AF30
AF31
AF32
AF35
AF4
AF6
AF8

1

C66

0.1U_0402_16V4Z

2

954Monday, August 09, 2004

1A

of

5

4

3

2

1

U35H

D D

C C

B B

A A

AG12

VSS74

AG13

VSS75

AG15
AG16
AG18
AG19
AG21
AG22
AG25
AG28
AG29

AG5

AH1
AH11
AH14
AH17
AH20
AH23
AH26
AH29
AH32
AH34

AH5

AH6

AH8

AJ10
AJ13
AJ15
AJ16
AJ19
AJ22
AJ27
AJ30
AJ32
AJ35

AJ4
AJ9

AK1
AK11
AK14
AK17
AK20
AK23
AK25
AK26
AK28
AK30

AK4

AK6

AK7

AK8

AL10
AL13
AL16
AL19
AL22

AL32
AM29
AM31

AM4
AM6
AM7
AM8
AN1

AP8
AR13
AR17
AR21
AR25

AR3

AR30

AR6

B10

B12

B14

B16

B18

B24

B28

B2

B5
B6
B7
B8

(8/9)

VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167

GRANTSDALE-DDR1_BGA1210

GND

DDR1

VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250

B9
C1
C11
C13
C17
C18
C23
C3
C35
C4
D10
D11
D15
D16
D18
D23
D25
D26
D28
D3
D30
D31
D32
D4
D6
D7
D8
D9
E1
E10
E17
E18
E2
E23
E26
E29
E4
E6
E8
F10
F16
F18
F2
F23
F25
F29
F30
F32
F35
F4
F5
F6
F8
G10
G11
G13
G15
G17
G19
G2
G20
G23
G26
G27
G28
G4
G7
G8
G9
H10
H13
H2
H21
H24
H25
H27
H30
H32
H34
H4
H5
H6
H9

U35I

J10

VSS251

J15

VSS252

J16
J17
J18

J2
J20
J23
J30

J4

J7

J8

J9

K10
K11
K14

K2
K20
K24
K26
K28
K31
K32
K35

K4

K5

K6

K9

L11
L13
L15
L16
L17
L18

L2

L20
L21
L22
L24
L27
L30
L32

L4

L7

L8

L9

M10
M11
M17

M2
M20
M24
M25
M27
M29
M34

M4

M5

M6

M9

N10
N11
N17
N19

N2
N25
N28
N30
N32

N4

N7

N8

N9
P11
P16
P18

P2
P20
P25
P27
P29
P31

GRANTSDALE-DDR1_BGA1210

VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333

(9/9)

GND

DDR1

VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373
VSS374
VSS375
VSS376
VSS377
VSS378
VSS379
VSS380
VSS381
VSS382
VSS383
VSS384
VSS385
VSS386
VSS387
VSS388
VSS389
VSS390
VSS391
VSS392
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS414

P32
P35
P4
P5
P6
P9
R11
R17
R19
R2
R21
R25
R26
R27
R4
R7
R8
R9
T10
T11
T18
T2
T22
T25
T28
T30
T32
T34
T4
T5
T6
T7
U11
U15
U17
U19
U2
U21
U23
U25
U27
U29
U31
U32
U4
U7
U8
U9
V1
V11
V16
V18
V2
V20
V22
V25
V26
V27
V35
V4
V6
V9
W11
W15
W17
W19
W21
W23
W25
W28
W30
W32
Y11
Y18
Y22
Y25
Y27
Y29
Y31
Y32
Y34

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Grantsdale-GND(4/4)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

10 54Monday, August 09, 2004

1

of

1A

5

JP27

1

VREF

3

DDRA_SDQ0
DDRA_SDQ4

DDRA_SDQS0
DDRA_SDQ2

DDRA_SDQ3 DDRA_SDQ7

D D

DDRA_CLK18
DDRA_CLK1#8

C C

DDRA_CKE18,13

DDRA_SBS08,13
DDRA_SWE#8,13
DDRA_SCS#08,13

B B

A A

CLK_SDATA12,14
CLK_SCLK12,14

5

DDRA_SDQ8
DDRA_SDQ12

DDRA_SDQS1
DDRA_SDQ10

DDRA_SDQ16
DDRA_SDQ20

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ22
DDRA_SDQ28

DDRA_SDQ24
DDRA_SDQS3

DDRA_SDQ25
DDRA_SDQ29

DDRA_CKE1
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
DDRA_SMA13

DDRA_SDQ32
DDRA_SDQ37 DDRA_SDQ36

DDRA_SDQS4
DDRA_SDQ35

DDRA_SDQ38
DDRA_SDQ44

DDRA_SDQ40
DDRA_SDQS5

DDRA_SDQ42
DDRA_SDQ46

DDRA_SDQ48
DDRA_SDQ53 DDRA_SDQ52

DDRA_SDQS6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ61

DDRA_SDQ56
DDRA_SDQS7

DDRA_SDQ62
DDRA_SDQ58

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP_1565918-1

4

DU/RESET#

DU/BA2

H = 5.2mm

REVERSE
SO-DIMM 0

4

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1
VSS

DQ14
DQ15

VDD
VDD
VSS
VSS

DQ20
DQ21

VDD
DM2

DQ22

VSS

DQ23
DQ28

VDD

DQ29

DM3
VSS

DQ30
DQ31

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

CKE0

A11
VSS

VDD

BA1

RAS#
CAS#

S1#
VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

CK1#

CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7
VSS

DQ62
DQ63

VDD

SA0

SA1

SA2

+2.6V+2.6V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DDRA_SDQ5
DDRA_SDQ1

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ9
DDRA_SDQ13

DDRA_SDM1
DDRA_SDQ15

DDRA_SDQ11DDRA_SDQ14

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ19

DDRA_SDQ23
DDRA_SDQ26

DDRA_SDQ30
DDRA_SDM3

DDRA_SDQ31
DDRA_SDQ27

DDRA_CKE0
DDRA_SMA11

DDRA_SMA8
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SDQ33

DDRA_SDM4
DDRA_SDQ39

DDRA_SDQ34
DDRA_SDQ45

DDRA_SDQ41
DDRA_SDM5

DDRA_SDQ43
DDRA_SDQ47

DDRA_SDQ49

DDRA_SDM6
DDRA_SDQ50

DDRA_SDQ51
DDRA_SDQ60

DDRA_SDQ57
DDRA_SDM7

DDRA_SDQ59
DDRA_SDQ63

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDRA_VREF trace width of
12mils and space 12mils(min)

DDRA_VREF

1

C297

0.1U_0402_16V4Z

2

Close to SO-DIMM

1

+

C263

@470U_D_4VM

DDRA_CKE0 8,13

DDRA_SBS1 8,13
DDRA_SRAS# 8,13
DDRA_SCAS# 8,13
DDRA_SCS#1 8,13

DDRA_CLK2# 8
DDRA_CLK2 8

3

2

+2.6V

+2.6V

1

C277
22U_1206_10V4Z

2

+2.6V

1

C278

0.1U_0402_16V4Z

2

12

R243
1K_0402_1%

12

R244
1K_0402_1%

System Memory Decoupling caps

1

C294

0.1U_0402_16V4Z

2

1

C279

0.1U_0402_16V4Z

2

Decoupling Reference Document:
Grantsdale Customer Schematic R1.0 page24
Channel A(two DIMMs) requirement 22uF*1 ; 0.1uF*22

2

DDRA_SDQ[0..63]8,13
DDRA_SDQS[0..7]8,13
DDRA_SMA[0..13]8,13
DDRA_SDM[0..7]8,13

1

C293

0.1U_0402_16V4Z

2

1

C280

0.1U_0402_16V4Z

2

2

1

C292

0.1U_0402_16V4Z

2

1

C281

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Title

DDR SO-DIMM 0 (CHANNEL A)

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..13]
DDRA_SDM[0..7]

1

C291

0.1U_0402_16V4Z

2

1

C282

0.1U_0402_16V4Z

2

1

1

C290

0.1U_0402_16V4Z

2

1

1

C289

0.1U_0402_16V4Z

2

11 54Monday, August 09, 2004

of

1A

5

4

3

2

1

+2.6V

JP25

1

VREF

3

DDRB_SDQ4
DDRB_SDQ0

DDRB_SDQS0
DDRB_SDQ7

D D

DDRB_CLK18
DDRB_CLK1#8

C C

DDRB_CKE18,13

DDRB_SBS08,13
DDRB_SWE#8,13
DDRB_SCS#08,13

B B

A A

CLK_SDATA11,14
CLK_SCLK11,14

5

DDRB_SDQ2 DDRB_SDQ3
DDRB_SDQ8

DDRB_SDQ9
DDRB_SDQS1

DDRB_SDQ11
DDRB_SDQ14

DDRB_SDQ17
DDRB_SDQ21

DDRB_SDQS2
DDRB_SDQ16

DDRB_SDQ20
DDRB_SDQ28

DDRB_SDQ24
DDRB_SDQS3

DDRB_SDQ27
DDRB_SDQ31 DDRB_SDQ26

DDRB_CKE1
DDRB_SMA12

DDRB_SMA9
DDRB_SMA7

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
DDRB_SMA13

DDRB_SDQ34
DDRB_SDQ39

DDRB_SDQS4
DDRB_SDQ32

DDRB_SDQ37
DDRB_SDQ45

DDRB_SDQ40 DDRB_SDQ41
DDRB_SDQS5

DDRB_SDQ42
DDRB_SDQ43

DDRB_SDQ48
DDRB_SDQ52

DDRB_SDQS6
DDRB_SDQ55

DDRB_SDQ51

DDRB_SDQS7
DDRB_SDQ59

DDRB_SDQ57

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

TYCO_1470804-2

REVERSE SO-DIM M 2

DU/RESET#

H= 9.2mm

4

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1
VSS

DQ14
DQ15

VDD
VDD
VSS
VSS

DQ20
DQ21

VDD
DM2

DQ22

VSS

DQ23
DQ28

VDD

DQ29

DM3
VSS

DQ30
DQ31

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

CKE0

DU/BA2

A11
VSS

VDD

BA1

RAS#
CAS#

S1#
VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD

CK1#

CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7
VSS

DQ62
DQ63

VDD

SA0

SA1

SA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DDRB_VREF trace width of
12mils and space 12mils(min)

DDRB_SDQ5
DDRB_SDQ1

DDRB_SDM0
DDRB_SDQ6

DDRB_SDQ12
DDRB_SDQ13

DDRB_SDM1
DDRB_SDQ10

DDRB_SDQ15

DDRB_SDQ22
DDRB_SDQ18

DDRB_SDM2
DDRB_SDQ19

DDRB_SDQ23
DDRB_SDQ25

DDRB_SDQ29
DDRB_SDM3

DDRB_SDQ30

DDRB_CKE0
DDRB_SMA11

DDRB_SMA8
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

DDRB_SDQ38
DDRB_SDQ35

DDRB_SDM4
DDRB_SDQ33

DDRB_SDQ36
DDRB_SDQ44

DDRB_SDM5
DDRB_SDQ46

DDRB_SDQ47

DDRB_SDQ49
DDRB_SDQ53

DDRB_SDM6
DDRB_SDQ54

DDRB_SDQ50
DDRB_SDQ60DDRB_SDQ56

DDRB_SDQ62DDRB_SDQ61
DDRB_SDM7

DDRB_SDQ63
DDRB_SDQ58

12

R424 10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDRB_VREF

1

C240

0.1U_0402_16V4Z

2

DDRB_CKE0 8,13

DDRB_SBS1 8,13
DDRB_SRAS# 8,13
DDRB_SCAS# 8,13
DDRB_SCS#1 8,13

DDRB_CLK2# 8
DDRB_CLK2 8

+3VS

3

+2.6V

1

2

+2.6V

1

2

+2.6V+2.6V

12

12

C260

0.1U_0402_16V4Z

C564

0.1U_0402_16V4Z

DDRB_SDQ[0..63]8,13

R225
1K_0402_1%

R220
1K_0402_1%

DDRB_SDQS[0..7]8,13
DDRB_SMA[0..13]8,13
DDRB_SDM[0..7]8,13

System Memory Decoupling caps

2

1

C261

0.1U_0402_16V4Z

2

1

C262

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

1

C562

0.1U_0402_16V4Z

2

1

C563

0.1U_0402_16V4Z

2

1

C259

0.1U_0402_16V4Z

2

1

C565

0.1U_0402_16V4Z

2

Decoupling Reference Document:
Grantsdale Customer Schematic R1.0 page28
Channel B(two DIMMs) requirement 0.1uF*21

DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..13]
DDRB_SDM[0..7]

1

C559

0.1U_0402_16V4Z

2

1

C560

0.1U_0402_16V4Z

2

DDR SO-DIMM 1 (CHANNEL B)

ECQ60 LA-2271

1

1

C561

0.1U_0402_16V4Z

2

12 54Monday, August 09, 2004

of

1A

5

Channel A(DIMM0) Termination resistors & Decoupling caps Channel B(DIMM1) Termination resistors & Decoupling caps

+1.3VS +1.3VS

DDRA_SDQ5
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ6

D D

DDRA_SDQ2
DDRA_SDQS0
DDRA_SDQ4
DDRA_SDQ0

DDRA_SDQ7
DDRA_SDQ9
DDRA_SDQ13
DDRA_SDM1

DDRA_SDQS1
DDRA_SDQ12
DDRA_SDQ8
DDRA_SDQ3

C C

DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQ14
DDRA_SDQ10

DDRA_SDQ15
DDRA_SDQ11
DDRA_SDQ17
DDRA_SDQ21

DDRA_SDQ28
DDRA_SDQ22
DDRA_SDQ18
DDRA_SDQS2

B B

DDRA_SDM2
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ26

DDRA_SDQ29
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ24

DDRA_SDQ30
DDRA_SDM3
DDRA_SDQ31

A A

DDRA_SDQ27

RP39

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP43

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP38

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP44

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP45

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP37

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP46

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP36

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP47

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP35

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

5

RP50

18
27
36
45

56_1206_8P4R_5%

RP32

18
27
36
45

56_1206_8P4R_5%

RP51

18
27
36
45

56_1206_8P4R_5%

RP31

18
27
36
45

56_1206_8P4R_5%

RP52

18
27
36
45

56_1206_8P4R_5%

RP30

18
27
36
45

56_1206_8P4R_5%

RP53

18
27
36
45

56_1206_8P4R_5%

RP29

18
27
36
45

56_1206_8P4R_5%

RP54

18
27
36
45

56_1206_8P4R_5%

RP28

18
27
36
45

56_1206_8P4R_5%

DDRA_SDQ35
DDRA_SDQS4
DDRA_SDQ37
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQ36
DDRA_SDM4
DDRA_SDQ39

DDRA_SDQS5
DDRA_SDQ40
DDRA_SDQ44
DDRA_SDQ38

DDRA_SDQ34
DDRA_SDQ45
DDRA_SDQ41
DDRA_SDM5

DDRA_SDQ53
DDRA_SDQ48
DDRA_SDQ46
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ47
DDRA_SDQ49
DDRA_SDQ52

DDRA_SDQ61
DDRA_SDQ55
DDRA_SDQ54
DDRA_SDQS6

DDRA_SDM6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ60

DDRA_SDQ58
DDRA_SDQ62
DDRA_SDQS7
DDRA_SDQ56

DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ59
DDRA_SDQ63

RP34

47_1206_8P4R_5%

RP48

47_1206_8P4R_5%

RP33

47_1206_8P4R_5%

RP49

47_1206_8P4R_5%

1 2

R426 47_0402_5%

1 2

R250 47_0402_5%

1 2

R249 47_0402_5%

1 2

R251 56_0402_5%

1 2

R427 56_0402_5%

1 2

R425 56_0402_5%

1 2

R236 56_0402_5%

+1.3VS

+1.3VS

+1.3VS

+1.3VS

4

DDRA_SMA11

18

DDRA_SMA8

27

DDRA_SMA12

36

DDRA_SMA9

45

DDRA_SMA1

18

DDRA_SMA3

27

DDRA_SMA5

36

DDRA_SMA7

45

DDRA_SMA6

18

DDRA_SMA4

27

DDRA_SMA2

36

DDRA_SMA0

45

DDRA_SBS1

18

DDRA_SWE#

27

DDRA_SBS0

36

DDRA_SMA10

45

DDRA_SMA13

DDRA_SRAS#

DDRA_SCAS#

DDRA_CKE0

DDRA_CKE1

DDRA_SCS#0

DDRA_SCS#1

1

C576

0.1U_0402_16V4Z

2

1

C571

0.1U_0402_16V4Z

2

1

C306

0.1U_0402_16V4Z

2

1

C313

4.7U_0805_10V4Z

2

Decoupling Re f e r e n c e Document:
Grantsdale Customer Schematic R1.0 page24
Channel A(two DIMMs) requirement 4.7u*3 ; 0.1uF*26

4

DDRA_SDQ[0..63]8,11
DDRA_SDQS[0..7]8,11
DDRA_SMA[0..13]8,11
DDRA_SDM[0..7]8,11

DDRA_SBS1 8,11

DDRA_SRAS# 8,11

DDRA_SCAS# 8,11

1

C575

0.1U_0402_16V4Z

2

1

C574

0.1U_0402_16V4Z

2

1

C309

0.1U_0402_16V4Z

2

1

C311

4.7U_0805_10V4Z

2

DDRA_SWE# 8,11
DDRA_SBS0 8,11

DDRA_CKE0 8,11

DDRA_CKE1 8,11

DDRA_SCS#0 8,11

DDRA_SCS#1 8,11

1

C305

0.1U_0402_16V4Z

2

1

C573

0.1U_0402_16V4Z

2

1

C308

0.1U_0402_16V4Z

2

1

C304

0.1U_0402_16V4Z

2

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..13]
DDRA_SDM[0..7]

1

C570

0.1U_0402_16V4Z

2

1

C572

0.1U_0402_16V4Z

2

1

C307

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.3VS +1.3VS

DDRB_SDQ6
DDRB_SDM0
DDRB_SDQ1
DDRB_SDQ5

DDRB_SDQ4
DDRB_SDQ0
DDRB_SDQS0
DDRB_SDQ7

DDRB_SDM1
DDRB_SDQ13
DDRB_SDQ12
DDRB_SDQ3

DDRB_SDQ2
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1

DDRB_SDQ11
DDRB_SDQ14
DDRB_SDQ17
DDRB_SDQ21

DDRB_SDQ18
DDRB_SDQ22
DDRB_SDQ15
DDRB_SDQ10

DDRB_SDQS2
DDRB_SDQ16
DDRB_SDQ20

3

DDRB_SDQ28

DDRB_SDQ25
DDRB_SDQ23
DDRB_SDQ19
DDRB_SDM2

DDRB_SDQ24
DDRB_SDQS3
DDRB_SDQ27
DDRB_SDQ31

DDRB_SDQ26
DDRB_SDQ30
DDRB_SDM3
DDRB_SDQ29

RP15

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP27

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP14

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP26

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP25

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP13

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP24

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP12

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP23

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

RP11

1 8
2 7
3 6
4 5

56_1206_8P4R_5%

Decoupling Re f e r e n c e Document:
Grantsdale Customer Schematic R1.0 page28
Channel B(two D I MMs) requirement 4.7u*3 ; 0.1uF*28

RP22

56_1206_8P4R_5%

RP8

56_1206_8P4R_5%

RP21

56_1206_8P4R_5%

RP7

56_1206_8P4R_5%

RP20

56_1206_8P4R_5%

RP6

56_1206_8P4R_5%

RP19

56_1206_8P4R_5%

RP5

56_1206_8P4R_5%

RP18

56_1206_8P4R_5%

RP4

56_1206_8P4R_5%

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

2

DDRB_SDQ34
DDRB_SDQ39
DDRB_SDQS4
DDRB_SDQ32

DDRB_SDQ33
DDRB_SDM4
DDRB_SDQ35
DDRB_SDQ38

DDRB_SDQ37
DDRB_SDQ45
DDRB_SDQ40
DDRB_SDQS5

DDRB_SDM5
DDRB_SDQ41
DDRB_SDQ44
DDRB_SDQ36

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ52

DDRB_SDQ53
DDRB_SDQ49
DDRB_SDQ47
DDRB_SDQ46

DDRB_SDQS6
DDRB_SDQ55
DDRB_SDQ51
DDRB_SDQ56

DDRB_SDQ60
DDRB_SDQ50
DDRB_SDQ54
DDRB_SDM6

DDRB_SDQ61
DDRB_SDQS7
DDRB_SDQ59
DDRB_SDQ57

DDRB_SDQ58
DDRB_SDQ63

DDRB_SDM7

DDRB_SDQ62

2

1

RP10

DDRB_SMA8

18

DDRB_SMA11

27

DDRB_SMA9

36

DDRB_SMA12

45

47_1206_8P4R_5%

RP17

DDRB_SMA7

18

DDRB_SMA5

27

DDRB_SMA3

36

DDRB_SMA1

45

47_1206_8P4R_5%

RP9

DDRB_SMA0

18

DDRB_SMA2

27

DDRB_SMA4

36

DDRB_SMA6

45

47_1206_8P4R_5%

RP16

DDRB_SBS1

18

DDRB_SMA10

27

DDRB_SBS0

36

DDRB_SWE#

45

47_1206_8P4R_5%

1 2

R232 47_0402_5%

1 2

R224 47_0402_5%

1 2

R223 47_0402_5%

1 2

R234 56_0402_5%

1 2

R221 56_0402_5%

1 2

R233 56_0402_5%

1 2

R222 56_0402_5%

+1.3VS

+1.3VS

+1.3VS

+1.3VS

DDRB_SMA13

DDRB_SRAS#
DDRB_SCAS#

DDRB_CKE1

DDRB_CKE0

DDRB_SCS#0

DDRB_SCS#1

1

C236

0.1U_0402_16V4Z

2

1

C243

0.1U_0402_16V4Z

2

1

C266

0.1U_0402_16V4Z

2

1

C237

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

Date: Sheet of

1

C239

0.1U_0402_16V4Z

2

1

C242

0.1U_0402_16V4Z

2

1

C267

0.1U_0402_16V4Z

2

1

C235

4.7U_0805_10V4Z

2

Compal Electronics, Inc.

DDR Termination & Decoupling

Custom

ECQ60 LA-2271

DDRB_SDQ[0..63]8,12
DDRB_SDQS[0..7]8,12
DDRB_SMA[0..13]8,12
DDRB_SDM[0..7]8,12

DDRB_SBS1 8,12
DDRB_SBS0 8,12

DDRB_SWE# 8,12

DDRB_SRAS# 8,12
DDRB_SCAS# 8,12

DDRB_CKE1 8,12

DDRB_CKE0 8,12

DDRB_SCS#0 8,12

DDRB_SCS#1 8,12

1

C238

0.1U_0402_16V4Z

2

1

C245

0.1U_0402_16V4Z

2

1

C268

0.1U_0402_16V4Z

2

1

C270

0.1U_0402_16V4Z

2

1

DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..13]
DDRB_SDM[0..7]

1

C244

0.1U_0402_16V4Z

2

1

C272

0.1U_0402_16V4Z

2

1

C269

0.1U_0402_16V4Z

2

1

C271

0.1U_0402_16V4Z

2

13 54Monday, August 09, 2004

1A

A

+3VS

4.7K_0402_5%

D

ICH_SMBDATA25

1 1

ICH_SMBCLK25

2 2

3 3

4 4

0

0

0

0

0

*

1

0

1

1

0

1

0

1

1

1

1

1 3

Q28

2N7002_SOT23

+3VS

2N7002_SOT23

2
2

Q29

1 3

D

FS_AFS_BFS_C

CPU SRC PCI REF USB DOT

0

266

1

133

0

200

1

166

0

333

1

100

0

400

1

RESERVED

A

12

12

R347

R348

4.7K_0402_5%

S

CLK_SDATA

G

G

CLK_SCLK

S

100

33.33

100

33.33

100

33.33

100

33.33

100

33.33

100

33.33

100

33.33

+CPU_CORE

+V_FSB_VTT

CLK_SDATA 11,12

CLK_SCLK 11,12

+CLK_VDD48 +CLK_VDDREF

14.318

14.318

14.318

14.318

14.318

14.318

14.318

14.318

CLK_14M_CODEC41

1

1

C356

2

2

4.7U_0805_10V4Z

48
48
48
48
48
48
48
48

1 2

R295 220_0402_5%

1 2

R294 @220_0402_5%

CLK_ICH_48M25

CLK_ICH_14M25
CLK_14M_SIO35

CLK_PCI_139430
CLK_PCI_LAN31
CLK_PCI_PCM28,38
CLK_PCI_MINI33
CLK_PCI_SIO35
CLK_PCI_LPC37

CLK_PCI_ICH23

C598

0.047U_0402_16V7K

96
96
96
96
96
96
96
96

+3VS

B

1 2

L26
KC FBM-L11-201209-221LMAT_0805

1 2

L27
KC FBM-L11-201209-221LMAT_0805

1

C601

2

0.047U_0402_16V7K

C364

33P_0402_50V8J

12

C362

33P_0402_50V8J

12

CPU_CLKSEL05,7
CPU_CLKSEL15,7
CPU_CLKSEL25,7

1 2

R293
10K_0402_5%

C

Q23

2

B

MMBT3904_SOT23

E

3 1

R300 475_0402_1%

1 2

R315 33_0402_5%

1 2

R324 12_0402_5%

1 2

R328 12_0402_5%

1 2

R333 12_0402_5%

1 2

R325 33_0402_5%
R329 33_0402_5%
R334 33_0402_5%
R332 33_0402_5%
R331 33_0402_5%
R330 33_0402_5%

R320 33_0402_5%

+CLK_VDD2

12

R321
10K_0402_5%

ITP_EN

12

R326
@10K_0402_5%

B

+CLK_VDD2

+CLK_VDD2

R459
1_0402_5%

1 2

R456

2.2_0402_5%

1 2

CK_XTAL_IN

12

Y3

14.31818MHz_20P_1BX14318BE1A

CK_XTAL_OUT

12
12
12
12
12
12

12

C

+CLK_VDD1+3VS

+CLK_VDD1

21
28
34

1
7

+CLK_VDDREF

+CLK_VDD48

CLK_PWRGD#

CLK_SCLK
CLK_SDATA

CLK_IREF

ICH_48M

ICH_14M

PCI_1394
PCI_LAN
PCI_PCM
PCI_MINI
PCI_SIO
PCI_LPC

PCI_ICH
ITP_EN

42
48

11

50

49

18
16
53

17

46
47

39

12

52

5
4

3
56
55
54

10

9

8

13
29

2
45
51

6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C365
10U_0805_10V4Z

2

2

C368
10U_0805_10V4Z

1

1 2

U19

VDDSRC_0
VDDSRC_1
VDDSRC_2

VDDPCI_0
VDDPCI_1

VDDCPU
VDDREF

VDD48

X1

X2

FS_A
FS_B/TEST_MODE
FS_C/TEST_SEL

VTT_PWRGD#/PD

SCLK
SDATA

IREF

USB_48MHz

REFOUT

PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

PCICLK_F2
PCICLK_F1
PCICLK_F0/ITP_EN

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5

ICS954101DG_TSSOP56

C

1

C582

0.047U_0402_16V7K

2

1

C606

0.047U_0402_16V7K

2

R434

2.2_0402_5%

CPUCLKT2_ITP/SRCCLKT_7

CPUCLKC2_ITP/SRCCLKC_7

+CLK_VDDA

VDDA

GNDA

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

SRCCLKT6

SRCCLKC6

SRCCLKT5

SRCCLKC5

SRCCLKT4_SATA

SRCCLKC4_SATA

SRCCLKT3

SRCCLKC3

SRCCLKT2

SRCCLKC2

SRCCLKT1

SRCCLKC1

DOTT_96MHz

DOTC_96MHz

1

C581

0.047U_0402_16V7K

2

1

C614

0.047U_0402_16V7K

2

37

38

41

40

44

43

36

35

33

32

31

30

26

27

24

25

22

23

19

CLK_SRC1#

20

14

15

1

C337

2

R309 33_0402_5%

R305 33_0402_5%

R319 33_0402_5%

R314 33_0402_5%

R285 33_0402_5%

R277 33_0402_5%

R266 33_0402_5%

R259 33_0402_5%

R271 33_0402_5%

R262 33_0402_5%

R287 33_0402_5%

R282 33_0402_5%

R297 33_0402_5%

R290 33_0402_5%

R306 @33_0402_5%

R302 @33_0402_5%

D

1

C577

0.047U_0402_16V7K

2

1

2

4.7U_0805_10V4Z

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

D

1

C590

0.047U_0402_16V7K

2

C584

0.047U_0402_16V7K

R308 49.9_0402_1%

1 2

R304 49.9_0402_1%

1 2

R318 49.9_0402_1%

1 2

R313 49.9_0402_1%

1 2

R284 49.9_0402_1%

1 2

R276 49.9_0402_1%

1 2

R265 49.9_0402_1%

1 2

R258 49.9_0402_1%

1 2

R272 49.9_0402_1%

1 2

R263 49.9_0402_1%

1 2

R288 49.9_0402_1%

1 2

R283 49.9_0402_1%

1 2

R298 49.9_0402_1%

1 2

R291 49.9_0402_1%

1 2

R307 @49.9_0402_1%

1 2

R303 @49.9_0402_1%

1 2

Title

Size Document Number Rev

Date: Sheet

Clock Generator

CLK_HCLKCLK_CPU1

CLK_HCLK#CLK_CPU1#

CLK_BCLKCLK_CPU0

CLK_BCLK#CLK_CPU0#

CLK_ITPCLK_CPU2

CLK_ITP#CLK_CPU2#

CLK_PCIE_VGACLK_SRC5

CLK_PCIE_VGA#CLK_SRC5#

CLK_PCIE_SATACLK_SRC4

CLK_PCIE_SATA#CLK_SRC4#

CLK_PCIE_MCHCLK_SRC3

CLK_PCIE_MCH#CLK_SRC3#

CLK_PCIE_ICHCLK_SRC1

CLK_PCIE_ICH#

CLK_DOT_MCHCLK_DOT

CLK_DOT_MCH#CLK_DOT#

Compal Electronics, Inc.

CLOCK GENERATOR

Custom

ECQ60 LA-2271

E

CLK_HCLK 7

CLK_HCLK# 7

CLK_BCLK 4

CLK_BCLK# 4

CLK_ITP 5

CLK_ITP# 5

CLK_PCIE_VGA 15

CLK_PCIE_VGA# 15

CLK_PCIE_SATA 24

CLK_PCIE_SATA# 24

CLK_PCIE_MCH 7

CLK_PCIE_MCH# 7

CLK_PCIE_ICH 25

CLK_PCIE_ICH# 25

14 54Monday, August 09, 2004

E

1A

of

A

1 1

PCIE_TXN[0..15]7

PCIE_TXP[0..15]7
VGA_PCIE_RXN[0..15]7
VGA_PCIE_RXP[0..15]7

PCIE_TXP0
PCIE_TXN0
PCIE_TXP1
PCIE_TXN1
PCIE_TXP2
PCIE_TXN2

2 2

3 3

1K_0402_5%

PLTRST#

+3VS

R415

1,23,27,30,35,37

4 4

PCIE_TXP3
PCIE_TXN3
PCIE_TXP4
PCIE_TXN4
PCIE_TXP5
PCIE_TXN5
PCIE_TXP6
PCIE_TXN6
PCIE_TXP7
PCIE_TXN7
PCIE_TXP8
PCIE_TXN8
PCIE_TXP9
PCIE_TXN9
PCIE_TXP10
PCIE_TXN10
PCIE_TXP11
PCIE_TXN11
PCIE_TXP12
PCIE_TXN12
PCIE_TXP13
PCIE_TXN13
PCIE_TXP14
PCIE_TXN14
PCIE_TXP15
PCIE_TXN15

C665

10P_0402_50V8K

PLTRST_VGA#25
ECRST_VGA#37

12

C548 0.1U_0402_16V4Z

C197 0.1U_0402_16V4Z
C191 0.1U_0402_16V4Z
C184 0.1U_0402_16V4Z
C174 0.1U_0402_16V4Z
C170 0.1U_0402_16V4Z
C166 0.1U_0402_16V4Z
C153 0.1U_0402_16V4Z
C144 0.1U_0402_16V4Z
C136 0.1U_0402_16V4Z
C128 0.1U_0402_16V4Z
C122 0.1U_0402_16V4Z
C113 0.1U_0402_16V4Z
C105 0.1U_0402_16V4Z
C101 0.1U_0402_16V4Z
C93 0.1U_0402_16V4Z
C84 0.1U_0402_16V4Z

12

PLTRST#

1 2

X3

4

VDD

1

OE

27MHZ_15P

PCIE_TXN[0..15]

PCIE_TXP[0..15]
VGA_PCIE_RXN[0..15]
VGA_PCIE_RXP[0..15]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA#14

R188 @0_0402_5%

1 2

R187 0_0402_5%

1 2

R525 @0_0402_5%

1 2

OSC_OUT

3

OUT

2

GND

LUMA22
CRMA22
COMPS22

(1.2V)

+PCIE_1.2VS

1 2

R421

121_0603_1%

71.5_0402_1%

C201 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4Z

1 2

C189 0.1U_0402_16V4Z

1 2

C183 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4Z

1 2

C169 0.1U_0402_16V4Z

1 2

C162 0.1U_0402_16V4Z

1 2

C151 0.1U_0402_16V4Z

1 2

C141 0.1U_0402_16V4Z

1 2

C133 0.1U_0402_16V4Z

1 2

C127 0.1U_0402_16V4Z

1 2

C119 0.1U_0402_16V4Z

1 2

C112 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

+3VS

+3VS

SMBCLK
SMBDATA

+3VS

R414

12

R183 @10K_0402_5%

R208 4.7K_0402_5%
R209 @0_0402_5%

R200 @0_0402_5%

R199 4.7K_0402_5%

For VGA thermal monitor

Reserved for EC to monitor VGA tempturature.

SMBCLK
SMBDATA

A

R210 0_0402_5%
R201 0_0402_5%

12
12

B

VGA_PCIE_RXP0
VGA_PCIE_RXN0
VGA_PCIE_RXP1
VGA_PCIE_RXN1
VGA_PCIE_RXP2
VGA_PCIE_RXN2
VGA_PCIE_RXP3
VGA_PCIE_RXN3
VGA_PCIE_RXP4
VGA_PCIE_RXN4
VGA_PCIE_RXP5
VGA_PCIE_RXN5
VGA_PCIE_RXP6
VGA_PCIE_RXN6
VGA_PCIE_RXP7
VGA_PCIE_RXN7
VGA_PCIE_RXP8
VGA_PCIE_RXN8
VGA_PCIE_RXP9
VGA_PCIE_RXN9
VGA_PCIE_RXP10
VGA_PCIE_RXN10
VGA_PCIE_RXP11
VGA_PCIE_RXN11
VGA_PCIE_RXP12
VGA_PCIE_RXN12
VGA_PCIE_RXP13
VGA_PCIE_RXN13
VGA_PCIE_RXP14
VGA_PCIE_RXN14
VGA_PCIE_RXP15
VGA_PCIE_RXN15

VGA_PCIE_TXP0
VGA_PCIE_TXN0
VGA_PCIE_TXP1
VGA_PCIE_TXN1
VGA_PCIE_TXP2
VGA_PCIE_TXN2
VGA_PCIE_TXP3
VGA_PCIE_TXN3
VGA_PCIE_TXP4
VGA_PCIE_TXN4
VGA_PCIE_TXP5
VGA_PCIE_TXN5
VGA_PCIE_TXP6
VGA_PCIE_TXN6
VGA_PCIE_TXP7
VGA_PCIE_TXN7
VGA_PCIE_TXP8
VGA_PCIE_TXN8
VGA_PCIE_TXP9
VGA_PCIE_TXN9
VGA_PCIE_TXP10

VGA_PCIE_TXP11
VGA_PCIE_TXN11
VGA_PCIE_TXP12
VGA_PCIE_TXN12
VGA_PCIE_TXP13
VGA_PCIE_TXN13
VGA_PCIE_TXP14
VGA_PCIE_TXN14
VGA_PCIE_TXP15
VGA_PCIE_TXN15

CLK_PCIE_VGA
CLK_PCIE_VGA#

R150 150_0402_1%

1 2

R143 100_0402_1%

1 2

R146 10K_0402_1%

1 2

R154 1K_0402_5%
R162 715_0402_1%

12

PCIE_TESTIN

12

12

LUMA
CRMA
COMPS

12
12

12
12

R160 1K_0402_5%

R182 10K_0402_5%

B

XTALOUT

12

12

DDC3CLK
DDC3DATA

EC_SMC1 37,38,46
EC_SMD1 37,38,46

AH30
AG30
AG29

AF29
AE29

AE30
AD30
AD29
AC29

AB29

AB30

AA30

AA29

Y29
W29
W30

V30

V29

U29

T29

T30

R30

R29

P29

N29

N30
M30
M29

K29

K30

AF26
AE26

AC25

AB25

AC27

AB27

AC26

AB26

Y25
W25

Y27
W27

Y26
W26

U25

T25

U27

T27

U26

T26

P25

N25

P27

N27

P26

N26

K25

K27

K26

AF27
AE27

AC23

AB24
AB23

AE25

AD25
AD24

AH21

AK21

AJ22

AK22

AJ24

AK24

AG22
AG23

AJ23

AH24
AH28

AJ29

AH27

AF25

AH25

L29

J30

L25
L27
L26

E8
B6

U39A

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_CALRP
PCIE_CALRN
PCIE_CALI

PCIE_TESTIN
PWRGD

PWRGD_MASK
R2SET
Y_G

C_R_PR
COMP_B_PB

H2SYNC
V2SYNC

DDC3CLK
DDC3DATA

SSIN
SSOUT

XTALIN
XTALOUT

TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST

STEREOSYNC

M24P_BGA708

C

GPIO0

Part 1 of 5

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO_PWRCNTL

GPIO_MEMSSIN

DVOMODE

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15

DVO / EXT TMDS / GPIOTMDSDAC1

DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL_0

PCI EXPRESS

DVPCNTL_1

DVPCNTL_2

DVPCNTL_3

VREFG

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N

LVDS

TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

DIGON

BLON
TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TXCM

TXCP

DDC2CLK

DDC2DATA

DAC2CLK

SS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HSYNC
VSYNC

DDC1DATA

DDC1CLK

GPIO_AUXWIN

DPLUS

DMINUS

THERM

HPD1

RSET

C

R

G

B

AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4
AH15

AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

AE12
AG12

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

AE13
AE14
AF12

AK27
AJ27
AJ26
AJ25
AK25

AH26
AG25
AF24
AG24

AF11
AE11

VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6

GPIO8
ROM_ID4

ROM_ID1
ROM_ID2
ROM_ID3
M_SEN
POWER_SEL
MCLK_SPREAD

MEM_ID0
MEM_ID1

R185

4.7K_0402_5%

I2C_DAT
I2C_CLK

DVPDATA_20

R155 10K_0402_5%

10K_1206_8P4R_5%

TXOUT0­TXOUT0+
TXOUT1-VGA_PCIE_TXN10
TXOUT1+
TXOUT2­TXOUT2+

TXCLK­TXCLK+
TZOUT0­TZOUT0+
TZOUT1­TZOUT1+
TZOUT2­TZOUT2+

TZCLK­TZCLK+

ENVDD
ENBKL

R179 100K_0402_5%

R
G
B
DAC1_HSYNC
DAC1_VSYNC

DACA_RSET
DDC_DATA
DDC_CLK

DPLUS
DMINUS

VGA_GPIO0

AJ5

ROM_ID[3:0]
ROMIDCFG(3:0) 1 0 1 1 SERIAL M25P10 ROM

R195 10K_0402_5%

1 2

SIN 16
SCLK 16

M_SEN 22,37
POWER_SEL 49

POWER_SEL(High):VDDC=1.05V
(Low):VDDC=1.2V

+3VS +3VS

12

12

R186

4.7K_0402_5%

DVPDATA_20(High): No slave VIP host port
devices reporting presence during reset

I2C_DAT 21

1 2

1 2

I2C_CLK 21

TXOUT0- 21
TXOUT0+ 21
TXOUT1- 21
TXOUT1+ 21
TXOUT2- 21
TXOUT2+ 21

TXCLK- 21
TXCLK+ 21
TZOUT0- 21
TZOUT0+ 21
TZOUT1- 21
TZOUT1+ 21
TZOUT2- 21CLK_PCIE_VGA14
TZOUT2+ 21

TZCLK- 21
TZCLK+ 21

ENVDD 21
ENBKL 21,37

R22
G22
B22
DAC1_HSYNC 22
DAC1_VSYNC 22

DDC_DATA 22
DDC_CLK 22

R189
10K_0402_5%

1 2

RP3

1 8
2 7
3 6
4 5

C214 0.1U_0402_16V4Z

12

R180
100K_0402_5%

1 2

D

+3VS

+VREFG+VREFG

2200P_0402_50V7K

R216 @0_0402_5%

D

+3VS

12

12

SOUT 16

*

R198
1K_0402_1%

R177
1K_0402_1%

OSC_OUT MCLK_SPREAD

1

C217

2

1 2

R181 499_0402_1%

12

E

+3VS

M_SEN
POWER_SEL
MEM_ID0

MEM_ID1

Vedio Memory Config.

MEM_ID0

0
0
1
1

GPIO0 DEFAULT : 0
GPIO1
GPIO(3:2)
GPIO4
GPIO5
GPIO6

+3VS

C227 0.1U_0402_16V4Z

Pin3 : Reserved for P1819 Spread Rate selection.

+3VS

C216 0.1U_0402_16V4Z

DPLUS

DMINUS

AUXWIN

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

R178 10K_0402_5%

1 2

R527 @10K_0402_5%

1 2

R412 @10K_0402_5%

1 2

R419 10K_0402_5%

1 2

R413 @10K_0402_5%

1 2

R420 10K_0402_5%

ROM_ID1
ROM_ID2
ROM_ID3
ROM_ID4

1 2

R520 @10K_0402_5%

1 2

R521 @10K_0402_5%

1 2

R522 @10K_0402_5%

1 2

R523 @10K_0402_5%

1 2

Delete R416, R417

MEM_ID1

0
1
0
1

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6

1 2

R411 10K_0402_5%

1 2

R193 @10K_0402_5%

1 2

R410 @10K_0402_5%

1 2

R418 @10K_0402_5%

1 2

R176 @10K_0402_5%

1 2

R194 @10K_0402_5%

1 2

R409 @10K_0402_5%

64MB
64MB
128MB
128MB

CAL_BG_BACKUP
PLL_CAL_FORCE_EN
PCIE_MODE(1:0)
CAL_OFF
BYPASS_PLL
ICOMP

DDR SPREAD SPECTRUM

1 2

U14

7

VDD

1

XIN

8

XOUT

2

VSS

ASM3P1819-SR_SO8

1 2

U13

1

VCC

2

DXP

3

DXN
THERM4GND

G781-1_SOP8

G781-1

REF

MODOUT

PD#

SMBCLK

SMBDATA

5
4
3

NC

6

8
7
6

ALERT

5

@10K_0402_5%

AUXWIN

@MMBT3904_SOT23

M24-P

ECQ60 LA-2271

Size Vendor

4Mx32 Samsung
4Mx32 Hynix
8Mx32 Samsung
8Mx32 Hynix

+3VS

DEFAULT : 0
DEFAULT : 00
DEFAULT : 0
DEFAULT : 0
DEFAULT : 0

1 2

R206 22_0402_5%

1 2

R217 @10K_0402_5%

1 2

R205 @10K_0402_5%

SMBCLK
SMBDATA

+3VS+3VS

12

R218

C

Q14

2

B

E

3 1

E

12

R219
@10K_0402_5%

ALERT#

15 54Monday, August 09, 2004

+3VS

1A

of

A

B

C

D

E

NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63

NMDB[0..63]

NMAB[0..13]

NDQSB[0..7]

NDQMB#[0..7]

D7
F7

E7
G6
G5

F5

E5

C4

B5

C5

A4

B4

C2

D3

D1

D2
G4

H6

H5

J6
K5
K4
L6
L5

G2

F3
H2
E2
F2

J3
F1
H3
U6
U5
U3
V6

W5
W4

Y6
Y5
U2
V2
V1
V3

W3

Y2
Y3

AA2
AA6
AA5
AB6

AB5
AD6
AD5

AE5

AE4

AB2

AB3
AC2
AC3
AD3

AE1

AE2

AE3

C

NMDA[0..63]

NMAA[0..13]

NDQSA[0..7]

U39B

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63

M24P_BGA708

NDQMA#[0..7]

Part 2 of 5

MEMORY INTERFACE A

NMCKEA

1 2

R88 10_0402_5%

1 2

R89 10_0402_5%

1 2

R91 10_0402_5%

1 2

R90 10_0402_5%

1 1

NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21

2 2

3 3

4 4

NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63

H28
H29

J28
J29

J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10

C9

B9
B10
E13
E12
E10
F12
F11

E9

F9

F8

MCLKA0
MCLKA0#
MCLKA1
MCLKA1#

A

NMDA[0..63] 19

NMAA[0..13] 19

NDQSA[0..7] 19

NDQMA#[0..7] 19

NMAA0

E22

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7
RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD
MVREFS

DIMA_0
DIMA_1

R44

1 2

10K_0402_5%

NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1# NMCLKB1

B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19

J25
F29
E25
A27
F15
C15
C11
E11

J27
F30
F24
B27
E16
B16
B11
F10

A19
E18
E19
E20
F20
B19

B21
C20

C18
A18

B7
B8

D30
B13

NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13

NDQMA#0
NDQMA#1
NDQMA#2
NDQMA#3
NDQMA#4
NDQMA#5
NDQMA#6
NDQMA#7

NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7

NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA

MCLKA0
MCLKA0#

MCLKA1
MCLKA1#

+MVREFD
+MVREFS

NMCLKA0 19
NMCLKA0# 19
NMCLKA1 19
NMCLKA1# 19

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B

NMRASA# 19
NMCASA# 19
NMWEA# 19
NMCSA0# 19
NMCSA1# 19
NMCKEA 19

C82

C77

+2.6VS

12

R86
100_0402_1%

12

1

2

1

2

+2.6VS

R93
100_0402_1%

12

R85
100_0402_1%

12

R92
100_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U39C

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63

M24P_BGA708

NMCKEB

MCLKB0
MCLKB0#
MCLKB1
MCLKB1#

NMDB[0..63] 20

NMAB[0..13] 20

NDQSB[0..7] 20

NDQMB#[0..7] 20

Part 3 of 5

MEMORY INTERFACE B

R127

1 2

10K_0402_5%

1 2

R130 10_0402_5%

1 2

R126 10_0402_5%

1 2

R135 10_0402_5%

1 2

R140 10_0402_5%

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#

CSB0#
CSB1#

CKEB

CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB_0
DIMB_1

NMAB0

N5

NMAB1

M1

NMAB2

M3

NMAB3

L3

NMAB4

L2

NMAB5

M2

NMAB6

M5

NMAB7

P6

NMAB8

N3

NMAB9

K2

NMAB10

K3

NMAB11

J2

NMAB12

P5

NMAB13

P3
P2

NDQMB#0

E6

NDQMB#1

B2

NDQMB#2

J5

NDQMB#3

G3

NDQMB#4

W6

NDQMB#5

W2

NDQMB#6

AC6

NDQMB#7

AD2

NDQSB0

F6

NDQSB1

B3

NDQSB2

K6

NDQSB3

G1

NDQSB4

V5

NDQSB5

W1

NDQSB6

AC5

NDQSB7

AD1

NMRASB#

R2

NMCASB#

T5

NMWEB#

T6

NMCSB0#

R5

NMCSB1#

R6

NMCKEB

R3

MCLKB0

N1

MCLKB0#

N2

MCLKB1

T2

MCLKB1#

T3

E3
AA3

ROMCS#

AF5

R94 4.7K_0402_5%

1 2

C6

R76 4.7K_0402_5%

1 2

C7

R75 47_0402_1%

1 2

C8

(15mil)

NMCLKB0
NMCLKB0#

NMCLKB1#

NMCLKB0 20
NMCLKB0# 20
NMCLKB1 20
NMCLKB1# 20

D

+3VS

12

R524
@10K_0402_5%

SCLK15

+3VS

NMRASB# 20
NMCASB# 20
NMWEB# 20
NMCSB0# 20
NMCSB1# 20
NMCKEB 20

+1.8VS

ROMCS#

U46

5

D

6

C

1

S

7

HOLD

3

W

8

VCC

@M25P10_SO8

VSS

2

Q

4

MEM IO Voltage Selection

2.5V
VDDR1

MEMVMODE0
MEMVMODE1

Compal Electronics, Inc.

Title

M24-P MEMORY INTERFACE

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

LOW

HI

E

1.8V
VDDR1(ELPIDA)

16 54Monday, August 09, 2004

SOUT 15SIN15

LOW

HI

1A

of

A

+AVDD1.8

L43

L41

1 2

L42

1 2

L33

1 2

L31

1 2

1 2

0_0603_5%

0_0603_5%

0_0603_5%

0_0603_5%

0_0603_5%

1

2

+1.8VS

1 1

+2.6VS

+2.6VS

2 2

+1.8VS

+1.8VS

3 3

CHB1608U301_0603 (P/N:SM010012500)

L40

+1.8VS

4 4

1 2

0_0603_5%

+3VS

C547

@470P_0402_50V7K

+2.6VS

1

2

1

2

(10 mil)

1

C545
22U_1206_10V4Z

2

+VDD_DAC2.5

(20 mil)

1

C544
22U_1206_10V4Z

2

+VDDRH2.5

(20 mil)

1

C514
22U_1206_10V4Z

2

+MPVDD1.8

(10 mil)

1

C470
22U_1206_10V4Z

2

0.1U_0402_16V4Z

1

C543
22U_1206_10V4Z

C542
22U_1206_10V4Z

L39

1
4
3

MIC5205-2.8BM5_SOT23-5~D

C209

2

Place near pin AK28

0.1U_0402_16V4Z

1

C193

2

1 2

@0_0603_5%

VOUT

VIN
PG
EN

GND

U41

1

C204

0.1U_0402_16V4Z

2

1

C192

0.1U_0402_16V4Z

2

1

C100

0.1U_0402_16V4Z

2

1

C81

0.1U_0402_16V4Z

2

(10 mil)

1

C202

2

0.1U_0402_16V4Z

(10 mil)

1

C185

2

0.1U_0402_16V4Z

5

2

+2.6VS

+2.6VS

+2.6VS

+2.6VS

+VDD_PLL1.8

1

C203

0.1U_0402_16V4Z

2

+VDD_PNLIO1.8

1

C194

0.1U_0402_16V4Z

2

1

C541
22U_1206_10V4Z

2

1

C114

2

22U_1206_10V4Z

1

C94

2

1000P_0402_50V7K

1

C90

2

0.1U_0402_16V4Z

1

C111

2

0.1U_0402_16V4Z

+VDD_PNLIO2.5

(10 mil)

SA052050010(MIC5205-2.8BM5), max:150mA

A

B

22U_1206_10V4Z

1

C115

2

0.1U_0402_16V4Z

1

C88

2

0.1U_0402_16V4Z

1

C181

2

0.1U_0402_16V4Z

1

C83

2

+VDD_PNLIO2.5

+VDD_PNLIO1.8

+VDD_PLL1.8

+VDDRH2.5

+VDD_DAC2.5

+AVDD1.8

+VDD_PNLIO1.8

+VDD_PLL1.8

+MPVDD1.8

1

C186

0.1U_0402_16V4Z

2

B

1

C116

0.1U_0402_16V4Z

2

1

C89
1000P_0402_50V7K

2

1

C139
1000P_0402_50V7K

2

1

C154
1000P_0402_50V7K

2

130mA

30mA

10mA

400mA

Second DAC Supply

Analog

70mA

10mA

30mA
10mA

C

U39D

T7

K23
K24

H10
H13
H15
H17

AA1
AA4
AA7
AA8

A15
A21
A28

B30
D26
D23
D20
D17
D14
D11

E27

G10
G13
G15
G19
G22
G27
H22
H19

AD4

AE16
AE17

AF15

AE15

AH19
AH13

AF13
AF14

F18

AF21

AE20

AF23

AH23

AE23
AE22

AK28

R4
R1
N8
N7

M4

L8

N4

J8
J7
J4
J1

T8
V4
V7
V8

A3
A9

B1

D8
D5

F4

G7

L23

N6

A7

VDDR1_0
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_44
VDDR1_45
VDDR1_46
VDDR1_47
VDDR1_48
VDDR1_49
VDDR1_50
VDDR1_51
VDDR1_52
VDDR1_53

LVDDR_25_0
LVDDR_25_1
LVDDR_18_0
LVDDR_18_1

LPVDD
TPVDD

TXVDDR_0
TXVDDR_1

VDDRH0
VDDRH1

A2VDD_0
A2VDD_1

A2VDDQ
AVDD

VDD1DI
VDD2DI

PVDD
MPVDD

M24P_BGA708

Part 4 of 5

POWER

PCIE_VDDR_12_0
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4

PCIE_PVDD_12_0
PCIE_PVDD_12_1
PCIE_PVDD_12_2

PCIE_PVDD_18_0
PCIE_PVDD_18_1
PCIE_PVDD_18_2
PCIE_PVDD_18_3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40

VDDC1_0
VDDC1_1
VDDC1_2
VDDC1_3

VDD15_0
VDD15_1
VDD15_2
VDD15_3
VDD15_4
VDD15_5
VDD15_6
VDD15_7

VDDR3_0
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6

VDDR4_0
VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

AC13
AD13
AD15
AC15
AC17
P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19

W16
M15
R19
T12

P8
Y8
AC11
AC20
H20
H11
M23
Y23

AD7
AD19
AD21
AC22
AC8
AC21
AC19

AG7
AD9
AC9
AC10
AD10

AG26
AK29
AJ30
AG28
AG27

N24
N23
P23

U23
T23
V23
W23

1

2

0.1U_0402_16V4Z

2.2U_0805_10V6K

1

C172

2

C195

Near PIN AG26

+PCIE_PVDD1.2

1

2

1

C147

2

0.1U_0402_16V4Z

1

C148

0.1U_0402_16V4Z

2

+VGA_CORE_CI

C161

0.1U_0402_16V4Z

1

1

C176

2

2

0.1U_0402_16V4Z

1

C175

2

1000P_0402_50V7K

1

2

0.1U_0402_16V4Z

Near PIN P23

1

C129

2

1000P_0402_50V7K

Near PIN N23

C145

0.1U_0402_16V4Z

C106

0.1U_0402_16V4Z

Near PIN AK29

0.1U_0402_16V4Z

1

C132

2

D

0.1U_0402_16V4Z

1

C124

2

1

2

L13

CHB1608U301_0603

1 2

1

C125

0.1U_0402_16V4Z

2

1

C138
22U_1206_10V4Z

2

1

C177

2

0.1U_0402_16V4Z

1

C206

2

1

C140
22U_1206_10V4Z

2

+PCIE_PVDD1.8

(20 mil)

1

C159

0.1U_0402_16V4Z

2

D

1

C182

2

0.1U_0402_16V4Z

C160

0.1U_0402_16V4Z

2004/05/31

2004/05/31

+VGA_CORE

+VDD1.5

+3VS

1

C225
22U_1206_10V4Z

2

C207

1

2

1

2

C539
22U_1206_10V4Z

1

2

1000P_0402_50V7K

Near PIN AG30

E

DIODE SUPPLIES POWER
TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON

+VGA_CORE

0.1U_0402_16V4Z

1

C134

2

1

C126

0.1U_0402_16V4Z

2

16.9K_0603_1%

+3VS

R45

L15

0_0603_5%

1

C135

2

0.1U_0402_16V4Z

1

C146

0.1U_0402_16V4Z

2

+2.6VS

1

12

@22U_1206_10V4Z

2

12

+PCIE_1.2VS

R46
10K_0402_1%

12

C438

+1.5VS

1

C171

22U_1206_10V4Z

2

U32

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TR_SO8

6
5

NC

7

NC

8

NC

9

TP

SM010012500

C208
22U_1206_10V4Z

L16

0_0603_5%

J1

2 1

JUMP_43X79

(1.2V)

+PCIE_1.2VS

12

(1.2V)

+VGA_CORE+PCIE_1.2VS

SM010012500

L38

12

0_0603_5%

Compal Electronics, Inc.

Title

M24-P POWER

Size Document Number Rev

Custom

ECQ60 LA-2271

Date: Sheet

+1.8VS

17 54Monday, August 09, 2004

E

of

+3VS

1A