Compal LA-2211, Compaq nc4200 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Dothan uFCBGA/uFCPGA with
Intel Alviso_GM+ICH6-M core logic

3 3

4 4

A

B

2004-09-09

REV:06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Document Number Rev
Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2211

E

0.6

of

148Thursday, September 09, 2004

A

B

C

D

E

Compal confidential

File Name : LA-2211

Heavenly

1 1

DOCK/DVI

page 33

DVI controller

SiI1362

page 16

Fan Control

page 4

SDVO

H_A#(3..31)

CRT/TV-OUT

page 15

2 2

LCD CONN

page 16

Mobile Dothan/Yonah

uFCBGA-479/uFCPGA-478 CPU

page 4,5,6

FSB

400/533MHz

H_D#(0..63)

Intel Alviso GMCH

PCBGA 1257

page 7,8,9,10,11

DMI

Thermal Sensor
ADM1031AR

page 4

DDR2 -400/533

Dual Channel

USB2.0

Clock Generator

CY28430-3

page 14

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

page 12,13

USB conn x3

page 28

PCI-E BUS

BT Conn

page 28

PCI BUS

Intel ICH6-M

Gigabit LAN
BCM5751M

page 23

3 3

RTC CKT.

page 18

RJ45/11 CONN

page 24

Mini PCI
socket

page 25

CardBus Controller

TI PCI6611

page 21,22

Slot 0

page 22

SD/SDIO Slot

page 21

mBGA-609

page 17,18,19,20

LPC BUS

AC-LINK

PATA

Power OK CKT.

page 35

Power On/Off CKT.

page 32

4 4

DC/DC Interface CKT.

page 34

Security Module

Touch Pad CONN. Int.KBD

SMSC LPC47N250

page 32

page 31

page 32

SMSC Super I/O

LPC47N217

COM1 on
Docking side

page 29page 30

Audio CKT

AD1981B

page 26

PATA HDD
Connector

page 18

Flash ROM

SST49LF008A

FIR

page 30

AMP & Audio Jack

page 31

page 27

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

page 33

LPT on

Power Circuit DC/DC

36,37,38,39,40,41,42,43

A

Digitizer

page 16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Docking side

Title

Size Document Number Rev
Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2211

E

0.6

of

248Thursday, September 09, 2004

A

Voltage Rails

Power Plane

VIN
B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VALW
+1.5VS
+1.8V

+2.5VS
+3VALW
+3V

+5VALW
+5V
+5VS
+12VALW
+12V

RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

1 1

Internal PCI Devices

DEVICE

LAN
Azalia D27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V always on power rail

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V always on power rail
3V power rail

3.3V switched power rail+3VS
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail
12V power rail
12Vswitched power rail on power rail
RTC power

PCI Device ID

D8

IDSEL #

AD24

AD11
D28PCI-E
D29
D30
D30
D30
D31
D31
D31

AD12

AD13

AD14

AD14

AD14

AD15

AD15

AD15

S0-S1

N/A

ON OFF
ON
ON
ON
ON
ON
ON+1.8VS OFF OFF1.8V switched power rail

ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

S3

N/A
N/A

OFF
OFF
ON
OFF
ON

ON2.5V always on power rail+2.5VALW ON*ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF+12VS
ON

S5

N/A
N/AN/A
OFF
OFF
OFF
ON*
OFF
OFF

OFF2.5V switched power rail for MCH video PLL
ON*
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ONON

Symbol note:

:means digital ground.

:means analog ground.

:means reserved.@

External PCI Devices

DEVICE

Mini-PCI
CARD BUS

PCI Device ID

D4
D6

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0
A2
D2

IDSEL #

AD20

AD22

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 0 1 0
1 1 0 1 0 0 1 0

REQ/GNT #

0
2

PIRQ

F
A B C D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-2211

of

348Thursday, September 09, 2004

0.6

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>
H_ADSTB#1<7>

H_RS#[0..2]<7>

1 2
1 2

5

CK_ITP
CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_TRDY#<7>

ITP_DBRESET#<19>

H_DBSY#<7>

H_DPSLP#<18>

H_DPRSTP#<18>

H_DPWR#<7>

H_PWRGOOD<18>

H_CPUSLP#<7,18>

H_THERMTRIP#<7,18>

12
12

C C

B B

A A

CK_ITP<14>
CK_ITP#<14>

CLK_CPU_BCLK<14>
CLK_CPU_BCLK#<14>

R172

1 2

+VCCP

56_0402_5%

H_PROCHOT#

R410 56_0402_5%

H_PWRGOOD

R166 200_0402_1%

TEST1

R382 1K_0402_5%@

TEST2

R416 1K_0402_5%@

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

R203 0_0402_5%

CPU_CK_ITP

1 2

CPU_CK_ITP#

1 2

R199 0_0402_5%

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

+VCCP
+VCCP

JP12A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

FOX_PZ47803-2749-01

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_D#0

A19

H_D#[0..63] <7>

ITP700FLEX FOR Dothan

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R
ITP_TRST#

RESETITP#
ITP_TCK
CK_ITP#

CK_ITP

JP19

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLK#

9

BCLK

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

ITP700-FLEXCON

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

VTT0
VTT1

VTAP
DBR#

DBA#

NC1
NC2

+VCCP

1 2

R243

1 2

200_0402_1%

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

C296

0.1U_0402_16V4Z

27
28
26

25
24

23
21
19
17
15
13

4
6

Thermal Sensor ADM1032AR

+3VS

2

C273

0.1U_0402_16V4Z

C264

1 2

2200P_0402_50V7K

R228

1 2

+3VS

10K_0402_5%

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>
H_NMI <18>

H_STPCLK# <18>
H_SMI# <18>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PWM Fan Control circuit

FAN_PWM<31>

THERM#

1

H_THERMDA
H_THERMDC THERM_SCI#

THERM#

+3VS

5

U24

1

P

INB

O

2

INA

G

TC7SH00FU_SSOP5

3

2

ITP_DBRESET#

U16

1
2
3

ADM1032AR_SOP8

Address:100_1100

4

+VCCP +VCCP

R240

54.9_0402_1%

1 2

H_RESET# RESETITP# ITP_TDO_RITP_TDO

+VCCP

1 2

R236 39.2_0603_1%

1 2

R246 150_0402_5%

VDD

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ICH_SMBCLK<8,12,13,14,19,23>

ICH_SMBDATA<8,12,13,14,19,23>

+5VS

D11
RB751V_SOD323

2 1

6

2

1

D

Q33

G

3

SI3456DV-T1_TSOP6

S

4 5

Title

Size Document Number Rev
Custom

Date: Sheet

12

R242

22.6_0402_1%

ITP_TMS
ITP_TDI

ICH_SMBCLK

8

ICH_SMBDATA

7
6
5

ICH_SMBCLK
ICH_SMBDATA

1

C122

4.7U_0805_10V4Z

2

FAN

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

LA-2211

R238

54.9_0402_1%

1 2

1 2

R237 680_0402_5%

1 2

R239 27.4_0402_1%

12

R227
10K_0402_5%

THERM_SCI# <8,19>

1

C125

0.1U_0402_16V4Z

2

1

12

R241

22.6_0402_1%

ITP_TRST#
ITP_TCK

ACES_85205-0200

of

448Thursday, September 09, 2004

JP8

1
2

0.6

5

4

3

2

1

R175

54.9_0402_1%@

D D

+1.5VS

C520

0.01U_0402_16V7K

C C

+VCCP

12

R248
1K_0402_1%

B B

A A

12

R247
2K_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

1

C298
1U_0603_10V4Z

2

1

C297
220P_0402_50V7K

2

12

54.9_0402_1%

27.4_0402_1%

R245

R244

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

12

R355

1

1

C531

2

2

10U_1206_6.3V6M

12

27.4_0402_1%

R356

54.9_0402_1%@

+VCC_CORE

CPU_VID0<43>
CPU_VID1<43>
CPU_VID2<43>
CPU_VID3<43>
CPU_VID4<43>
CPU_VID5<43>

CPU_BSEL0<14>
CPU_BSEL1<14>

12

54.9_0402_1%

1 2
1 2

R170

+VCCP

H_PSI#<43>

V_CPU_GTLREF

VCCSENSE
VSSSENSE

H_PSI#

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

JP12B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

FOX_PZ47803-2749-01

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

T9 PAD
T11 PAD
T25 PAD
T30 PAD

Dothan

+VCC_CORE

JP12C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

FOX_PZ47803-2749-01

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

LA-2211

1

of

548Thursday, September 09, 2004

0.6

5

4

3

2

1

+VCC_CORE

D D

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C201
10U_1206_6.3V6M

C200
10U_1206_6.3V6M

C443
10U_1206_6.3V6M

C248
10U_1206_6.3V6M

1

C222
10U_1206_6.3V6M

2

1

C190
10U_1206_6.3V6M

2

1

C460
10U_1206_6.3V6M

2

1

C189
10U_1206_6.3V6M

2

1

C237
10U_1206_6.3V6M

2

1

C433
10U_1206_6.3V6M

2

1

C475
10U_1206_6.3V6M

2

1

C450
10U_1206_6.3V6M

2

1

C254
10U_1206_6.3V6M

2

1

C432
10U_1206_6.3V6M

2

1

C469
10U_1206_6.3V6M

2

1

C208
10U_1206_6.3V6M

2

1

C253
10U_1206_6.3V6M

2

1

C438
10U_1206_6.3V6M

2

1

C484
10U_1206_6.3V6M

2

1

C474
10U_1206_6.3V6M

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C267
10U_1206_6.3V6M

C485
10U_1206_6.3V6M

C482
10U_1206_6.3V6M

1

C249
10U_1206_6.3V6M

2

1

C467
10U_1206_6.3V6M

2

1

C481
10U_1206_6.3V6M

2

1

C238
10U_1206_6.3V6M

2

1

C476
10U_1206_6.3V6M

2

1

C209
10U_1206_6.3V6M

2

1

C223
10U_1206_6.3V6M

2

1

C461
10U_1206_6.3V6M

2

1

C180
10U_1206_6.3V6M

2

1

C439
10U_1206_6.3V6M

2

1

C445
10U_1206_6.3V6M

2

1

C266
10U_1206_6.3V6M

2

Near VCORE regulator.

+VCC_CORE

1

1

+

B B

+VCCP

1

+

C203
100U_6.3V_M

2

A A

5

1

C497

0.1U_0402_16V4Z

2

1

C496

0.1U_0402_16V4Z

2

4

1

C495

0.1U_0402_16V4Z

2

C493

1

C477

0.1U_0402_16V4Z

2

330U_D2E_2.5VM_R9

@

9mOhm
7343
PS CAP

+

C456

C472

2

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

9mOhm

9mOhm

7343

7343

PS CAP

PS CAP

1

C420

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

+

+

C428

2

2

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

C419

0.1U_0402_16V4Z

2

3

1

C418

0.1U_0402_16V4Z

2

1

C444

0.1U_0402_16V4Z

2

1

2

2

C468

0.1U_0402_16V4Z

1

C462

0.1U_0402_16V4Z

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-2211

1

0.6

of

648Thursday, September 09, 2004

5

4

3

2

1

U15B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO_BGA1257

V_DDR_MCH_REF<12,13>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13

DMIDDR MUXING

CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

V_DDR_MCH_REF

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG17

CFG18

CFG19

CFG20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26

RSVD27

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
VGATE
PLT_RST#

DREFCLK#
DREFCLK
DREF_SSCLK
DREF_SSCLK#

TP_NC1

TP_NC2

TP_NC3

TP_NC4

TP_NC5

TP_NC6

TP_NC7

TP_NC8

TP_NC9

TP_NC10

TP_NC11

+1.8V

12

R101
10K_0402_1%

12

R102
10K_0402_1%

CFG0 <11>
MCH_CLKSEL1 <14>
MCH_CLKSEL0 <14>

T43

PAD

T47

PAD

CFG5 <11>
CFG6 <11>
CFG7 <11>

T40

PAD

CFG9 <11>

T49

PAD
T53

PAD

CFG12 <11>
CFG13 <11>

T14

PAD
T46

PAD

CFG16 <11>

T50

PAD

CFG18 <11>
CFG19 <11>

T39

PAD
T36

PAD
T38

PAD
T41

PAD
T31

PAD
T33

PAD
T35

PAD
T37

PAD

PM_BMBUSY# <19>

H_THERMTRIP# <4,18>
VGATE <14,19,43>
PLT_RST# <16,17,18,19,29,30,31>

DREFCLK# <14>
DREFCLK <14>
DREF_SSCLK <14>
DREF_SSCLK# <14>

T7 PAD
T6 PAD
T8 PAD
T28 PAD
T27 PAD
T26 PAD
T24 PAD
T23 PAD
T4 PAD
T5 PAD
T3 PAD

PM_EXTTS#0

PM_EXTTS#1

R381

10K_0402_5%

R377

10K_0402_5%

+2.5VS

12

12

C510

12

R393

40.2_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR4
M_CLK_DDR5

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_CLK_DDR#4
M_CLK_DDR#5

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP
V_DDR_MCH_REF

1

C384

2

0.1U_0402_16V4Z

M_OCDOCMP0
M_OCDOCMP1

1

2

0.1U_0402_16V4Z

DMI_TXN0<19>

D D

C C

B B

H_A#[3..31]<4> H_D#[0..63] <4>

T13 PAD

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>

CLK_MCH_BCLK#<14>
CLK_MCH_BCLK<14>

H_DSTBN#[0..3]<4>

H_DSTBP#[0..3]<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_RESET#<4>
H_ADS#<4>

H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>

T57 PAD

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>
H_BR0#<4>
H_BNR#<4>
H_BPRI#<4>
H_DBSY#<4>

H_RS#[0..2]<4>

H_CPUSLP#<4,18>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_CPUSLP#

Note:
"Open for Dothan-A and Short for Dothan-B"

U15A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

J16

1 2

SHORT PADS

Alviso

HOST

H_R_CPUSLP#

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

12

R250

24.9_0402_1%

H_SWNG1

H_SWNG0

+VCCP

R232

12

R427

24.9_0402_1%

1

2

C511

0.1U_0402_16V4Z

1

2

C512

0.1U_0402_16V4Z

12

R434

54.9_0402_1%

54.9_0402_1%

+VCCP

R249

221_0603_1%

R428

100_0402_1%

+VCCP

R435

221_0603_1%

R426

100_0402_1%

12

C483

12

12

12

12

+1.8V

+VCCP

12

R409

100_0402_1%

1

12

R412

2

0.1U_0402_16V4Z

200_0402_1%

DMI_TXN1<19>
DMI_TXN2<19>
DMI_TXN3<19>

DMI_TXP0<19>
DMI_TXP1<19>
DMI_TXP2<19>
DMI_TXP3<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXN2<19>
DMI_RXN3<19>

DMI_RXP0<19>
DMI_RXP1<19>
DMI_RXP2<19>
DMI_RXP3<19>

M_CLK_DDR0<12>
M_CLK_DDR1<12>

T51 PAD

M_CLK_DDR3<13>
M_CLK_DDR4<13>

T52 PAD

M_CLK_DDR#0<12>
M_CLK_DDR#1<12>

T54 PAD

M_CLK_DDR#3<13>
M_CLK_DDR#4<13>

T55 PAD

DDR_CKE0_DIMMA<12>
DDR_CKE1_DIMMA<12>
DDR_CKE2_DIMMB<13>
DDR_CKE3_DIMMB<13>

DDR_CS0_DIMMA#<12>
DDR_CS1_DIMMA#<12>
DDR_CS2_DIMMB#<13>
DDR_CS3_DIMMB#<13>

M_ODT0<12>
M_ODT1<12>
M_ODT2<13>

1 2
1 2

Layout Note:
Route as short
as possible

R380

M_ODT3<13>

12

40.2_0402_1%

R411 80.6_0402_1%
R407 80.6_0402_1%

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(1 of 5)

LA-2211

1

0.6

of

748Thursday, September 09, 2004

5

D D

4

3

2

1

DDR_A_BS#0<12>
DDR_A_BS#1<12>
DDR_A_BS#2<12>

DDR_A_DM[0..7]<12>

DDR_A_DQS[0..7]<12>

C C

B B

T32 PAD
T34 PAD

DDR_A_DQS#[0..7]<12>

DDR_A_MA[0..13]<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>

DDR_A_WE#<12>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AM8
AM4

AK35
AP34
AN30
AN23

AN8
AM5
AH1

AL17
AP17
AP18
AM17
AN18
AM18

AL19
AP20
AM19

AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4
AJ2
AD3

AJ1
AE5

AE4

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

U15C

DDR_A_D0

AG35

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <12>

T45 PAD
T48 PAD

DDR_B_BS#0<13>
DDR_B_BS#1<13>
DDR_B_BS#2<13>

DDR_B_DM[0..7]<13>

DDR_B_DQS[0..7]<13>

DDR_B_DQS#[0..7]<13>

DDR_B_MA[0..13]<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>

DDR_B_WE#<13>

DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

U15D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

ALVISO_BGA1257

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D0
DDR_B_D2

DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <13>

Reserved thermal CKT and closed to JP34.

+3VS

2

C588

0.1U_0402_16V4Z @

A A

C276

1 2

2200P_0402_50V7K@

B

2

DDR_THERMDA
DDR_THERMDC

E

31

Q43

MMBT3904_SOT23@

C

1

5

U38

1

VDD

SCLK

2

D+

SDATA

3

D-

ALERT#

4

OVERT#

GND

MAX6646MUA_8UMAX@

Address:100_1101

ICH_SMBCLK

8

ICH_SMBDATA

7

R547 10K_0402_5%@

6

R548 0_0402_5%@

5

1 2
1 2

ICH_SMBCLK <4,12,13,14,19,23>
ICH_SMBDATA <4,12,13,14,19,23>

+3VS

THERM_SCI# <4,19>

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

LA-2211

1

of

848Thursday, September 09, 2004

0.6

5

4

3

2

1

+2.5VS

R501

R366

R368

R509

1
2

1 2

12

BSS138_SOT23

12

BSS138_SOT23

12

BSS138_SOT23

+3VS

5

P

IN1
IN2

G

3

S

+2.5VS

S

S

U35
SN74AHC1G08DCKR_SC70

100K_0402_5%

+1.5VS_PCIE

R149

U15G

COMPS
LUMA
CRMA

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

AB29

GCLKN

AC29

GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

12

REFSET

E25

LBKLT_CTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

ALVISO_BGA1257

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

PCI - EXPRESS GRAPHICS

EXP_ICOMPO

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

SDVO_SDAT<16>
SDVO_SCLK<16>

CLK_MCH_3GPLL#<14>

D D

C C

B B

CLK_MCH_3GPLL<14>

COMPS<15,33>

LUMA<15,33>

CRMA<15,33>

DDCCLK<15>

DDCDATA<15>

VSYNC<15>
HSYNC<15>

ENAVDD<16>

TXACLK-<16>
TXACLK+<16>
TXBCLK-<16>
TXBCLK+<16>

TXA0-<16>
TXA1-<16>
TXA2-<16>

TXA0+<16>
TXA1+<16>
TXA2+<16>

TXB0-<16>
TXB1-<16>
TXB2-<16>

TXB0+<16>
TXB1+<16>
TXB2+<16>

12

R391

4.99K_0603_1%

VGA_BLU
VGA_GRN
VGA_RED

R389

255_0402_1%

BKLT_CTL
ENABLT

LCD_I2C_CLK
LCD_I2C_DAT
ENAVDD
LIBG

TXACLK­TXACLK+
TXBCLK­TXBCLK+

TXA0­TXA1­TXA2-

TXA0+
TXA1+
TXA2+

TXB0­TXB1­TXB2-

TXB0+
TXB1+
TXB2+

EXP_COMPI

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

24.9_0402_1%

1 2

SDVO_INT-

0.1U_0402_16V4Z

SDVO_INT+

0.1U_0402_16V4Z

SDVO_R-

C374 0.1U_0402_16V4Z

SDVO_G­SDVO_B­SDVO_CLK-

SDVO_R+

C375 0.1U_0402_16V4Z

SDVO_G+
SDVO_B+
SDVO_CLK+

C372

C373

C367 0.1U_0402_16V4Z

C368 0.1U_0402_16V4Z

SDVOB_INT- <16>

SDVOB_INT+ <16>

C370 0.1U_0402_16V4Z

C371 0.1U_0402_16V4Z

C365 0.1U_0402_16V4Z

C366 0.1U_0402_16V4Z

SDVOB_R- <16>
SDVOB_G- <16>
SDVOB_B- <16>
SDVOB_CLK- <16>

SDVOB_R+ <16>
SDVOB_G+ <16>
SDVOB_B+ <16>
SDVOB_CLK+ <16>

2.2K_0402_5%

LCD_I2C_CLK

2.2K_0402_5%

LCD_I2C_DAT

BKLT_CTL

2.2K_0402_5%

LID_SW#<19,32>

LID_SW#
ENABLT

2.2K_0402_5%

+3VS

12

G

2

G

2

G

2

O

R361

Q38

2.2K_0402_5%

13

D

+3VS

12

R365

Q39

2.2K_0402_5%

13

D

+5VS+2.5VS

12

R510

Q56

2.2K_0402_5%

13

D

Q53
DTA114YKA_SC59

+5VS

47K

10K

4

R360

2

G

1 2

2

13

D

S

LCD_I2C_CLK_C <16>

LCD_I2C_DAT_C <16>

BKLT_CTL_C <16>

13

Q36

BSS138_SOT23

+5VS_INV

LIBG

R351

1.5K_0402_1%

A A

5

COMPS
LUMA
CRMA

12

VGA_RED
VGA_GRN
VGA_BLU

12

R195

75_0402_1%

12

R384

75_0402_1%

12

R198

75_0402_1%

12

R383

75_0402_1%

R200

75_0402_1%

R386

75_0402_1%

4

12

VGA_RED D_RED

VGA_GRN GREEN_LL

VGA_BLU

12

L23

1 2

HLC0603CSCC39NJT_0603

L24

1 2

HLC0603CSCC39NJT_0603

L25

1 2

HLC0603CSCC39NJT_0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Layout Note:
Place these components as close
as possible to Alviso-GM.

RED_LL

BLUE_LL

1

C153

2

18P_0402_50V8J

1

2

C152
18P_0402_50V8J

1

2

L18

1 2

HLC0603CSCCR11JT_0603

L19

1 2

HLC0603CSCCR11JT_0603

L20

1 2

HLC0603CSCCR11JT_0603

C151

18P_0402_50V8J

D_GREEN

D_BLUE

2

D_RED <15,33>

D_GREEN <15,33>

D_BLUE <15,33>

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

LA-2211

1

of

948Thursday, September 09, 2004

0.6

5

U15F

K13

D D

+VCCP

1

C471

C414

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

C C

1

C282

0.47U_0603_10V7K

2

1

1

C288

2

2

0.47U_0603_10V7K

B B

CHB1608U301_0603

1 2

+1.5VS

+VCCP

A A

1

1

C459

C415

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C299

C522

2

0.22U_0603_10V7K

0.22U_0603_10V7K

ALVISO_BGA1257

+1.5VS_DPLLA +1.5VS_DPLLB

L22

1

1

+

C172

C184

2

1

C525

2

10U_1206_6.3V6M

2

0.1U_0402_16V4Z

470U_D2_2.5VM

1

1

C403

C490

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

CHB1608U301_0603

+1.5VS +1.5VS +1.5VS

1

C434

2

0.1U_0402_16V4Z

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

L21

1 2

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C261

10U_1206_6.3V6M

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

1

+

C140

2

470U_D2_2.5VM

+1.8V

C412

0.1U_0402_16V4Z

1

2

1

2

Note : All VCCSM pin
shorted internally.

C171

10U_1206_6.3V6M

1

C389

2

0.1U_0402_16V4Z

C448

0.1U_0402_16V4Z

1

2

1

2

+1.8V

1

C217

2

220U_D2_4M_R45

@

1

C464

2

0.1U_0402_16V4Z

4

U15E

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C479

C524

0.1U_0402_16V4Z

470U_D2_2.5VM

1

2

T29
R29
N29

M29

K29
J29
V28

U28

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21
W20
U20

T20

K20

V19
U19

K19
W18

V18

T18

K18

K17
AC1

AC2

B23
C35
AA1
AA2

+1.5VS_HPLL

1

+

C513

2

0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257

1

2

POWER

CHB1608U301_0603

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

1 2

+VCCP

1

1

2

1

2

0.1U_0402_16V4Z

4

C383

2

0.1U_0402_16V4Z

1

C508

2

0.1U_0402_16V4Z

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

CHB1608U301_0603

1 2

1

C411

2

0.1U_0402_16V4Z

C382

C494

+1.5VS

L50

1

2

C400

0.1U_0402_16V4Z

C509

0.1U_0402_16V4Z

1

+

2

1

C425

2

3

R401

D28

+1.5VS_TVDAC_D

2 1

+1.5VS

RB751V_SOD323

+3VS

F17

+3VS_TVDACA
E17
D18

+3VS_TVDACB
C18
F18

+3VS_TVDACC
E18

H18

+3VS_ATVBG
G18

D19

+1.5VS
H17

+1.5VS_QTVDAC
B26

+1.5VS
B25

A25
A35

+2.5VS
B22

VCCHV0
VCCHV1
VCCHV2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCC_SYNC

L49

C523

470U_D2_2.5VM

+2.5VS_CRTDAC
B21

A21
B28

+2.5VS
A28

+1.5VS_DDRDLL

A27
AF20

AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

+1.5VS_MPLL

1

+

C505

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C447

C454

2

0.1U_0402_16V4Z

+2.5VS_CRT

1

C449

2

0.022U_0402_16V7K

1

2

0.1U_0402_16V4Z

Route VSSATVBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+1.5VS_QTVDAC

C427

0.022U_0402_16V7K

1

+

2

100U_D2_6.3VM

C129

220U_D2_4M_R45

L42 CHB1608U301_0603

1 2

1

C442

2

0.1U_0402_16V4Z

2 1

+VCCP

RB751V_SOD323

+2.5VS

10_0805_1%

1 2

PJP11

2 1

PAD-SHORT 2x2m

L40

CHB1608U301_0603

1

1

C435

2

2

0.1U_0402_16V4Z

+1.5VS_PCIE

1

1

+

C381

C380

2

2

0.22U_0603_10V7K
10U_1206_6.3V6M

1

C431

C590

2

0.1U_0402_16V4Z

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

D14

+VCCP_CRTDAC_D

2

+3VS_TVDAC

+1.5VS

12

1

1

C409

C436

2

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

+1.5VS_3GPLL

1

1

C379

2

1

+

2

150U_B2_4VM

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

2

10U_1206_6.3V6M

C406

+2.5VS_CRTDAC

R182

10_0805_1%

1 2

PJP12

2 1

PAD-SHORT 2x2m

2

1

C405

2

0.1U_0402_16V4Z

+3VS_TVDACA

+3VS_TVDACB

R372

0.5_0805_1%

1 2

1

2

10U_1206_6.3V6M

1

2

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+2.5VS_CRTDAC

1

C457

C480

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

C215

C214

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

3GRLL_R

L16

CHB1608U301_0603

C134

0.1U_0402_16V4Z

CHB1608U301_0603

1

2

CHB1608U301_0603

1

2

BLM18PG600SN1_0603

BLM18PG600SN1_0603

BLM18PG600SN1_0603

Title

Size Document Number Rev
Custom

Date: Sheet

12

L44

L26

L39

L35

L38

+2.5VS+2.5VS_3GBG

1

2

+2.5VS

C399

10U_1206_6.3V6M

LA-2211

+3VS_TVDAC

12

12

12

12

+1.5VS

12

C413

0.1U_0402_16V4Z

1

2

1

+3VS_TVDACC

+3VS_ATVBG

+1.5VS

C369

1

0.1U_0402_16V4Z

2

C133

0.1U_0402_16V4Z

1

C392

C404

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C466

C453

2

0.022U_0402_16V7K

1

C451

C452

2

0.022U_0402_16V7K

+1.5VS

1

C421

2

1

0.1U_0402_16V4Z

2

1

2

CHB1608U301_0603

1

2

0.1U_0402_16V4Z

CHB1608U301_0603

1

2

0.1U_0402_16V4Z

+2.5VS_CRTDAC

1

C426

2

10U_1206_6.3V6M

L43

L41

C429

0.1U_0402_16V4Z

Compal Electronics, Inc.

Alviso(4 of 5)

1

10 48Thursday, September 09, 2004

+3VS_TVDAC

12

+3VS_TVDAC+3VS_TVDAC

12

1

2

of

0.6

5

4

3

2

1

+VCCP

U15H

L12

VTT_NCTF17

M12

VTT_NCTF16

N12

AA12
AA13

AA14
AB14

AA15
AB15

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

R12
U12
W12
M13

N13
R13
U13
W13

M14
N14

R14
U14
W14

M15
N15

R15
U15
W15

M16
N16

R16
U16
W16

R17

R21

W25
M26

N26
R26
U26
W26

P12
T12
V12
L13

P13
T13
V13

Y12
Y13
L14

P14
T14
V14
Y14

L15

P15
T15
V15
Y15

L16

P16
T16
V16
Y16

Y17

Y21

Y22

Y23

Y24

Y25

Y26

V25
L26

P26
T26
V26

VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO_BGA1257

D D

C C

B B

A A

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.8V

+VCCP

AG7

AA10

Y1
D2
G2

J2

L2

P2

T2

V2

AD2
AE2
AH2
AL2
AN2

A3
C3

AA3
AB3
AC3

AJ3

C4
H4

L4

P4
U4

Y4

AF4
AN4

E5

W5
AL5
AP5

B6
J6
L6
P6

T6
AA6
AC6
AE6

AJ6

G7

V7
AA7

AK7
AN7

C8

E8

L8

P8

Y8
AL8

A9

H9

K9

T9

V9
AA9
AC9
AE9
AH9
AN9
D10

L10

Y10

F11
H11
Y11

U15I

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

ALVISO_BGA1257

VSS

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24

AN24

W27
AA27
AB27
AF27
AG27

AJ27
AL27

AN27

W28
AA28
AB28
AC28

W29
AA29
AD29
AG29

AJ29

AM29

AA30
AB30
AC30
AE30
AP30

M31

W31
AD31
AG31

AL31

AA32
AB32

A26
E26

G26

J26
B27
E27
G27

E28

A29
D29
E29
F29
G29
H29

L29
P29
U29
V29

C30
Y30

D31
E31
F31
G31
H31

J31
K31

L31
N31

P31
R31
T31
U31
V31

A32
C32
Y32

U15J

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

ALVISO_BGA1257

VSS

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG[13:12]
CFG16

(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

CFG0<7>

CFG5<7>
CFG6<7>
CFG7<7>
CFG9<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>

Refer to page14 for FSB
frequency select

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I

*

*

Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane

*

High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)

*

High = 1.5V
Low = 1.05V (Default)
High = 1.2V

R394 10K_0402_5%

R398 2.2K_0402_5%@
R395 2.2K_0402_5%
R192 2.2K_0402_5%@
R399 2.2K_0402_5%@
R404 2.2K_0402_5%@
R408 2.2K_0402_5%@
R397 2.2K_0402_5%@

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG[17:3] have internal pull-up

R379 1K_0402_5%@

1 2

R378 1K_0402_5%@

1 2

CFG[19:18] have internal pull-down

*

*

*
*

+VCCP

+2.5VS

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(5 of 5)

LA-2211

1

0.6

of

11 48Thursday, September 09, 2004

5

4

3

2

1

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..13]<8>

D D

+1.8V

2.2U_0805_16V4Z
C458

1

2

0.1U_0402_16V4Z

C255

1

2

C C

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

B B

A A

C229

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C250

C239

5

RP27

1 4
2 3

RP29

1 4
2 3

RP32

1 4
2 3

RP31

1 4
2 3

RP33

1 4
2 3

2 3
1 4

C498

1

1

2

2

0.1U_0402_16V4Z
C242

1

2

0.1U_0402_16V4Z

1

1

2

2

C272

C257

+0.9VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

RP35

56_0404_4P2R_5%

C473

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C491

1

2

0.1U_0402_16V4Z

C280

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C279

C281

RP22 56_0404_4P2R_5%

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

RP26 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP28 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP30 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP34 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP24 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

C235

0.1U_0402_16V4Z

C465

1

2

0.1U_0402_16V4Z

1

2

C274

1

2

C268

Layout Note:
Place near JP34

10P_0402_50V8J

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C252

M_CLK_DDR0

1

C394

2

M_CLK_DDR#0

0.1U_0402_16V4Z

1

1

2

2

C234

C241

Layout Note:
Place these resistor
closely JP34,all
trace length<750 mil

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.3"

4

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1

M_CLK_DDR1

10P_0402_50V8J

1

C534

2

M_CLK_DDR#1

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

0.1U_0402_16V4Z

1

2

C227

M_ODT1<7>

ICH_SMBDATA<4,8,13,14,19,23>

ICH_SMBCLK<4,8,13,14,19,23>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

0.1U_0402_16V4Z

+3VS

C308

+1.8V

JP34

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1

2

VDDSPD

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

2

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

+1.8V

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D14

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R453

R455

10K_0402_5%

10K_0402_5%

12

Title

Size Document Number Rev
Custom

Date: Sheet

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C363

2

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2211

C362

1

V_DDR_MCH_REF <7,13>

12 48Thursday, September 09, 2004

of

0.6

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

+1.8V

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C176

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

2.2U_0805_16V4Z

1

2

1

2

C179

RP14

1 4
2 3

RP17

56_0404_4P2R_5%

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

RP19

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP23

2 3
1 4

56_0404_4P2R_5%

2.2U_0805_16V4Z

C236

0.1U_0402_16V4Z
C166

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C186

+0.9VS

5

C265

1

1

2

2

0.1U_0402_16V4Z
C219

1

2

0.1U_0402_16V4Z

1

1

2

2

C197

RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%

RP9

56_0404_4P2R_5%

C247

0.1U_0402_16V4Z

C213

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

2

C188

1

2

0.1U_0402_16V4Z

1

2

C220

DDR_B_MA9

14

DDR_B_MA12

23

DDR_CKE3_DIMMB

14

DDR_B_MA11

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

M_ODT2

14

DDR_B_MA13

23

DDR_B_BS#2

14

DDR_CKE2_DIMMB

23

C159

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C183

C161

C164

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C199

C210

4

Layout Note:
Place near JP10

M_CLK_DDR3

10P_0402_50V8J

1

C121

2

M_CLK_DDR#3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C173

Layout Note:
Place these resistor
closely JP10,all
trace length<750 mil

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.3"

1

1

2

2

C163

C218

4

3

+1.8V

JP10

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

M_CLK_DDR4

10P_0402_50V8J

1

C285

2

M_CLK_DDR#4

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>

DDR_B_WE#<8>

0.1U_0402_16V4Z

1

2

C177

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<4,8,12,14,19,23>

ICH_SMBCLK<4,8,12,14,19,23>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C301

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM B

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

12

R254

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C89

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR4 <7>
M_CLK_DDR#4 <7>

R257

1 2

10K_0402_5%

Title

Size Document Number Rev
Custom

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2211

1

V_DDR_MCH_REF <7,12>

C90

1

13 48Thursday, September 09, 2004

0.6

of

5

FSC FSB FSA CPU

CLKSEL0 CLKSEL2

CLKSEL1

00

011

D D

CLK-RaCPU Type

Dothan-A PSB400
Dothan-A PSB533
Dothan-B

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

B B

+3VS

1 2

A A

1 2

OPEN 1K Ohm

SHORT 1K Ohm OPEN

+VCCP

CLKSEL0

J17

1 2

SHORT PADS

CLK-Ra

+VCCP

J18

1 2

SHORT PADS

CLK-Rd

R148

10K_0402_5%@

96*_100MSEL

R150
10K_0402_5%

5

SRC
MHz

100
100100

PCI
MHz

33.3

33.3

CLK-Rc

OPEN
0 Ohm

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

CLK-Rd CLK-Re

OPEN
OPEN

MHz

1331

R147
1K_0402_5%

CLK-Rb

1 2

1 2

R137
1K_0402_5%

R145

0_0402_5%@

CLK-Rc

1 2

R153
1K_0402_5%

CLK-Rf

1 2

1 2

R155
1K_0402_5%

R154

0_0402_5%@

CLK-Re

1 2

CLK-Rb

OPENOPEN

SS frequency selection

96*_100MSEL 96_100MSST/C

LOW
HIGH

96 MHZ
100 MHZ

CLK_PCI_FWH<30>

4

+3VS

PJP13

1 2

PAD-SHORT 3x3m

1

C117

2

0.1U_0402_16V4Z

CLK-Rf

0 Ohm
0 Ohm
OPEN0 Ohm

C361

33P_0402_50V8J

C364

33P_0402_50V8J

CLK_48M_CB<21>

CLK_48M_ICH<19>

CLK_PCI_EC<31>

CLK_PCI_PCM<21>

CLK_PCI_MINI<25>

CLK_PCI_SIO<29>

CLK_PCI_TCG<30>

CLK_PCI_ICH<17>

OPEN
OPEN
1K Ohm

Place crystal within
500 mils of CK410M

12

12

Y3

14.31818MHZ_20P_6X1430004201

12

CLK_48M_CB
CLK_48M_ICH

CLK_PCI_EC
CLK_PCI_PCM
CLK_PCI_FWH
CLK_PCI_MINI
CLK_PCI_SIO PCICLK2

CLK_PCI_TCG PCICLK2
CLK_PCI_ICH PCICLKF0

4

PJP14

1 2

PAD-SHORT 3x3m

CK_XTAL_IN

CK_XTAL_OUT

R296 10K_0402_5%

+3VS

R302 12_0402_5%
R308 12_0402_5%
R489 2.2K_0402_5%
R152 475_0402_1%

R298 12_0402_5%
R299 12_0402_5%
R294 33_0402_5%
R295 33_0402_5%
R290 12_0402_5%

R303

10K_0402_5%

1 2

+3VS

ICH_SMBCLK<4,8,12,13,19,23>

ICH_SMBDATA<4,8,12,13,19,23>

1 2

R292 12_0402_5%
R304 33_0402_5%

R511 10K_0402_5%@

J27

1 2

SHORT PADS

R521

1 2

0_0402_5%@

+3VS

CLKSEL0_R

REFOUT REFOUT1

CK_VDD_MAIN

CK_VDD_MAIN2

12
12

12
12
12

12
12
12
12
12

R331 475_0402_1%

12
12

PCICLK2

12

CLKSEL2
CLKSEL0_RCLKSEL0
CLKIREF1

PCICLK5
PCICLK4
PCICLK3

96*_100MSEL

PCICLKF0
ICH_SMBCLK

ICH_SMBDATA

CLKIREF

3

2

Width=40mils

2

C407
10U_1206_6.3V6M

1

1

C142
1U_0603_10V4Z

2

Width=40mils

2

C113
10U_1206_6.3V6M

1

U25

21
28
34

1
7

42
48

11

50
49

12
53

16

5
4
3

56

9

8

46

47

39

13
29

2
45
51

6

IDTCV140PAG_TSSOP56

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C136

0.047U_0402_16V4Z

2

1

C141

0.047U_0402_16V4Z

2

1

C130

0.047U_0402_16V4Z

2

VDDSRC_0
VDDSRC_1
VDDSRC_2

VDDPCI_0
VDDPCI_1

VDDCPU
VDDREF

VDD48

XIN
XOUT

FS_A/USB_48MHz
FS_C/TEST_SEL/REF1

FS_B/TEST_MODE

PCICLK5
PCICLK4
PCICLK3
PCICLK2/SEL_CLKREQ
PCICLK_F1/96*_100MSEL

PCICLK_F0/ITP_EN
SCLK

SDATA

IREF

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5

1

C137

0.047U_0402_16V4Z

2

1

C139

0.047U_0402_16V4Z

2

1

C131

0.047U_0402_16V4Z

2

VDDA

GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1

CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/SRCCLKT_7

CPUCLKC2_ITP/SRCCLKC_7

SRCCLKT6/CLKREQA#

SRCCLKC6/CLKREQB#

SRCCLKT5

SRCCLKC5

SRCCLKT4_SATA
SRCCLKC4_SATA

SRCCLKT3
SRCCLKC3

SRCCLKT2
SRCCLKC2

SRCCLKT1
SRCCLKC1

96_100MSST/SRCCLKT0

96_100MSSC/SRCCLKC0

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0/FS_D

1

C143

0.047U_0402_16V4Z

2

1

C135

0.047U_0402_16V4Z

2

1

C126

0.047U_0402_16V4Z

2

37
38

H_STP_PCI#

55

H_STP_CPU#

54

CK_CPU1

41

CK_CPU1#

40

CK_CPU0

44

CK_CPU0#

43

CK_CPU2

36

CK_CPU2#

35

33
32

SRC5

31

SRC5#

30

SRC4

26

SRC4#

27

SRC3

24

SRC3#

25

22
23

SRC1

19

SRC1#

20

SSCLK

17

SSCLK#

18

DOT96 DREFCLK

14
15

CLK_EN#

NO SHORT PADS

10
52

REFOUT

REFOUT1

1

C144

0.047U_0402_16V4Z

2

1 2

R319 33_0402_5%

1 2

R323 33_0402_5%

1 2

R309 33_0402_5%

1 2

R315 33_0402_5%

1 2

R336 33_0402_5%

1 2

R342 33_0402_5%

1 2

R499 10K_0402_5%@

1 2

R346 33_0402_5%

1 2

R352 33_0402_5%

1 2

R333 33_0402_5%

1 2

R340 33_0402_5%

1 2

R345 33_0402_5%

1 2

R349 33_0402_5%

1 2

R328 33_0402_5%

1 2

R335 33_0402_5%

1 2

R322 33_0402_5%

1 2

R326 33_0402_5%

1 2

R314 33_0402_5%

1 2

R318 33_0402_5%

12

13

D

J4

S

1 2

R297 12_0402_5%

1 2

R291 12_0402_5%

1 2

R305 12_0402_5%

1 2

R293 12_0402_5%

2

H_STP_PCI# <19>
H_STP_CPU# <19,43>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CK_ITP
CK_ITP#

+3VS

CLK_PCIE_DOCK
CLK_PCIE_DOCK#

CLK_PCIE_LOM
CLK_PCIE_LOM# CLK_PCIE_LOM#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK#DOT96#

1 2

R146 10K_0402_5%

2

G

Q20
2N7002_SOT23

CLK_14M_ICH
CLK_14M_SIO
CLK_14M_CODEC
CLK_14M_KBC

1

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CK_ITP <4>
CK_ITP# <4>
CLKREQA# <24>

CPPE# <17,33>

CLK_PCIE_DOCK <33>
CLK_PCIE_DOCK# <33>

CLK_PCIE_LOM <23>
CLK_PCIE_LOM# <23>

CLK_MCH_3GPLL <9>
CLK_MCH_3GPLL# <9>

CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>

DREF_SSCLK <7>
DREF_SSCLK# <7>

DREFCLK <7>
DREFCLK# <7>

+3VS

VGATE <7,19,43>

CLK_14M_ICH <19>
CLK_14M_SIO <29>
CLK_14M_CODEC <26>
CLK_14M_KBC <31>

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

LA-2211

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CPU_BCLK

CLK_CPU_BCLK#

CK_ITP

CK_ITP#

CLK_PCIE_DOCK

CLK_PCIE_DOCK#

CLK_PCIE_LOM

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICH

CLK_PCIE_ICH#

DREF_SSCLK

DREF_SSCLK#

DREFCLK

DREFCLK#

Clock Generator

1

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

14 48Thursday, September 09, 2004

of

R320

R324

R310

R316

R337

R343

R332

R339

R347

R353

R344

R348

R327

R334

R321

R325

R313

R317

12

12

12

12

12

12

12

12

0.6

A

CRT Connector

B

C

D

E

R542

1 2

0_0603_5%

R543

1 2

0_0603_5%

R544

1 2

0_0603_5%

C310
5P_0402_50V8C@

+5VS

F1

1.1A_6VDC_FUSE

CRTVDD+2.5VS

D18

21

2 1

CH491D_SC59

0.1U_0402_16V4Z

RED_R

GREEN_R

BLUE_R

D_DDCCLK

C315

D_DDCDATA

1

2

1 1

HSYNC<9>
VSYNC<9>

DDCCLK<9>

DDCDATA<9>

2 2

HSYNC
VSYNC

DDCCLK
DDCDATA

C319

0.22U_0603_10V7K

1

2

CRTVDD

1

U19

VCC_SYNC

SYNC_IN1
SYNC_IN2

DDC_IN1
DDC_IN2

BYP

R5 10K_0402_5%

1 2

R6 10K_0402_5%

1 2

HSYNC
VSYNC

13
15

10
11

8

C3

1 2

0.22U_0603_10V7K

+3VS

C321

1 2

0.22U_0603_10V7K

+2.5VS

7

2

VCC_DDC

VCC_VIDEO

VIDEO_1
VIDEO_2
VIDEO_3

SYNC_OUT1
SYNC_OUT2

DDC_OUT1
DDC_OUT2

GND

6

D_BLUE

3

D_GREEN

4

D_RED

5

D_HSYNC

14

D_VSYNC

16

D_DDCCLK

9

D_DDCDATA

12

CM2009_QSOP16

D_HSYNC <33>
D_VSYNC <33>

D_DDCCLK <33>
D_DDCDATA <33>

D_RED<9,33>

D_GREEN<9,33>

D_BLUE<9,33>

D_RED

D_GREEN

D_BLUE

1

C313
5P_0402_50V8C@

2

D_HSYNC

D_VSYNC

DDCCLK
DDCDATA

D_DDCCLK
D_DDCDATA

1 2
1 2

1 2
1 2

1

2

1

C314
5P_0402_50V8C@

2

R2 2.2K_0402_5%
R4 2.2K_0402_5%

R1 2.2K_0402_5%
R3 2.2K_0402_5%

CRTVDD+RCRT_VCC

W=40mils

JP2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070453FR015S208CU

TV-Out Connector

3 3

D3
DAN217_SC59@

D5
DAN217_SC59@

1

D1
DAN217_SC59@

1

1

+3VS

2

3

2

3

L3

LUMA<9,33>

CRMA<9,33>

COMPS<9,33>

1

1

2

82P_0402_50V8J

C30

2

C14

4 4

82P_0402_50V8J

A

FCM1608C-121T_0603

FCM1608C-121T_0603

FCM1608C-121T_0603

1

C6
82P_0402_50V8J

2

1 2

L5

1 2

L4

1 2

82P_0402_50V8J

B

C317

1

2

LUMA_CL

CRMA_CL

COMPS_CL

C318

82P_0402_50V8J

1

2

1

C316
82P_0402_50V8J

2

2

3

JP1

1
2
3
4
5
6
7

SUYIN_33007SR-07T1-C

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-2211

Friday, September 10, 2004

E

of

15 48

0.6