Compal LA-2211, Compaq nc4200 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Dothan uFCBGA/uFCPGA with
Intel Alviso_GM+ICH6-M core logic

3 3

4 4

A

B

2004-09-09

REV:06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Document Number Rev
Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2211

E

0.6

of

148Thursday, September 09, 2004

A

B

C

D

E

Compal confidential

File Name : LA-2211

Heavenly

1 1

DOCK/DVI

page 33

DVI controller

SiI1362

page 16

Fan Control

page 4

SDVO

H_A#(3..31)

CRT/TV-OUT

page 15

2 2

LCD CONN

page 16

Mobile Dothan/Yonah

uFCBGA-479/uFCPGA-478 CPU

page 4,5,6

FSB

400/533MHz

H_D#(0..63)

Intel Alviso GMCH

PCBGA 1257

page 7,8,9,10,11

DMI

Thermal Sensor
ADM1031AR

page 4

DDR2 -400/533

Dual Channel

USB2.0

Clock Generator

CY28430-3

page 14

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

page 12,13

USB conn x3

page 28

PCI-E BUS

BT Conn

page 28

PCI BUS

Intel ICH6-M

Gigabit LAN
BCM5751M

page 23

3 3

RTC CKT.

page 18

RJ45/11 CONN

page 24

Mini PCI
socket

page 25

CardBus Controller

TI PCI6611

page 21,22

Slot 0

page 22

SD/SDIO Slot

page 21

mBGA-609

page 17,18,19,20

LPC BUS

AC-LINK

PATA

Power OK CKT.

page 35

Power On/Off CKT.

page 32

4 4

DC/DC Interface CKT.

page 34

Security Module

Touch Pad CONN. Int.KBD

SMSC LPC47N250

page 32

page 31

page 32

SMSC Super I/O

LPC47N217

COM1 on
Docking side

page 29page 30

Audio CKT

AD1981B

page 26

PATA HDD
Connector

page 18

Flash ROM

SST49LF008A

FIR

page 30

AMP & Audio Jack

page 31

page 27

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

page 33

LPT on

Power Circuit DC/DC

36,37,38,39,40,41,42,43

A

Digitizer

page 16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Docking side

Title

Size Document Number Rev
Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2211

E

0.6

of

248Thursday, September 09, 2004

A

Voltage Rails

Power Plane

VIN
B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VALW
+1.5VS
+1.8V

+2.5VS
+3VALW
+3V

+5VALW
+5V
+5VS
+12VALW
+12V

RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

1 1

Internal PCI Devices

DEVICE

LAN
Azalia D27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V always on power rail

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

3.3V always on power rail
3V power rail

3.3V switched power rail+3VS
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail
12V power rail
12Vswitched power rail on power rail
RTC power

PCI Device ID

D8

IDSEL #

AD24

AD11
D28PCI-E
D29
D30
D30
D30
D31
D31
D31

AD12

AD13

AD14

AD14

AD14

AD15

AD15

AD15

S0-S1

N/A

ON OFF
ON
ON
ON
ON
ON
ON+1.8VS OFF OFF1.8V switched power rail

ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

S3

N/A
N/A

OFF
OFF
ON
OFF
ON

ON2.5V always on power rail+2.5VALW ON*ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF+12VS
ON

S5

N/A
N/AN/A
OFF
OFF
OFF
ON*
OFF
OFF

OFF2.5V switched power rail for MCH video PLL
ON*
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ONON

Symbol note:

:means digital ground.

:means analog ground.

:means reserved.@

External PCI Devices

DEVICE

Mini-PCI
CARD BUS

PCI Device ID

D4
D6

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0
A2
D2

IDSEL #

AD20

AD22

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 0 1 0
1 1 0 1 0 0 1 0

REQ/GNT #

0
2

PIRQ

F
A B C D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-2211

of

348Thursday, September 09, 2004

0.6

5

4

3

2

1

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>
H_ADSTB#1<7>

H_RS#[0..2]<7>

1 2
1 2

5

CK_ITP
CK_ITP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>

H_BR0#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HIT#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_TRDY#<7>

ITP_DBRESET#<19>

H_DBSY#<7>

H_DPSLP#<18>

H_DPRSTP#<18>

H_DPWR#<7>

H_PWRGOOD<18>

H_CPUSLP#<7,18>

H_THERMTRIP#<7,18>

12
12

C C

B B

A A

CK_ITP<14>
CK_ITP#<14>

CLK_CPU_BCLK<14>
CLK_CPU_BCLK#<14>

R172

1 2

+VCCP

56_0402_5%

H_PROCHOT#

R410 56_0402_5%

H_PWRGOOD

R166 200_0402_1%

TEST1

R382 1K_0402_5%@

TEST2

R416 1K_0402_5%@

H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

R203 0_0402_5%

CPU_CK_ITP

1 2

CPU_CK_ITP#

1 2

R199 0_0402_5%

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

H_PROCHOT#

H_PWRGOOD

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

+VCCP
+VCCP

JP12A

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

FOX_PZ47803-2749-01

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_D#0

A19

H_D#[0..63] <7>

ITP700FLEX FOR Dothan

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R
ITP_TRST#

RESETITP#
ITP_TCK
CK_ITP#

CK_ITP

JP19

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLK#

9

BCLK

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

ITP700-FLEXCON

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

VTT0
VTT1

VTAP
DBR#

DBA#

NC1
NC2

+VCCP

1 2

R243

1 2

200_0402_1%

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

C296

0.1U_0402_16V4Z

27
28
26

25
24

23
21
19
17
15
13

4
6

Thermal Sensor ADM1032AR

+3VS

2

C273

0.1U_0402_16V4Z

C264

1 2

2200P_0402_50V7K

R228

1 2

+3VS

10K_0402_5%

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>
H_NMI <18>

H_STPCLK# <18>
H_SMI# <18>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PWM Fan Control circuit

FAN_PWM<31>

THERM#

1

H_THERMDA
H_THERMDC THERM_SCI#

THERM#

+3VS

5

U24

1

P

INB

O

2

INA

G

TC7SH00FU_SSOP5

3

2

ITP_DBRESET#

U16

1
2
3

ADM1032AR_SOP8

Address:100_1100

4

+VCCP +VCCP

R240

54.9_0402_1%

1 2

H_RESET# RESETITP# ITP_TDO_RITP_TDO

+VCCP

1 2

R236 39.2_0603_1%

1 2

R246 150_0402_5%

VDD

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ICH_SMBCLK<8,12,13,14,19,23>

ICH_SMBDATA<8,12,13,14,19,23>

+5VS

D11
RB751V_SOD323

2 1

6

2

1

D

Q33

G

3

SI3456DV-T1_TSOP6

S

4 5

Title

Size Document Number Rev
Custom

Date: Sheet

12

R242

22.6_0402_1%

ITP_TMS
ITP_TDI

ICH_SMBCLK

8

ICH_SMBDATA

7
6
5

ICH_SMBCLK
ICH_SMBDATA

1

C122

4.7U_0805_10V4Z

2

FAN

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

LA-2211

R238

54.9_0402_1%

1 2

1 2

R237 680_0402_5%

1 2

R239 27.4_0402_1%

12

R227
10K_0402_5%

THERM_SCI# <8,19>

1

C125

0.1U_0402_16V4Z

2

1

12

R241

22.6_0402_1%

ITP_TRST#
ITP_TCK

ACES_85205-0200

of

448Thursday, September 09, 2004

JP8

1
2

0.6

5

4

3

2

1

R175

54.9_0402_1%@

D D

+1.5VS

C520

0.01U_0402_16V7K

C C

+VCCP

12

R248
1K_0402_1%

B B

A A

12

R247
2K_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

1

C298
1U_0603_10V4Z

2

1

C297
220P_0402_50V7K

2

12

54.9_0402_1%

27.4_0402_1%

R245

R244

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

12

R355

1

1

C531

2

2

10U_1206_6.3V6M

12

27.4_0402_1%

R356

54.9_0402_1%@

+VCC_CORE

CPU_VID0<43>
CPU_VID1<43>
CPU_VID2<43>
CPU_VID3<43>
CPU_VID4<43>
CPU_VID5<43>

CPU_BSEL0<14>
CPU_BSEL1<14>

12

54.9_0402_1%

1 2
1 2

R170

+VCCP

H_PSI#<43>

V_CPU_GTLREF

VCCSENSE
VSSSENSE

H_PSI#

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

JP12B

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

FOX_PZ47803-2749-01

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

POWER, GROUNG, RESERVED SIGNALS AND NC

T9 PAD
T11 PAD
T25 PAD
T30 PAD

Dothan

+VCC_CORE

JP12C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

FOX_PZ47803-2749-01

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

LA-2211

1

of

548Thursday, September 09, 2004

0.6

5

4

3

2

1

+VCC_CORE

D D

C C

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C201
10U_1206_6.3V6M

C200
10U_1206_6.3V6M

C443
10U_1206_6.3V6M

C248
10U_1206_6.3V6M

1

C222
10U_1206_6.3V6M

2

1

C190
10U_1206_6.3V6M

2

1

C460
10U_1206_6.3V6M

2

1

C189
10U_1206_6.3V6M

2

1

C237
10U_1206_6.3V6M

2

1

C433
10U_1206_6.3V6M

2

1

C475
10U_1206_6.3V6M

2

1

C450
10U_1206_6.3V6M

2

1

C254
10U_1206_6.3V6M

2

1

C432
10U_1206_6.3V6M

2

1

C469
10U_1206_6.3V6M

2

1

C208
10U_1206_6.3V6M

2

1

C253
10U_1206_6.3V6M

2

1

C438
10U_1206_6.3V6M

2

1

C484
10U_1206_6.3V6M

2

1

C474
10U_1206_6.3V6M

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C267
10U_1206_6.3V6M

C485
10U_1206_6.3V6M

C482
10U_1206_6.3V6M

1

C249
10U_1206_6.3V6M

2

1

C467
10U_1206_6.3V6M

2

1

C481
10U_1206_6.3V6M

2

1

C238
10U_1206_6.3V6M

2

1

C476
10U_1206_6.3V6M

2

1

C209
10U_1206_6.3V6M

2

1

C223
10U_1206_6.3V6M

2

1

C461
10U_1206_6.3V6M

2

1

C180
10U_1206_6.3V6M

2

1

C439
10U_1206_6.3V6M

2

1

C445
10U_1206_6.3V6M

2

1

C266
10U_1206_6.3V6M

2

Near VCORE regulator.

+VCC_CORE

1

1

+

B B

+VCCP

1

+

C203
100U_6.3V_M

2

A A

5

1

C497

0.1U_0402_16V4Z

2

1

C496

0.1U_0402_16V4Z

2

4

1

C495

0.1U_0402_16V4Z

2

C493

1

C477

0.1U_0402_16V4Z

2

330U_D2E_2.5VM_R9

@

9mOhm
7343
PS CAP

+

C456

C472

2

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

9mOhm

9mOhm

7343

7343

PS CAP

PS CAP

1

C420

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

+

+

C428

2

2

330U_D2E_2.5VM_R9

9mOhm
7343
PS CAP

1

C419

0.1U_0402_16V4Z

2

3

1

C418

0.1U_0402_16V4Z

2

1

C444

0.1U_0402_16V4Z

2

1

2

2

C468

0.1U_0402_16V4Z

1

C462

0.1U_0402_16V4Z

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-2211

1

0.6

of

648Thursday, September 09, 2004

5

4

3

2

1

U15B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO_BGA1257

V_DDR_MCH_REF<12,13>

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13

DMIDDR MUXING

CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22

CFG/RSVD

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN
DREF_CLKP

DREF_SSCLKP

CLK

DREF_SSCLKN

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC10

NC

NC11

V_DDR_MCH_REF

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG17

CFG18

CFG19

CFG20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26

RSVD27

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
VGATE
PLT_RST#

DREFCLK#
DREFCLK
DREF_SSCLK
DREF_SSCLK#

TP_NC1

TP_NC2

TP_NC3

TP_NC4

TP_NC5

TP_NC6

TP_NC7

TP_NC8

TP_NC9

TP_NC10

TP_NC11

+1.8V

12

R101
10K_0402_1%

12

R102
10K_0402_1%

CFG0 <11>
MCH_CLKSEL1 <14>
MCH_CLKSEL0 <14>

T43

PAD

T47

PAD

CFG5 <11>
CFG6 <11>
CFG7 <11>

T40

PAD

CFG9 <11>

T49

PAD
T53

PAD

CFG12 <11>
CFG13 <11>

T14

PAD
T46

PAD

CFG16 <11>

T50

PAD

CFG18 <11>
CFG19 <11>

T39

PAD
T36

PAD
T38

PAD
T41

PAD
T31

PAD
T33

PAD
T35

PAD
T37

PAD

PM_BMBUSY# <19>

H_THERMTRIP# <4,18>
VGATE <14,19,43>
PLT_RST# <16,17,18,19,29,30,31>

DREFCLK# <14>
DREFCLK <14>
DREF_SSCLK <14>
DREF_SSCLK# <14>

T7 PAD
T6 PAD
T8 PAD
T28 PAD
T27 PAD
T26 PAD
T24 PAD
T23 PAD
T4 PAD
T5 PAD
T3 PAD

PM_EXTTS#0

PM_EXTTS#1

R381

10K_0402_5%

R377

10K_0402_5%

+2.5VS

12

12

C510

12

R393

40.2_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR4
M_CLK_DDR5

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_CLK_DDR#4
M_CLK_DDR#5

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP
V_DDR_MCH_REF

1

C384

2

0.1U_0402_16V4Z

M_OCDOCMP0
M_OCDOCMP1

1

2

0.1U_0402_16V4Z

DMI_TXN0<19>

D D

C C

B B

H_A#[3..31]<4> H_D#[0..63] <4>

T13 PAD

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>

CLK_MCH_BCLK#<14>
CLK_MCH_BCLK<14>

H_DSTBN#[0..3]<4>

H_DSTBP#[0..3]<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

H_RESET#<4>
H_ADS#<4>

H_TRDY#<4>
H_DPWR#<4>
H_DRDY#<4>
H_DEFER#<4>

T57 PAD

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>
H_BR0#<4>
H_BNR#<4>
H_BPRI#<4>
H_DBSY#<4>

H_RS#[0..2]<4>

H_CPUSLP#<4,18>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_CPUSLP#

Note:
"Open for Dothan-A and Short for Dothan-B"

U15A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257

J16

1 2

SHORT PADS

Alviso

HOST

H_R_CPUSLP#

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

12

R250

24.9_0402_1%

H_SWNG1

H_SWNG0

+VCCP

R232

12

R427

24.9_0402_1%

1

2

C511

0.1U_0402_16V4Z

1

2

C512

0.1U_0402_16V4Z

12

R434

54.9_0402_1%

54.9_0402_1%

+VCCP

R249

221_0603_1%

R428

100_0402_1%

+VCCP

R435

221_0603_1%

R426

100_0402_1%

12

C483

12

12

12

12

+1.8V

+VCCP

12

R409

100_0402_1%

1

12

R412

2

0.1U_0402_16V4Z

200_0402_1%

DMI_TXN1<19>
DMI_TXN2<19>
DMI_TXN3<19>

DMI_TXP0<19>
DMI_TXP1<19>
DMI_TXP2<19>
DMI_TXP3<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXN2<19>
DMI_RXN3<19>

DMI_RXP0<19>
DMI_RXP1<19>
DMI_RXP2<19>
DMI_RXP3<19>

M_CLK_DDR0<12>
M_CLK_DDR1<12>

T51 PAD

M_CLK_DDR3<13>
M_CLK_DDR4<13>

T52 PAD

M_CLK_DDR#0<12>
M_CLK_DDR#1<12>

T54 PAD

M_CLK_DDR#3<13>
M_CLK_DDR#4<13>

T55 PAD

DDR_CKE0_DIMMA<12>
DDR_CKE1_DIMMA<12>
DDR_CKE2_DIMMB<13>
DDR_CKE3_DIMMB<13>

DDR_CS0_DIMMA#<12>
DDR_CS1_DIMMA#<12>
DDR_CS2_DIMMB#<13>
DDR_CS3_DIMMB#<13>

M_ODT0<12>
M_ODT1<12>
M_ODT2<13>

1 2
1 2

Layout Note:
Route as short
as possible

R380

M_ODT3<13>

12

40.2_0402_1%

R411 80.6_0402_1%
R407 80.6_0402_1%

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(1 of 5)

LA-2211

1

0.6

of

748Thursday, September 09, 2004

5

D D

4

3

2

1

DDR_A_BS#0<12>
DDR_A_BS#1<12>
DDR_A_BS#2<12>

DDR_A_DM[0..7]<12>

DDR_A_DQS[0..7]<12>

C C

B B

T32 PAD
T34 PAD

DDR_A_DQS#[0..7]<12>

DDR_A_MA[0..13]<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>

DDR_A_WE#<12>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

TP_MA_RCVENIN#

TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AM8
AM4

AK35
AP34
AN30
AN23

AN8
AM5
AH1

AL17
AP17
AP18
AM17
AN18
AM18

AL19
AP20
AM19

AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4
AJ2
AD3

AJ1
AE5

AE4

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

U15C

DDR_A_D0

AG35

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257

AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <12>

T45 PAD
T48 PAD

DDR_B_BS#0<13>
DDR_B_BS#1<13>
DDR_B_BS#2<13>

DDR_B_DM[0..7]<13>

DDR_B_DQS[0..7]<13>

DDR_B_DQS#[0..7]<13>

DDR_B_MA[0..13]<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>

DDR_B_WE#<13>

DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AK5
AE7
AB7

AF34
AK32

AJ28
AK23
AM10

AH6
AF8
AB4

AF35
AK33
AK28

AJ23

AL10

AH7
AF7
AB5

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

U15D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

ALVISO_BGA1257

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D0
DDR_B_D2

DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] <13>

Reserved thermal CKT and closed to JP34.

+3VS

2

C588

0.1U_0402_16V4Z @

A A

C276

1 2

2200P_0402_50V7K@

B

2

DDR_THERMDA
DDR_THERMDC

E

31

Q43

MMBT3904_SOT23@

C

1

5

U38

1

VDD

SCLK

2

D+

SDATA

3

D-

ALERT#

4

OVERT#

GND

MAX6646MUA_8UMAX@

Address:100_1101

ICH_SMBCLK

8

ICH_SMBDATA

7

R547 10K_0402_5%@

6

R548 0_0402_5%@

5

1 2
1 2

ICH_SMBCLK <4,12,13,14,19,23>
ICH_SMBDATA <4,12,13,14,19,23>

+3VS

THERM_SCI# <4,19>

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

LA-2211

1

of

848Thursday, September 09, 2004

0.6

5

4

3

2

1

+2.5VS

R501

R366

R368

R509

1
2

1 2

12

BSS138_SOT23

12

BSS138_SOT23

12

BSS138_SOT23

+3VS

5

P

IN1
IN2

G

3

S

+2.5VS

S

S

U35
SN74AHC1G08DCKR_SC70

100K_0402_5%

+1.5VS_PCIE

R149

U15G

COMPS
LUMA
CRMA

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

AB29

GCLKN

AC29

GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

12

REFSET

E25

LBKLT_CTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

ALVISO_BGA1257

MISCTVVGALVDS

EXP_RXN2/SDVO_FLDSTALL#

PCI - EXPRESS GRAPHICS

EXP_ICOMPO

EXP_RXN0/SDVO_TVCLKIN#

EXP_RXN1/SDVO_INT#

EXP_RXP0/SDVO_TVCLKIN

EXP_RXP1/SDVO_INT

EXP_RXP2/SDVO_FLDSTALL

EXP_TXN0/SDVOB_RED#

EXP_TXN1/SDVOB_GREEN#

EXP_TXN2/SDVOB_BLUE#

EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#

EXP_TXN5/SDVOC_GREEN#

EXP_TXN6/SDVOC_BLUE#

EXP_TXN7/SDVOC_CLKN

EXP_TXP0/SDVOB_RED

EXP_TXP1/SDVOB_GREEN

EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP

EXP_TXP4/SDVOC_RED

EXP_TXP5/SDVOC_GREEN

EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP

SDVO_SDAT<16>
SDVO_SCLK<16>

CLK_MCH_3GPLL#<14>

D D

C C

B B

CLK_MCH_3GPLL<14>

COMPS<15,33>

LUMA<15,33>

CRMA<15,33>

DDCCLK<15>

DDCDATA<15>

VSYNC<15>
HSYNC<15>

ENAVDD<16>

TXACLK-<16>
TXACLK+<16>
TXBCLK-<16>
TXBCLK+<16>

TXA0-<16>
TXA1-<16>
TXA2-<16>

TXA0+<16>
TXA1+<16>
TXA2+<16>

TXB0-<16>
TXB1-<16>
TXB2-<16>

TXB0+<16>
TXB1+<16>
TXB2+<16>

12

R391

4.99K_0603_1%

VGA_BLU
VGA_GRN
VGA_RED

R389

255_0402_1%

BKLT_CTL
ENABLT

LCD_I2C_CLK
LCD_I2C_DAT
ENAVDD
LIBG

TXACLK­TXACLK+
TXBCLK­TXBCLK+

TXA0­TXA1­TXA2-

TXA0+
TXA1+
TXA2+

TXB0­TXB1­TXB2-

TXB0+
TXB1+
TXB2+

EXP_COMPI

EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

24.9_0402_1%

1 2

SDVO_INT-

0.1U_0402_16V4Z

SDVO_INT+

0.1U_0402_16V4Z

SDVO_R-

C374 0.1U_0402_16V4Z

SDVO_G­SDVO_B­SDVO_CLK-

SDVO_R+

C375 0.1U_0402_16V4Z

SDVO_G+
SDVO_B+
SDVO_CLK+

C372

C373

C367 0.1U_0402_16V4Z

C368 0.1U_0402_16V4Z

SDVOB_INT- <16>

SDVOB_INT+ <16>

C370 0.1U_0402_16V4Z

C371 0.1U_0402_16V4Z

C365 0.1U_0402_16V4Z

C366 0.1U_0402_16V4Z

SDVOB_R- <16>
SDVOB_G- <16>
SDVOB_B- <16>
SDVOB_CLK- <16>

SDVOB_R+ <16>
SDVOB_G+ <16>
SDVOB_B+ <16>
SDVOB_CLK+ <16>

2.2K_0402_5%

LCD_I2C_CLK

2.2K_0402_5%

LCD_I2C_DAT

BKLT_CTL

2.2K_0402_5%

LID_SW#<19,32>

LID_SW#
ENABLT

2.2K_0402_5%

+3VS

12

G

2

G

2

G

2

O

R361

Q38

2.2K_0402_5%

13

D

+3VS

12

R365

Q39

2.2K_0402_5%

13

D

+5VS+2.5VS

12

R510

Q56

2.2K_0402_5%

13

D

Q53
DTA114YKA_SC59

+5VS

47K

10K

4

R360

2

G

1 2

2

13

D

S

LCD_I2C_CLK_C <16>

LCD_I2C_DAT_C <16>

BKLT_CTL_C <16>

13

Q36

BSS138_SOT23

+5VS_INV

LIBG

R351

1.5K_0402_1%

A A

5

COMPS
LUMA
CRMA

12

VGA_RED
VGA_GRN
VGA_BLU

12

R195

75_0402_1%

12

R384

75_0402_1%

12

R198

75_0402_1%

12

R383

75_0402_1%

R200

75_0402_1%

R386

75_0402_1%

4

12

VGA_RED D_RED

VGA_GRN GREEN_LL

VGA_BLU

12

L23

1 2

HLC0603CSCC39NJT_0603

L24

1 2

HLC0603CSCC39NJT_0603

L25

1 2

HLC0603CSCC39NJT_0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Layout Note:
Place these components as close
as possible to Alviso-GM.

RED_LL

BLUE_LL

1

C153

2

18P_0402_50V8J

1

2

C152
18P_0402_50V8J

1

2

L18

1 2

HLC0603CSCCR11JT_0603

L19

1 2

HLC0603CSCCR11JT_0603

L20

1 2

HLC0603CSCCR11JT_0603

C151

18P_0402_50V8J

D_GREEN

D_BLUE

2

D_RED <15,33>

D_GREEN <15,33>

D_BLUE <15,33>

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

LA-2211

1

of

948Thursday, September 09, 2004

0.6

5

U15F

K13

D D

+VCCP

1

C471

C414

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

C C

1

C282

0.47U_0603_10V7K

2

1

1

C288

2

2

0.47U_0603_10V7K

B B

CHB1608U301_0603

1 2

+1.5VS

+VCCP

A A

1

1

C459

C415

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C299

C522

2

0.22U_0603_10V7K

0.22U_0603_10V7K

ALVISO_BGA1257

+1.5VS_DPLLA +1.5VS_DPLLB

L22

1

1

+

C172

C184

2

1

C525

2

10U_1206_6.3V6M

2

0.1U_0402_16V4Z

470U_D2_2.5VM

1

1

C403

C490

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

CHB1608U301_0603

+1.5VS +1.5VS +1.5VS

1

C434

2

0.1U_0402_16V4Z

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

L21

1 2

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

C261

10U_1206_6.3V6M

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

1

+

C140

2

470U_D2_2.5VM

+1.8V

C412

0.1U_0402_16V4Z

1

2

1

2

Note : All VCCSM pin
shorted internally.

C171

10U_1206_6.3V6M

1

C389

2

0.1U_0402_16V4Z

C448

0.1U_0402_16V4Z

1

2

1

2

+1.8V

1

C217

2

220U_D2_4M_R45

@

1

C464

2

0.1U_0402_16V4Z

4

U15E

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C479

C524

0.1U_0402_16V4Z

470U_D2_2.5VM

1

2

T29
R29
N29

M29

K29
J29
V28

U28

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21
W20
U20

T20

K20

V19
U19

K19
W18

V18

T18

K18

K17
AC1

AC2

B23
C35
AA1
AA2

+1.5VS_HPLL

1

+

C513

2

0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO_BGA1257

1

2

POWER

CHB1608U301_0603

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

1 2

+VCCP

1

1

2

1

2

0.1U_0402_16V4Z

4

C383

2

0.1U_0402_16V4Z

1

C508

2

0.1U_0402_16V4Z

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL
+1.5VS_MPLL

CHB1608U301_0603

1 2

1

C411

2

0.1U_0402_16V4Z

C382

C494

+1.5VS

L50

1

2

C400

0.1U_0402_16V4Z

C509

0.1U_0402_16V4Z

1

+

2

1

C425

2

3

R401

D28

+1.5VS_TVDAC_D

2 1

+1.5VS

RB751V_SOD323

+3VS

F17

+3VS_TVDACA
E17
D18

+3VS_TVDACB
C18
F18

+3VS_TVDACC
E18

H18

+3VS_ATVBG
G18

D19

+1.5VS
H17

+1.5VS_QTVDAC
B26

+1.5VS
B25

A25
A35

+2.5VS
B22

VCCHV0
VCCHV1
VCCHV2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCC_SYNC

L49

C523

470U_D2_2.5VM

+2.5VS_CRTDAC
B21

A21
B28

+2.5VS
A28

+1.5VS_DDRDLL

A27
AF20

AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

+1.5VS_MPLL

1

+

C505

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C447

C454

2

0.1U_0402_16V4Z

+2.5VS_CRT

1

C449

2

0.022U_0402_16V7K

1

2

0.1U_0402_16V4Z

Route VSSATVBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+1.5VS_QTVDAC

C427

0.022U_0402_16V7K

1

+

2

100U_D2_6.3VM

C129

220U_D2_4M_R45

L42 CHB1608U301_0603

1 2

1

C442

2

0.1U_0402_16V4Z

2 1

+VCCP

RB751V_SOD323

+2.5VS

10_0805_1%

1 2

PJP11

2 1

PAD-SHORT 2x2m

L40

CHB1608U301_0603

1

1

C435

2

2

0.1U_0402_16V4Z

+1.5VS_PCIE

1

1

+

C381

C380

2

2

0.22U_0603_10V7K
10U_1206_6.3V6M

1

C431

C590

2

0.1U_0402_16V4Z

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

D14

+VCCP_CRTDAC_D

2

+3VS_TVDAC

+1.5VS

12

1

1

C409

C436

2

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

+1.5VS_3GPLL

1

1

C379

2

1

+

2

150U_B2_4VM

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Alviso.

2

10U_1206_6.3V6M

C406

+2.5VS_CRTDAC

R182

10_0805_1%

1 2

PJP12

2 1

PAD-SHORT 2x2m

2

1

C405

2

0.1U_0402_16V4Z

+3VS_TVDACA

+3VS_TVDACB

R372

0.5_0805_1%

1 2

1

2

10U_1206_6.3V6M

1

2

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+2.5VS_CRTDAC

1

C457

C480

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

C215

C214

2

0.1U_0402_16V4Z

0.022U_0402_16V7K

3GRLL_R

L16

CHB1608U301_0603

C134

0.1U_0402_16V4Z

CHB1608U301_0603

1

2

CHB1608U301_0603

1

2

BLM18PG600SN1_0603

BLM18PG600SN1_0603

BLM18PG600SN1_0603

Title

Size Document Number Rev
Custom

Date: Sheet

12

L44

L26

L39

L35

L38

+2.5VS+2.5VS_3GBG

1

2

+2.5VS

C399

10U_1206_6.3V6M

LA-2211

+3VS_TVDAC

12

12

12

12

+1.5VS

12

C413

0.1U_0402_16V4Z

1

2

1

+3VS_TVDACC

+3VS_ATVBG

+1.5VS

C369

1

0.1U_0402_16V4Z

2

C133

0.1U_0402_16V4Z

1

C392

C404

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

1

C466

C453

2

0.022U_0402_16V7K

1

C451

C452

2

0.022U_0402_16V7K

+1.5VS

1

C421

2

1

0.1U_0402_16V4Z

2

1

2

CHB1608U301_0603

1

2

0.1U_0402_16V4Z

CHB1608U301_0603

1

2

0.1U_0402_16V4Z

+2.5VS_CRTDAC

1

C426

2

10U_1206_6.3V6M

L43

L41

C429

0.1U_0402_16V4Z

Compal Electronics, Inc.

Alviso(4 of 5)

1

10 48Thursday, September 09, 2004

+3VS_TVDAC

12

+3VS_TVDAC+3VS_TVDAC

12

1

2

of

0.6

5

4

3

2

1

+VCCP

U15H

L12

VTT_NCTF17

M12

VTT_NCTF16

N12

AA12
AA13

AA14
AB14

AA15
AB15

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

R12
U12
W12
M13

N13
R13
U13
W13

M14
N14

R14
U14
W14

M15
N15

R15
U15
W15

M16
N16

R16
U16
W16

R17

R21

W25
M26

N26
R26
U26
W26

P12
T12
V12
L13

P13
T13
V13

Y12
Y13
L14

P14
T14
V14
Y14

L15

P15
T15
V15
Y15

L16

P16
T16
V16
Y16

Y17

Y21

Y22

Y23

Y24

Y25

Y26

V25
L26

P26
T26
V26

VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO_BGA1257

D D

C C

B B

A A

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.8V

+VCCP

AG7

AA10

Y1
D2
G2

J2

L2

P2

T2

V2

AD2
AE2
AH2
AL2
AN2

A3
C3

AA3
AB3
AC3

AJ3

C4
H4

L4

P4
U4

Y4

AF4
AN4

E5

W5
AL5
AP5

B6
J6
L6
P6

T6
AA6
AC6
AE6

AJ6

G7

V7
AA7

AK7
AN7

C8

E8

L8

P8

Y8
AL8

A9

H9

K9

T9

V9
AA9
AC9
AE9
AH9
AN9
D10

L10

Y10

F11
H11
Y11

U15I

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

ALVISO_BGA1257

VSS

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24

AN24

W27
AA27
AB27
AF27
AG27

AJ27
AL27

AN27

W28
AA28
AB28
AC28

W29
AA29
AD29
AG29

AJ29

AM29

AA30
AB30
AC30
AE30
AP30

M31

W31
AD31
AG31

AL31

AA32
AB32

A26
E26

G26

J26
B27
E27
G27

E28

A29
D29
E29
F29
G29
H29

L29
P29
U29
V29

C30
Y30

D31
E31
F31
G31
H31

J31
K31

L31
N31

P31
R31
T31
U31
V31

A32
C32
Y32

U15J

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

ALVISO_BGA1257

VSS

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG[13:12]
CFG16

(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

CFG0<7>

CFG5<7>
CFG6<7>
CFG7<7>
CFG9<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>

Refer to page14 for FSB
frequency select

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I

*

*

Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane

*

High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)

*

High = 1.5V
Low = 1.05V (Default)
High = 1.2V

R394 10K_0402_5%

R398 2.2K_0402_5%@
R395 2.2K_0402_5%
R192 2.2K_0402_5%@
R399 2.2K_0402_5%@
R404 2.2K_0402_5%@
R408 2.2K_0402_5%@
R397 2.2K_0402_5%@

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG[17:3] have internal pull-up

R379 1K_0402_5%@

1 2

R378 1K_0402_5%@

1 2

CFG[19:18] have internal pull-down

*

*

*
*

+VCCP

+2.5VS

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Alviso(5 of 5)

LA-2211

1

0.6

of

11 48Thursday, September 09, 2004

5

4

3

2

1

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..13]<8>

D D

+1.8V

2.2U_0805_16V4Z
C458

1

2

0.1U_0402_16V4Z

C255

1

2

C C

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

B B

A A

C229

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C250

C239

5

RP27

1 4
2 3

RP29

1 4
2 3

RP32

1 4
2 3

RP31

1 4
2 3

RP33

1 4
2 3

2 3
1 4

C498

1

1

2

2

0.1U_0402_16V4Z
C242

1

2

0.1U_0402_16V4Z

1

1

2

2

C272

C257

+0.9VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

RP35

56_0404_4P2R_5%

C473

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C491

1

2

0.1U_0402_16V4Z

C280

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C279

C281

RP22 56_0404_4P2R_5%

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

RP26 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP25 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP28 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP30 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP34 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP24 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

C235

0.1U_0402_16V4Z

C465

1

2

0.1U_0402_16V4Z

1

2

C274

1

2

C268

Layout Note:
Place near JP34

10P_0402_50V8J

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C252

M_CLK_DDR0

1

C394

2

M_CLK_DDR#0

0.1U_0402_16V4Z

1

1

2

2

C234

C241

Layout Note:
Place these resistor
closely JP34,all
trace length<750 mil

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.3"

4

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1

M_CLK_DDR1

10P_0402_50V8J

1

C534

2

M_CLK_DDR#1

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<7>

0.1U_0402_16V4Z

1

2

C227

M_ODT1<7>

ICH_SMBDATA<4,8,13,14,19,23>

ICH_SMBCLK<4,8,13,14,19,23>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
ICH_SMBDATA

ICH_SMBCLK

0.1U_0402_16V4Z

+3VS

C308

+1.8V

JP34

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1

2

VDDSPD

FOX_ASOA426-M4R-TR

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

2

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

+1.8V

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D14

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R453

R455

10K_0402_5%

10K_0402_5%

12

Title

Size Document Number Rev
Custom

Date: Sheet

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C363

2

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2211

C362

1

V_DDR_MCH_REF <7,13>

12 48Thursday, September 09, 2004

of

0.6

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

+1.8V

+0.9VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C176

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

2.2U_0805_16V4Z

1

2

1

2

C179

RP14

1 4
2 3

RP17

56_0404_4P2R_5%

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

RP18

56_0404_4P2R_5%

1 4
2 3

RP19

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP23

2 3
1 4

56_0404_4P2R_5%

2.2U_0805_16V4Z

C236

0.1U_0402_16V4Z
C166

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C186

+0.9VS

5

C265

1

1

2

2

0.1U_0402_16V4Z
C219

1

2

0.1U_0402_16V4Z

1

1

2

2

C197

RP10 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP15 56_0404_4P2R_5%

RP21 56_0404_4P2R_5%

RP9

56_0404_4P2R_5%

C247

0.1U_0402_16V4Z

C213

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1

2

C188

1

2

0.1U_0402_16V4Z

1

2

C220

DDR_B_MA9

14

DDR_B_MA12

23

DDR_CKE3_DIMMB

14

DDR_B_MA11

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

M_ODT2

14

DDR_B_MA13

23

DDR_B_BS#2

14

DDR_CKE2_DIMMB

23

C159

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C183

C161

C164

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C199

C210

4

Layout Note:
Place near JP10

M_CLK_DDR3

10P_0402_50V8J

1

C121

2

M_CLK_DDR#3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C173

Layout Note:
Place these resistor
closely JP10,all
trace length<750 mil

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.3"

1

1

2

2

C163

C218

4

3

+1.8V

JP10

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

M_CLK_DDR4

10P_0402_50V8J

1

C285

2

M_CLK_DDR#4

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>

DDR_B_WE#<8>

0.1U_0402_16V4Z

1

2

C177

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

ICH_SMBDATA<4,8,12,14,19,23>

ICH_SMBCLK<4,8,12,14,19,23>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
ICH_SMBDATA

ICH_SMBCLK

+3VS

1

C301

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM B

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

12

R254

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C89

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR4 <7>
M_CLK_DDR#4 <7>

R257

1 2

10K_0402_5%

Title

Size Document Number Rev
Custom

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2211

1

V_DDR_MCH_REF <7,12>

C90

1

13 48Thursday, September 09, 2004

0.6

of

5

FSC FSB FSA CPU

CLKSEL0 CLKSEL2

CLKSEL1

00

011

D D

CLK-RaCPU Type

Dothan-A PSB400
Dothan-A PSB533
Dothan-B

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

B B

+3VS

1 2

A A

1 2

OPEN 1K Ohm

SHORT 1K Ohm OPEN

+VCCP

CLKSEL0

J17

1 2

SHORT PADS

CLK-Ra

+VCCP

J18

1 2

SHORT PADS

CLK-Rd

R148

10K_0402_5%@

96*_100MSEL

R150
10K_0402_5%

5

SRC
MHz

100
100100

PCI
MHz

33.3

33.3

CLK-Rc

OPEN
0 Ohm

MCH_CLKSEL0 <7>

MCH_CLKSEL1 <7>

CLK-Rd CLK-Re

OPEN
OPEN

MHz

1331

R147
1K_0402_5%

CLK-Rb

1 2

1 2

R137
1K_0402_5%

R145

0_0402_5%@

CLK-Rc

1 2

R153
1K_0402_5%

CLK-Rf

1 2

1 2

R155
1K_0402_5%

R154

0_0402_5%@

CLK-Re

1 2

CLK-Rb

OPENOPEN

SS frequency selection

96*_100MSEL 96_100MSST/C

LOW
HIGH

96 MHZ
100 MHZ

CLK_PCI_FWH<30>

4

+3VS

PJP13

1 2

PAD-SHORT 3x3m

1

C117

2

0.1U_0402_16V4Z

CLK-Rf

0 Ohm
0 Ohm
OPEN0 Ohm

C361

33P_0402_50V8J

C364

33P_0402_50V8J

CLK_48M_CB<21>

CLK_48M_ICH<19>

CLK_PCI_EC<31>

CLK_PCI_PCM<21>

CLK_PCI_MINI<25>

CLK_PCI_SIO<29>

CLK_PCI_TCG<30>

CLK_PCI_ICH<17>

OPEN
OPEN
1K Ohm

Place crystal within
500 mils of CK410M

12

12

Y3

14.31818MHZ_20P_6X1430004201

12

CLK_48M_CB
CLK_48M_ICH

CLK_PCI_EC
CLK_PCI_PCM
CLK_PCI_FWH
CLK_PCI_MINI
CLK_PCI_SIO PCICLK2

CLK_PCI_TCG PCICLK2
CLK_PCI_ICH PCICLKF0

4

PJP14

1 2

PAD-SHORT 3x3m

CK_XTAL_IN

CK_XTAL_OUT

R296 10K_0402_5%

+3VS

R302 12_0402_5%
R308 12_0402_5%
R489 2.2K_0402_5%
R152 475_0402_1%

R298 12_0402_5%
R299 12_0402_5%
R294 33_0402_5%
R295 33_0402_5%
R290 12_0402_5%

R303

10K_0402_5%

1 2

+3VS

ICH_SMBCLK<4,8,12,13,19,23>

ICH_SMBDATA<4,8,12,13,19,23>

1 2

R292 12_0402_5%
R304 33_0402_5%

R511 10K_0402_5%@

J27

1 2

SHORT PADS

R521

1 2

0_0402_5%@

+3VS

CLKSEL0_R

REFOUT REFOUT1

CK_VDD_MAIN

CK_VDD_MAIN2

12
12

12
12
12

12
12
12
12
12

R331 475_0402_1%

12
12

PCICLK2

12

CLKSEL2
CLKSEL0_RCLKSEL0
CLKIREF1

PCICLK5
PCICLK4
PCICLK3

96*_100MSEL

PCICLKF0
ICH_SMBCLK

ICH_SMBDATA

CLKIREF

3

2

Width=40mils

2

C407
10U_1206_6.3V6M

1

1

C142
1U_0603_10V4Z

2

Width=40mils

2

C113
10U_1206_6.3V6M

1

U25

21
28
34

1
7

42
48

11

50
49

12
53

16

5
4
3

56

9

8

46

47

39

13
29

2
45
51

6

IDTCV140PAG_TSSOP56

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C136

0.047U_0402_16V4Z

2

1

C141

0.047U_0402_16V4Z

2

1

C130

0.047U_0402_16V4Z

2

VDDSRC_0
VDDSRC_1
VDDSRC_2

VDDPCI_0
VDDPCI_1

VDDCPU
VDDREF

VDD48

XIN
XOUT

FS_A/USB_48MHz
FS_C/TEST_SEL/REF1

FS_B/TEST_MODE

PCICLK5
PCICLK4
PCICLK3
PCICLK2/SEL_CLKREQ
PCICLK_F1/96*_100MSEL

PCICLK_F0/ITP_EN
SCLK

SDATA

IREF

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5

1

C137

0.047U_0402_16V4Z

2

1

C139

0.047U_0402_16V4Z

2

1

C131

0.047U_0402_16V4Z

2

VDDA

GNDA

PCI/SRC_STOP#

CPU_STOP#

CPUCLKT1

CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/SRCCLKT_7

CPUCLKC2_ITP/SRCCLKC_7

SRCCLKT6/CLKREQA#

SRCCLKC6/CLKREQB#

SRCCLKT5

SRCCLKC5

SRCCLKT4_SATA
SRCCLKC4_SATA

SRCCLKT3
SRCCLKC3

SRCCLKT2
SRCCLKC2

SRCCLKT1
SRCCLKC1

96_100MSST/SRCCLKT0

96_100MSSC/SRCCLKC0

DOTT_96MHz
DOTC_96MHz

VTT_PWRGD#/PD

REF0/FS_D

1

C143

0.047U_0402_16V4Z

2

1

C135

0.047U_0402_16V4Z

2

1

C126

0.047U_0402_16V4Z

2

37
38

H_STP_PCI#

55

H_STP_CPU#

54

CK_CPU1

41

CK_CPU1#

40

CK_CPU0

44

CK_CPU0#

43

CK_CPU2

36

CK_CPU2#

35

33
32

SRC5

31

SRC5#

30

SRC4

26

SRC4#

27

SRC3

24

SRC3#

25

22
23

SRC1

19

SRC1#

20

SSCLK

17

SSCLK#

18

DOT96 DREFCLK

14
15

CLK_EN#

NO SHORT PADS

10
52

REFOUT

REFOUT1

1

C144

0.047U_0402_16V4Z

2

1 2

R319 33_0402_5%

1 2

R323 33_0402_5%

1 2

R309 33_0402_5%

1 2

R315 33_0402_5%

1 2

R336 33_0402_5%

1 2

R342 33_0402_5%

1 2

R499 10K_0402_5%@

1 2

R346 33_0402_5%

1 2

R352 33_0402_5%

1 2

R333 33_0402_5%

1 2

R340 33_0402_5%

1 2

R345 33_0402_5%

1 2

R349 33_0402_5%

1 2

R328 33_0402_5%

1 2

R335 33_0402_5%

1 2

R322 33_0402_5%

1 2

R326 33_0402_5%

1 2

R314 33_0402_5%

1 2

R318 33_0402_5%

12

13

D

J4

S

1 2

R297 12_0402_5%

1 2

R291 12_0402_5%

1 2

R305 12_0402_5%

1 2

R293 12_0402_5%

2

H_STP_PCI# <19>
H_STP_CPU# <19,43>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CK_ITP
CK_ITP#

+3VS

CLK_PCIE_DOCK
CLK_PCIE_DOCK#

CLK_PCIE_LOM
CLK_PCIE_LOM# CLK_PCIE_LOM#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DREF_SSCLK
DREF_SSCLK#

DREFCLK#DOT96#

1 2

R146 10K_0402_5%

2

G

Q20
2N7002_SOT23

CLK_14M_ICH
CLK_14M_SIO
CLK_14M_CODEC
CLK_14M_KBC

1

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CK_ITP <4>
CK_ITP# <4>
CLKREQA# <24>

CPPE# <17,33>

CLK_PCIE_DOCK <33>
CLK_PCIE_DOCK# <33>

CLK_PCIE_LOM <23>
CLK_PCIE_LOM# <23>

CLK_MCH_3GPLL <9>
CLK_MCH_3GPLL# <9>

CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>

DREF_SSCLK <7>
DREF_SSCLK# <7>

DREFCLK <7>
DREFCLK# <7>

+3VS

VGATE <7,19,43>

CLK_14M_ICH <19>
CLK_14M_SIO <29>
CLK_14M_CODEC <26>
CLK_14M_KBC <31>

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

LA-2211

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CPU_BCLK

CLK_CPU_BCLK#

CK_ITP

CK_ITP#

CLK_PCIE_DOCK

CLK_PCIE_DOCK#

CLK_PCIE_LOM

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICH

CLK_PCIE_ICH#

DREF_SSCLK

DREF_SSCLK#

DREFCLK

DREFCLK#

Clock Generator

1

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

1 2

49.9_0402_1%

14 48Thursday, September 09, 2004

of

R320

R324

R310

R316

R337

R343

R332

R339

R347

R353

R344

R348

R327

R334

R321

R325

R313

R317

12

12

12

12

12

12

12

12

0.6

A

CRT Connector

B

C

D

E

R542

1 2

0_0603_5%

R543

1 2

0_0603_5%

R544

1 2

0_0603_5%

C310
5P_0402_50V8C@

+5VS

F1

1.1A_6VDC_FUSE

CRTVDD+2.5VS

D18

21

2 1

CH491D_SC59

0.1U_0402_16V4Z

RED_R

GREEN_R

BLUE_R

D_DDCCLK

C315

D_DDCDATA

1

2

1 1

HSYNC<9>
VSYNC<9>

DDCCLK<9>

DDCDATA<9>

2 2

HSYNC
VSYNC

DDCCLK
DDCDATA

C319

0.22U_0603_10V7K

1

2

CRTVDD

1

U19

VCC_SYNC

SYNC_IN1
SYNC_IN2

DDC_IN1
DDC_IN2

BYP

R5 10K_0402_5%

1 2

R6 10K_0402_5%

1 2

HSYNC
VSYNC

13
15

10
11

8

C3

1 2

0.22U_0603_10V7K

+3VS

C321

1 2

0.22U_0603_10V7K

+2.5VS

7

2

VCC_DDC

VCC_VIDEO

VIDEO_1
VIDEO_2
VIDEO_3

SYNC_OUT1
SYNC_OUT2

DDC_OUT1
DDC_OUT2

GND

6

D_BLUE

3

D_GREEN

4

D_RED

5

D_HSYNC

14

D_VSYNC

16

D_DDCCLK

9

D_DDCDATA

12

CM2009_QSOP16

D_HSYNC <33>
D_VSYNC <33>

D_DDCCLK <33>
D_DDCDATA <33>

D_RED<9,33>

D_GREEN<9,33>

D_BLUE<9,33>

D_RED

D_GREEN

D_BLUE

1

C313
5P_0402_50V8C@

2

D_HSYNC

D_VSYNC

DDCCLK
DDCDATA

D_DDCCLK
D_DDCDATA

1 2
1 2

1 2
1 2

1

2

1

C314
5P_0402_50V8C@

2

R2 2.2K_0402_5%
R4 2.2K_0402_5%

R1 2.2K_0402_5%
R3 2.2K_0402_5%

CRTVDD+RCRT_VCC

W=40mils

JP2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070453FR015S208CU

TV-Out Connector

3 3

D3
DAN217_SC59@

D5
DAN217_SC59@

1

D1
DAN217_SC59@

1

1

+3VS

2

3

2

3

L3

LUMA<9,33>

CRMA<9,33>

COMPS<9,33>

1

1

2

82P_0402_50V8J

C30

2

C14

4 4

82P_0402_50V8J

A

FCM1608C-121T_0603

FCM1608C-121T_0603

FCM1608C-121T_0603

1

C6
82P_0402_50V8J

2

1 2

L5

1 2

L4

1 2

82P_0402_50V8J

B

C317

1

2

LUMA_CL

CRMA_CL

COMPS_CL

C318

82P_0402_50V8J

1

2

1

C316
82P_0402_50V8J

2

2

3

JP1

1
2
3
4
5
6
7

SUYIN_33007SR-07T1-C

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-2211

Friday, September 10, 2004

E

of

15 48

0.6

5

4

3

2

1

LCD POWER CIRCUIT LCD/PANEL BD. CONN.

B+_LCD

C586

12

+5VALWLCDVDD

D D

100_0402_1%

2N7002_SOT23

ENAVDD<9>

C C

R19

Q5

ENAVDD

12

13

D

S

R12
100K_0402_5%

1 2

2

G

13

Q6

2

DTC124EK_SC59

LCDVDD

12

R474
100_0402_5%

0.1U_0402_16V4Z

1

C28

0.047U_0402_16V4Z

2

1

2

C29

Q8

SI2301DS_SOT23

1 3

1

C31

4.7U_0805_10V4Z

2

+3VALW

2

1

C20

4.7U_0805_10V4Z

2

INV_PWM<31>

BKLT_CTL_C<9>

J8 No SHORT PADS

1 2

J9 SHORT PADS

1 2

LCD_I2C_CLK_C<9>
LCD_I2C_DAT_C<9>

0.1U_0603_50V4Z
C587

12

68P_0402_50V8J

L62

1 2

B+

KC FBM-L11-201209-221LMAT_0805

DIGI_TX<31>
DIGI_RX<31>

DIG_RESET#<19>

ALS_EN<17>

+5VS_INV

KSI_D_8<31,32>
KSI_D_9<31,32>

KSI_D_10<31,32>
KSI_D_11<30,31,32>

KSO14<31,32>

PID0

PID0<29>

PID1<29>

+3VS

LCDVDD

DIGI_TX
DIGI_RX

PID1
ALS_EN

LCD_I2C_CLK_C
LCD_I2C_DAT_C
KSI_D_8
KSI_D_9
KSI_D_10
KSI_D_11
KSO14

JP28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

ACES_88107-5000G

TXBCLK­TXBCLK+

TXB0­TXB0+

TXB1­TXB1+

TXB2­TXB2+DIG_RESET#

TXACLK+
TXACLK-

TXA2+
TXA2-

TXA1+
TXA1-

TXA0­TXA0+

TXBCLK- <9>
TXBCLK+ <9>

TXB0- <9>
TXB0+ <9>

TXB1- <9>
TXB1+ <9>

TXB2- <9>
TXB2+ <9>

TXACLK+ <9>
TXACLK- <9>

TXA2+ <9>
TXA2- <9>

TXA1+ <9>
TXA1- <9>

TXA0- <9>
TXA0+ <9>

DVI CONTROLLER

DVI_DVDD_2.5V

DVI_AVDD_3V
DVI_DVDD_2.5V

B B

+2.5VS

12

R497

10K_0402_5%DVI_7307@

W=20 mils

12

R103

1.2K_0402_5%DVI_7307@

A A

5

SDVOB_INT+<9>
SDVOB_INT-<9>

SDVOB_R+<9>
SDVOB_R-<9>

SDVOB_G+<9>
SDVOB_G-<9>

SDVOB_B+<9>
SDVOB_B-<9>

SDVOB_CLK+<9>
SDVOB_CLK-<9>

PLT_RST#<7,17,18,19,29,30,31>

R107

10K_0402_5%DVI_7307@

ASAS
PLT_RST#

12

R498

1 2

U11

32

SDVOB_INT+

33

SDVOB_INT-

37

SDVOB_R+

38

SDVOB_R-

40

SDVOB_G+

41

SDVOB_G-

43

SDVOB_B+

44

SDVOB_B-

46

SDVOB_CLK+

47

SDVOB_CLK-

3

AS

2

RESET#

25

VSWING

27

ATPG

26

SCEN

10K_0402_5%DVI_7307@

4

28

DVDD12DVDD

DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL

DVI_DVDD_2.5V

1

48

21

TVDD15TVDD

AVDD36AVDD42AVDD

TLC#

6

TLC

TDC0#

TDC0

TDC1#

TDC1

TDC2#

TDC2

HPDET

SC_DDC
SD_DDC

SC_PROM
SD_PROM

SPD
SPC

NC

NC

CH7307C_LQFP48

35

34

AVDD_PLL

DVI_CLK-

13

DVI_CLK+

14

DVI_TX0-

16

DVI_TX0+

17

DVI_TX1-

19

DVI_TX1+

20

DVI_TX2-

22

DVI_TX2+

23

DVI_DETECT

29

DVI_DDC_CLK

11

DVI_DDC_DAT

10
9

8

SDVO_SDAT

5

SDVO_SCLK

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DVI_CLK- <33>
DVI_CLK+ <33>
DVI_TX0- <33>
DVI_TX0+ <33>
DVI_TX1- <33>
DVI_TX1+ <33>
DVI_TX2- <33>
DVI_TX2+ <33>

DVI_DETECT <33>
DVI_DDC_CLK <33>

DVI_DDC_DAT <33>

SDVO_SDAT <9>
SDVO_SCLK <9>

DVI_DDC_DAT

C115

C358

C104

0.1U_0402_16V4ZDVI_7307@

DVI_AVDD_3V

0.1U_0402_16V4Z

SDVO_SDAT
SDVO_SCLK

1

2

2

C359

R131 5.6K_0402_5%

1 2

R132 5.6K_0402_5%

1 2

C584
150P_0402_50V8J

0.1U_0402_16V4ZDVI_7307@

0.1U_0402_16V4Z

+5VS +5VS

12

R301
30K_0402_5%

PJP23

2 1

PAD-SHORT 2x2m

1

C123

10U_1206_16V4ZDVI_7307@

2

PJP24

2 1

PAD-SHORT 2x2m

1

C360
10U_1206_16V4Z

2

DVI_DDC_CLK

Title

Size Document Number Rev
Custom

Date: Sheet

+2.5VS

+3VS

+2.5VS

12

R300
30K_0402_5%

Compal Electronics, Inc.

DVI (SiI1362)/LCD CONN.

LA-2211

Thursday, September 09, 2004

1

of

16 48

0.6

5

4

3

2

1

D D

+3VS

+3VS

+3VS

C C

+3VS

+3VS

+3VS

RP39

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP36

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP38

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP46

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP47

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

RP37

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_SERR#

PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
PCI_DEVSEL#

PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQD#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
RUNSCI_EC#

PCI_REQ5#
PCI_REQ3#
PCI_REQ1#
PCI_REQ4#

PCI_REQ0#
PCI_REQ2#
PCI_PIRQH#

R473

1 2

0_0402_5%@

PCI_AD[0..31]<21,25>

+3VS

R472
10K_0402_5%

1 2

CPPE# <14,33> PCI_PIRQE# <21>

PCI_FRAME#<21,25>

PCI_PIRQC#<21>
PCI_PIRQD#<21>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

T20PAD
T19PAD
T56PAD
T21PAD
T12PAD
T15PAD
T44PAD
T42PAD
T22PAD

U26B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

ICH6_BGA609

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PLTRST#

PCICLK

PME#

PCI_REQ0#

L5

PCI_GNT0#

C1

PCI_REQ1#

B5
B6

PCI_REQ2#

M5

PCI_GNT2#

F1

PCI_REQ3#

B8
C8

PCI_REQ4#

F7
E7

PCI_REQ5#

E8

ALS_EN#

F6

RUNSCI_EC#

B7

NPCI_RESET

D8

PCI_C_BE0#

J6

PCI_C_BE1#

H6

PCI_C_BE2#

G4

PCI_C_BE3#

G2

PCI_IRDY#

A3

PCI_PAR

E1

PCIRST#

R2

PCI_DEVSEL#

C3

PCI_PERR#

E3

PCI_PLOCK#

C5

PCI_SERR#

G5

PCI_STOP#

J1

PCI_TRDY#

J2

PLTRST#

R5

CLK_ICH_PCI

G6

PCI_PME#

P6

PCI_PIRQE#

D9

PCI_PIRQF#

C7

PCI_PIRQG#

C6

PCI_PIRQH#

M3

PCI_REQ0# <25>
PCI_GNT0# <25>

T17 PAD

PCI_REQ2# <21>
PCI_GNT2# <21>

T16 PAD

RUNSCI_EC# <31>
NPCI_RESET <29>

PCI_CBE#0 <21,25>
PCI_CBE#1 <21,25>
PCI_CBE#2 <21,25>
PCI_CBE#3 <21,25>

PCI_IRDY# <21,25>
PCI_PAR <21,25>

PCI_DEVSEL# <21,25>
PCI_PERR# <21,25>

PCI_SERR# <21,25,31>
PCI_STOP# <21,25>
PCI_TRDY# <21,25>

CLK_PCI_ICH <14>
PCI_PME# <21,25>

PCI_PIRQF# <25>
PCI_PIRQG# <21>

ALS_EN#

CLK_PCI_ICH

+5VS

R433
330_0402_5%

1 2

ALS_EN

13

D

Q45

2

2N7002_SOT23

G

S

R216

10_0402_5%@

1 2
1

C260

10P_0402_50V8J@

2

ALS_EN <16>

B B

1

C289

0.1U_0402_16V4Z@

2

U17

5

PCIRST#

A A

5

4

1

IN1

2

IN2

1 2

SHORT PADS

SN74AHC1G08DCKR_SC70@

P

PCI_RST#

4

O

G

3

J19

PCI_RST# <19,21>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CKT Notice : Used for BCM5751M A0 die only.

+3VS+3VS

1

C529

0.1U_0402_16V4Z@

2

5

U30

1

P

INB

4

PLTRST#

O

2

INA

G

TC7SH00FU_SSOP5@

3

33K_0402_5%@

1U_0603_10V4Z@

R234

C295

J20

1 2

SHORT PADS

J21

1 2

SHORT PADS

+3VS

1

C517

0.1U_0402_16V4Z@

2

5

U29

1

P

12

INB

2

INA

1

2

PLT_RST# <7,16,18,19,29,30,31>

2

LOM_PLT_RST#

4

O

G

TC7SH00FU_SSOP5@

3

Title

Size Document Number Rev
Custom

Date: Sheet

LOM_PLT_RST# <23>

Compal Electronics, Inc.

ICH6(1/4)

LA-2211

1

17 48Thursday, September 09, 2004

0.6

of

5

C516

D D

32.768KHZ_12.5P_1TJS125BJ2A251

+RTCVCC

12

R221
1M_0402_1%

INTRUDER#

C C

B B

+RTCVCC

AC97_BITCLK<26,32>

AC97_RST#<26,32>

18P_0402_50V8J

Y4

2

NC

3

OUT

NC

C528

18P_0402_50V8J

1 2

R230
20K_0402_5%

CMOS_CLR1

SHORT PADS

1U_0603_10V4Z

10P_0402_50V8J@

AC97_SYNC<26,32>

1 2

AC97_SDIN0<26>
AC97_SDIN1<32>

AC97_SDOUT<26,32>

R390 4.7K_0402_5%

+3VS

1 2

R191 8.2K_0402_5%

1 2

12

IN

12

1 2

C287

1 2

C231

1 2

4

ICH_RTCX1

ICH_RTCX2

R202

10_0402_5%@

12

R432

10M_0402_5%

ICH_RTCRST#
INTRUDER#

12

AC97_BITCLK
AC97_SYNC

AC97_RST_R#
AC_SDIN0

AC_SDIN1

AC97_SDOUT

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

U26A

AC19

AG2

AG6

AG11
AF11

AF16
AB16
AB15
AC14
AE16

Y1

Y2
AA2
AA3

AA5

D12
B12
D11
F13

F12
B11
E12

E11
C13

C12
C11
E13

C10

B9
A10
F11

F10
B10

C9

AE3
AD3

AF2
AD7

AC7
AF6

AC2
AC1

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH6_BGA609

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

A20GATE

A20M#

LAN

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

RCIN#

STPCLK#

THRMTRIP#

DCS1#
DCS3#

SATAAC-97/AZALIA

PIDE

DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

INIT#
INTR

SMI#

DA[0]
DA[1]
DA[2]

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]

NMI

1
4

R39633_0402_5%

3

LPC_LAD0

P2

LPC_LAD1

N3

LPC_LAD2

N5

LPC_LAD3

N4

LPC_DRQ#0

N6

LPC_DRQ#1

P4

LPC_FRAME#

P3

GATEA20

AF22

H_A20M#

AF23

CPUSLP# H_CPUSLP#

AE27
AE24

H_DPSLP#

AD27

FERR# H_FERR#

AF24

H_PWRGOOD

AG25

H_IGNNE#

AG26

FWH_INIT#

AE22

H_INIT#

AF27

H_INTR

AG24

KB_RST#

AD23

H_NMI

AF25

H_SMI#

AG27

H_STPCLK#

AE26

THRMTRIP#

AE23

PD_A0

AC16

PD_A1

AB17

PD_A2

AC17

PD_CS#1

AD16

PD_CS#3

AE17

PD_D0

AD14

PD_D1

AF15

PD_D2

AF14

PD_D3

AD12

PD_D4

AE14

PD_D5

AC11

PD_D6

AD11

PD_D7

AB11

PD_D8

AE13

PD_D9

AF13

PD_D10

AB12

PD_D11

AB13

PD_D12

AC13

PD_D13

AE15

PD_D14

AG15

PD_D15

AD13

PD_DREQ

AB14

LPC_AD0 <29,30,31>
LPC_AD1 <29,30,31>
LPC_AD2 <29,30,31>
LPC_AD3 <29,30,31>

LPC_DRQ#0 <29>
LPC_DRQ#1 <30>

LPC_FRAME# <29,30,31>

GATEA20 <31>
H_A20M# <4>

R160 0_0402_5%@

R165 56_0402_5%

12

J22

1 2

SHORT PADS

12

H_PWRGOOD <4>
H_IGNNE# <4>

FWH_INIT# <30>
H_INIT# <4>
H_INTR <4>

KB_RST# <31> H_THERMTRIP# <4,7>

H_NMI <4>
H_SMI# <4>

H_STPCLK# <4>

R177

1 2

10K_0402_5%

R174

10K_0402_5%

1 2

2

H_FERR#

H_DPRSTP#

C

2

B

E

+VCCP

12

100_0402_5%@

1

Q40

2SC2411K_SC59@

3

R168
56_0402_5%

H_THERMTRIP#

CPU Type

Dothan-A

+3VS

H_DPRSTP#DPRSTP#

+3VS

Dothan-B

H_CPUSLP# <4,7>
H_DPRSTP# <4>

H_DPSLP# <4>
H_FERR# <4>

J22

OPEN

SHORT

+VCCP

R160

0 Ohm

OPEN

+VCCP

330_0402_5%@

1 2

1 2

1U_0603_10V6K@

R173

C178

1 2

R167
75_0402_1%

R164
56_0402_5%

R476

12

+VCCP

12

THRMTRIP#

1

12

R161
56_0402_5%@

MAINPWON <39,41,44>

PATA CONN

JP23

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

SUYIN_200227MR044SX17ZU_NORMAL

PD_D8
PD_D9PD_D6
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_CSEL

PD_A2
PD_CS#3

1 2

R458 470_0402_5%

+5VS

+5VS

PLT_RST#
PD_D7

PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_DREQ
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQ
PD_A1
PD_A0
PD_CS#1
HDD_LED#

+5VS

PLT_RST#<7,16,17,19,29,30,31>

1

2

C557
10U_1206_16V4Z

2

+RTCVCC

1 2

100_0603_1%

2

C100

0.1U_0402_16V4Z

1

A A

R122

D10

1

DAN202U_SC70

5

CHGRTC

3

BATT1.2

2

R121

1 2

511_0603_1%

BATT1.1

W=20mils

JP32

E&T_7651

-+

21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C554

0.1U_0402_16V4Z

2

Place component's closely IDE CONN.

HDD_LED#<32>

1

C555

0.1U_0402_16V4Z

2

+3VS

12

R181

10K_0402_5%

Title

Size Document Number Rev
Custom

Date: Sheet

HDD_LED#

Compal Electronics, Inc.

LA-2211

1

C556

0.1U_0402_16V4Z

2

ICH6(2/4)

1

18 48Thursday, September 09, 2004

0.6

of

5

4

3

2

1

SB_SPKR<26>
LPC_PD#<30,31>

OVP_OV#<38>

LID_SW#<9,32>

BT_OFF<28>

LP_EN#<24>

M24_RST#<21>
FWH_WP#<30>

FWH_TBL#<30>

T18 PAD

SLP_S3#<23,26,27,31,33,34>

PM_POK<31>

DPRSLPVR<43>

PLT_RST#<7,16,17,18,29,30,31>

R214
10K_0402_5%

R224
240_0402_5%

R223
10K_0402_5%

+3VALW

12

R225

10K_0402_5%

ICH_RI#

RP20 100_1206_8P4R_5%

XMIT<25>

SIRQ<21,29,30,31>

VGATE<7,14,43>

R217 0_0402_5%@

SLP_S5#

J25 SHORT PADS

LINKALERT#

ITP_DBRESET#

LOW_BAT# LAN_PCIE_WAKE#

4 5
3 6
2 7
1 8

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SB_SPKR

LPC_PD#
ITP_DBRESET#
PM_BMBUSY#
ISO_PREP#

ICH_GPI8
OVP_OV#
PANEL_FLIP#

LID_SW#
H_STP_PCI#
MINIPCI_RST

DIG_RESET#
XMIT
BT_OFF

LP_EN#
M24_RST#
PM_CLKRUN#
FWH_WP#
FWH_TBL#

ICH_PCIE_WAKE#
SIRQ
THERM_SCI#
VGATE
CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#

1 2

1 2

PM_POK
DPRSLPVR
ICH_LOW_BAT#
ON/OFFBTN#
PLT_RST#
PM_RSMRST#

R229

12

10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

U26C

T2

RI#

AF17

SATA[0]GP/GPI[26]

AE18

SATA[1]GP/GPI[29]

AF18

SATA[2]GP/GPI[30]

AG18

SATA[3]GP/GPI[31]

Y4

SMBCLK

W5

SMBDATA

Y5

LINKALERT#

W4

SMLINK[0]

U6

SMLINK[1]

AG21

MCH_SYNC#

F8

SPKR

W3

SUS_STAT#/LPCPD#

U2

SYS_RESET#

AD19

BM_BUSY#/GPI[6]

AE19

GPI[7]

R1

GPI[8]

W6

SMBALERT#/GPI[11]

M2

GPI[12]

R6

GPI[13]

AC21

STP_PCI#/GPO[18]

AB21

GPO[19]

AD22

STP_CPU#/GPO[20]

AD20

GPO[21]

AD21

GPO[23]

V3

GPIO[24]

P5

GPIO[25]

R3

GPIO[27]

T3

GPIO[28]

AF19

CLKRUN#/GPIO[32]

AF20

GPIO[33]

AC18

GPIO[34]

U5

WAKE#

AB20

SERIRQ

AC20

THRM#

AF21

VRMPWRGD

E10

CLK14

A27

CLK48

V6

SUSCLK

T4

SLP_S3#

T5

SLP_S4#

T6

SLP_S5#

AA1

PWROK

AE20

DPRSLPVR/TP[1]

V2

BATLOW#/TP[0]

U1

PWRBTN#

V5

LAN_RST#

Y3

RSMRST#

ICH6_BGA609

12

10K_0402_5%

R219

+3VS

+3VS

V_3P3_LAN

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PERn[1]
PERp[1]

PETn[1]
PETp[1]

PERn[2]
PERp[2]

PETn[2]
PETp[2]

PERn[3]
PERp[3]

PETn[3]
PETp[3]

GPIO

PERn[4]
PERp[4]

PETn[4]

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETp[4]

DMI[0]RXN

DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

DMI[1]RXN

DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

DMI[2]RXN

DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

DMI[3]RXN

DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

DMI_CLKN

DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]

OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

OC[0]#
OC[1]#
OC[2]#
OC[3]#

USBP[0]N
USBP[0]P
USBP[1]N

CLOCK

USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P

USB

USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N

POWER MGT

USBP[7]P

USBRBIAS#

USBRBIAS

R179
10K_0402_5%

1 2

R178
10K_0402_5%

1 2

R218
1K_0402_5%

1 2

H25
H24
G27
G26

K25
K24
J27
J26

M25
M24
L27
L26

P24
P23
N27
N26

T25
T24
R27
R26

V25
V24
U27
U26

Y25
Y24
W27
W26

AB24
AB23
AA27
AA26

AD25
AC25

F24
F23
C23

D23
C25
C24

C27
B27
B26
C26

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

A22
B22

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2H_STP_CPU#

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
SLEEP#

CB_IN#
USB_OC#6
USB_OC#7

USB_OC#0
USB_OC#1
USB_OC#2_R
USB_OC#3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USBRBIAS

MCH_SYNC#

SIRQ

PCIE_RXN1 <23>
PCIE_RXP1 <23>

PCIE_RXN2 <33>
PCIE_RXP2 <33>

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>

DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

CLK_PCIE_ICH# <14>
CLK_PCIE_ICH <14>

R163 24.9_0402_1%

1 2

R502 0_0402_5%@
J23 SHORT PADS

USB_OC#0 <28>
USB_OC#1 <28>
USB_OC#2_R <28>

USB20_N0 <28>
USB20_P0 <28>
USB20_N1 <28>
USB20_P1 <28>
USB20_N2 <28>
USB20_P2 <28>
USB20_N3 <28>
USB20_P3 <28>
USB20_N4 <33>
USB20_P4 <33>
USB20_N5 <33>
USB20_P5 <33>

R171

1 2

22.6_0402_1%

2

C386 0.1U_0402_16V4Z

1 2

C385 0.1U_0402_16V4Z

C387 0.1U_0402_16V4Z

1 2

C388 0.1U_0402_16V4Z

+1.5VS

1 2

1 2

1000P_0402_50V7K

USB_OC#6

1 2

1 2

LOM_LOW_PWR <23,24>
CABLE_DETECT <24>

USB_OC#2_R

1

C96

2

+3VS

R508
10K_0402_5%

1 2
2

G

1 3

D

S

Q55

2N7002_SOT23

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

LA-2211

PCIE_TXN1 <23>
PCIE_TXP1 <23>

PCIE_TXN2 <33>
PCIE_TXP2 <33>

R545

1 2

1K_0402_5%

SLEEP#
USB_OC#6
USB_OC#7
USB_OC#3

LANLINK_STATUS# <23,24,33>

ICH6(3/4)

USB_OC#2 <28>

R546

1 2

10K_0402_5%

RP8

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

1

+3VALW

19 48Thursday, September 09, 2004

of

0.6

+3VALW+3VALW

12

12

D D

ICH_SMBDATA<4,8,12,13,14,23>

ICH_SMBCLK<4,8,12,13,14,23>

+3VALW

OVP_OV#

+3VALW

C C

MINIPCI_RST#<25>

B B

A A

LID_SW#

+3VALW

ICH_GPI8

PCI_RST#<17,21>

12

J24
SHORT PADS

R490

10K_0402_5%@

12

12

12

5

R206

R205
10K_0402_5%

R207
10K_0402_5%

R46
10K_0402_5%

4

12

CLK_14M_ICH<14>

CLK_48M_ICH<14>

2.2K_0402_5%

+3VS

Y

R204

2.2K_0402_5%

10K_0402_5%

PREP#<24,33>

PM_CLKRUN#

5

1

P

B

2

A

G

3

U34
TC7SH08FU_SSOP5@

R209

1 2

10K_0402_5%

V_3P3_LAN

R522

+3VS

12

R180
10K_0402_5%

MINIPCI_RST

R201

C246

R208

12

1 2

2

1

10K_0402_5%

@

@

1 2

ICH_SMLINK0
ICH_SMLINK1
ICH_SMBDATA
ICH_SMBCLK

RB751V_SOD323

PANEL_FLIP#

LAN_PCIE_WAKE#<23>

LOW_BAT#<31>

CLK_14M_ICH

CLK_48M_ICH

10_0402_5%

1 2

2

1

10P_0402_50V8J

D35

+3VALW

V_3P3_LAN

+3VALW

R338

10_0402_5%

@

C376

10P_0402_50V8J

@

+3VS

21

+3VS

12

R187
10K_0402_5%

ISO_PREP#PREP#

12

R226
10K_0402_5%

R532
1K_0402_5%

1 2

BSS138_SOT23

S

R533
10K_0402_5%

1 2

D38

RB751V_SOD323

ITP_DBRESET#<4>

PM_BMBUSY#<7>

PANEL_FLIP#<32>

H_STP_PCI#<14>

H_STP_CPU#<14,43>

DIG_RESET#<16>

+3VL

PM_CLKRUN#<21,25,29,30,31>

THERM_SCI#<4,8>

SLP_S4#<40>
SLP_S5#<21,22,23,28,34,40>

ON/OFFBTN#<32>

PM_RSMRST#<31>

1 2

1 2

1 2

Q71

D

13

G

2

21

+3VALW

+3VALW

4

5

4

3

2

1

Near PIN F27(C155),
P27(C154), AB27(C157)

+1.5VS

1

2

+

D D

10_0402_5%

R169

10_0402_5%

R189

+5VALW

+5VS

1 2

1 2

+3VALW

+3VS

21

D15
RB751V_SOD323

2

C221
1U_0603_10V4Z

1

21

D13
RB751V_SOD323

ICH_V5REF_SUS

2

C162
1U_0603_10V4Z

1

ICH_V5REF_RUN

2

C212

0.1U_0402_16V4Z

1

2

C174

0.1U_0402_16V4Z

1

+5VALW

R197

10_0402_5%@

1 2

C C

C378

2

1

2

C251

0.1U_0402_16V4Z

C155

1

220U_D2_4M_R45

+1.5VS

Near PIN AG5

+1.5VS

+3VS

Near PIN
E26, E27

Near PIN AG9

+1.5VS

2

C158

1

0.1U_0402_16V4Z

Near PIN AE1

+3VALW

L17

CHB1608U301_0603

1 2

+1.5VS

B B

ICH6_VCCDMIPLL

R459

0.5_0805_1%

1 2

C145

0.1U_0402_16V4Z

2

1

ICH6_VCCPLL

1

C146

2

0.01U_0402_16V7K

Near PIN
AC27

0.1U_0402_16V4Z

C283

@

C196

C154

0.1U_0402_16V4Z

2

1

2

1

C275

C245

2

1

0.1U_0402_16V4Z

2

C157

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

ICH6_VCCPLL

+3VS

+3VS

+3VALW

2

C195

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U26E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

ICH6_BGA609

COREIDE

PCIE

PCIUSB

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

SATA

USB CORE

PCI/IDE RBP

VCCSUS3_3[20]

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]

VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]

V5REF[1]
V5REF_SUS
VCCUSBPLL

VCCRTC

Near PIN A17

A A

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VS

C182

ICH_V5REF_RUN

ICH_V5REF_SUS

0.1U_0402_16V4Z

C225

C269

1

2

+1.5VS

1

2

2

1

2

1

+1.5VALW

+1.5VS
+3VALW

+RTCVCC

+1.5VS

+VCCP

C167

0.1U_0402_16V4Z

2

C198

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C278

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C256

Near PIN U7

Near PIN AG23

+3VS

Near PIN
AG13, AG16

+3VS

2

C284

1

0.1U_0402_16V4Z

Near PIN
A2-A6, D1-H1

2

1

1

2

C259

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5VS

1

2

C185

Near PIN AB18

+3VS

C226

0.1U_0402_16V4Z

1 2

C240

1 2

0.1U_0402_16V4Z

Near PIN AG10

+1.5VALW

0.1U_0402_16V4Z

+1.5VS

C149

0.1U_0402_16V4Z

1 2

C233

0.1U_0402_16V4Z

1 2

C169

0.1U_0402_16V4Z

1 2

C193

0.1U_0402_16V4Z

1 2

C194

0.1U_0402_16V4Z

1 2

C216

0.1U_0402_16V4Z

1 2

C170

0.1U_0402_16V4Z

1 2

C168

0.1U_0402_16V4Z

1 2

C230

0.1U_0402_16V4Z

1 2

C232

0.1U_0402_16V4Z

1 2

C160

0.01U_0402_16V7K

1 2

Near PIN A25

C181

0.01U_0402_16V7K

1 2

Near PIN AA19

+3VALW

C258

0.1U_0402_16V4Z

1 2

C207

0.1U_0402_16V4Z

1 2

C187

0.1U_0402_16V4Z

1 2

C165

0.1U_0402_16V4Z

1 2

Near PIN A24

U26D

E27

VSS[172]

Y6

VSS[171]

Y27

W25
W24
W23

U25
U24
U23
U15
U13

R25
R24
R23
R17
R16
R15
R14
R13
R12
R11

N17
N16
N15
N14
N13
N12
N11

M27
M26
M23
M16
M15
M14
M13
M12

H27
H26
H23

G21
G12

Y26
Y23
W7

W1

V4
V27
V26
V23

T7
T27
T26
T23
T16
T15
T14
T13
T12

T1

R4

P22
P16
P15
P14
P13
P12

N7

N1

M4

L25
L24
L23
L15
L13

K7
K27
K26
K23

K1

J4
J25
J24
J23

G9
G7

G1

VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

ICH6_BGA609

+RTCVCC

1

2

C277

0.1U_0402_16V4Z

GROUND

1

2

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

C286

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

0.1U_0402_16V4Z

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

ICH6(4/4)

LA-2211

1

20 48Thursday, September 09, 2004

0.6

of

A

B

C

D

E

AO3413_SOT23@

D

S

+3VALW

+3V

1

C101

2

10U_1206_16V4Z

MC_PWR_CTRL

F1
F2

SD_CARD_DET#

E3
F5
F6

G5
F3
H5
G3
G2
G1

J5

SD_CMD

J3

SD0

H3

SD1

J6

SD2

J1

SD3

J2

SD_WP

H7

J7
K1
K2

L2
K5
K3

R91 10K_0402_5%

K7
L1
L3
L5

P12
W17
T19

CLK_48M_CB

M1

R133 4.7K_0402_5%

R17

U18
U19
U15
V15
W15
V14
W14
U17
V18
W18
V16
W16
M11
P15
R19
R18
R12
U13
V13

R283

56_0402_5%

12

CLK_48M_CB

12

R282

10_0402_5%@

2

C348

10P_0402_50V8J@

1

SD_CLKSD_CLK_6611

+5VS

CLK_48M_CB <14>

+3V

SLP_S5<25,33,34>

SD_3VCC

C38

0.1U_0402_16V4Z

M24_RST#<19>

SLP_S5#<19,22,23,28,34,40>

R284

10_0402_5%@

15P_0402_50V8J@

+3V

1

C91

C74

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U23B

U2

AD31

V1

AD30

V2

AD29

U3

AD28

W2

AD27

V3

AD26

U4

AD25

V4

AD24

V5

AD23

U5

AD22

R6

AD21

P6

AD20

W6

AD19

V6

AD18

U6

AD17

R7

AD16

V9

AD15

U9

AD14

R9

AD13

N9

AD12

V10

AD11

U10

AD10

R10

AD9

N10

AD8

V11

AD7

U11

AD6

R11

AD5

W12

AD4

V12

AD3

U12

AD2

N11

AD1

W13

AD0

W4

C/BE3#

W7

C/BE2#

W9

C/BE1#

W11

C/BE0#

P9

PAR

V7

FRAME#

R8

TRDY#

U7

IRDY#

W8

STOP#

N8
W5

V8
U8
U1

T2

P5
R3

T1

T3
R2

L7
N3

M5

P1

P2

P3
N5
R1

M3
M2

H2

DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#

PCICLK
PCIRST#
GRST#
RI_OUT#/PME#

SUSPEND#
SPKROUT
MFUNC0

MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

SCL
SDA

VR_EN#

R93

1

C351

2

1U_0603_10V4Z

1

C112

2

1U_0603_10V4Z

M19

H1

W10

VCCP

VCCP

VR_PORT

VR_PORT

PCI6611/6411

VSSPLL

VSSPLL

T17

P14

1

C106

2

0.1U_0402_16V4Z

T18

V19

VDPLL_15

VDPLL_33

MS_CLK/SD_CLK/SM_EL_WP#

MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1

MS_SDIO(DATA0)/SD_DAT0/SM_D0

SD_CLK/SM_RE#/SC_GPIO1

SD_CMD/SM_ALE/SC_GPIO2

SD_DAT0/SM_D4/SC_GPIO6
SD_DAT1/SM_D5/SC_GPIO5
SD_DAT2/SM_D6/SC_GPIO4
SD_DAT3/SM_D7/SC_GPIO3

AGND

AGND

AGND

N12

U14

U16

1

C111

C114

2

1U_0603_10V4Z

0.01U_0402_16V7K

R13

R14

V17

AVDD

AVDD

AVDD

MC_PWR_CTRL_0
MC_PWR_CTRL_1

SD_CD#
MS_CD#
SM_CD#

MS_BS/SD_CMD/SM_WE#

SD_WP/SM_CE#

SM_CLE/SC_GPIO0

SM_R#/SC_RFU

SM_PHYS_WP#/SC_FCB

SC_CD#

SC_CLK

SC_RST

SC_VCC_5V

SC_DATA

SC_OC#

SC_PWR_CTRL

TEST0

CLK_48

PHY_TEST_MA

PCI6611ZHK_PBGA288

RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

1

2

NC

1

2

W3

1 1

1 2

+3V

SIRQ<19,29,30,31>

1 2

1 2
1 2

1 2

PCI_AD[0..31]
PCI_CBE#[0..3]

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

100_0402_1%

CLK_PCI_PCM
GRST#

43K_0402_5%

FM_LED

CLK_PCI_PCM

12

R288

1

C347

2

PCI_AD[0..31]<17,25>

PCI_CBE#[0..3]<17,25>

2 2

PCI_PAR<17,25>

PCI_FRAME#<17,25>

PCI_TRDY#<17,25>

PCI_IRDY#<17,25>

PCI_STOP#<17,25>

PCI_AD22

3 3

PM_CLKRUN#<19,25,29,30,31>

4 4

PCI_DEVSEL#<17,25>

PCI_PERR#<17,25>
PCI_SERR#<17,25,31>
PCI_REQ2#<17>
PCI_GNT2#<17>

CLK_PCI_PCM<14>

PCI_RST#<17,19>

PCI_PME#<17,25>

PCM_SPK#<26>

PCI_PIRQC#<17>
PCI_PIRQD#<17>
PCI_PIRQG#<17>

PCI_PIRQE#<17>

R488 220_0402_5%@
R285 220_0402_5%

R286 220_0402_5%
R287 220_0402_5%

13

G

2

SLP_S5 SLP_S5

2

G

FM_LED

MC_PWR_CTRL

RB751V_SOD323

RB751V_SOD323

22P_0402_50V8J@

1 2

10K_0402_5%

D22

RB751V_SOD323@

D21

RB751V_SOD323@

0.01U_0402_16V7K

12

R531

13

D

S

D33

2 1

D34

2 1

C43

C33

4.7U_0805_10V4Z

R279

21

21

C352

PJP15

1 2

PAD-SHORT 3x3m

470_0402_5%@

Q67

2N7002_SOT23@

R33 10_0402_5%@

12

1

2

+3V

Q66

+3VS

+3VS

R21

10K_0402_5%

100P_0402_50V8J

SD_CARD_DET#
SD1

SD0
SD_CLK

SD_CMD
SD3

SD2

+3V

5

U22

P

2

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

12

C55

12

SD_CARD_DET#
SD_WP

GRST#

+5VALW

U3

3

VIN

4

VIN/CE

2

GND

RT9701-CB_SOT23-5

JP27

MMC_DET#10Wr_Pt_Vss

8

SD4

7

SD3

6

Vss2

5

SDCLK

4

Vdd

3

Vss1

2

SD2

1

SD1

9

SD5

MOLEX_67913-0001

GRST# <22>

AO3413_SOT23@

R51 47K_0402_5%@
R280 47K_0402_5%@

+5V

Q68

D

S

13

G

2

2

G

VOUT
VOUT

1
5

Vss3
Vss4

Wr_Pt

PJP16

1 2

PAD-SHORT 3x3m

12

R534

470_0402_5%@

13

D

Q69

2N7002_SOT23@

S

11

12
13
14

SD_3VCC

+3V

+5VS

SD_WP

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

TI PCI6611 PCI/SD

LA-2211

E

0.6

of

21 48Friday, September 10, 2004

A

B

C

D

E

1 1

2 2

3 3

4 4

+3V

1

1

1

1

C85

C97

C109

2

2

10U_1206_16V4Z

CB_CLK<31>

C110

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CB_DAT
CB_CLK
CB_LATCH

1

1

C99

2

0.1U_0402_16V4Z

1

1

C98

C107

0.1U_0402_16V4Z

U23A

DATA
CLOCK
LATCH

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

C108

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H10

H11

H12

J12

M10

M12

K12

N7

D19

K19

VCC

VCC

VCCJ8VCCM7VCC

VCCM9VCC

VCC

VCCK8VCC

VCC

VCCB

VCCB

PCI 6611/6411

A_CSTSCHG/A_BVD1(STSCHG/RI)

GND

GNDK9GND

GND

GNDL8GNDL9GND

GND

GND

GND

M8

L10

L11

L12

J10

J11

K10

K11

2

0.1U_0402_16V4Z

N1

L6

N2

B15
A16
B16

A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19
F15
G18
K14
M18
K13
G19
H17

J13

J17
H19

J19

J18
B18
E18

J15
F14
A18
H18
B19
F17
C17
N13
B17
C18
F19
N17
A15
K15

1

C354

2

A11

VCCH8VCCH9VCC

A_CAD31/A_D10

VCCAA5VCCA

A_CAD30/A_D9
A_CAD29/A_D1
A_CAD28/A_D8
A_CAD27/A_D0
A_CAD26/A_A0
A_CAD25/A_A1
A_CAD24/A_A2
A_CAD23/A_A3
A_CAD22/A_A4
A_CAD21/A_A5
A_CAD20/A_A6

A_CAD19/A_A25

A_CAD18/A_A7
A_CAD17/A_A24
A_CAD16/A_A17

A_CAD15/A_IOWR#

A_CAD14/A_A9

A_CAD13/A_IORD#

A_CAD12/A_A11
A_CAD11/A_OE#

A_CAD10/A_CE2#

A_CAD9/A_A10

A_CAD8/A_D15

A_CAD6/A_D13

A_CAD4/A_D12

A_CAD2/A_D11

A_CC/BE3#/A_REG#

A_CC/BE2#/A_A12

A_CC/BE1#/A_A8

A_CC/BE0#/A_CE1#

A_CPAR/A_A13

A_CFRAME#/A_A23

A_CTRDY#/A_A22

A_CIRDY#/A_A15

A_CSTOP#/A_A20

A_CDEVSEL#/A_A21

A_CBLOCK#/A_A19

A_CPERR#/A_A14

A_CSERR#/A_WAIT#

A_CREQ#/A_INPACK#

A_CGNT#/A_WE#

A_CCLKRUN#/A_WP(IOIS16)

A_CCLK/A_A16

A_CINT#/A_READY(IREQ)

A_CRST#/A_RESET

A_CAUDIO/A_BVD2(SPKR#)

A_CCD1#/A_CD1#
A_CCD2#/A_CD2#

A_CVS1/A_VS1#
A_CVS2/A_VS2#

A_CRSVD/A_D14

A_CRSVD/A_D2

A_CRSVD/A_A18

GNDG7GNDG8GND

GND

GNDJ9GND

PCI6611ZHK_PBGA288

H13

G13

1

C356

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A_CAD7/A_D7
A_CAD5/A_D6
A_CAD3/A_D5
A_CAD1/A_D4

A_CAD0/A_D3

A_USB_EN#
B_USB_EN#

S1_VCC

D1
C1
D3
C2
B1
B4
A4
E6
B5
C6
B6
G9
C7
B7
A7
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14

C5
F9
B10
G12

G10
C8
A8
B8
A9
C9
E10
F10
B3
E7
B9
B2
C3
E9
C4

A6
A2
C15

E5
A3
E8

B13
D2
C10

E2
E1

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

S1_RST
S1_BVD2
S1_CD1#

S1_CD2#
S1_VS1
S1_VS2

S1_D14
S1_D2
S1_A18

S1_VCC
S1_VPP

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

GRST#<21>

SLP_S5#<19,21,23,28,34,40>

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
69
71
73
75
77
79
81
83

CB_DAT
CB_CLK
CB_LATCH
GRST#

SLP_S5#

S1_VPP

S1_VCC

JP7

1

GND

2

S1_D3

3
4
5
6
7
8
9

S1_CD1#

S1_D4

S1_D11

S1_D5

S1_D12

S1_D6

S1_D13

S1_D7

S1_D14

S1_CE1#

S1_D15

S1_A10

S1_CE2#

S1_OE#

S1_VS1

S1_A11

S1_IORD#

S1_A9

S1_IOWR#

S1_A8

S1_A17

S1_A13

S1_A18

S1_A14

S1_A19

S1_WE#

S1_A20

S1_RDY#

S1_A21

S1_VCC

S1_VCC

S1_VPP

S1_VPP

S1_A16

S1_A22

S1_A15

S1_A23

S1_A12

S1_A24

S1_A7

S1_A25

S1_A6

S1_VS2

S1_A5

S1_RST

S1_A4

S1_WAIT#

S1_A3

S1_INPACK#

S1_A2

S1_REG#

S1_A1

S1_BVD2

S1_A0

S1_BVD1
S1_D0
S1_D1
S1_D2

S1_D10

S1_WP

S1_CD2#
GND
GND
GND
GND
GND
GND
GND
GND
GND

FOX_WZ21131-G2-P4_LT

GND

S1_D8
S1_D9

GND
GND
GND
GND
GND
GND
GND
GND
GND

U10

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

NC0

9

AVCC

10

AVCC

17

NC1

18

NC2

TPS2220ADBR_SSOP24

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
72
74
76
78
80
82
84

12V
12V

NC3

3.3V

NC4

GND

NC5
NC6
NC7
NC8

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

20
7

14
13

24
2

5V

1

5V

11

23
22
16
6

+3V

1

+5V

C355

2

1

C68

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

Near to PCMCIA slot.

S1_VCC

S1_VCC
S1_VPP

1

C353
10U_1206_16V4Z

2

S1_VPP

1

C344
10U_1206_16V4Z

2

J5

CARDBUS HOUSING

S1_CD1#

S1_CD2#

1

C346

0.1U_0402_16V4Z

2

1

C345

0.1U_0402_16V4Z

2

C357

1 2

100P_0402_50V8J

C21

1 2

100P_0402_50V8J

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

TI PCI6611 CB socket

LA-2211

E

0.6

of

22 48Thursday, September 09, 2004

5

4

3

2

1

Layout Notice : Place as close
chip as possible.

+3VALW

V_3P3_LAN

+3VS

+3VS

R14

5

R_CLK_PCI_LAN

18

R_LPC_AD0

27

R_LPC_AD1

36

R_LPC_AD2

45

R_LPC_AD3

18

R_LPC_FRAME#

27

R_PLT_RST#

36

R_SIRQ

45

R_CLK_PCI_LAN
R_LPC_AD0
R_LPC_AD1
R_LPC_AD2
R_LPC_AD3
R_LPC_FRAME#
R_PLT_RST#
R_SIRQ

1 2

1 2
1 2

1 2

5751_GPIO1
ICH_SMBCLK

ICH_SMBDATA
5751_EECLK
5751_EEDAT

R73

1 2

4.7K_0402_5%

LANLINK_STATUS#

LAN_ACT#

R36

4.7K_0402_5%

1 2
1 2

R39

4.7K_0402_5%@

12

2

C19

1

R174.7K_0402_5%@

R2744.7K_0402_5%@
R134.7K_0402_5%@

R2770_0402_5%@

XTALI
XTALO

27P_0402_50V8J

ADP_PRES<31,38>

2N7002_SOT23

J13

NO SHORT PADS

BroadSAFE

Msic

Hot Plug

Support

1 2

SHORT PADS

J14

1 2

Media

Power

Control

Control

Regulator

U6A

K10

LCLK

M11

LAD0

L11

LAD1

K9

LAD2

L5

LAD3

H11

LFRAME

M9

LRESET

L8

SERIRQ

L9

EXPORT

J11

BSAFE_GPIO0

N13

BSAFE_GPIO1

G12

GPIO0_TST_CLKOUT

H13

GPIO1

G13

GPIO2

D10

SMB_CLK

D9

SMB_DATA

K11

EECLK

L10

EEDATA

E12

SI

E11

SCLK

F11

SO

C12

CS

H2

PWR_IND

J2

ATTN_IND

A2

ATTN_BTTN

SLP_S3#<19,26,27,31,33,34>

SLP_S5#<19,21,22,28,34,40>

BCM5751M

PCI-ETEST

A11

LINKLED

B11

SPD100LED

A12

SPD1000LED

B10

TRAFFICLED

A9

WL_ACTIVITY

B9

WL_LINK5G

C10

WL_LINK2.4G

P12

XTALI

N12

XTALO

F4

REFCLK_SEL

BCM5751MKFB_FPBGA196

XTALO

XTALI

LED

Clock

Bias

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

D D

C C

B B

A A

22K_1206_8P4R_5%

22K_1206_8P4R_5%

V_3P3_LAN

LANLINK_STATUS#<19,24,33>

2

C16

1

RP41

RP40

T2 PAD

ICH_SMBCLK<4,8,12,13,14,19>

ICH_SMBDATA<4,8,12,13,14,19>

LAN_ACT#<24,33>

200_0402_1%

25MHZ_20P_1BX25000CK1A

1 2

Y1

27P_0402_50V8J

Q30

13

D

2

G

S

2

G

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

LOW_PWR

VMAIN_ON

VAUX_ON

PERST

REGSUP12

REGCTL12

REGSEN12

REGOUT25
REGSUP25

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

WAKE

REFCLK-

REFCLK+

VAUXPRSNT

TDO
TMS

TRST

RDAC

4

TST

TCK

TDI

12

R267

4.7K_0402_5%

13

D

Q29
2N7002_SOT23

S

E13
E14
D13
D14
C13
C14
B13
B14

L6
N14

M13
C2

K14
J13
J14

M14
L14

P6
N6
N10
P10
A6

P8
N8

J12
D8

D7
H12
D6
C11
D12

A10

R70

R268

47K_0402_5%

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

R15 4.7K_0402_5%@

LOM_PLT_RST#

PCIE_C_RXN1
PCIE_C_RXP1

ICH_PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

LAN_AUXPWR

R69

1.24K_0402_1%

1 2

Q31

SI2301DS_SOT23

2

12

ENAB_LAN_V# <34,41>

LAN_TX3+ <24>
LAN_TX3- <24>
LAN_TX2+ <24>
LAN_TX2- <24>
LAN_TX1+ <24>
LAN_TX1- <24>
LAN_TX0+ <24>
LAN_TX0- <24>
LOM_LOW_PWR <19,24>

1 2

LOM_PLT_RST# <17>

C17 0.1U_0402_16V4Z

1 2

C18 0.1U_0402_16V4Z

1 2

1 2

R276

4.7K_0402_5%

4.7K_0402_5%

12

R71

4.7K_0402_5%

1 2

0.1U_0402_16V4Z

U4

1

A0

2

A1

3

NC

4

GND

AT24C256_SO8

13

2

2

C39

C41

C324

1

1

4.7U_0805_10V4Z

PCIE_TXN1 <19>
PCIE_TXP1 <19>

LAN_PCIE_WAKE# <19>
CLK_PCIE_LOM# <14>
CLK_PCIE_LOM <14>

V_3P3_LAN

0.1U_0402_16V4Z

R275

1 2

100_0402_5%

0.1U_0402_16V4Z

PCIE_RXN1 <19>
PCIE_RXP1 <19>

CKT Notice : Reserved for A1 die.

C9

12

VCC
SCL

SDA

8
7

WP

6
5

R16

5751_GPIO1
5751_EECLK
5751_EEDAT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C32

1

CLK_PCIE_LOM#CLK_PCIE_LOM

12

1K_0402_5%

3

2

1

0.1U_0402_16V4Z

R35

1K_0402_5%

C44

12

2

1

0.1U_0402_16V4Z

V_3P3_LAN

12

R34

1K_0402_5%

V_3P3_LAN

Layout Notice : Filter place as close
chip as possible.

V_2P5_LAN

V_1P2_LAN

Layout Notice : 3.3V filter. Place as close
chip as possible.

2

2

C40

4.7U_0805_10V4Z

Layout Notice : Filter place as close
chip as possible.

PJP17

2 1

PAD-SHORT 2x2m

0.1U_0402_16V4Z

PJP18

2 1

PAD-SHORT 2x2m

0.1U_0402_16V4Z

PJP19

2 1

PAD-SHORT 2x2m

0.1U_0402_16V4Z

L33

BLM11A601S_0603

BLM11A601S_0603

BLM11A601S_0603

BLM11A601S_0603

C342

4.7U_0805_10V4Z

L32

C331

4.7U_0805_10V4Z

L30

C323

4.7U_0805_10V4Z

L29

C322

4.7U_0805_10V4Z

12

12

12

12

C53

C45

1

1

0.1U_0402_16V4Z

C35

C60

C46

2

2

C339

0.1U_0402_16V4Z

1

1

2

2

C332

0.1U_0402_16V4Z

1

1

2

2

C326

0.1U_0402_16V4Z

1

1

1

2

C325

0.1U_0402_16V4Z

2

1

2

C62

1

0.1U_0402_16V4Z

XTALVDD

2

1

AVDD1

2

1

AVDD2

2

1

AVDDL

GPHY_PLLVDD

PCIE_PLLVDD

PCIE_SDS_VDD

2

2

1

0.1U_0402_16V4Z

C64

0.1U_0402_16V4Z

V_2P5_LAN

C65

2

1

1

2

0.1U_0402_16V4Z
C15

2

1

PCIE_SDS_VDD

GPHY_PLLVDD

BLM11A601S_0603

0.1U_0402_16V4Z

V_1P2_LAN+3VS

C66

4.7U_0805_10V4Z

0.1U_0402_16V4Z

V_3P3_LAN

+3VS

V_2P5_LAN

XTALVDD

V_3P3_LAN

AVDDL

AVDD1
AVDD2

PCIE_PLLVDD

+3VS

V_2P5_LAN

L8

C63

2

1

V_1P2_LAN

Layout Notice : 1.2V filter. Place as close
chip as possible.

2

2

2

C61

1 2

1

2

C341

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B8
E5
E6
E7
E8
E9

E10

F5

F10

G4

J5

J10

K5
K6
K7
K8
K4
J4

D11
G11
K12

A7
B3

C5

E1
E4

G1

K3
L4
P2

A8

D5

P13
H14

M12
P14

M6

F12
F13
A13
F14

M8

G14

P1

G2

A1

L3
M1
M2
M3
M4
M5
M7
N2
N3
N4
N5
N7

P3

P4

P5

P7

V_BIAS

A14

Title

Size Document Number Rev
Custom

LA-2211

Date: Sheet

2

2

C334

C340

C335

1

1

1

0.1U_0402_16V4Z

U6B

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17

VDDIO_0
VDDIO_1
VDDIO_2

Digial power

VDDIO-PCI_0
VDDIO-PCI_1
VDDIO-PCI_2
VDDIO-PCI_3
VDDIO-PCI_4
VDDIO-PCI_5
VDDIO-PCI_6
VDDIO-PCI_7
VDDIO-PCI_8

VDDP_0
VDDP_1
VDDP_2

XTALVDD
WOL_VAUX
WOL_INRSH_ON
PCIE_SDS_VDD

AVDDL_0
AVDDL_1
AVDD_0
AVDD_1

PCIE_PLLVDD
GPHY_PLLVDD

VESD1
VESD2
VESD3

DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39
DC_40
DC_41
DC_42
DC_43
DC_44
DC_45
DC_46

BIASVDD

BCM5751MKFB_FPBGA196

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BCM5751M

Analog
power

PLL

Clamp

Don't care

BIAS

Compal Electronics, Inc.

BCM5751M

1

C336

0.1U_0402_16V4Z

GND

2

C343

1

0.1U_0402_16V4Z

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27

DC_10

DC_11

DC_12

DC_13

DC_14

DC_15

DC_16

DC_17

DC_18

DC_19

DC_20

DC_21

DC_22

DC_23

DC_24

DC_25

DC_26

DC_27

DC_28

DC_29

DC_30

23 48Thursday, September 09, 2004

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8
DC_9

2

C337

1

0.1U_0402_16V4Z

B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9

K13
L7
L12
L13
M10
N11
P11

A3
A4
A5
B1
B2
B5
B6
C1
C3
C4
C6
C7
C8
C9
D1
D2
D3
D4
E3
F1
F2
F3
G3
H1
H3
H4
J1
J3
K1
L1
L2

of

2

1

C338

2

1

0.1U_0402_16V4Z

0.6

5

4

3

2

1

RJ-45 CONN.

PJP20

V_2P5_LAN

D D

2 1

PAD-SHORT 2x2m

C330 0.01U_0402_16V7K

12

C327 0.01U_0402_16V7K

12

C328 0.01U_0402_16V7K

12

C329 0.01U_0402_16V7K

12

LAN_TX0­LAN_TX0+
TRM_CT

LAN_TX1­LAN_TX1+
TRM_CT

LAN_TX2­LAN_TX2+
TRM_CT

LAN_TX3­LAN_TX3+
TRM_CT

U2

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3
TD2-6MX2-

5

TD2+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

PULSE_H5007

MX4­MX4+
MCT4

MX3­MX3+
MCT3

MX2+
MCT2

MX1­MX1+
MCT1

MDO0-

13

MDO0+

14
15

MDO1-

16

MDO1+

17
18

MDO2-

19

MDO2+

20
21

MDO3-

22

MDO3+

23
24

75_0402_1%

75_0402_1%

75_0402_1%

75_0402_1%

R269

12

R270

12

R271

12

R272

12

C320

1000P_1808_3KV7K

1 2

V_3P3_LAN_LED

V_3P3_LAN_LED

LANLINK_STATUS#<19,23,33>

R266 300_0402_5%

MDO3-<33>
MDO3+<33>
MDO1-<33>
MDO2-<33>
MDO2+<33>
MDO1+<33>
MDO0-<33>
MDO0+<33>

LAN_ACT#<23,33>

R265 300_0402_5%

LANLINK_STATUS#

12

MDO3­MDO3+
MDO1­MDO2­MDO2+
MDO1+
MDO0­MDO0+
LAN_ACT#

12

JP3

14

Green LED-

13

Green LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

12

Yellow LED-

11

Yellow LED+

FOX_JM36113-P1121-7F

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

16

CABLE_DETECT

9

10
15

C C

B B

LOM_LOW_PWR<19,23> CLKREQA# <14>

SN74LVC1G17DBVR_SOT23-5

CKT Notice : CABLE IN, CABLE_DETECT=0

CABLE OUT, CABLE_DETECT=1

A A

CABLE_DETECT<19>

0.1U_0402_16V4Z
C56

0.1U_0402_16V4Z
C54

0.1U_0402_16V4Z
C50

0.1U_0402_16V4Z
C49

1

CABLE_DETECT

0.1U_0402_16V4Z@

1 2
1 2
1 2
1 2

V_3P3_LAN V_3P3_LAN

5

U36

P

2

O4I
NC

G

3

V_3P3_LAN

12

R506
10K_0402_5%

1

C578

2

R50 49.9_0402_1%
R63 49.9_0402_1%
R45 49.9_0402_1%
R48 49.9_0402_1%
R42 49.9_0402_1%
R44 49.9_0402_1%
R40 49.9_0402_1%
R41 49.9_0402_1%

R503

1 2

100K_0402_5%

1

C576

0.1U_0402_16V4Z

2

R507

1 2

0_0402_5%@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

13

D

S

RB751V_SOD323

1 2

200K_0402_5%

0.1U_0402_16V4Z

R540

10K_0402_5%

Q54

2

G

2N7002_SOT23

D32

R504

LP_EN#

Layout Notice : Place
termination as close as
BCM5751M as possible

12

21

C577

1

2

V_3P3_LAN

LP_EN# <19>

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

5

U37

P

2

O4I

NC

G

SN74LVC1G17DBVR_SOT23-5

3

LAN_TX0- <23>
LAN_TX0+ <23>
LAN_TX1- <23>
LAN_TX1+ <23>
LAN_TX2- <23>
LAN_TX2+ <23>
LAN_TX3- <23>
LAN_TX3+ <23>

1

V_3P3_LAN V_3P3_LAN_LED

R525

100K_0402_5%@

PREP#<19,33>

PJP21

2 1

PAD-SHORT 2x2m

Q60

FDN338P_SOT23@

D

S

12

13

G

2

13

D

Q61

2

2N7002_SOT23@

G

S

RJ-11 CONN.

MOD_TIP
MOD_RING

MOD_TIP
MOD_RING

JP4

1

TIP

2

RING

3

GND

4

GND

ALLTOP_C10134-10204

JP24

1
2

ACES_88231-0200

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-2211

1

0.6

of

24 48Thursday, September 09, 2004

A

B

C

D

E

C533

+3VS

1

2

0.1U_0402_16V4Z

C291

SLP_S5<21,33,34>

1

0.1U_0402_16V4Z

2

R437

47K_0402_5%

+3VALW

1

C532

2

+3VAUX_LAN+3VALW

12

S

2N7002_SOT23

NDS352P_SOT23@

S

R514

1 2

0_0402_5%@

+3VAUX_LAN

C530

4.7U_0805_10V4Z

G

2

PCI_PME#MINI_PME#

13

D

PCI_PME# <17,21>

Q49

+3V_MINIPCI

Q50

D

13

G

2

R439

12

PJP22

+3V_MINIPCI

V_3P3_LAN

1

0_0805_5%@

2 1

PAD-SHORT 2x2m

2

+5VS

1

1 1

C290

0.01U_0402_16V7K

0.01U_0402_16V7K

2

C543

1

10U_1206_16V4Z

2

C544

1

0.01U_0402_16V7K

2

C292

1

0.1U_0402_16V4Z

2

C538

1

4.7U_0805_10V4Z

2

PCI_AD[0..31]

+3VS

1

C542

0.01U_0402_16V7K

2

PCI_AD[0..31] <17,21>

C293

1

0.1U_0402_16V4Z

2

C294

1

4.7U_0805_10V4Z

2

JP20

RINGTIP

12

R516
10K_0402_5%

2 2

XMIT<19>

CLK_PCI_MINI

12

R448

10_0402_5%@

1

C537

10P_0402_50V8K@

2

3 3

2

G

12

R517
100K_0402_5%

13

D

Q58
2N7002_SOT23

S

+3VS

WL_LED
XMIT#

PCI_PIRQF#

W=40mils

CLK_PCI_MINI
PCI_REQ0#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_CBE#2
PCI_IRDY#

PCI_SERR#
PCI_PERR#

PCI_CBE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

WL_LED<32>

CLK_PCI_MINI<14>

PCI_REQ0#<17>

R452
100_0402_1%

CH_DATA<28>

PCI_CBE#3<17,21>

PCI_CBE#2<17,21>

PM_CLKRUN#<19,21,29,30,31>

PCI_SERR#<17,21,31>

1 2

PCI_IRDY#<17,21>

PCI_CBE#1<17,21>

PCI_AD5
PCI_AD3

W=30mils

+5VS

PCI_AD1

R451

1 2

8.2K_0402_5%

+5VS

101
103
105
107
109
111
113
115
117
119
121
123

125

AMP_1318916-1

112

KEY KEY

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

2
4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

126

PCI_PIRQF#

MINIPCI_RST#
PCI_GNT0#
MINI_PME#
PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINI_IDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_CBE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

W=40milsW=30mils

W=40mils

W=40mils

R441

1 2

100_0402_1%

1 2

1 2

+5VS
PCI_PIRQF# <17>

+3VAUX_LAN

MINIPCI_RST# <19>

+3VS
PCI_GNT0# <17>

CH_CLK <28>

PCI_AD20

R235

100_0402_1%

PCI_PAR <17,21>

PCI_FRAME# <17,21>
PCI_TRDY# <17,21>
PCI_STOP# <17,21>

PCI_DEVSEL# <17,21>PCI_PERR#<17,21>

PCI_CBE#0 <17,21>

R44710K_0402_5%

+3VS

+3VAUX_LAN

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

Mini PCI Slot

LA-2211

E

0.6

of

25 48Thursday, September 09, 2004

A

B

C

D

E

F

G

H

VDDA_CODEC

C553

L36

1

2

VDDA_CODEC

2

1

+3VS

C424
1U_0603_10V4Z

12

R456

49.9K_0402_1%

12

R457
143K_0402_1%

1

C416

0.1U_0402_16V4Z

2

1

+

C309
22U_B_10V

2

1

C307

0.1U_0402_16V4Z

2

12

R329

1 1

PCM_SPK#<21>

10K_0402_5%

13

D

Q35

2

2N7002_SOT23

G

S

C390

1 2

0.1U_0402_16V4Z

R341

1 2

150K_0402_1%

12

R330
10K_0402_5%

0.1U_0402_16V4Z

2

C377

0.01U_0402_16V7K

1

C391

1 2

MONO_INR

+5VAMP

1

+

C548
22U_B_10V

2

2

C552
1U_0603_10V4Z

1

VDDA_CODEC

12

R350
10K_0402_5%

13

D

Q37

SB_SPKR<19>

2 2

2

2N7002_SOT23

G

S

DLINE_IN_L<33>

3 3

C563

1 2

0.1U_0402_16V4Z
C564

1 2

0.1U_0402_16V4Z
C565

1 2

0.1U_0402_16V4Z
C566

1 2

C396

1 2

0.1U_0402_16V4Z

R370 4.7K_0402_5%
R375 4.7K_0402_5%

R369 4.7K_0402_5%
R374 4.7K_0402_5%

0.1U_0402_16V4Z

4 4

GNDAGND

1 2

150K_0402_1%

1 2

1 2

R359

VDDA_CODEC

1

C395

0.1U_0402_16V4Z

2

2

C402

0.1U_0402_16V4Z

1

38

AVDD125AVDD2

43

AVDD434AVDD3

U14

MONO_INR

R388 2.2K_0402_5%

HPS<27>

12

12

DLINE_IN_R_L

DLINE_IN_R_R

1 2

C423 1U_0603_10V4Z

1 2

C422 1U_0603_10V4Z

MIC1<27>
MIC2<27>

AC97_RST#<18,32>

AC97_SYNC<18,32>

AC97_SDOUT<18,32>

EAPD<27>

1 2

R387 2.2K_0402_5%@

1 2

DLINE_IN_RC_L
DLINE_IN_RC_R

MIC1_C

1 2

C204 1U_0603_10V4Z
C205 1U_0603_10V4Z

MIC2_C

1 2

R376 33_0402_5%

1 2

R367 33_0402_5%

1 2

R159 1K_0402_5%

1 2

R158 1K_0402_5%

1 2

L53

1 2

FBM-L10-160808-301-T_0603

14
15
16
17
23
24
18
20
19
21
22
13

11
10

5

45
46

47
48

4
7

AUX_L
AUX_R
JS1
JS0
LINE_IN_L
LINE_IN_R
CD_L
CD_R
CD_GND
MIC1
MIC2
PHONE

RESET#
SYNC
SDATA_OUT
ID0

ID1
EAPD
SPDIFO
DVSS1

DVSS2

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT
HP_LOUT_L
HP_LOUT_R

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

VREFOUT

VREF

AFILT1
AFILT2
AFILT3
AFILT4

AVSS1
AVSS2
AVSS3
AVSS4

1

C147

0.1U_0402_16V4Z

2

9

35
36
37
39
41

6
8
2

3

28
27

29
30
31
32

12

NC

42

NC

26
40
44
33

AD1981BJST_LQFP48

SLP_S3#<19,23,27,31,33,34>

2

C551
100P_0402_50V8J

1

1

C417

0.1U_0402_16V4Z

2

+3VS_CODEC

1

C156

0.1U_0402_16V4Z

2

1

C175

0.1U_0402_16V4Z

2

LINE_OUTL <27>
LINE_OUTR <27>

L_HP <27>
R_HP <27>

R371 33_0402_5%
R373 33_0402_5%

1 2

AUD_REF

AFILT1
AFILT2
AFILT3
AFILT4

12
12

CLK_14M_CODEC

C397

R364

1 2

10_0402_5%@

15P_0402_50V8J@

CODEC_REF

1 2
1 2
1 2
1 2

U18

1

IN

OUT

3

EN

ADJ

2

GND

MIC5205BM5_SOT23-5

R258

1 2

0_1206_5%

1

C148
10U_1206_16V4Z

2

1

C393
10U_1206_16V4Z

2

AC97_BITCLK <18,32>DLINE_IN_R<33>
AC97_SDIN0 <18>
CLK_14M_CODEC <14>

C410
270P_0402_50V7K
C408
270P_0402_50V7K
C401
270P_0402_50V7K
C398
270P_0402_50V7K

5
4

0.01U_0402_16V7K

1 2

CHB2012U121_0805

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

F

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

AC97 CODEC AD1981B

LA-2211

G

0.6

of

26 48Thursday, September 09, 2004

H

A

B

C

D

E

AMP. FOR INTERNAL SPEAKER

+5VAMP

+5VALW

1 1

LINE_OUTR<26>

LINE_OUTL<26>

SLP_S3#<19,23,26,31,33,34>

EAPD#<32>

2 2

C503

1 2

0.1U_0402_16V4Z
C502

1 2

0.1U_0402_16V4Z
C504

1 2

0.22U_0603_10V7K

R430 10K_0402_5%

EAPD<26>

2N7002_SOT23

LINE_C_OUTR

LINE_C_OUTL

1 2

Q28

2

G

R425

1 2

34.8K_0603_1%
R424

1 2

34.8K_0603_1%
R429

1 2

16.2K_0603_1%

13

D

S

0_1206_5%

LINE_OUT

R443

1 2

LINE OUT/HEADPHONES AUDIO JACK

VDDA_CODEC

12

R423
100K_0402_5%

HPS<26>

2N7002_SOT23

3 3

4 4

DOCK_HPS#<33>

R_HP<26>

DLINE_OUT_R<33>
DLINE_OUT_L<33>

L_HP<26>

1 2

C262 100U_6.3V_M

1 2

C263 100U_6.3V_M

13

D

Q44

1U_0603_10V6K@

+

+

A

2

G

S

1

C526

2

R252

R_C_HP R_CRL_HP

1 2

33_0805_5%

R253

L_C_HP

1 2

33_0805_5%

1K_0402_1%

2N7002_SOT23

R445

VDDA_CODEC

Q48

12

12

D

S

R_CR_HP

L_CR_HP

R446
1K_0402_1%

1 2

0_1206_5%

3

4

1
2

1

C521

0.47U_0603_16V7K

2

12

R251
100K_0402_5%

13

2

G

CHB1608B121_0603

1 2

L52

L51

1 2

CHB1608B121_0603

0.01U_0402_16V7K

R442

6

U31

IN+

IN-

SHUTDOWN
BYPASS

7

R255

1 2

1

100K_0402_5%

C536
1U_0603_10V4Z

2

L_CRL_HP

C540

470P_0402_50V7K

C470

1 2

1

+

C300
100U_6.3V_M

2

VDD

GND

SPK+

5

VO+

SPK-

8

VO-

TPA6211A1DGNR_PMSOP8

VDDA_CODEC

12

R256
100K_0402_5%

1

1

C547
470P_0402_50V7K

2

2

B

+5VAMPP

1

C539

0.1U_0402_16V4Z

2

L47

1 2

CHB1608B121_0603

L48

1 2

CHB1608B121_0603

JP21

5
4
3

6
2
1

SUYIN_010178FR006G100HL

C506

SPK++

SPK--

1

2

100P_0402_50V8J

ACES_85205-0200

1

2

C514

100P_0402_50V8J

UNUSED

VDDA_CODECCODEC_REF

1

C440

2

0.01U_0402_16V7K

4

U27B

5

P

+

OUT

6

-

G

TLV2464_TSSOP14

11

J28

1 2

SHORT PADS

JP36

INT_MIC_2

1
2

ACES_85205-0200

VDDA_CODEC

R196

JP15

1
2

7

VDDA_CODEC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

INT_MIC_1 INT_MIC_3

1 2

3K_0402_5%

INT_MIC_SW

EXT_MICB

1

C224
1U_0603_10V4Z

2

C271

1 2

0.22U_0603_10V7K
C499

1 2

4700P_0402_25V7K

C500

1 2

4700P_0402_25V7K

C270

1 2

0.22U_0603_10V7K

R418

470_0402_5%

1 2

1 2

R417

470_0402_5%

4.7U_0805_10V4Z

AMP. FOR INTERNAL MICROPHONE

CODEC_REF VDDA_CODEC

C585

1 2

1200P_0402_50V7K@

R193

1 2

3K_0402_5%

HLC0603CSCCR10JT_0603

C202

1 2

0.22U_0603_10V7K

L57

1 2

C571

68P_0402_50V8J

R385

1 2

1

10K_0402_5%

2

C446

100P_0402_50V8J

INT_MIC_4

1

2

AMP. FOR EXTERNAL MICROPHONE

1

C244

2

100P_0402_50V8J

EXT_MICA_2EXT_MICA

CODEC_REF VDDA_CODEC

1

C243

2

100P_0402_50V8J

EXT_MICB_2

EXT_MICA_1

1 2

HLC0603CSCCR10JT_0603

INT_MIC_SW_1

1 2

HLC0603CSCCR10JT_0603

INT_MIC_SW_2

1 2

HLC0603CSCCR10JT_0603

68P_0402_50V8J

EXT_MICB_1

1 2

HLC0603CSCCR10JT_0603

L58

L59

L60

C574

1

2

68P_0402_50V8J

L61

C573

1

2

1

2

R211

1 2

10K_0402_5%

R419

1 2

100K_0402_5%

R420

1 2

100K_0402_5%
C572

1

68P_0402_50V8J

2

R210

1 2

10K_0402_5%

C575
68P_0402_50V8J

EXT. MICIN AUDIO JACK

INT_MIC
INT_MIC_SW

R422

C487

2

2

1

1

3.9K_0402_1%

1 2

1 2

3.9K_0402_1%

C486

4.7U_0805_10V4Z

R421

EXT_MICB

EXT_MICA

1 2

L46

CHB1608B121_0603

1 2

L45

CHB1608B121_0603

D

C507

470P_0402_50V7K

C211

1 2

680P_0402_50V7K

R190

1 2

100K_0402_5%

1

C441

2

0.1U_0402_16V4Z

4

U27A

3

P

+

OUT

2

-

G

TLV2464_TSSOP14

11

VDDA_CODECCODEC_REF

4

U27C

10

P

+

OUT

9

-

G

TLV2464_TSSOP14

11

4

U27D

12

P

+

OUT

13

-

G

TLV2464_TSSOP14

11

1

1

C518
470P_0402_50V7K

2

2

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

LA-2211

INT_MIC

1

C488

1 2

100P_0402_50V8J

R413

1 2

100K_0402_5%

8

14

MIC1

C489

1 2

100P_0402_50V8J

R414

1 2

100K_0402_5%

MIC2

JP13

5
4
3

6
2
1

SUYIN_010178FR006G100HL

AMP & Audio Jack

E

MIC1 <26>

MIC2 <26>

27 48Thursday, September 09, 2004

of

0.6

5

4

3

2

1

USB CONNECTOR 1

U32

3

1

2

VIN

4

VIN/CE

2

GND

RT9701-CB_SOT23-5

D D

SLP_S5#

C535

4.7U_0805_10V4Z

C C

USB_VCCA+5VALW +5VALW USB_VCCC

1

VOUT

5

VOUT

560K_0402_5%

R450

12

12

R449
470K_0402_5%

USB_OC#0

W=40mils

USB_OC#0 <19>

1

C541
1000P_0402_50V7K

2

1

+

C527

2

100U_6.3V_M

USB20_N0<19>
USB20_P0<19>

1

1

2

C515

0.1U_0402_16V4Z

USB_VCCA
USB20_N0
USB20_P0

SF10402ML080C@

2

USB20_N0
USB20_P0

C519

TVS8

1000P_0402_50V7K

1

2

SF10402ML080C@

JP16

1
2
3
4

SUYIN_020133MR004S516ZL

1

1

TVS9

TVS7

SF10402ML080C@

2

2

SLP_S5#<19,21,22,23,34,40>

SLP_S5#

C4

4.7U_0805_10V4Z

1

2

U1

3

VIN

VOUT

4

VIN/CE

VOUT

2

GND

RT9701-CB_SOT23-5

560K_0402_5%

USB CONNECTOR 3

R512

C580

1 2

0.01_1206_1%

1

2

12

0.1U_0402_16V4Z

R513
820_0805_1%

+5VALW

B B

1

2

U12

13

ENABLE

11

FAULT

12

PWRGD

ISENSE

3

TIMER

4

VREG

2

DGND

6

AGND

9

VSENSE

AGND

TPS2331IPWR_TSSOP14

IN

ISET

GATE

DISCH

C589

1

2

1000P_0402_50V7K

USB_OC#2_R
USB_OC#2

1

2

C582

0.1U_0402_16V7K

C583

0.1U_0402_16V4Z

USB_OC#2_R<19>

USB_OC#2<19>

1

2

C579

2.2U_0805_16V4Z

8

USB_ISENSE1

10

USB_ISENSE2

7
1
14
5

Q57

8

D

7

D

6

D

5

D

SI4800DY_SO8

S
S
S
G

C581

0.1U_0402_16V7K

1
2
3
4

1

2

USB_VCCB

C102

100U_D2_6.3VM

W=40mils

1

+

0.1U_0402_16V4Z

2

C437

1

1

C430
1000P_0402_50V7K

2

2

JP11

FOX_UB11123-C1203-TR

1

1

TVS6

2

2

SF10402ML080C@

1
2
3
4

USB_VCCB
USB20_N2
USB20_P2

SF10402ML080C@

USB20_N2
USB20_P2

TVS5

USB20_N2<19>
USB20_P2<19>

USB CONNECTOR 2

1
5

12

R9
470K_0402_5%

USB_OC#1

12

R10

1

TVS4
SF10402ML080C@

2

W=40mils

USB_OC#1 <19>

1

C8
1000P_0402_50V7K

2

1

2

USB20_N1<19>
USB20_P1<19>

1

C306
1U_0603_10V4Z

2

BT_OFF<19>

1

+

C1

C312

2

100U_6.3V_M

0.1U_0402_16V4Z

USB20_N1
USB20_P1

USB_VCCC
USB20_N1
USB20_P1

TVS1

SF10402ML080C@

BT Connector

JP22

1
2
3
4
5
6
7
8

ACES_87212-0800

12

R518
100K_0402_5%

R454

1 2

47K_0402_5%

1

C311

2

1000P_0402_50V7K

1

2

SF10402ML080C@

2

0.01U_0402_16V7K

JP5

1
2
3
4

SUYIN_020133MR004S516ZL

1

1

TVS3

TVS2

SF10402ML080C@

2

2

+3VAUX_BT

USB20_P3 <19>
USB20_N3 <19>
BT_LED <32>
CH_DATA <25>
CH_CLK <25>

Q51
SI2301DS_SOT23

13

1

1

2

C546

C545

0.1U_0402_16V4Z

2

+3VAUX_BT+3VALW

1

C549

4.7U_0805_10V4Z

2

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

USB & BT Connector

LA-2211

1

0.6

of

28 48Thursday, September 09, 2004

A

1 1

+3VS

12

R98

10K_0402_5%@

NPCI_RESET<17>

PLT_RST#<7,16,17,18,19,30,31>

RP6

2 2

10K_1206_8P4R_5%

RP7

10K_1206_8P4R_5%

+3VS

R68

1 2

10K_0402_5%

3 3

R77

1 2

10K_0402_5%

R79

1 2

10K_0402_5%

R80

1 2

10K_0402_5%

R100

1 2

10K_0402_5%

D9

RB751V_SOD323@

1 2

SHORT PADS

SIO_GPIO43

18

SIO_GPIO12

27

SIO_GPIO10

36

SIO_GPIO44

45

18

SIO_GPIO46

27

SIO_GPIO45

36

SIO_IRQ

45

R500

1 2

0_0402_5%@

SW_EXPCRD_RST#

PID0

PID1

SIO_GPIO11

SIO_GPIO40

SIO_RESET

21

J26

EXPCRD_RST# <33>

B

+3VS

R67 10K_0402_5%

R99 10K_0402_5%

+3VS

1 2

LPC_FRAME#<18,30,31>

LPC_DRQ#0<18>

1 2

PM_CLKRUN#<19,21,25,30,31>

CLK_PCI_SIO<14>

CLK_14M_SIO<14>

C

+3VS

DCD#1
RI#1
CTS#1
DSR#1

IRRX

LPC_AD0<18,30,31>
LPC_AD1<18,30,31>
LPC_AD2<18,30,31>
LPC_AD3<18,30,31>

SIRQ<19,21,30,31>

PID0<16>
PID1<16>

SER_SHD<33>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RESET
SIO_PD#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_GPIO45
SIO_GPIO46
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

SW_EXPCRD_RST#

U8

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh
1 = 04Eh*

12

R96
10_0402_5%@

1

C94
18P_0402_50V8K

@

2

RP3

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

1 2

R76
1K_0402_5%

FIR

LPC I/F

IRMODE/IRRX3

CLOCK

GPIO

POWER

62

RXD1

63

TXD1

64

DSR1#

1

RTS1#

2

CTS1#

3

DTR1#

4

RI1#

DCD1#

IRRX2

IRTX2

INIT#

SLCTIN#

SLCT

BUSY

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

R81
10_0402_5%@

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

5
37

38
39

41
42
44
46
47
48
49
50
51
53
55
56

PE

57
58
59
60
61

7
11
26
45
54

SERIAL I/F

PARALLEL I/F

CLK_14M_SIOCLK_PCI_SIO

12

1

C70
10P_0402_25V8K

@

2

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX
IRTXOUT
IRMODE

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

0.1U_0402_16V4Z

D

1

1

C88

C84

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RXD1 <33>

R64 1K_0402_5%

1 2

TXD1 <33>
DSR#1 <33>
RTS#1 <33>
CTS#1 <33>
DTR#1 <33>
RI#1 <33>
DCD#1 <33>

IRRX <32>
IRTXOUT <32>
IRMODE <32>

LPTINIT# <33>
LPTSLCTIN# <33>
LPD0 <33>
LPD1 <33>
LPD2 <33>
LPD3 <33>
LPD4 <33>
LPD5 <33>
LPD6 <33>
LPD7 <33>
LPTSLCT <33>
LPTPE <33>
LPTBUSY <33>
LPTACK# <33>
LPTERR# <33>
LPTAFD# <33>
LPTSTB# <33>

1

1

C57

C76

2

2

4.7U_0805_10V4Z

+3VS

LPD0
LPD1
LPD2
LPD3

LPD4
LPD5
LPD6
LPD7

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

LPTERR#
LPTAFD#
LPTSTB#

LPTSLCTIN#

LPTINIT#

E

D36

RB751V_SOD323

+5VS_PRN

RP51

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP52

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP53

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP54

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
R480

1 2

4.7K_0402_5%
R481

1 2

4.7K_0402_5%

+5VS

21

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-2211

E

0.6

of

29 48Thursday, September 09, 2004

5

4

3

2

1

Wireless/BT ON & OFF Button

BIOS ROM

U20

24

D D

FWH_TBL#<19>

FWH_WP#<19>

R273

1 2

100_0402_1%

RP42

4 5
3 6
2 7
1 8

100_1206_8P4R_5%

C C

FWH_TBL#
FWH_WP# LPC_AD3

FWH_GPI0
FWH_GPI1
FWH_GPI2
FWH_GPI3
FWH_GPI4

23
22
21

20
19

18
17
16
15

7
1

3
4
5
6

8
11
13
14
31
36

A0/ID0
A1/ID1
A2/ID2
A3/ID3

A4/TBL#
A5/WP#

A6/FGP10
A7/FGP11
A8/FGP12
A9/FGP13
A10/FGP14

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

SST49LF008A-33-4C-EI_TSOP40@

VDD2
VDD1

VSS3
VSS2
VSS1

DQ0/FWH0
DQ1/FWH1
DQ2/FWH2
DQ3/FWH3

WE#/FWH4

DQ4/RES
DQ5/RES
DQ6/RES
DQ7/RES

R/C#/CLK

RST#

OE#/INIT#

IC

39
10

40
30
29

25
26
27
28
38

32
33
34
35

9
12
37

2

+3VS

1

C333

0.1U_0402_16V4Z

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

CLK_PCI_FWH
PLT_RST#
FWH_INIT#

FWH_IC

CLK_PCI_FWH <14>

FWH_INIT# <18>

12

R278
10K_0402_5%

1

C42

0.1U_0402_16V4Z

2

LPC_AD0
LPC_AD1
LPC_AD2

LPC_FRAME#
FWH_WP#
FWH_TBL#
PLT_RST#
FWH_INIT#
CLK_PCI_FWH

FWH_GPI0
FWH_GPI1
FWH_GPI2
FWH_GPI3
FWH_GPI4

U21

13
14
15
17
23

7
8

2
24
31

6

5

4

3
30

1
22
26
27

1M8_PLCC32

FWH0
FWH1
FWH2
FWH3
FWH4
WP#
TBL#
RST#
INIT#
CLK

FGPI0
FGPI1
FGPI2
FGPI3
FGPI4
NC
NC
NC
NC

VDD

VDD

GND
GND

RES
RES
RES
RES

+3VS

25
32

16
28

21
20
19
18

12

ID0

11

ID1

10

ID2

9

ID3

FWH_IC

29

IC

KSI_D_11<16,31,32> KSO15 <31,32>

KSI_D_12<31,32>

KSI_D_12

ON/OFF & SLEEP Button

ON/OFF#<32,33>

ON/OFF#

TPM Module

+3VS

12

R186

R185 0_0402_5%@

1

C192

0.1U_0402_16V4Z

2

10K_0402_5%

1 2

+3VS

LPC_PD#

PM_CLKRUN#

LPC_PD# <19,31>
PM_CLKRUN# <19,21,25,29,31>

CAPS_LED#<31>

17-21SYGC/S530-E1/TR8_GRN

CAPS_LED#

GREEN
CAP LED

STB_LED#<31,32,33>

2

ACES_88028-2400

+3VS

1

C191

0.1U_0402_16V4Z

2

JP33

1 2
3 4
5 6
7 8
9 10
111312

15
17
19
21
23

14
16
18
20
22
24

CLK_PCI_TCG<14>

LPC_DRQ#1<18>

LPC_AD0<18,29,31>
LPC_AD1<18,29,31>
LPC_AD2<18,29,31>
LPC_AD3<18,29,31>

LPC_FRAME#<18,29,31>

PLT_RST#<7,16,17,18,19,29,31>

B B

A A

CLK_PCI_TCG
LPC_DRQ#1

SIRQ

SIRQ<19,21,29,31>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

R176 0_0402_5%@

1 2

SW2

2 1
4 3

EVQPJT05M_4P

QuickLook Button

SW1

2 1
4 3

EVQPJT05M_4P

123

4

8
7

SW3

SS607-212N-FEEG1T

GREEN
POWER LED

STB_LED#

2

G

+3VS

47K

10K

Q72
DTA114YKA_SC59

1 3

12

R184
150_0402_5%

21

CAPS LED

D12

KSO15KSI_D_11

KSO15

6
5

+3VALW

21

D41
17-21SYGC/S530-E1/TR8_GRN

12

R259
150_0402_5%

13

D

Q25
2N7002_SOT23

S

12

R541
150_0402_5%

21

D30
17-21SYGC/S530-E1/TR8_GRN

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

LA-2211

30 48Thursday, September 09, 2004

1

0.6

of

5

4

+3VL

+3VS

3

2

1

99
100

98
97
96
95
93

62
63
64
66

68
69
70

71
72
73
74
75
76
77

78
80

86
87

84
85

56
82
83
48
58
49
61
60
50

1
57

91
88
90
89

R62

R52

R29

R65

R28

R27

1

C78

0.1U_0402_16V4Z

2

KBC_PWR_ON
GREEN_BATLED#

BATSELB_A#
KBRST#
INV_PWM
FAN_PWM
CHGCTRL

ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15

PM_RSMRST#
DIGI_RX
DIGI_TX

BATCON
EC_GPIO12
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M

NUM_LED#
SLP_S3#

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

PGM
FWP#
EA#
CLK_14M_KBC

PM_POK
PWR_GD
VCC1_PWRGD

S_CLK

R49 33_0402_5%

MODE

AMBER_BATLED#
STB_LED#
CAPS_LED#

1. For normal operation:

+3VL

2. For KBC internal ROM flash:

12

12

1

C81

4.7U_0805_10V4Z

2

KBC_PWR_ON <38,39>
GREEN_BATLED# <32>

BATSELB_A# <38>
INV_PWM <16>

FAN_PWM <4>
CHGCTRL <38>

ON/OFFBTN_KBC# <32>
LOW_BAT# <19>
KSO14 <16,32>
KSO15 <30,32>

PM_RSMRST# <19>
DIGI_RX <16>
DIGI_TX <16>

BATCON <38>

THM_MBAY# <37>
PCI_SERR# <17,21,25>
THM_MAIN# <37>

NUM_LED# <32>
SLP_S3# <19,23,26,27,33,34>

AB1A_DATA <37>
AB1A_CLK <37>

AB1B_DATA <37>
AB1B_CLK <37>

CLK_14M_KBC <14>
PM_POK <19>

PWR_GD <35,40,43>
VCC1_PWRGD <35>

1 2

T61PAD
T62PAD

T63PAD

AMBER_BATLED# <32>
STB_LED# <30,32,33>
CAPS_LED# <30>

Un-install R29,R65

Install R29,R65

2

+3VL

12

R30
10K_0402_5%

D7

+3VL

12

R538
100K_0402_5%

J10

1 2

NO SHORT PADS

AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK

4.7K_1206_8P4R_5%

NUM_LED#

RB751V_SOD323

BATCON

J11

1 2

SHORT PADS

RP1

1 8
2 7
3 6
4 5

R32

1 2

100K_0402_5%

21

KB_RST# <18>

J15

1 2

NO SHORT PADS

ADP_PRES

J12

1 2

NO SHORT PADS

+3VL

D6

RB751V_SOD323

R31

10K_0402_5%

21

12

Battery selector function define.

1. For MAXIM solution.
a. Short J10, J12,J15 and
uninstall R538.

b. Open J11.

2. For Common solution. (Default)
a. Short J11 and install R538.
b. Open J10,J12 and J15.

R25

FWP# PWR_GD

1 2

10K_0402_5%

+3VL

JP31

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

1
2
3
4
5
6

ACES_85201-0602

For KBC debugging used.

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

LPC47N250

LA-2211

1

OUT0 <38>

ADP_PRES <23,38>

OUT2 <38>

GATEA20 <18>

+3VL

of

31 48Thursday, September 09, 2004

0.6

1

C37

+3VL

D D

C C

B B

A A

1 8
2 7
3 6
4 5

47K_1206_8P4R_5%

1 8
2 7
3 6
4 5

47K_1206_8P4R_5%

+5VS

1 2

10K_0402_5%

1 2

10K_0402_5%

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

+3VS

12

R94
10K_0402_5%

LPCPD#

CLK_PCI_EC

12

R86

10_0402_5%@

2

C80

10P_0402_50V8J@

1

KSI0

KSI1

KSI2

KSI1
KSI2
KSI3

RP44

RP43

R84

R85

RP5

D27

1

DAP202U_SOT323
D26

1

DAP202U_SOT323
D25

1

DAP202U_SOT323
RP4

1 8
2 7
3 6
4 5

0_1206_8P4R_5%@

KSI0
KSI1
KSI2
KSI3

KSI4
KSI5
KSI6
KSI7

TP_CLK

TP_DATA

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

10P_0402_50V8J

KSI_D_0

2

KSI_D_8

3

KSI_D_1

2

KSI_D_9

3

KSI_D_2 KSI_D_5

2

KSI_D_10

3

KSI_D_0
KSI_D_1
KSI_D_2
KSI_D_3

5

0.1U_0402_16V4Z

LPC_PD#<19,30>

1 2

R74
2M_0402_5%@

1

IN

1

C350

2

2

32.768KHZ_12.5P_1TJS125DJ2A073

KSI_D_0 <32>
KSI_D_8 <16,32>

KSI_D_1 <32>
KSI_D_9 <16,32>

KSI_D_2 <32>
KSI_D_10 <16,32>

2

R87 0_0402_5%@

120K_0402_5%

4

Y2

1

OUT

C349
10P_0402_50V8J

NC3NC

2

KSI3

KSI4

KSI5

KSI4KSI0
KSI5
KSI6

0.1U_0402_16V4Z

KSO[0..11]<32>

PM_CLKRUN#<19,21,25,29,30>

CLK_PCI_EC<14>

RUNSCI_EC#<17>

LPC_FRAME#<18,29,30>

1 2

R75

1U_0603_10V4Z

D24

1

DAP202U_SOT323
D23

1

DAP202U_SOT323
D20

1

DAP202U_SOT323
RP2

1 8
2 7
3 6
4 5

0_1206_8P4R_5%@

1

C52

0.1U_0402_16V4Z

2

KSO[0..11]

T58 PAD
T59 PAD

KSI7<32>

TP_CLK<32>
TP_DATA<32>
KBD_CLK<33>
KBD_DATA<33>
PS2_CLK<33>
PS2_DATA<33>

SIRQ<19,21,29,30>

LPC_AD3<18,29,30>
LPC_AD2<18,29,30>
LPC_AD1<18,29,30>
LPC_AD0<18,29,30>

PLT_RST#<7,16,17,18,19,29,30> CB_CLK <22>

12

+RTCVCC

2

C69

1

KSI_D_3

2

KSI_D_11

3

KSI_D_4

2

KSI_D_12

3

2

KSI_D_13

3

KSI_D_4
KSI_D_5
KSI_D_6

C51

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#
PLT_RST#

LPCPD#
CRY1

CRY2

1

C67

0.1U_0402_16V4Z

2

KSI_D_3 <32>
KSI_D_11 <16,30,32>

KSI_D_4 <32>
KSI_D_12 <30,32>

KSI_D_5 <32>
KSI_D_13 <32>

4

1

0.1U_0402_16V4Z

2

17
16
15
14
13
12
10

9
7
6
5
4
3
2

25
24
23
22
21
20
19
18

26
27
29
31
32
33

44
46
43
59

40
39
37
35

41
42
34

53
54

51
52

12

R78
300_0402_5%

U7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/OUT8/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#
LPCPD#

XTAL1
XTAL2

VCC0
XOSEL

1

C36

4.7U_0805_10V4Z

2

Power Mgmt/SIRQ

AGND FILTER

D19

KSI6

1

DAP202U_SOT323

1

C34

2

VCC111VCC167VCC181VCC194VCC230VCC238VCC2

Keyboard/Mouse Interface

LPC

Bus

AGND

GND92GND79GND65GND45GND36GND28GND

55

C58

1 2

0.1U_0402_16V4Z

KSI_D_6

2

KSI_D_14

3

SMSC_LPC47N250_TQFP-100P

8

KSI_D_6 <32>
KSI_D_14 <32>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C75

0.1U_0402_16V4Z

2

47

General Purpose I/O Interface

Access Bus Interface

LPC47N250_TQFP100

3

1

2

OUT0

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO2

GPIO3
GPIO4/KSO14
GPIO5/KSO15

GPIO7/PWM3

GPIO8/RXD
GPIO9/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK

GPIO21/PS2DAT

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM

FWP#

CLOCK

32KHZ_OUT

RESET_OUT#

PWRGD

VCC1_PWRGD

24MHZ_OUT

TEST PIN

MODE

DMS_LED#

BAT_LED#

PWR_LED#/8051TX

Miscellaneous

FDD_LED#/8051RX

MODE

PGM

FWP#

J3

PGM

1 2

NO SHORT PADS

FWP#

EA#

C79

0.1U_0402_16V4Z

EA#

1 2

10K_0402_5%

1 2

1K_0402_5%@

1 2

1K_0402_5%@

1 2

1K_0402_5%

1K_0402_5%@

1K_0402_5%

FUN BD. FIR & LED BD.

INT_KBD CONN.

KSO14<16,31>
KSO15<30,31>

LID_SW#<9,19>

EAPD#<27>

NUM_LED#<31>

C7

1000P_0402_50V7K

ON/OFF#<30,33>

+3VS

JP9

1

C12

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

ACES_87212-1200

+3VALW

1

2

C13

0.1U_0402_16V4Z

2

1

AMBER_BATLED#<31>

GREEN_BATLED#<31>

AC97_SDOUT<18,26>

AC97_RST#<18,26>

4.7U_0805_10V4Z

+3VS

1

2

KSI_D_8
KSI_D_9
KSI_D_10
KSI_D_13
KSO14
KSO15
LID_SW#
EAPD#
NUM_LED#

1

C5

0.1U_0402_16V4Z

2

Power button

+3VL

+3VL

12

R22

100K_0402_5%

ON/OFF#

C23

1U_0603_10V4Z

U5F

14

SN74LVC14APWLE_TSSOP14

P

13

O12I

G

1

7

2

R26

1 2

100K_0402_5%

C11

1U_0603_10V4Z

IRTXOUT<29>

IRMODE<29>

HDD_LED#<18>

BT_LED<28>

WL_LED<25>

STB_LED#<30,31,33>

PANEL_FLIP#<19>

R405 33_0402_5%

1

2

+3VS +5VS

IRRX

IRRX<29>

IRMODE IRMODE
HDD_LED#

+3VL

AMBER_BATLED#
BT_LED
WL_LED WL_LED
STB_LED#
PANEL_FLIP#
GREEN_BATLED# GREEN_BATLED#

JP18

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85203-2002

MDC Conn.

JP25

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

+3VALW

+3VS

1 2

+3VL

2

G

12

R536
100K_0402_5%

ON/OFFBTN_KBC#

13

D

Q70
2N7002_SOT23

S

17

+3.3Vaux/BT_VCC

19

GND

21

+3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

ACES_88018-3010

ON/OFFBTN_KBC# <31>

D42

RB751V_SOD323

21

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

R8

1 2

100K_0402_5%

ON/OFFBTN#

+3VALW+3VALW

IRRX
IRTXOUTIRTXOUT

HDD_LED#

AMBER_BATLED#
BT_LED

STB_LED#
PANEL_FLIP#

+3VS+5VS

AUDIO_PWRDN/DETECH

MONO_PHONE

RESERVED/BT_ON#

RESERVED/USB+

RESERVED/USB-

RESERVED/PRIMARY_DN

RESERVED/+5VD/WAKEUP

RESERVED/GND

AC97_SDATA_IN1
AC97_SDATA_IN0

AC97_BITCLK

+3VALW

ON/OFFBTN# <19>

0.1U_0402_16V4Z

+3VL

GND

+5Vmain

AC97_SYNC

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

C304

+5VS

1

1

C303

0.1U_0402_16V4Z

2

2

+3VS

1

C305

0.1U_0402_16V4Z

2

1000P_0402_50V7K

1 2

R402 33_0402_5%

+3VL

1

2

1

C10

2

+5VS

+3VALW

AC97_SDIN1 <18>
AC97_BITCLK <18,26>

C302

0.1U_0402_16V4Z

+5VS

1

C22

0.1U_0402_16V4Z

2

AC97_SYNC <18,26>

KSI_D_14<31>
KSI_D_8<16,31>
KSI_D_12<30,31>
KSI_D_10<16,31>
KSI_D_0<31>
KSI_D_4<31>
KSI_D_2<31>
KSI_D_1<31>
KSI_D_3<31>

KSI_D_5<31>
KSI_D_6<31>
KSI7<31>
KSI_D_13<31>
KSI_D_11<16,30,31>
KSI_D_9<16,31>

KSI_D_11
KSI_D_9
KSO9

KSO7
KSO6
KSO10
KSO1

KSO11
KSO0
KSO2
KSO5

4 5
3
2

100P_1206_8P4C_50V8@

4 5
3
2

100P_1206_8P4C_50V8@

4 5
3
2

100P_1206_8P4C_50V8@

KSO[0..11]<31>

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9

CP1

6
7
81

CP3

6
7
81

CP7

6
7
81

JP6

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

ACES_85203-3002

KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10

KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1

KSI_D_5
KSI_D_6
KSI7
KSI_D_13

KSI_D_3
KSO3
KSO8
KSO4

TrackPoint CONN. TP BD.

JP14

1

SP_DATA

2

3

4

5

6

7

8

ACES_87153-0801L

SP_CLK

+5VS

TP_DATA<31>

TP_CLK<31>

TP_DATA
TP_CLK

SP_DATA
SP_CLK

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

+5VS

KSO[0..11]

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

4 5
3
2

100P_1206_8P4C_50V8@

4 5
3
2

100P_1206_8P4C_50V8@

4 5
3
2

100P_1206_8P4C_50V8@

4 5
3
2

100P_1206_8P4C_50V8@

ACES_87212-0800

KSO11

30

KSO0

29

KSO2

28

KSO5

27

KSI_D_14

26

KSI_D_8

25

KSI_D_12

24

KSI_D_10

23

KSI_D_0

22

KSI_D_4

21

KSI_D_2

20

KSI_D_1

19

KSI_D_3

18

KSO3

17

KSO8

16

KSO4

15

KSO7

14

KSO6

13

KSO10

12

KSO1

11

KSI_D_5

10

KSI_D_6

9

KSI7

8

KSI_D_13

7

KSI_D_11

6

KSI_D_9

5

KSO9

4
3
2
1

CP6

6
7
81

CP5

6
7
81

CP2

6
7
81

CP4

6
7
81

JP17

1
2
3
4
5
6
7
8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-2211

of

32 48Thursday, September 09, 2004

0.6

A

B

C

D

E

1 1

ON/OFF#<30,32>

MDO2+<24>
MDO2-<24>

MDO0+<24>
MDO0-<24>

2 2

3 3

D_VSYNC<15>
D_HSYNC<15>

D_DDCDATA<15>

D_DDCCLK<15>

DVI_DETECT<16>

D_RED<9,15>

D_GREEN<9,15>

D_BLUE<9,15>

COMPS<9,15>

CRMA<9,15>

LUMA<9,15>

DCD#1<29>

RI#1<29>
DTR#1<29>
CTS#1<29>
RTS#1<29>
DSR#1<29>

TXD1<29>
RXD1<29>

LPTSTB#<29>
LPTAFD#<29>

LPTERR#<29>

ON/OFF#
MDO2+

MDO2­MDO0+

MDO0-

LAN_ACT#_DOCK
LANLINK_STATUS#_DOCK

D_VSYNC
D_HSYNC
D_DDCDATA
D_DDCCLK
DVI_DETECT

D_RED
D_GREEN
D_BLUE

COMPS
CRMA
LUMA

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

LPTSTB#
LPTAFD#
LPTERR#

KC FBM-L18-453215-900LMA90T_1812

VIN

C72

1000P_0402_50V7K

L10

12

1

2

JP30A

P1G1

83

1

84

2

85

3

86

4

87

5

88

6

89

7

90

8

91

9

92

10

93

11

94

12

95

13

96

14

97

15

98

16

99

17

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

JAE_SP03-14588-PCL03

DOCKVIN

1

C73
1000P_0402_50V7K

2

DOCKVIN

DETECT
MDO3+

MDO3­MDO1+

MDO1­PWR_LED

1 2

R515 1K_0402_5%

DVI_DDC_CLK
DVI_DDC_DAT

DVI_TX2­DVI_TX2+

DVI_TX1­DVI_TX1+

DVI_CLK­DVI_CLK+

DVI_TX0­DVI_TX0+

MDO3+ <24>
MDO3- <24>

MDO1+ <24>
MDO1- <24>

SLP_S5#_5R

DVI_DDC_CLK <16>
DVI_DDC_DAT <16>

DVI_TX2- <16>
DVI_TX2+ <16>

DVI_TX1- <16>
DVI_TX1+ <16>

DVI_CLK- <16>
DVI_CLK+ <16>

DVI_TX0- <16>
DVI_TX0+ <16>

DOCK CONN. 184PIN

LPTACK#<29>
LPTBUSY<29>

LPTPE<29>

LPTSLCT<29>

LPD7<29>
LPD6<29>
LPD5<29>
LPD4<29>
LPD3<29>
LPD2<29>
LPD1<29>
LPD0<29>

LPTSLCTIN#<29>

LPTINIT#<29>

USB20_N4<19>

USB20_P4<19>
USB20_N5<19>
USB20_P5<19>
SER_SHD<29>

EXPCRD_RST#<29>

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

USB20_N4
USB20_P4
USB20_N5
USB20_P5
SER_SHD

EXPCRD_RST#
DETECT

JP30B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

165

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND

GND

G2

G2

RING

JAE_SP03-14588-PCL03

RING

166
167
168
169
170

128

128

129

129

130

130

131

131

132

132

133

133

134

134

135

135

136

136

137

137

138

138

139

139

140

140

141

141

142

142

143

143

144

144

145

145

146

146

147

147

148

148

149

149

150

150

151

151

152

152

153

153

154

154

155

155

156

156

157

157

158

158

159

159

160

160

161

161

162

162

163

163

164

164

171
172
173
174
175
176

P2

P2

TIP

TIP

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

DLINE_IN_L
DLINE_IN_R

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXP2
PCIE_TXN2

PCIE_RXP2
PCIE_RXN2

CLK_PCIE_DOCK
CLK_PCIE_DOCK#
PREP#

VA_ON#

12

R66
1K_0402_5%

+5VS

DOCK_MOD_TIPDOCK_MOD_RING

KBD_DATA <31>
KBD_CLK <31>
CPPE# <14,17>
PS2_DATA <31>
PS2_CLK <31>
DOCK_HPS# <27>

DLINE_IN_L <26>
DLINE_IN_R <26>

DLINE_OUT_L <27>
DLINE_OUT_R <27>

PCIE_TXP2 <19>
PCIE_TXN2 <19>

PCIE_RXP2 <19>
PCIE_RXN2 <19>

CLK_PCIE_DOCK <14>
CLK_PCIE_DOCK# <14>
PREP# <19,24>

1

C59

0.1U_0402_16V4Z

2

+3VALW +5VALW

LAN_ACT#_DOCK

13

R527

V_3P3_LAN

4 4

12

10K_0402_5%

A

D

2

G

S

13

D

2

G

S

Q62
2N7002_SOT23

LAN_ACT#

LANLINK_STATUS#_DOCK

Q63
2N7002_SOT23

LANLINK_STATUS#

LAN_ACT# <23,24>

LANLINK_STATUS# <19,23,24>

B

STB_LED#<30,31,32>

SLP_S3#<19,23,26,27,31,34>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R526
10K_0402_5%

PWR_LED

13

D

Q59

2

2N7002_SOT23

G

S

C

SLP_S5<21,25,34>

2

G

D

12

R529
100K_0402_5%

SLP_S5#_5R

13

D

Q65
2N7002_SOT23

S

DOCK_MOD_TIP
DOCK_MOD_RING

Title

Size Document Number Rev
Custom

LA-2211

Date: Sheet

JP29

1
2

ACES_88231-0200

Compal Electronics, Inc.

SPR Connector

of

33 48Thursday, September 09, 2004

E

0.6

A

B

C

D

E

+1.5VALW to +1.5VS Transfer +3VALW to +3VS Transfer

+1.5VALW

U28

8

D

7

1

C501
10U_1206_16V4Z

2

+1.5VALW

D

6

D

5

D

SI4800DY_SO8

1 1

S
S
S
G

2

1 3

D

Q42

AO3400_SOT23@

1
2
3
4

G

+1.5VS

S

1

C455

2

10U_1206_16V4Z

RUNON

+1.5VS

0.1U_0402_16V4Z

1

C463

2

12

R431
475_0402_1%

13

D

S

SLP_S3

2

G

Q47
2N7002_SOT23

+1.8V to +1.8VS Transfer

C478

1U_0603_10V4Z

+1.8V

SI2306DS-T1 1N_SOT23

1

2

RUNON

+1.8VS +3VS+3VALW

Q41

D

S

1 3

1

C492

G

2

1U_0603_10V4Z

2

R139

330K_0402_5%

J1

SHORT PADS

SLP_S3

2

G

B+

12

12

13

D

S

1

C127

2

10U_1206_16V4Z

100K_0402_5%@

Q18
2N7002_SOT23

R138

U13

8

D

7

D

6

D

5

D

SI4800DY_SO8

RUNON

12

1

S

2

S

3

S

4

G

12

R469
470_0402_5%

1

C120

0.01U_0402_25V7Z

2

1

C132

2

0.1U_0402_16V4Z

1

C128
10U_1206_16V4Z

2

+2.5VALW to V_2P5_LAN Transfer +2.5VALW to +2.5VS Transfer

V_2P5_LAN+2.5VALW +2.5VS+2.5VALW

Q13

2 2

1U_0603_10V4Z

ENAB_LAN_V#<23,41>

SI2301DS_SOT23

1

C87

2

13

1

2

C83
1U_0603_10V4Z

2

+5VALW

12

R125
100K_0402_5%

C93

1U_0603_10V4Z

Q15

SI2306DS-T1 1N_SOT23

D

1 3

1

2

RUNON

G

2

S

1

C103
1U_0603_10V4Z

2

+5VALW

12

R135
100K_0402_5%

+5VALW to +5VS Transfer

1

C86

2

10U_1206_16V4Z

U9

8

D

7

D

6

D

5

D

SI4800DY_SO8

S
S
S

G

RUNON

1
2
3
4

+5VS+5VALW

1

C71

2

0.1U_0402_16V4Z

1

C77
10U_1206_16V4Z

2

SLP_S3

13

3 3

SLP_S3#<19,23,26,27,31,33> SLP_S5#<19,21,22,23,28,40>

SLP_S3#

D

Q19

2

2N7002_SOT23

G

S

SLP_S5<21,25,33>SLP_S3<41>

SLP_S5

SLP_S5#

13

D

Q22

2

2N7002_SOT23

G

S

Discharge circuit

+0.9VS +1.5VS

12

R188
470_0402_5%

13

4 4

SLP_S3

D

Q27

2

2N7002_SOT23

G

S

A

SLP_S3 SLP_S3 SLP_S3 SLP_S3 SLP_S3

12

R151

470_0402_5%@

13

D

Q24

2

2N7002_SOT23@

G

S

+1.8VS

12

R95
470_0402_5%

13

D

Q14

2

2N7002_SOT23

G

S

B

+2.5VS

12

R130
470_0402_5%

13

D

Q21

2

2N7002_SOT23

G

S

+3VS +5VS

12

R134
470_0402_5%

13

D

Q17

2

2N7002_SOT23

G

S

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

12

R116

470_0402_5%

13

D

Q16

2

2N7002_SOT23

G

S

D

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuits

LA-2211

E

34

of

48Thursday, September 09, 2004

0.6

+1.8VS

+3VS+3VS

+3VL+3VL

R89

1K_0402_5%

330_0402_5%

1 2

R82

2

B

330_0402_5%

1 2

C

Q11

MMBT3904_SOT23

E

3 1

R37

560K_0402_5%

R281

2

B

12

1 2

C

Q10

MMBT3904_SOT23

E

3 1

+5VS

12

1

2

+2.5VS

12

1

2

14

1

7

R43
180K_0402_5%

C47

0.47U_0603_10V7K

R23
180K_0402_5%

C24

0.47U_0603_10V7K

U5A

P

O2I

G

SN74LVC14APWLE_TSSOP14

5

11

R38

1 2

100K_0402_5%

1U_0603_10V4Z

+3VL

1

C25

0.1U_0402_16V4Z

2

14

U5C

P

O6I

G

SN74LVC14APWLE_TSSOP14

7

+3VL

14

U5E

P

O10I

G

SN74LVC14APWLE_TSSOP14

7

14

U5B

P

3

O4I

G

SN74LVC14APWLE_TSSOP14

1

C48

7

2

13

D

Q9

2

G

2N7002_SOT23

S

13

D

Q2

2

2N7002_SOT23

G

S

D8

21

RB751V_SOD323

+3VS

J2

1 2

SHORT PADS

12

R47
10K_0402_5%

PWR_GD <31,40,43>

+3VL

12

R24
560K_0402_5%

1

C26

0.1U_0402_16V4Z

2

EMI Clip PAD

EP1

1

PAD_177X80@

EP2

1

PAD_177X80@

1

1

H29
HOLEA

H14
HOLEA

H12
HOLEA

+3VL

12

2

1

1

H9
HOLEA

H18
HOLEA

H1
HOLEA

G

1

1

1

FM4

CF9

R7
10K_0402_5%

13

D

Q3
2N7002_SOT23

S

FM5

1

CF10

1

H4
HOLEA

1

H19
HOLEA

1

H27
HOLEA

1

1

1

H5
HOLEA

H21
HOLEA

H13
HOLEA

CF6

CF4

1

1

1

VCC1_PWRGD <31>

CF8

1

1

CF12

1

1

H17

H25

HOLEA

HOLEA

1

1

H15

H22

HOLEA

HOLEA

1

1

H30

H26

HOLEA

HOLEA

1

1

CF7

CF11

H28
HOLEA

H23
HOLEA

H31
HOLEA

1

1

1

H32
HOLEA

1

+3VL

14

U5D

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

FM3

FM6

1

CF5

1

H2
HOLEA

1

H16
HOLEA

1

H8
HOLEA

1

FM1

1

CF3

1

H3
HOLEA

1

H24
HOLEA

1

H11
HOLEA

1

FM2

1

CF1

CF2

1

H10
HOLEA

1

1

H6
HOLEA

1

1

H20
HOLEA

1

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev
Custom

Date: Sheet

Compal Electronics, Inc.

POK CKT

LA-2211

of

35 48Thursday, September 09, 2004

0.6

5

D D

4

3

2

1

AC
Adapter
in

ADPPWR

VIN

VS

SWITCH

B+ B+

C C

BATT+

CELLSEL

51_ON#

VMB

MAX1908
Charger

VS

1908REF

TPO610T
SWITCH

MAINPWON

RUN

MAX1999
DC/DC
(3V/5V)

SHDN#

LM358
Thermal
Protector

2.5VREF

VL

+3VALWP

+5VALWP

B+

MAX1845
DC/DC
(1.8V/1.05V)

Vcc

+1.5VS

+1.8VALW

CM8562
DC/DC
(0.9V)

+1.8VSP 7.5A
DDR II

EN

+0.9V 1A

SUSP#

+5VS

VR_ON

VCC SHDN#

MAX1532
DC/DC
(CPU_CORE)

CPU_CORE
(+1.38V 27A)

B B

G920AT24U

CHGRTC

+5VALW/SYSON#

ON1/ON2

+1.05VSP 6.4A

RTC BATT
Charger

ADPPWR

VIN

FSTCHG
A/B#USE
ACIN#

BATT+

A A

BATT+

VS

1908REF
CELLSEL

MAX1538
Battery
Selector

LM393
BATT OVP

5

BATT_VID

B+

CHG/DIS

SWITCH

BATT_OVP

Battery A
8 Cell

Battery
Connector
A

BATT_A

Battery B
8 Cell

B+

VMB

Battery

+5VALW

VMB_A VMB_B

Connector
B

BATT_B

4

3

MAX1845
DC/DC
(2.5V/1.5V)

ON1/ON2

Vcc

+1.5VALW 2A

LM358
DC/DC
(1.2VLAN)

+1.2VLAN 2A

EN

ENAB_3VLAN

+2.5VALW 1A

Title

POWER BLOCK DIAGRAM

Size Document Number Rev

A4

LA-2211 0.5

Date: Sheet

2

36 47Thursday, September 09, 2004

of

1

A

B

C

D

PCN1

123

3

4

1 1

SINGATRON_2DC_S736I201

1

ADPIN

2

4

PD2

@EC10QS04_SOD106

PC1

100P_0402_50V8J

12

FBM-L18-453215-900LMA90T_1812

12

12

PCN2

1

BATT+

SMD
SMC

GND

SUYIN_200275MR006G113ZL

2 2

B/I
TS

2
3
4
5

6

100_0402_5%

EC_SMD_A

EC_SMC_A
AB/I_A

PR4

12

PR5

100_0402_5%

PR1

TS_A

PR3
1K_0402_5%

1 2

1K_0402_5%

1 2

PR2

210K_0402_1%

12

12

EC_SMD_A1
EC_SMC_A1

PL1

1 2

PC2
1000P_0402_50V7K

12

PC3

100P_0402_50V8J

VMB_A

12

+3VL

12

PC4

1000P_0402_50V7K

PL2

FBM-L18-453215-900LMA90T_1812

1 2

PC5
1000P_0402_50V7K

12

THM_MAIN# <31>

AB1A_DATA <31>
AB1A_CLK <31>

VIN

12

PR270
@15K_0402_5%

PC6

0.01U_0402_50V4Z

BATT_A <38>

VMB_A

VMB_B

200_0805_5%

PR7

PD3

1N4148_SOD80

PD6

1N4148_SOD80

12

PR295

VIN

21

PD5
EP10QY03

12

PR6
47_1206_5%

12

PC7

0.1U_0603_50V4Z

PD40

1N4148_SOD80

VS

12

12

PR298

1 2

47_1206_5%

1.5K_1206_5%

1 2

PR296

12

1 2

1.5K_1206_5%

1 2

1.5K_1206_5%
PR297

P4

G920AT24U_SOT89

3 3

PCN3

1

BATT+

8

GND

7

GND

SUYIN_20163S-06G1-K

SMD
SMC

GND

TS

B/I

EC_SMD_B

2

EC_SMC_B

3

AB/I_B

4

TS_B

5
6

PR15

100_0402_5%

2

+3VL

3

1

PD43
@SM24_SOT23

PR10

12

1K_0402_5%

1 2

PR11

PR12
1K_0402_5%

1 2

12

12

PR16

@SM05_SOT23

100_0402_5%

210K_0402_1%

PD42

3

1

2

EC_SMD_B1

EC_SMC_B1

4 4

A

VMB_B

PL3

FBM-L18-453215-900LMA90T_1812

1 2

12

PC9
1000P_0402_50V7K

THM_MBAY# <31>

AB1B_DATA <31>
AB1B_CLK <31>

B

BATT_B <38,44>

12

PC10

0.01U_0402_50V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHGRTCP

12

C

PU1

2

IN

PC12
1U_0805_50V4Z

OUT

GND

1

RTCVREF

1 2

PR14

200_0402_5%

Compal Electronics, Inc.

D

12

PC11

10U_1206_10V4Z

1 2

PR13

200_0402_5%

3

Title

BATTERY CONN

Size Document Number Rev

B

Date: Sheet of

CHGRTC

37 47Thursday, September 09, 2004

A

+3VL

12

PR165

PR268

PQ52

2

G

D

S

12

PQ55

47K_0402_5%

12

PR167

47K_0402_1%

13

D

S

1908LDO

1 2

332K_0402_1%

1908LDO

PR37

1 2

100K_0402_5%

ACOK

PD38

1N4148_SOD80

12

13

D

RHU002N06_SOT323

G

S

2200P_0402_50V7K

12

47K_0402_1%

RHU002N06_SOT323

1U_0805_50V4Z

PR277

@91K_0402_1%
PR33

12

PC27

12

ACIN#

2

12

PR166

47K_0402_5%

1 1

12

BATSELB_A#

13

PQ53

2

G

RHU002N06_SOT323

12

PC20

1U_0603_10V6K

PR24

91K_0402_1%

1 2

12

12

PC21

2 2

PR28

100K_0402_1%

CHGCTRL<31>

0.1U_0402_16V7K

VIN

ACIN#

PR39

1 2

10.2K_0603_0.1%
PR273

20K_0402_1%

PR42

1 2

1.87K_0603_0.1%

3 3

VIN

PR275

20K_0402_5%

PQ73

TP0610T_SOT23

1 3

D

2

1 2

RHU002N06_SOT323

PQ75

13

D

2

G

KBC_PWR_ON<31,39>

S

PC19

1 2

1908REF

0_0402_5%

+3VL

12

1 2

1U_0603_6.3V6M

12

PR29

PR278

@150K_0402_1%

PR32

1 2

0_0402_5%

1908_IINP

PR36

499K_0402_1%

12

1 2
12

12

PR43

PC35

1 2

10K_0402_1%

0.01U_0402_16V7K

CHGCTRL(V)=1.22(V/A)*Icharger(A)
CHGCTRL=0.73~3.3V

VS

S

G

PR316

1 2

100K_0402_5%

PR317

PQ74

47K_0402_5%

RHU002N06_SOT323

13

D

2

G

S

PU3

MAX1908ETI_QFN28

1

DCIN

17

CELLS

4

REF

3

CLS

12

REFIN

15

VCTL

13

ICTL

11

ACOK#

8

SHDN#

10

ACIN

9

ICHG

28

IINP

7

CCV

CCI

6

PR40

1K_0402_1%

12

PC32

PC30

0.1U_0402_16V7K

0.01U_0402_16V7K

12

PC167

0.22U_0805_16V7K_V2

VIN

PR319

47K_0402_5%

1 2

PR318

1 2

100K_0402_5%

CCS

GND

5

14

PGND

20

CSSP

CSSN

DLO

DLOV

LDO

CSIP
CSIN

BATT

DHI

LX

BST

0.1U_0603_25V7K

27

26

25

23

21

24

22
2

19
18
16

12

PC31

0.01U_0402_16V7K

PC159

1908_IINP

PR280

12

100K_0402_1%

1908REF

12

PR281

10K_0402_1%

12

12

PC160

1000P_0402_50V7K

4 4

2

3

G

-

1

+

P

5

11.5K_0402_1%
PR283

PU17
LMV321M7_SC70-5

4

O

+5VS

A

PR250

215K_0402_1%

12

12

PR191

1 2

118K_0402_1%

12

0.015U_0603_25V7K

PR194

1 2

215K_0402_1%

8

PU16B

5

P

+

6

-

G

LM393M_SO8

4

PR193

18.7K_0603_1%

PC47

7

O

1 2

PR192 267K_0402_1%

PD36

12

1N4148_SOD80

12

PD37

1 2

1N4148_SOD80

PR196
10K_0402_1%

0_0402_5%

P4

0.012_2512_1%

1 2

1908LDO

PR44

1 2

0_0402_5%

12

LM393M_SO8

PR274

1 2

0_0402_5%

B

PR20

1 2

PC14

1 2

0.1U_0603_25V7K

PR34

2.2_0402_5%

1 2

1 2

PR35

33_1206_5%

PC28

1 2

1U_0603_10V6K

BATT

PR263

PU16A

2
3

B

PC15

­+

+5VS

DLCHG

4

G

P

8

B+

1 2

O

1

12

PC18

2

4.7U_1206_25V6K

PQ4

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

LXCHG

BSTCHG

PD15

12

1SS355_SOD323

PC29

1U_0603_10V6K

+5VS

12

PR197
47K_0402_5%

1

PQ2
SI4835BDY_SO8

1
2
3 6

ACIN#

RHU002N06_SOT323

PC17

10U_1206_25V6M

8

G2

7

D1/S2/K

6

D1/S2/K

5

D1/S2/K

DHCHG

PL5

1 2

15U_PLFC1045P-150A_3.7A_20%

12

PC22

0.1U_0603_50V4Z

CC=0.5~3A
CV=12.6V(6 CELLS LI-ION)

16.8V(8 CELL LI-ION)

OVP_OV# <19>

13

D

PQ47

2

G

RHU002N06_SOT323

PR200
470K_0402_5%

S

12

C

4

PQ50

ACIN<39,44>

1 2

13

D

2

G

S

PR255

1 2

10K_0402_5%

PR27

0.015_2512_1%

3K_0402_5%

VIN

8
7

5

12

PR300

12

PR262

1 2

10K_0402_5%

12

PZD1
RLZ4.3B_LL34

BATT

1

PC23

2

4.7U_1206_25V6K

FDS4935_SO8

12

10K_0402_5%

PR294

1 2

PC25

10U_1206_25V6M

DISB

DCIN

PR312

PQ31

150K_0402_5%

2

G

PQ5

20K_0402_5%

4

5

8

1

PR157

13

D

PQ51

S

ACON <44>

47P_0402_50V8J

36

241

3

1

2

S1

S2

G2

G1

D2

D1

D2

D1

8

7

6

5

7

6

D2

D1

D2

D1

G2

S1

S2

G1

2

3

4

SI4835BDY_SO8

8
7

5

12

PQ76
DTA144EUA_SC70

1 3

RHU002N06_SOT323

SI4835BDY_SO8

578

PQ32

FDS4935_SO8

12

PR302

2K_0402_5%

BATT_B<37,44> BATT_A <37>

13

D

PQ65

RHU002N06_SOT323

+3VL

CHRG

12

13

D

2

RHU002N06_SOT323

G

13

S

D

PQ79

S

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE

RHU002N06_SOT323

SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.

PR321

PQ78

G

S

100K_0402_5%

ADP_PRES

2

C

2

G

RHU002N06_SOT323

PQ62

PC168

1 2

PR269
0_0402_5%

D

S

PQ3

PR156

4

200K_0402_5%

47K

47K

2

1 2

PR299

3K_0402_5%

12

PR301

2K_0402_5%

13

2

G

1
2
36

PR320

ADPPWR

DCIN

12

12

PR308

10_1206_5%

47K_0402_5%

1 2

D

S

Travel<44>

D

VIN

PQ48

TP0610T_SOT23

D

S

13

1 2

PR253

887K_0603_1%

G

2

ADPPWR

12

DCIN

42.2K_0603_0.1%

1 2

1U_0805_50V4Z

12

PC13

PU2

11

ADPIN

12

ADPPWR

13

REVBLK

16

EXTLD

14

ADPBLK

18

DISBAT

17

CHGIN

19

CHGA

20

CHGB

23

DISB

24

DISA

22

BATB

25

BATA

PC33

1 2

0.01U_0603_50V7K

OUT0

BATSELB_A#

CHRG

PQ67

13

RHU002N06_SOT323

2

G

ADP_PRES

Title

Size Document Number Rev

Custom

Date: Sheet

ACDET

10

AIRDET

PR18

1.62K_0603_0.1%

9

ACDET

CHRG

BATSEL

RELRN

OUT2
OUT1
OUT0

12

PR17

MAX1538_QFN28

BATSUP

NC
NC

VDD

MINVA

GND

27

PC34

1 2

0.01U_0603_50V7K

+3VL

2

A

1

B

1

1

2

PR38

200K_0402_1%

1 2

PR41

1 2

200K_0402_1%

5

PU19
74LVC1G86_SOT353

P

4

Y

G

3

+3VL

PU18

SN74LVC1G17DBVR_SOT23-5

5

P

O4I
NC

G

3

+3VL

5

PU20

2

P

I0

O

1

I1

G

TC7SH32FU_SSOP5

3

MINVB

PR256

100K_0402_1%

PR257

1 2

2

12

PD41

4

200K_0402_1%

1N4148_SOD80

Compal Electronics, Inc.

Charger

D

PR19

5.49K_0603_0.1%

1 2

CHRG

5
3

4

8
7
6

VS

26
21

15

28

12

PC36

+3VL

2

G

PC166

0.022U_0603_25V7K

12

PR304

12

12

PR279

1M_0402_1%

PR22

1 2

0_0402_5%

OUT1

12

PC26

1U_0805_50V4Z

12

1U_0603_10V4Z

12

PR306

200K_0402_5%

13

D

PQ69

RHU002N06_SOT323

S

12

PR311

0_0402_5%

470K_0402_1%

38 47Thursday, September 09, 2004

1SS355_SOD323

PD39

PR310

10K_0402_5%

12

PC16

0.1U_0402_16V7K

BATSELB_A#<31>

OUT2<31>

PR309

0_0402_5%

12

OUT0 <31>

ADP_PRES<23,31>

12

PR26

PR30

1 2

100K_0402_5%

200K_0402_5%

PR313

@200K_0402_5%

ADP_PRES

2

G

1 3

D

S

PQ68

RHU002N06_SOT323

BATCON<31>

12

of

CHGCTRL

1 2

12

0.5

A

B

C

D

E

+3.3V/+5V

B+

1 1

PL6
FBM-L18-453215-900LMA90T_1812

1 2

2 2

B++

1

12

PC48

2

2200P_0402_50V7K

10U_SPC-1204P-100_4.5A_20%

PQ9

1

G2

D2

PC50

10U_1206_25V6M

PL18

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

AO4912_SO8

12

+5VALWP

VS

PC63

1

PR71

+

1 2

1 2

@10.2K_0402_1%

PR76

0_0402_5%

2

150U_D_6.3VM

3 3

PR74

47K_0402_5%

0.1U_0603_50V4Z

5HG

8
7
6
5

DL5

12

12

PC66

0.1U_0603_25V7K

PC44

1 2

PR57

0_0402_5%

1 2

LX5

DH5

ACIN<38,44>

12

PC67

0.1U_0603_16V7K

RHU002N06_SOT323

PR56
0_0402_5%

1 2

BST5A

PR67

10K_0402_5%

1 2

2VREF_1999

MAINPWON <18,41,44>

PR314

13

D

2

PQ70

G

S

14
16
15

19
21

9
1

6
4
3

12

8

12

PC164

+3VL

12

100K_0402_5%

13

D

2

G

PQ77

S

RHU002N06_SOT323

3

1

4.7_1206_5%

PC162

VL

12

PC51

4.7U_0805_10V4Z

BST5
DH5
LX5

DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#
REF

0.22U_0603_10V7K

ACIN

2

PD17
CHP202U_SC70

VS

12

PR288

12

4.7U_1206_25V6K

12

0.1U_0603_50V4Z

PC52

13

20

18

V+

TON

LD05

PU7

MAX1999EEI_QSOP28

GND

LDO3

23

25

12

PC165

4.7U_0805_10V4Z

13

D

2

G

PQ71

S

RHU002N06_SOT323

VL

1 2

17

VCC

ILIM3

ILIM5
BST3

OUT3

PGOOD

PRO#

10

+3VLP

1 2

PR287

47_0402_5%

12

PC163

5

11
28

26

DH3

24

DL3

27

LX3

22
7

FB3

2

PR293
0_0402_5%

BST3BBST5B

12

PC161

0.1U_0603_16V7K

2VREF_1999

PR289

1 2

PR291

1 2

220K_0402_1%

499K_0402_1%

1U_0805_16V7K

KBC_PWR_ON <31,38>

1 2

1 2

PR290

PR292

499K_0402_1%

220K_0402_1%

0.1U_0603_50V4Z

PR54
0_0402_5%

1 2

BST3A

PC43

1 2

DH3

B++

12

PC45

0_0402_5%

2200P_0402_50V7K

PR53

12

PC46

4.7U_1206_25V6K

1 2

PQ8

1

D2

2

D2

3

G1

4

S1/A

AO4912_SO8

3HG

LX3

DL3

D1/S2/K
D1/S2/K
D1/S2/K

8

G2

7
6
5

12

PL7

10U_SPC-1204P-100_4.5A_20%

+3VALWP

1

+

PC59

2

150U_D_6.3VM

1 2

1 2

PR68

@3.57K_0402_1%

PR75

0_0402_5%

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

B 0.1

Date: Sheet

Compal Electronics, Inc.

3.3V / 5V

LA-2211

of

39 47Thursday, September 09, 2004

E

A

1 1

1

12

PC69
10U_1206_25V6M

2

PC68

2200P_0402_50V7K

5

PQ12

D8D7D6D

AO4404_SO8

S1S2S3G

4

2 2

3 3

SKS10-04AT_TSMA

+1.8VP

PD23

2 1

1

+

2

12

PC80

220U_D2_4VM

PC81

4.7U_0805_6.3V6K

PL9

4.7UH_PLFC1045P-4R7A_5.5A_30%

1 2

AO4702_SO8

PQ14

5

D8D7D6D

S1S2S3G

4

0.1U_0603_50V4Z
PC78

1 2

SLP_S5#<19,21,22,23,28,34>

SLP_S4#<19>

B

PD22

2

CHP202U_SC70

BST1.8

12

PR84

0_0402_5%

C

B++++

PR78

0_0402_5%

1 2

1U_0805_50V4Z

1

3

1 2

PR79

0_0402_5%

1 2

0_0402_5%

PR87

PC75

12

1U_0805_16V7K

12

4

BST1

V+
DH1
LX1

DL1

MAX1845EEI_QSOP28

CS1
OUT1

FB1

ON1

GND

OVP

8

23

PR160

@0_0402_5%

PR161

0_0402_5%

PC77

MAX1845_VCC

12

22

VCC

PU8

SKIP

6

12

12

0.1U_0603_50V4Z
PC76

25

DH1.8

26

LX1.8

27

DL1.8 DLVCCP

24
28

1
2

11

MAX1845_VCC

PR80

20_0603_5%

1 2

9

VDD

UVP

BST2

DH2
LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR201

10

20K_0402_1%

0_0402_5%

12

PC86

0.22U_0603_10V7K

PR90

21
19

18
17
20
16

15
14
12

7
5

13
3

+5VALW

12

12

12

PC71

4.7U_1206_16V4Z

BSTVCCP

PR81

0_0402_5%

1 2

BST2VCCP

DHVCCP

1 2

12

0_0402_5%

PR91

100K_0402_1%

12

PC79

0.1U_0603_50V4Z

12

PR82

PR86
0_0402_5%

PR202
100K_0402_1%

12

PQ13

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

AO4912_SO8

LXVCCP

PWR_GD <31,35,43>

D

PL8

FBM-L18-453215-900LMA90T_1812

1 2

B+

12

12

PC72

PC73

8
7
6
5

PL10

3.3UH_PLFC0745P-3R3A_4.8A_30%

1 2

4.7U_1206_25V6K

2200P_0402_50V7K

+1.05V_VCCP

PD24

1

PR85

PR88

12

+

SKS10-04AT_TSMA

PC82

PC83

2 1

2

4.7U_0805_6.3V6K

220U_D2_4VM

12

5.1K_0402_1%

12

100K_0402_1%

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDRII/+1.05VSP/+1.8VSP

Size Document Number Rev

Custom

Date: Sheet

D

40 47Thursday, September 09, 2004

of

5

4

3

2

1

PH1 under BATT botten side :

+1.5VS

D D

10U_0805_10V4Z

PC87

+0.9VSP

1A

1

PC93

22U_1206_6.3V6M

C C

2

+1.5VALW

12

12

PR92
10_0603_1%

12

PC94

0.1U_0603_50V4Z

10U_0805_10V4Z

12

PC88

+3VS

PU9

1

VIN

2

VFB

3

VTT

4

VTT

PGND

AGND

VCCA

REFEN

AGND

CM8562IS_PSOP8

9

100K_0402_1%

PR95

8

7

6

5

12

12

PC92
4700P_0603_50V7K

13

D

S

12

+1.8VP

PR94

100K_0402_1%

1 2

2

G

PQ16
RHU002N06_SOT323

PC90
10U_0805_10V4Z

SLP_S3 <34>

PC96

0.22U_0603_16V7K

CPU

12

CPU thermal protection at 90 +-3 degree C
Recovery at 43 +-3 degree C

VL

PR100

47K_0402_1%

1 2

VL

PTH1
10K_1%

PR96
15K_0603_1%

1 2

VL

12

PR98

2.55K_0603_1%

1 2

PR97
150K_0402_1%

PR99

150K_0402_1%

12

12

PC95
1000P_0402_50V7K

PU10A

3
2

8

P

+

-

G

4

12

PC91

0.1U_0603_16V4Z

1

0

LM358A_SO8

2

G

VL

PR77
499K_0603_1%

1 2

13

D

S

PQ72
RHU002N06_SOT323

MAINPWON<18,39,44>

12

PQ17

PR101

0_1206_5%

12

PC98

B B

A A

4.7U_1206_16V4Z

SI3442DV

D

6

S

2
1

5

45

G

3

PU10B

7

0

LM358A_SO8

1 2

PC101

1000P_0402_50V7K

12

12

PR102
0_0402_5%

PR103

5.1K_0402_1%

5

+

6

-

12

PR106

5.1K_0402_1%

PC99
47P_0402_50V8J

1 2

12

PC100

330P_0402_25V8K

12

PR105

4

13

D

150K_0402_1%

S

PR104

100K_0402_1%

PQ18

2

G

RHU002N06_SOT323

+1.2VLANP

1

PC97
22U_1206_6.3V6M

2

12

2VREF

ENAB_LAN_V#<23,34>

Title

<Title>

Size Document Number Rev

B

3

2

Date: Sheet of

LA-2211

41 47Thursday, September 09, 2004

1

0.5

A

PC138

2200P_0402_50V7K

12

12

1 1

AO4912_SO8

5

D1/S2/K

6

D1/S2/K

7

D1/S2/K

8

G2

PQ36

PL16

+1.5VALWP +2.5VALWP

1

+

PD32

2 1

SKS10-04AT_TSMA

2 2

12

PC148

2

PC149

220U_B2_2.5VM

4.7U_0805_6.3V6K

3.3UH_PLFC0745P-3R3A_4.8A_30%

1 2

S1/A

4
3

G1

2

D2

1

D2

CHP202U_SC70

PC144

0.1U_0603_50V4Z

DL1.5 DL2.5

PC139

4.7U_1206_25V6K

3

BST1.5

1 2

12

1 2

PR173
0_0402_5%

B

MAx1845_B++

+5VALW

PR168

0_0402_5%

1U_0805_50V4Z

1

PD31

PC140

2

1 2

12

PR170

20_0603_5%

12

12

PC141

4.7U_1206_16V4Z

BST2.5

PR171

0_0402_5%

PC145

0.1U_0603_50V4Z

VCC_MAX1845

25
26
27

24
28

1
2

11

@0_0402_5%

DH1.5

LX1.5 LX2.5

12

0_0402_5%

PR175

VCC_MAX1845

12

4

1U_0805_16V7K

BST1

V+
DH1
LX1

DL1

MAX1845EEI_QSOP28

CS1
OUT1

FB1

ON1

GND

OVP

8

23

12

PR182

PR183

0_0402_5%

VCC_MAX1845

12

PC146

9

22

VCC

PGOOD

SKIP

6

10

2VREF

12

12

PC152

VDD

UVP

BST2

DH2
LX2
DL2
CS2

OUT2

FB2

ON2

TON

ILIM2
ILIM1

REF

PR177

301K_0402_1%

PR178

0_0402_5%

100K_0402_1%

21
19

18
17
20
16

15
14
12

7
5

13
3

PU15

12
12

PR179

PR172

0_0402_5%

1 2

DH2.5

12

12

0_0402_5%

1 2

0_0402_5%

PR176

PR180

100K_0402_1%

C

PC147

0.1U_0603_50V4Z

12

PR174

+5VALW+5VALW

12

AO4912_SO8

5

D1/S2/K

6

D1/S2/K

7

D1/S2/K

8

G2

PQ37

S1/A

4
3

G1

2

D2

1

D2

PL15

PL17

1 2

5U_TPRH6D38-5R0M-N_2.9A_20%

D

12

FBM-L11-322513-151LMAT_1210

12

PC142

2200P_0402_50V7K

12

PC143

12

PC151

4.7U_0805_6.3V6K

B+

4.7U_1206_25V6K

1

PD33

2 1

SKS10-04AT_TSMA

+

PC150

2

150U_B2_4VM

0.22U_0603_10V7K

3 3

1.5VALWP/ +2.5VALWP

PJP2

+1.5VALWP

+1.8VP

+1.05V_VCCP

+2.5VALWP

4 4

+3VLP

+0.9VSP

1 2

PAD-OPEN 3x3m

PJP4

PAD-OPEN 4x4m

1 2

PJP6

PAD-OPEN 4x4m

1 2

PJP7

1 2

PAD-OPEN 3x3m

PJP9

2 1

PAD-OPEN 2x2m

PJP10

1 2

+1.5VALW

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.= 12)

+VCCP

(400mA,40mils ,Via NO.= 1)

+2.5VALW

(100mA,20mils ,Via NO.= 1)

+3VL

+0.9VS

(1A,40mils ,Via NO.= 2)

+5VALWP

(4.5A,180mils ,Via NO.= 9)

+3VALWP

(3A,120mils ,Via NO.= 6)

+1.2VLANP

PAD-OPEN 3x3m

A

PJP3

1 2

PAD-OPEN 4x4m

PJP5

1 2

PAD-OPEN 4x4m

PJP8

1 2

PAD-OPEN 3x3m

B

+5VALW

+3VALW

V_1P2_LAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Electronics, Inc.

Title

DDRII/+1.05VSP/+1.8VSP

Size Document Number Rev

Custom

Date: Sheet

D

42 47Thursday, September 09, 2004

of

5

4

3

2

1

+VCC_CORE

CPU VCC SENSE

PC122

1 2

PR135 3K_0402_1%

B+

1 2

@1000P_0402_50V7K

+5VS

+3VS

12

1 2

PR267

1 2

0_0402_5%

12

PC129

12

12

PR276
10K_0402_1%

13

D

PQ56
RHU002N06_SOT323

S

PR119 10_0402_5%

PC119
1U_0603_10V6K

VCC

REF

1 2

27P_0402_50V8J

PC118

DHM
LXM
DLM

PC121

PR147

PC134

BSTM

12

0.22U_0603_16V7K

1 2

2.2_0402_5%

12

0.22U_0603_16V7K

PR125
0_0402_5%

1 2

BSTM

1 2

PD28

2

3

CHP202U_SC70

PQ26

IRF7413Z_SO8
PR151

0_0402_5%

PQ23

2.2U_0603_6.3V4Z

10

VCC

24

D0

23

D1

22

D2

21

D3
D4
D5
VROK
S0
S1
SHDN#
TIME
CCV
TON
REF
ILIM
OFS
SUS
SKIP
GND

PU13

MAX1532

20
19
25

4
5
6
1

12

2
8
9
7

3
18
11

VDD

BSTM

DHM
LXM
DLM

PGND

CMP
CMN

OAIN+

OAIN-

CCI

BSTS

DHS

LXS

DLS
CSP
CSN

GNDS

1 2

30
36

V+

26
28

12

PC120

PR123

1 2

2.2_0402_5%

0.01U_0402_50V4Z

27
29
31
37
38
17
16

FB

14
35
33
34
32
40

1 2

PC125 470P_0402_50V8J

DHS
LXS
DLSFB

FB

15

39
13

D D

PR137

@100K_0402_5%

PR121 0_0402_5%

PR122 0_0402_5%
PR124 0_0402_5%
PR126 0_0402_5%
PR128 0_0402_5%
PR129 0_0402_5%

PR131 0_0402_5%

1 2

PR264

@0_0402_5%

VCC

1 2

REF

PR265

1 2

@0_0402_5%

1 2

PR266

0_0402_5%

PR136

C C

PWR_GD<31,35,40>

0_0402_5%

1 2

CPU_VID0<5>
CPU_VID1<5>
CPU_VID2<5>
CPU_VID3<5>
CPU_VID4<5>
CPU_VID5<5>

VGATE<7,14,19>

1 2

1 2

71.5K_0402_1%

1 2

PR142

PR140 200K_0402_1%

PC126 0.22U_0603_16V7K

12

PR120 10K_0402_5%

12
12
12
12
12
12

VCC

PR138 30.1K_0402_1%

PC124

1 2

270P_0402_50V7K

1 2

1 2

PR143 100K_0402_1%

PR159

0_0402_5%

1 2

H_STP_CPU#<14,19>

PR158

1 2

+3VS

B B

100K_0402_5%

DPRSLPVR<19>

13

D

PQ24

2

G

S

RHU002N06_SOT323

PR145

0_0402_5%

H_PSI#<5>

A A

1 2

10.7K_0402_1%

0_0402_5%

1 2

+3VS

PR154

12

12

PC128

PR148

PR152

100K_0402_1%

2

B

100P_0402_50V8J

C

E

13

D

PQ25

2

G

S

RHU002N06_SOT323

PR150

10K_0402_1%

1 2

2

1

PQ29

3

HMBT2222A_SOT23

G

CPU_B+

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

S1S3G

S

4

2

FDS7764S_SO8

PR139 820_0402_5%

1 2

+5VS

1

5

D8D7D6D

S1S3G

S

4

2

5

D8D7D6D

PQ27

S1S3G

S

4

2

FDS7764S_SO8

PR155

1 2

820_0402_5%

12

PQ22

IRF7413Z_SO8

12

PC130

12

PC113

PC112

4.7U_1206_25V6K

4.7U_1206_25V6K

CPU_B+

12

PC131

4.7U_1206_25V6K

2200P_0402_50V7K

12

12

PC114

PC115

.56UH_MPC1040LR56_ 23A_20%

0.01U_0402_50V4Z

PL13

1 2

12

PC123

1 2

PR132 820_0402_5%

0.47U_0603_16V7K

12

12

PC133

PC132

4.7U_1206_25V6K

0.01U_0402_50V4Z

.56UH_MPC1040LR56_ 23A_20%

1 2

PR153
820_0402_5%

1 2

0.47U_0603_16V7K

PL12

FBM-L18-453215-900LMA90T_1812

1 2

2200P_0402_50V7K

PR127

1 2

0.001_2512_5%

12

<BOM Structure>

PR133 499_0402_1%

PR141

1 2

3K_0402_1%

PL14

1 2

PC135

1

+

PC116

2

@100U_25V_M

12

PR134 499_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Title

+CPU_CORE

Size Document Number Rev

Custom

Date: Sheet of

43 47Thursday, September 09, 2004

1

0.5

5

4

3

2

1

D D

+3VL

12

PR327
100K_0402_5%

Travel<38>

C C

PQ81
RHU002N06_SOT323

13

D

2

G

S

12

PC171

0.022U_0402_16V7K

+3VL

12

PR326
470K_0402_1%

PQ80
RHU002N06_SOT323

13

D

2

G

S

12

PD44

1N4148_SOD80

PC170

0.022U_0402_16V7K

12

12

PR325
470K_0402_1%

12

PR324
47K_0402_1%

LM393M_SO8

VS+3VL

12

PC102

8

PU6A

P

+

1

O

-

G

4

0.01U_0402_50V4Z

3

VL

2

12

PR323
604K_0402_1%

12

12

PC169

PR322
1M_0402_1%

BATT_B <37,38>

100P_0402_50V8K

7

LM393M_SO8

0.1U_0603_16V7K

VL

PR185
1M_0402_1%

8

PU6B

O

4

PR190
10K_0402_5%

12

5

P

+

6

-

G

12

PC155

RHU002N06_SOT323

12

13

D

PQ38

1000P_0402_50V7K

S

PR187

12

267K_0402_1%

2

G

13

B+

12

PR186
301K_0402_1%

12

PR188

PR189

1 2

47K_0402_5%

12

1M_0402_1%

+5VALW

2

PQ39
DTC115EUA_SC70

PC153

1500P_0402_50V7K

ACIN <38,39>

PR184
100K_0402_5%

VL

1 2

B B

ACON<38>

MAINPWON<18,39,41>

A A

PD35

12

RB751V_SOD323

PD34

12

RB751V_SOD323

12

PC154

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

BATT OVP

Size Document Number Rev

A3

Date: Sheet

44 47Thursday, September 09, 2004

1

of

0.5

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Item Issue DescriptionDate

D D

1 DB2

Title

12VALWP remove 12V

Owner

HP

delete PQ11,PC54,PR55,PC42,PR52,PD16,PC41,PR5139 03/3/2004

(DB2)

2

41 +1.2VLANP

44 BATT_OVP

3

03/3/2004
(DB2)

03/3/2004
(DB2)

Compal

Compal

1.2VLANP rise plus voltage

For BATT_OVP issue

change the Vref form 2.5VREF to 2VREF,
and change PR104 form 107k_0603 to 100k_0402,
PR105 form 100k_0402 to 150k_0402

add PC157,PC158
change PR241 from 20k_0402 to 499k_0402,
PR243 from 40.2k_0603 to 402k_0402 ,
PR244 from 453k_00603 to 4499k_0402,
PR251 from 20k_0402 to 499k_0402.

41

4

C C

38

6

38 CHARGER

+1.2VLANP

CHARGER

7 38 CHARGER

8 38 CHARGER

9 42 1.5VALW/2.5VALW 04/20/2004 For +1.5VS/+2.5VS peak current issue

03/3/2004
(DB2)

03/3/2004
(DB2)

03/3/2004
(DB2)

03/19/2004
(DB2)
04/20/2004

Compal

Compal5

HP

For ME issue

For Charger issue Change PC27 from 0.1u_0402 to 1u_0603

For SYSTEM OCP function issue

HP For support that Main Battery is 4 cell pack (4S).

HP

To drop the 4 cell battery design.

Compal

Change PC97,PC93 from 22u_1210 to 22u_1206

Delete PR263,PR274 .
add PU17,PR280,PR281,PR282,PR283,PC159.

add PQ60,PQ61,PQ62,PR284,PR285,PR286,PR287

delete PQ60,PQ62,PR284,PR285,PR287

Change PL16 from 5uF to 3.3uF PLC0745-3R3A
Change PR177 from 100k to 301k
Change PR178 from 100K to 0 ohm

10 39 3.3VALW/5VALW 04/28/2004 remove 12V Change PU7 from MAX1902 to MAX1999

HP

delete PD19,PD20,PR58,PR61,PR63,PR64,PR66,PR59.
add PR294,PR295,PR296,PR287,PR288.

B B

11 38 CHARGER 05/13/2004 Compal add B+ soft start resister. Add PR294,PR295,PR296

Solution Description Rev.Page#

DB2

DB2

DB2

DB2

DB2

DB2

SI

SI

SI

SI

Request

12 38 CHARGER 07/5/2004 HP Add PU18,PQ62,PQ65,PD41,PR299,

PR300,PR301,PR302,PR304,PR305,PC166

13
14

38
39

CHARGER 07/5/2004 HP Add HP common logic solution

3.3VALW/5VALW 07/5/2004 HP For S5 POWER consumption issue Add PQ70,PQ71,PR314

Add PU19,PQ68,PQ69,PR306

15 38 CHARGER 09/1/2004 HP remove AC OCP delete PR249

16 38 CHARGER

A A

5

09/1/2004

Compal To improve S5 POWER consumption Add PQ73,PQ74,PQ75,PR316,PR317,PR318,PR319,PC167

Title

Size Document Number Rev

4

3

2

Date: Sheet

Compal Electronics, Inc.
Changed-List History-1

LA-2211

1

45 47Thursday, September 09, 2004

SI1-BFor MAX1538 5ms issue

SI1-B
SI1-B

SI2

SI2

0.5

of

5

4

Version Change List ( P. I. R. List ) for EE Circuit

3

2

1

Item Issue DescriptionDate

Page#

D D

C C

26

1

2

16

3

16

4

27

5

32

23

6

7

4 ADM1031

8 23 ATTN_BTTN#

Title

AGND

SiI1362

SiI1362

Microphone
circuit

Trackpoint CONN

V_1P2_LAN V_1P2_LAN ripple over spec

CH7307169

03/22/2004
(DB2)

03/22/2004
(DB2)

03/23/2004
(DB2)

03/23/2004
(DB2)

03/23/2004
(DB2)

04/01/2004
(DB2)

04/02/2004
(DB2)
04/08/2004
(DB2)

04/08/2004
(DB2)

Owner

HP Link AGND and GND with capacitor

HP Follow SiI1362 demo circuit

HP

HP To improve frequncy response

Compal Change trackpoint connector from pitch1.0mm to 0.5mm

Compal

Compal Can't read DDRII temprature link Q43 pin1 from GND to Q43 pin2 SI1(0.4)

HP Per Broadcom, this signal should be pulled up to +3VS. Delete R72 layout pad and change R73.1 from GND to +3VS. SI1(0.4)

CHrontle Recommendation from Chrontle.

Follow SiI1362 data sheet recommend

changeR460,R461,R462,R463 from 0_0402_5% to
C563,C564,C565,C566 0.1U_0402_16V4Z

changeR117 from 100_0402_5% to 1k_0402_5%
changeR105 from 300_0402_5% to 1k_0402_5%

Add R493,R494,R495,R496 300_0402_1%
Add C567,C568,C569,C570 0.1U_0402_16V4Z

Add L57,L58,L59,L60,L61 HLC0603CSCCR10JT_0603
Add C571,C572,C573,C574,C575 68P_0402_50V8J

change JP14 from ACES_85203-0802 to
ACES_87153-0801L

change L8,L29,L30,L32,L33 from 0_0603_5% to
BLM11A601S_0603

1. Pin25 VSWING for CH7307 should be added 1.2K ohm to GND.

2. Pin 26, 27 should be GND as 10K ohm.

Solution Description

Request

Cut-In
Date

DB2(0.3)

DB2(0.3)

DB2(0.3)

DB2(0.3)

DB2(0.3)

DB2(0.3)

SI1(0.4)

3. Pin3 AS should be pull up as 1K ohm.

Add active high signal SER_SHD to GPIO47 on U8 pin 31

10 29,33 SER_SHD

B B

11 34 PWR on fail

12 29 MAX3243

13 9 White screen

04/08/2004
(DB2)

04/19/2004
(DB2)

04/28/2004
(DB2)

04/28/2004
(DB2)

HP

Compal System can't boot reliably. SI1(0.4)

Compal Delete COM port components. Delete U33,C558,C559,C561,C560,C562,R468,RP50. SI1(0.4)

Compal

that connects to pin 80 on docking connector JP30B. Add
Pull down to this signal. This is used to control
serial port transceiver in dock.

LCD has white screen when system power on or resume from
S3/S4.

1. Change Q15 from SI2301 to SI2306.

2. Change Q15.2 control signal from SLP_S3 to RUNON.

3. Change R139 from 100K_0402_5% to 330K_0402_5%.

1. Exchange U35.3 and U35.5

2. Add a 2.2K_0402_5% pull down resistor on U35.2

SI1(0.4)

SI1(0.4)

1. Delete R499 10K_0402_5%.

2. Add R502,R505,R507 0_0402_5%.

3. Delete R15 4.7K_0402_5%.

14,19

14

23,24

A A

LAN PWR down 04/29/2004

(DB2)

HP

Support LAN controller power down feature when LAN cable
do not installed.

4. Add U36,U37 SN74LVC1G17DBVR.

5. Add Q54 2N7002.

6. Add C576,C577 0.1U_0402_16V4Z.

7. Add D32 RB751V.

SI1(0.4)

8. Add R503 100K_0402_5%.

9. Add R504 120K_0402_5%.

10. Add R506 10K_0402_5%.

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

Changed-List EE History-1

LA-2211

1

46 48Thursday, September 09, 2004

0.6

of

5

4

Version Change List ( P. I. R. List ) for EE Circuit

3

2

1

Item Issue DescriptionDate

Page#

D D

15

21 TI Flash

16 19 LANLINK_STATUS# 04/30/2004

17 21,22

18 28

19 27

20 21,22

C C

21 21,22

Title

media IO

Change power rail05/12/2004

USB+PWR
switcher

Microphone
pre-amp

Change power
rail

Change power
rail

04/30/2004
(DB2)

(DB2)

(DB2)
05/21/2004

(DB2)
05/26/2004

(DB2)
05/27/2004

(DB2)

07/05/2004
(SI1)

Owner

HP Solve TI Flash media IO work around circuit.

HP Change this signal from pin M3 of U26B to pin C25 of

U26C.

HP PCMCIA interface don't support S3 or S5 wake up feature. Change all of components power rail to main power plane. SI1(0.4)

Compal Change USB power switcher from MIC2044 to TPS2330. SI1(0.4)

HP

HP

Per HP's requirement change microphone pre-amp from
MAX4492 to TLV2464A.

Going back and forth for waking up support for PCMCIA
interface.

HP PCMCIA interface don't support S3 or S5 wake up feature.

Add D33,D34 RB751V.

1. Add R508 10K_0402_5%.

2. Add Q55 2N7002.

Change all of components power rail to resume power
plane.

1. Reserved some component layout pads for +3V/+5V.

2. Add R530 and R537 for supportting PCMCIA power rail
with main power rail.

Solution Description

Request

Cut-In
Date

SI1(0.4)

SI1(0.4)

SI1(0.4)

SI1(0.4)

SI1-B(0.5)

1. Add isolation circuit. (R532,R533,D37,D38)

19,31 S5 power

22

32,35

consumption

07/05/2004
(SI1)

HP

To reduce power consumption on S5. The specification is
under 50 mW.

2. Change some component's power rail from +3VALW to +3VL.
(R223,R218[V_3P3_LAN],U7,RP44,RP43,R65,R28,R27,JP31

SI1-B(0.5)

RP1,R32,R31,R30,U5,R22,R24,R7)

23 28

24 31

USB+PWR
switcher

Wrong voltage
level on FWP#.

25 27 OTS#133751

B B

26 18

ICH_RTCRST# timing07/22/2004

27 14 R511

28 27 R429, C504

29 30

Power LED
active error.

07/20/2004
(SI1)

07/22/2004
(SI1)

07/22/2004
(SI1)

(SI1)
08/03/2004

(SI1)
08/03/2004

(SI1)
08/03/2004

(SI1)

Compal

Compal

Compal

To solve voltage droop issue when cradle plugged in USB
port.

To solve wrong voltage on FWP# when system is powered off.

When mute is off, the mute button LED remains on (very dim though).

Intel Intel changed component's value.

Compal For supporting CY28442 on SI2. Delete R511. SI2(0.6)

HP

Compal

Follow Lloyd Daniel's suggestion, change R429 to 16.2K
ohm and change C504 to 0.22uF.

Swap D41.1 with D41.4 for solving LED active error on SI1-B unit.

1. Change C582 from 1000pF to 0.1uF.

2. Add C581 0.1uF.

SI2(0.6)

3. Change C102 to 100uF Low ESR capacitor.

Delete R28. SI2(0.6)

Change R430 from 100K ohm to 10K ohm. SI2(0.6)

1. Change R230 from 180K ohm to 20K ohm.

2. Change C287 from 0.1uF to 1uF.

SI2(0.6)

change R429 to 16.2K ohm and change C504 to 0.22uF. SI2(0.6)

SI2(0.6)

1. Add FBM-L11-201209-221LMAT on L62 and delete R466.

16,2632Modify EMI

30

solution

08/03/2004
(SI1)

Compal

2. Add 0.1u (C586) / 68p (C587) capacitors at B+_LCD.

3. Add CHB2012U121 on L36.

SI2(0.6)

4. Remove CP1~CP7

31 30

A A

Delete sleep
button function

Add additional

32 30

R & LED for
CAP. function

5

08/10/2004
(SI1)

08/10/2004
(SI1)

HP Sleep LED is no longer required. Delete D40 & R261. SI2(0.6)

Compal For solving CAP LED bright issue. This requirement was

coming from ME team.

4

3

1. Add R541 150 ohm.

2. Add green LED 17-21SYGC/S530-E1/TR8.

Title

Size Document Number Rev

LA-2211

2

Date: Sheet

SI2(0.6)

Compal Electronics, Inc.

Changed-List EE History-2

1

47 48Thursday, September 09, 2004

of

0.6

5

4

Version Change List ( P. I. R. List ) for EE Circuit

3

2

1

Item Issue DescriptionDate

Page#

D D

33

30 Power Button Change powr button from 2-way to 1-way. From SS056-Pt213BBT-PA2 to SS607-212N-FEEG1T. SI2(0.6)Compal

Title

Owner

08/10/2004
(SI1)

Solution Description

Request

Cut-In
Date

1. Change R532 from 10K ohm to 1K ohm.

2. Delete D37.

3. Add a additional MOS Q71 (BSS138).

4. Connection Q71.2 with V_3P3_LAN.

5. Connection Q71.3 with D37.1.

SI2(0.6)

34 19 OTS#137561

08/19/2004
(SI1)

Compal

I found this issue was caused by ICH_PCIE_WAKE# signal
generated again. Because V_3P3_LAN disappeared before
+3VALW under battery mod. This is wrong.

6. Connection Q71.1 with D37.2.

35 15

RGB rise/fall
time.

36 18 RTC Accuracy

37 16 DVI CKT

C C

38 4 ADM1032

08/23/2004
(SI1)

08/27/2004
(SI1)

08/31/2004
(SI1)

09/02/2004
(SI1)

Compal RGB rise/fall time out of specification issue. Short L54,L55,L56. SI2(0.6)

Compal To improve RTC accuracy.

HP

Compal SI2(0.6)

Remove any components that associate with Silicon Image
controller for DVI.

Change thermal sensor to ADM1032 and reserve a thermal sensor CKT (MAX6646) on page 8.

1. Change Y4 to 32.768 KHz +-10 ppm.

2. Change C516 and C528 to 18pF.

SI2(0.6)

SI2(0.6)

B B

A A

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

Compal Electronics, Inc.

Changed-List EE History-3

LA-2211

1

48 48Thursday, September 09, 2004

0.6

of