5
D D
4
3
2
1
SULLIVAN
REV : X01
C C
B B
@ : Depop Component for All
DothanSchematic with Capture CIS and Functionfield
uFCPGADothan
A A
02-11-2004
REV: 0.2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
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DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
LA-2171
1 50, 12, 2004
1
0.2
5
4
3
2
1
Compal confidential
GUARDIAN
D D
EMC6N300
page 15
HA#(3..31)
CRT CONN.
& TV-OUT
VGA
page 19
Board
PCI-E 16X
VGA CONN.
C C
page 18
Dothan
uFCPGA CPU
System Bus
400 /533MHz
Alviso
GMCH-M
1257 FC-BGA
page 10,11,12,13,14
page 7,8,9
HD#(0..63)
Memory
BUS(DDRII)
1.8V 400 / 533MHz
SO-DIMM X2
BANK0, 1, 2, 3
page 16,17
Block Diagram
Clock Generator
CK410M
page 6
Fan Control
page 15
LED/B
page 37
DMI
MINI PCI
page 33
PCI BUS
IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)
3.3V 33MHz
LAN
BCM4401
CardBus Controller
B B
RICHO R5C841
page 31,32
page 29
Transformer
SDIO CONN.
page32
1394 CONN.
page31
Slot 0
page32
GPIO
& RJ45
page 30
LPC BUS
3.3V 33MHz
Macallan III
X BUS
LCM CONN.
page36
A A
Multi-media
SST39VF080
page 36
Touch Pad
page 36
Board
5
4
1.5V
100MHz
LPC toX-BUS
& Super I/O
page 34,35
ICH6
609 BGA
Int.KBD
3.3V 24.576MHz
3.3V or 5V SATA
ATA100
SATA
SATA to PATA Bridge
Marvell 88SA8040
CDROM
page 24
HDD
USBPORT 0
USBPORT 1
48MHz / 480Mb
page 36
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
USB2.0
page 28
3
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
NEW CARD
page 24
page 24
JUSB1 U
JUSB1 D
Blue Tooth
JUSB2 U
JUSB2 D
JUSB3 U
JUSB3 D
2
MDC
page 27
AC-LINK
AC97 CODEC
STAC9751
AMP &
Phone Jack
page 26
DC IN
page 41
BATT IN/+2.5V
page 42
1.5V/1.05V(+VCCP)
page 25
page 43page 20,21,22,23
5V/3.3V/15V
page 44
Subwoofer
page 27
1.8V / 0.9V
VCORE
page 45
page 46
CHARGER
page 47
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA-2171
2 50, 12, 2004
1
0.2
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5
D D
4
3
2
1
PM TABLE
C C
power
plane
State
S0
S1
S3
S5 S4/AC
B B
S5 S4/AC don't exist
A A
+3VALW
+5VALW
ON
ON
ON
ON
+3VSUS
+5VSUS
+1.8VSUS
+1.5VSUS
ON ON
ON
ON
OFF
OFFOFF
+5VRUN
+3VRUN
+0.9V_DDR_VTT
+2.5VRUN
+1.8VRUN
+1.5VRUN
+VCC_CORE
+VCCP
+15V
ON
OFF
OFF
OFF
PCI TABLE
PCI DEVICE
CARD BUS
MINI PCI
IDSEL
AD17
AD19
REQ#/GNT#
1
3
LAN AD16 4 C
PIRQ
D,C
D,B
USB TABLE
USB PORT#0DESTINATION
JUSB1 (Top)
1
2
3
4
5
6
7
JUSB1 (Bottom)
Blue Tooth
NEW CARD
JUSB2 (Top)
JUSB2 (Bottom)
JUSB3 (Top)
JUSB3 (Bottom)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
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DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
LA-2171
3 50, 12, 2004
1
0.2
5
D D
4
3
2
1
+5VALW
ADAPTER
PWR_SRC
+3VALW
BATTERY
C C
SUS_ON
+5VSUS
B B
+5VHDD +5VMOD +5VRUN VDDA
A A
RUN_ON
PL9
+15V +2.5VRUN
(Option)
AUDIO_AVDD_ON
+3VRUN
L10
SUS_ON
+3VSRC
RUN_ON
V3P3LAN
SUSPWROK_5V
+3VSUS
+VCC_CORE
RUN_ON_D
RUNPWROK
+1.5VSUS
RUN_ON SUSPWROK_1.5V
RUNPWROK
+VCCP
+1.5VRUN
SUSPWROK_5V
+1.8VSUSP +0.9V_DDR_VTT
PJP11,PJP12
+1.8VSUS
RUN_ON
SUSPWROK_5V
+1.8VRUN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Power Rail
LA-2171
4 50, 12, 2004
1
0.2
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4
3
2
1
ICH_SMBCLK
D D
ICH6
ICH_SMBDATA
+3VSUS
7002
+3VRUN
7002
CK_SCLK
CK_SDATA
CLK GEN.
DIMM1DIMM0
CLK_SMB
DAT_SMB
C C
+3VALW
GUARDIAN
24C04
Device Address
SIO
Macallan III
B B
SMBCLK_VGA
SMBDAT_VGA +5VALW VGA
ICH6-SMBus
DIM0
DIM1
CLK GEN.
GUARDIAN
24C04
A0h
A2h
D2h
5Eh
A2h
PBAT_SMBCLK
PBAT_SMBDAT +5VALW BATTERY
EC-SMBus
VGA
Battery
Charger
58h
16h
12h
CHARGER
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-2171
5 50, 12, 2004
1
0.2
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+3VRUN
ICH_SMBDATA<22>
D D
ICH_SMBCLK<22>
ICH_SMBDATA
+3VRUN
ICH_SMBCLK
D
1 3
1 3
D
D
1
3
G
S
2
2N7002
12
12
R117
R118
Q9
100K_0402_5%~D
100K_0402_5%~D
S
2N7002_SOT23~D
G
2
2
G
Q10
2N7002_SOT23~D
S
CK_VDD_A CK_VDD_REF
CK_SDATA
CK_SCLK
1
2
C401
4.7U_0805_6.3V6K~D
0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz
FSC FSB FSA CPU
CLKSEL0 CLKSEL1 CLKSEL2
C C
*
00
0
1
1 1
0
0
1
11
1
0
0
1
0
0
0
0
0
1
1
1
Table :ICS 954201 / Cypress CY28411
+VCCP
B B
CLKSEL0
CPU_BSEL0<8>
A A
CPU_BSEL1<8>
1 2
R395
0_0402_5%~D@
CLKSEL1
1 2
R396
0_0402_5%~D@
5
1 2
1 2
+VCCP
1 2
1 2
R390
1 2
R391
1K_0402_5%~D
R394
0_0402_5%~D
R389
1K_0402_5%~D
@
1 2
R392
1K_0402_5%~D
R393
0_0402_5%~D
MHz
266
133
200
166
333
100
400
1K_0402_5%~D@
SRC
PCI
MHz
MHz
100 33.30
33.3
100
33.3
100
33.3
100
33.3
100
33.3
100
33.3
100
RESERVED
Dothan-A 400MHz, Install R390, Nopop. R394, R395
Dothan-A 533MHz, Install R394, Nopop. R390, R395
MCH_CLKSEL0 <10>
MCH_CLKSEL1 <10>
4
CK_SDATA <16,17>
CK_SCLK <16,17>
CK_VDD_48
1
2
C57
0.047U_0402_10V7K~D
CK_48M_ICH<22>
CK_33M_CBPCI<31>
CK_33M_SIOPCI<34>
CK_33M_MINIPCI<33>
CK_33M_LANPCI<29>
CK_33M_ICHPCI<20>
+3VRUN
1
1
2
2
C405
R86
10K_0402_5%~D
1 2
CLKSEL2
R94
10K_0402_5%~D
@
1 2
C69
4.7U_0805_6.3V6K~D
C83
33P_0402_50V8J~D@
12
C77
33P_0402_50V8J~D@
12
CLKSEL1
CLKSEL0 CK_ITP
CK_33M_CBPCI
CK_33M_SIOPCI
CK_33M_MINIPCI
CK_33M_LANPCI
CK_33M_ICHPCI
+3VRUN
1 2
L20
BLM21PG600SN1D_0805~D
1
C100
2
0.1U_0402_16V4Z~D
1 2
L21
BLM21PG600SN1D_0805~D
1
2
C72
0.047U_0402_10V7K~D
Placecrystal within
500milsofCK410
X2
14.31818MHz_20P_1BX14318CC1A~D12R113
R84 33_0402_5%~D
+3VRUN
0.047U_0402_10V7K~D
CK_XTAL_IN
CK_XTAL_OUT
12
12
R93 33_0402_5%~D
12
R95 33_0402_5%~D
12
R106 33_0402_5%~D
12
R123 33_0402_5%~D
12
R83 33_0402_5%~D
R85
10K_0402_5%~D
1 2
CK_VDD_MAIN2
1 2
R385 475_0603_1%~D
1 2
R119
1_0402_5%~D
1 2
2.2_0402_5%~D
PCICLKF0
3
CK_VDD_MAIN
CK_VDD_REF
CK_VDD_48
CLKSEL2CK_48M_ICH
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1
CK_SCLK
CK_SDATA
CLKIREF
2
C42
10U_0805_10V4M~D
1
2
C94
10U_0805_10V4M~D
1
U7
21
VDD_SRC0
28
VDD_SRC1
34
VDD_SRC2
1
VDD_PCI0
7
VDD_PCI1
42
VDD_CPU
48
VDD_REF
11
VDD_48
50
XTAL_IN
49
XTAL_OUT
12
FSA/USB_48
16
FSB/TEST_MODE
53
FSC/TEST_SEL
5
PCI5
4
PCI4
3
PCI3
56
PCI2
9
PCIF1
8
PCIF0/ITP_EN
46
SCLOCK
47
SDATA
39
IREF
13
VSS_48
29
VSS_SRC
2
VSS_PCI0
45
VSS_CPU
51
VSS_REF
6
VSS_PCI1
CY28411ZCT_TSSOP56~D
1
C49
0.047U_0402_10V7K~D
2
1
C78
0.047U_0402_10V7K~D
2
R376
2.2_0402_5%~D
1 2
CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#
VTT_PWRGD#/PD
1
C62
0.047U_0402_10V7K~D
2
1
C89
0.047U_0402_10V7K~D
2
CK_VDD_A
37
VDD_A
38
VSS_A
55
PCI_STOP#
54
CPU_STOP#
41
CPU1
40
CPU1#
44
CPU0
43
CPU0#
36
35
33
SRC6
32
SRC6#
31
SRC5
30
SRC5#
26
SRC4
27
SRC4#
24
SRC3
25
SRC3#
22
SRC2
23
SRC2#
19
SRC1
20
SRC1#
17
SRC0
18
SRC0#
14
DOT96
15
DOT96#
10
52
REF
2
1
C44
0.047U_0402_10V7K~D
2
1
C53
0.047U_0402_10V7K~D
2
Place near each pin
W>40 mil
Place near CK410M
H_STP_PCI#
H_STP_CPU#
CK_CPU1
1 2
R71 33_0402_5%~D
CK_CPU1#
1 2
R66 33_0402_5%~D
CK_CPU0
1 2
R81 33_0402_5%~D
CK_CPU0#
1 2
R76 33_0402_5%~D
CK_CPU2
1 2
R59 33_0402_5%~D
CK_CPU2#
1 2
R54 33_0402_5%~D
SCR5 CLK_MCH_3GPLL
1 2
R47 33_0402_5%~D
SRC5#
1 2
R41 33_0402_5%~D
SRC4
1 2
R48 33_0402_5%~D
SRC4#
1 2
R42 33_0402_5%~D
SRC3 CLK_PCIE_TV
1 2
R551 33_0402_5%~D
SRC3#
1 2
R552 33_0402_5%~D
SRC1
1 2
R67 33_0402_5%~D
SRC1#
1 2
R63 33_0402_5%~D
SRC2
1 2
R55 33_0402_5%~D
SRC2# CLK_PCIE_ICH#
1 2
R50 33_0402_5%~D
CLK_ENABLE#
CLKREF
1 2
R116 12.1_0402_1%~D
1 2
R112 12.1_0402_1%~D
1 2
R122 12.1_0402_1%~D
H_STP_PCI# <22>
H_STP_CPU# <22,46>
CLK_MCH_BCLK
CLK_MCH_BCLK#
CK_BCLK
CK_BCLK#
CK_ITP#
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_TV#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CK_14M_ICH
CK_14M_SIO
CK_14M_CODEC
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CK_BCLK <7>
CK_BCLK# <7>
CK_ITP <7>
CK_ITP# <7>
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CLK_PCIE_TV <37>
CLK_PCIE_TV# <37>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>
CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_ENABLE# <46>
CK_14M_ICH <22>
CK_14M_SIO <34>
CK_14M_CODEC <25>
1
CLK_MCH_BCLK
CLK_MCH_BCLK#
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_TV
CLK_PCIE_TV#
R70
49.9_0402_1%~D
R65
49.9_0402_1%~D
R80
49.9_0402_1%~D
R75
49.9_0402_1%~D
R58
49.9_0402_1%~D
R53
49.9_0402_1%~D
R49
1 2
49.9_0402_1%~D
R43
1 2
49.9_0402_1%~D
R56
1 2
49.9_0402_1%~D
R51
1 2
49.9_0402_1%~D
R46
1 2
49.9_0402_1%~D
R40
1 2
49.9_0402_1%~D
R68
1 2
49.9_0402_1%~D
R64
1 2
49.9_0402_1%~D
R553
1 2
49.9_0402_1%~D
R554
1 2
49.9_0402_1%~D
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Clock Generator
LA-2171
6 50, 12, 2004
1
0.2
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1
H_A#[3..31]<10>
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
1 4
2 3
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CPU_CK_ITP
CPU_CK_ITP#
CK_BCLK
CK_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSLP#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
D D
H_REQ#[0..4]<10>
RN2
0_0404_4P2R_5%~D
CK_ITP_R#
1 4
CK_ITP_R
C C
B B
2 3
+VCCP
CK_ITP
CK_ITP#
R92
56_0402_5%~D
1 2
CK_ITP<6>
CK_ITP#<6>
H_ADSTB#0<10>
H_ADSTB#1<10>
0_0404_4P2R_5%~D
CK_BCLK<6>
CK_BCLK#<6>
H_DEFER#<10>
H_DRDY#<10>
H_LOCK#<10>
H_RESET#<10>
H_RS#[0..2]<10>
H_TRDY#<10>
ITP_DBRESET#<39>
H_PROCHOT#<35>
T2 PAD~D
T21 PAD~D
H_THERMDA<15>
H_THERMDC<15>
H_THERMTRIP#<15>
RN3
@
H_ADS#<10>
H_BNR#<10>
H_BPRI#<10>
H_BR0#<10>
H_HIT#<10>
H_HITM#<10>
H_DBSY#<10>
H_DPSLP#<21>
H_DPRSLP#<21>
H_DPWR#<10>
H_PWRGOOD<21>
H_CPUSLP#<10,21>
JCPUA
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
ADDR GROUP
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
U3
ADSTB0#
AE5
ADSTB1#
A16
ITP_CLK0
A15
ITP_CLK1
B15
BCLK0
B14
BCLK1
N2
ADS#
L1
BNR#
J3
BPRI#
N4
BR0#
L4
DEFER#
H2
DRDY#
K3
HIT#
K4
HITM#
A4
IERR#
J2
LOCK#
B11
RESET#
H1
RS0#
K1
RS1#
L2
RS2#
M3
TRDY#
C8
BPM0#
B8
BPM1#
A9
BPM2#
C9
BPM3#
A7
DBR#
M2
DBSY#
B7
DPSLP#
G1
DPRSTP#
C19
DPWR#
A10
PRDY#
B10
PREQ#
B17
PROCHOT#
E4
PWRGOOD
A6
SLP#
A13
TCK
C12
TDI
A12
TDO
C5
TEST1
F23
TEST2
C11
TMS
B13
TRST#
B18
THERMDA
A18
THERMDC
C17
THERMTRIP#
AMP_1473129-1_Dothan~D
Dothan
DATA GROUP
HOST CLK
CONTROL GROUP
MISC
THERMAL
DIODE
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>
H_A20M# <21>
H_FERR# <21>
H_IGNNE# <21>
H_INIT# <21>
H_INTR <21>
H_NMI <21>
H_STPCLK# <21>
H_SMI# <21>
H_D#0H_A#3
A19
H_D#[0..63] <10>
H_RESET#
ITP_TDO
H_DSTBN#[0..3] <10>
H_DSTBP#[0..3] <10>
+VCCP
+VCCP
R20
22.6_0603_1%~D
1 2
R31
22.6_0603_1%~D
1 2
R397
75_0402_5%~D
1 2
R405
200_0402_5%~D
1 2
+VCCP
ITP_DBRESET# ITP_TDO
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CK_ITP_R
CK_ITP_R#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
29
JITP
28
VTT1
GND6
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
MOLEX_52435-2891_28P~D@
30
Check ITP connector.
H_THERMTRIP#
H_PWRGOOD
Add pullupsfor PWRGOOD and THERMTRIP per INTEL
+3VSUS
R11
150_0402_5%~D
1 2
+VCCP
R36
54.9_0603_1%~D
1 2
R19
54.9_0603_1%~D
1 2
+VCCP
R61
39.2_0603_1%~D
1 2
R62
150_0402_5%~D
1 2
R45
680_0402_5%~D
1 2
R44
27.4_0603_1%~D
1 2
+VCCP
1
C20
0.1U_0402_10V7K~D
2
Place near JITP
ITP_DBRESET#
H_RESET#
ITP_TMS
ITP_TDI
Thisshallplace near CPU
ITP_TRST#
ITP_TCK
A A
5
TEST1
R99
1 2
1K_0402_5%~D@
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
Dothan Processor(1/2)
LA-2171
7 50, 12, 2004
1
0.2
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5
4
3
2
1
R208
+VCCA_PROC
OPEN
+1.8VRUN
D D
For test only ,Cmos output
CPU Voltage ID
10K_1206_8P4R_5%~D
H_VID0
R383 0_0402_5%~D
H_VID1
R382 0_0402_5%~D
H_VID2
R381 0_0402_5%~D
H_VID3
R380 0_0402_5%~D
H_VID4
R379 0_0402_5%~D
H_VID5
R378 0_0402_5%~D
C C
12
12
12
12
12
12
B_VID6
OPEN~D
2
2
1
1
OPEN OPEN OPEN OPEN OPEN OPEN
@
+VCCP
10K_0402_5%~D
10K_0402_5%~D
12
RN1
4 5
B_VID5
OPEN~D
2
2
1
1
@
12
R38
R37
1 8
2 7
3 6
B_VID4
OPEN~D
2
2
1
1
@
B_VID3
OPEN~D
2
2
1
1
@
+1.5VRUN
B_VID2
OPEN~D
2
2
1
1
@
PJP5
2 1
PAD-OPEN 2x2m~D@
PJP3
2 1
PAD-OPEN 2x2m~D
SHORT
B_VID1
OPEN~D
2
2
1
1
@
1
C117
C122
2
0.01U_0402_16V7K~D
VID0 <46>
VID1 <46>
VID2 <46>
VID3 <46>
VID4 <46>
VID5 <46>
H_PSI#<46>
10U_1206_6.3V6M~D
54.9_0603_1%~D@
54.9_0603_1%~D@
1
2
+VCC_CORE
Layout Note:
500 mil max length
+VCCP
B B
Layout close CPU
V_CPU_GTLREF
R_A
12
R201
1K_0603_1%~D
R_B
12
R203
2K_0603_1%~D
12
12
R417
R416
27.4_0603_1%~D
R426
54.9_0603_1%~D
12
12
27.4_0603_1%~D
R427
54.9_0603_1%~D
Resistor placed within
0.5" of CPU pin.Trace
shouldbe at least 25
milesaway from any
other togglingsignal.
V_CPU_GTLREF
CPU_BSEL0<6>
CPU_BSEL1<6>
1 2
1 2
R207
+VCCP
T42 PAD~D
T43 PAD~D
T44 PAD~D
T45 PAD~D
VCCSENSE
VSSSENSE
H_PSI#
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
CPU_BSEL0
CPU_BSEL1
COMP0
COMP1
COMP2
COMP3
JCPUB
AE7
VCCSENSE
AF6
VSSSENSE
F26
VCCA0
B1
VCCA1
N1
VCCA2
AC26
VCCA3
P23
VCCQ0
W4
VCCQ1
D10
VCCP
D12
VCCP
D14
VCCP
D16
VCCP
E11
VCCP
E13
VCCP
E15
VCCP
F10
VCCP
F12
VCCP
F14
VCCP
F16
VCCP
K6
VCCP
L5
VCCP
L21
VCCP
M6
VCCP
M22
VCCP
N5
VCCP
N21
VCCP
P6
VCCP
P22
VCCP
R5
VCCP
R21
VCCP
T6
VCCP
T22
VCCP
U21
VCCP
D6
VCC
D8
VCC
D18
VCC
D20
VCC
D22
VCC
E5
VCC
E7
VCC
E9
VCC
E17
VCC
E19
VCC
E21
VCC
F6
VCC
F8
VCC
F18
VCC
E1
PSI#
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AD26
GTLREF
C16
BSEL0
C14
BSEL1
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
B2
RSVD
C3
RSVD
E26
RSVD
AF7
RSVD
AC1
RSVD
AMP_1473129-1_Dothan~D
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
E25
VSS
F1
VSS
F4
VSS
F5
VSS
F7
VSS
F9
VSS
F11
VSS
F13
VSS
F15
VSS
F17
VSS
F19
VSS
F21
VSS
F24
VSS
G2
VSS
G6
VSS
G22
VSS
G23
VSS
G26
VSS
H3
VSS
H5
VSS
H21
VSS
H25
VSS
J1
VSS
J4
VSS
J6
VSS
J22
VSS
J24
VSS
K2
VSS
K5
VSS
K21
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L22
VSS
L25
VSS
M1
VSS
+VCC_CORE
JCPUC
F20
VCC
F22
VCC
G5
VCC
G21
VCC
H6
VCC
H22
VCC
J5
VCC
J21
VCC
K22
VCC
U5
VCC
V6
VCC
V22
VCC
W5
VCC
W21
VCC
Y6
VCC
Y22
VCC
AA5
VCC
AA7
VCC
AA9
VCC
AA11
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AB6
VCC
AB8
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AC9
VCC
AC11
VCC
AC13
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AD8
VCC
AD10
VCC
AD12
VCC
AD14
VCC
AD16
VCC
AD18
VCC
AE9
VCC
AE11
VCC
AE13
VCC
AE15
VCC
AE17
VCC
AE19
VCC
AF8
VCC
AF10
VCC
AF12
VCC
AF14
VCC
AF16
VCC
AF18
VCC
M4
VSS
M5
VSS
M21
VSS
M24
VSS
N3
VSS
N6
VSS
N22
VSS
N23
VSS
N26
VSS
P2
VSS
P5
VSS
P21
VSS
P24
VSS
R1
VSS
R4
VSS
R6
VSS
R22
VSS
R25
VSS
T3
VSS
T5
VSS
T21
VSS
T23
VSS
AMP_1473129-1_Dothan~D
Dothan
POWER, GROUND
T26
VSS
U2
VSS
U6
VSS
U22
VSS
U24
VSS
V1
VSS
V4
VSS
V5
VSS
V21
VSS
V25
VSS
W3
VSS
W6
VSS
W22
VSS
W23
VSS
W26
VSS
Y2
VSS
Y5
VSS
Y21
VSS
Y24
VSS
AA1
VSS
AA4
VSS
AA6
VSS
AA8
VSS
AA10
VSS
AA12
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA20
VSS
AA22
VSS
AA25
VSS
AB3
VSS
AB5
VSS
AB7
VSS
AB9
VSS
AB11
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB26
VSS
AC2
VSS
AC5
VSS
AC8
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC21
VSS
AC24
VSS
AD1
VSS
AD4
VSS
AD7
VSS
AD9
VSS
AD11
VSS
AD13
VSS
AD15
VSS
AD17
VSS
AD19
VSS
AD22
VSS
AD25
VSS
AE3
VSS
AE6
VSS
AE8
VSS
AE10
VSS
AE12
VSS
AE14
VSS
AE16
VSS
AE18
VSS
AE20
VSS
AE23
VSS
AE26
VSS
AF2
VSS
AF5
VSS
AF9
VSS
AF11
VSS
AF13
VSS
AF15
VSS
AF17
VSS
AF19
VSS
AF21
VSS
AF24
VSS
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Dothan Processor(2/2)
LA-2171
8 50, 12, 2004
1
0.2
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5
4
3
2
1
+VCC_CORE
1
C213
10U_1206_6.3V6M~D
D D
C C
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C463
10U_1206_6.3V6M~D
C165
10U_1206_6.3V6M~D
C214
10U_1206_6.3V6M~D
1
C138
10U_1206_6.3V6M~D
2
1
C464
10U_1206_6.3V6M~D
2
1
C127
10U_1206_6.3V6M~D
2
1
C465
10U_1206_6.3V6M~D
2
1
C128
10U_1206_6.3V6M~D
2
1
C208
10U_1206_6.3V6M~D
2
1
C166
10U_1206_6.3V6M~D
2
1
C209
10U_1206_6.3V6M~D
2
1
C139
10U_1206_6.3V6M~D
2
1
C163
10U_1206_6.3V6M~D
2
1
C215
10U_1206_6.3V6M~D
2
1
C466
10U_1206_6.3V6M~D
2
1
C212
10U_1206_6.3V6M~D
2
1
C168
10U_1206_6.3V6M~D
2
1
C211
10U_1206_6.3V6M~D
2
1
C210
10U_1206_6.3V6M~D
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C167
10U_1206_6.3V6M~D
C443
10U_1206_6.3V6M~D
C144
10U_1206_6.3V6M~D
1
2
1
2
1
2
10uF 1206 X5R -> 85 degree
C526
10U_1206_6.3V6M~D
C532
10U_1206_6.3V6M~D
C441
10U_1206_6.3V6M~D
1
C528
10U_1206_6.3V6M~D
2
1
C527
10U_1206_6.3V6M~D
2
1
C531
10U_1206_6.3V6M~D
2
X7R
High Frequence Decoupling
1
C530
10U_1206_6.3V6M~D
2
1
C440
10U_1206_6.3V6M~D
2
1
C525
10U_1206_6.3V6M~D
2
1
C529
10U_1206_6.3V6M~D
2
1
C207
10U_1206_6.3V6M~D
2
1
C444
10U_1206_6.3V6M~D
2
Near VCORE regulator.
+VCC_CORE
220U_D2_2VM~D
1
C415
B B
+
2
220U_D2_2VM~D
1
C416
+
2
NOTE:Place close to CPU south side
@
220U_D2_2VM~D@
220U_D2_2VM~D
1
1
C408
C407
+
+
2
2
220U_D2_2VM~D
1
1
C665
C85
+
+
2
2
220U_D2_2VM~D
ESR <= 3m ohm
Capacitor > 880 uF
+VCCP
1
+
C160
150U _D2_6.3VM~D
2
A A
1
C446
0.1U_0402_10V7K~D
2
1
C447
0.1U_0402_10V7K~D
2
1
C448
0.1U_0402_10V7K~D
2
1
C457
0.1U_0402_10V7K~D
2
1
C452
0.1U_0402_10V7K~D
2
1
C437
0.1U_0402_10V7K~D
2
1
C436
0.1U_0402_10V7K~D
2
1
C432
0.1U_0402_10V7K~D
2
1
C435
0.1U_0402_10V7K~D
2
1
C445
0.1U_0402_10V7K~D
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Dothan Bypass
LA-2171
9 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
4
3
2
1
DMI_TXN0
DMI_TXN0<22>
DMI_TXN1
DMI_TXN1<22>
D D
C C
LayoutGuide will show
these signals routed
differentially.
B B
A A
H_A#[3..31]<7>
T1 PAD~D
H_REQ#[0..4]<7>
H_ADSTB#0<7>
H_ADSTB#1<7>
CLK_MCH_BCLK#<6>
CLK_MCH_BCLK<6>
H_DSTBN#[0..3]<7>
H_DSTBP#[0..3]<7>
H_DINV#0<7>
H_DINV#1<7>
H_DINV#2<7>
H_DINV#3<7>
H_RESET#<7>
H_ADS#<7>
H_TRDY#<7>
H_DPWR#<7>
H_DRDY#<7>
H_DEFER#<7>
T3 PAD~D
H_HITM#<7>
H_HIT#<7>
H_LOCK#<7>
H_BR0#<7>
H_BNR#<7>
H_BPRI#<7>
H_DBSY#<7>
H_RS#[0..2]<7>
H_CPUSLP#<7,21>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_RESET#
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_R_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP# H_R_CPUSLP#
Note:
"Do not install R97 for Dothan-A,
Install R97 for Dothan-B"
U15A
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
A11
A7
D7
B8
C7
A8
B9
E13
AB1
AB2
G4
K1
R3
V3
G5
K2
R2
W4
H8
K3
T7
U5
H10
F8
B5
G6
F7
E6
F6
D6
D4
B3
E7
A5
D5
C6
G8
A4
C5
B4
ALVISO_BGA1257~D
R97
0_0402_5%~D@
1 2
HA3#
Alviso
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
HCLKN
HCLKIN
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HSLPCPU#
HRS0#
HRS1#
HRS2#
HOST
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
H_D#0
E4
H_D#1
E1
H_D#2
F4
H_D#3
H7
H_D#4
E2
H_D#5
F1
H_D#6
E3
H_D#7
D3
H_D#8
K7
H_D#9
F2
H_D#10
J7
H_D#11
J8
H_D#12
H6
H_D#13
F3
H_D#14
K8
H_D#15
H5
H_D#16
H1
H_D#17
H2
H_D#18
K5
H_D#19
K6
H_D#20
J4
H_D#21
G3
H_D#22
H3
H_D#23
J1
H_D#24
L5
H_D#25
K4
H_D#26
J5
H_D#27
P7
H_D#28
L7
H_D#29
J3
H_D#30
P5
H_D#31
L3
H_D#32
U7
H_D#33
V6
H_D#34
R6
H_D#35
R5
H_D#36
P3
H_D#37
T8
H_D#38
R7
H_D#39
R8
H_D#40
U8
H_D#41
R4
H_D#42
T4
H_D#43
T5
H_D#44
R1
H_D#45
T3
H_D#46
V8
H_D#47
U6
H_D#48
W6
H_D#49
U3
H_D#50
V5
H_D#51
W8
H_D#52
W7
H_D#53
U2
H_D#54
U1
H_D#55
Y5
H_D#56
Y2
H_D#57
V4
H_D#58
Y7
H_D#59
W1
H_D#60
W3
H_D#61
Y3
H_D#62
Y6
H_D#63
W2
H_VREF
J11
H_XRCOMP
C1
H_XSCOMP
C2
H_YRCOMP
T1
H_YSCOMP
L1
H_SWNG0
D1
H_SWNG1
P1
R180
12
24.9_0603_1%~D
H_D#[0..63] <7>
H_SWNG1
C146
H_SWNG0
C112
0.1U_0402_16V4Z~D
+VCCP
12
R121
54.9_0603_1%~D
12
R125
24.9_0603_1%~D
+VCCP
12
R157
221_0603_1%~D
12
1
R176
2
100_0603_1%~D
0.1U_0402_16V4Z~D
+VCCP
12
R131
221_0603_1%~D
12
1
R132
2
100_0603_1%~D
12
R156
54.9_0603_1%~D
C124
0.1U_0402_10V7K~D
1
2
Layout Guide
will show these
signalsrouted
differentially.
+1.8VSUS
+VCCP
12
R143
100_0603_1%~D
12
R142
200_0603_1%~D
M_CLK_DDR0<17>
M_CLK_DDR1<17>
M_CLK_DDR3<16>
M_CLK_DDR4<16>
M_CLK_DDR#0<17>
M_CLK_DDR#1<17>
M_CLK_DDR#3<16>
M_CLK_DDR#4<16>
DDR_CKE0_DIMMA<17>
DDR_CKE1_DIMMA<17>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>
DDR_CS0_DIMMA#<17>
DDR_CS1_DIMMA#<17>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>
R458 80.6_0603_1%~D
1 2
V_DDR_MCH_REF<16,17,45>
12
R457
80.6_0603_1%~D
Layout Note:
Rote as short
as possible
12
12
R455
R456
40.2_0603_1%~D
40.2_0603_1%~D
DMI_TXN2<22>
DMI_TXN3<22>
DMI_TXP0<22>
DMI_TXP1<22>
DMI_TXP2<22>
DMI_TXP3<22>
DMI_RXN0<22>
DMI_RXN1<22>
DMI_RXN2<22>
DMI_RXN3<22>
DMI_RXP0<22>
DMI_RXP1<22>
DMI_RXP2<22>
DMI_RXP3<22>
M_OCDOCMP0
M_OCDOCMP1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT0<17>
M_ODT1<17>
M_ODT2<16>
M_ODT3<16>
C490
0.1U_0402_16V4Z~D
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR3
M_CLK_DDR4
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#3
M_CLK_DDR#4
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
1
C484
2
0.1U_0402_16V4Z~D
U15B
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
1
2
SMYSLEWIN
AF10
SMYSLEWOUT
ALVISO_BGA1257~D
DMIDDR MUXING
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
CFG/RSVD
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
PM
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN
CLK
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC
NC9
NC10
NC11
PM_EXTTS#0
PM_EXTTS#1
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
D37
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CFG0
MCH_CLKSEL1
MCH_CLKSEL0
T19PAD~D
T20PAD~D
CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
THERMTRIP_MCH#
PM_EXTTS#0
PM_EXTTS#1
THERMTRIP_MCH#
PLTRST_R#
+1.5VRUN
R413
10K_0402_5%~D
R398
10K_0402_5%~D
CFG0 <12>
MCH_CLKSEL1 <6>
MCH_CLKSEL0 <6>
CFG5 <12>
CFG6 <12>
CFG7 <12>
CFG9 <12>
CFG12 <12>
CFG13 <12>
CFG16 <12>
CFG18 <12>
CFG19 <12>
R114
75_0402_5%~D
1 2
PM_BMBUSY# <22>
THERMTRIP_MCH# <15>
IMVP_PWRGD <22,39,46>
1 2
R200 100_0603_1%~D
+2.5VRUN
12
12
+VCCP
PLTRST_MCH# <20>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(1 of 5)
LA-2171
10 50, 12, 2004
1
0.2
5
D D
4
3
2
1
DDR_A_BS#0<17>
DDR_A_BS#1<17>
DDR_A_BS#2<17>
DDR_A_DM[0..7]<17>
DDR_A_DQS[0..7]<17>
This Symbol assame
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
C C
B B
DDR_A_DQS#[0..7]<17>
DDR_A_MA[0..13]<17>
DDR_A_CAS#<17>
DDR_A_RAS#<17>
DDR_A_WE#<17>
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5 DDR_A_D18
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
TP_MA_RCVENIN#
DDR_A_WE#
U15C
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
AK35
SA_DQS0#
AP34
SA_DQS1#
AN30
SA_DQS2#
AN23
SA_DQS3#
AN8
SA_DQS4#
AM5
SA_DQS5#
AH1
SA_DQS6#
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
AM18
SA_MA5
AL19
SA_MA6
AP20
SA_MA7
AM19
SA_MA8
AL20
SA_MA9
AM16
SA_MA10
AN20
SA_MA11
AM20
SA_MA12
AM15
SA_MA13
AN15
SA_CAS#
AP16
SA_RAS#
AF29
SA_RCVENIN#
AF28
SA_RCVENOUT#
AP15
SA_WE#
ALVISO_BGA1257~D
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
DDR MEMORY SYSTEM A
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
This Symbol assame
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
DDR_B_BS#0<16>
DDR_B_BS#1<16>
DDR_B_BS#2<16>
DDR_B_DM[0..7]<16>
DDR_B_DQS[0..7]<16>
DDR_B_DQS#[0..7]<16>
DDR_B_MA[0..13]<16>
DDR_B_CAS#<16>
T22 PAD~DT25 PAD~D
T23 PAD~DT24 PAD~D
DDR_B_RAS#<16>
DDR_B_WE#<16>
DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#TP_MA_RCVENOUT#
DDR_B_WE#
U15D
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SD_DM0
AK34
SD_DM1
AK27
SD_DM2
AK24
SD_DM3
AJ10
SD_DM4
AK5
SD_DM5
AE7
SD_DM6
AB7
SD_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
AF35
SB_DQS0#
AK33
SB_DQS1#
AK28
SB_DQS2#
AJ23
SB_DQS3#
AL10
SB_DQS4#
AH7
SB_DQS5#
AF7
SB_DQS6#
AB5
SB_DQS7#
AH17
SB_MA0
AK17
SB_MA1
AH18
SB_MA2
AJ18
SB_MA3
AK18
SB_MA4
AJ19
SB_MA5
AK19
SB_MA6
AH19
SB_MA7
AJ20
SB_MA8
AH20
SB_MA9
AJ16
SB_MA10
AG18
SB_MA11
AG20
SB_MA12
AG15
SB_MA13
AH14
SB_CAS#
AK14
SB_RAS#
AF15
SB_RCVENIN#
AF14
SB_RCVENOUT#
AH16
SB_WE#
ALVISO_BGA1257~D
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
DDR SYSTEM MEMORY B
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D0
AE31
SBDQ0
AE32
DDR_B_D[0..63] <16>DDR_A_D[0..63] <17>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(2 of 5)
LA-2171
11 50, 12, 2004
1
0.2
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1
U15G
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
D D
C C
B B
CLK_MCH_3GPLL#<6>
CLK_MCH_3GPLL<6>
+VCCP
AB29
GCLKN
AC29
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCCLK
E23
DDCDATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
E25
LBKLT_CTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
F26
LVDD_EN
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
B30
LACLKN
B29
LACLKP
C25
LBCLKN
C24
LBCLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
ALVISO_BGA1257~D
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
EXP_RXN1
MISC
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
TVVGALVDS
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
PCI - EXPRESS GRAPHICS
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
PEGCOMP
D36
D34
PEG_RXN0
E30
PEG_RXN1
F34
PEG_RXN2
G30
PEG_RXN3
H34
PEG_RXN4
J30
PEG_RXN5
K34
PEG_RXN6
L30
PEG_RXN7
M34
PEG_RXN8
N30
PEG_RXN9
P34
PEG_RXN10
R30
PEG_RXN11
T34
PEG_RXN12
U30
PEG_RXN13
V34
PEG_RXN14
W30
PEG_RXN15
Y34
PEG_RXP0
D30
PEG_RXP1
E34
PEG_RXP2
F30
PEG_RXP3
G34
PEG_RXP4
H30
PEG_RXP5
J34
PEG_RXP6
K30
PEG_RXP7
L34
PEG_RXP8
M30
PEG_RXP9
N34
PEG_RXP10
P30
PEG_RXP11
R34
PEG_RXP12
T30
PEG_RXP13
U34
PEG_RXP14
V30
PEG_RXP15
W34
PEG_TXN0
E32
PEG_TXN1
F36
PEG_TXN2
G32
PEG_TXN3
H36
PEG_TXN4
J32
PEG_TXN5
K36
PEG_TXN6
L32
PEG_TXN7
M36
PEG_TXN8
N32
PEG_TXN9
P36
PEG_TXN10
R32
PEG_TXN11
T36
PEG_TXN12
U32
PEG_TXN13
V36
PEG_TXN14
W32
PEG_TXN15
Y36
PEG_TXP0
D32
PEG_TXP1
E36
PEG_TXP2
F32
PEG_TXP3
G36
PEG_TXP4
H32
PEG_TXP5
J36
PEG_TXP6
K32
PEG_TXP7
L36
PEG_TXP8
M32
PEG_TXP9
N36
PEG_TXP10
P32
PEG_TXP11
R36
PEG_TXP12
T32
PEG_TXP13
U36
PEG_TXP14
V32
PEG_TXP15
W36
R129
24.9_0603_1%~D
1 2
PEG_RXN[0..15]
PEG_RXP[0..15]
PEG_TXN[0..15]
PEG_TXP[0..15]
+1.5VRUN_PCIE
PEG_RXN[0..15] <18>
PEG_RXP[0..15] <18>
This Symbol assame
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
PEG_TXN[0..15] <18>
PEG_TXP[0..15] <18>
CFG[2:0]
CFG5
CFG6
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
Refer tosheet 6 for FSB
frequencyselect
Low = DMIx 2
High =DMI x 4
Low = DDR-II
High =DDR-I
*
*
Low = DT/Transportable CPU
High =Mobile CPU
Low =Reverse Lane
High =Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All ZMode Enabled
11 = Normal Operation(Default)
*
Low = Disabled
High =Enabled
Low = 1.05V (Default)
High =1.5V
*
*
Low = 1.05V (Default)
High =1.2V
+VCCP
R415 10K_0402_5%~D
CFG0<10>
R408 2.2K_0402_5%~D@
CFG5<10>
R404 2.2K_0402_5%~D
CFG6<10>
R108 2.2K_0402_5%~D@
CFG7<10>
R401 2.2K_0402_5%~D@
CFG9<10>
R402 2.2K_0402_5%~D@
CFG12<10>
R411 2.2K_0402_5%~D@
CFG13<10>
R412 2.2K_0402_5%~D@
*
CFG16<10>
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CFG[17:3] have internal pull-up
*
+2.5VRUN
R406 1K_0402_5%~D@
CFG18<10>
CFG19<10>
*
1 2
1 2
R407 1K_0402_5%~D@
CFG[19:18] have internal pull-down
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(3 of 5)
LA-2171
12 50, 12, 2004
1
0.2
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1
U15F
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
POWER
VTT8
N11
VTT9
M11
1
2
C449
1
2
0.22U_0603_10V7K~D
VTT10
L11
VTT11
K11
VTT12
W10
VTT13
V10
VTT14
U10
VTT15
T10
VTT16
R10
VTT17
P10
VTT18
N10
VTT19
M10
VTT20
K10
VTT21
J10
VTT22
Y9
VTT23
W9
VTT24
U9
VTT25
R9
VTT26
P9
VTT27
N9
VTT28
M9
VTT29
L9
VTT30
J9
VTT31
N8
VTT32
M8
VTT33
N7
VTT34
M7
VTT35
N6
VTT36
M6
VTT37
A6
VTT38
N5
VTT39
M5
VTT40
N4
VTT41
M4
VTT42
N3
VTT43
M3
VTT44
N2
VTT45
M2
VTT46
B2
VTT47
V1
VTT48
N1
VTT49
M1
VTT50
G1
VTT51
C118
0.22U_0603_10V7K~D
ALVISO_BGA1257~D
D D
+VCCP
1
C453
C460
2
2.2U_0805_10V6K~D
4.7U_0805_6.3V6K~D
1
C422
C C
B B
2
0.47U_0603_16V7K~D
1
1
C423
2
2
0.47U_0603_16V7K~D
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
V1.8_DDR_CAP1
AM37
V1.8_DDR_CAP2
AH37
V1.8_DDR_CAP5
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
Note: Place near chip.
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
V1.8_DDR_CAP6
AP8
V1.8_DDR_CAP4
AM1
V1.8_DDR_CAP3
AE1
C639
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
Note : AllVCCSM pin
shorted internally.
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
C495
+1.8VSUS
10U_1206_6.3V6M~D
10U_1206_6.3V6M~D
C233
C232
1
2
C238
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C641
C640
2
1
2
1
2
1
2
C523
0.1U_0402_10V7K~D
C513
330U_D2E_2.5VM~D@
1
+
2
0.1U_0402_16V4Z~D
C642
1
C504
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5VRUN_HPLL
+1.5VRUN_MPLL
0.1U_0402_16V4Z~D
1
2
W=20 mils
+VCCP
1
C515
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C519
1
2
+1.5VRUN
+1.8VSUS
0.1U_0402_16V4Z~D
1
1
C644
C643
2
2
0.1U_0402_16V4Z~D
U15E
T29
VCC0
R29
VCC1
N29
VCC2
M29
VCC3
K29
VCC4
J29
VCC5
V28
VCC6
U28
VCC7
T28
VCC8
R28
VCC9
P28
VCC10
N28
VCC11
M28
VCC12
L28
VCC13
K28
VCC14
J28
VCC15
H28
VCC16
G28
VCC17
V27
VCC18
U27
VCC19
T27
VCC20
R27
VCC21
P27
VCC22
N27
VCC23
M27
VCC24
L27
VCC25
K27
VCC26
J27
VCC27
H27
VCC28
K26
VCC29
H26
VCC30
K25
VCC31
J25
VCC32
K24
VCC33
K23
VCC34
K22
VCC35
K21
VCC36
W20
VCC37
U20
VCC38
T20
VCC39
K20
VCC40
V19
VCC41
U19
VCC42
K19
VCC43
W18
VCC44
V18
VCC45
T18
VCC46
K18
VCC47
K17
VCC48
AC2
VCCD_HMPLL1
AC1
VCCD_HMPLL2
B23
VCCA_DPLLA
C35
VCCA_DPLLB
AA1
VCCA_HPLL
AA2
VCCA_MPLL
ALVISO_BGA1257~D
POWER
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCHV0
VCCHV1
VCCHV2
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
F17
E17
D18
C18
F18
E18
H18
G18
D19
H17
B26
B25
A25
A35
B22
B21
A21
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
H20
F19
E19
G19
+1.5VRUN
+2.5VRUN
+2.5VRUN
+2.5VRUN
C520
0.1U_0402_16V4Z~D
1
2
C237
100U_D2_6.3VM_R45~D
+VCCP
Close B26,B25,A25
+1.5VRUN
0.1U_0402_16V4Z~D
10U_1206_6.3V6M~D
C418
1
1
C638
2
2
+1.5VRUN_PCIE
1
+
2
1
+
C173
C510
2
220U_D2_4VM
Route VSSA3GBG gnd fromGMCH to
decoupling cap ground lead and
then connect to the gnd plane.
1
1
C126
2
2
10U_1206_6.3V6M~D
10U_1206_6.3V6M~D
+1.5VRUN
1
C186
2
0.1U_0402_16V4Z~D
1
C120
0.1U_0402_16V4Z~D
2
+1.5VRUN+1.5VRUN_DDRDLL
1
C231
2
0.1U_0402_16V4Z~D
L34
BLM18PG600SN1_0603
12
L32
BLM18PG600SN1_0603
R422
0.5_0805_1%~D
1 2
1
1
C462
C479
2
2
0.1U_0402_16V4Z~D
10U_1206_6.3V6M~D
BLM18PG600SN1_0603
3GRLL_R
BLM11A601S_0603~D
1
C119
0.1U_0402_16V4Z~D
2
12
+1.5VRUN+1.5VRUN_3GPLL
L78
12
1
C497
2
0.1U_0402_16V4Z~D
+2.5VRUN+2.5VRUN_3GBG
L24
12
+VCCP
1
+1.5VRUN_DPLLA +1.5VRUN_DPLLB
L15
BLM11A601S_0603~D
+1.5VRUN
A A
1 2
+1.5VRUN
0.1U_0402_16V4Z~D
C429
1
2
L19
BLM11A601S_0603~D
1 2
+1.5VRUN_HPLL
L29
BLM11A601S_0603~D
0.1U_0402_16V4Z~D
+1.5VRUN
C430
1
2
1 2
0.1U_0402_16V4Z~D
470U_D2_2.5VM~D
1
C485
C477
1
+
2
2
+1.5VRUN
BLM11A601S_0603~D
1 2
+1.5VRUN_MPLL
L30
1
1
+
C481
C461
2
2
0.1U_0402_16V4Z~D
470U_D2_2.5VM~D
C455
2
10U_1206_6.3V6M~D
1
C459
2
10U_1206_6.3V6M~D
W=20 mils
1
C451
C454
2
0.1U_0402_16V4Z~D
10U_1206_6.3V6M~D
1
1
C456
C450
2
2
0.1U_0402_16V4Z~D
+2.5VRUN
1
1
2
0.1U_0402_16V4Z~D
1
C79
C425
2
2
4.7U_0805_6.3V6K~D
10U_1206_6.3V6M~D
1
1
C90
2
4.7U_0805_6.3V6K~D
1
C427
2
0.01U_0402_16V7K~D
1
C426
C428
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(4 of 5)
LA-2171
13 50, 12, 2004
1
0.2
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5
4
3
2
1
+VCCP
D D
C C
B B
A A
U15H
L12
VTT_NCTF17
M12
VTT_NCTF16
N12
VTT_NCTF15
P12
VTT_NCTF14
R12
VTT_NCTF13
T12
VTT_NCTF12
U12
VTT_NCTF11
V12
VTT_NCTF10
W12
VTT_NCTF9
L13
VTT_NCTF8
M13
VTT_NCTF7
N13
VTT_NCTF6
P13
VTT_NCTF5
R13
VTT_NCTF4
T13
VTT_NCTF3
U13
VTT_NCTF2
V13
VTT_NCTF1
W13
VTT_NCTF0
Y12
VSS_NCTF68
AA12
VSS_NCTF67
Y13
VSS_NCTF66
AA13
VSS_NCTF65
L14
VSS_NCTF64
M14
VSS_NCTF63
N14
VSS_NCTF62
P14
VSS_NCTF61
R14
VSS_NCTF60
T14
VSS_NCTF59
U14
VSS_NCTF58
V14
VSS_NCTF57
W14
VSS_NCTF56
Y14
VSS_NCTF55
AA14
VSS_NCTF54
AB14
VSS_NCTF53
L15
VSS_NCTF52
M15
VSS_NCTF51
N15
VSS_NCTF50
P15
VSS_NCTF49
R15
VSS_NCTF48
T15
VSS_NCTF47
U15
VSS_NCTF46
V15
VSS_NCTF45
W15
VSS_NCTF44
Y15
VSS_NCTF43
AA15
VSS_NCTF42
AB15
VSS_NCTF41
L16
VSS_NCTF40
M16
VSS_NCTF39
N16
VSS_NCTF38
P16
VSS_NCTF37
R16
VSS_NCTF36
T16
VSS_NCTF35
U16
VSS_NCTF34
V16
VSS_NCTF33
W16
VSS_NCTF32
Y16
VSS_NCTF31
AA16
VSS_NCTF30
AB16
VSS_NCTF29
R17
VSS_NCTF28
Y17
VSS_NCTF27
AA17
VSS_NCTF26
AB17
VSS_NCTF25
AA18
VSS_NCTF24
AB18
VSS_NCTF23
AA19
VSS_NCTF22
AB19
VSS_NCTF21
AA20
VSS_NCTF20
AB20
VSS_NCTF19
R21
VSS_NCTF18
Y21
VSS_NCTF17
AA21
VSS_NCTF16
AB21
VSS_NCTF15
Y22
VSS_NCTF14
AA22
VSS_NCTF13
AB22
VSS_NCTF12
Y23
VSS_NCTF11
AA23
VSS_NCTF10
AB23
VSS_NCTF9
Y24
VSS_NCTF8
AA24
VSS_NCTF7
AB24
VSS_NCTF6
Y25
VSS_NCTF5
AA25
VSS_NCTF4
AB25
VSS_NCTF3
Y26
VSS_NCTF2
AA26
VSS_NCTF1
AB26
VSS_NCTF0
V25
VCC_NCTF10
W25
VCC_NCTF9
L26
VCC_NCTF8
M26
VCC_NCTF7
N26
VCC_NCTF6
P26
VCC_NCTF5
R26
VCC_NCTF4
T26
VCC_NCTF3
U26
VCC_NCTF2
V26
VCC_NCTF1
W26
VCC_NCTF0
ALVISO_BGA1257~D
5
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
NCTF
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+1.8VSUS
+VCCP
U15I
Y1
VSS271
D2
VSS270
G2
VSS269
J2
VSS268
L2
VSS260
P2
VSS259
T2
VSS258
V2
VSS257
AD2
VSS256
AE2
VSS255
AH2
VSS254
AL2
VSS253
AN2
VSS252
A3
VSS251
C3
VSS250
AA3
VSS249
AB3
VSS248
AC3
VSS247
AJ3
VSS246
C4
VSS245
H4
VSS244
L4
VSS243
P4
VSS242
U4
VSS241
Y4
VSS240
AF4
VSS239
AN4
VSS238
E5
VSS237
W5
VSS236
AL5
VSS235
AP5
VSS234
B6
VSS233
J6
VSS232
L6
VSS231
P6
VSS230
T6
VSS229
AA6
VSS228
AC6
VSS227
AE6
VSS226
AJ6
VSS225
G7
VSS224
V7
VSS223
AA7
VSS222
AG7
VSS221
AK7
VSS220
AN7
VSS219
C8
VSS218
E8
VSS217
L8
VSS216
P8
VSS215
Y8
VSS214
AL8
VSS213
A9
VSS212
H9
VSS211
K9
VSS210
T9
VSS209
V9
VSS208
AA9
VSS207
AC9
VSS206
AE9
VSS205
AH9
VSS204
AN9
VSS203
D10
VSS202
L10
VSS201
Y10
VSS200
AA10
VSS199
F11
VSS198
H11
VSS197
Y11
VSS196
ALVISO_BGA1257~D
VSS
VSSALVDS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
U15J
AL24
VSS267
AN24
VSS266
A26
VSS265
E26
VSS264
G26
VSS263
J26
VSS262
B27
VSS261
E27
VSS129
G27
VSS128
W27
VSS127
AA27
VSS126
AB27
VSS125
AF27
VSS124
AG27
VSS123
AJ27
VSS122
AL27
VSS121
AN27
VSS120
E28
VSS119
W28
VSS118
AA28
VSS117
AB28
VSS116
AC28
VSS115
A29
VSS114
D29
VSS113
E29
VSS112
F29
VSS111
G29
VSS110
H29
VSS109
L29
VSS108
P29
VSS107
U29
VSS106
V29
VSS105
W29
VSS104
AA29
VSS103
AD29
VSS102
AG29
VSS101
AJ29
VSS100
AM29
VSS99
C30
VSS98
Y30
VSS97
AA30
VSS96
AB30
VSS95
AC30
VSS94
AE30
VSS93
AP30
VSS92
D31
VSS91
E31
VSS90
F31
VSS89
G31
VSS88
H31
VSS87
J31
VSS86
K31
VSS85
L31
VSS84
M31
VSS83
N31
VSS82
P31
VSS81
R31
VSS80
T31
VSS79
U31
VSS78
V31
VSS77
W31
VSS76
AD31
VSS75
AG31
VSS74
AL31
VSS73
A32
VSS72
C32
VSS71
Y32
VSS70
AA32
VSS69
AB32
VSS68
ALVISO_BGA1257~D
VSS
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Alviso(5 of 5)
LA-2171
14 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
+15V
R104
100K_0402_5%~D
FAN1_PWM<35>
D D
FAN2_PWM<35>
C C
1 2
R111
100K_0402_5%~D
1 2
FAN1VREF
FAN1_VFB
1
C75
2
1U_0603_10V4Z~D
R483
1 2
150K_0402_5%~D
FAN2VREF
FAN2_VFB
1
C84
2
1U_0603_10V4Z~D
R96
1 2
150K_0402_5%~D
8
3
P
IN+
2
IN-
G
4
C583
2200P_0402_50V7K~D@
1 2
R481
100K_0402_5%~D
RB751V_SOD323~D
+15V
8
5
P
IN+
6
IN-
G
4
C74
2200P_0402_50V7K~D@
1 2
R82
100K_0402_5%~D
RB751V_SOD323~D
U4A
LM358M_SO8~D
O
12
U4B
LM358M_SO8~D
O
12
4
+5VRUN
6
2
1
D
Q47
G
FAN1_ON
1
7
D18
1
C51
2
FAN2_ON
D5
3
S
SI3456DV-T1_TSOP6~D
4 5
1
1
+
C257
C560
2
2
2 1
47U_D_16VM_R70~D
@
+5VRUN
6
2
1
0.1U_0603_25V7K~D
D
Q7
G
3
S
SI3456DV-T1_TSOP6~D
4 5
1
1
+
C64
C65
2
2
2 1
@
47U_D_16VM_R70~D
FAN1_VOUT
1000P_0402_50V7K~D
FAN2_5V
1000P_0402_50V7K~D
JFAN1
1
2
3
E&T_3801-03-1~D
FAN1
JFAN2
1
2
3
E&T_3801-03-1~D
FAN2
3
+3VRUN
12
R476
10K_0402_5%~D
1
C559
0.47U_0603_16V7K~D
2
+3VRUN
12
R57
10K_0402_5%~D
1
C54
0.47U_0603_16V7K~D
2
FAN1 Control andTachometer
FAN1_TACH <35>
FAN2 Control andTachometer
FAN2_TACH <35>
2
C
B
1
1
E 3
2
2222 SYMBOL(SOT23-NEW)
H_THERMDA<7>
B B
A A
H_THERMDC<7>
+3VSUS
+RTC_CELL
+3VSUS
C483
0.1U_0402_16V4Z~D
2200P_0402_50V7K~D
R428
49.9_0603_1%~D
1 2
C496
0.1U_0402_16V4Z~D
1
2
1
2
5
C508
0.1U_0402_16V4Z~D
12
R421
30.1K_0603_1%~D
12
R418
12.1K_0603_1%~D
1
C505
2
1
2
SUSPWROK<22,39>
ICH_PWRGD#<39>
POWER_SW#<35,37>
THERMATRIP_VGA#<18>
1 2
R430 8.2K_0402_5%~D
1
2
DAT_SMB<35,36>
CLK_SMB<35,36>
R453 1K_0402_5%~D
+3VSUS_R
R444 1K_0402_5%~D
R433 1K_0402_5%~D
THERMATRIP2#
THERMATRIP_VGA#
C478
2200P_0402_50V7K~D
1 2
1 2
1 2
1 2
U25
1
THDAT_SMB
2
THCLK_SMB
13
SMBADDRSEL
18
REM_DIODE2_P
17
REM_DIODE2_N
4
+3VSUS
11
VSUS_PWRGD
10
+RTC_PWR3V
5
+3V_PWROK
21
POWER_SW
6
THERMTRIP1
7
THERMTRIP2
8
THERMTRIP3
22
VSET
14
HW_LOCK
3
VSS
EMC6N300_SSOP24~D
R452
1K_0402_5%~D
4
ATF_INT
VCP
RESSERVED
REM_DIODE1_N
REM_DIODE1_P
THERMTRIP_SIO
THERM_STP
INTRUDER
+5VSUS
12
9
23
16
19
20
15
24
12
R424
2.21K_0603_1%~D
1
C489
2
2200P_0402_50V7K~D
+3VALW
12
ATF_INT# <34>
B
2
+5VSUS
12
E
3
Q40
C
MMBT3904_SOT23~D
1
R450
10K_0402_5%~D
5V_CAL_SIO# <34>
12
R475
10KB_0603_1%_TSM1A103F34D3R~D
13
D
Q46
2N7002_SOT23~D
REN_DIODE_NTHERMATRIP1#
REN_DIODE_P
R451
100K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
G
S
1
C503
2
2200P_0402_50V7K~D
THERMTRIP_SIO <35>
THERM_STP# <44>
INTRUDER# <21>
Trace width = 10mil
+VCCP
R120
2.2K_0402_5%~D
1 2
MMBT3904_SOT23~D
H_THERMTRIP#<7>
+VCCP
R388
2.2K_0402_5%~D
1 2
MMBT3904_SOT23~D
THERMTRIP_MCH#<10>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
LA-2171
2
Date: Sheet of
+3VSUS
12
R124
8.2K_0402_5%~D
THERMATRIP1#
1
C
E
+3VSUS
E
3
12
1
C
3
1
C95
0.1U_0402_16V4Z~D
2
R386
8.2K_0402_5%~D
THERMATRIP2#
1
C406
0.1U_0402_16V4Z~D
2
2
B
Q8
2
B
Q37
Compal Electronics, Inc.
Thermal sensor andFan
15 50, 12, 2004
1
0.2
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5
DDR_B_DQS#[0..7]<11>
DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>
DDR_B_MA[0..13]<11>
D D
C C
B B
A A
+1.8VSUS
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C580
DDR_B_MA1
DDR_B_MA3
56_0404_4P2R_5%~D
DDR_B_BS#0
DDR_B_MA10
56_0404_4P2R_5%~D
DDR_B_MA0
DDR_B_BS#1
56_0404_4P2R_5%~D
DDR_B_RAS#
DDR_CS2_DIMMB#
56_0404_4P2R_5%~D
DDR_B_CAS#
DDR_B_WE#
56_0404_4P2R_5%~D
DDR_CS3_DIMMB#
M_ODT3
56_0404_4P2R_5%~D
2.2U_0805_10V6K~D
1
2
C318
1
2
0.1U_0402_16V4Z~D
1
2
RN14
RN22
RN13
RN23
RN24
RN27
RN15
2.2U_0805_10V6K~D
C291
0.1U_0402_16V4Z~D
C317
1
2
0.1U_0402_16V4Z~D
1
2
C577
C582
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
2.2U_0805_10V6K~D
2.2U_0805_10V6K~D
1
2
C581
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
2 3
1 4
C310
C312
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C293
1
2
Layout Note:
Place one cap close to every2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C578
C298
+0.9V_DDR_VTT
RN12
RN11
RN25
RN26
RN10
RN9
5
2.2U_0805_10V6K~D
C292
1
1
2
2
0.1U_0402_16V4Z~D
C294
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C579
DDR_B_MA9
DDR_B_MA12
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
M_ODT2
DDR_B_MA13
DDR_B_BS#2
DDR_CKE2_DIMMB
C311
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C300
C297
4
Layout Note:
Place near JDIM1
@
M_CLK_DDR3
10P_0402_50V8J~D
1
C287
2
M_CLK_DDR#3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C301
C299
Layout Note:
Place these resistor
closely JDIM1,all
trace length<750 mil
Layout Note:
Place these resistor
closely JDIM1,all
trace length
Max=1.3"
4
3
@
M_CLK_DDR4
10P_0402_50V8J~D
1
C289
2
M_CLK_DDR#4
DDR_CKE2_DIMMB<10>
DDR_B_BS#2<11>
DDR_B_BS#0<11>
DDR_B_WE#<11>
DDR_B_CAS#<11>
0.1U_0402_16V4Z~D
1
1
2
2
C302
C296
DDR_CS3_DIMMB#<10>
M_ODT3<10>
CK_SDATA<6,17>
CK_SCLK<6,17>
+3VRUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.8VSUS +1.8VSUS
JDIM1
1
VREF
3
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
C313
VSS
5
DQ0
7
DQ1
9
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
FOX_AS0A426-M2S-TR~D
DIMMA
STANDARD
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CK_SDATA
CK_SCLK
0.1U_0402_16V4Z~D
C319
1
2
2.2U_0805_10V6K~D
1
2
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
BA1
CK1
SA1
NC
A11
A7
A6
A4
A2
A0
S0#
NC
2
V_DDR_MCH_REF
2
DDR_B_D4
4
DDR_B_D5
6
8
DDR_B_DM0
10
12
DDR_B_D6
14
DDR_B_D7
16
18
DDR_B_D12
20
DDR_B_D13
22
24
DDR_B_DM1
26
28
M_CLK_DDR3
30
M_CLK_DDR#3
32
34
DDR_B_D14
36
DDR_B_D15
38
40
42
DDR_B_D20
44
DDR_B_D21
46
48
50
DDR_B_DM2
52
54
DDR_B_D22
56
DDR_B_D23
58
60
DDR_B_D28
62
DDR_B_D29
64
66
DDR_B_DQS#3
68
DDR_B_DQS3
70
72
DDR_B_D30
74
DDR_B_D31
76
78
DDR_CKE3_DIMMB
80
82
84
86
88
DDR_B_MA11
90
DDR_B_MA7
92
DDR_B_MA6
94
96
DDR_B_MA4
98
DDR_B_MA2
100
DDR_B_MA0
102
104
DDR_B_BS#1
106
DDR_B_RAS#
108
DDR_CS2_DIMMB#
110
112
M_ODT2
114
DDR_B_MA13
116
118
120
122
DDR_B_D36
124
DDR_B_D37
126
128
DDR_B_DM4
130
132
DDR_B_D38
134
DDR_B_D39
136
138
DDR_B_D44
140
DDR_B_D45
142
144
DDR_B_DQS#5
146
DDR_B_DQS5
148
150
DDR_B_D46
152
DDR_B_D47
154
156
DDR_B_D52
158
DDR_B_D53
160
162
M_CLK_DDR4
164
M_CLK_DDR#4
166
168
DDR_B_DM6
170
172
DDR_B_D54
174
DDR_B_D55
176
178
DDR_B_D60
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
198
200
10K_0402_5%~D
12
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_CKE3_DIMMB <10>
DDR_B_BS#1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2 <10>
M_CLK_DDR4 <10>
M_CLK_DDR#4 <10>
R271
1 2
10K_0402_5%~D
R272
2.2U_0805_10V6K~D
0.1U_0402_16V4Z~D
1
1
C308
C320
2
2
+3VRUN
1
V_DDR_MCH_REF <10,17,45>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA-2171
16 50, 12, 2004
1
0.2
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DDR_A_DQS#[0..7]<11>
DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_MA[0..13]<11>
D D
+1.8VSUS
2.2U_0805_10V6K~D
2.2U_0805_10V6K~D
C341
1
2
0.1U_0402_16V4Z~D
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
B B
A A
0.1U_0402_16V4Z~D
1
1
2
2
C605
C606
DDR_A_MA5
DDR_A_MA8
56_0404_4P2R_5%~D
DDR_A_MA1
DDR_A_MA3
56_0404_4P2R_5%~D
DDR_A_RAS#
DDR_CS0_DIMMA#
56_0404_4P2R_5%~D
DDR_A_BS#0
DDR_A_MA10
56_0404_4P2R_5%~D
DDR_A_CAS#
DDR_A_WE#
56_0404_4P2R_5%~D
DDR_CS1_DIMMA#
M_ODT1
56_0404_4P2R_5%~D
0.1U_0402_16V4Z~D
1
2
C607
5
2.2U_0805_10V6K~D
C324
C326
1
1
2
2
0.1U_0402_16V4Z~D
1
2
RN32
RN33
RN17
RN34
RN35
RN36
C608
0.1U_0402_16V4Z~D
C342
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C335
+0.9V_DDR_VTT
C323
1
2
Layout Note:
Place one cap close to every2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
2 3
1 4
2.2U_0805_10V6K~D
1
2
C343
1
2
1
2
C330
RN30
RN20
RN31
RN19
RN18
RN16
RN21
2.2U_0805_10V6K~D
C340
1
2
0.1U_0402_16V4Z~D
C344
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C331
DDR_A_BS#2
14
DDR_CKE0_DIMMA
23
56_0404_4P2R_5%~D
DDR_A_MA7
14
DDR_A_MA6
23
56_0404_4P2R_5%~D
DDR_A_MA9
14
DDR_A_MA12
23
56_0404_4P2R_5%~D
DDR_A_MA4
14
DDR_A_MA2
23
56_0404_4P2R_5%~D
DDR_A_MA0
14
DDR_A_BS#1
23
56_0404_4P2R_5%~D
M_ODT0
14
DDR_A_MA13
23
56_0404_4P2R_5%~D
DDR_CKE1_DIMMA
14
DDR_A_MA11
23
56_0404_4P2R_5%~D
C325
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
C333
1
2
2
C332
4
Layout Note:
Place near JDIM2
@
M_CLK_DDR0
10P_0402_50V8J~D
1
C328
2
M_CLK_DDR#0
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C602
C334
Layout Note:
Place these resistor
closely JDIM2,all
trace length<750 mil
Layout Note:
Place these resistor
closely JDIM2,all
trace lengthMax=1.3"
4
3
@
M_CLK_DDR1
10P_0402_50V8J~D
1
C329
2
M_CLK_DDR#1
DDR_CKE0_DIMMA<10>
DDR_A_BS#2<11>
DDR_A_BS#0<11>
DDR_A_WE#<11>
DDR_A_CAS#<11>
DDR_CS1_DIMMA#<10>
M_ODT1<10>
0.1U_0402_16V4Z~D
1
1
2
2
C603
C604
CK_SDATA<6,16>
CK_SCLK<6,16>
+3VRUN
+1.8VSUS +1.8VSUS
JDIM2
1
VREF
3
C345
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-M2R-TR~D
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CK_SDATA
CK_SCLK
0.1U_0402_16V4Z~D
2.2U_0805_10V6K~D
C336
1
1
2
2
REVERSE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
NC/CKE1
DIMMB
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
2
1
V_DDR_MCH_REF
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DM0
10
12
DDR_A_D6
14
DDR_A_D7
16
18
DDR_A_D12
20
DDR_A_D13
22
24
DDR_A_DM1
26
28
M_CLK_DDR0
30
CK0
NC
A11
A7
A6
A4
A2
A0
BA1
S0#
NC
CK1
SA1
M_CLK_DDR#0
32
34
DDR_A_D14
36
DDR_A_D15
38
40
42
DDR_A_D20
44
DDR_A_D21
46
48
50
DDR_A_DM2
52
54
DDR_A_D22
56
DDR_A_D23
58
60
DDR_A_D28
62
DDR_A_D29
64
66
DDR_A_DQS#3
68
DDR_A_DQS3
70
72
DDR_A_D30
74
DDR_A_D31
76
78
DDR_CKE1_DIMMA
80
82
84
86
88
DDR_A_MA11
90
92
DDR_A_MA6
94
96
DDR_A_MA4
98
DDR_A_MA2
100
DDR_A_MA0
102
104
DDR_A_BS#1
106
DDR_A_RAS#
108
DDR_CS0_DIMMA#
110
112
M_ODT0
114
DDR_A_MA13
116
118
120
122
DDR_A_D36
124
DDR_A_D37
126
128
DDR_A_DM4
130
132
DDR_A_D38
134
DDR_A_D39
136
138
DDR_A_D44
140
DDR_A_D45
142
144
DDR_A_DQS#5
146
DDR_A_DQS5
148
150
DDR_A_D46
152
DDR_A_D47
154
156
DDR_A_D52
158
DDR_A_D53
160
162
M_CLK_DDR1
164
M_CLK_DDR#1
166
168
DDR_A_DM6
170
172
DDR_A_D54
174
DDR_A_D55
176
178
DDR_A_D60
180
DDR_A_D61
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D62
192
DDR_A_D63
194
196
198
200
10K_0402_5%~D
12
10K_0402_5%~D
R282
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_CKE1_DIMMA <10>
DDR_A_BS#1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
R286
1 2
0.1U_0402_16V4Z~D
2.2U_0805_10V6K~D
1
1
C346
2
2
V_DDR_MCH_REF <10,16,45>
C337
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
LA-2171
17 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
+3VRUN
1
C409
D D
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXP[0..15]
PEG_TXN[0..15]
5
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN15
C C
B B
PEG_TXP[0..15]<12>
PEG_TXN[0..15]<12>
A A
2
0.047U_0402_16V4Z~D
C121 0.1U_0402_16V4Z~D
1 2
C125 0.1U_0402_16V4Z~D
1 2
C134 0.1U_0402_16V4Z~D
1 2
C141 0.1U_0402_16V4Z~D
1 2
C143 0.1U_0402_16V4Z~D
1 2
C147 0.1U_0402_16V4Z~D
1 2
C149 0.1U_0402_16V4Z~D
1 2
C151 0.1U_0402_16V4Z~D
1 2
C155 0.1U_0402_16V4Z~D
1 2
C162 0.1U_0402_16V4Z~D
1 2
C170 0.1U_0402_16V4Z~D
1 2
C175 0.1U_0402_16V4Z~D
1 2
C182 0.1U_0402_16V4Z~D
1 2
C184 0.1U_0402_16V4Z~D
1 2
C187 0.1U_0402_16V4Z~D
1 2
C191 0.1U_0402_16V4Z~D
1 2
+1.8VSUS
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
1
1
C414
C417
2
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C123 0.1U_0402_16V4Z~D
1 2
C129 0.1U_0402_16V4Z~D
1 2
C140 0.1U_0402_16V4Z~D
1 2
C142 0.1U_0402_16V4Z~D
1 2
C145 0.1U_0402_16V4Z~D
1 2
C148 0.1U_0402_16V4Z~D
1 2
C150 0.1U_0402_16V4Z~D
1 2
C154 0.1U_0402_16V4Z~D
1 2
C161 0.1U_0402_16V4Z~D
1 2
C169 0.1U_0402_16V4Z~D
1 2
C174 0.1U_0402_16V4Z~D
1 2
C181 0.1U_0402_16V4Z~D
1 2
C183 0.1U_0402_16V4Z~D
1 2
C185 0.1U_0402_16V4Z~D
1 2
C189 0.1U_0402_16V4Z~D
1 2
C199 0.1U_0402_16V4Z~D
1 2
+3VSUS
PJP11
PAD-OPEN 4x4m
1 2
RUNPWROK<35,39,43,46>
VDDM
+15V
+2.5VRUN
4
DVI_TX0+
DVI_TX0-
DVI_TX1+
DVI_TX1-
DVI_TX2+
DVI_TX2-
DVI_CLK+
DVI_CLK-
PEG_A_TXP_0
PEG_A_TXN_0
PEG_A_TXP_1
PEG_A_TXN_1
PEG_A_TXP_2
PEG_A_TXN_2
PEG_A_TXP_3
PEG_A_TXN_3
PEG_A_TXP_4
PEG_A_TXN_4
PEG_A_TXP_5
PEG_A_TXN_5
PEG_A_TXP_6
PEG_A_TXN_6
PEG_A_TXN_7
PEG_A_TXP_8
PEG_A_TXN_8
PEG_A_TXP_9PEG_TXP9
PEG_A_TXN_9
PEG_A_TXP_10
PEG_A_TXN_10
PEG_A_TXP_11PEG_TXP11
PEG_A_TXN_11
PEG_A_TXP_12
PEG_A_TXN_12
PEG_A_TXP_13
PEG_A_TXN_13
PEG_A_TXP_14
PEG_A_TXN_14PEG_TXN14
PEG_A_TXP_15PEG_TXP15
PEG_A_TXN_15 PEG_RXP7
RUNPWROK
4
JVID
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
147
149
149
151
151
153
153
155
155
157
157
159
159
161
161
163
163
165
165
167
167
169
169
171
171
173
173
175
175
177
177
179
179
181
181
183
183
185
185
187
187
189
189
191
191
193
193
195
195
197
197
199
199
201
201
203
203
205
205
JAE_WB3M200VD1~D
2
2
4
4
6
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
SMBCLK_VGA
SMBDAT_VGA
TV_Y
TV_CVBS
TV_C
VSYNC
HSYNC
VGA_BLU
VGA_GRN
VGA_RED
CLK_DDC2
DAT_DDC2
DVI_SCLK_L
DVI_SDAT_L
PLTRST_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6PEG_A_TXP_7
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
+1.5VRUN
THERMATRIP_VGA#
GC_BL_SUSPEND
C537
0.1U_0603_25V7K~D
ICH_PCIE_WAKE#
3
+5VALW
SMBCLK_VGA <35>
SMBDAT_VGA <35>
TV_Y <19>
TV_CVBS <19>
TV_C <19>
VSYNC <19>
HSYNC <19>
VGA_BLU <19>
VGA_GRN <19>
VGA_RED <19>
CLK_DDC2 <19>
DAT_DDC2 <19>
PLTRST_VGA# <20>
CLK_PCIE_VGA <6>
CLK_PCIE_VGA# <6>
THERMATRIP_VGA# <15>
+5VRUN
GC_BL_SUSPEND <34>
2
2
C540
1
C535
1
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
ICH_PCIE_WAKE# <22,34>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+3VRUN
Q57
C
3 1
12
R545
+5VRUN
RB751V_SOD323~D
1
2
2
C647
C543
2
1
1
0.1U_0603_25V7K~D
2
B
E
100K_0402_5%~D
MMBT3904_SOT23~D
10K_0402_5%~D
D22
2 1
DVI_SCLK_L
DVI_SDAT_L
G_PWR_SRC
@
10U_1210_25V6K~D
R134
1 2
R548
12
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
1K_0402_5%~D
DVI_DETECT
G
2
Q58
13
D
S
2N7002_SOT23~D
G
2
Q59
13
D
S
2N7002_SOT23~D
PEG_RXP[0..15]
PEG_RXN[0..15]
2
1
2
1
2
PEG_RXP[0..15] <12>
PEG_RXN[0..15] <12>
2
DVI_TX2ÂDVI_TX2+
DVI_SCLK
DVI_SDAT
DVI_TX1ÂDVI_TX1+
L86
1 2
BLM11A121S_0603~D
C66
220P_0402_50V7K~D
L87
1 2
BLM11A121S_0603~D
C67
220P_0402_50V7K~D
1
L11
SHIELD5
12
1 2
DATA3
VCC5
GND5
HPDET
DATA0#
DATA0
DATA5#
DATA5
CLK#
CRT_B
5.6K_0402_5%~D
GND
CLK
G2
G4
G6
NC2
R547
12
1
C17
2
13
14
15
DVI_DETECT
16
DVI_TX0-
17
DVI_TX0+
18
19
20
21
22
DVI_CLK+
23
DVI_CLK-
24
C3
C4
C5
25
28
30
32
5.6K_0402_5%~D
12
DVI_SCLK
DVI_SDAT
Q42
1
2
3 6
4
SI4435DY_SO8~D
12
R462
100K_0402_5%~D
PEG_PWRON# GPWR_SRC_ON
13
D
Q44
2
2N7002_SOT23~D
G
S
0.1U_0402_16V4Z~D
8
7
5
+5VRUN
BLM31A260SPT_1206~D
JDVI
1
DATA2#
2
DATA2
3
SHIELD24
4
DATA4#
5
DATA4
6
DDCCLK
7
DDCDATA
9
DATA1#
10
DATA1
11
SHIELD13
12
8
C1
C2
26
27
29
31
2
C512
C518
1
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
SHIELDCLK
DATA3#
CRT_VSYNC
CRT_R
CRT_G
CRT_HSYNC
G1
G3
G5
NC1
JAE_DV2R029NDA
+5VRUN
R546
1
C658
220P_0402_50V7K~D
2
1
C659
220P_0402_50V7K~D
2
PWR_SRC G_PWR_SRC
2
R463
1
100K_0402_5%~D
RUN_ON<34,38,39,42,44,45>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
VGA andDVI connector
LA-2171
1
10U_0805_10V4M~D
1
C18
2
18 50, 12, 2004
0.2
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5
TV_C<18>
D D
C C
VGA_RED<18>
VGA_GRN<18>
VGA_BLU<18>
B B
TV_CVBS<18>
TV_Y<18>
VGA_RED
VGA_GRN
VGA_BLU
@
75_0402_5%~D
12
R363
C390
@
75_0402_5%~D
12
R364
C389
12
@
75_0402_5%~D
C391
R362
@
75_0402_5%~D
12
12
R5
R4
DDA204U
A2
K1
A1
A A
K2
5
L68
1.8UH_MDF1608A1R8K_10%_0603~D
1 2
@
82P_0402_50V8J~D
CLOSETOJSVID
1
2
@
1
2
1
2
@
75_0402_5%~D
L66
1.8UH_MDF1608A1R8K_10%_0603~D
1 2
82P_0402_50V8J~D
L67
1.8UH_MDF1608A1R8K_10%_0603~D
1 2
@
82P_0402_50V8J~D
@
75_0402_5%~D
12
R6
DAT_DDC2<18>
CLK_DDC2<18>
C8
HSYNC<18>
VSYNC<18>
@
22P_0402_50V8J~D
1
2
4
82P_0402_50V8J~D
1
C384
2
82P_0402_50V8J~D
1
C382
2
82P_0402_50V8J~D
1
C383
2
@
22P_0402_50V8J~D
1
C9
2
EvaluatePackage
1
C392
C393
2
33P_0402_50V8J~D
33P_0402_50V8J~D
4
1
C10
2
1
2
SVIDEO_C
SVIDEO_CVBS
SVIDEO_Y
@
22P_0402_50V8J~D
L71
BLM11A121S_0603~D
1 2
L70
BLM11A121S_0603~D
1 2
SPDIF<25>
L3
BLM18BB600SN1D_0603~D
1 2
L5
BLM18BB600SN1D_0603~D
1 2
L4
BLM18BB600SN1D_0603~D
1 2
CRT_VCC
12
R357
@
R358
1K_0402_5%~D
1
C385
2
22P_0402_50V8J~D
3
D16
DA204U_SOT323~D
1
@
+3VSUS
2
3
+5VRUN
2
C23
1
0.1U_0402_16V4Z~D
SPDIF
+3VRUN
12
@
R356
1 2
1K_0402_5%~D
C386
22P_0402_50V8J~D
2.2K_0402_5%~D
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
SPDIF_SHDN
5
1
U1
P
4
OE#
A2Y
G
3
SN74AHCT1G125DCKR_SC70-5~D
D2
DA204U_SOT323~D
1
@
2
3
1
C2
10P_0402_50V8J~D
2
R3
1 2
2.2K_0402_5%~D
3
SPDIF_SHDN <25,34>
R7
SP_DIFBSP_DIF
12
220_0603_1%~D
1
2
C11
0.01U_0402_16V7K~D
D3
DA204U_SOT323~D
1
@
2
3
C6
10P_0402_50V8J~D
12
1
2
T18 PAD~D
2
D14
DA204U_SOT323~D
1
@
2
3
D15
DA204U_SOT323~D
1
@
2
3
Overlap R8,R1 & L6 for PopOption
R8
1 2
0_0805_5%~D
SP_DIF_C
D4
DA204U_SOT323~D
1
@
3
2
4 5
1 8
L6
TA08F010_4P~D@
300P_1808_3000V8K~D@
+5VRUN
D1
12
R2
110_0603_1%~D
2
C3
10P_0402_50V8J~D
1
JSVID
2
4
6
7
5
3
1
8
9
FOX_MH11777-WRUR6~D
SP_DIF_D
SP_DIF_E
1
2
RB751V_SOD323~D
CRT_VCC
0.01U_0402_16V7K~D
1
C4
2
RED
DAT_DDC2
GREEN
JVGA_HS
BLUE
JVGA_VS
M_ID2#
CLK_DDC2
C5
0.1U_0402_16V4Z~D
12
R1
0_0805_5%~D
JVGA
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
FOX_DZ11A91-L8
C1
21
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
TV_OUT and CRT connector
LA-2171
1
18
19
19 50, 12, 2004
0.2
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5
RN5
+3VRUN
D D
+3VRUN
+3VRUN
+3VRUN
C C
+3VRUN
8.2K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
RN6
8.2K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
RN4
8.2K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_IRDY#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_PIRQD#
PCI_PIRQB#
ICH_GPIO5_PIRQH#
PCI_PIRQC#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R4618.2K_0402_5%~D
R2548.2K_0402_5%~D
R2558.2K_0402_5%~D
R4548.2K_0402_5%~D
R4598.2K_0402_5%~D
R4808.2K_0402_5%~D
R2518.2K_0402_5%~D
R4688.2K_0402_5%~D
R4608.2K_0402_5%~D
R4668.2K_0402_5%~D
R2538.2K_0402_5%~D
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
PCI_PIRQA#
PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#
PCI_REQ2#
PCI_REQ5#
PCI_REQB#
PCI_AD[0..31]<29,31,33>
PCI_FRAME#<29,31,33>
PCI_PIRQB#<31,33>
PCI_PIRQC#<29,31>
PCI_PIRQD#<31,33>
4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27ICH_GPIO4_PIRQG#
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_FRAME#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
U16B
E2
AD[0]
E5
AD[1]
C2
AD[2]
F5
AD[3]
F3
AD[4]
E9
AD[5]
F2
AD[6]
D6
AD[7]
E6
AD[8]
D3
AD[9]
A2
AD[10]
D2
AD[11]
D5
AD[12]
H3
AD[13]
B4
AD[14]
J5
AD[15]
K2
AD[16]
K5
AD[17]
D4
AD[18]
L6
AD[19]
G3
AD[20]
H4
AD[21]
H2
AD[22]
H5
AD[23]
B3
AD[24]
M6
AD[25]
B2
AD[26]
K6
AD[27]
K3
AD[28]
A5
AD[29]
L1
AD[30]
K4
AD[31]
J3
FRAME#
Interrupt I/F
N2
PIRQ[A]#
L2
PIRQ[B]#
M1
PIRQ[C]#
L3
PIRQ[D]#
AC5
SATA[1]RXN/RSVD[1]
AD5
SATA[1]RXP/RSVD[2]
AF4
SATA[1]TXN/RSVD[3]
AG4
SATA[1]TXP/RSVD[4]
AC9
SATA[3]RXN/RSVD[5]
AD9
SATA[3]RXP/RSVD[6]
AF8
SATA[3]TXN/RSVD[7]
AG8
SATA[3]TXP/RSVD[8]
U3
TP[3]/RSVD[9]
ICH6_BGA609~D
PCI
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]
PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]
PIRQ[H]#/GPI[5]
RESERVED
REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
PLTRST#
PCICLK
PME#
PAR
L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8
J6
H6
G4
G2
A3
E1
R2
C3
E3
C5
G5
J1
J2
R5
G6
P6
D9
C7
C6
M3
3
PCI_REQ0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_REQB#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PLTRST#
CK_33M_ICHPCI
ICH_PME#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ1# <31>
PCI_GNT1# <31>
PCI_REQ3# <33>
PCI_GNT3# <33>
PCI_REQ4# <29>
PCI_GNT4# <29>
PCI_C_BE0# <29,31,33>
PCI_C_BE1# <29,31,33>
PCI_C_BE2# <29,31,33>
PCI_C_BE3# <29,31,33>
PCI_IRDY# <29,31,33>
PCI_PAR <29,31,33>
PCI_DEVSEL# <29,31,33>
PCI_PERR# <29,31,33>
PCI_SERR# <29,31,33>
PCI_STOP# <29,31,33>
PCI_TRDY# <29,31,33>
PLTRST# <22,24,37>
CK_33M_ICHPCI <6>
ICH_PME# <34>
Internal Pull-up.
Sample high destination is LPC.
PCI_GNT5#
12
R470
0_0402_5%~D@
PLTRST_DELAY#<22,37>
PLTRST#
PCI_PCIRST#
2
+3VSUS
74VHC08MTC_TSSOP14~D
14
U13A
1
P
IN1
OUT
2
IN2
G
74VHC08MTC_TSSOP14~D
7
U13B
4
IN1
OUT
5
IN2
13
IN1
OUT
12
IN2
U13C
10
IN1
OUT
9
IN2
74VHC08MTC_TSSOP14~D
PCIRSTB1#
3
PCIRSTB2#
6
U13D
11
74VHC08MTC_TSSOP14~D
PCIRSTB3#
8
0.1U_0402_16V4Z~D
R151
33_0402_5%~D
1 2
C116
R152
33_0402_5%~D
1 2
R154
33_0402_5%~D
1 2
R153
33_0402_5%~D
1 2
R133
33_0402_5%~D
1 2
12
1
PLTRST_VGA# <18>
CK_33M_ICHPCI
PLTRST_LOM# <29>
PLTRST_SIO# <34>
PLTRST_MCH# <10>
PCIRST_CB# <31,33>
R469
10_0402_5%~D
@
1 2
B B
A A
+3.3VX
3
COINCELL
12
COINCELL_R
2
1
R509
1K_0402_5%~D
D20
BAT54C_SOT23~D
+RTC_CELL
1
C596
2
1U_0603_10V4Z~D
CLK_ICH_TERM
1
@
C547
8.2P_0402_50V8J~D
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
ICH6(1/4)
LA-2171
20 50, 12, 2004
1
0.2
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5
C188
12P_0603_50V8J~D
12
Package
D D
9.6X4.06 mm
+RTC_CELL
12
R182
100K_0402_5%~D
INTRUDER#
C C
ICH_SDOUT_AUDIO<25>
B B
ICH_SYNC_AUDIO<25>
ICH_RST_AUDIO#<25>
ICH_AC_BITCLK<25>
1 2
1 2
1 2
R266
33_0402_5%~D
ICH_AC_SDOUT_R
R265
33_0402_5%~D
ICH_AC_SYNC_R
R248
33_0402_5%~D
ICH_AC_RST_R#
32.768KHZ_12.5P_MC-306~D
C203
12P_0603_50V8J~D
12
+RTC_CELL
INTRUDER#<15>
ICH_SYNC_MDC<27>
ICH_RST_MDC#<27>
R473
10_0402_5%~D
@
1 2
ICH_SDOUT_MDC<27>
ICH_AC_BITCLK_TERM
2
C571
10P_0402_50V8J~D
1
@
1 2
X3
R184
180K_0402_5%~D
CMOS_CLR
SHORTPADS~D
1
1
C172
0.1U_0402_16V4Z~D
1 2
ICH_RTCX1
ICH_RTCX2
1 2
2
ICH_AC_SDIN0<25>
ICH_AC_SDIN1<27>
IDE_DIORDY<24>
IDE_IRQ<24>
IDE_DDACK#<24>
12
R204
10M_0402_5%~D
2
1 2
1 2
R252
1 2
33_0402_5%~D
SATA_ACT#<37>
SATA_RXN0_C<24>
SATA_RXP0_C<24>
CLK_PCIE_SATA#<6>
CLK_PCIE_SATA<6>
IDE_DIOW#<24>
IDE_DIOR#<24>
4
R25033_0402_5%~D
R24933_0402_5%~D
ICH_RTCRST#
INTRUDER#
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDIN0
ICH_AC_SDIN1
ICH_AC_SDOUT_R
SATA_ACT#
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
1 2
24.9_0603_1%~D
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
R177
AC19
AG11
AF11
AF16
AB16
AB15
AC14
AE16
Y1
Y2
AA2
AA3
AA5
D12
B12
D11
F13
F12
B11
E12
E11
C13
C12
C11
E13
C10
B9
A10
F11
F10
B10
C9
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
AC2
AC1
U16A
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LANRXD[0]
LANRXD[1]
LANRXD[2]
LANTXD[0]
LANTXD[1]
LANTXD[2]
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO
SATALED#
SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
ICH6_BGA609~D
RTC
LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]
LPC
LDRQ[0]#
LDRQ[1]#/GPI[41]
LFRAME#/FWH[4]
LAN
A20GATE
A20M#
CPUSLP#
CPU
DPRSLP#/TP[4]
DPSLP#/TP[2]
FERR#
CPUPWRGD/GPO[49]
IGNNE#
INIT3_3V#
RCIN#
STPCLK#
THRMTRIP#
DA[0]
DA[1]
DA[2]
DCS1#
DCS3#
SATAAC-97/AZALIA
DD[0]
DD[1]
IDE
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]
DDREQ
SMI#
INIT#
INTR
3
LPC_LAD0
P2
LPC_LAD1
N3
LPC_LAD2
N5
LPC_LAD3
N4
LPC_LDRQ0#
N6
LPC_LDRQ1#
P4
LPC_LFRAME#
P3
SIO_A20GATE
AF22
A20M#
AF23
CPUSLP#
AE27
AE24
DPSLP#
AD27
FERR#
AF24
H_PWRGOOD
AG25
IGNNE#
AG26
AE22
ICH4_INIT#
AF27
INTR
AG24
SIO_RCIN#
AD23
NMI
AF25
NMI
AG27
AE26
AE23
AC16
AB17
AC17
AD16
AE17
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AB14
SMI#
STPCLK#
THRMTRIP_ICH#
IDE_DA0
IDE_DA1
IDE_DA2
IDE_DCS1#
IDE_DCS3#
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
LPC_LAD[0..3] <34>
Note : R169 Do not populate for
Dothan-A, Populte for Dothan-B.
LPC_LDRQ0# <34>
LPC_LDRQ1# <34>
LPC_LFRAME# <34>
R170 0_0402_5%~D
R423 0_0402_5%~D
R169 0_0402_5%~D@
R425 0_0402_5%~D
R168 56_0402_5%~D
R158 0_0402_5%~D
R419 0_0402_5%~D
R159 0_0402_5%~D
R167 0_0402_5%~D
R166 0_0402_5%~D
R420 0_0402_5%~D
R164 75_0402_5%~D
IDE_DA0 <24>
IDE_DA1 <24>
IDE_DA2 <24>
IDE_DCS1# <24>
IDE_DCS3# <24>
R435
0_0402_5%~D
12
12
12
12
12
12
12
12
12
12
12
1 2
IDE_DD[0..15] <24>
1 2
C506
33P_0402_50V8J~D
RDDREQIDE_DDREQ
2
1
2
H_A20M#
H_CPUSLP#
H_DPRSLP#DPRSLP#
H_DPSLP#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
RDDREQ <24>
SIO_A20GATE <35>
H_A20M# <7>
H_CPUSLP# <7,10>
H_DPRSLP# <7>
H_DPSLP# <7>
H_FERR# <7>
H_PWRGOOD <7>
H_IGNNE# <7>
H_INIT# <7>
H_INTR <7>
SIO_RCIN# <34>
H_NMI <7>
H_SMI# <7>
H_STPCLK# <7>
+VCCP
1
+VCCP
12
12
H_FERR#
H_DPRSLP#
R160
56_0402_5%~D
R161
56_0402_5%~D@
Note : R423 must be stuff for
Dothan-A, no-stuff for Dothan-B.
Note : R168 populate 56 ohm for
Dothan-A, Populte zero ohm for
Dothan-B.
SATA_TXN0_C
1 2
C467 0.01U_0402_16V7K~D
1 2
C476 0.01U_0402_16V7K~D
SATA_TXN0
SATA_TXP0SATA_TXP0_C
SATA_TXN0 <24>
SATA_TXP0 <24>
Near ICH6 side.
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
ICH6(2/4)
LA-2171
21 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
4
+3VSUS
12
3
2
1
R448
10K_0402_5%~D
D D
+3VSUS
10K_0402_5%~D
R431
ICH_SMBDATA<6>
ICH_SMBCLK<6>
C C
B B
+3VRUN
R178
@
DPRSLPVR
A A
R165
100K_0402_5%~D
KAPALUA system can'tboot issue
May need pulldownfor DPRSLPVR incase
the ICH6m does not set thisvaluein time
for boot.
5
+3VSUS
10K_0402_5%~D
R429
10K_0402_5%~D
10K_0402_5%~D
R446
1 2
1 2
1K_0402_5%~D
12
@
R437
1 2
1 2
(PCI Express Wake Event)
CK_14M_ICH<6>
CK_48M_ICH<6>
1 2
ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK0
ICH_SMLINK1
R471
@
1 2
CK_14M_ICH_TERM
@
2
C558
1
CLKRUN#
CK_14M_ICH
CK_48M_ICH
1 2
10_0402_5%~D
CK_48M_ICH_TERM
2
1
4.7P_0402_50V8C~D
SIO_EXT_WAK#<34>
+3VSUS
PLTRST_DELAY#<20,37>
+3VRUN
12
R173
10K_0402_5%~D
R432
10K_0402_5%~D
+3VSUS
+3VSUS
R474
@
10_0402_5%~D
+3VSUS
+3VSUS
@
+3VSUS
C567
4.7P_0402_50V8C~D
1 2
R445
10K_0402_5%~D
1 2
R440
10K_0402_5%~D
1 2
R442
10K_0402_5%~D
1 2
R443
680_0402_5%~D
1 2
4
R174 33_0402_5%~D
SPKR<25>
PM_BMBUSY#<10>
R163 10K_0402_5%~D
+3VRUN
SIO_EXT_SMI#<34>
SIO_EXT_SCI#<34>
H_STP_PCI#<6>
H_STP_CPU#<6,46>
R172
1 2
10K_0402_5%~D@
CLKRUN#<29,31,33,34>
ICH_PCIE_WAKE#<18,34>
IRQ_SERIRQ<31,34>
SIO_THRM#<34>
IMVP_PWRGD<10,39,46>
SIO_SLP_S3#<34>
SIO_SLP_S5#<34>
ICH_PWRGD<39>
DPRSLPVR<46>
SIO_PWRBTN#<34>
PLTRST#<20,24,37>
SUSPWROK<15,39>
LINKALERT#
SYS_RESET#
USB2P0_SMI#
ICH_BATLOW#
ICH_PCIE_WAKE#
ICH_RI#
1 2
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR
PAD~D
T26
SYS_RESET#
PM_BMBUSY#
1 2
SIO_EXT_SMI#
USB2P0_SMI#
SIO_EXT_WAK# GPI12
T27
PAD~D
R91 0_0402_5%~D
1 2
SIO_EXT_SCI#
H_STP_PCI#
H_STP_CPU#
LCD_BIST_EN
R549
0_0402_5%~D
1 2
R90
0_0402_5%~D@
GPIO24SIO_EXT_WAK#
1 2
CLKRUN#
IRQ_SERIRQ
SIO_THRM#
IMVP_PWRGD
CK_14M_ICH
CK_48M_ICH
ICH_SUSCLK
SIO_SLP_S3#
T28
SIO_SLP_S5#
ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
PLTRST#
SUSPWROK
12
10K_0402_5%~D
R198
+3VRUN
+3VRUN
+3VRUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PAD~D
12
1 2
1 2
1 2
3
U16C
T2
RI#
AF17
SATA[0]GP/GPI[26]
AE18
SATA[1]GP/GPI[29]
AF18
SATA[2]GP/GPI[30]
AG18
SATA[3]GP/GPI[31]
Y4
SMBCLK
W5
SMBDATA
Y5
LINKALERT#
W4
SMLINK[0]
U6
SMLINK[1]
AG21
MCH_SYNC#
F8
SPKR
W3
SUS_STAT#/LPCPD#
U2
SYS_RESET#
AD19
BM_BUSY#/GPI[6]
AE19
GPI[7]
R1
GPI[8]
W6
SMBALERT#/GPI[11]
M2
GPI[12]
R6
GPI[13]
AC21
STP_PCI#/GPO[18]
AB21
GPO[19]
AD22
STP_CPU#/GPO[20]
AD20
GPO[21]
AD21
GPO[23]
V3
GPIO[24]
P5
GPIO[25]
R3
GPIO[27]
T3
GPIO[28]
AF19
CLKRUN#/GPIO[32]
AF20
GPIO[33]
AC18
GPIO[34]
U5
WAKE#
AB20
SERIRQ
AC20
THRM#
AF21
VRMPWRGD
E10
CLK14
A27
CLK48
V6
SUSCLK
T4
SLP_S3#
T5
SLP_S4#
T6
SLP_S5#
AA1
PWROK
AE20
DPRSLPVR/TP[1]
V2
BATLOW#/TP[0]
U1
PWRBTN#
V5
LAN_RST#
Y3
RSMRST#
ICH6_BGA609~D
10K_0402_5%~D
R197
R441
8.2K_0402_5%~D
R171
10K_0402_5%~D
R434
10K_0402_5%~D
SIO_THRM#
MCH_SYNC#
IRQ_SERIRQ
GPIO
CLOCK
POWER MGT
PERn[1]
PERp[1]
PETn[1]
PETp[1]
PERn[2]
PERp[2]
PETn[2]
PETp[2]
PERn[3]
PERp[3]
PETn[3]
PETp[3]
PERn[4]
PERp[4]
PCI-EXPRESSDIRECT MEDIA INTERFACE
PETn[4]
PETp[4]
DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP
DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP
DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP
DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]
OC[0]#
OC[1]#
OC[2]#
OC[3]#
USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USB
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P
USBRBIAS#
USBRBIAS
H25
H24
G27
G26
K25
K24
J27
J26
M25
M24
L27
L26
P24
P23
N27
N26
T25
T24
R27
R26
V25
V24
U27
U26
Y25
Y24
W27
W26
AB24
AB23
AA27
AA26
AD25
AC25
F24
F23
C23
D23
C25
C24
C27
B27
B26
C26
C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14
A22
B22
PCIE_RXN1_C
PCIE_RXP1_C
PCIE_TXN1_C
PCIE_TXP1_C
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_IRCOMP
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USBRBIAS
PCIE_RXN1_C <37>
PCIE_RXP1_C <37>
PCIE_TXN1_C
PCIE_TXP1_C
DMI_RXN0 <10>
DMI_RXP0 <10>
DMI_TXN0 <10>
DMI_TXP0 <10>
DMI_RXN1 <10>
DMI_RXP1 <10>
DMI_TXN1 <10>
DMI_TXP1 <10>
DMI_RXN2 <10>
DMI_RXP2 <10>
DMI_TXN2 <10>
DMI_TXP2 <10>
DMI_RXN3 <10>
DMI_RXP3 <10>
DMI_TXN3 <10>
DMI_TXP3 <10>
R467 24.9_0603_1%~D
1 2
1 2
22.6_0603_1%~D
2
C661 0.1U_0402_10V7K~D
1 2
C662 0.1U_0402_10V7K~D
1 2
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
R479
+1.5VRUN
USBP0- <28>
USBP0+ <28>
USBP1- <28>
USBP1+ <28>
USBP2- <28>
USBP2+ <28>
USBP3- <31>
USBP3+ <31>
USBP4- <28>
USBP4+ <28>
USBP5- <28>
USBP5+ <28>
USBP6- <28>
USBP6+ <28>
USBP7- <28>
USBP7+ <28>
USB_OC4# <28>
USB_OC5# <28>
USB_OC6# <28>
USB_OC7# <28>
USB_OC0# <28>
USB_OC1# <28>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
PCIE_TXN1
PCIE_TXP1
USB_OC0#
USB_OC3#
USB_OC1#
USB_OC2#
USB_OC6#
USB_OC7#
USB_OC4#
USB_OC5#
10K_1206_8P4R_5%~D
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
4 5
3 6
2 7
1 8
Compal Electronics, Inc.
ICH6(3/4)
LA-2171
PCIE_TXN1 <37>
PCIE_TXP1 <37>
RN7
RN8
1
+3VSUS
0.2
22 50, 12, 2004
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5
Near PINF27(C968),
L82
+1.5VRUN
D D
+3VRUN
+5VRUN
21
1 2
1 2
D19
RB751V_SOD323~D
@
2
C574
1U_0603_10V4Z~D
1
+3VSUS+5VSUS
21
D17
RB751V_SOD323~D@
2
C538
1U_0603_10V4Z~D
1
R477
1K_0402_5%~D@
R472
10_0402_5%~D@
C C
1 2
BLM21PG600SN1D_0805~D
ICH_V5REF_RUN
2
C561
0.1U_0402_16V4Z~D
1
ICH_V5REF_SUS
2
C549
0.1U_0402_16V4Z~D
1
2
C570
0.1U_0402_16V4Z~D
1
Replacing by this circuit?
Note: Intel will update design guide.
R162
10_0402_5%~D
R478
10_0402_5%~D
5
ICH_V5REF_RUN
ICH_V5REF_SUS
L80
BLM11A601S_0603~D
1 2
+3VRUN
ICH6_VCCPLL
2
1
C501
C491
1
2
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
Near PIN
AC27
+5VSUS
B B
+5VALW
+1.5VRUN
A A
1 2
1 2
R438
1 2
1_0402_5%~D
P27(C949), AB27(C950)
+1.5VRUN_L
1
+
C514
2
220U_D2_4VM
+1.5VRUN
Near PINAG5
+1.5VRUN
Near PINAG9
2
C557
1
0.1U_0402_16V4Z~D
Near PIN
E26, E27
+3VSUS
Near PINA17
+1.5VRUN
4
2
2
C542
C488
1
1
0.1U_0402_16V4Z~D
C480
C468
2
C475
1
0.1U_0402_16V4Z~D
Near PINAE1
2
C569
1
0.1U_0402_16V4Z~D
4
2
C516
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
ICH6_VCCPLL
+3VRUN
+3VRUN
+3VSUS
2
C562
1
3
+1.5VRUN
V5REF[2]
V5REF[1]
VCCRTC
F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19
AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12
P1
M7
L7
L4
J7
H7
H1
E4
B1
A6
U7
R7
G19
G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24
G8
AB18
P7
AA18
A8
F21
A25
A24
AB3
G11
G10
AG23
AD26
AB22
G16
G15
F16
F15
E16
D16
C16
+1.5VRUN
2
C471
1
2
C546
1
+1.5VSUS
1
2
C551
0.1U_0402_16V4Z~D
+1.5VRUN
ICH_V5REF_RUN
ICH_V5REF_SUS
+1.5VRUN
+3VSUS
1
2
C469
0.1U_0402_16V4Z~D
2
C474
1
0.1U_0402_16V4Z~D
2
C564
1
0.1U_0402_16V4Z~D
+RTC_CELL
+1.5VRUN
+VCCP
+3VRUN
Near PIN
AG13, AG16
0.1U_0402_16V4Z~D
+3VRUN
2
C568
1
Near PIN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
A2-A6, D1-H1
1
2
2
1
C511
C524
0.1U_0402_16V4Z~D
Near PINU7
+2.5VRUN
1
2
Near PINAB18
Near PINAG23
+3VRUN
0.1U_0402_16V4Z~D
1 2
1 2
0.1U_0402_16V4Z~D
C473
C472
0.1U_0402_16V4Z~D
C487
+1.5VSUS
0.1U_0402_16V4Z~D
@
U16E
AA22
VCC1_5[1]
AA23
VCC1_5[2]
AA24
VCC1_5[3]
AA25
VCC1_5[4]
AB25
VCC1_5[5]
AB26
VCC1_5[6]
AB27
VCC1_5[7]
F25
VCC1_5[8]
F26
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
VCC1_5[9]
F27
VCC1_5[10]
G22
VCC1_5[11]
G23
VCC1_5[12]
G24
VCC1_5[13]
G25
VCC1_5[14]
H21
VCC1_5[15]
H22
VCC1_5[16]
J21
VCC1_5[17]
J22
VCC1_5[18]
K21
VCC1_5[19]
K22
VCC1_5[20]
L21
VCC1_5[21]
L22
VCC1_5[22]
M21
VCC1_5[23]
M22
VCC1_5[24]
N21
VCC1_5[25]
N22
VCC1_5[26]
N23
VCC1_5[27]
N24
VCC1_5[28]
N25
VCC1_5[29]
P21
VCC1_5[30]
P25
VCC1_5[31]
P26
VCC1_5[32]
P27
VCC1_5[33]
R21
VCC1_5[34]
R22
VCC1_5[35]
T21
VCC1_5[36]
T22
VCC1_5[37]
U21
VCC1_5[38]
U22
VCC1_5[39]
V21
VCC1_5[40]
V22
VCC1_5[41]
W21
VCC1_5[42]
W22
VCC1_5[43]
Y21
VCC1_5[44]
Y22
VCC1_5[45]
AA6
VCC1_5[46]
AB4
VCC1_5[47]
AB5
VCC1_5[48]
AB6
VCC1_5[49]
AC4
VCC1_5[50]
AD4
VCC1_5[51]
AE4
VCC1_5[52]
AE5
VCC1_5[53]
AF5
VCC1_5[54]
AG5
VCC1_5[55]
AA7
VCC1_5[56]
AA8
VCC1_5[57]
AA9
VCC1_5[58]
AB8
VCC1_5[59]
AC8
VCC1_5[60]
AD8
VCC1_5[61]
AE8
VCC1_5[62]
AE9
VCC1_5[63]
AF9
VCC1_5[64]
AG9
VCC1_5[65]
AC27
VCCDMIPLL
E26
VCC3_3[1]
AE1
VCCSATAPLL
AG10
VCC3_3[22]
A13
VCCLAN3_3/VCCSUS3_3[1]
F14
VCCLAN3_3/VCCSUS3_3[2]
G13
VCCLAN3_3/VCCSUS3_3[3]
G14
VCCLAN3_3/VCCSUS3_3[4]
A11
VCCSUS3_3[1]
U4
VCCSUS3_3[2]
V1
VCCSUS3_3[3]
V7
VCCSUS3_3[4]
W2
VCCSUS3_3[5]
Y7
VCCSUS3_3[6]
A17
VCCSUS3_3[7]
B17
VCCSUS3_3[8]
C17
VCCSUS3_3[9]
F18
VCCSUS3_3[10]
G17
VCCSUS3_3[11]
G18
VCCSUS3_3[12]
ICH6_BGA609~D
PCIE
SATA
VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
COREIDE
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]
VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]
VCC3_3[11]
VCC3_3[10]
VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
PCIUSB
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]
VCCSUS1_5[3]
VCCSUS1_5[2]
VCCSUS1_5[1]
VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
USB CORE
VCC1_5[69]
VCC1_5[68]
VCC1_5[67]
VCC2_5[4]
PCI/IDE RBP
VCC2_5[2]
V5REF_SUS
VCCUSBPLL
VCCSUS3_3[20]
VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]
V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]
VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]
Near PINAG10
2
C502
0.1U_0402_16V4Z~D
1 2
C550
0.1U_0402_16V4Z~D
1 2
C548
0.1U_0402_16V4Z~D
1 2
C494
0.1U_0402_16V4Z~D
1 2
C498
0.1U_0402_16V4Z~D
1 2
C556
0.1U_0402_16V4Z~D
1 2
C555
0.1U_0402_16V4Z~D
1 2
C521
0.1U_0402_16V4Z~D
1 2
C522
0.1U_0402_16V4Z~D
1 2
C536
0.1U_0402_16V4Z~D
1 2
C566
0.01U_0402_16V7K~D
1 2
Near PINA25
C499
0.01U_0402_16V7K~D
1 2
Near PINAA19
+3VSUS
C565
0.1U_0402_16V4Z~D
1 2
C552
0.1U_0402_16V4Z~D
1 2
C554
0.1U_0402_16V4Z~D
1 2
C553
0.1U_0402_16V4Z~D
1 2
Near PINA24
U16D
E27
Y6
Y27
Y26
Y23
W7
W25
W24
W23
W1
V4
V27
V26
V23
U25
U24
U23
U15
U13
T7
T27
T26
T23
T16
T15
T14
T13
T12
T1
R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N7
N17
N16
N15
N14
N13
N12
N11
N1
M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13
K7
K27
K26
K23
K1
J4
J25
J24
J23
H27
H26
H23
G9
G7
G21
G12
G1
ICH6_BGA609~D
VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]
+RTC_CELL
1
2
C492
0.1U_0402_16V4Z~D
1
2
VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]
C493
1
F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
ICH6(4/4)
LA-2171
23 50, 12, 2004
1
0.2
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A
+3VRUN
1 1
R303
4.7K_0402_5%~D
R276
1 2
10K_0402_5%~D@
IDE_HIORDY
12
ATAIOSEL
HDD Connector
IDE_HRESET#
IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
+5VHDD
2 2
+5VHDD
IDE_HDD0
IDE_HDREQ
IDE_HDIOW#
510_0402_5%~D@
IDE_HDIOR#
12
IDE_HIORDY
IDE_HDMACK#
R285
IDE_HINTRQ
IDE_HDA1
IDE_HCS0#
0.1U_0402_16V4Z~D
C307
0.1U_0402_16V4Z~D
C306
2
2
1
1
JHDD
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
13
13
14
15
15
16
17
17
18
19
19
20
21
21
22
23
23
24
25
25
26
27
27
28
29
29
30
31
31
32
33
33
34
35
35
36
37
37
38
39
39
40
41
41
42
43
43
FOX_HH99223-SA_REVERS~D
44
B
R298
1 2
10K_0402_5%~D
R317
1 2
5.6K_0402_5%~D
2
IDE_HDD8
4
IDE_HDD9
6
IDE_HDD10
8
IDE_HDD11
10
IDE_HDD12
12
IDE_HDD13
14
IDE_HDD14
16
IDE_HDD15
18
20
22
24
26
R306 470_0402_5%~D
28
30
32
34
36
38
40
42
44
1 2
R296 10K_0402_5%~D
1 2
IDE_HDA2IDE_HDA0
IDE_HCS1#
C322
1
2
C
SATA to PATA Bridge
IDE_HINTRQ
IDE_HDREQ
VSS_SATA
+3VRUN
R291
+5VHDD
4.7U_0805_10V4Z~D
@
10K_0402_5%~D
1 2
IDE_HRESET#
R273
R499 33_0402_5%~D
1 2
1 2
25MHz_20P_1BX25000CK1A~D
1 2
1M_0402_5%~D
1
C593
33P_0402_50V8J~D
2
IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
10K_0402_5%~D
IDE_HDA0
IDE_HDA1
IDE_HDA2
IDE_HCS0#
IDE_HCS1#
1 2
IDE_HIOCS16#
IDE_HINTRQ
IDE_HDMACK#
IDE_HIORDY
IDE_HDIOR#
IDE_HDIOW#
IDE_HDREQ
10K_0402_5%~D
12
T40 PAD~D
R484
T41 PAD~D
D
X7
XTLOUTXTLIN
0_0402_5%~D
12
R494
R493
33P_0402_50V8J~D
1
C592
2
U28
62
HDD0
64
HDD1
2
HDD2
5
HDD3
7
HDD4
11
HDD5
13
HDD6
15
HDD7
14
HDD8
12
HDD9
10
HDD10
6
HDD11
3
HDD12
1
HDD13
63
HDD14
61
HDD15
50
HDA0
51
HDA1
49
HDA2
48
HCS0#
47
HCS1#
52
HIOCS16#
53
HINTRQ
54
HDMACK#
55
HIORDY
58
HDIOR#
59
HDIOW#
60
HDMARQ
16
HRESET#
46
HPDIAG#
45
UART
UAO
43
UAI
88SA8040_TQFP64~D
CNFG2
CNFG1
CNFG0
SATA
Parallel ATA
Config & Debug
Power
E
+3VRUN +3VRUN +3VRUN
10K_0402_5%~D@
10K_0402_5%~D@
R280
R278
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D@
R281
R279
1 2
1 2
32
TX_P
31
TX_M
27
RX_P
28
RX_M
17
RST#
33
T0
34
T1
35
T2
36
T3
37
T4
38
T5
39
T6
40
T7
20
CNFG2
19
CNFG1
18
CNFG0
21
ATAIOSEL
22
XTLIN/OSC
23
XTLOUT
R275 12.1K_0603_1%~D
26
ISET
4
VDDIO_0
44
VDDIO_1
9
VDD_0
41
VDD_1
56
VDD_2
24
VAA1
29
VAA2
VSS_SATA
25
VSS1
30
VSS2
8
GND_0
42
GND_1
57
GND_2
Reference clock configuration
10K_0402_5%~D@
R283
1 2
@
10K_0402_5%~D
R284
1 2
SATA_RXP0
SATA_RXN0
SATA_TXP0 <21>
SATA_TXN0 <21>
1 2
1 2
1 2
1 2
1 2
1 2
CNFG2
CNFG1
CNFG0
ATAIOSEL
XTLIN
XTLOUT
C305
PLTRST# <20,22,37>
12
0.01U_0402_16V7K~D
1
C314
2
R489 10K_0402_5%~D
R488 10K_0402_5%~D
R487 10K_0402_5%~D@
R486 10K_0402_5%~D
R485 10K_0402_5%~D
R496 10K_0402_5%~D
*
@
@
+3VRUN
+1.8VRUN
+3VRUN_SATA
0.1U_0402_16V4Z~D
1
C304
2
T4 T3
1000P_0402_50V7K~D
1
2
F
0
0
0
1
1
0
1
1
+3VRUN
VSS_SATA
BLM31A260SPT_1206~D
2.2U_0805_10V6K~D
1
C316
2
20MHz
25MHz
30MHz
40MHz
L45
1 2
Place near 88SA8040
Layout Notes:
Place close to 88SA8040
+3VRUN
1
C295
2
G
H
PU / PD is internal pull-up or pull-down 100Kohm
Pin Name
SATATEST0
SATATEST1
SATATEST2
SATATEST3
SATATEST4
SATATEST5
SATATEST6
SATATEST7
CFG0
CFG1
CFG2
SATA_RXN0
SATA_RXP0
4.7U_0805_10V4Z~D
C594
1
2
Pin No. Settings
C482
0.01U_0402_16V7K~D
C486
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
C587
1
2
Int. PU/PD
33
34
35
36
37
38
39
40
20
19
PD
PU NC
PD
PD
PD
PU
PD
PD
PD
PU
18 PD
12
12
+1.8VRUN +3VRUN
0.1U_0402_16V4Z~D
C309
1
2
0.1U_0402_16V4Z~D
SATA_RXN0_C <21>
SATA_RXP0_C <21>
4.7U_0805_10V4Z~D
C595
1
C588
2
0.1U_0402_16V4Z~D
1
2
NC
NC
1
NC
0
1
NC
NC
0
NC
0.1U_0402_16V4Z~D
C586
1
2
3 3
IDE_RST_MOD<34>
+5VMOD
100K_0402_5%~D
R520
1 2
4 4
A
IDE_DIOW#<21>
IDE_DIORDY<21>
IDE_IRQ<21>
IDE_DA1<21>
IDE_DA0<21>
IDE_DCS1#<21> IDE_DCS3# <21>
R524
470_0402_5%~D
1 2
CD-ROM Connector
C350
1 2
47P_0402_50V8J~D
+5VMOD
SEC_CSEL
B
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
CDROM_ACT#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SUYIN_80095AR-050G1T~D
JMOD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
C
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
RDDREQ <21>
IDE_DIOR# <21>
RPDDACK#
PDIAG#
R523 100K_0402_5%~D
1 2
IDE_DA2 <21>
C367
1 2
0.1U_0402_16V4Z~D
+5VMOD
+5VMOD
Layout Note: W=80 mils
D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3VRUN
R436
12
8.2K_0402_5%~D
R175
1 2
4.7K_0402_5%~D
R325
IDE_DDACK#<21>
1 2
22_0402_5%~D
Layout Note: Place close to CD-ROM CONN.
+5VMOD
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
C370
1
C368
2
E
1U_0603_10V4Z~D
1
1
C365
2
2
IDE_IRQ
IDE_DIORDY
RPDDACK#
10U_0805_10V4M~D
1
C363
2
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DD[0..15] <21>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
F
Date: Sheet of
Compal Electronics, Inc.
SATA to PATA BRIDGE & CD-ROM CONN.
LA-2171
G
24 50, 12, 2004
H
0.2
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5
4
3
2
1
VDDA
1
1A
2
BEEP<34>
1B
CBS_SPK<31>
C222
0.33U_0603_10V7K~D
1 2
C217
1 2
0.1U_0402_16V4Z~D
C205
1 2
0.1U_0402_16V4Z~D
1 2
R210
0_0402_5%~D
2
C193
1000P_0402_50V7K~D
1
2
C192
1000P_0402_50V7K~D
1
L16
BLM11A121S_0603~D
1 2
8
U8A
P
7
1Y
G
4
Z2401
5
2A
Z2402
6
2B
HP_OUT_L <26>
HP_OUT_R <26>
AUD_MONO_OUT <27>
AUD_LINE_OUT_L <26>
AUD_LINE_OUT_R <26>
1
C81
0.1U_0402_16V4Z~D
2
8
U8B
P
3
2Y
G
SN74LVC2G86DCTR_SSOP8~D
4
R115
10K_0402_5%~D
Z2403 PC_BEEP
1 2
NB_MICIN <26>
single gate TTL
0.1U_0402_16V4Z~D
Z2404
12
R105
8.2K_0402_5%~D@
TRACE>15 mil
CLOCK SOURCE
14.318 MHz
27 MHz
48 MHz
24.576 MHz
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
LA-2171
2
Date: Sheet of
1
C98
C93
2
0.1U_0402_16V4Z~D
STAC9751
DVSS14DVSS2
7
VDDA
1
C96
2
2.2U_0805_10V6K~D
DVDD11DVDD29AVDD125AVDD2
1
2
0.1U_0402_16V4Z~D
38
AVSS126AVSS2
42
1 2
1
C101
2
0.047U_0402_16V4Z~D
VDDA
LINE_IN_L
LINE_IN_R
CD_L
CD_GND
CD_R
AUX_L
AUX_R
MIC1
MIC2
VIDEO_L
VIDEO_R
PHONE
PC_BEEP
HP_OUT_L
HP_COMM
HP_OUT_R
MONO_OUT
LOUT_L
LOUT_R
STAC9751TG_TQFP48~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+5VSUS
2
1
1
C97
C99
C115
D D
C C
ICH_AC_BITCLK<21>
MDC_AC_BITCLK<27>
ICH_AC_SDIN0<21>
B B
A A
2
0.1U_0402_16V4Z~D@
0.01U_0402_16V7K~D@
ICH_SDOUT_AUDIO
R222
47_0402_5%~D@
1 2
ICH_AC_SDOUT_TERM
1
C258
22P_0402_50V8J~D
2
@
2
ICH_RST_AUDIO#
ICH_SYNC_AUDIO
ICH_SDOUT_AUDIO
AUDIO_AVDD_ON<35>
1
1U_0603_10V4Z~D@
C249
10P_0402_50V8J~D@
1 2
C248
10P_0402_50V8J~D@
1 2
C247
10P_0402_50V8J~D@
1 2
1
1
C266
C267
2
2
@
27P_0603_50V8J~D
CK_14M_CODEC
12
R219
33_0402_5%~D@
CK_14M_CODEC_TERM
1
C244
2
5
@
27P_0603_50V8J~D
2
C190
1
2.2U_0805_10V6K~D
22P_0402_50V8J~D@
@
AUDIO_AVDD_ON TPS793333_BYPASS
R233
33_0402_5%~D
1 2
R234
33_0402_5%~D
1 2
R235
33_0402_5%~D
1 2
1
C268
2
27P_0603_50V8J~D
2
C194
2
C195
1
1
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
CK_14M_CODEC<6>
U9
IN1OUT
2
GND
EN3BYPASS
TPS793333DBVR_SOT23-5~D@
ICH_RST_AUDIO#<21>
ICH_SYNC_AUDIO<21>
ICH_SDOUT_AUDIO<21>
SPK_SHUTDOWN#<26,27>
SPDIF_SHDN<19,34>
22P for
Crystal Only
C246
@
1 2
22P_0402_50V8J~D
C245
@
1 2
22P_0402_50V8J~D
R220
0_0402_5%~D
5
4
+3VRUN
2
2
C544
C545
1
0.1U_0402_16V4Z~D
C197 820P_0603_50V7K~D
1 2
C196 820P_0603_50V7K~D
1 2
C198 0.1U_0402_16V4Z~D
1 2
@
SPDIF<19>
EAPD<26>
12
C541
1
0.1U_0402_16V4Z~D
@
R_ICH_AC_BITCLK
R_ICH_AC_SDIN0
AFLT1
AFLT2
VREFOUT
AC97VREFI
CAP2
SPK_SHUTDOWN#
SPDIF_SHDN
SPDIF
EAPD
12
R215
10K_0402_5%~D
XTL_24M-
X5
24.576 MHz_20P_1BX24576CC1A~D
@
PACKAGE : 8X4.5X1.5mm
1 2
XTL_24M+
XTL_24M-
W=30 mil
2
1
2.2U_0805_10V6K~D
R214
1K_0402_5%~D@
1 2
1 2
R212
1K_0402_5%~D@
4
C92
0.1U_0402_16V4Z~D@
12
1
2
11
10
5
6
8
29
30
28
27
32
43
44
48
47
31
33
34
46
45
3
2
R221
0_0402_5%~D
VDDA=3.3V
U19
RESET#
SYNC
SDATA_OUT
BIT_CLK
SDATA_IN
AFLT1
AFLT2
VREFOUT
VREF
CAP2
GPIO0/NC
GPIO1/NC
SPDIF
EAPD
NC/BPCFG
NC/FLTIN
NC/FLTOUT
CID1
CID0
XTL_OUT
XTL_IN
+3VRUN
L25
BLM31A260SPT_1206~D
23
24
18
19
20
14
15
CNB_MICIN
21
22
16
17
9750_PHONE
13
PC_BEEP
12
HP_OUT_L
39
HP_COMM
40
HP_OUT_R
41
37
35
36
3
SPKR<22>
SN74LVC2G86DCTR_SSOP8~D
45
2
31
C252
1 2
2
C251
1000P_0402_50V7K~D
1
@
Pin46
CID1
Pin45
CID0
OPENOPEN
OPEN
1K
OPEN
1K
1K1K
Compal Electronics, Inc.
AC97 CODEC
25 50, 12, 2004
1
Pin3
XTL_OUT
GND
GND
GND
GND
0.2
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5
U18
SHDNR#
SHDNL#
INR
INL
C1P
C1N
PVss
5
1
C204
2
13
D
Q41
S
2N7002_SOT23~D
19
PVDD
+3VRUN
10
SVDD
SVss
7
1 2
1 2
1 2
1 2
PGND
2
NB_MUTE<34>
17
C264
0.01U_0402_16V7K~D
C260
0.01U_0402_16V7K~D
C271
0.01U_0402_16V7K~D
C563
0.01U_0402_16V7K~D
+3VRUN
12
R216
10K_0402_5%~D
D D
C223
+5VRUN
12
R218
10K_0402_5%~D
12
R223
10K_0402_5%~D@
2
G
1U_0603_10V4Z~D
1U_0603_10V4Z~D
+3VRUN
5
HP_OUT_R<25>
HP_OUT_L<25>
C C
AUD_GAIN0
AUD_GAIN1
B B
SPK_SHUTDOWN#<25,27>
A A
EAPD<25>
1 2
1 2
C216
1
C221
1U_0603_10V4Z~D
2
Gain Setting
R447
100K_0402_5%~D
1 2
13
D
Q43
S
2N7002_SOT23~D
AUD_LINE_IN_R
AUD_LINE_IN_L
12
R231
10K_0402_5%~D@
12
R236
10K_0402_5%~D
HP_NB_SENSE
1U_0603_10V4Z~D
AUD_LINE_OUT_R<25>
AUD_LINE_OUT_L<25>
14
18
15
13
1
3
2
G
4
1
C229
1U_0603_10V4Z~D
2
HP_SPK_R1HP_NB_SENSE
11
OUTR
HP_SPK_L1
9
OUTL
4
NC-4
6
NC-6
8
NC-8
12
NC-12
16
NC-16
20
NC-20
SGND
MAX4411ETP-T_TQFN20~D
13
D
2
G
S
4
BLM11A121S_0603~D
BLM11A121S_0603~D
1
C573
0.1U_0402_16V4Z~D
2
U21
7
RIN+
17
RIN-
9
LIN+
5
LIN-
19
SHUTDOWN
Q45
2N7002_SOT23~D
L79
L77
LINE OUT
W=40mils
HP_NB_SENSE<34>
HP_SPK_R2
12
HP_SPK_L2
12
+5VRUN
+5VAMPVCC
16
15
6
VDD
PVDD1
PVDD2
GND41GND311GND213GND1
TPA6017A2PWPR_TSSOP20~D
20
2
C458
C500
1
100P_0402_50V8J~D
D11
DA204U_SOT323~D
1
@
2
3
L84
1 2
BLM21AF121SN1D_0805~D
2
GAIN0
3
GAIN1
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
12
NC
10
BYPASS
3
JAUDO
1
2
6
3
4
2
1
100P_0402_50V8J~D
1
C269
10U_0805_10V4M~D
2
AUD_GAIN0
AUD_GAIN1
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
BYPASS
5
FOX_JA6333L-1ST-TR
NB_MICIN<25>
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
D10
DA204U_SOT323~D
1
@
2
3
+5VRUN
D13
DA204U_SOT323~D
1
@
2
3
1
C272
0.1U_0402_16V4Z~D
2
INT_SPK_R2
D12
DA204U_SOT323~D
1
@
2
3
1
C572
0.1U_0402_16V4Z~D
2
Added new
Amplifier, same as
Nimitz
1
C276
0.47U_0603_16V7K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C283
0.1U_0402_16V4Z~D
@
2
R449
1 2
100_0402_5%~D
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
2
BLM11A121S_0603~D
1
C533
100P_0402_50V8J~D
2
4
3
2
1
2
C534
BLM11A121S_0603~D
L81
EMICIN
12
C507
60milsingleend
connectionnear JACK
TRACE>15 mil
JSPK
4
3
2
1
E&T_3801-04
1
+5VRUN
12
R465
1.33K_0603_1%~D
12
1
R464
2K_0402_5%
2
L83
4.7U_0805_10V4Z~D
2
C539
1
100P_0402_50V8J~D
100P_0402_50V8J~D
12
100P_0402_50V8J~D
2
1
C517
1 2
JMIC
1
2
6
3
4
5
FOX_JA6333L-1ST-TR
COINCELL
COINCELL
1
2
E&T_3801-02~D
Place close to connector
INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1
@
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C630
C632
C631
2
2
GAIN0 INPUTAV(inv)GAIN1
0
0
1
*
6dB
0
10dB
1
15.6dB
0
21.6dB
11
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Amplifier and Phone Jack
LA-2171
1
JCOIN
1
2
@
0.1U_0402_16V4Z~D
1
1
C633
2
2
IMPEDANCE
90K ohm
70K ohm
45K ohm
25K ohm
26 50, 12, 2004
@
0.1U_0402_16V4Z~D
0.2
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5
COEX2_WLAN_ACTIVE<33>
D D
COEX1_BT_ACTIVE<33>
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
T17
PAD~D
BT_ACTIVE<37>
HW_RADIO_DIS#<33,35>
USBP2_D-<28>
USBP2_D+<28>
HW_RADIO_DIS#
COEX3
USBP2_DÂUSBP2_D+
Place near BT
GAIN0 GAIN1 Amplifier gain(db) INPUT
0
0
1
1
0
1 1
C C
AUD_MONO_OUT<25>
SUB_VREF
B B
SUB_VREF
12
SUB_GAIN0
SUB_GAIN1
A A
12
12dB
18dB0
23.6dB
36dB
C637
1 2
0.056U_0603_10V7K~D
1
C636
1U_0805_25V4Z~D
2
Gain Setting
R537
100K_0402_5%~D
R538
100K_0402_5%~D@
5
C635
1000P_0402_50V7K~D
1 2
C634
0.22U_0603_10V7K~D
1 2
R539
1 2
1.21K_0603_1%~D
12
R535
100K_0402_5%~D
12
R536
100K_0402_5%~D@
IMPEDANCE
241K ohm
168K ohm
104K ohm
33K ohm
1
C628
2
SUB_SHUTDOWN#
C629
1 2
0.22U_0603_10V7K~D
SUB_GAIN0
SUB_GAIN1
1U_0805_25V4Z~D
1
C627
2
1U_0805_25V4Z~D
C626
1 2
12
220P_0402_50V7K~D
1
C381
@
1000P_0402_50V7K~D
2
1
C380
1000P_0402_50V7K~D@
2
4
+3VRUN
C379
1 2
0.1U_0402_16V4Z~D
JBT
1
2
3
4
5
6
7
8
9
1U_0805_25V4Z~D
2
1
PGND
6
E&T_3702-10-1~D
10U_1210_25V6K~D
1
C615
2
PGND12PGND
13
R349
1 2
0_0805_5%~D
R346
1 2
0_0805_5%~D
101112
+15V
C646
AGND18AGND
1
+
2
TPA3001D1PWP_TSSOP24~D
19
12
R345
10K_0402_5%~D
C625
U33
24
VCC
5
SHDN
1
INN
2
INP
3
GAIN0
4
GAIN1
7
VCLAMP
23
VREF
22
BYPASS
21
COSC
20
ROSC
R534
120K_0402_5%~D
SUBOUT2 SUBOUT1
4
150U_4B_16VM~D
SUBOUT1
SUBOUT2
SUB_DETECT#
BSN
PVCC
OUTN
OUTN
OUTP
OUTP
PVCC
BSP
SUB_OUT2
SUB_OUT1SUBOUT1
ICH_SDOUT_MDC
ICH_SYNC_MDC
ICH_RST_MDC#
8
9
11
10
14
15
16
17
+15V
1U_0805_25V4Z~D
+15V
ICH_AC_SDIN1<21>
4
3
2
1
C623
1 2
C624
1 2
1U_0805_25V4Z~D
+15V
C273
10P_0402_50V8J~D@
1 2
C281
10P_0402_50V8J~D@
1 2
C280
10P_0402_50V8J~D@
1 2
JWOFR
4
3
2
1
E&T_3801-04
R532
1 2
51_0603_1%~D
R531
1 2
51_0603_1%~D
3
ICH_SDOUT_MDC<21>
R202
1 2
33_0402_5%~D
SUB_DETECT#<34>
0.22U_1206_25V7M~D
0.22U_1206_25V7M~D
1
2
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3VRUN
12
R155
C621
1 2
D6
2 1
B130-13_SMA~D
D7
2 1
B130-13_SMA~D
C622
1 2
D8
DA204U_SOT323~D
@
3
ICH_SYNC_MDC<21>
ICH_RST_MDC#<21>
SPK_SHUTDOWN#<25,26>
10K_0402_5%~D
2
G
MDC_SDIN
10K_0402_5%~D
12
R144
13
D
Q12
2N7002_SOT23~D
S
L64
1 2
BLM21PG600SN1D_0805~D
L65
1 2
BLM21PG600SN1D_0805~D
SUBOUT2
1
D9
DA204U_SOT323~D
@
2
3
+3VRUN
5
1
P
B
2
A
G
3
JMDC
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
U11
SUB_SHUTDOWN#
4
O
TC7SH08FU_SSOP5~D
AUD_MONO_OUT<25>
SUB_OUT1
1
C377
1000P_0402_50V7K~D
2
1
C378
1000P_0402_50V7K~D
2
SUB_OUT2
2
W=20 mil
IAC_BITCLK
131314141515161617171818191920
SUB_SHUTDOWN#
2
2
RES0
4
RES1
6
3.3V
8
GND3
10
GND4
12
TYCO_1-179397-2~D
20
MDC_AC_BITCLK <25>
Connector for MDC Rev1.5
+15V
150U_4B_16VM~D@
150U_4B_16VM~D@
1
1
C354
C372
C619
+
+
2
2
15
+3VRUN
8
P
A3Y
G
4
16
18
17
5
U10C
SN74LVC3G14DCTR_SSOP8~D@
1 2
0.47U_0603_16V7K~D@
C616
MODE
1
ICH_SDOUT_MDC
MDC_AC_BITCLK
@
4.7K_0402_5%~D
@
15K_0402_5%
R12
0_0805_5%~D@
1 2
1 2
R79
0_0805_5%~D@
@
1U_0805_25V4Z~D
C645
2
1
R205
C201
10_0402_5%~D@
10P_0402_50V8J~D@
MODE
1 2
MDC_AC_BITCLK_TERM
2
1
SUBOUT2
SUBOUT1
150U_4B_16VM~D@
1
C353
+
2
U31
VP1
VP2
3
IN1+
IN2-
MODE
5
SVRR
TDA1517ATW_HTSSOP20~D@
R541
1 2
@
1K_0402_5%~D
+3VSUS
1
4.7U_0805_10V4Z~D
DTC144EKA_SOT23~D@
2
8
9
12
13
11
10
4
1
2
6
7
14
19
20
C219
SUB_OUT2_P
SUB_OUT1_N
13
1
2
0.1U_0402_16V4Z~D
+15V
12
R521
12
R514
C224
150U_4B_16VM~D@
0.1U_0603_25V7K~D@
1
C617
1
+
2
2
OUT1A
OUT1B
OUT2A
OUT2B
PGND2
PGND1
SGND
NC1
NC2
NC3
NC4
NC5
NC6
NC7
2
Q51
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
SUBWOOFER,BT PORTand MDC
LA-2171
27 50, 12, 2004
1
R213
1 2
10_0402_5%~D@
ICH_AC_SDOUT_MDCTERM
2
C235
10P_0402_50V8J~D@
1
0.2
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5
L69 DLW21SN900SQ2_0805~D@
USBP0+<22>
USBP0-<22>
D D
C C
B B
A A
USBP1+<22>
USBP1-<22>
USBP2-<22>
USBP2+<22>
CBS_CAD15<31>
CBS_CAD13<31>
USBP4-<22>
USBP4+<22>
USBP5-<22>
USBP5+<22>
USBP6-<22>
USBP6+<22>
USBP7-<22>
USBP7+<22>
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
L41 DLW21SN900SQ2_0805~D@
1
4
L59 DLW21SN900SQ2_0805~D@
1
4
L38 DLW21SN900SQ2_0805~D@
1
4
L72 DLW21SN900SQ2_0805~D@
1
4
L8 DLW21SN900SQ2_0805~D@
1
4
L40 DLW21SN900SQ2_0805~D@
1
4
L43 DLW21SN900SQ2_0805~D@
1
4
R361
0_0402_5%~D
1 2
R360
0_0402_5%~D
1 2
R245
0_0402_5%~D
1 2
R246
0_0402_5%~D
1 2
R341
0_0402_5%~D
1 2
R342
0_0402_5%~D
1 2
R237
0_0402_5%~D
1 2
R238
0_0402_5%~D
1 2
R366
0_0402_5%~D
1 2
R365
0_0402_5%~D
1 2
R10
0_0402_5%~D
1 2
R9
0_0402_5%~D
1 2
R243
0_0402_5%~D
1 2
R247
0_0402_5%~D
1 2
R268
0_0402_5%~D
1 2
R269
0_0402_5%~D
1 2
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
1
C277
47P_0402_50V8J~D
2
@
1
C282
47P_0402_50V8J~D
2
@
1
C395
47P_0402_50V8J~D
2
@
1
C274
47P_0402_50V8J~D
2
@
1
C14
47P_0402_50V8J~D
2
@
1
C374
47P_0402_50V8J~D
2
@
1
C262
47P_0402_50V8J~D
2
@
1
C388
47P_0402_50V8J~D
2
@
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
USBP0_D+
USBP0_D-
C265
47P_0402_50V8J~D
@
USBP1_D+
USBP1_D-
C286
47P_0402_50V8J~D
@
USBP2_D-
USBP2_D+
C394
47P_0402_50V8J~D
@
CBS_CAD15_L
CBS_CAD13_L
C275
47P_0402_50V8J~D
@
USBP4_D-
USBP4_D+
C13
47P_0402_50V8J~D
@
USBP5_D-
USBP5_D+
C375
47P_0402_50V8J~D
@
USBP6_D-
USBP6_D+
C263
47P_0402_50V8J~D
@
USBP7_D-
USBP7_D+
C387
47P_0402_50V8J~D
@
PLACE CHOKE
NEAR
CONNECTOR
USBP2_D- <27>
USBP2_D+ <27>
USBP4_PWR
CBS_CAD15_L <32>
CBS_CAD13_L <32>
USBP5_PWR
USBP6_PWR
BLM21PG600SN1D_0805~D
USBP7_PWR
BLM21PG600SN1D_0805~D
1 2
BLM21PG600SN1D_0805~D
1 2
1 2
BLM21PG600SN1D_0805~D
1 2
BLM21PG600SN1D_0805~D
BLM21PG600SN1D_0805~D
L9
L10
L12
L7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
3
L36
BLM21PG600SN1D_0805~D
1 2
L39
1 2
1 2
L42
1 2
L44
BLM21PG600SN1D_0805~D
1
+
C21
C15
2
150U _D2_6.3VM~D
1
+
C19
C16
2
150U _D2_6.3VM~D
+5VSUS
1
C261
2
+5VSUS
1
C47
2
+5VSUS
1
C279
2
1
C250
2
150U _D2_6.3VM~D
1
C278
2
150U _D2_6.3VM~D
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
C259
10U_1206_16V4Z~D
2
1
C41
10U_1206_16V4Z~D
2
1
C285
10U_1206_16V4Z~D
2
+
+
USB_BACK_EN#<34>
USB_SIDE_EN#<34>
USB_SIDE_EN#<34>
1
C575
2
0.1U_0402_16V4Z~D
1
C576
2
0.1U_0402_16V4Z~D
USBP4_VCC
USBP4_DÂUSBP4_D+
USBP4_GND
USBP5_VCC
USBP5_DÂUSBP5_D+
USBP5_GND
USBP6_VCC
USBP6_DÂUSBP6_D+
USBP6_GND
USBP7_VCC
USBP7_DÂUSBP7_D+
USBP7_GND
JUSB2
A1
A_VCC
A2
A_D-
A3
A_D+
A4
A_GND
B1
B_VCC
B2
B_D-
B3
B_D+
B4
B_GND
9
G1
10
G2
11
G3
12
G4
FOX_UB11123-8Z4-HT~D
USB_BACK_EN#
USB_SIDE_EN#
USB_SIDE_EN#
2
JUSB3
8
8
7
7
6
6
5
5
10
10
9
9
4
4
3
3
2
2
1
1
JST_SM8B-SRSS~D
USBP0_PWR
USBP1_PWR
U20
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
U2
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
U22
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
L1
BLM21PG600SN1D_0805~D
1 2
L2
BLM21PG600SN1D_0805~D
1 2
1 2
L14
BLM21PG600SN1D_0805~D
1 2
L17
BLM21PG600SN1D_0805~D
USB_OC6#
8
OC1#
7
OUT1
6
OUT2
USB_OC7#
5
OC2#
USB_OC4#
8
OC1#
7
OUT1
6
OUT2
USB_OC5#
5
OC2#
USB_OC0#
8
OC1#
7
OUT1
USB_OC1#
6
OUT2
5
OC2#
USB PORT#
0
1
2
3
4
5
6
7
C12
150U _D2_6.3VM~D
C88
150U _D2_6.3VM~D
USB_OC6# <22>
USBP6_PWR
USBP7_PWR
USB_OC7# <22>
USB_OC4# <22>
USBP4_PWR
USBP5_PWR
USB_OC5# <22>
USB_OC0# <22>
USBP0_PWR
USB_OC1# <22>
USBP1_PWR
1
DESTINATION
JUSB1 (Top)
JUSB1 (Bottom)
BlueTooth
NEW CARD
JUSB2 (Top)
JUSB2 (Bottom)
JUSB3 (Top)
JUSB3 (Bottom)
1
1
+
C7
2
2
0.1U_0402_16V4Z~D
1
+
C87
2
0.1U_0402_16V4Z~D
USBP0_VCC
USBP0_DÂUSBP0_D+
USBP1_VCC
USBP1_DÂUSBP1_D+
USBP1_GND
1
2
USBP0_GND
JUSB1
A1
A_VCC
A2
A_D-
A3
A_D+
A4
A_GND
B1
B_VCC
B2
B_D-
B3
B_D+
B4
B_GND
9
G1
10
G2
11
G3
12
G4
FOX_UB11123-8Z4-HT~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
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DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
USB 2.0 PORT
LA-2171
28 50, 12, 2004
1
0.2
5
+3VSRC
D
6
S
VAUX_LAN
45
2
Q13
1
G
SI3456DV-T1_TSOP6~D
L13
1 2
3
C70
2
1
ENAB_3VLAN<38>
D D
Note: Place these components
as closeto the chip aspossible.
V_1P2_LAN
BLM11A601S_0603~D
L28
1 2
BLM31A260SPT_1206~D
V_1P2_PLLVDD_PHY
2.2U_0805_10V6K~D
0.1U_0402_16V4Z~D
C71
2
1
C113
2
1
+3V_LOM_PCI
10U_0805_10V4M~D
C55
0.1U_0402_16V4Z~D
4.7U_0805_10V4Z~D
C76
2
2
1
1
0.1U_0402_16V4Z~D
C80
2
1
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C103
C59
2
1
0.1U_0402_16V4Z~D
C63
C108
2
1
0.1U_0402_16V4Z~D
C104
C56
2
1
2
1
2
2
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C73
2
1
V_3P3_LAN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C82
2
1
V_3P3_LAN
LAN_CTRL_2P5V
BCP69_SOT223~D@
B
1
BCP69
C
2
C1E
4
Q38
3
V_2P5_LAN
LAN_CTRL_1P2V
3
0.1U_0402_16V4Z~D
10U_0805_10V4M~D
C411
C421
2
2
3
2
4
1
1
@
@
4.7U_0805_10V4Z~D
10U_0805_10V4M~D
C33
C22
C60
2
2
1
1
1
Q36
BCP69_SOT223~D@
@
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C61
C68
2
2
1
2
1
1
3
2
@
0.1U_0402_16V4Z~D
C404
4
C45
V_2P5_LAN
@
4.7U_0805_10V4Z~D
C402
2
1
10U_0805_10V4M~D
2
C27
1
2
@
0.1U_0402_16V4Z~D
2
1
10U_0805_10V4M~D
2
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
C46
C48
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C37
C36
1
0.1U_0402_16V4Z~D
2
2
C105
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C29
1
0.1U_0402_16V4Z~D
2
2
C43
C91
C31
1
1
1
V_1P2_LAN
0.1U_0402_16V4Z~D
2
C30
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C32
1
0.1U_0402_16V4Z~D
2
2
C50
C34
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
C35
1
1
For 5705M only
PCI_AD[0..31]<20,31,33>
C C
B B
V_3P3_LAN
A A
PCI_AD16
1K_0402_5%~D@
1 2
PCI_C_BE3#<20,31,33>
PCI_C_BE2#<20,31,33>
PCI_C_BE1#<20,31,33>
PCI_C_BE0#<20,31,33>
100_0402_5%~D
1 2
PCI_FRAME#<20,31,33>
PCI_IRDY#<20,31,33>
PCI_TRDY#<20,31,33>
PCI_DEVSEL#<20,31,33>
PCI_STOP#<20,31,33>
PCI_PERR#<20,31,33>
PCI_SERR#<20,31,33>
PCI_PAR<20,31,33>
CK_33M_LANPCI<6>
PCI_PIRQC#<20,31>
PLTRST_LOM#<20>
PCI_GNT4#<20>
PCI_REQ4#<20>
R35
R39
4.7K_0402_5%~D
SYS_PME#<31,33,34>
R130
10_0402_5%~D@
12
5
R128
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
LAN_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
CK_33M_LANPCI
PCI_PIRQC#
PLTRST_LOM#
PCI_GNT4#
PCI_REQ4#
LAN_AUXPWR
SYS_PME#
CLK_82540_TERMCK_33M_LANPCI
12
B8
A8
C7
C6
B6
B5
A5
B4
B2
B1
C1
D3
D2
D1
E3
K1
L2
L1
M3
M2
M1
N2
N3
P3
N4
P4
M5
N5
P5
P6
M7
N7
C4
F3
L3
M4
A4
F2
F1
G3
H3
H1
J2
A2
J1
A3
H2
C2
J3
C3
J12
F4
A6
C114
1 2
8.2P_0402_50V8J~D@
U5A
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
BCM4401
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CBE3
CBE2
CBE1
CBE0
IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
PCI_CLK
INTA
PCI_RST
GNT
REQ
VAUXPRSNT
M66EN
PME
BCM4401KFB_FBGA196~D
REGSUP12
REGCTL12
REGSEN12
REGSUP25
REGCTL25
REGSEN25
EEDATA
LINKLEDB
SPD100LEDB
SPD1000LEDB
TRAFFICLEDB
PLLVDD2
XTALVDD
BIASVDD
SMB_CLK
SMB_DATA
4
E13
TRD3+
E14
TRD3-
D13
TRD2+
D14
TRD2-
C13
TRD1+
C14
TRD1-
B13
TRD0+
B14
TRD0-
B9
LAN_CTRL_1P2V
B10
A9
B11
LAN_CTRL_2P5V
C11
C10
P1
VESD1
G2
VESD2
A1
VESD3
LAN_EEDATA_SPROM_CS
P10
LAN_EECLK_SPROM_CLK
M10
EECLK
H12
GPIO0
LAN_EEPROM_W
K13
GPIO1
J13
GPIO2
LINK_10#
G13
LINK_100#
H13
G12
LAN_ACT#
G14
V_1P2_PLLVDD_PHY
H14
P7
NC
C12
TCK
D12
TDI
B12
TDO
A12
TMS
LAN_TRST#
D11
TRST
J14
XTALO
N10
XTALO
XTALI
SCLK
RDAC
XTALI
N11
G11
SO
E10
SI
E11
H11
CS
LAN_BIAS
A14
LAN_RDAC
D10
A10
C9
R136
for 4401 :1.27K
for 5705M:1.24K
LAN_TX3+
LAN_TX3ÂLAN_TX2+
LAN_TX2ÂLAN_TX1+
LAN_TX1ÂLAN_TX0+
LAN_TX0-
R135
4.7K_0603_1%~D
R30
0_0402_5%~D
1 2
C25
27P_0402_50V8J
LAN_TX3+ <30>
LAN_TX3- <30>
LAN_TX2+ <30>
LAN_TX2- <30>
LAN_TX1+ <30>
LAN_TX1- <30>
LAN_TX0+ <30>
LAN_TX0- <30>
V_2P5_LAN
V_1P2_LAN
V_3P3_LAN
V_2P5_LAN
+3V_LOM_PCI
LINK_10# <30>
LINK_100# <30>
LAN_ACT# <30>
12
V_2P5_LAN
2
25MHz_20P_1BX25000CK1A~D
1
12
R136
1.27K_0603_1%~D
V_1P2_LAN
U5B
E12
VDDC_E12
H5
VDDC_H5
H6
VDDC_H6
H7
VDDC_H7
H8
VDDC_H8
J5
VDDC_J5
J6
VDDC_J6
J7
VDDC_J7
J8
VDDC_J8
J9
VDDC_J9
J10
VDDC_J10
K5
VDDC_K5
K6
VDDC_K6
K7
V_3P3_LAN +3VRUN
@
BLM11A601S_0603~D
BLM11A601S_0603~D
12
12
L26
L27
+3V_LOM_PCI
Note: Place these components
as closeto the chip aspossible.
X1
12
2
C26
27P_0402_50V8J
2
C109
1000P_0402_50V7K~D
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
CLKRUN#<22,31,33,34>
L22
BLM11A601S_0603~D
1 2
3
0_0402_5%~D
1 2
V_2P5_LAN
Note: Place these components
as closeto the chip aspossible.
V_2P5_LAN
V_3P3_LAN
R77
10U_0805_10V4M~D
2
C58
1
5705M_CLOCKRUN
VDDC_K7
K8
VDDC_K8
K9
VDDC_K9
K10
VDDC_K10
L5
VDDC_L5
L10
VDDC_L10
M14
VDDC_M14
N14
VDDC_N14
P8
VDDC_P8
P12
VDDC_P12
P13
VDDC_P13
P14
VDDC_P14
A7
VDDIO-PCI_A7
B3
VDDIO-PCI_B3
C5
VDDIO-PCI_C5
E1
VDDIO-PCI_E1
E4
VDDIO-PCI_E4
G1
VDDIO-PCI_G1
K3
VDDIO-PCI_K3
L4
VDDIO-PCI_L4
N6
VDDIO-PCI_N6
P2
VDDIO-PCI_P2
K14
VDDP_K14
L13
VDDP_L13
P11
VDDP_P11
A11
VDDIO_A11
F11
VDDIO_F11
K12
VDDIO_K12
L12
VDDIO_L12
C8
CSTSCHG
H4
CLKRUN
H10
NC_H10
J4
NC_J4
K4
NC_K4
J11
NC_J11
K11
NC_K11
L7
NC_L7
L8
NC_L8
BCM4401KFB_FBGA196~D
BCM4401
LOW_POWER
2
VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9
VSS_F10
VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9
VSS_G10
VSS_H9
VSS_K2
VSS_L6
VSS_L9
VSS_M6
VSS_M12
VSS_M13
VSS_N1
VSS_N12
VSS_N13
AVDDL_F12
AVDDL_F13
AVDD_F14
AVDD_A13
NC_L11
NC_L14
NC_M8
NC_M9
NC_N8
NC_N9
NC_P9
12
R72
B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13
F12
F13
F14
A13
R540
LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS
LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_SPROM_DOUT
LAN_SPROM_DIN
AVDD1P2
AVDD2P5
1U_0603_10V4Z~D
C86
For 4401 only
R540
L11
1 2
L14
0_0402_5%~D
M8
M9
5705M_LOWPWR
M11
N8
NC_LAN_N9
N9
P9
R32 0_0402_5%~D
NC_LAN_P9
R34 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
LA-2171
Date: Sheet of
R69
10K_0402_5%~D
AT93C46-10SI-2.7_SO8~D
BLM11A601S_0603~D
1 2
1 2
0.1U_0402_16V4Z~D
2
2
C102
1
1
R29
0_0402_5%~D@
1 2
1 2
1 2
Compal Electronics, Inc.
LAN Controller (BCM4401)
@
1K_0402_5%~D
12
12
R60
4.7K_0402_5%~D@
U3
1
CS
2
SK
3
DI
4
DO
L18
L23
BLM11A601S_0603~D
@
@
1
V_3P3_LAN
C52
U6
8
VCC
7
WP
6
SCL
5
SDA
AT24C256_SO8~D@
8
VCC
7
NC
6
ORG
5
GND
V_1P2_LAN
V_2P5_LAN
LAN_LOW_PWR <35>
LAN_SPROM_DOUT
LAN_SPROM_DIN
29 50, 12, 2004
@
2
1
0.1U_0402_16V4Z~D
GND
V_3P3_LAN
Z2702
1
A0
2
A1
3
NC
4
10K_0402_5%~D
12
R33
0.01U_0402_16V7K~D
2
C24
1
0.2
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5
D D
LAN_TX0+<29>
LAN_TX0-<29>
LAN_TX1+<29>
LAN_TX1-<29>
LAN_TX2+<29>
LAN_TX2-<29>
LAN_TX3+<29>
LAN_TX3-<29>
C C
4
Layout Notice : Place
termination asclose as
chip as possible
@
@
49.9_0603_1%~D
49.9_0603_1%~D
R23
R24
1 2
1 2
@
0.1U_0402_16V4Z~D
2
C40
1
@
@
49.9_0603_1%~D
49.9_0603_1%~D
R22
R21
1 2
1 2
@
0.1U_0402_16V4Z~D
2
C39
1
49.9_0603_1%~D
49.9_0603_1%~D
R27
R28
C28
R25
1 2
1 2
2
1
1 2
0.1U_0402_16V4Z~D
2
C38
1
3
V_2P5_LAN
LAN_ACTLED_YEL#
49.9_0603_1%~D
49.9_0603_1%~D
R26
1 2
0.1U_0402_16V4Z~D
LED_10_GRN#
LED_100_ORG#
C397 0.01U_0402_16V7K~D
C398 0.01U_0402_16V7K~D
C399 0.01U_0402_16V7K~D
1
2
C396 0.01U_0402_16V7K~D
1
1
1
2
2
2
2
V_3P3_LAN
200_0402_5%~D
200_0402_5%~D
12
12
R52
R377
13
14
11
12
10
4
6
5
3
1
2
8
7
9
16
17
15
Place these caps as close
to the center tap pins
of the mag/connector.
JLOM
YELLOW
COMMON0
TRD1P
TRCT1
TRD1N
TRD2P
TRCT2
TRD2N
TRD3P
TRCT3
TRD3N
TRD4P
TRCT4
TRD4N
COMMON1
GREEN
ORANGE
TYCO_1368398-1~D
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
4 X 75 OHMS
1000pF 2KV
1
TRP1P
TRP1N
TRP2P
TRP2N
TRP3P
TRP3N
TRP4P
TRP4N
SHIELD018SHIELD1
202021
19
21
B B
R352
10K_0402_5%~D
1 2
R353
1 2
0_0402_5%~D
A A
LINK_10#<29> LINK_100#<29>LAN_ACT#<29>
V_3P3_LAN V_3P3_LANV_3P3_LAN
1 2
R350
10K_0402_5%~D
R351
1 2
0_0402_5%~D
R355
10K_0402_5%~D
1 2
LED_10_GRN# LED_100_ORG#LAN_ACTLED_YEL#
R354
1 2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
LAN Transfomer and RJ45
LA-2171
1
30 50, 12, 2004
0.2
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5
PCI_AD[0..31]<20,29,33>
D D
PCI_C_BE3#<20,29,33>
PCI_C_BE2#<20,29,33>
PCI_C_BE1#<20,29,33>
PCI_C_BE0#<20,29,33>
PCI_PAR<20,29,33>
PCI_FRAME#<20,29,33>
PCI_TRDY#<20,29,33>
C C
B B
PCI_AD17 CBS_IDSEL
+3VRUN
CLKRUN#<22,29,33,34>
+3VSUS
PCI_IRDY#<20,29,33>
PCI_STOP#<20,29,33>
PCI_DEVSEL#<20,29,33>
1 2
PCI_PERR#<20,29,33>
PCI_SERR#<20,29,33>
PCI_REQ1#<20>
PCI_GNT1#<20>
CK_33M_CBPCI<6>
PCIRST_CB#<20,33>
R74 10K_0402_5%~D
1 2
R185 10K_0402_5%~D@
1 2
R183 0_0402_5%~D@
1 2
PCI_PIRQD#<20,33>
PCI_PIRQC#<20,29>
PCI_PIRQB#<20,33>
+3VSUS
R194 10K_0402_5%~D
1 2
R190 10K_0402_5%~D
1 2
R333 10K_0402_5%~D
+3VSUS
1 2
SYS_PME#<29,33,34>
CBS_SPK<25>
CB_HWSPND#<34>
R193 100K_0402_5%~D
1 2
R192100_0402_5%~D
IRQ_SERIRQ<22,34>
CBS_SPK
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_REQ1#
PCI_GNT1#
PCIRST_CB#
CBS_GRST#
M2
M1
N5
N4
N2
N1
P5
P4
R4
R2
R1
T2
T1
U2
U1
V1
T7
V7
W7
R8
T8
V8
W8
R9
V9
W9
T11
V11
W11
T12
V12
W12
P2
W2
W6
T9
V6
V3
W4
V4
V5
T5
P1
W5
T6
M4
M5
K1
L4
G2
L5
J2
K4
K2
J4
H1
H2
H4
H5
G1
G4
F1
F2
F4
LayoutNote: Placecloseto R5C841
IEEE1394_TPBIAS0
CK_33M_CBPCI
@
10_0402_5%~D
12
R196
@
A A
4.7P_0402_50V8C~D
CK33M_CBS_TERM
C171
2
1
+3VSUS
R186
C657
12
1
2
5
100K_0402_5%~D
CBS_GRST#
1U_0603_10V4Z~D
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
56.2_0603_1%~D
12
R229
12
R241
C284
12
R239
56.2_0603_1%~D
12
R244
Z3008
270P_0402_50V7K~D
R261
2
1
1 2
U17A
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3#
C/BE2#
C/BE1#
C/BE0#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
PCICLK
PCIRST#
GBRST#
CLKRUN#
INTA#
INTB#
INTC#
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
RI_OUT#/PME#
SPKROUT
HWSPND#
TEST
R5C841_PBGA208~D
0.01U_0402_16V7K~D
56.2_0603_1%~D
C243
1
2
56.2_0603_1%~D
5.1K_0603_1%~D
4
R5C841
CSTSCHG/BVD1(STSCHG#/RI#)
0.33U_0603_10V7K~D
C290
1
2
4
CAD31/CDATA10
CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0
CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6
CAD19/CADR25
CAD18/CADR7
CAD17/CADR24
CAD16/CADR17
CAD15/IOWR#
CAD14/CADR9
CAD13/IORD#
CAD12/CADR11
CAD11/OE#
CAD10/CE2#
CAD9/CADR10
CAD8/CDATA15
CAD7/CDATA7
CAD6/CDATA13
CAD5/CDATA6
CAD4/CDATA12
CAD3/CDATA5
CAD2/CDATA11
CAD1/CDATA4
CAD0/CDATA3
CC/BE3#/REG#
CC/BE2#/CADR12
CC/BE1#/CADR8
CC/BE0#/CE1#
CPAR/CADR13
CFRAME#/CADR23
CTRDY#/CADR22
CIRDY#/CADR15
CSTOP#/CADR20
CDEVSEL#/CADR21
RESERVED/CADR19
CPERR#/CADR14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CCLKRUN#/WP(IOIS16#)
CCLK/CADR16
CINT#/RDY(IREQ#)
CRST#/RESET
CAUDIO/BVD2(SPKR#/LED)
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#
RESERVED/CDATA14
RESERVED/CDATA2
RESERVED/CADR18
LayoutNote: Placecloseto 1394 CONN.
R227 0_0402_5%~D
R232 0_0402_5%~D
R240 0_0402_5%~D
R242 0_0402_5%~D
LayoutNote: ShieldGND for
IEEE1394_TPAand TPB
5
6
7
8
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
F16
K18
P15
V19
N15
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
M18
H19
F19
T14
D15
R16
H16
W18
C19
N16
5
6
7
8
857CM-0009~D@
1 2
1 2
1 2
1 2
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CPAR
CBS_CFRAME#
CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_INTERNAL
CBS_CINT#
CBS_CRST#
CBS_CAUDIO
CBS_CCD1#_INTERNAL
CBS_CCD2#_INTERNAL
CBS_CVS1
CBS_CVS2
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
L37
4
4
3
3
2
2
1
1
3
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <28>
CBS_CAD14 <32>
CBS_CAD13 <28>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
R230 47_0402_5%~D
CBS_CINT# <32>
CBS_CRST# <32>
CBS_CAUDIO <32>
CBS_CVS1 <32>
CBS_CVS2 <32>
CBS_RSVD/D14 <32>
CBS_RSVD/D2 <32>
CBS_RSVD/A18 <32>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LayoutNote: ShieldGND for
CBS_CAD13 and CBS_CAD15
CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>
12
CBS_CRST#
TPA0+
TPA0ÂTPB0+
TPB0-
3
C255
12
22P_0402_50V8J~D
C256
12
22P_0402_50V8J~D
LayoutNote: Placecloseto R5C841
and ShieldGND for these signals
2
C253
1
LayoutNote: ShieldGND for
CBS_CCLK_INTERNAL and CBS_CCLK
CBS_CCLK <32>
CBS_CCD2# <32>
0_0402_5%~D
270P_0402_50V7K~D
0.01U_0402_16V7K~D
1 2
@
C236
2
1
CBS_CCD1# <32>
R217
0_0402_5%~D
270P_0402_50V7K~D
J1394
4 5
3
6
2
1
R211
1 2
@
C218
2
1
C400
1
2
SUYIN_020115FR004S502ZL~D
R5C841XI
X4
24.576MHz_16P_1BG24576CKIA~D
1 2
R5C841XO
C234 0.01U_0402_16V7K~D
1 2
LayoutNote: ShieldGND
for USBP3+ and USBP3-
0.01U_0402_16V7K~D
10K_0603_1%~D
R191
1 2
VPPEN0<32>
VPPEN1<32>
VCC5EN#<32>
VCC3EN#<32>
USBP3+<22>
USBP3-<22>
2
LayoutNote: Placecloseto R5C841
and ShieldGND for SD_CLK
+3V_PHY
R5C841XI
R5C841XO
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
IEEE1394_TPBIAS0
100K_0402_5%~D
12
R188
R195
100K_0402_5%~D
12
U17B
D11
CPS
A16
XI
B16
XO
A14
FIL0
B12
TPAP0
A12
TPAN0
B13
TPBP0
A13
TPBN0
B10
TPAP1
A10
TPAN1
B11
TPBP1
A11
TPBN1
D12
TPBIAS0
D10
TPBIAS1
D13
VREF
B14
REXT
V14
USBDP
W14
USBDM
V13
VPPEN0
W13
VPPEN1
R13
VCC5EN#
T13
VCC3EN#
R7
REGEN#
R5C841_PBGA208~D
SD_EN
R5C841
10K_0402_5%~D
12
R543
+3VSUS
For RICHO R5C841 Review Control
REV. Date
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
2
Date: Sheet of
1
B1
MDIO00
A2
MDIO01
A3
MDIO02
B3
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
SD_EN
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
R73
B8
0_0402_5%~D
D8
E8
1 2
LayoutNote: ShieldGND for SD_CLK
U34
3
VIN
4
VIN/CE
2
GND
RT9701-CB_SOT23-5
VOUT
VOUT
1
+SD_VCC
5
12/18/030.1
Compal Electronics, Inc.
CardBus Controller(R5C841)
LA-2171
1
SD_DET# <32>
SD_WP <32>
SD_CMD <32>
SD_DATA0 <32>
SD_DATA1 <32>
SD_DATA2 <32>
SD_DATA3 <32>
SD_CLK <32>
31 50, 12, 2004
0.2
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5
+3VSUS
10U_0805_10V4M~D
0.01U_0402_16V7K~D
C176
C202
C206
1
1
2
10U_0805_10V4M~D
C164
1
2
+5VSUS
C156
2
+3VSUS
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
C241
C220
1
1
2
2
0.47U_0603_16V7K~D
0.01U_0402_16V7K~D
C652
C653
1
1
2
2
0.1U_0402_16V4Z~D
1
2
+3VRUN
D D
10U_0805_10V4M~D
C240
C239
1
2
C C
B B
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
2
0.01U_0402_16V7K~D
C225
C228
1
1
2
2
+3VSUS
C227
2
1
0.01U_0402_16V7K~D
C650
C651
1
2
0.1U_0402_16V4Z~D
C509
1
2
VPPEN0<31>
VPPEN1<31>
VCC3EN#<31>
VCC5EN#<31>
LayoutNote: Placecloseto SDCONN.
+SD_VCC
A A
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1
1
C648
C660
2
2
5
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C649
1
1
2
2
10U_0805_10V4M~D
C178
C200
1
2
0.01U_0402_16V7K~D
+3V_PHY
1
2
0.47U_0603_16V7K~D
U14
11
VCC3IN
13
VCC5IN
15
VCC5IN
3
EN0
4
EN1
2
VCC3_EN
1
VCC5_EN
5
FLG
16
GND
R5331V002-E2-FA_SSOP16~D
0.01U_0402_16V7K~D
C254
1
2
0.01U_0402_16V7K~D
1
2
VCCOUT
VCCOUT
VCCOUT
VPPOUT
NC
NC
NC
SD_DATA3<31>
SD_CMD<31>
SD_CLK<31>
SD_DATA0<31>
SD_DATA1<31>
SD_DATA2<31>
SD_DET#<31>
SD_WP<31>
+SD_VCC
R78
9
14
12
8
7
6
10
F5
G5
J19
K19
W3
R11
R12
A4
R6
E13
L1
E14
E10
E11
A17
B17
A9
B9
D9
D14
A15
B15
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
+SD_VCC
12
CBS_VPP
C355
33K_0402_5%~D
4
U17C
VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4
R5C841
VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3
VCC_MD3V
VCC_RIN1
VCC_RIN2
VCC_ROUT1
VCC_ROUT2
AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
R5C841_PBGA208~D
CBS_VCC+3VSUS
C351
1
2
0.1U_0402_16V4Z~D
1
2
1
2
3
4
5
6
7
8
9
10
11
12
4
0.1U_0402_16V4Z~D
JSD
CD/DAT3
CMD
VSS1
VDD
CLK
VSS2
GND1
DAT0
GND2
DAT1
GND3
DAT2
GND4
DETECT#
WP_VSS
WP
Molex_SD-67840-0002~D
3
L31
+3VSUS
L2
NC1
C1
NC2
D1
NC3
E1
NC4
C2
NC5
D2
NC6
E2
NC7
E4
NC8
E12
NC9
1 2
BLM21A601SPT_0805~D
22U_D2_6.3VM~D
1
C654
C177
1
+
2
2
2
+3V_PHY
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C179
1
2
1
1
C656
C655
2
2
1
Place close to JCBUS
CBS_VPP
0.01U_0402_16V7K~D
1
C410
2
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#<31>
CBS_CC/BE1#<31>
CBS_CPAR<31>
CBS_CPERR#<31>
CBS_CGNT#<31>
CBS_CINT#<31>
CBS_VCC
CBS_VPP
CBS_CCLK<31>
CBS_CIRDY#<31>
CBS_CC/BE2#<31>
13
14
15
16
CBS_RSVD/D2<31>
CBS_CCLKRUN#<31>
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#
CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#
JCBUS
1
A_CAD0
2
A_CAD1
3
A_CAD3
4
A_CAD5
5
GND0
6
A_CAD7
7
A_PCI_C/BE0#
8
A_CAD9
9
A_CAD11
10
GND1
11
A_CAD12
12
A_CAD14
13
A_PCI_C/BE1#
14
A_CPAR
15
GND2
16
A_CPERR#
17
A_CGNT#
18
A_CINT#
19
+AVCC0
20
GND3
21
+AVPP0
22
A_CCLK
23
A_CIRDY
24
A_PCI_C/BE2#
25
GND4
26
A_CAD18
27
A_CAD20
28
A_CAD21
29
A_CAD22
30
GND5
31
A_CAD23
32
A_CAD24
33
A_CAD25
34
A_CAD26
35
GND6
36
A_CAD27
37
A_CAD29
38
CB_A_D2
39
A_CCLKRUN#
40
GND7
FOX_QT600806-7121_LT~D
GND15
A_CCD1#
A_CAD2
A_CAD4
A_CAD6
GND14
CB_A_D14
A_CAD8
A_CAD10
A_CVS1
GND13
A_CAD13
A_CAD15
A_CAD16
CB_A_A18
GND12
A_CBLOCK#
A_CSTOP#
A_CDEVSEL#
+AVCC1
GND11
+AVPP1
A_CTRDY#
A_CFRAME#
A_CAD17
GND10
A_CAD19
A_CVS2
A_CRST#
A_CSERR#
GND9
A_CREQ#
A_PCI_C/BE3#
A_CAUDIO
A_CSTSCHG
GND8
A_CAD28
A_CAD30
A_CAD31
A_CCD2#
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13_L
CBS_CAD15_L
CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#
CBS_CCD1# <31>
CBS_RSVD/D14 <31>
CBS_CVS1 <31>
CBS_CAD13_L <28>
CBS_CAD15_L <28>
CBS_RSVD/A18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>
CBS_VCC
CBS_VPP
CBS_CTRDY# <31>
CBS_CFRAME# <31>
CBS_CVS2 <31>
CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>
CBS_CCD2# <31>
0.01U_0402_16V7K~D
1
C412
2
CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD14
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0
CBS_VCC
1
C413
2
10U_0805_10V4M~D
CBS_CAD31 <31>
CBS_CAD30 <31>
CBS_CAD29 <31>
CBS_CAD28 <31>
CBS_CAD27 <31>
CBS_CAD26 <31>
CBS_CAD25 <31>
CBS_CAD24 <31>
CBS_CAD23 <31>
CBS_CAD22 <31>
CBS_CAD21 <31>
CBS_CAD20 <31>
CBS_CAD19 <31>
CBS_CAD18 <31>
CBS_CAD17 <31>
CBS_CAD16 <31>
CBS_CAD14 <31>
CBS_CAD12 <31>
CBS_CAD11 <31>
CBS_CAD10 <31>
CBS_CAD9 <31>
CBS_CAD8 <31>
CBS_CAD7 <31>
CBS_CAD6 <31>
CBS_CAD5 <31>
CBS_CAD4 <31>
CBS_CAD3 <31>
CBS_CAD2 <31>
CBS_CAD1 <31>
CBS_CAD0 <31>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
CardBus/SD card Socket
LA-2171
32 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
PCI_AD[0..31]<20,29,31>
D D
C C
B B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
CK_33M_MINIPCI
R179
10_0402_5%~D@
1 2
CK_33M_MINPCI_TERM
2
C157
4.7P_0402_50V8C~D
@
1
COEX2_WLAN_ACTIVE<27>
4
HW_RADIO_DIS#<27,35>
PCI_PIRQD#<20,31>
CK_33M_MINIPCI<6>
PCI_REQ3#<20>
R181
0_0402_5%~D
1 2
PCI_C_BE3#<20,29,31>
PCI_C_BE2#<20,29,31>
PCI_IRDY#<20,29,31>
CLKRUN#<22,29,31,34>
PCI_SERR#<20,29,31>
PCI_PERR#<20,29,31>
PCI_C_BE1#<20,29,31>
+5VRUN
R139 10K_0402_5%~D
+3VALW
DEBUG_ENABLE<34>
3
+3VRUN+3VRUN
JPCI
1
TIP
3
8PMJ-3
5
8PMJ-6
7
8PMJ-7
9
8PMJ-8
11
HW_RADIO_DIS#
PCI_PIRQD#
PCI_REQ3#
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C_BE3#
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C_BE2#
PCI_IRDY#
CLKRUN#
PCI_SERR# PCI_STOP#
PCI_PERR#
PCI_C_BE1#
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
12
LED1_GRNP
13
LED1_GRNN
15
CHSGND
17
INTB#
19
3.3V
21
RESERVED
23
GROUND
25
CLK
27
GROUND
29
REQ#
31
3.3V
33
AD31
35
AD29
37
GROUND
39
AD27
41
AD25
43
RESERVED
45
C/BE3#
47
AD23
49
GROUND
51
AD21
53
AD19
55
GROUND
57
AD17
59
C/BE2#
61
IRDY#
63
3.3V
65
CLKRUN#
67
SERR#
69
GROUND
71
PERR#
73
C/BE1#
75
AD14
77
GROUND
79
AD12
81
AD10
83
GROUND
85
AD8
87
AD7
89
3.3V
91
AD5
93
RESERVED
95
AD3
97
5V
99
AD1
101
GROUND
103
AC_SYNC
105
AC_SDATA_IN
107
AC_BIT_CLK
109
AC_CODEC_ID1#
111
MOD_AUDIO_MON
113
AUDIO_GND
115
SYS_AUDIO_OUT
117
SYS_AUDIO_OUTGND
119
AUDIO_GND
121
RESERVED
123
VCC5A
AMP_1318644-1~D
AC_SDATA_OUT
AC_CODEC_ID0#
SYS_AUDIO_IN
SYS_AUDIO_INGND
RING
8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5
LED2_YELP
LED2_YELN
RESERVED
INTA#
RESERVED
3.3VAUX
RST#
GNT#
GROUND
PME#
RESERVED
AD30
AD28
AD26
AD24
IDSEL
GROUND
AD22
AD20
AD18
AD16
GROUND
FRAME#
TRDY#
STOP#
DEVSEL#
GROUND
AD15
AD13
AD11
GROUND
C/BE0#
RESERVED
RESERVED
GROUND
M66EN
AC_RESET#
RESERVED
GROUND
AUDIO_GND
MCPIACT#
3.3VAUX
3.3V
3.3V
PAR
3.3V
AD9
3.3V
AD6
AD4
AD2
AD0
2
4
6
8
10
12
14
16
18
5V
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
LED_WLAN24
LED_WLAN5
R146 0_0402_5%~D
MPCIACT#
2
R149 100K_0402_5%~D
1 2
R148 100K_0402_5%~D
1 2
PCI_PIRQB#
PCIRST_CB#CK_33M_MINIPCI
PCI_GNT3#
SYS_PME#
1 2
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
MINIDSEL
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_DEVSEL#
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C_BE0#
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
DEBUG_OUT
V_3P3_LAN
2
C137
0.1U_0402_16V4Z~D
1
LED_WLAN24
LED_WLAN5
PCI_PIRQB# <20,31>
PCIRST_CB# <20,31>
PCI_GNT3# <20>
SYS_PME# <29,31,34>
R147
@
10K_0402_5%~D
1 2
R145
100_0402_5%~D
PCI_PAR <20,29,31>
PCI_FRAME# <20,29,31>
PCI_TRDY# <20,29,31>
PCI_STOP# <20,29,31>
PCI_DEVSEL# <20,29,31>
PCI_C_BE0# <20,29,31>
DEBUG_OUT <34>
R150
1 2
10K_0402_5%~D
+3VRUN
5
U12
1
P
INB
O
2
INA
G
TC7SH32FU_SSOP5~D
3
COEX1_BT_ACTIVE <27>
12
PCI_AD19
+3VSUS
R138 200_0402_5%~D
4
1 2
2
C135
0.1U_0402_16V4Z~D
1
1
V_3P3_LAN
LED_WLAN_OUT <37>
+5VRUN
2
C136
0.1U_0402_16V4Z~D
1
+3VRUN
2
C158
0.047U_0402_16V4Z~D
1
A A
2
C133
0.047U_0402_16V4Z~D
1
2
C470
0.047U_0402_16V4Z~D
1
2
C159
0.047U_0402_16V4Z~D
1
2
C153
0.047U_0402_16V4Z~D
1
2
C132
0.047U_0402_16V4Z~D
1
2
C130
0.047U_0402_16V4Z~D
1
2
C131
0.047U_0402_16V4Z~D
1
2
C152
0.047U_0402_16V4Z~D
1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
MINIPCI
LA-2171
33 50, 12, 2004
1
0.2
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+3VALW
D D
DEBUG_ENABLE<33>
DEBUG_OUT<33>
C C
B B
5
12
12
R321
R330
10K_0402_5%~D
KSO_17<36>
12
R320
10K_0402_5%~D
10K_0402_5%~D
ATF_INT#
SYS_PME#
DEBUG_ENABLE
CB_HWSPND#<31>
HP_NB_SENSE<26>
VAUX_EN<38>
USB_BACK_EN#<28>
SUB_DETECT#<27>
SIO_EXT_SMI#<22>
SIO_EXT_SCI#<22>
SIO_EXT_WAK#<22>
SIO_RCIN#<21>
NB_MUTE<26>
BEEP<25>
SIO_SLP_S3#<22>
SYS_PME#<29,31,33>
ATF_INT#<15>
SIO_SLP_S5#<22>
SPDIF_SHDN<19,25>
SIO_PWRBTN#<22>
RUN_ON<18,38,39,42,44,45>
ICH_PME#<20>
SIO_THRM#<22>
SUS_ON<38,39,44>
ICH_PCIE_WAKE#<18,22>
5V_CAL_SIO#<15>
IDE_RST_MOD<24>
GC_BL_SUSPEND<18>
USB_SIDE_EN#<28>
MODC_EN#<38>
HDDC_EN#<38>
CK_33M_SIOPCI<6>
R501
0_0402_5%~D
+3VRUN
T46 PAD~D
T16 PAD~D
R340 0_0402_5%~D
T31 PAD~D
T32 PAD~D
T38 PAD~D
T34 PAD~D
T14 PAD~D
T35 PAD~D
CK_14M_SIO<6>
T6 PAD~D
254VCC0
12
2
C599
0.1U_0402_16V4Z~D
1
L46
BLM11A121S_0603~D
1 2
KSO_17
1.5mmSMT~D@
D21
RB751V_SOD323~D
2 1
J1397
1
1
2
2
3
3
+3.3VX
CB_HWSPND#
HP_NB_SENSE
VAUX_EN
KSO17
USB_BACK_EN#
1 2
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAK#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S5#
SPDIF_SHDN
LID_CL_SIO#
SIO_PWRBTN#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
ICH_PCIE_WAKE#
5V_CAL_SIO#
IDE_RST_MOD
GC_BL_SUSPEND
USB_SIDE_EN#
MODC_EN#
HDDC_EN#
CK_33M_SIOPCI
CK_14M_SIO
2
1
4
+3VALW
+3VRUN
KPLLVCC
C352
0.1U_0402_16V4Z~D
U24A
F13
SGPIO30
F14
SGPIO31
E16
SGPIO32
E15
SGPIO33
E12
SGPIO34
E13
SGPIO35
D16
SGPIO36
D15
SGPIO37
C16
SGPIO40
B16
SGPIO41
C15
SGPIO42
A16
SGPIO43
D14
SGPIO44
C14
SGPIO45
C13
SGPIO46
B14
SGPIO47
T5
LGPIO50
N6
LGPIO51
L6
LGPIO52
R6
LGPIO53
T6
LGPIO54
L7
LGPIO55
P7
LGPIO56
N7
LGPIO57
A15
LGPIO60/SPCLK
D13
LGPIO61/SPDOUT
A14
LGPIO62/SPDIN
C12
LGPIO63
B13
LGPIO64
A13
LGPIO65
D12
LGPIO66
F11
LGPIO67
B12
LGPIO70
A12
LGPIO71
C11
LGPIO72
D11
LGPIO73
E11
LGPIO74
A11
LGPIO75
F10
LGPIO76
C10
LGPIO77
L3
PCI_CLK
L4
CLOCKI
B2
GPIO83/32KHZ_OUT
E2
VCCO/BAT
M7
VCC1_1
B11
VCC1_2
R13
VCC1_3
H12
VCC1_4
E14
VCC1_5
B7
VCC1_6
A1
VCC1_7
L11
VCC1_8
G2
VCC2_1
P4
VCC2_2
J2
VCC2_3
M2
VCC2_4
R5
VCC2_5/PLL
P6
VSS13/PLL
LPC47N354_LBGA256~D
LPC47N354
MACALLEN III
8051
GPIO
LPC
GPIO
CLOCK
VCC
256 - LBGA
3
EC_SCI/SPDIN
CLKRUN#
LPC INTERFACE
LFRAME#
LRESET#
DLDRQ1#
DLFRAME#
DSER_IRQ
DCLKRUN#
COM1
GPIO10/WK_SE14/IRMODE/IRRX3B
IR
GPIOB2/SLCTIN
GPIOB1/INIT
GPIOC0/PD0
GPIOC1/PD1
GPIOC2/PD2
GPIOC3/PD3
GPIOC4/PD4
GPIOC5/PD5
GPIOC6/PD6
GPIOC7/PD7
LPT
OUTD0/SLCT
OUTD1/PE
OUTD2/BUSY
OUTD3/ACK
OUTD4/ERROR
GPIOB0/STROBE
GPIOB3/ALF
GND
SER_IRQ
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#
DLAD0
DLAD1
DLAD2
DLAD3
RXD1
TXD1
DSR
CTS
DTR
DCD
IRRX
IRTX
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
AGND
2
J12
IRQ_SERIRQ
T4
CLKRUN#
P5
LPC_LAD0
M3
LPC_LAD1
R1
LPC_LAD2
T1
LPC_LAD3
P3
LPC_LDRQ0#
M6
LPC_LDRQ1#
R3
LPC_LFRAME#
N4
PLTRST_SIO#
L2
N2
P1
P2
N3
R2
T2
R4
T3
R290 10K_0402_5%~D
K1
K5
K2
K4
RTS
K3
K6
B10
RI
L1
H15
K14
M4
J4
J5
J1
H2
H1
H3
H4
H5
H6
H8
F1
G5
G1
H7
J6
K7
J7
C2
G4
N5
R15
B15
G9
J3
N1
T10
J11
G14
B6
F3
1 2
TXD0
R289 10K_0402_5%~D
1 2
R288 10K_0402_5%~D
1 2
R517 10K_0402_5%~D
1 2
R300 10K_0402_5%~D
1 2
10K_0402_5%~D
R338
1 2
KAGND
1 2
BLM11A121S_0603~D
L85
IRQ_SERIRQ <22,31>
CLKRUN# <22,29,31,33>
LPC_LAD[0..3] <21>
LPC_LDRQ0# <21>
LPC_LDRQ1# <21>
LPC_LFRAME# <21>
PLTRST_SIO# <20>
+3VRUN
CK_33M_SIOPCI
CK_14M_SIO
R502
Note: For system debug
pin4 connect to serial port pin3
U36
1
NC
TXD0
2
INA
3
GND
TC7SH04FU_SSOP5~D@
+3VALW
12
R324
100K_0402_5%~D
LID_CL_SIO#
12
12
10_0402_5%~D@
R503
10_0402_5%~D@
10_0402_5%~D
1
C362
0.047U_0402_10V7K~D
2
VCC
OUTY
R329
1
+5VSUS
5
4
LID_CL#
12
T13PAD~D
LID_CL# <36>
+3VRUN+3VALW
C364
2
A A
0.1U_0402_16V4Z~D
C614
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C601
1
1
C373
2
2
0.1U_0402_16V4Z~D
C600
0.1U_0402_16V4Z~D
2
2
C349
1
1
0.1U_0402_16V4Z~D
CK_14M_SIO_TERM
CK_33M_SIOPCI_TERM
2
2
C598
C597
4.7P_0402_50V8C~D@
1
1
4.7P_0402_50V8C~D@
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
SIO LPC47N354(1/2)
LA-2171
34 50, 12, 2004
1
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
5
+5VALW
R322
IN2
12
4.7K_0402_5%~D
D D
+3VALW+3VALW
+3VALW
R512
R513
R339
1 2
4.7K_0402_5%~D
PBAT_ALARM#
12
R326
10K_0402_5%~D
Note: SMSC errata
C C
LPC47N354 A Rev AnomalyÂTouch Pad IMCLK and IMDAT signals are inverted
+5VRUN
B B
R500
1 2
4.7K_0402_5%~D
DAT_KBD
CLK_KBD
CLK_SM1
DAT_SM1 CLK_32KX2
BID0
BID1
BID2
BID3
R318
10K_0402_5%~D
A A
1 2
10K_0402_5%~D
1 2
4.7K_0402_5%~D
R299
R507
1 2
@
IN6
IN5
FPVCC
CLK_SM2<36>
DAT_SM2<36>
12
12
R301
R297
1 2
4.7K_0402_5%~D
10K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
+3VRUN
R511
R311
1 2
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D
@
@
R319 10K_0402_5%~D@
1 2
R506 10K_0402_5%~D
1 2
R510 10K_0402_5%~D
1 2
R312 10K_0402_5%~D
1 2
5
+3VALW
R327 100K_0402_5%~D
1 2
R331 100K_0402_5%~D
1 2
PBAT_PRES#<42>
THERMTRIP_SIO<15>
T36 PAD~D
T33 PAD~D
KSO16<36>
CAP_LED#<37>
NUM_LED#<37>
SRL_LED#<37>
T15 PAD~D
NB_PSID<41>
PS_ID_DISABLE#<41>
T11 PAD~D
T8 PAD~D
T7 PAD~D
T9 PAD~D
T10 PAD~D
M_LED_C<36>
M_LED_B<36>
M_LED_A<36>
T37 PAD~D
T39 PAD~D
CLK_SM2<36>
DAT_SM2<36>
PBAT_ALARM#<42>
KSO[0..15]<36>
CLK_SM2
DAT_SM2
KSI[0..7]<36>
C338
1 2
C339
1 2
12
X6
32.768KHZ_12.5P_MC-306~D
3.8X12.1mm
CLK_32KX1
4
U24B
A9
IN0(WK_EE4)
B9
IN2
FPVCC
IN5
IN6
PBAT_PRES#
THERMTRIP_SIO
H_PROCHOT_SIO#
KSO16
CAP_LED#
NUM_LED#
SRL_LED#
NB_PSID
BID0
BID1
BID2
BID3
PS_ID_DISABLE#
SIO_MSCLK
SIO_MSDAT
CLK_SM1
DAT_SM1
CLK_SM2
DAT_SM2
CLK_KBD
DAT_KBD
PBAT_ALARM#
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6 SIO_FA11
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
BID2 BID1
0
0
0
0
4
IN1(WK_EE2)
B8
IN2(WK_EE3)
A8
IN3(GPWKUP)
C8
IN5(WK_SE01)
D8
IN6(WK_SE05)
E8
IN7(WK_EE1)
H13
GPIO0(WK_SE02)
H11
GPIO1(WK_SE03)
H10
GPIO2(WK_SE04)
G10
GPIO3(TRIGGER)
G13
GPIO7(WK_SE06)
J14
GPIO8(WK_SE12)/IRRX2
J16
GPIO9(WK_SE13)/IRTX2
G11
GPIO17(WK_SE23)/A20M
F15
GPIO20(WK_SE25)/PS2CLK/8051RX
F12
GPIO21(WK_SE26)/PS2DAT/8051TX
B5
GPIO84
E5
GPIO85
D5
GPIO86
A4
GPIO87
B4
GPIO90
C5
GPIO91
A3
GPIO92
A2
GPIO93
C3
GPIO96
D3
GPIO97
B1
GPIOA0
D4
GPIOA1
C1
GPIOA2
D10
MSCLK/SPCLK
E10
MSDATA/SPDOUT
G6
EMCLK
G3
EMDAT
B3
GPIO94/IMCLK
C4
GPIO95/IMDAT
M1
KCLK
M5
KDAT
G15
GPIO6(WK_SE11)/IRMODE/IRRX3A
G12
GPIO5(WK_SE10)/KSO15
G16
GPIO4(WK_SE07)/KSO14
R7
KSO13/GPIO18(WK_SE27)
T7
KSO12/OUT8/KBRST
K8
KSO11
J8
KSO10
L8
KSO9
M8
KSO8
N8
KSO7
P8
KSO6
T8
KSO5
R8
KSO4
R9
KSO3
T9
KSO2
P9
KSO1
N9
KSO0
M9
KSI7
L9
KSI6
K9
KSI5
K10
KSI4
M10
KSI3
R10
KSI2
N10
KSI1
P10
KSI0
E1
XTAL1
D1
XTAL2
LPC47N354_LBGA256~D
GPIO
K/B
BID0BID3
0
0
1
0
LPC47N354
MACALLEN III
GPIO11(WK_SE15)/AB2A_DATA
GPIO12(WK_SE16)/AB2A_CLK
GPIO13(WK_SE17)/AB2B_DATA
GPIO14(WK_SE20)/AB2B_CLK
GPIO15(WK_SE21)/FAN_TACH1
GPIO16(WK_SE22)/FAN_TACH2
256 - LBGA
REV
X00
X01
3
FPGM
TEST_PIN
XOSEL
SYSOPT0/GPIO80
SYSOPT1/GPIO81
BAT_LED
PWR_LED
GPIOA3/WINDMON
TESTA
VCC1RST#
RESET_OUT
PWRGD
ACAV_IN
POWER_SW_IN#
ALWON
OUT0
OUT1/IRQ8
OUT2/FRD
OUT3/FWR
OUT4
OUT5/KBRST
MISC
FLASH
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
OUT6
OUT7/SMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1
AB1A_CLK
AB1B_DATA
AB1B_CLK
AB1A_DATA
GPIO82/FAN_TACH3
GPIO19(WK_SE24)
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22
3
FWR
2
+3VALW
12
+3VALW
12
R528
1K_0402_5%~D
@
R527
SIO_KAH_PGM
L10
K12
XOSEL
E4
SYSOPT0
K15
SYSOPT1
K16
BAT1_LED#
J9
BAT2_LED#
J10
E3
F2
VCC1RST#
D2
RESET_OUT#
L5
RUNPWROK
K13
ACAV_IN
F4
F5
ALWON
F6
EEPROM_WC
D7
C7
HW_RADIO_DIS#
F7
LAN_LOW_PWR
A6
CHG_PBATT
E6
D6
AUDIO_AVDD_ON
C6
E7
A7
FAN2_PWM
G7
BREATH_LED
G8
FAN1_PWM
F8
CLK_SMB
C9
SMBUS_DATA
F9
SMBUS_CLK
E9
DAT_SMB
D9
SMBDAT_VGA
H16
SMBCLK_VGA
H14
PBAT_SMBDAT
J15
PBAT_SMBCLK
J13
FAN1_TACH
A10
FAN2_TACH
H9
A5
SIO_A20GATE
F16
SIO_FA0
N12
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FRD
FCS
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
SIO_FA1
T13
SIO_FA2
P12
SIO_FA3
T14
SIO_FA4
T15
SIO_FA5
R16
SIO_FA6
N13
SIO_FA7
P16
SIO_FA8
M14
SIO_FA9
N15
SIO_FA10
N16
M13
SIO_FA12
L12
SIO_FA13
M15
SIO_FA14
M16
SIO_FA15
L14
SIO_FA16
L13
SIO_FA17
L15
SIO_FA18
L16
SIO_FA19
K11
R14
T16
P13
FRD#
P14
FWR#
N14
FCS#
P15
SIO_FD7
M12
SIO_FD6
R12
SIO_FD5
T12
SIO_FD4
P11
SIO_FD3
N11
SIO_FD2
M11
SIO_FD1
R11
SIO_FD0
T11
SIO_FA[0..19] <36>
FRD# <36>
FWR# <36>
FCS# <36>
SIO_FD[0..7] <36>
10K_0402_5%~D
R508 10K_0402_5%~D
R334 10K_0402_5%~D
1 2
R335 10K_0402_5%~D
1 2
BAT1_LED# <37>
BAT2_LED# <37>
VCC1RST# <36>
RESET_OUT# <39>
RUNPWROK <18,39,43,46>
ACAV_IN <47>
ALWON <44>
EEPROM_WC <36>
HW_RADIO_DIS# <27,33>
LAN_LOW_PWR <29>
CHG_PBATT <47>
AUDIO_AVDD_ON <25>
FAN2_PWM <15>
BREATH_LED <37>
FAN1_PWM <15>
FAN1_TACH <15>
FAN2_TACH <15>
SIO_A20GATE <21>
1 2
R505 0_0402_5%~D
CLK_SMB <15,36>
DAT_SMB <15,36>
SMBDAT_VGA <18>
SMBCLK_VGA <18>
PBAT_SMBDAT <42,47>
PBAT_SMBCLK <42,47>
12
12
R491
1K_0402_5%~D
1
C
E
3
POWER_SW#POWER_SW_IN#
POWER_SW# <15,37>
Level shifter
H_PROCHOT_SIO#
PROCHOT_SFTON
Q39
2
B
MMBT3904_SOT23~D
R409
56_0402_5%~D
1 2
R410
56_0402_5%~D
1 2
DAT_SMB
CLK_SMB
POWER_SW_IN#
SMBDAT_VGA
SMBCLK_VGA
PBAT_SMBDAT
PBAT_SMBCLK
SMBUS_DATA
SMBUS_CLK
LAN_LOW_PWR
CHG_PBATT
1
+VCCP
+VCCP
H_PROCHOT# <7>
R516
10K_0402_5%~D
1 2
R515
10K_0402_5%~D
1 2
R504
10K_0402_5%~D
1 2
1
C609
0.1U_0402_16V4Z~D
2
R337
22K_0402_5%~D
1 2
R525
22K_0402_5%~D
1 2
R336
8.2K_0402_5%~D
1 2
R526
8.2K_0402_5%~D
1 2
R519
10K_0402_5%~D
1 2
R518
10K_0402_5%~D
1 2
+3VALW
R323
10K_0402_5%~D
@
12
R304
100K_0402_5%~D
1 2
+3VALW
+3.3VX
+5VALW
+3VALW
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
SIO LPC47N354(2/2)
LA-2171
35 50, 12, 2004
1
0.2
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5
4
3
2
1
Note: SMSC errata
LPC47N354 A Rev Anomaly- Touch Pad IMCLK and IMDAT signals are inverted
+5VRUN
D D
R315
4.7K_0402_5%~D
DAT_SM2<35>
CLK_SM2<35>
DAT_SM2
CLK_SM2
C356
10P_0402_50V8J~D
12
12
R316
4.7K_0402_5%~D
1
C357
2
10P_0402_50V8J~D
BLM11A601S_0603~D
1 2
1 2
BLM11A601S_0603~D
1
2
L47
L48
1
C358
C359
2
10P_0402_50V8J~D
TP_DATA
TP_CLK
1
2
10P_0402_50V8J~D
12
R495
0_0402_5%~D
1
2
3
4
U27
NC
A1
A2
VSS
AT24C04N-10SI-2.7_SO8~D
SUB_6782U
+3VALW+3VALW
8
VCC
7
WP
6
SCL
5
SDA
SMbusaddress A2
1
C590
0.1U_0402_16V4Z~D
2
EEPROM_WC
CLK_SMB
DAT_SMB
EEPROM_WC <35>
CLK_SMB <15,35>
DAT_SMB <15,35>
LCM & Direct play SW & T PAD
JLCM
2
L57BLM15AG221PN1D_0402~D
TP_CLK
TP_DATA
12
L61BLM15AG221PN1D_0402~D
12
L63BLM15AG221PN1D_0402~D
12
L60BLM15AG221PN1D_0402~D
12
0.1U_0402_16V4Z~D
C376
1
2
C C
KSO_17<34>
M_LED_A<35>
M_LED_B<35>
M_LED_C<35>
LID_CL#<34>
+3VALW
112
334
556
778
9910
11
11
13
13
151516
17
17
19
19
ACES_87216-2012
12
14
18
20
L56 BLM15AG221PN1D_0402~D
4
6
8
10
12
14
16
18
20
1 2
L52 BLM15AG221PN1D_0402~D
1 2
L55 BLM15AG221PN1D_0402~D
1 2
L51 BLM15AG221PN1D_0402~D
1 2
L54 BLM15AG221PN1D_0402~D
1 2
L50 BLM15AG221PN1D_0402~D
1 2
L53 BLM15AG221PN1D_0402~D
1 2
1 2
0.1U_0402_16V4Z~D
BLM31A260SPT_1206~D
C369
1
2
L58
+5VRUN
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSI6
KSI4
KSI2
B B
KSO[0..15]<35>
A A
KSI[0..7]<35>
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
5
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO16<35>
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
CN1
CN6
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
@
CN5
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
@
4
CN4
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
@
CN3
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
@
CN2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
@
100P_1206_8P4C_50V8~D
@
JKYBD
25
24
23
22
21
20
19
18
17
16
15
30
29
14
13
28
27
12
11
26
10
9
8
31
7
32
6
5
33
4
34
3
2
1
JAE_FK2S030W11~D
1
C366
100P_0402_50V8J~D
@
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SIO_FA[0..19]<35>
SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19
FCS#<35>
FRD#<35>
FWR#<35>
FCS#
FRD#
FWR#
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
22
24
9
2
U32
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE#
OE#
WE#
SST39VF080-70-4C-EI_TSOP40~D
VCC
VCC
RP#/RESET#
WP#/RY/BY#
GND
GND
31
30
11
VPP
25
D0
26
D1
27
D2
28
D3
32
D4
33
D5
34
D6
35
D7
10
12
29
NC
38
NC
23
39
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
SIO_FD0
SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7
FWH_RST
R533
0_0402_5%~D
FWH_RST
Compal Electronics, Inc.
LA-2171
C360
12
VCC1RST#
1
2
0.1U_0402_16V4Z~D
R302
10K_0402_5%~D@
1 2
INT KB
1
+3VALW
1
C361
2
0.1U_0402_16V4Z~D
VCC1RST# <35>
SIO_FD[0..7] <35>
+3VALW
0.2
36 50, 12, 2004
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5
OUT
1
+3VRUN
R16
12
R17
12
+3VALW
R371
150_0402_5%~D
1 2
Z3901
1
C
Q33
MMBT3904_SOT23~D
E
3
+3VALW
R372
150_0402_5%~D
1 2
Z3902
1
C
Q32
MMBT3904_SOT23~D
E
3
DTA114YKA
R13
470_0402_5%~D
R14
470_0402_5%~D
R15
470_0402_5%~D
BAT1_LED
R_BREATH_LED
R_BT_MPCI_ACT
D D
47K
Q3
10K
DTA114YKA_SC59~D
1 3
R_CAP
R_SRL
470_0402_5%~D
470_0402_5%~D
2
B
2
B
CAP_LED#<35>
47K
10K
1 3
+5VALW
47K
10K
1 3
R373
10K_0402_5%~D
1 2
10K_0402_5%~D
5
2
2
1 2
NUM_LED#<35>
SRL_LED#<35>
C C
BAT1_LED#<35>
BAT2_LED#<35>
B B
BREATH_LED<35>
A A
BT_ACTIVE<27>
2
2
BT_ACTIVE
2
47K
Q4
DTA114YKA_SC59~D
10K
1 3
Q5
DTA114YKA_SC59~D
47K
Q6
DTA114YKA_SC59~D
10K
1 3
R_BAT1_LED
Q1
DTA114YKA_SC59~D
R_BAT2_LED BAT2_LED
BREATH_LED_B
R370
BT_MPCI_ACTIVE
4
GNDIN
32
CAP_LED
12
NUM_LEDR_NUM
12
SRL_LED
12
JTV2
E&T_3801-08-1~D
4
SATA_ACT#<21>
Luma_Pr
CVBS_Y
Chroma_Pb
Audio_R
Audio_L
9
1
9
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
10
10
3
+3VRUN
47K
Q2
10K
JWIRE
E&T_3802-02-1~D
DTA114YKA_SC59~D
1 3
R_PIDEACT
1.8UH_MDF1608A1R8K_10%_0603~D
@
22P_0402_50V8J~D
CLOSETOJSVID
C434
1
2
1.8UH_MDF1608A1R8K_10%_0603~D
@
22P_0402_50V8J~D
C433
1
2
1.8UH_MDF1608A1R8K_10%_0603~D
@
22P_0402_50V8J~D
1
C424
2
1.8UH_MDF1608A1R8K_10%_0603~D
@
33P_0402_50V8J~D
C439
1
2
1.8UH_MDF1608A1R8K_10%_0603~D
@
33P_0402_50V8J~D
C610
1
2
RJ_TIP
1
RJ_RING
2
3
R18
470_0402_5%~D
L73
1 2
L75
1 2
L74
1 2
L76
1 2
L88
1 2
12
RJ_TIP
RJ_RING
ACTLED
C431
C419
C420
C438
C442
CLK_PCIE_TV#<6>
CLK_PCIE_TV<6>
22P_0402_50V8J~D
1
2
22P_0402_50V8J~D
1
2
22P_0402_50V8J~D
1
2
33P_0402_50V8J~D
1
2
33P_0402_50V8J~D
1
2
JPHON
1
1
2
2
3
GND1
4
GND2
SUYIN_100002FR006G202ZU~D
2
CVBS_Y
Luma_Pr
Chroma_Pb
Audio_L
Audio_R
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
R_BT_MPCI_ACT
BAT1_LED
BAT2_LED
+5VALW
LED_WLAN_OUT<33>
POWER_SW#<15,35>
1 2
0_0402_5%~D@
TV_Luma_Pr
TV_CVBS_Y
TV_Chroma_Pb TV_Chroma_Pb
TV_Audio_R
TV_Audio_L
JTUNR
112
334
556
CLK_PCIE_TV#
CLK_PCIE_TV
778
9910
11
11
13
13
151516
17
17
19
19
SUYIN_800160FA020S200ZR~D
PCIE_RXN1
PCIE_RXP1
R_BREATH_LED
ACTLED
CAP_LED
NUM_LED
SRL_LED
LED_WLAN_OUT
POWER_SW#
POWER_SW_EMI
R375
TV_Audio_R
TV_Luma_Pr
TV_Audio_L
TV_CVBS_Y
2
+5VRUN+3VRUN
4
TUNR_PLTRST#
6
8
10
PCIE_RXN1
12
12
14
18
20
C663 0.1U_0402_10V7K~D
C664 0.1U_0402_10V7K~D
14
16
18
20
1 2
1 2
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
2
Date: Sheet of
Compal Electronics, Inc.
LA-2171
JLED
121314
11
10
9
8
7
6
5
4
3
2
1
E&T_3801-12-1~D
R556
0_0402_5%~D
1 2
1 2
R555
0_0402_5%~D@
PCIE_TXN1 <22>
PCIE_TXP1 <22>
PCIE_RXN1_C
PCIE_RXP1_C
JLED
1
JTV1
2
4
6
7
5
3
1
8
9
10
11
FOX_MH11777-WRUR6~D
PLTRST_DELAY# <20,22>
PLTRST# <20,22,24>
PCIE_RXN1_C <22>
PCIE_RXP1_C <22>
1
37 50, 12, 2004
0.2
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5
Run Planes Enable
Q24
2
G
SUS_ON<34,39,44>
+15V
2
G
PWR_SRC
11
12
R347
100K_0402_5%~D
13
D
Q29
2N7002_SOT23~D
S
12
R314
100K_0402_5%~D
RUN_ENABLE
13
D
S
SUS_ON
1
C348
2
4700P_0402_25V7K~D
ENAB_3VLAN <29>
12
R343
470K_0402_5%~D
+5VALW
D D
100K_0402_5%~D
RUN_ON<18,34,39,42,44,45>
2N7002_SOT23~D
C C
B B
2
VAUX_EN<34>
A A
R310
RUN_ON_5V#
Q23
PWR_SRC
12
13
D
G
S
5
12
13
D
2
G
S
R348
100K_0402_5%~D
N21917830
Q30
R344
2N7002_SOT23~D
2N7002_SOT23~D
12
200K_0402_5%~D
4
+3VSRC
8
7
5
PWR_SRC
12
1 1
R258
470K_0402_5%~D
13
D
2
Q15
G
S
2N7002_SOT23~D
4
Q18
SI4810DY_SO8~D
4
+5VSUS
Q52
SI3456DV-T1_TSOP6~D
D
6
2
1
+1.5VSUS
D
6
2
1
+1.5VSUS
SI4800DY-T1_SO8~D
8
7
5
+1.8VSUS
D
6
2
1
2
G
12
R267
200K_0402_5%~D
1
2
36
1
C321
2
4.7U_0805_10V4Z~D
S
45
G
C618
3
4.7U_0805_10V4Z~D
S
45
Q35
G
SI3456DV-T1_TSOP6~D@
3
Q55
1
2
36
4
Q21
SI3456DV-T1_TSOP6~D
S
45
G
C347
3
4.7U_0805_10V4Z~D
+3VSRCPWR_SRC
12
R262
200K_0402_5%~D
13
D
Q16
S
R270
2N7002_SOT23~D
+3VRUN Source
+3VRUN
12
R277
10K_0402_5%~D
@
+5VRUN Source
+5VRUN
1
12
R522
10K_0402_5%~D
2
@
+1.5VRUN Source
1
C403
2
4.7U_0805_10V4Z~D
+1.8VRUN Source
+1.8VRUN
1
12
R305
10K_0402_5%~D
2
@
Q17
SI4810DY_SO8~D
8
7
5
12
C288
470K_0402_5%~D
0.1U_0402_16V4Z~D
4
1
2
3
+VCC_CORE
12
1
R225
47_0805_5%~D@
Z4005
2
Q14
13
D
RUN_ON_5V#
12
+1.5VRUN
12
R384
10K_0402_5%~D
@
+3VSUS
1
2
36
1
C303
4.7U_0805_10V4Z~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
SUSPWROK_5V
+3VSUS Source
3
13
D
2
G
S
SUSPWROK_5V <44,45>
2
G
R89
100K_0402_5%~D@
SUSPWROK_5V#
Q48
2N7002_SOT23~D@
2N7002_SOT23~D@
S
+1.5VSUS +1.8VSUS+5VALW
2
G
2
+0.9V_DDR_VTT +3VRUN
12
1
R313
22_0805_5%~D@
Z4006
2
Q22
13
D
2N7002_SOT23~D@
2
G
S
12
R87
22_0805_5%~D@
Z4015
13
D
Q31
2N7002_SOT23~D@
S
+5VHDD Source
HDDC_EN#<34>
+5VMOD Source
MODC_EN#<34>
2
12
1
R309
Z4007
2
Q27
13
D
2
G
S
12
R88
22_0805_5%~D@
Z4018
13
D
Q34
2
2N7002_SOT23~D@
G
S
Q20
DTC144EKA_SOT23~D
DTC144EKA_SOT23~D
1
+1.5VRUN +VCCP +1.8VRUN
12
1
2
G
+15V
12
R287
100K_0402_5%~D
HDD_EN
13
+15V
12
R530
100K_0402_5%~D
2
13
R127
Z4008
2
Q11
13
D
S
MOD_EN
C371
22_0805_5%~D@
2N7002_SOT23~D@
1
C327
2
1
2
0.01U_0402_25V7K~D
22_0805_5%~D@
2N7002_SOT23~D@
2
2
Q53
3
0.01U_0402_25V7K~D
3
+5VSUS
1
G
C315
+5VSUS
1
G
C620
4.7U_1206_16V6K~D
2
G
2
4.7U_1206_16V6K~D
2
12
1
R308
22_0805_5%~D@
Z4009
2 2
Q26
13
D
2N7002_SOT23~D@
S
6
D
Q19
S
SI3456DV-T1_TSOP6~D
+5VHDD
4 5
1
12
R274
2
6
D
Q28
S
SI3456DV-T1_TSOP6~D
+5VMOD
4 5
1
12
R529
2
100K_0402_5%~D
12
1
R307
47_0805_5%~D@
Z4010
Q25
13
D
2N7002_SOT23~D@
2
G
S
100K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
POWER CONTROL
LA-2171
38 50, 12, 2004
1
0.2
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5
U29B
74VHC08MTC_TSSOP14~D
IMVP_PWRGD<10,22,46>
ITP_DBRESET#<7>
D D
RESET_OUT#<35>
IMVP_PWRGD
RUNPWROK
4
5
1
2
13
12
+3VSUS
IN1
IN2
+3VSUS
IN1
IN2
IN1
IN2
OUT
14
P
OUT
G
7
6
+3VSUS
4
5
U30A
3
74VHC08MTC_TSSOP14~D
R497
0_0402_5%~D
1 2
@
U30D
11
OUT
74VHC08MTC_TSSOP14~D
IN1
OUT
IN2
4
U30B
6
74VHC08MTC_TSSOP14~D
R498
0_0402_5%~D
1 2
ICH_PWRGD <22>
+3VRUN
12
R492
100K_0402_5%~D
5VRUNRC
1
C591
0.1U_0402_16V4Z~D
2
2P5V_PWRGD<42>
RUN_ON<18,34,38,42,44,45>
3
+3VSUS
C589
0.1U_0402_16V4Z~D
1 2
8
U26A
P
7
A1Y
G
SN74LVC3G14DCTR_SSOP8~D
4
U30C
10
IN1
9
IN2
74VHC08MTC_TSSOP14~D
1 2
0_0402_5%~D@
R293
+3VSUS
A6Y
8
OUT
2
8
U26B
P
2
G
SN74LVC3G14DCTR_SSOP8~D
4
R292
1 2
0_0402_5%~D
1
2
+3VSUS
IN1
IN2
14
P
OUT
G
7
C585
0.1U_0402_16V4Z~D
1 2
U29A
74VHC08MTC_TSSOP14~D
3
+3VSUS
U29D
74VHC08MTC_TSSOP14~D
13
IN1
12
IN2
1
RUNPWROK
11
OUT
RUNPWROK <18,35,43,46>
C C
ICH_PWRGD
B B
+1.5VSUS
12
R482
10K_0402_5%~D
2
B
1
0.1U_0402_16V4Z~D
A A
C584
2
+3VALW
100K_0402_5%~D
12
R490
1
C
Q50
MMBT3904_SOT23~D
E
3
2
G
+3VSUS
12
R550
100K_0402_5%~D
ICH_PWRGD#
13
D
Q60
2N7002_SOT23~D
S
ICH_PWRGD# <15>
+3VSUS
8
U26C
P
5
A3Y
G
SN74LVC3G14DCTR_SSOP8~D
4
SUS_ON<34,38,44>
1.5VSUS_PWRGD
1.5VSUS_PWRGD
SUS_ON
+3VSUS
10
IN1
8
OUT
9
IN2
U29C
74VHC08MTC_TSSOP14~D
SUSPWROK <15,22>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
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DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Power Good
LA-2171
39 50, 12, 2004
1
0.2
5
4
3
2
1
Fiducial Mark
FD3
FD17
FD4
1
SMD40M80@
FD18
1
SMD40M80@
FD1
1
SMD40M80@
D D
CLP4
EMI_CLIP~D@
CLP13
EMI_CLIP~D@
GND
GND
1
1
CLP10
EMI_CLIP~D@
1
GND
CLP11
EMI_CLIP~D@
1
GND
CLP18
EMI_CLIP~D@
1
GND
FD10
1
SMD40M80@
FD2
FD11
1
SMD40M80@
1
SMD40M80@
1
SMD40M80@
1
SMD40M80@
FD5
1
SMD40M80@
FD12
1
FIDUCAL@
FD6
FD13
FD7
1
SMD40M80@
FD14
1
FIDUCAL@
1
SMD40M80@
1
FIDUCAL@
FD8
1
SMD40M80@
FD15
1
FIDUCAL@
FD9
1
SMD40M80@
FD16
1
FIDUCAL@
FD21
1
FIDUCAL@
MY1
MYLAR_CARDBUS~D@
MYLAR(ZZZ)
1
C C
H2
C315D126@
1
H13
C236D110@
1
H23
C315D91@
1
B B
H4
H3
C315D126@
C276D126@
1
1
H14
H15
C236D110@
C315D209@
1
1
H25
H24
C315D91@
C315D91@
1
1
H6
H5
C276D126@
1
H16
C315D110@
1
H26
C236D110@
1
H7
C315D126@
C276D126@
1
1
H17
H18
C315D110@
C315D209@
1
1
H28
H27
C276D110@
C236D110@
1
1
H9
H8
C315D126@
C315D126@
1
1
H19
H20
C315D110@
C236D110@
1
1
H29
H32
C276D126@
C276D110@
1
1
H12
H10
C236D110@
C315D126@
1
1
H22
H21
C315D91@
C236D110@
1
1
H30
H31
C134D134N@
O181X134D181X134N@
1
1
NC
MY2
MYLAR_HDD~D@
MYLAR(ZZZ)
1
NC
MY3
MYLAR_DIMMA~D@
MYLAR(ZZZ)
1
NC
MY4
MYLAR_DIMMB~D@
MYLAR(ZZZ)
1
NC
MY5
MYLAR_MINIPCI~D@
MYLAR(ZZZ)
1
NC
MY6
MYLAR_DOCK_FRAME~D@
MYLAR(ZZZ)
1
NC
MY7
MYLAR_MCH_TOP~D@
MYLAR(ZZZ)
1
NC
MY8
MYLAR_MCH_BOTTOM~D@
MYLAR(ZZZ)
1
NC
MY9
MYLAR_BATTERY~D@
MYLAR(ZZZ)
1
NC
TPAD1
THERMAL_PAD_MCH~D@
THERM PAD
1
NC
TPAD2
THERMAL_PAD_VGA~D@
THERM PAD
1
NC
TPAD3
THERMAL_PAD_VRAM~D@
THERM PAD
1
NC
CAGE1
FCI_57996-001(W/SC)~D
CARDBUS CAGE
1
NC
PCB
DAQ20_LA-2171 _REV0 _M/B~D
BARE PCB
1
NC
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
PAD and Standoff
LA-2171
40 50, 12, 2004
1
0.2
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5
4
3
2
1
+5VALW
D D
PQ12
1 2
1 2
GND_4
GND_3
GND_2
GND_1
MH1
MH2
2
Low_PWR
DC+_1
DC+_2
DC-_1
DC-_2
2N7002_SOT23~D
D
S
1 3
G
2
C
B
E PQ10
3 1
MMBT3904_SOT23~D
1
2
3
4
5
DCIN+
DCIN-
PS_ID
PR68
100K_0402_1%~D
C C
Z-series AC Adaptor
Connctor
B B
PR62
15K_0402_1%~D
PJDC1
HRS_HR33-DL-7~D
9
8
7
6
+5VALW
1 2
PD9
@
DA204U_SOT323~D
PR75
0_0402_5%~D
1 2
PR69
100K_0402_5%~D
FBM-L18-453215-900LMA90T_1812~D@
FBM-L18-453215-900LMA90T_1812~D@
PS_ID_DISABLE# <35>
PL15
BLM11A121S_0603~D
12
PL2
1 2
PL3
OC8070-A301~D
3
2
1 4
PL1
1 2
+3VALW PWR_SRC
2
3
PR78
1 2
1
2.2K_0402_5%~D
NB_PSID <35>
DC_IN+ Source
PS_IDPWR_ID
PC3
1 2
0.47U_1812_50V7M~D
DC_IN
12
PR16
150K_0402_5%~D
1
2
3 6
4
PQ_G
12
PR11
100K_0402_5%~D
PQ1 SI4825DY_SO8~D
8
7
5
PD8
2 1
EC10QS04_SOD106~D
12
PC45
PC48
0.01U_0402_25V7K~D
1 2
PR57
0_0402_5%~D
12
PC34
0.1U_0805_50V7M~D
+DC_IN
12
12
PC1
10U_1210_25V7K~D
0.1U_0805_50V7M~D
+3.3VRTC Source
RTC_SHDN#
1
5
MAX1615EUK_SOT23-5~D
PU2
IN
#SHDN
+3.3VX
3
OUT
4
5/3+
GND
2
12
PC33
10U_1206_6.3V7K~D
THE POINT
NOTE: "THE POINT LOCATED
AT PS MODULE
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
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5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet of
CompalElectronics, Inc.
+DCIN
LA-2171
1
41 50, 12, 2004
0.2
5
D D
+3VALW
4
3
2
1
ESD Diodes
2
3
Primary Battery Connector
PJBAT
C C
12
PC40
10
GND
11
GND
2200P_0402_50V7K~D
SUYIN_200275MR009G516ZL~D
BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYSPRES#
BATT_VOLT
BATT1ÂBATT2-
1
2
3
4
5
6
7
8
9
Z4304
Z4305
Z4306
PD19
DA204U_SOT323~D@
PR164
100_0402_5%~D
1 2
1
100_0402_5%~D
1 2
PR161
2
3
PD20
1
DA204U_SOT323~D@
100_0402_5%~D
1 2
PR155
2
3
PD17
1
DA204U_SOT323~D@
PR162
100_0402_5%~D
1 2
2
3
PD21
1
DA204U_SOT323~D@
PBATT+
PBAT_SMBCLK <35,47>
PBAT_SMBDAT <35,47>
PBAT_ALARM# <35>
EMI team suggest
PL13
FBM-L18-453215-900LMA90T_1812~D
1 2
1 2
PC41
0.1U_0805_50V7M~D
+VCHGR
+3VALW
12
PR156
10K_0402_5%~D
PBAT_PRES# <35>
9
8
7
6
5
4
3
2
1
SUYIN_20175A-09G1
TOP view
B B
+2.5VRUN
PU1
+3VSRC +2.5VRUNP
12
+3VSUS
PR33
2P5V_PWRGD<39>
A A
PJP4
1 2
PAD-OPEN 4x4m
+2.5VRUN+2.5VRUNP
RUN_ON<18,34,38,39,44,45>
2P5V_PWRGD
12
10K_0402_5%~D
PC15
PR166
1 2
10K_0402_1%~D
12
PC16
0.1U_0805_25V7K~D
1U_0805_10V7K~D
1
IN
2
IN
3
POK
SHDN#4GND1
MAX1806EUA25_8UMAX~D
12
PC130
0.1U_0402_10V6K~D
OUT
OUT
SET
GND2
R1=R2* (Vo/ 0.8 -1), R2:25K~100K.
8
7
6
5
9
12
PR30
66.5K_0402_1%
12
PR31
30.9K_0402_1%~D
12
PC14
10U_1206_6.3V7K~D
PR32
0_0603_5%~D@
1 2
PC13
12
0.1U_0805_25V7K~D
NC_TEST6
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Battery Conn./+2.5V
LA-2171
42 50, 12, 2004
1
0.2
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A
B
C
D
+1.5VSUSP / +VCCP_1P05VP
PL14
1 1
FBM-L11-322513-151LMAT_1210~D
1 2
PWR_SRC
1
PC8
PC53
2
10U_1206_25V6M~D
Design current 3A for +1.5VSUSP
2 2
+1.5VSUSP
1
12
PD5
EP10QY03~D
3 3
+
PC73
PC12
2
2 1
220U_D_2.5VM~D
0.1U_0805_25V7K~D
+1.5VSUSP
PR107
0_0603_5%~D@
1 2
PJP1
1 2
PAD-OPEN 4x4m
PJP2
1 2
PAD-OPEN 4x4m
NC_TEST1
+VCCP
3U_SPC-07040-3R0_5A_30%~D
12
PR108
10K_0402_1%~D
12
PR109
20K_0402_1%~D
1 2
12
PR104
0_0402_5%~D
12
PC70
1000P_0402_50V7K~D
@
+1.5VSUS
+VCCP_1P05VP
PL5
VCCP_PWRGD<46>
SUSPWROK_1P8V<45>
1 2
0.1U_0603_25V7K~D
SI4814DY_SO8~D
8
7
6
5
RUNPWROK<18,35,39,46>
12
PC9
2200P_0402_50V7K~D
PQ2
G1
D1
D1
S1/D2
G2
S1/D2
S1/D2
S2
+3VSUS
PR91
100K_0402_5%~D
SUSPWROK_1P8V
1
2
3
4
0_0402_5%~D
12
PR101
12
PD11
RB751V-40_SOD323~D
12
PC68
0.1U_0805_50V7M~D
2 1
12
PD13
1.5V_V+ 1.05V_BST
PR100
0_0603_5%~D
1.5V_BST
12
PR24
1 2
0_0603_5%~D
1.5V_LX
1.5V_DL
1.5V_OUT
1.5V_FB
VCCP_PWRGD
MAX1845_VCC
PC129
1000P_0402_50V7K~D
21
RB751V-40_SOD323~D
1.5V_BST2
1.5V_DH
+5VSUS
21
GND
23
PC67
1 2
4.7U_0805_6.3V6K~D
25
VDD
BST1
26
DH1
27
LX1
28
CS1
24
DL1
1
OUT1
2
FB1
10
REF
5
TON
3
ILIM1
13
ILIM2
MAX1845EEI_QSOP28~D
1.05V_DH
1.05V_LX
1.05V_DL
1.05V_OUT
1.05V_FB
MAX1845_REF
12
PC66
1U_0603_10V6K~D
1 2
PR94
0_0402_5%~D
@
PR92
20_0603_1%~D
1 2
12
PC65
MAX1845_VCC
1U_0603_6.3V6M~D
22
PU4
4
19
18
17
16
20
15
14
7
11
12
6
8
9
V+
BST2
DH2
LX2
CS2
DL2
OUT2
FB2
PGOOD
ON1
ON2
SKIP
OVP
UVP
VCC
PR86
0_0603_5%~D
1 2
PR90
1 2
150K_0402_1%~D
PR89
90.9K_0402_1%~D
21
PD10
RB751V-40_SOD323~D
1.05V_BST2
PR80
0_0603_5%~D
12
PR98
90.9K_0402_1%~D
12
PR99
280K_0402_1%~D
578
12
PC52
0.1U_0805_50V7M~D
12
12
3 6
578
3 6
241
PQ16
FDS6676S_SO8~D
241
12
PC7
PC49
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
PQ15
IRF7811A_SO8~D
PL4
1.8U+-30%DC104C-919AS-1R8N 9.5A~D
1 2
Peak current 7.124A for +VCCP_1P05VP
PC50
PC51
2
2
10U_1206_25V6M~D
10U_1206_25V6M~D
Design current 5A for +VCCP_1P05VPPeak current 4.034A for +1.5VSUSP
+VCCP_1P05VP
1
1
PR87
12
PC11
PC69
0.1U_0805_25V7K~D
@
12
PR97
1K_0402_1%~D
0_0603_5%~D@
1 2
12
PR96
20K_0402_1%~D
+
2
330U_D2E_2.5VM~D
NC_TEST2
+
PD12
PC10
2
EP10QY03~D
2 1
330U_D2E_2.5VM~D
1
1
12
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
+1.5VSUSP /+VCCP_1P05VP
LA-2171
D
43 50, 12, 2004
0.2
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5
4
3
2
1
DC/DC +3V/ +5V/ +15V
PL20
FBM-L11-322513-151LMAT_1210~D
PWR_SRC
D D
Design current 3.4A for +3.3VSRC
Peak current 4.758A for +3VSRCP
+3VSRCP
1
12
+
PC119
PC39
2
C C
B B
A A
0.1U_0805_50V7M~D
330U_D3L_6.3VM_R25~D
NC_TEST3
+15VP
+5VSUSP
+3VSRCP
PJP13
1 2
PAD-OPEN4x4m
PJP8
1 2
PAD-OPEN4x4m
PJP9
1 2
PAD-OPEN4x4m
PR54
0_0603_5%~D@
1 2
PR145
0_0402_5%~D
1 2
@
PR144
1 2
0_0402_5%~D
(150mA,Via NO.= 2)
+15V
(6A,240mils ,Via NO.= 12)
+5VSUS
(4A,160mils ,Via NO.= 8)
+3VSRC
1 2
Place these CAPs
close to FETs
10U_SPC-1204P-100_4.5A_20%~D
PL10
1 2
SUS_ON<34,38,39>
SUS_ON
PC98
10U_1206_25V6M~D
1
PC97
2
12
PC99
PC106
2200P_0402_50V7K~D
PQ29
SI4814DY_SO8~D
8
G1
7
S1/D2
6
S1/D2
5
S1/D2
SUS_ON<34,38,39>
1
2
10U_1206_25V6M~D
12
0.1U_0805_50V7M~D
1
D1
2
D1
3
G2
4
S2
PR60
ALWON<35>
THERM_STP#<15>
12
PC95
PC93
4.7U_1206_25V6K~D
0.1U_0603_25V7K~D
2K_0402_1%~D
1 2
1 2
240K_0402_5%~D
PR121
12
0.1U_0603_25V7K~D
PC29
PR124
0_0603_5%~D
FB3
PR61
1K_0402_5%~D
1 2
4.7_1206_5%~D
12
PR147
1 2
12
PC38
1000P_0402_50V7K~D
@
PR49
0_0603_5%~D
1 2
12
+5VSUSP
22U_1206_6.3VAM~D
VCC_MAX1999
12
PC91
1U_0603_10V6K~D
BST3
DH3
LX3
DL3
12
PC94
10U_1206_6.3V7K~D
PR48
47_0603_5%~D
PU6
20
V+
17
VCC
6
SHDN
28
BST3
26
DH3
27
LX3
24
DL3
22
OUT3
7
FB3
3
ON3
4
ON5
25
LDO3
+3VALW
12
PC90
+5VALW
12
1
PD7
2
3
RB717F_SOT323~D
SKIP
12
MAX1999_SKIP#
12
PR137
0_0402_5%~D
@
BST_5BST_3
18
LDO5
14
BST5
16
DH5
15
LX5
19
DL5
21
OUT5
1
N.C.
9
FB5
10
PRO
11
ILIM5
5
ILIM3
8
REF
13
TON
23
GND
2
PGOOD
MAX1999EEI_QSOP28~D
PR136
0_0402_5%~D
12
PR138
0_0402_5%~D@
12
Adding SKIP control
12
PR125
1 2
PC116
1.07K_0402_1%~D
0.1U_0603_25V7K~D
12
PC26
PC28
1U_0603_10V6K~D
4.7U_1206_25V6K~D
PC31
PR56
0_0603_5%~D
BST5
DH5
LX5
DL5
TON
0.1U_0603_25V7K~D
1 2
1 2
1 2
PR126
0_0603_5%~D
FB5
PRO#
ILIM5
ILIM3
REF
12
PC120
+3VSRCP
1U_0805_10V7K~D
PR140
100K_0402_5%~D
VCC_MAX1999
RUN_ON <18,34,38,39,42,45>
PR157
1 2
150_0603_1%~D
12
1 2
1000P_0603_50V8J~D@
30.9K_0402_1%~D
1 2
PU8
1
2
3
4
PJ3800CS_SO8~D
PC96
PR122
-IN
SCP
VCC
BR/CTL
Place these CAPs
close to FETs
PC107
578
3 6
578
3 6
SUSPWROK_5V <38,45>
ILIM5
ILIM3
PRO#
TON
12
8
FB
7
OSC
6
GND
5
OUT
12
12
PC113
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
PQ32
SI4800DY-T1_SO8~D
5.6U_CEP125-5R6MC_8.8A_20%~D
241
PQ27
SI4810DY_SO8~D
241
PR142
1 2
57.6K_0402_1%~D
PR148
1 2
147K_0402_1%~D
PL11
22U_SPC_06704_22R0_1.5A_30%~D
12
12
PR135
PC111
1 2
3.01K_0402_1%~D
270P_0402_25V8K~D
Design current 4A for +5VSUS
PL9
12
REF
PR141
1 2
30.1K_0402_1%~D
PR146
1 2
147K_0402_1%~D
Peak current 5.7A for +5VSUSP
+5VSUSP
1
12
PC121
0.1U_0805_50V7M~D
PR55
0_0603_5%~D@
1 2
+
PC27
2
330U_D3L_6.3VM_R25~D
NC_TEST4
1 2
1 2
VCC_MAX1999
PR58
0_0402_5%~D
1 2
@
PR59
1 2
0_0402_5%~D
PR120
0_0402_5%~D
@
PR123
0_0402_5%~D
PR143
0_0402_5%~D
1 2
PR149
1 2
0_0402_5%~D
@
Note: check the power consumption of +15V plane
+15VP
PD15
2 1
EC31QS04~D
6
2
1
D PQ30
G
S
4 5
SI3442DV_TSOP6~D
1
1
+
PC92
2
2
PC128
10U_1206_25V6M~D
15U_D2_25M_R90~D
3
12
PC110
0.1U_0603_25V7K~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
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5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
CompalElectronics, Inc.
+3.3V/+5V/+15V
LA-2171
1
44 50, 12, 2004
0.2
5
4
3
2
1
+1.8VSUSP/ +0.9V_DDR_VTT
D D
PWR_SRC
PL17
FBM-L11-322513-151LMAT_1210~D
12
1.8V_0.9V_PWR_SRC
1
PC79
2
10U_1206_25V6M~D
1
PC78
PC76
2
10U_1206_25V6M~D
12
12
PC81
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
21
PD14
PC83
12
PC74
RB751V-40_SOD323~D
PR113
0_0603_5%~D
1 2
PR36 0_0402_5%~D
12
1.8V_DH
1.8V_LX
1.8V_DL
1.8V_FB
1.8V_REF
PR41
100K_0402_1%~D
PR38
150K_0402_1%~D
12
1 2
12
Design current 7A for +1.8V_SUSP
Peak current 10.1A for +1.8VSUSP
+1.8VSUSP
C C
1
1
+
PC24
2
330U_D2E_2.5VM~D
PC23
330U_D2E_2.5VM~D
NC_TEST5
12
+
PC25
2
0.1U_0603_25V7K~D
0_0603_5%~D@
1 2
12
PR116
27.4K_0603_1%~D
PR117
PL8
2.2U_SPC-1205P-2R2B_13A_30%~D
1 2
12
PR118
17.4K_0402_1%~D
B B
578
PQ25
IRF7811A_SO8~D
241
0.1U_0603_25V7K~D
3 6
578
PQ24
FDS6676S_SO8~D
3 6
241
0.22U_0603_16V7K~D
DDR2 Termination
+5VSUS
PC22
1 2
4.7U_0805_6.3V6K~D
22
PU5
20
BST
18
DH
19
LX
21
DL
23
PGND1
16
VOUT
15
FB
1
TON
3
REF
4
+5VSUS
PR35
1 2
10_0402_5%~D
AVDD
12
PC18
1U_0603_6.3V6M~D
17
VIN
AVDD
5
POK1
6
POK2
27
SHDNA
7
STBY
13
VTTI
14
REFIN
11
PGND2
12
VTT
9
VTTS
10
VTTR
SS8GND
MAX8550ETI_TQFN28~D
1000P_0402_50V7K~D
1.8V_0.9V_PWR_SRC
PR45 0_0402_5%~D
PC80
2
VDD
ILIM
25
26
28
SHDNB
OVP/UVP
SKIP
24
PC19
1 2
12
12
PR42 0_0402_5%~D
PR40
20_0603_1%~D
1 2
PC82
0.1U_0603_25V7K~D
1 2
1 2
1U_0603_10V6K~D
PR46
1 2
470K_0402_5%~D
PC87
PR34
1 2
470K_0402_5%~D
+0.9V_PWRGD
SUSPWROK_5V <38,44>
PC75
12
PC86
0.1U_0603_25V7K~D
150U _D2_6.3VM~D
@
12
10U_1206_6.3V7K~D
1
+
2
SUSPWROK_1P8V <43>
1
PC17
2
22U_1206_6.3VAM~D
+1.8VSUS
2N7002_SOT23~D
1
1
PC21
PC20
2
2
22U_1206_6.3VAM~D
22U_1206_6.3VAM~D
V_DDR_MCH_REF <10,16,17>
+5VSUS
PR37
1 2
100K_0402_5%~D
13
D
PQ23
2
G
S
+0.9V_DDR_VTTP
12
PC131
10U_1206_6.3V7K~D
@
Design current 1.05A for +0.9V_DDR_VTTP
Peak current 1.5A for +0.9V_DDR_VTTP
RUN_ON <18,34,38,39,42,44>
PJP6
PAD-OPEN4x4m
1 2
PJP7
PAD-OPEN4x4m
+1.8VSUSP
A A
+0.9V_DDR_VTTP
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1 2
PJP12
1 2
PAD-OPEN4x4m
5
+1.8VSUS
(8A,320mils ,Via NO.=16)
+0.9V_DDR_VTT
(3A,200mils ,Via NO.=6)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
+1.8VSUSP/ +0.9V_DDR_VT
Size Document Number Rev
Board Number LA2111
Date: Sheet of
1
45 50, 12, 2004
0.1
8
7
6
5
4
3
2
1
VID 50VID 4
0
H H
1 0
1
G G
MAX1987_VCC
F F
V I D
VID 3
1
1110 1
1
1
1
The C4 Modevoltage
is 0.748V, S2 open
0_0402_5%~D@
PR8
0_0402_5%~D
VID 2
1
0
1
1
PR9
VID 1
1 2
1 2
12
PR71
0_0402_5%~D
E E
MAX1987_VCC
12
12
PR17
PR18
D D
C C
B B
0_0402_5%~D@
PR15
0_0402_5%~D@
12
PR13
0_0402_5%~D
PR79
@
PBOOT voltage seeting up on 1.212V
PR12
PR14
0_0402_5%~D
0_0402_5%~D
@
12
12
12
12
PR74
0_0402_5%~D
PR72
@
0_0402_5%~D
@
DPRSLPVR<22>
CLK_ENABLE#<6>
CLK_ENABLE#<6>
1
0
0_0402_5%~D
0_0402_5%~D
+3VRUN
+3VRUN
12
12
VID 0
0_0402_5%~D@
0
1
1
00
Vcore
1.484
1.308
0.956
0.748
PR26
0_0402_5%~D@
PR25
PR27
100K_0402_1%~D@
1 2
V
VCCP_PWRGD<43>
IMVP_PWRGD<10,22,39>
CLK_ENABLE#<6>
H_PSI#<8>
H_STP_CPU#<6,22>
12
PC42
270P_0402_25V8K~D
PR22
100K_0402_1%~D@
1 2
12
12
PR23
100K_0402_1%~D@
1 2
DPRSLPVR<22>
PC2
0.22U_0603_16V7K~D
12
PR64
10K_0402_5%~D
@
VID5<8>
VID4<8>
VID3<8>
VID2<8>
VID1<8>
VID0<8>
PR1 0_0402_5%~D@
PR83 0_0402_5%~D
PR84 0_0402_5%~D
RUNPWROK<18,35,39,43>
12
12
PR3
100K_0402_1%~D
12
PC47
PR7
20.5K_0402_1%~D
13
D
PQ8
2
G
S
13
D
PQ18
2
G
S
+3VRUN
12
PR66
PR65
1.91K_0603_1%~D
12
0_0402_5%~D@
12
12
PR4 0_0402_5%~D
MAX1987_REFMAX1987_REF
12
PR20
15K_0402_1%~D
@
100P_0402_50V8K~D
2
G
2N7002_SOT23~D@
2N7002_SOT23~D@
CPU_PWR_SRC
1
+5VRUN
PQ20
5
PQ21
D8D7D6D
IRF7821_S08~D
S1S3G
S
4
2
5
PQ6
D8D7D6D
IRF7832_SO8~D
S1S3G
S
4
2
5
D8D7D6D
PC61
S1S3G
S
4
2
5
PQ3
D8D7D6D
IRF7832_SO8~D
S1S3G
S
4
2
12
PR63
10_0805_5%~D
MAX1987_VCC
12
PC44
12
12
PR88
10K_0402_1%~D
10K_0402_1%~D
22
23
24
25
26
27
28
29
30
8
7
6
5
4
3
12
21
44
43
9
12
14
PR85
VID5
VID4
VID3
VID2
VID1
VID0
10
11
2
1
12
13
D
S
12
12
PR82
PR19
36K_0402_5%
@
30.1K_0402_1%~D
PQ7
2N7002_SOT23~D@
13
D
PQ17
2
2N7002_SOT23~D@
G
S
1U_0603_10V6K~D
PU3
SYSOK
IMVPOK
CLKEN#
D5
D4
D3
D2
D1
D0
S2
S1
S0
B2
B1
B0
PSI#
DPSLP#
SUS
SHDN#
CCV
REF
ILIM
TON
TIME
12
VCC
POS15NEG
PR5
1.24K_0603_1%~D
PR6
100K_0402_1%~D
+5VRUN
36
42
VDD
V+
32
BSTM
34
DHM
33
LXM
35
DLM
45
CMP
46
CMN
48
CSP
47
CSN
20
OAIN+
19
OAIN-
17
CCI
18
FB
39
DHS
40
LXS
38
DLS
41
BSTS
37
PGND
13
GND
31
DD0#
MAX1987ETM_TQFN48~D
16
12
12
PC5
Remote Vcore sense
PC43
470P_0402_50V7K~D
1 2
PR2
1M_0402_1%~D
1 2
12
10U_1206_6.3V7K~D
CPU_PWR_SRC
3.01K_0402_1%~D
PR110
12
PR67
21
PR10
2.2_0603_5%~D
1 2
0_0603_5%~D
1 2
12
+VCC_CORE
1 2
1K_0402_1%~D
1 2
1K_0402_1%~D
1 2
1K_0402_1%~D
1 2
1K_0402_1%~D
3.01K_0402_1%~D
RB751V-40_SOD323~D
PD1
RB751V-40_SOD323~D
PR93
PR102
PR106
PR103
PR105
12
PR21
2.2_0603_5%~D
PD2
12
PC6
0.1U_0603_25V7K~D
PC4
0.1U_0603_25V7K~D
PR95
0_0603_5%~D
1 2
12
2 1
+5VRUN
IRF7821_S08~D
PQ19
5
PQ22
D8D7D6D
IRF7821_S08~D
S1S3G
S
4
2
5
D8D7D6D
PQ5
IRF7832_SO8~D
S1S3G
S
4
2
5
IRF7821_S08~D
D8D7D6D
S1S3G
S
4
2
5
PQ4
D8D7D6D
IRF7832_SO8~D
S1S3G
S
4
2
12
PC60
0.1U_0603_25V7K~D
0.7U_ETQP2H0R7BFL_29A_20%~D
PD3
2 1
EC31QS04~D
@
12
12
PC55
PC64
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
0.7U_ETQP2H0R7BFL_29A_20%~D
1
12
PC56
PC63
2
2200P_0402_50V7K~D
10U_1210_25V7K~D
PL7
12
CPU_PWR_SRC
1
1
PC58
PC59
2
2
10U_1210_25V7K~D
10U_1210_25V7K~D
PL6
1 2
PD4
2 1
EC31QS04~D
@
1
PC57
PC54
2
2
10U_1210_25V7K~D
10U_1210_25V7K~D
OutputCapatitors inH/W, ESR=3mohms
PR28
0.001_2512_5%~D
1 2
1
2
10U_1210_25V7K~D
PL16
FBM-L18-453215-900LMA90T_1812~D
12
12
PC62
0.1U_0603_25V7K~D
+VCC_CORE
12
PC71
0.01U_0402_25V7K~D
PR29
0.001_2512_5%~D
1 2
+VCC_CORE
PC72
PWR_SRC
12
0.01U_0402_25V7K~D
ChangePR82:30.1k. DeletePR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23
and PR19for BANIAS and DOTHAN
PR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23and PR19 are only for YONAHCPU.
A A
TRANSITION TIMING:
(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us
(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/us
(c): EXIT SUSPEND (SUS=LOW, RUNPWROK=HIGH): 24.7mV/us
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8
7
6
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
2
CompalElectronics, Inc.
+VCORE
LA-2171
46 50, 12, 2004
1
0.2
5
4
3
2
1
+DC_IN discharge path
PQ14 SI4825DY_SO8~D
8
1 2
13
D
S
12
PR53
PR151
59K_0402_1%~D
G
PR154
7
5
PR73
10K_0402_5%~D
PQ11
2N7002_SOT23~D
PR77
0_0402_5%~D@
PDS
PR51
150K_0603_1%~D
1 2
1 2
+VCHGR
PR153
10K_0402_1%~D
1 2
TH
13
D
S
PR152
10K_0402_1%~D
12
PC112
1U_1206_25V7K~D
MAX1535_CCS
MAX1535_CCI
MAX1535_CCV
MAX1535_DAC
CHVREF
TM
1 2
1 2
+DC_IN
D D
1
PC46
2
10U_1210_25V7K~D
C C
12
12
PR134
0_0402_5%~D
PR133
0_0402_5%~D
12
12
PC104
B B
PC105
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
ACAV_IN<35>
Vin Detector
High 17.859 V
Low 16.988 V
12
PR132
10K_0402_5%~D
12
12
12
PC109
PC114
PC103
1U_0805_10V7K~D
0.1U_0603_25V7K~D
1000P_0402_50V7K~D
2
G
13
D
PQ13
S
2N7002_SOT23~D
PR70
10K_0402_5%~D
2
G
PR52
20K_0603_1%~D
PC32
0.01U_0402_25V7K~D
1 2
681K_0402_1%~D
ACAV_IN
+5VALW
PC118
1 2
1U_0805_10V7K~D
Connect GND side of PC150, PC151, PC152 to GND through 1 via.
PQ33
2N7002_SOT23~D
PD18
CHG_PBATT<35>
2 1
RB751V-40_SOD323~D
2
1 2
100K_0402_5%~D
1 2
AC_IN
PC122
1500P_0402_50V7K~D
1
2
36
4
PR81
100K_0402_5%~D
1 2
PDL
1 2
Adress :12H
PDS
12
PR139
CSSP
PDS
SRC
DCIN
ACIN
ACOK
CCS
CCI
CCV
DAC
REF
BATT
VDD
THM
INT
PDL
I.C.
29
5
CSSP
GND
CSSN
28
CSSN
GND18IMAX
PR128
182K_0402_1%~D
PC123
1 2
DHIV
LDO
DLOV
DHI
DLO
PGND
CSIP
CSIN
SCL
SDA
VMAX
MAX1535AX_QFN32~D
10
280K_0402_1%~D
1 2
2
PC117
1
0.1U_0603_25V7M~D
@
PU7
31
27
1
3
32
6
7
8
11
4
19
12
13
16
30
17
0_0402_5%~D
1 2
0.1U_0603_25V7M~D
@
25
2
24
26
23
22
21
20
15
14
9
0.01_2512_1%~D
1 2
12
PC124
1U_0805_25V4Z~D
PR163
DLOV
0_0805_5%~D
PR130
PR76
DLO
CHVREF
12
PWR_SRC+SDC_IN
PR150
0_0402_5%~D
1 2
ACAV_IN
PZD1
12
RLZ4.3B_LL34~D
PR127
10K_0402_1%~D
1 2
PR160
1 2
12
PBAT_SMBCLK <35,42>
PBAT_SMBDAT <35,42>
VMAX=2.625V
Maximum charger voltage=13.12V
IMAX=1.6135V
Maximum charger current=8A
SI4835DY_SO8~D
PC108
1U_0603_6.3V6M~D
1 2
PC126
0.1U_0603_25V7K~D
33_0402_5%~D
12
CSIP
CSIN
PR129
1 2
182K_0402_1%~D
102K_0402_1%~D
PL19
FBM-L18-453215-900LMA90T_1812~D
36
PQ28
578
578
PC115
3 6
1 2
1000P_0402_50V7K~D
@
CHVREF
12
PR131
12
Reserver H-side MOSFET
36
241
MAX1535_LX
241
241
578
5.6U_CEP125-5R6MC_8.8A_20%~D
PD16
EC31QS04~D
@
2 1
PQ31
FDS6670S_SO8~D
1 2
PC127
0.1U_0603_25V7K~D
@
1 2
0_0402_5%~D
1 2
PQ26
SI4835DY_SO8~D@
PR159
PC125
PL12
@
PQ9 SI4825DY_SO8~D
1
2
3 6
1
1
PC102
1 2
0.1U_0805_50V7M~D
PR50
0.01_2512_1%~D
1 2
0_0402_5%~D
1 2
10U_1210_25V7K~D
PR158
1
PC101
PC100
2
2
2
10U_1210_25V7K~D
10U_1210_25V7K~D
1
PC35
PC30
1 2
0.1U_0603_25V7K~D
PC36
2
10U_1210_25V7K~D
10U_1210_25V7K~D
12
PC88
PC89
2200P_0402_50V7K~D
CHG_CS
1 2
0.1U_0603_25V7K~D
8
7
5
4
PDL
+VCHGR
1
1
PC37
2
2
10U_1210_25V7K~D
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Charger
LA-2171
47 50, 12, 2004
1
0.2
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DELL CONFIDENTIAL/PROPRIETARY
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
1
31&32 Change U162
2
3
4
5
6
7
8
C C
9
10
11
12
13
14
15
16
B B
17
18
19
18
25
28
40
27
31&32
33
1
40 Compal01/07/04 X01Pop CLP4,5,10,11,13 and depop CLP18For EMI requirement.
22
37
10
6
7&10
1 Cover page 01/29/04 Compal Change schematic revision fromX00 to X01. X01
Title
Cardbus
VGA/B &
DVI CONN.
SATA Bridge Dell
Subwoofer
LED/B
Amplifier &
Phone JACK
LOM
Cardbus
PAD & ME &
spare parts
ICH6(3/4)
LED/B &
TV TUNER
PAD & ME &
spare parts
Alviso(1/5) 01/28/04
Clock Generator
Dothan(1/2)
&Alviso(1/5)
Internal K/B
& LCM CONN.
10/15/03
10/16/03
10/16/03
10/16/03
10/16/03
10/17/03
10/17/03
10/17/03
10/17/03
01/08/04
01/08/04
01/08/04
01/28/0432 CardBus(2/2) Fixed SD card issue.
01/28/04
01/28/04
01/29/04
Owner
Change cardbus controller to TI PCI4515.Dell
Dell Add DVI connector. Add JDVI
Add SATA toPATA circuit. Add page25
Dell
Dell
Dell
Dell
Dell
Dell
Dell
Dell
Add subwoofer circuit.
Removed IR circuit. Delete U52
Removed internal MICcircuit.
Change LAN controller (U164) from5751M to4401.
Add pop optionfor the 5705 like Kapalua/Lindberghboard.
Depop 1394 choke, L142 andpop bypass
resistors, R1025, R1026, R1027, R1028
Change schematic revision from M00 to X00.
Connected PCIE channel1 to TV-Tuner connector.
Connected TV tunersignals.
Compal40
Compal
Dell
Dell
Dell
From IntelMessage.
Per Intel andICS recommendation.
Per the Intel Check list 1.301
Compal36 The BIOS debug connector is for bring up only. Delete JDBUG.
Add page28
Delete T4,T5,T29,T30 and add C661,C662
Add C663,C664
The pin11 of JSD need to be connected to GND
and pin12 need to be connected to U17 pin b3.
Change C124 from 220pF to 0.1uF and move capacitor
as close as possible to the HVREF pin (pin J11 of U15).
Connect the SATA clock toSRC4 and connect the VGAclock to SRC1.
Change R397 and R114 to 75 ohm.
20
21
22
23
24
A A
25
37 02/02/04 Compal X01
37
6 Dell02/04/04Clock Generator Added PCIEclock connection to JTUNR Added R551, R552, R553, R554
PAD & ME &
spare parts
LED/B &
TV TUNER
LED/B &
TV TUNER
01/30/04 Compal Delete CLP5 and addH32 X0140
This cliphave interferenced with screw hole.
The indicative LED of HDD doesn't work well. Remove R12 and connect the pin3of Q2 to +3VRUN.
02/04/04 Dell Changed JTUNR pin definitions Added PCIRST#,CLK_PCIE_TV/TV# signals
Solution Description Rev.Page#
M00
M00
M00
M00
M00
X00
X00
X00
X00Cover page
X01
X01
X01Pop H12,H13,H14,H17,H20,H21,H26,H27Added MEstandoff.
X01
X01
X01
X01
X01
X01Compal01/29/04Macallen(2/2)35 Board ID X01. Pop R318 and depop R319.
X0134 01/29/04 CompalMacallen(1/2) Reserved a inverter for serial port debug. Add U36 andT13.
X01
X01
Request
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
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DELL CONFIDENTIAL/PROPRIETARY
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Changed-List History
LA-2171
48 50, 12, 2004
1
0.2
5
4
Version Change List ( P. I. R. List )
3
2
1
Request
Item Issue DescriptionDate
D D
C C
B B
Page# Title
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
13&23
Owner
37
35
5
38 Power control
18
27
37
28 USB2.0 PORT
39 Dell02/09/04
37
38 Power control 02/10/04 Dell Decrease Rdson for+1.5SUS to +1.5RUN switching FET. Add Q55 and nopop Q35. X01
35 02/11/04Macallen(2/2) Delete RN28 and RN29.
22 02/11/04 Dell Added R90, R91 (0 ohmpop option)
LED/B &
TV TUNER
02/05/04 Dell Changed JTUNR PCIRST# to PLTRST# or PLTRST_DELY# Pop Option Added R555, R556
Macallen(2/2) 02/05/04 Dell
SMBus Diagram
Alviso(4/5)
&ICH6(4/4)
02/05/04
02/05/04
02/06/04
VGA/B &
DVI CONN.
Subwoofer
LED/B &
TV TUNER
02/06/04
02/06/04
02/06/04
02/06/04
Power
Sequence
LED/B &
TV TUNER
02/09/04 Dell
ICH6(3/4)
02/11/04 Dell38 Power control X01
VGA/B &
DVI CONN.
02/11/04 Compal
02/11/04 X01Compal Change the footprint of Q13,Q19,Q21,Q28,Q35,Q47,Q52,Q7Reduce the pad width bycompal's DFX requirement.
Improves the rise time of the SMBUS signals. Allbatteryvendors and
Compal agree tothe change per Youseff Dauo.
Dell Add a SMbus device address table in the Schematic.
Panasonic has phase out SGA2022114L.
Dell
Dell
Dell
Dell
Dell
SUSPWROK_5V no longer controlsthe switching FET for +3VSUS.
Add bulk capacitor to G_PWR_SRC.
Add 0 ohm pop options to make it easier to
switch between bothsubwoofer amps.
TV tuner solution for X01 gerber.
Change the single USB portin the back to dual stack.
Delays 1.5VSUS power good sothat it comes upafter 1.5VSUS
is completelyup.
Add EMIpi-filters for 5 AV signals. X01
Dell
Backout workaround for SMSC errata item.Connect
CLK_SM2 and DAT_SM2 appropriately.
SIO_EXT_WAK# signal leakage to+3VRUN via GPI12 of
ICH6M when system is into S3 status.
Add drainFETs for +1.5VSUS and +1.8VSUS. FETs to drainpower
plane when system isturned off.
Dell02/11/0418
ME team decidedto use JAE DVI-I connector (with shielding) instead of
Suyin DVI-D connector (without shielding) for EA/SST build this time.
System auto power on issue.
Change battery SMBUSpullups, R336 and R526, from22K to 8.2k. X01
Removed R256 and R257.
Add C647, but nopop.
Add R12,R79 for pop options.
Change JTV1,JTV2 and JTUNR pindefinitions.
JTV1 is a 8pinMINI DIN CONN.
Add L14,L17,C88,C87 and change the P/N of JUSB1.
Add L73,L74,L75,L76,L88,C438,C442,C419,C420,C431,C433,C434,C424
,C439,C610
Added R87~R89, Q31, Q34,Q48
Change the P/N of JDVI
Change C609 from 1uFto 0.1uF and R504 from100K to 10K ohm.
Solution Description Rev.
X01
X01
X01Change C510,C514 from SGA2022114L to SGA2022110L.Compal
X01
X01
X01
X01
X01
X01Change R482 from 330ohmto 10K. Change R490 from 10k to 100K.
X01
X01
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X0135 Macallen(2/2)
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DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Changed-List History
LA-2171
49 50, 12, 2004
1
0.2
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Version Change List ( P. I. R. List ) for Power Circuit
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1
Request
Page#
Item Issue DescriptionDate
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D D
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42 PSID & +3VX 2003/10/15 Compal
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44 +15VP 2003/11/4 Compal +15VP current rating is not enoughfor subwoofer Use MB3800 Boost ICto genearte +15VP from +5VSUSP X00
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47 Charger Compal2003/11/5
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44 +15VP 2003/12/11 Compal
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45 2004/2/1 DELL+1.8VSUSP X01Change DDRII DC-DC solutionfor cost down. Using MAXIM MAX8550 .
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45 2004/2/5 Compal+1.8VSUSP Voltage divider setting iserror, theFB regulate on 0.7V.
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C C
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46 +VCC_CORE 2004/2/5 Compal Choke height is over mechnical height limitation X01Change PL6 andPL7 from 0.6U_HK_AE26A0R6 to 0.7U_ETQP2H0R7BFL.
46 +VCC_CORE 2004/2/6 Compal EMI broad band test is over 1~2 db Change PR10 and PR21 from0_0603_5% to 2.2_0603_5%. X01
4145PS_ID 2004/2/11 DELL Open issue #60 ChangePS_ID pullup resistor, PR78, from1.5K to 2.2K Change PR78 from 1.5K_0603_1% to 2.2K_0402_5%. X01
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Title
Owner
Compal2003/10/14Charger selector49
Compal2004/2/143
+0.9V_DDR_VTTP 2004/2/11 DELL
Modify charger selector circuit.
Modify PSID circuit same as Nimitas. And add current limit resistor on
RTC charger.
That has leakage current frombattery goes through PQ22 and PQ44 to
DC_IN.
Test +15VP on Demonboard.The output ripple voltage islarge
and improve efficiency.
VCCP_1p05VP has two 330uF caps on it(PC10, PC11), Laguna
only has one. Do we need two?
Open issue#63 Please add a 10uf, 1206 package capacitor at the output
of PU5 pin12, +0.9V_DDR_VTTP.
Need to discuss.
Add ESD solution on PSID, and limit RTC charge current. 0.0
Move Adaptor current sense PR144 after PQ24 andbefore PWR_SRC.
That is same as Nimitaz.
Add PC128 10U_1206_25V,change PQ30 from SI2302DS toSI3442DV,
change PR157 form 392_0603_1% to 150_0603_1%, no-popPC96.
Can de-populate PC11,and test is OK. X01+VCCP_1P05VP
Change PR116 from 45.3K_0402_1% to 27.4K_0603_1%.
Change PC22 from 1U_0603_6.3V to 4.7U_0805_6.3V
Add andreserve PC131 10U_1206_6.3V7K. X01
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Solution Description Rev.
0.0
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DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size DocumentNumber Rev
Date: Sheet of
Compal Electronics, Inc.
Power-Changed-List History
LA-2171
1
50 50, 12, 2004
0.2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
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