Compal LA-2151, Inspiron 6000 Schematic

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

COMPAL P/N :

MODEL NAME :

PCB NO :
Revision :

2 2

LA2151

1.0 (DELL: A00)

TOBAGO

45128331001/45128331002

TOBAGO Schematics Document

uFCBGA/uFCPGA Mobile Dothan
Intel Alviso + ICH6M

2004-11-03

REV : 1.0 (DELL: A00)

3 3

4 4

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

TOBAGO-LA2151

151Wednesday, November 03, 2004

E

0.6

of

A

Compal confidential

Model : Tobago

B

C

D

E

Block Diagram

FAN

1 1

+5VRUN

page 15

VGA Board

VGA CONN

page 18

LVDS CONN

on VGA Board

2 2

IDSEL:AD19
(PIRQB,D#,GNT#3,REQ#3)

Minipci CONN

WIRELESS

+3VRUN
+3VSUS
+5VRUN

page 33

SD card

3 3

SLOT

page 32

CardBus
& 1394

R5C841

+3VSUS

page 31,32

Card Bus

SLOT CONN

page 32

1.5V/1.05V

page 43

1.8V/0.9V

VCORE

page 44

page 45

DC IN

page 40

BATT IN/2.5V

page 41

Thermal

GUARDIAN
EMC6N300

+3VSUS

TV OUT

CRT CONN

LVDS CONN

on M/B Board

+3VRUN 33MHz

IDSEL:AD17
(PIRQC,D#,GNT#1,REQ#1)

48MHz

USB[3]

1394

page 31

Power Sequence
& RTC BATT

Power On/Off
SW & LED

page 15

page 20

page 20

page 19

PCI BUS

IDSEL:AD16
(PIRQC#,GNT#4,REQ#4)

BCM4401KQL

+3VLAN

RJ45

page 38

page 39

PCI-E 16X

CRT Signal

Internal LVDS

page 30

page 30

SST39VF080

+3VALW

+VCCP (1.05V)
+VCC_CORE

+1.5VRUN
+1.8VSUS
+VCCP
+3VRUN
+2.5VRUN

+3VRUN
+3VSUS
+1.5VRUN
+1.5VSUS
+2.5VRUN

X BUS

EC DEBUG

+3VALW

Pentium-M

Dothan

uFCPGA CPU

+VCCP 400/533 MHz

1257BGA

DMI

+1.5VRUN
100MHz

LPC BUS

LPC47N354
MACALLAN III

+3VRUN
+3VALW

page 36

478pin

System Bus

INTEL

Alviso

page 10,11,12,13,14

INTEL
ICH6-M
609 BGA

page 21,22,23,24

+3VRUN
33MHz

page 34,35

page 7,8

H_D#(0..63)H_A#(3..31)

Int.KBD

page 36

Memory BUS
(DDR2)

48MHz

24.576MHz

SATA

88SA8040

+1.8VRUN
+3VRUN

page 25

Parallel ATA

+5VHDD

page 25

CPU ITP Port

+VCCP

USB[4,5,6,7]

ATA100

CD-ROM

+5VMOD

page 7

+1.8VSUS 400MHz

AC-LINK

IDE

+3VRUN

page 25

+VDDA

AMP & INT.
Speaker

+5VRUN +5VRUN

page 27

Clock Generator

CY28411ZCT

+3VRUN

DDRII-DIMM X2

BANK 0, 1, 2, 3

+0.9V_DDR_VTT
+1.8VSUS

AC97 Codec

STAC9751

page 26

HeadPhone &
MIC Jack

page 6

page 16,17

USB Ports X4

+5VSUS

page 28

MDC

+3VSUS

page 29

RJ11

page 27

Cable

4 4

CHARGER

page 46

A

3V/5V/15V

page 42

DC/DC Interface

page 37

B

LCM SW & Touch
Pad & LID SW

+5VRUN
+3VALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

page 29

C

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

TOBAGO-LA2151

251Monday, October 18, 2004

E

of

0.6

5

Ceramic Capacitors :

4

3

TABLE

PCI

2

1

0.1U_0402_6.3VXX

D D

Tolerance
Temperatur e Characteristics
Rated Voltage

PCI DEVICE

CARD BUS
LAN

IDSEL

AD17

AD16

REQ#/GNT#

1

4

PIRQ

D,C

C

Package Size
Value

MINI PCI

AD19

3

PM TABLE

+5VRUN

Tantalum or Polymer Capacitors :

power
plane

10U_D2_10VX_R45

C C

Low ESR Mark : 45 m ohm
Tolerance
Rated Voltage
Package Size
Value

State

S0

S1

S3

S5 S4/AC

S5 S4/AC don't exist

+3VALW
+5VALW

+3VSUS
+5VSUS
+1.8VSUS
+1.5VSUS

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

+3VRUN
+1.8VRUN
+0.9V_DDR_VTT
+1.5VRUN
+VCC_CORE

+VCCP

+15V

D,B

ON

ON

OFF

OFF

OFFOFF

Capacitor Spec Guide:
Temperature Characteristics:

B B

A A

Symbol

CODE

Tolerance:

Symbol
CODE

Z5U

8

9

COG SJ

HI J

UK

UJ

A

+-0.05PF

+-0.1PF

M

K

+-20%

+-10%

+-30%

Z5V

X6SNPO

SL

N

A

1

B

2

Z5P

B

BJ

K
X5S

C

+-0.25PF

P

+100,-0%

4

5

G

X

6

X5R

SH

H

+-3%

Z

+80,-20%

30

Y5V

Y5U X7R

C
CH

D

+-0.5PF +-1PF

Q

+20,-10%

+30,-10%

Y5P

DEFG
CJ

CK

F

+-2%

V

+40,-20%

7

J

+-5%

NOTE1:
@XX : Depop component

1@XX : Pop for Integrated Graphic
2@XX : Pop for External Graphic

USB

TABLE

USB PORT#

0
1
2

3
4,5
6,7

DESTINATION

NC

NC

Blue tooth

PCMCIA
REAR

SIDE

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

TOBAGO-LA2151

351Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+5VALW

D D

ADAPTER

+3VALW

PWR_SRC

FDS4435 G_PWR_SRC

+5VRUN

BATTERY

MAX1999 MAX1987 MAX1845 MAX8550

C C

SUS_ON

+5VSUS

B B

HDDC_EN#

RUN_ON

PL8

793333

AUDIO_AVDD_ON

(Option)

SUS_ON

SI4810

RUN_ON

+3VSUS

RUNPWROK

+VCC_CORE

RUN_ON

MAX1845_VCC

+1.5VSUS

SI4810

RUN_ON

(Integrated)

+VCCP

RUN_ON_D

(Discreted)

RUNPWROK

SUSPWROK_5V

+1.8SUS +0.9V_DDR_VTT

SI4810SI3456SI3456

RUN_ON

SUSPWROK_5V

L47

+3VRUN

MAX1806 +1.8VRUN

RUN_ON

+1.5VRUN

+2.5VRUN

+5VHDD +5VRUN VDDA

A A

+15V

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail

TOBAGO-LA2151

451Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+3VRUN

ICH_SMBCLK

D D

ICH6-M

ICH_SMBDATA

+3VSUS

7002

7002

CLK_SCLK

CLK GEN.

CLK_SDATA

DIMM0

CLK_SMB
DAT_SMB

C C

+3VALW

GUARDIAN

DIMM1

24C04

SIO

Macallan III

B B

SBAT_SMBCLK
SBAT_SMBDAT

+5VALW

PBAT_SMBCLK
PBAT_SMBDAT +5VALW

INVERTER

BATTERY

CHARGER

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY

TOBAGO-LA2151

551Monday, October 18, 2004

1

0.6

of

5

+3VRUN

R270

D

ICH_SMBDATA<23>

D D

ICH_SMBCLK<23>

ICH_SMBDATA

+3VRUN

ICH_SMBCLK

1 3

2

2

1 3

D

S

Q36
2N7002_SOT23~D

G

G

Q38
2N7002_SOT23~D

S

D
1

3

G

S

2

2N7002

FSC FSB FSA CPU

CLKSEL0 CLKSEL2CLKSEL1

C C

000

0

0

00

1

11

*

1

1

0

1

1

1

0

00

1

0

111

MHz

266

133

200

166

333

100

400

SRC
MHz

100

100

100

100

100

100

100

RESERVED

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

12

12

R275

2.2K_0402_5%~D

2.2K_0402_5%~D

C68

CLK_SDATA

CLK_SCLK

1

1

2

2

C61

4.7U_0805_10V4Z~D

0.047U_0402_16V4Z~D

Table : ICS954201BG

R531

1 2

1 2

0_0402_5%~D

5

12

+VCCP

+VCCP

@

R342
1K_0402_5%~D

1 2

@

R305
0_0402_5%~D

1 2

@

R353
1K_0402_5%~D

1 2

1 2

R354
0_0402_5%~D

@

R364
0_0402_5%~D

1 2

1 2

R330

0_0402_5%~D

MCH_CLKSEL0 <10>

MCH_CLKSEL1 <10>

B B

8.2K_0402_5%~D

CLKSEL0

CPU_BSEL0<8>

A A

CPU_BSEL1<8>

R329
0_0402_5%~D

R343

4

1

C326

0.1U_0402_16V4Z~D

CLK_SDATA <11,16,17>

CLK_SCLK <11,16,17>

CK_VDD_48CK_VDD_A CK_VDD_REF

1

1

2

2

C50

CLK_ICH_48M<23>

CLK_PCI_PCM<31>

CLK_PCI_SIO<34>

CLK_PCI_MINI<33>

CLK_PCI_LOM<30>
CLK_PCI_ICH<21>

C51

4.7U_0805_10V4Z~D

27P_0402_50V8J~D

27P_0402_50V8J~D

+3VRUN

0.047U_0402_16V4Z~D

C329

12

C333

12

CLK_ICH_48M CLKSEL2
CLKSEL1
CLKSEL0
CLK_CODEC_14M
CLK_PCI_PCM PCI_PCM

CLK_PCI_LOM PCI_LOM
CLK_PCI_ICH P CI_ICH

R271
10K_0402_5%~D

1 2

CLKSEL2

R278
10K_0402_5%~D

@

1 2

4

2

Place crystal within
500 mils of CK410

X2

12

14.31818MHz_20P_1BX14318CC1A~D

1 2

L40

BLM21PG600SN1D_0805~D

BLM21PG600SN1D_0805~D

1

2

CLK_XTAL_IN

CLK_XTAL_OUT

R532 12.1_0402_1%~D

R302 33_0402_5%~D
R294 33_0402_5%~D
R293 33_0402_5%~D
R277 33_0402_5%~D
R331

33_0402_5%~D

CK_VDD_MAIN2

1 2

L32

C52

0.047U_0402_16V4Z~D

R298 33_0402_5%~D

@

12
12
12
12
12
12

+3VRUN

10K_0402_5%~D

CK_VDD_MAIN+3VRUN

1 2

R274

1_0603_5%~D

1 2

R273

2.2_0603_5%~D

12

PCI_SIOCLK_PCI_SIO
PCI_MINICLK_PCI_MINI

R538

@

12

100K_0402_5%~D

1 2

R316

1 2

R362 475_0603_1%~D

PCICLKF0
CLK_SCLK

CLK_SDATA

CLKIREF

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CK_VDD_REF

CK_VDD_48

3

CK_VDD_MAIN

2

C402
10U_0805_10V4M~D

1

2

C308
10U_0805_10V4M~D

1

U16

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

VDD_CPU

48

VDD_REF

11

VDD_48

50

XTAL_IN

49

XTAL_OUT

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

5

PCI5

4

PCI4

3

PCI3

56

PCI2/REQ_SEL

9

PCIF1/SELPCIEX_LCDCLK#

8

PCIF0/ITP_EN

46

SCLOCK

47

SDATA

39

IREF

13

VSS_48

29

VSS_SRC

2

VSS_PCI0

45

VSS_CPU

51

VSS_REF

6

VSS_PCI1

ICS954226AG_TSSOP56~D

1

C384

0.1U_0402_16V4Z~D

2

1

C344

0.1U_0402_16V4Z~D

2

R401

2.2_0603_5%~D

1 2

1

C58

0.1U_0402_16V4Z~D

2

1

C330

0.1U_0402_16V4Z~D

2

CK_VDD_A

VDD_A
VSS_A

PCI_STOP#

CPU_STOP#

CPU1

CPU1#

CPU0

CPU0#

CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0/LCDCLK_SS

SRC0#/LCDCLK_SS

DOT96

DOT96#

VTT_PWRGD#/PD

REF

2

1

C64

0.1U_0402_16V4Z~D

2

1

C389

0.1U_0402_16V4Z~D

2

Place near each pin
W>40 mil

Place near CK410

37
38

H_STP_PCI#

55

H_STP_CPU#

54

MCH_BCLK

41

MCH_BCLK#

40

CPU_BCLK

44

CPU_BCLK#

43

36

CPU_ITP# CLK_CPU_ITP#

35

33
32

MCH_3GPLL

31

MCH_3GPLL# CLK_MCH_3GPLL#

30

PCIE_SATA CLK_PCIE_SATA

26

PCIE_SATA#

27

24
25

PCIE_VGA

22

PCIE_VGA#

23

PCIE_ICH CLK_PCIE_ICH

19

PCIE_ICH#

20

DOT96_SSC

17

DOT96_SSC#

18

DOT96 DREFCLK

14
15

CLK_ENABLE#

10

CLKREF

52

H_STP_PCI# <23>

H_STP_CPU# <23,45>

1 2

R348 33_0402_5%~D

1 2

R359 33_0402_5%~D

1 2

R321 33_0402_5%~D

1 2

R337 33_0402_5%~D

1 2

R368 33_0402_5%~D

1 2

R376 33_0402_5%~D

1 2

R397 33_0402_5%~D

1 2

R402 33_0402_5%~D

1 2

R394 33_0402_5%~D

1 2

R400 33_0402_5%~D

1 2

R382 33_0402_5%~D

1 2

R386 33_0402_5%~D

1 2

R366 33_0402_5%~D

1 2

R375 33_0402_5%~D

1 2

R524 33_0402_5%~D1@

1 2

R525 33_0402_5%~D1@

1 2

R345 33_0402_5%~D

1 2

R356 33_0402_5%~D

1 2

R266 12.1_0402_1%~D

1 2

R259 12.1_0402_1%~D

1 2

R250 12.1_0402_1%~D

1 2

R301 12.1_0402_1%~D@

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITPCPU_ITP

CLK_MCH_3GPLL

CLK_PCIE_SATA#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH#

DREFCLK#DOT96#

CLK_ICH_14M
CLK_CODEC_14M
CLK_SIO_14MCLKSEL1
CLK_SSC_IN

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

CLK_CPU_ITP
CLK_CPU_ITP#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_VGA
CLK_PCIE_VGA#
DREFCLK
DREFCLK#
DREF_SSCLK
DREF_SSCLK#

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_MCH_3GPLL <12>

CLK_MCH_3GPLL# <12>

CLK_PCIE_SATA <22>

CLK_PCIE_SATA# <22>

CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>

CLK_PCIE_ICH <23>
CLK_PCIE_ICH# <23>

DREF_SSCLK <10,11>
DREF_SSCLK# <10,11>

DREFCLK <10>
DREFCLK# <10>

CLK_ENABLE# <11,45>

CLK_ICH_14M <23>
CLK_CODEC_14M <26>
CLK_SIO_14M <34>
CLK_SSC_IN <11>

Compal Electronics, Inc.

Clock Generator

TOBAGO-LA2151

1

R369 49.9_0402_1%~D
R377 49.9_0402_1%~D
R349 49.9_0402_1%~D
R360 49.9_0402_1%~D
R322 49.9_0402_1%~D
R338 49.9_0402_1%~D

1 2

R392 49.9_0402_1%~D

1 2

R403 49.9_0402_1%~D

1 2

R381 49.9_0402_1%~D

1 2

R385 49.9_0402_1%~D

1 2

R365 49.9_0402_1%~D

1 2

R374 49.9_0402_1%~D

1 2

R393 49.9_0402_1%~D

1 2

R399 49.9_0402_1%~D

1 2

R344 49.9_0402_1%~D

1 2

R355 49.9_0402_1%~D

1 2

R522 49.9_0402_1%~D1@

1 2

R523 49.9_0402_1%~D1@

651Monday, October 18, 2004

1

12
12
12
12
12
12

0.6

of

5

4

3

2

1

H_A#[3..31]<10>

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

RN28

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22

H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CPU_ITTP
CPU_ITTP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#

ITP_BPM#4
ITP_BPM#5

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

D D

H_REQ#[0..4]<10>

H_ADSTB#0<10>

C C

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

R422

56_0402_5%~D

1 2

+VCCP

B B

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_ADSTB#1<10>

@

2 3
1 4

0_0404_4P2R_5%~D

CLK_CPU_BCLK<6>
CLK_CPU_BCLK#<6>

H_ADS#<10>

H_BNR#<10>

H_BPRI#<10>

H_BR0#<10>

H_DEFER#<10>

H_DRDY#<10>

H_HIT#<10>
H_HITM#<10>

H_LOCK#<10>
H_RESET#<10>

H_RS#[0..2]<10>

H_TRDY#<10>

ITP_DBRESET#<38>

H_DBSY#<10>

H_DPSLP#<22>
H_DPRSTP#<22>

H_DPWR#<10>

H_PROCHOT#<35>
H_PWRGOOD<22>

H_CPUSLP#<10,22>

@

T37 PAD~D
T38 PAD~D

@

H_THERMDA<15>
H_THERMDC<15>
H_THERMTRIP#<15>

5

JCPUA

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

TYCO_1612364-1~D

Dothan

ADDR GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

+VCCP

+VCCP

4

DATA GROUP

LEGACY CPU

R398
56_0402_5%~D

1 2

R423
200_0402_5%~D

1 2

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT0
LINT1

STPCLK#

SMI#

H_THERMTRIP#

H_PWRGOOD

H_D#0H_A#3

A19

H_D#1

A25

H_D#2

A22

H_D#3

B21

H_D#4

A24

H_D#5

B26

H_D#6

A21

H_D#7

B20

H_D#8

C20

H_D#9

B24

H_D#10

D24

H_D#11

E24

H_D#12

C26

H_D#13

B23

H_D#14

E23

H_D#15

C25

H_D#16

H23

H_D#17

G25

H_D#18

L23

H_D#19

M26

H_D#20H_A#23

H24

H_D#21

F25

H_D#22

G24

H_D#23

J23

H_D#24

M23

H_D#25

J25

H_D#26

L26

H_D#27

N24

H_D#28

M25

H_D#29

H26

H_D#30

N25

H_D#31

K25

H_D#32

Y26

H_D#33

AA24

H_D#34

T25

H_D#35

U23

H_D#36

V23

H_D#37

R24

H_D#38

R26

H_D#39

R23

H_D#40

AA23

H_D#41

U26

H_D#42

V24

H_D#43

U25

H_D#44

V26

H_D#45

Y23

H_D#46

AA26

H_D#47

Y25

H_D#48

AB25

H_D#49

AC23

H_D#50

AB24

H_D#51

AC20

H_D#52

AC22

H_D#53

AC25

H_D#54

AD23

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AF20

H_D#59

AE21

H_D#60

AD21

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>

H_A20M# <22>

H_FERR# <22>

H_IGNNE# <22>

H_INIT# <22>

H_INTR <22>

H_NMI <22>

H_STPCLK# <22>

H_SMI# <22>

Add pullups for PWRGOOD and THERMTRIP per INTEL

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

H_D#[0..63] <10>

H_RESET#

ITP_TDO

H_DSTBN#[0..3] <10>

H_DSTBP#[0..3] <10>

+VCCP

ITP_DBRESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

R424

22.6_0603_1%~D

1 2

R434

22.6_0603_1%~D

1 2

ITP_BPM#4
ITP_BPM#5
ITP_TCK
CLK_CPU_ITP

CLK_CPU_ITP#

ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

Check ITP connector.

29

JITP

28

VTT1

27

GND6

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

GND7

MOLEX_52435-2891_28P~D

30

@

+3VSUS

+VCCP

+VCCP

+VCCP

R367

150_0603_1%~D

1 2

R415

54.9_0603_1%~D

1 2

R416

54.9_0603_1%~D

1 2

R387

39.2_0603_1%~D

1 2

R417

150_0603_1%~D

1 2

This shall place near CPU

R391

680_0402_5%~D

1 2

R436

27.4_0603_1%~D

1 2

1

C381

0.1U_0402_16V4Z~D

2

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near JITP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

TOBAGO-LA2151

751Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

JCPUB

AE7

VCCSENSE

AF6

VSSSENSE

F26

VCCA0

B1

VCCA1

N1

VCCA2

AC26

VCCA3

P23

VCCQ0

W4

VCCQ1

D10

VCCP

D12

VCCP

D14

VCCP

D16

VCCP

E11

VCCP

E13

VCCP

E15

VCCP

F10

VCCP

F12

VCCP

F14

VCCP

F16

VCCP

K6

VCCP

L5

VCCP

L21

VCCP

M6

VCCP

M22

VCCP

N5

VCCP

N21

VCCP

P6

VCCP

P22

VCCP

R5

VCCP

R21

VCCP

T6

VCCP

T22

VCCP

U21

VCCP

D6

VCC

D8

VCC

D18

VCC

D20

VCC

D22

VCC

E5

VCC

E7

VCC

E9

VCC

E17

VCC

E19

VCC

E21

VCC

F6

VCC

F8

VCC

F18

VCC

E1

PSI#

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AD26

GTLREF

C16

BSEL0

C14

BSEL1

P25

COMP0

P26

COMP1

AB2

COMP2

AB1

COMP3

B2

RSVD

C3

RSVD

E26

RSVD

AF7

RSVD

AC1

RSVD

TYCO_1612364-1~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

+VCC_CORE

H_PSI#<45>
VID0<45>

VID1<45>
VID2<45>
VID3<45>
VID4<45>
VID5<45>

V_CPU_GTLREF

CPU_BSEL0<6>
CPU_BSEL1<6>

R159

54.9_0603_1%~D@

1 2
1 2

R158

54.9_0603_1%~D@

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
VID0

VID1
VID2
VID3
VID4
VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

Note:
Pop R97 for Dothan-A,
Pop R92 for Dothan-B

+1.8VRUN

D D

+1.5VRUN

C C

B B

+VCCP

R_A

12

V_CPU_GTLREF

R140
1K_0603_1%~D

R_B

12

R147
2K_0603_1%~D

Layout close CPU

12

R129

R124

27.4_0603_1%~D

@

0_0805_5%~D

1 2

0_0805_5%~D

1 2

12

12

R465

27.4_0603_1%~D

54.9_0603_1%~D

+VCCA_PROC

R97

R92

1

1

C88

C87

2

2

10U_0805_10V4M~D

0.01U_0402_16V7K~D

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25

12

miles away from any
other toggling signal.

R457

54.9_0603_1%~D

+VCC_CORE

JCPUC

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC

Y22

VCC

AA5

VCC

AA7

VCC

AA9

VCC

AA11

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AB6

VCC

AB8

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AC9

VCC

AC11

VCC

AC13

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AD8

VCC

AD10

VCC

AD12

VCC

AD14

VCC

AD16

VCC

AD18

VCC

AE9

VCC

AE11

VCC

AE13

VCC

AE15

VCC

AE17

VCC

AE19

VCC

AF8

VCC

AF10

VCC

AF12

VCC

AF14

VCC

AF16

VCC

AF18

VCC

M4

VSS

M5

VSS

M21

VSS

M24

VSS

N3

VSS

N6

VSS

N22

VSS

N23

VSS

N26

VSS

P2

VSS

P5

VSS

P21

VSS

P24

VSS

R1

VSS

R4

VSS

R6

VSS

R22

VSS

R25

VSS

T3

VSS

T5

VSS

T21

VSS

T23

VSS

TYCO_1612364-1~D

Dothan

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Dothan Processor in mFCPGA479

TOBAGO-LA2151

851Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+VCC_CORE

1

C100
10U_0805_4VAM~D

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

@

C428
10U_0805_4VAM~D

C468
10U_0805_4VAM~D

@

C448
10U_0805_4VAM~D

D D

C C

1

C429
10U_0805_4VAM~D

2

1

C138
10U_0805_4VAM~D

2

1

C140
10U_0805_4VAM~D

2

1

C432
10U_0805_4VAM~D

2

1

C98
10U_0805_4VAM~D

2

1

C447
10U_0805_4VAM~D

2

1

C139
10U_0805_4VAM~D

2

1

C426
10U_0805_4VAM~D

2

1

C430
10U_0805_4VAM~D

2

1

C470
10U_0805_4VAM~D

2

1

@

C446
10U_0805_4VAM~D

2

1

C427
10U_0805_4VAM~D

2

1

C99
10U_0805_4VAM~D

2

1

C469
10U_0805_4VAM~D

2

1

C466
10U_0805_4VAM~D

2

1

@

C431
10U_0805_4VAM~D

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C472
10U_0805_4VAM~D

C467
10U_0805_4VAM~D

C137
10U_0805_4VAM~D

1

2

1

2

1

2

10uF 0805 X6S -> 105 degree C

1

C473
10U_0805_4VAM~D

C471
10U_0805_4VAM~D

C120
10U_0805_4VAM~D

@

C119
10U_0805_4VAM~D

2

1

C97
10U_0805_4VAM~D

2

1

@

C118
10U_0805_4VAM~D

2

High Frequence Decoupling

1

C142
10U_0805_4VAM~D

2

1

C102
10U_0805_4VAM~D

2

1

C117
10U_0805_4VAM~D

2

1

C141
10U_0805_4VAM~D

2

1

C433
10U_0805_4VAM~D

2

1

C101
10U_0805_4VAM~D

2

Near VCORE regulator.

+VCC_CORE

1

1

+

+

C496

330U_D_2VM~D

2

9mOhm
7343
PS CAP

C354

330U_D_2VM~D

9mOhm
7343
PS CAP

C352

330U_D_2VM~D

2

@

B B

9mOhm
7343
PS CAP

1

1

+

+

C497

330U_D_2VM~D

2

2

@

9mOhm
7343
PS CAP

ESR <= 3m ohm
Capacitor > 880uF

+VCCP

1

+

C455
150U_D2_4VK~D

2

A A

1

C415

0.1U_0402_10V7K~D

2

1

C439

0.1U_0402_10V7K~D

2

1

C451

0.1U_0402_10V7K~D

2

1

C416

0.1U_0402_10V7K~D

2

1

C462

0.1U_0402_10V7K~D

2

1

C414

0.1U_0402_10V7K~D

2

1

C438

0.1U_0402_10V7K~D

2

1

C445

0.1U_0402_10V7K~D

2

1

C457

0.1U_0402_10V7K~D

2

1

C474

0.1U_0402_10V7K~D

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

TOBAGO-LA2151

951Monday, October 18, 2004

1

0.6

of

5

D D

C C

Layout Guide
will show these
signals routed
differentially.

B B

A A

H_A#[3..31]<7>

T32 PAD~D

CLK_MCH_BCLK#<6>
CLK_MCH_BCLK<6>

H_CPUSLP#<7,22>

@

H_ADSTB#0<7>
H_ADSTB#1<7>

H_DINV#0<7>
H_DINV#1<7>
H_DINV#2<7>
H_DINV#3<7>

H_RESET#<7>

H_ADS#<7>
H_TRDY#<7>
H_DPWR#<7>
H_DRDY#<7>
H_DEFER#<7>

T33 PAD~D

H_HITM#<7>
H_HIT#<7>
H_LOCK#<7>

H_BR0#<7>
H_BNR#<7>
H_BPRI#<7>

H_DBSY#<7>

H_REQ#[0..4]<7>

H_DSTBN#[0..3]<7>

H_DSTBP#[0..3]<7>

H_RS#[0..2]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DRDY#

H_DEFER#
TP_H_EDRDY#

@

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_CPUSLP# H_R_CPUSLP#

Note:
"Do not install R88 for Dothan-A,
Install R88 for Dothan-B"

U4A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKP

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HCPUSLP#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO-915PM-B0_BGA1257~D

R88
0_0402_5%~D

1 2

Alviso

HOST

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

4

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

12

R90

24.9_0603_1%~D

Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20

H_D#[0..63] <7>

H_SWNG1

C65

0.1U_0402_16V4Z~D

H_SWNG0

C48

0.1U_0402_16V4Z~D

+VCCP

12

R52

54.9_0603_1%~D

12

R57

24.9_0603_1%~D

3

DMI_TXN0<23>
DMI_TXN1<23>
DMI_TXN2<23>
DMI_TXN3<23>

M_CLK_DDR0<16>
M_CLK_DDR1<16>

M_CLK_DDR3<17>
M_CLK_DDR4<17>

M_CLK_DDR#0<16>
M_CLK_DDR#1<16>

M_CLK_DDR#3<17>
M_CLK_DDR#4<17>

DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>

DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>

R142

1 2

V_DDR_MCH_REF<16,17,44>

DMI_TXP0<23>
DMI_TXP1<23>
DMI_TXP2<23>
DMI_TXP3<23>

DMI_RXN0<23>
DMI_RXN1<23>
DMI_RXN2<23>
DMI_RXN3<23>

DMI_RXP0<23>
DMI_RXP1<23>
DMI_RXP2<23>
DMI_RXP3<23>

80.6_0603_1%~D

Layout Note:
Rote as short
as possible

@

+VCCP

12

R85

221_0603_1%~D

12

1

R86

2

100_0603_1%~D

+VCCP

12

R64

221_0603_1%~D

12

1

R65

2

R80

100_0603_1%~D

12

54.9_0603_1%~D

1

C363

2

0.1U_0402_16V4Z~D

+1.8VSUS

12

R141

80.6_0603_1%~D

+VCCP

R326

100_0603_1%~D

R325

200_0603_1%~D

12

12

DMI_TXN0
DMI_TXN1 MCH_CLKSEL1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR3
M_CLK_DDR4

M_CLK_DDR#0
M_CLK_DDR#1

M_CLK_DDR#3
M_CLK_DDR#4

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0

M_ODT0<16>

M_ODT1

M_ODT1<16>

M_ODT2

M_ODT2<17>

M_ODT3

M_ODT3<17>

SMRCOMPN

R435

40.2_0402_1%~D

SMRCOMPP

1

1

C435

C425

2

2

0.1U_0402_16V4Z~D

2.2U_0805_6.3V6K~D

M_OCDOCMP0
M_OCDOCMP1

12

12

R437

@

40.2_0402_1%~D

2

Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown

CFG0

MCH_CLKSEL0

@
@

CFG5
CFG6
CFG7

CFG9

CFG12
CFG13

CFG16
CFG18

CFG19

THERMTRIP_MCH#

PM_EXTTS#0
PM_EXTTS#1

IMVP_PWRGD
PLTRST_R#

1 2

R441 100_0603_1%~D

R336

10K_0402_5%~D

R253

10K_0402_5%~D

12

12

CFG0 <12>
MCH_CLKSEL1 <6>

MCH_CLKSEL0 <6>

CFG5 <12>
CFG6 <12>
CFG7 <12>

CFG9 <12>

CFG12 <12>
CFG13 <12>

CFG16 <12>
CFG18 <12>

CFG19 <12>

DREFCLK# <6>
DREFCLK <6>

DREF_SSCLK <6,11>
DREF_SSCLK# <6,11>

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33
AA37
AB33
AC37

AM33

AL1
AE11

AJ34

AF6
AC10

AN33

AK1
AE10

AJ33

AF5
AD10

AP21
AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16
AP14
AL15
AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9
AF10

DMIDDR MUXING

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO-915PM-B0_BGA1257~D

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21

CFG/RSVD

RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

PM

DREF_CLKN

DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN

CLK

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC

NC10
NC11

U4B

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

PM_EXTTS#0

PM_EXTTS#1

1

T34PAD~D
T35PAD~D

R335
56_0402_5%~D

1 2

PM_BMBUSY# <23>

THERMTRIP_MCH# <15>
IMVP_PWRGD <23,38,45>

+2.5VRUN

PLTRST# <21,23,25,34>

+VCCP

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(1 of 5)

TOBAGO-LA2151

10 51Wednesday, November 03, 2004

1

0.6

of

5

D D

4

3

2

1

DDR_A_BS#0<16>
DDR_A_BS#1<16>
DDR_A_BS#2<16>

DDR_A_DM[0..7]<16>

DDR_A_DQS[0..7]<16>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

C C

B B

DDR_A_DQS#[0..7]<16>

DDR_A_MA[0..13]<16>

DDR_A_CAS#<16>
DDR_A_RAS#<16>

DDR_A_WE#<16>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AM8
AM4

AN8
AM5
AH1

AP9
AP4
AJ2
AD3

AJ1
AE5

AE4

U4C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

ALVISO-915PM-B0_BGA1257~D

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43

DDR MEMORY SYSTEM A

SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_B_DQS#[0..7]<17>

DDR_B_BS#0<17>
DDR_B_BS#1<17>
DDR_B_BS#2<17>

DDR_B_DM[0..7]<17>

DDR_B_DQS[0..7]<17>

DDR_B_MA[0..13]<17>

+3VRUN

DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#<17>
DDR_B_RAS#<17>

DDR_B_WE#<17>

DDR_B_CAS#
DDR_B_RAS#

DDR_B_WE#

U4D

AJ15

SB_BS0#

AG17

SB_BS1#

AG21

SB_BS2#

AF32

SB_DM0

AK34

SB_DM1

AK27

SB_DM2

AK24

SB_DM3

AJ10

SB_DM4

AK5

SB_DM5

AE7

SB_DM6

AB7

SB_DM7

AF34

SB_DQS0

AK32

SB_DQS1

AJ28

SB_DQS2

AK23

SB_DQS3

AM10

SB_DQS4

AH6

SB_DQS5

AF8

SB_DQS6

AB4

SB_DQS7

AF35

SB_DQS0#

AK33

SB_DQS1#

AK28

SB_DQS2#

AJ23

SB_DQS3#

AL10

SB_DQS4#

AH7

SB_DQS5#

AF7

SB_DQS6#

AB5

SB_DQS7#

AH17

SB_MA0

AK17

SB_MA1

AH18

SB_MA2

AJ18

SB_MA3

AK18

SB_MA4

AJ19

SB_MA5

AK19

SB_MA6

AH19

SB_MA7

AJ20

SB_MA8

AH20

SB_MA9

AJ16

SB_MA10

AG18

SB_MA11

AG20

SB_MA12

AG15

SB_MA13

AH14

SB_CAS#

AK14

SB_RAS#

AF15

SB_RCVENIN#

AF14

SB_RCVENOUT#

AH16

SB_WE#

ALVISO-915PM-B0_BGA1257~D

SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42

DDR SYSTEM MEMORY B

SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AE31

SBDQ0

AE32

DDR_B_D[0..63] <17>DDR_A_D[0..63] <16>

+3VRUN

+3VRUN

CLK_SSC_IN
SSC_S3

SSC_S2
SSC_S1

CLK_SCLK
CLK_SDATA

CLK_ENABLE#

R310

@

10K_0402_5%~D

1 2

CLK_SSC_IN<6>

R291

R292

@

1 2

1 2

10K_0402_5%~D

12

A A

5

12

R313

@

10K_0402_5%~D

R311

@

@

1 2

10K_0402_5%~D

12

R312

@

@

10K_0402_5%~D

R290

SSC_S3

10K_0402_5%~D

SSC_S2
SSC_S1

10K_0402_5%~D

4

CLK_SCLK<6,16,17>

CLK_SDATA<6,16,17>
CLK_ENABLE#<6,45>

U18

1

CLKIN

2

SSC_S3

3

SSC_S2

4

SSC_S1

7

SCLOCK

8

SDATA

5

PWRDWN

6

REFOUT/SEL

R289

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VDDA

VDD

CLKOUT

CLKOUT#

IREF

VSSIREF

VSS

VSSA

@CY25823

33_0402_5%~D

@

3

16
9

12
11

14
13

10
15

DREFSSCLK
DREFSSCLK#

1

C385

0.1U_0402_16V4Z~D

2

@

R390 33_0402_5%~D

1 2

R389 33_0402_5%~D

1 2

12

R395
475_0603_1%~D

@

REFOUT_14M

@

@

DREF_SSCLK <6,10>
DREF_SSCLK# <6,10>

DREF_SSCLK
DREF_SSCLK#

@

R388

49.9_0402_1%~D

1 2
1 2

@

R384

49.9_0402_1%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Alviso(2 of 5)

TOBAGO-LA2151

11 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

SDVO_CTRLDATA

D D

C C

B B

+2.5VRUN

+3VRUN

A A

CLK_MCH_3GPLL#<6>
CLK_MCH_3GPLL<6>

COMP/B<18>
Y/G<18>
C/R<18>

BIA_PWM<18,35>

R283 2.2K_0402_5%~D

R279 2.2K_0402_5%~D

R247 2.2K_0402_5%~D

R37 2.2K_0402_5%~D

R285 100K_0402_5%~D

R300 100K_0402_5%~D

INTCRT_B<18>
INTCRT_G<18>
INTCRT_R<18>

1@

1 2

1@

1 2

1@

1 2

1@

1 2

@

1 2

@

1 2

12

R25

150_0603_1%~D

INT_VSYNC<18>
INT_HSYNC<18>

PANEL_BKEN<19>

ENVDD<19>

R251

1.5K_0603_1%~D

1@

LCD_ACLK-<19>
LCD_ACLK+<19>
LCD_BCLK-<19>
LCD_BCLK+<19>

LCD_A0-<19>
LCD_A1-<19>
LCD_A2-<19>

LCD_A0+<19>
LCD_A1+<19>
LCD_A2+<19>

LCD_B0-<19>
LCD_B1-<19>
LCD_B2-<19>

LCD_B0+<19>
LCD_B1+<19>
LCD_B2+<19>

5

12

R23

R24

150_0603_1%~D

R533

1@

0_0402_5%~D

12

LCTLA_CLK

LCTLB_DATA

LCD_DDCCLK

LCD_DDCDATA

BIA_PWM_MCH

PANEL_BKEN

12

12

R314

150_0603_1%~D

G_CLK_DDC2
G_DAT_DDC2

1@

R284

255_0603_1%~D

BIA_PWM_MCH

12

PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA

L_IBG

TVIREF

4.99K_0603_1%~D

12

AB29
AC29

H24
H25

A15
C16
A17
J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

ALVISO-915PM-B0_BGA1257~D

1@

LDDC_CLK

LDDC_DATA

MISC

TVVGALVDS

+2.5VRUN

R34

2.2K_0402_5%~D

EXP_COMPI

EXP_ICOMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

PCI - EXPRESS GRAPHICS

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

12

12

R242

1@

+2.5VRUN

4

U4G

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

1@

S

2.2K_0402_5%~D

G

2

G

2

S

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

D

LCD_DDCCLK

13

Q33
BSS138_SOT23~D

LCD_DDCDATA

13

D

Q7
BSS138_SOT23~D1@

24.9_0603_1%~D

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_TXN[0..15]

PEG_TXP[0..15]

R287

+1.5VRUN_PCIE

PEG_RXN[0..15] <18>

PEG_RXP[0..15] <18>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

PEG_TXN[0..15] <18>

PEG_TXP[0..15] <18>

INTCRT_R
INTCRT_G
INTCRT_B

LCD_DDCCLK <19>

LCD_DDCDATA <19>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

R261 150_0603_1%~D

1 2

R260 150_0603_1%~D

1 2

R295 150_0603_1%~D

3

Strap Table

CFG5

CFG6

CFG7

CFG9

CFG[13:12]

CFG16
(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

SDVO_CTRLDATA

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I

*

*

Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

*

*

*

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
Low = No SDVO Device Present

(Default)

High = SDVO Device Present

*

*

G_CLK_DDC2

G_DAT_DDC2

2

1@

*

*

+2.5VRUN

R229

2.2K_0402_5%~D

12

1@

+2.5VRUN

+VCCP

R333 10K_0402_5%~D

CFG0<10>

R307 2.2K_0402_5%~D@

CFG5<10>

R299 2.2K_0402_5%~D

CFG6<10>

R281 2.2K_0402_5%~D @

CFG7<10>

R282 2.2K_0402_5%~D @

CFG9<10>

R288 2.2K_0402_5%~D @

CFG12<10>

R323 2.2K_0402_5%~D @

CFG13<10>

R346 2.2K_0402_5%~D @

CFG16<10>

1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

CFG[3:17] have internal pullup

+2.5VRUN

1 2
1 2

@

R308 1K_0402_5%~D

CFG18<10>
CFG19<10>

R306 1K_0402_5%~D@

CFG[18:19] have internal pulldown

+2.5VRUN

SDVO_CTRLDATA

1 2

R334 1K_0402_5%~D@

Have internal pulldown

12

R232

2.2K_0402_5%~D

S

G

2

G

2

S

1@

D

INT_CLK_DDC2

13

Q31
BSS138_SOT23~D

INT_DAT_DDC2

13

D

Q27
BSS138_SOT23~D1@

INT_CLK_DDC2 <18>

INT_DAT_DDC2 <18>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(3 of 5)

TOBAGO-LA2151

12 51Monday, October 18, 2004

1

0.6

of

5

U4F

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1 2

+2.5VRUN

1

D14
MMBD4148_SOT23~D1@

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

L33

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

1

C160

2

10U_0805_4VAM~D

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

+1.5VRUN_DPLLB

1

+

C335

2

1@

220U_D2_4VM_R45~D

C158

C331

1

2

1

2

10U_0805_4VAM~D

1

2

1

2

0.1U_0402_16V4Z~D

+1.5VRUN

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

D D

+VCCP

1

C390

C391

2

4.7U_0805_10V4Z~D

2.2U_0805_6.3V6K~D

1

C316

C C

B B

A A

1

2

+1.5VRUN

0.47U_0603_16V4Z~D

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

2

C45

0.47U_0603_16V4Z~D

1

2

1 2

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

1

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

2

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C54

C81

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

ALVISO-915PM-B0_BGA1257~D

+1.5VRUN_DPLLA

L28

1

1

+

C294

C322

2

2

1@

0.1U_0402_16V4Z~D

220U_D2_4VM_R45~D

Note : C294, C335 No stuff for Ext. VGA.
Stuff for Int. VGA.

+VCCP

1 2

R320

10_0402_5%~D1@

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

Note : All VCCSM pin
shorted internally.

+1.5VRUN

2

3

CRT DAC Voltge Follower Circuit - 700mV T V DAC Voltge F ollower Circuit - 700mV

5

C465

0.1U_0402_16V4Z~D

+1.8VSUS

C165

C437

R12

1

C450

2

1

C379

2

0.1U_0402_16V4Z~D

1

C366

2

10U_0805_4VAM~D

1

+

2

330U_D2E_2.5VM~D@

1

2

0.1U_0402_16V4Z~D

+1.5VRUN

1 2

10_0402_5%~D1@

4

1

C460

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C358

2

0.1U_0402_16V4Z~D

1

C367

2

10U_0805_4VAM~D

+1.5VRUN_DPLLA
+1.5VRUN_DPLLB

+1.5VRUN_HPLL
+1.5VRUN_MPLL

1

C463

C464

2

0.1U_0402_16V4Z~D

4

+VCCP

1

C383

2

0.1U_0402_16V4Z~D

1

C368

2

10U_0805_4VAM~D

+1.5VRUN

0.1U_0402_16V4Z~D

L39

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1 2

2

3

C94

T29
R29
N29

M29

K29

J29
V28
U28
T28
R28
P28
N28

M28

L28
K28

J28
H28
G28
V27
U27
T27
R27
P27
N27

M27

L27
K27

J27
H27
K26
H26
K25

J25
K24
K23
K22
K21

W20

U20
T20
K20
V19
U19
K19

W18

V18
T18
K18
K17

AC1
AC2
B23
C35
AA1
AA2

+1.5VRUN_HPLL

1

+

C413

2

0.1U_0402_16V4Z~D

150U_D2_2VM_R15~D

+3VRUN

1

D8
MMBD4148_SOT23~D1@

W=30 mils

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

POWER

VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

ALVISO-915PM-B0_BGA1257~D

+1.5VRUN

1

2

U4E

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

L38

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1 2

3

F17

+3VRUN_TVDACA
E17
D18

+3VRUN_TVDACB
C18
F18

+3VRUN_TVDACC
E18

+3VRUN_ATVBG
H18

VSSA_TVBG

G18
D19

+1.5VRUN_TVDAC
H17

+1.5VRUN_QTVDAC
B26

+1.5VRUN_DLVDS
B25

A25
A35

+2.5VRUN_ALVDS

B22

+2.5VRUN
B21

A21
B28

+2.5VRUN_TXLVDS
A28

A27
AF20

AP19
AF19
AF18

AE37

C441

W37
U37
R37

C419

N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

1

2

150U_D2_2VM_R15~D

0.1U_0402_16V4Z~D

VCC_SYNC

1 2

C357

22n_0805_25V

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" o f Alviso.

+1.5VRUN_MPLL

1

+

C418

2

0.1U_0402_16V4Z~D

1

C164

2

100U_D_6.3VM~D

+2.5VRUN_CRT

3

+2.5VRUN_CRT

VCC_SYNC

L11

BLM18PG181SN1_0603~D

1 2

3

1

C37

22n_0805_25V

Route VSSA_TVBG GND from GMCH to
decoupling cap ground lead and then
connect to the GND plane.

C35, C36, C37, C304, C305, C306, C357
replace by 0 ohm 0805 resistor

1

+

2

1

+

C53

C49

2

220U_D2_4VM_R45~D

R347

1@

0_0402_5%~D

1 2

L37 BLM11A601S_0603~D 1@

1 2

1

C364

2

+2.5VRUN_TXLVDS

1

C314

C324

2

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

R370

2@

0_0402_5%~D

1 2

R357

2@

0_0402_5%~D

1 2

C24

2

0.1U_0402_16V4Z~D

1

1

C59

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

1

C302

2

1@

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

R252

12

0_0402_5%~D

1

2

+VCCP

+VCCP

2

+1.5VRUN+1.5VRUN_QTVDAC

12

1

1

C293

C291

2

2

0.1U_0402_16V4Z~D

0.022U_0402_16V7K~D

R267

0.5_0805_1%~D

1 2

1

1

C404

C311

2

2

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

+2.5VRUN

1

C320

2

1@

+2.5VRUN

0.1U_0402_16V4Z~D

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

+1.5VRUN_TVDAC +1.5VRUN

1 2

C304

22n_0805_25V

Note : R370, R357 stuff and R347, L37 no stuff for Ext. VGA.
R370, R357 no stuff and R347, L37 stuff for Int. VGA.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

BLM18PG181SN1_0603~D

1 2

3

1

C35

2

22n_0805_25V

+3VRUN_TVDACB +3VRUN

3GRLL_R

1

C345

0.1U_0402_16V4Z~D

2

3

1

2

BLM18PG181SN1_0603~D

1 2

3

1

C306

2

22n_0805_25V

L18

BLM21PG600SN1D_0805~D

L35

BLM21PG600SN1D_0805~D

L34

BLM21PG600SN1D_0805~D

L36

BLM11A601S_0603~D

L24

BLM18PG181SN1_0603~D

C297

0.1U_0402_16V4Z~D

C22

C299

12

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

12
+1.5VRUN+1.5VRUN_3GPLL

12

C332

L26

0.1U_0402_16V4Z~D

+2.5VRUN+2.5VRUN_3GBG

12

12

+1.5VRUN+1.5VRUN_PCIE

C336

1

0.1U_0402_16V4Z~D

2

1

C351

0.1U_0402_16V4Z~D

2

+2.5VRUN_ALVDS

C323

+3VRUN+3VRUN_TVDACA

L9

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

1

BLM18PG181SN1_0603~D

1 2

3

1

C305

1

C598

2

1@

VSSA_TVBG

+1.5VRUN+1.5VRUN_DDRDLL

1

C168

2

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

BLM11A601S_0603~D

1

1

C318

2

2

0.01U_0402_16V7K~D

+1.5VRUN_DLVDS +1.5VRUN

1

C310

C325

2

10U_0805_4VAM~D

0.01U_0402_16V7K~D

C298

2

22n_0805_25V

1 2

3

C36

4.7U_0805_10V4Z~D

22n_0805_25V

12

L30

L31

BLM11A601S_0603~D

1

2

0.1U_0402_16V4Z~D

BLM18PG181SN1_0603~D

1

2

12

Compal Electronics, Inc.

Alviso(4 of 5)

13 51Monday, October 18, 2004

1

L25

C23

0.1U_0402_16V4Z~D

+2.5VRUN

+3VRUN+3VRUN_TVDACC

12

+3VRUN+3VRUN_ATVBG

L10

12

0.6

of

5

4

3

2

1

+VCCP

D D

C C

B B

A A

W12

W13

AA12
AA13

W14

AA14
AB14

W15

AA15
AB15

W16

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25

W26

M12
N12

R12
U12

M13
N13

R13
U13

M14
N14

R14
U14

M15
N15

R15
U15

M16
N16

R16
U16

R17

R21

M26
N26

R26
U26

L12

P12
T12
V12
L13

P13
T13
V13

Y12
Y13
L14

P14
T14
V14
Y14

L15

P15
T15
V15
Y15

L16

P16
T16
V16
Y16

Y17

Y21

Y22

Y23

Y24

Y25

Y26

V25
L26

P26
T26
V26

5

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

ALVISO-915PM-B0_BGA1257~D

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70

NCTF

VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

U4H

+1.8VSUS

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+VCCP

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

U4J

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

AA10

AD2
AE2
AH2

AN2

AA3
AB3
AC3

AF4
AN4

AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AA9
AC9
AE9
AH9
AN9
D10

H11

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257
VSS256
VSS255
VSS254

AL2

VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSS

ALVISO-915PM-B0_BGA1257~D

A3
C3

AJ3

C4
H4
L4
P4
U4
Y4

E5

W5

AL5

B6
J6
L6
P6
T6

AJ6

G7

V7

C8
E8
L8
P8
Y8

AL8

A9
H9
K9
T9
V9

L10
Y10

F11
Y11

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

U4I

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24
AN24

AA27
AB27
AF27

AG27

AJ27
AL27

AN27

AA28
AB28
AC28

AA29
AD29
AG29

AJ29

AM29

AA30
AB30
AC30
AE30
AP30

AD31
AG31

AL31

AA32
AB32

G26

G27
W27

W28

D29

G29
H29

U29
W29

C30

D31

G31
H31

M31
N31

R31
U31
W31

C32

VSS267
VSS266

A26

VSS265

E26

VSS264
VSS263

J26

VSS262

B27

VSS261

E27

VSS129
VSS128
VSS127
VSS126
VSS125

VSS

VSS124
VSS123
VSS122
VSS121
VSS120

E28

VSS119
VSS118
VSS117
VSS116
VSS115

A29

VSS114
VSS113

E29

VSS112

F29

VSS111
VSS110
VSS109

L29

VSS108

P29

VSS107
VSS106

V29

VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98

Y30

VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91

E31

VSS90

F31

VSS89
VSS88
VSS87

J31

VSS86

K31

VSS85

L31

VSS84
VSS83
VSS82

P31

VSS81
VSS80

T31

VSS79
VSS78

V31

VSS77
VSS76
VSS75
VSS74
VSS73

A32

VSS72
VSS71

Y32

VSS70
VSS69
VSS68

ALVISO-915PM-B0_BGA1257~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Alviso(5 of 5)

TOBAGO-LA2151

14 51Monday, October 18, 2004

1

0.6

of

5

+15V

D D

C C

FAN1_PWM<35>

R502

100K_0402_5%~D

1 2

C541

FAN1VREF
FAN1_VFB

1

2

1U_0603_10V4Z~D

R500

1 2

150K_0402_5%~D

8

3

P

IN+

2

IN-

G

4

C538

2200P_0402_50V7K~D

1 2

R501

100K_0402_5%~D

4

FAN1 Control and Tachometer

1

C540

2

U29A
LM358M_SO8~D

FAN1_ON

1

O

12

D10

RB751V_SOD323~D

0.1U_0603_50V4Z~D

2 1

G

3

6

2

1

S

4 5

1

22U_1206_10V4Z~D

2

<BOM Structure>

+5VRUN

D

Q48

SI3456DV-T1_TSOP6~D

1

C209

2

@

1000P_0402_50V7K~D

FAN1_VOUT

C210

R499
10K_0402_5%~D@

1 2

R498

1K_0402_5%~D

1 2

@

FAN1_TACH_FB

3

PMBT2222_SOT23~D @

FAN1TACH_ON

JFAN1

1

1

2

2

3

3

MOLEX_53398-0390~D

Q47

+3VRUN+5VRUN

2

1 2

0_0402_5%~D

12

R413
10K_0402_5%~D

3 1

R497

FAN1_TACH <35>

2

C

B

E3

2

2222 SYMBOL(SOT23-NEW)

+15V

8

U29B
LM358M_SO8~D

5

P

IN+

O

6

IN-

G

4

1

1

7

H_THERMDA<7>

+3VSUS

12

R241

8.2K_0402_5%~D

+VCCP

R40

2.2K_0402_5%~D

1 2

MMBT3904_SOT23~D

H_THERMTRIP#<7>

B B

+VCCP

1 2

MMBT3904_SOT23~D

THERMTRIP_MCH#<10>

A A

R39

2.2K_0402_5%~D

Q39

Q34

2

B

2

B

E

+3VSUS

E

C

3 1

12

C

3 1

THERMATRIP1#

1

C42

0.1U_0402_16V4Z~D

2

R239

8.2K_0402_5%~D

THERMATRIP2#

1

C43

0.1U_0402_16V4Z~D

2

0.1U_0402_16V4Z~D

H_THERMDC<7>

+3VSUS

+RTC_CELL

+3VSUS

C303

2200P_0402_50V7K~D

R50

49.9_0603_1%~D

1 2

C41

0.1U_0402_16V4Z~D

1

C44

0.1U_0402_16V4Z~D

2

1

2

12

R249
147K_0603_1%~D

12

R262

12.1K_0603_1%~D

1

C341

2

1

2

SUSPWROK<23,38>

ICH_PWRGD#<38>
POWER_SW#<35,39>

THERMATRIP_VGA#<18>

1 2

R41 8.2K_0402_5%~D

1

2

DAT_SMB<35,36>
CLK_SMB<35,36>

R59 1K_0402_5%~D

R42 1K_0402_5%~D

R38 1K_0402_5%~D

THERMATRIP2#

THERMATRIP_VGA#

C317
2200P_0402_50V7K~D

1 2

1 2

1 2

1 2

U15

1

THDAT_SMB

2

THCLK_SMB

13

SMBADDRSEL

18

REM_DIODE2_P

17

REM_DIODE2_N

4

+3VSUS

11

VSUS_PWRGD

10

+RTC_PWR3V

5

+3V_PWROK

21

POWER_SW

6

THERMTRIP1

7

THERMTRIP2

8

THERMTRIP3

22

VSET

14

HW_LOCK

3

VSS

EMC6N300_SSOP24~D

R61

1K_0402_5%~D

ATF_INT

VCP

RESSERVED

REM_DIODE1_N
REM_DIODE1_P

THERMTRIP_SIO

THERM_STP

INTRUDER

9

23

16

19
20

15
24

12

+5VSUS

12

R51

2.21K_0603_1%~D

1

C46

2

2200P_0402_50V7K~D

REM_DIODE1_NTHERMATRIP1#

REM_DIODE1_P

+3VALW

2N7002_SOT23~D

12

R60
100K_0402_5%~D

ATF_INT# <34>

10KB_0603_1%_TSM1A103F34D3R~D

12

R467

13

D

Q40

2

G

S

REM_DIODE1_N, REM_DIODE1_P routing together.
Trace width / Spacing = 10 / 10 mil

1

C47

2

2200P_0402_50V7K~D

REM_DIODE1_N, REM_DIODE1_P routing together.
Trace width / Spacing = 10 / 10 mil

THERMTRIP_SIO <35>
THERM_STP# <42>
SM_INTRUDER# <22>

+5VSUS

12

B

2

R475
10K_0402_5%~D

E

31

C

5V_CAL_SIO# <34>

Q12
MMBT3904_SOT23~D

Place under CPU

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN & Thermal Sensor

TOBAGO-LA2151

15 51Wednesday, November 03, 2004

1

0.6

of

5

DDR_A_DQS#[0..7]<11>

DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>

DDR_A_MA[0..13]<11>

D D

+1.8VSUS

2.2U_0805_6.3V6K~D

2.2U_0805_6.3V6K~D

C213

C214

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C212

1

2

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

1

2

B B

A A

C221

DDR_A_MA8
DDR_A_MA5

56_0404_4P2R_5%~D

DDR_A_MA3
DDR_A_MA1

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_MA10
DDR_A_BS#0

56_0404_4P2R_5%~D

DDR_A_WE#
DDR_A_CAS#

56_0404_4P2R_5%~D

M_ODT1
DDR_CS1_DIMMA#

56_0404_4P2R_5%~D

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

C220

1

2

2

C219

C218

RN25

1 4
2 3

RN24

1 4
2 3

RN16

1 4
2 3

RN23

1 4
2 3

RN22

1 4
2 3

RN21

2 3
1 4

5

2.2U_0805_6.3V6K~D

1

2

C215

1

2

0.1U_0402_16V4Z~D

1

2

C217

+0.9V_DDR_VTT

C222

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2.2U_0805_6.3V6K~D

1

2

C223

1

2

0.1U_0402_16V4Z~D

1

2

C216

RN27

RN19

RN26

RN18

RN17

RN15

RN20

C225

0.1U_0402_16V4Z~D

1

2

1

2

C231

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

2.2U_0805_6.3V6K~D
C229

1

2

C227

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C232

DDR_CKE0_DIMMA
DDR_A_BS#2

DDR_A_MA7
DDR_A_MA6

DDR_A_MA12
DDR_A_MA9

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

Layout Note:
Place near JDIM1

0.1U_0402_16V4Z~D

1

1

2

2

C235

C233

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C237

C236

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

4

3

+1.8VSUS +1.8VSUS

JDIM2

1

VREF

3

2.2U_0805_6.3V6K~D
C230

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

JAE_MM50-200B1-1R~D

RESERVE

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<10>

DDR_A_BS#2<11>

DDR_A_BS#0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

DDR_CS1_DIMMA#<10>

M_ODT1<10>

0.1U_0402_16V4Z~D

1

2

C234

CLK_SDATA<6,11,17>
CLK_SCLK<6,11,17>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SDATA

CLK_SCLK

+3VRUN

0.1U_0402_16V4Z~D
C228

1

1

2

2

NC/CKE1

DIMMA

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO

2

1

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8
10
12
14
16
18
20
22
24
26
28
30

CK0

32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

CK1

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

R175 10K_0402_5%~D

1 2

R176 10K_0402_5%~D

1 2

2.2U_0805_6.3V6K~D

0.1U_0402_16V4Z~D

1

C226

2

M_CLK_DDR0 <10>

M_CLK_DDR#0 <10>

DDR_CKE1_DIMMA <10>

DDR_A_BS#1 <11>

DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DDR1 <10>

M_CLK_DDR#1 <10>

1

2

V_DDR_MCH_REF <10,17,44>

C224

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

TOBAGO-LA2151

16 51Monday, October 18, 2004

1

0.6

of

5

DDR_B_DQS#[0..7]<11>

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>

DDR_B_MA[0..13]<11>

D D

C C

B B

A A

+1.8VSUS

0.1U_0402_16V4Z~D

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C248

DDR_B_MA3
DDR_B_MA1

56_0404_4P2R_5%~D

DDR_B_MA10
DDR_B_BS#0

56_0404_4P2R_5%~D

DDR_B_MA0
DDR_B_BS#1

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_WE#
DDR_B_CAS#

56_0404_4P2R_5%~D

M_ODT3
DDR_CS3_DIMMB#

56_0404_4P2R_5%~D

2.2U_0805_6.3V6K~D

2.2U_0805_6.3V6K~D

1

2

0.1U_0402_16V4Z~D

C239

RN13

RN7

RN12

RN6

RN5

RN2

RN14

1

2

1

2

C244

2.2U_0805_6.3V6K~D

C261

C242

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C251

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C243

DDR_B_MA12

14

DDR_B_MA9

23

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA8

14

DDR_B_MA5

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_CKE2_DIMMB

14

DDR_B_BS#2

23

56_0404_4P2R_5%~D

2.2U_0805_6.3V6K~D

C250

1

2

1

2

C247

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

C254

C249

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C240

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C245

C246

+0.9V_DDR_VTT

RN11

RN10

RN4

RN3

RN9

RN8

5

2.2U_0805_6.3V6K~D
C241

1

2

C255

1

2

0.1U_0402_16V4Z~D

1

1

2

2

C269

Layout Note:
Place near JDIM2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C267

C268

4

0.1U_0402_16V4Z~D

1

2

C266

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C265

C264

4

3

JDIM1

1

VREF

3

C548

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

JAE_MM50-200B1-1~D

DIMMB

STANDARD

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB<10>

DDR_B_BS#2<11>

DDR_B_BS#0<11>
DDR_B_WE#<11>

DDR_B_CAS#<11>

DDR_CS3_DIMMB#<10>

1

2

C263

M_ODT3<10>

CLK_SDATA<6,11,16>
CLK_SCLK<6,11,16>

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SDATA

CLK_SCLK

+3VRUN

2.2U_0805_6.3V6K~D

0.1U_0402_16V4Z~D

C549

1

1

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8VSUS+1.8VSUS

2

V_DDR_MCH_REF

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46DDR_B_D42

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR4

M_CLK_DDR#4
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%~D

12

R173

2.2U_0805_6.3V6K~D

0.1U_0402_16V4Z~D

1

C253

2

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

DDR_CKE3_DIMMB <10>

DDR_B_BS#1 <11>

DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>

M_ODT2 <10>

M_CLK_DDR4 <10>

M_CLK_DDR#4 <10>

+3VRUN

12

R174

10K_0402_5%~D

1

V_DDR_MCH_REF <10,16,44>

1

C252

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

TOBAGO-LA2151

17 51Monday, October 18, 2004

1

0.6

of

5

+3VRUN

D D

2@

PEG_TXP0

PEG_TXP[0..15]<12>

C C

PEG_TXN[0..15]<12>

B B

A A

PEG_TXP[0..15]

PEG_TXN[0..15]

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXN0

PEG_TXN1

PEG_TXN2

PEG_TXN3

PEG_TXN4

PEG_TXN5

PEG_TXN6

PEG_TXN7

PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXN0
PEG_TXP1

PEG_TXN1
PEG_TXP2

PEG_TXN2
PEG_TXP3

PEG_TXN3
PEG_TXP4

PEG_TXN4
PEG_TXP5

PEG_TXN5
PEG_TXP6

PEG_TXN6
PEG_TXP7

PEG_TXN7
PEG_TXP8

PEG_TXN8
PEG_TXP9

PEG_TXN9
PEG_TXP10

PEG_TXN10
PEG_TXP11

PEG_TXN11
PEG_TXP12

PEG_TXN12
PEG_TXP13

PEG_TXN13
PEG_TXP14

PEG_TXN14
PEG_TXP15

PEG_TXN15

2@

C57 0.1U_0402_10V6K~D

2@

C62 0.1U_0402_10V6K~D

2@

C69 0.1U_0402_10V6K~D

2@

C72 0.1U_0402_10V6K~D

2@

C75 0.1U_0402_10V6K~D

2@

C80 0.1U_0402_10V6K~D

2@

C85 0.1U_0402_10V6K~D

2@

C92 0.1U_0402_10V6K~D

2@

C96 0.1U_0402_10V6K~D

2@

C104 0.1U_0402_10V6K~D

2@

C107 0.1U_0402_10V6K~D

2@

C112 0.1U_0402_10V6K~D

2@

C116 0.1U_0402_10V6K~D

2@

C123 0.1U_0402_10V6K~D

2@

C126 0.1U_0402_10V6K~D

2@

C129 0.1U_0402_10V6K~D

4

1

1

C319

C313

C309

2

2

2@

0.047U_0402_16V4Z~D

2@

0.047U_0402_16V4Z~D

1 2

C56 0.1U_0402_10V6K~D

1 2

C67 0.1U_0402_10V6K~D

1 2

C71 0.1U_0402_10V6K~D

1 2

C74 0.1U_0402_10V6K~D

1 2

C79 0.1U_0402_10V6K~D

1 2

C84 0.1U_0402_10V6K~D

1 2

C91 0.1U_0402_10V6K~D

1 2

C95 0.1U_0402_10V6K~D

1 2

C103 0.1U_0402_10V6K~D

1 2

C106 0.1U_0402_10V6K~D

1 2

C111 0.1U_0402_10V6K~D

1 2

C115 0.1U_0402_10V6K~D

1 2

C122 0.1U_0402_10V6K~D

1 2

C125 0.1U_0402_10V6K~D

1 2

C128 0.1U_0402_10V6K~D

1 2

C132 0.1U_0402_10V6K~D

+1.8VRUN

1

2

0.047U_0402_16V4Z~D

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

PJP18

@PAD-OPEN 4x4m

1 2

DVI Interface

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

2@

+3VSUS

VDDM

+15V

RUNPWROK<35,38,43,45>

+2.5VRUN

PEG_A_TXP_0
PEG_A_TXN_0

PEG_A_TXP_1
PEG_A_TXN_1

PEG_A_TXP_2
PEG_A_TXN_2

PEG_A_TXP_3
PEG_A_TXN_3

PEG_A_TXP_4
PEG_A_TXN_4

PEG_A_TXP_5
PEG_A_TXN_5

PEG_A_TXP_6
PEG_A_TXN_6

PEG_A_TXP_7
PEG_A_TXN_7

PEG_A_TXP_8
PEG_A_TXN_8

PEG_A_TXP_9
PEG_A_TXN_9

PEG_A_TXP_10
PEG_A_TXN_10

PEG_A_TXP_11
PEG_A_TXN_11

PEG_A_TXP_12
PEG_A_TXN_12

PEG_A_TXP_13
PEG_A_TXN_13

PEG_A_TXP_14
PEG_A_TXN_14

PEG_A_TXP_15
PEG_A_TXN_15

RUNPWROK

JVID

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

147

149

149

151

151

153

153

155

155

157

157

159

159

161

161

163

163

165

165

167

167

169

169

171

171

173

173

175

175

177

177

179

179

181

181

183

183

185

185

187

187

189

189

191

191

193

193

195

195

197

197

199

199

201

201

203

203

205

205

JAE_WB3M200VD1~D

2@

3

R534

2@

+1.5VRUN

2

C155

1

2@

0.1U_0603_50V4Z~D

0_0402_5%~D

1 2
+5VALW

SBAT_SMBCLK <35>

SBAT_SMBDAT <35>
TV_Y <20>
TV_CVBS <20>
TV_C <20>

VSYNC <20>
HSYNC <20>

VGA_BLU <20>
VGA_GRN <20>

VGA_RED <20>

CLK_DDC2 <20>

DAT_DDC2 <20>

PLTRST_DELAY# <23>

CLK_PCIE_VGA <6>

CLK_PCIE_VGA# <6>

THERMATRIP_VGA# <15>

+5VRUN

GC_BL_SUSPEND <34>

2

C161

2@

2

C167

1

1

2@

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

ICH_PCIE_WAKE# <23,34>

BIA_PWM <12,35>

C171

2@

0.1U_0603_50V4Z~D

2

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

BIA_PWM_VGA
SBAT_SMBCLK

SBAT_SMBDAT
TV_Y
TV_CVBS
TV_C
VSYNC

HSYNC
VGA_BLU
VGA_GRN
VGA_RED
CLK_DDC2

DAT_DDC2

DVI Interface

PLTRST_DELAY#
CLK_PCIE_VGA

CLK_PCIE_VGA#

PEG_RXP0
PEG_RXN0

PEG_RXP1
PEG_RXN1

PEG_RXP2
PEG_RXN2

PEG_RXP3
PEG_RXN3

PEG_RXP4
PEG_RXN4

PEG_RXP5
PEG_RXN5

PEG_RXP6
PEG_RXN6

PEG_RXP7
PEG_RXN7

PEG_RXP8
PEG_RXN8

PEG_RXP9
PEG_RXN9

PEG_RXP10
PEG_RXN10

PEG_RXP11
PEG_RXN11

PEG_RXP12
PEG_RXN12

PEG_RXP13
PEG_RXN13

PEG_RXP14
PEG_RXN14

PEG_RXP15
PEG_RXN15

THERMATRIP_VGA#
+5VRUN
GC_BL_SUSPEND

ICH_PCIE_W AKE#

2

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

G_PWR_SRC

1

2

C569

2

1

@

10U_1206_25V6M~D

PEG_RXP[0..15]

PEG_RXN[0..15]

Y/G<12>

COMP/B<12>

C/R<12>

INT_VSYNC<12>

INT_HSYNC<12>

INT_DAT_DDC2<12>

INT_CLK_DDC2<12>

INTCRT_B<12>

INTCRT_G<12>

INTCRT_R<12>

1@

R48 0_0402_5%~D

1@

R49 0_0402_5%~D

1@

R53 0_0402_5%~D

1@

1 2

R58 0_0402_5%~D

1@

1 2

R63 0_0402_5%~D

1@

1 2

R79 0_0402_5%~D

1@

1 2

R76 0_0402_5%~D

1@

R67 0_0402_5%~D

1@

R70 0_0402_5%~D

1@

R73 0_0402_5%~D

Depop when wit h external graphics

1

PEG_RXP[0..15] <12>

PEG_RXN[0..15] <12>

TV_Y

12

TV_CVBS

12

TV_C

12

VSYNC

HSYNC

DAT_DDC2

CLK_DDC2

VGA_BLU

12

VGA_GRN

12

VGA_RED

12

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

VGA connector

TOBAGO-LA2151

18 51Monday, October 18, 2004

1

0.6

of

5

D D

4

3

2

1

JLVDS

45

MGND1

46
47
48
49
50
51
56
57
54
55

C C

B B

TXUCLKUT+

MGND2
MGND3
MGND4
MGND5
MGND6
MGND7
MGND8
MGND9
MGND10
MGND11

TXLCLKOUT-

TXLCLKOUT+

PANEL_I2C_CLK
PANEL_I2C_DAT

PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC

PBAT_SMBCLK
PBAT_SMBDAT

LAMP_START

JAE_FI-TD44SB-L~D

1@

TXUCLKUT-

GND1

TXUOUT2-

TXUOUT2+

GND2

TXUOUT1-

TXUOUT1+

GND3

TXUOUT0-

TXUOUT0+

GND4

GND5

TXLOUT2-

TXLOUT2+

GND6

TXLOUT1-

TXLOUT1+

GND7

TXLOUT0-

TXLOUT0+

GND8

GND9

VEDID

GND10
LCDVDD1
LCDVDD2

GND11

FPBACK

GND12

GND13

+5V_ALWF

GND14

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LCD_BCLK­LCD_BCLK+

LCD_B2­LCD_B2+

LCD_B1­LCD_B1+

LCD_B0­LCD_B0+

LCD_ACLK­LCD_ACLK+

LCD_A2­LCD_A2+

LCD_A1­LCD_A1+

LCD_A0­LCD_A0+

LCD_DDCCLK
LCD_DDCDATA

LCD_TST

BACKLITE_ON

LAMP_STAT

1

2

LCD_BCLK- <12>
LCD_BCLK+ <12>

LCD_B2- <12>
LCD_B2+ <12>

LCD_B1- <12>
LCD_B1+ <12>

LCD_B0- <12>
LCD_B0+ <12>

LCD_ACLK- <12>
LCD_ACLK+ <12>

LCD_A2- <12>
LCD_A2+ <12>

LCD_A1- <12>
LCD_A1+ <12>

LCD_A0- <12>
LCD_A0+ <12>

LCD_DDCCLK <12>
LCD_DDCDATA <12>

+LCDVCC

LCD_TST <23,34>

0.1U_0402_16V4Z~D

1@

1 2

R240 0_0402_5%~D

PBAT_SMBCLK <35,41,46>
PBAT_SMBDAT <35,41,46>

LAMP_STAT <21>

1@

12

R238

0_0805_5%~D

C296

0.1U_0603_50V4Z~D

1@

C27

1@

+3VRUN

1

1

C26

0.1U_0402_16V4Z~D

2

2

PANEL_BKEN <12>

G_PWR_SRC

1@

0_0805_5%~D

1@

1

2

R248

12

+LCDVDD

+5VALW

C28

0.1U_0402_16V4Z~D

1@

+LCDVDD

12

R35
470_0402_5%~D

1@

13

D

Q37

S

2N7002_SOT23~D

1@

ENVDD<12>

+15V

12

2

G

1

2

I

3

PWR_SRC

40mil

1

C290

1000P_0603_50V7K~D

2

R54
100K_0402_5%~D

1@

2

G

O

1@

G

Q8
DTC124EKA_SC59~D

12

R235
100K_0402_5%~D

+15V

12

R272
100K_0402_5%~D

1@

13

D

Q10

S

1@

FDS4435_SO8~D
Q32

1
2
3

+LCDVDD

2N7002_SOT23~D

4

1

C315

2

1@

8
7
6
5

S

4 5

0.1U_0402_16V4Z~D

40mil

1

2

D

Q9

6
2

1

G

SI3456DV-T1_TSOP6~D

3

1@

12

R263
100K_0402_5%~D

1@

G_PWR_SRC

C289

0.1U_0603_50V4Z~D

+3VRUN

1

2

C29

1@

0.1U_0402_16V4Z~D

R236

1 2

100K_0402_5%~D

RUN_ON<34,37,38,42,44>

A A

D

1 3

2

Q29
2N7002_SOT23~D

S

G

FDS4435: P CHANNAL

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Internal LVDS

TOBAGO-LA2151

19 51Wednesday, November 03, 2004

1

0.6

of

5

TV_C<18>

D D

TV_CVBS<18>

TV_Y<18>

12

R17

C16

75_0402_1%~D

82P_0402_50V8J~D

12

R16

C17

75_0402_1%~D

82P_0402_50V8J~D

12

C10

R13

75_0402_1%~D

82P_0402_50V8J~D

L3

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

CLOSE TO JTV1

1

2

1

2

1

2

L2

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

L1

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

R13, R16, R17, R18, R19, and R20 Pop
150 ohm resistor for internal Gfx

C C

HSYNC<18>

VSYNC<18>

VGA_RED

VGA_GRN

VGA_BLU

R19

75_0402_1%~D

DAT_DDC2<18>

CLK_DDC2<18>

12

1 2

39_0402_5%~D

1 2

39_0402_5%~D

R233

R234

12

12

R20

R18

75_0402_1%~D

75_0402_1%~D

CRT_VCC

VGA_RED<18>

VGA_GRN<18>

VGA_BLU<18>

B B

4

1

C7

2

82P_0402_50V8J~D

1

C6

2

82P_0402_50V8J~D

1

C5

2

82P_0402_50V8J~D

1

C14

@

C15

2

@

22P_0402_50V8J~D

Evaluate Package

1K_0402_5%~D

1 2

1

5

U13

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353~D

3

1

5

U12

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353~D

3

1

2

R228

HSYNC_R

VSYNC_R

22P_0402_50V8J~D

SVIDEO_C
SVIDEO_CVBS

SVIDEO_Y

1

C12

2

@

22P_0402_50V8J~D

BLM11A121S_0603~D

1 2

BLM11A121S_0603~D

1 2

L6

BLM18BB600SN1D_0603~D

1 2

L4

BLM18BB600SN1D_0603~D

1 2

L5

BLM18BB600SN1D_0603~D

1 2

CRT_VCC

12

R7

@

1K_0402_5%~D

L22

L23

1

C286

2

22P_0402_50V8J~D

3

D11
DA204U_SOT323~D

1

@

+3VRUN

2

3

D4
DA204U_SOT323~D

1

@

+3VRUN

2

3

1

C1
10P_0402_50V8J~D

2

@

12

@

R11

1K_0402_5%~D

C8

22P_0402_50V8J~D

R10

1

2

R9

1 2

2.2K_0402_5%~D

1 2

2.2K_0402_5%~D

0.1U_0402_16V4Z~D

2

1

C2
10P_0402_50V8J~D

2

@

@

T1 PAD~D

D5
DA204U_SOT323~D

1

@

3

C4

2

D12
DA204U_SOT323~D

1

@

2

3

1

C3
10P_0402_50V8J~D

2

@

1

2

D6
DA204U_SOT323~D

1

@

2

3

D13
DA204U_SOT323~D

1

@

2

3

D7

+5VRUN

21

RB751V_SOD323~D

CRT_VCC

1

C11

2

0.01U_0402_16V7K~D

RED
DAT_DDC2

GREEN
JVGA_HS

BLUE
CRT_VCC
JVGA_VS

M_ID2#

CLK_DDC2

1

JTVOUT

2
4
6
7
5
3
1
8
9

FOX_MH11777-WRUR6~D

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

JCRT

18
19

FOX_DZ11A91-L8

A A

DA204U

A2

K1

DELL CONFIDENTIAL/PROPRIETARY

A1

K2

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

TV_OUT and CRT

TOBAGO-LA2151

20 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

PCI_AD[0..31]<30,31,33>

D D

C C

B B

+3VRUN

1 2

R254 8.2K_0402_5%~D

1 2

R46 8.2K_0402_5%~D

1 2

R47 8.2K_0402_5%~D

1 2

R258 8.2K_0402_5%~D

1 2

R327 8.2K_0402_5%~D

1 2

R69 8.2K_0402_5%~D

1 2

R257 8.2K_0402_5%~D

1 2

R255 8.2K_0402_5%~D

+3VRUN

1 2

R43 8.2K_0402_5%~D

1 2

R45 8.2K_0402_5%~D

1 2

R44 8.2K_0402_5%~D

1 2

R286 8.2K_0402_5%~D

1 2

R350 8.2K_0402_5%~D

1 2

R324 8.2K_0402_5%~D

1 2

R309 8.2K_0402_5%~D

1 2

R315 8.2K_0402_5%~D

1 2

R317 8.2K_0402_5%~D

1 2

R72 8.2K_0402_5%~D

1 2

R340 8.2K_0402_5%~D

1 2

R77 8.2K_0402_5%~D

1 2

R256 8.2K_0402_5%~D

1 2

R339 8.2K_0402_5%~D

1 2

R75 8.2K_0402_5%~D

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
LAMP_STAT

PCI_FRAME#<30,31,33>

PCI_PIRQB#<31,33>
PCI_PIRQC#<30,31>
PCI_PIRQD#<31,33>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U3B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

Interrupt I/F

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

PCI

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]

PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

ICH6_BGA609~D

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PLTRST#

PCICLK

PME#

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

J6
H6
G4
G2

A3
E1
R2
C3
E3
C5
G5
J1
J2

R5
G6
P6

D9
C7
C6
M3

PCI_REQ0#
PCI_REQ1#

PCI_GNT1#
PCI_REQ2#

PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
LAMP_STAT

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#

PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

PCI_GNT5#

PCI_REQ1# <31>
PCI_GNT1# <31>

PCI_REQ3# <33>
PCI_GNT3# <33>
PCI_REQ4# <30>
PCI_GNT4# <30>

LAMP_STAT <19>

PCI_C_BE0# <30,31,33>
PCI_C_BE1# <30,31,33>
PCI_C_BE2# <30,31,33>
PCI_C_BE3# <30,31,33>

PCI_IRDY# <30,31,33>
PCI_PAR <30,31,33>

PCI_DEVSEL# <30,31,33>
PCI_PERR# <30,31,33>

PCI_SERR# <30,31,33>

PCI_STOP# <30,31,33>
PCI_TRDY# <30,31,33>

CLK_PCI_ICH <6>

ICH_PME# <34>

12

R328
1K_0402_5%~D @

PCI_PCIRST#

PCI_PLTRST#

Place closely pin G6Pop resistor to boot from PCI

10_0402_5%~D@

8.2P_0402_50V8J~D@

10

9

13
12

CLK_PCI_ICH

R332

C349

+3VSUS

14

P

IN1

8

OUT

IN2

G

U21C

74VHC08MTC_TSSOP14~D

7

+3VSUS

14

P

IN1

11

OUT

IN2

G

U21D

74VHC08MTC_TSSOP14~D

7

1 2
1

2

PCI_RST#

PLTRST#

PCI_RST# <30,31,33>

PLTRST# <10,23,25,34>

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH6(1/4)

TOBAGO-LA2151

21 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+RTC_CELL

12

R276
100K_0402_5%~D

D D

SM_INTRUDER#

Place closely pin C10

ICH_AC_BITCLK

12

R361
10_0402_5%~D

@

2

C362
10P_0402_50V8J~D

1

@

C C

+3VRUN

R414

8.2K_0402_5%~D
R378

33_0402_5%~D

ICH_SDOUT_AUDIO<26>

B B

ICH_SYNC_AUDIO<26>

ICH_RST_AUDIO#<26>

1 2

R82
33_0402_5%~D

1 2

R84
33_0402_5%~D

1 2

C38

12P_0402_50V8J~D

Package

9.6X4.06 mm

12P_0402_50V8J~D

SM_INTRUDER#<15>

IDE_IRQ

12

ICH_AC_SDOUT_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

12

32.768KHZ_12.5P_MC-306~D

C40

12

+RTC_CELL

CMOS_CLR
@SHORT PADS~D

1

1

C348

0.1U_0402_16V4Z~D

1 2

ICH_AC_BITCLK<26>

ICH_SYNC_MDC<29>

ICH_RST_MDC#<29>

ICH_AC_SDIN0<26>
ICH_AC_SDIN1<29>

ICH_SDOUT_MDC<29>

SATA_ACT#<39>

X1

1 2

ICH_RTCX1

ICH_RTCX2

1 2

R297
180K_0402_5%~D

2

2

CLK_PCIE_SATA#<6>
CLK_PCIE_SATA<6>

R36

10M_0402_5%~D

1 2
1 2

1 2

SATA_RXN0_C<25>
SATA_RXP0_C<25>

IDE_DIORDY<25>
IDE_IRQ<25>

IDE_DDACK#<25>

IDE_DIOW#<25>

IDE_DIOR#<25>

12

R8133_0402_5%~D
R8333_0402_5%~D

R371

33_0402_5%~D

ICH_RTCRST#
SM_INTRUDER#

ICH_AC_BITCLK
ICH_AC_SYNC_R

ICH_AC_RST_R#
ICH_AC_SDIN0

ICH_AC_SDIN1

ICH_AC_SDOUT_R

SATA_ACT#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

1 2

R380

24.9_0603_1%~D

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#

AC19

AG11

AF11

AF16
AB16
AB15
AC14
AE16

AA2
AA3

AA5

D12
B12
D11
F13

F12
B11
E12

E11
C13

C12
C11
E13

C10

A10
F11

F10
B10

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

U3A

Y1
Y2

B9

C9

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

LAN

A20GATE

A20M#

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

INIT#
INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

DA[0]
DA[1]
DA[2]

DCS1#
DCS3#

SATAAC-97/AZALIA

DD[0]
DD[1]

IDE

DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]

DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

ICH6_BGA609~D

P2
N3
N5
N4

N6
P4

P3

AF22
AF23

AE27
AE24

AD27
AF24
AG25
AG26

AE22
AF27
AG24

AD23
AF25

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ0#
LPC_LDRQ1#

LPC_LFRAME#

H_CPUSLP_R#

DPRSLP#

FERR#

THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DDREQ

LPC_LAD[0..3] <34>

LPC_LDRQ0# <34>
LPC_LDRQ1# <34>

LPC_LFRAME# <34>

R438 0_0402_5%~D@
R121 0_0402_5%~D

R120 56_0402_5%~D

12
12

12

R115 75_0402_5%~D

1 2

IDE_DA[0..2] <25>

IDE_DCS1# <25>
IDE_DCS3# <25>

IDE_DD[0..15] <25>

IDE_DDREQ <25>

SIO_A20GATE
H_A20M#
H_CPUSLP#

H_DPRSTP#
H_DPSLP#

H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

SIO_RCIN#
H_NMI

H_SMI#
H_STPCLK#

SIO_A20GATE <35>
H_A20M# <7>
H_CPUSLP# <7,10>

H_DPRSTP# <7>
H_DPSLP# <7>
H_FERR# <7>
H_PWRGOOD <7>
H_IGNNE# <7>
H_INIT# <7>

H_INTR <7>

SIO_RCIN# <34>
H_NMI <7>

H_SMI# <7>
H_STPCLK# <7>

+VCCP

H_FERR#

H_DPRSTP#

R118

56_0402_5%~D

R127

56_0402_5%~D

+VCCP

12

12

1 2

SATA_TXP0_C SATA_TXP0

A A

C340 3900P_0402_50V7K~D

1 2

C346 3900P_0402_50V7K~D

Place near ICH6 side.

SATA_TXN0SATA_TXN0_C

SATA_TXN0 <25>

SATA_TXP0 <25>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH6(2/4)

TOBAGO-LA2151

22 51Monday, October 18, 2004

1

0.6

of

5

4

+3VSUS

12

3

2

1

+3VSUS

D D

R351

2.2K_0402_5%~D

ICH_SMBDATA<6>

ICH_SMBCLK<6>

+3VRUN

C C

+3VSUS

B B

A A

1 2

R429 10K_0402_5%~D

1 2

R428 10K_0402_5%~D@

1 2

R112 10K_0402_5%~D

1 2

R432 10K_0402_5%~D

1 2

R111 8.2K_0402_5%~D

R373
10K_0402_5%~D

1 2

R268
10K_0402_5%~D

1 2

R372
10K_0402_5%~D

1 2

R269

8.2K_0402_5%~D

1 2

R318
680_0402_5%~D

1 2

DPRSLPVR<45>

GPI7

SIO_THRM#

MCH_SYNC#

IRQ_SERIRQ

CLKRUN#

LINKALERT#

SYS_RESET#

USB2P0_SMI#

ICH_BATLOW#

ICH_PCIE_W AKE#

+3VRUN

R431

1 2

@

12

R433

100K_0402_5%~D

+3VSUS

33_0402_5%~D

12

12

R352

10K_0402_5%~D

10K_0402_5%~D

R341

R363

1 2

2.2K_0402_5%~D

1K_0402_5%~D

1 2

ICH_SMLINK0
ICH_SMLINK1
ICH_SMBDATA
ICH_SMBCLK

SIO_EXT_WAK#<34>

(PCI Express Wake Event)

SIO_EXT_WAK#

LCD_TST<19,34>

LCD_TST

ICH_PCIE_W AKE#<18,34>

KAPALUA system can't boot issue
May need pulldown for DPRSLPVR in case

the ICH6m does not set this value in time
for boot.

5

4

R303

8.2K_0402_5%~D

R425

12

SPKR<26>

PM_BMBUSY#<10>

SIO_EXT_SMI#<34>

SIO_EXT_SCI#<34>

H_STP_PCI#<6>

H_STP_CPU#<6,45>

R539 0_0402_5%~D@

1 2

PLTRST_DELAY#<18>

SIO_EXT_WAK# GPIO24

CLKRUN#<30,31,33,34>

IDE_UAI<25>

IDE_UAO<25>

IRQ_SERIRQ<31,34>

SIO_THRM#<34>

IMVP_PWRGD<10,38,45>

CLK_ICH_14M<6>
CLK_ICH_48M<6>

SIO_SLP_S3#<34>
SIO_SLP_S5#<34>

ICH_PWRGD<38>

SIO_PWRBTN#<34>

SUSPWROK<15,38>

ICH_RI#

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR

SYS_RESET#
PM_BMBUSY#
GPI7

SIO_EXT_SMI#
USB2P0_SMI#

R526 0_0402_5%~D

GPIO12

12

SIO_EXT_SCI#
H_STP_PCI#

H_STP_CPU#

LCD_TST_ICH
PLTRST_DELAY#

R527 0_0402_5%~D

CLKRUN#
IDE_UAI
IDE_UAO

ICH_PCIE_W AKE#
IRQ_SERIRQ
SIO_THRM#
IMVP_PWRGD
CLK_ICH_14M

CLK_ICH_48M

T36
PAD~D

ICH_SUSCLK

@

SIO_SLP_S3#

SIO_SLP_S5#

ICH_PWRGD

DPRSLPVR

ICH_BATLOW#

SIO_PWRBTN#

PLTRST#

SUSPWROK

12

@

U3C

T2

RI#

AF17

SATA[0]GP/GPI[26]

AE18

SATA[1]GP/GPI[29]

AF18

SATA[2]GP/GPI[30]

AG18

SATA[3]GP/GPI[31]

Y4

SMBCLK

W5

SMBDATA

Y5

LINKALERT#

W4

SMLINK[0]

U6

SMLINK[1]

AG21

MCH_SYNC#

F8

SPKR

W3

SUS_STAT#/LPCPD#

U2

SYS_RESET#

AD19

BM_BUSY#/GPI[6]

AE19

GPI[7]

R1

GPI[8]

W6

SMBALERT#/GPI[11]

M2

GPI[12]

R6

GPI[13]

AC21

STP_PCI#/GPO[18]

AB21

GPO[19]

AD22

STP_CPU#/GPO[20]

AD20

GPO[21]

AD21

GPO[23]

V3

GPIO[24]

P5

GPIO[25]

R3

GPIO[27]

T3

GPIO[28]

AF19

CLKRUN#/GPIO[32]

AF20

GPIO[33]

AC18

GPIO[34]

U5

WAKE#

AB20

SERIRQ

AC20

THRM#

AF21

VRMPWRGD

E10

CLK14

A27

CLK48

V6

SUSCLK

T4

SLP_S3#

T5

SLP_S4#

T6

SLP_S5#

AA1

PWROK

AE20

DPRSLPVR/TP[1]

V2

BATLOW#/TP[0]

U1

PWRBTN#

V5

LAN_RST#

Y3

RSMRST#

12

12

10K_0402_5%~D

R280

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

10K_0402_5%~D

R296

3

GPIO

CLOCK

POWER MGT

PERn[1]
PERp[1]
PETn[1]
PETp[1]

PERn[2]
PERp[2]
PETn[2]
PETp[2]

PERn[3]
PERp[3]
PETn[3]
PETp[3]

PERn[4]
PERp[4]

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETn[4]
PETp[4]

DMI[0]RXN

DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

DMI[1]RXN

DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

DMI[2]RXN

DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

DMI[3]RXN

DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

OC[0]#
OC[1]#
OC[2]#
OC[3]#

USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N

USB

USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P

USBRBIAS#

USBRBIAS

ICH6_BGA609~D

H25
H24
G27
G26

K25
K24
J27
J26

M25
M24
L27
L26

P24
P23
N27
N26

T25
T24
R27
R26

V25
V24
U27
U26

Y25
Y24
W27
W26

AB24
AB23
AA27
AA26

AD25
AC25

F24
F23
C23

D23
C25
C24

C27
B27
B26
C26

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

A22
B22

TP_NC8
TP_NC9
TP_NC10
TP_NC11

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

2

T40 PAD~D
T39 PAD~D
T42 PAD~D
T41 PAD~D

DMI_RXN0 <10>
DMI_RXP0 <10>

DMI_TXN0 <10>
DMI_TXP0 <10>

DMI_RXN1 <10>
DMI_RXP1 <10>

DMI_TXN1 <10>
DMI_TXP1 <10>

DMI_RXN2 <10>
DMI_RXP2 <10>

DMI_TXN2 <10>
DMI_TXP2 <10>

DMI_RXN3 <10>
DMI_RXP3 <10>

DMI_TXN3 <10>
DMI_TXP3 <10>

CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>

R427 24.9_0603_1%~D

1 2

USBP2- <28>

USBP2+ <28>

USBP3- <31>

USBP3+ <31>

USBP4- <28>

USBP4+ <28>

USBP5- <28>

USBP5+ <28>

USBP6- <28>

USBP6+ <28>

USBP7- <28>

USBP7+ <28>

1 2

R113

22.6_0603_1%~D

Place closely pin A27Place closely pin E10

CLK_ICH_48M

12

R126
10_0402_5%~D

@

1

C124

4.7P_0402_50V8C~D

2

@

RN1

10K_1206_8P4R_5%~D

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

RN29

10K_1206_8P4R_5%~D

USB_OC6# <28>
USB_OC7# <28>
USB_OC4# <28>PLTRST#<10,21,25,34>
USB_OC5# <28>

+1.5VRUN

CLK_ICH_14M

12

R379
10_0402_5%~D

@

1

C380

@

2

4.7P_0402_50V8C~D

USB_OC0#
USB_OC3#
USB_OC1#
USB_OC2#

USB_OC6#
USB_OC7#
USB_OC4#
USB_OC5#

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH6(3/4)

TOBAGO-LA2151

23 51Wednesday, November 03, 2004

1

+3VSUS

0.6

of

5

Near PIN F27(C453),

L41

+3VRUN+5VRUN

1 2

1 2

1 2

R407
10_0402_5%~D

@

21

2

C375
1U_0603_10V4Z~D

1

+3VSUS+5VSUS

21

2

C420
1U_0603_10V4Z~D

1

100_0402_5%~D

10_0402_5%~D

+5VSUS

R535

R537

D D

C C

+1.5VRUN

D16
RB751V_SOD323~D

D17

RB751V_SOD323~D

ICH_V5REF_RUN

2

1

2

1

1 2

BLM21PG600SN1D_0805~D

ICH_V5REF_RUN

C370

0.1U_0402_16V4Z~D

ICH_V5REF_SUS

C436

0.1U_0402_16V4Z~D

2

C371

0.1U_0402_16V4Z~D

1

P27(C459), AB27(C454)

+1.5VRUN_L

1

+

C151

2

150U_D2_2VM_R15~D

+1.5VRUN

Near PIN AG5

+1.5VRUN

BLM11A601S_0603~D

5

ICH_V5REF_SUS

L42

1 2

C461

0.1U_0402_16V4Z~D

2

1

ICH6_VCCPLL

1

C458

2

0.01U_0402_16V7K~D

Near PIN
AB27

+3VRUN

Near PIN AG9

C449

Near PIN
E26, E27

+1.5VRUN

2

1

0.1U_0402_16V4Z~D

+3VSUS

Near PIN A17

+5VALW

B B

+1.5VRUN

A A

1 2

R426
10_0402_5%~D

@

R442

1 2

1_0603_5%~D

4

2

2

C454

C453

1

1

0.1U_0402_16V4Z~D

C353

C369

2

C337

1

0.1U_0402_16V4Z~D

Near PIN AE1

2

C405

1

0.1U_0402_16V4Z~D

4

2

C459

1

0.1U_0402_16V4Z~D

2

1

0.1U_0402_16V4Z~D

2

1

0.1U_0402_16V4Z~D

ICH6_VCCPLL

+3VRUN

+3VRUN

+3VSUS

2

C406

1

3

+1.5VRUN

U3E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

PCIE

SATA

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

COREIDE

PCIUSB

USB CORE

PCI/IDE RBP

ICH6_BGA609~D

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]

VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF[2]
V5REF[1]

V5REF_SUS

VCCUSBPLL

VCCSUS3_3[20]

VCCRTC

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VRUN

2

C412

1

2

C339

1

+1.5VSUS

1

2

C423

0.1U_0402_16V4Z~D

+1.5VRUN

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VRUN
+3VSUS

+RTC_CELL

+1.5VRUN

+VCCP

1

2

C442

0.1U_0402_16V4Z~D

2

C388

1

0.1U_0402_16V4Z~D

2

C338

1

0.1U_0402_16V4Z~D

Near PIN U7

Near PIN AG23

+3VRUN

Near PIN
AG13, AG16

0.1U_0402_16V4Z~D

+3VRUN

2

C361

1

Near PIN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

A2-A6, D1-H1

1

2

2

1

C372

0.1U_0402_16V4Z~D

+2.5VRUN

1

2

Near PIN AB18

+3VRUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C365

0.1U_0402_16V4Z~D

C411

C382

1 2

C374

1 2

+1.5VSUS

0.01U_0402_16V7K~D

@

Near PIN AG10

2

C386

0.1U_0402_16V4Z~D

1 2

C376

0.1U_0402_16V4Z~D

1 2

C377

0.1U_0402_16V4Z~D

1 2

C378

0.1U_0402_16V4Z~D

1 2

C387

0.1U_0402_16V4Z~D

1 2

C392

0.1U_0402_16V4Z~D

1 2

C410

0.1U_0402_16V4Z~D

1 2

C394

0.1U_0402_16V4Z~D

1 2

C408

0.1U_0402_16V4Z~D

1 2

C409

0.1U_0402_16V4Z~D

1 2

C452

0.01U_0402_16V7K~D

1 2

Near PIN A25

C424

0.01U_0402_16V7K~D

1 2

Near PIN AA19

+3VSUS

C393

0.1U_0402_16V4Z~D

1 2

C407

0.1U_0402_16V4Z~D

1 2

C422

0.1U_0402_16V4Z~D

1 2

C444

0.1U_0402_16V4Z~D

1 2

Near PIN A24

1

U3D

E27

VSS[172]

Y6

VSS[171]

Y27

VSS[170]

Y26

VSS[169]

Y23

VSS[168]

W7

VSS[167]

W25

VSS[166]

W24

VSS[165]

W23

VSS[164]

W1

VSS[163]

V4

VSS[162]

V27

VSS[161]

V26

VSS[160]

V23

VSS[159]

U25

VSS[158]

U24

VSS[157]

U23

VSS[156]

U15

VSS[155]

U13

VSS[154]

T7

VSS[153]

T27

VSS[152]

T26

VSS[151]

T23

VSS[150]

T16

VSS[149]

T15

VSS[148]

T14

VSS[147]

T13

VSS[146]

T12

VSS[145]

T1

VSS[144]

R4

VSS[143]

R25

VSS[142]

R24

VSS[141]

R23

VSS[140]

R17

VSS[139]

R16

VSS[138]

R15

VSS[137]

R14

VSS[136]

R13

VSS[135]

R12

VSS[134]

R11

VSS[133]

P22

VSS[132]

P16

VSS[131]

P15

VSS[130]

P14

VSS[129]

P13

VSS[128]

P12

VSS[127]

N7

VSS[126]

N17

VSS[125]

N16

VSS[124]

N15

VSS[123]

N14

VSS[122]

N13

VSS[121]

N12

VSS[120]

N11

VSS[119]

N1

VSS[118]

M4

VSS[117]

M27

VSS[116]

M26

VSS[115]

M23

VSS[114]

M16

VSS[113]

M15

VSS[112]

M14

VSS[111]

M13

VSS[110]

M12

VSS[109]

L25

VSS[108]

L24

VSS[107]

L23

VSS[106]

L15

VSS[105]

L13

VSS[104]

K7

VSS[103]

K27

VSS[102]

K26

VSS[101]

K23

VSS[100]

K1

VSS[99]

J4

VSS[98]

J25

VSS[97]

J24

VSS[96]

J23

VSS[95]

H27

VSS[94]

H26

VSS[93]

H23

VSS[92]

G9

VSS[91]

G7

VSS[90]

G21

VSS[89]

G12

VSS[88]

G1

VSS[87]

ICH6_BGA609~D

+RTC_CELL

1

2

C347

0.1U_0402_16V4Z~D

1

2

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

C328

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
ICH6(4/4)

TOBAGO-LA2151

24 51Monday, October 18, 2004

1

0.6

of

A

+3VRUN

1 2

R203 10K_0402_5%~D@

1 2

R192 4.7K_0402_5%~D

1 2

R187 10K_0402_5%~D

1 2

R181 10K_0402_5%~D@

1 2

R179 10K_0402_5%~D@

1 2

R178 10K_0402_5%~D

1 1

1 2

R177 10K_0402_5%~D

1 2

R180 10K_0402_5%~D@

R210 5.6K_0402_5%~D

R191 10K_0402_5%~D

ATAIOSEL
IDE_HIORDY
IDE_HIOCS16#

12

12

T0
T2
T3
T6

T1

IDE_HDREQ

IDE_HINTRQ

HDD Connector

IDE_HRESET#
IDE_HDD6

IDE_HDD5
IDE_HDD4 IDE_HDD11
IDE_HDD3 IDE_HDD12
IDE_HDD2 IDE_HDD13
IDE_HDD1 IDE_HDD14
IDE_HDD0 IDE_HDD15

IDE_HDREQ

+5VHDD

2 2

@

3 3

4 4

IDE_HDIOW#
IDE_HDIOR#
IDE_HIORDY
IDE_HDMACK#
IDE_HINTRQ
IDE_HDA1

R505

IDE_HDA0 IDE_HDA2
IDE_HCS0#

510_0402_5%~D

1 2

IDE_ACT#

+5VHDD

IDE_RST_MOD<34>

IDE_DIOW#<22>

IDE_DIORDY<22>

+5VMOD

IDE_IRQ<22>

IDE_DA1<22>
IDE_DA0<22>
IDE_DCS1#<22> IDE_DCS3# <22>

1 2

R514 510_0402_5%~D

A

JHDD

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

21

21

22

23

23

24

25

25

26

27

27

28

29

29

30

31

31

32

33

33

34

35

35

36

37

37

38

39

39

40

41

41

42

43

43

IDE_DD[0..15]<22>

1 2

IDE_RST_MOD
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1

IDE_LED#

PRI_CSEL

R516
470_0402_5%~D

1 2

44

FOX_HH99223-SA_REVERS~D

C550

47P_0402_50V8J~D

+5VMOD

B

2
4

IDE_HDD9

6

IDE_HDD10

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

R511

470_0402_5%~D

SEC_CSEL

1 2

R509 10K_0402_5%~D

1 2

R508 10K_0402_5%~D

1 2

IDE_HCS1#

+5VHDD

IDE_DD[0..15]

JMOD

1
3
5
7
9

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

42

41

42

44

43

44

46

45

46

48

47

48

50

49

50

SUYIN_80095AR-050G1T~D

CD-ROM Connector

B

+5VHDD

0.1U_0402_16V4Z~D

1

C543

2

1000P_0402_50V7K~D

Pleace near HD CONN

PJP19

1 2

@PAD-OPEN 4x4m
PJP20

1 2

@PAD-OPEN 4x4m

@

10K_0402_5%~D

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#

RPDDACK#
PDIAG#

IDE_DA2IDE_DA0
IDE_DCS3#IDE_DCS1#

1 2

C556

0.1U_0402_16V4Z~D

1

C544

2

IDE_HRESET#

12

R183

IDE_DDREQ <22>

IDE_DIOR# <22>

R513

100K_0402_5%~D

1 2

IDE_DA2 <22>

C

1

C545

2

1U_0603_10V4Z~D

R214 33_0402_5%~D

+5VMOD

C

1 2

IDE_UAO<23>
IDE_UAI<23>

+5VMOD

1

C542

2

0.1U_0402_16V4Z~D

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

IDE_HDA0
IDE_HDA1
IDE_HDA2
IDE_HCS0#
IDE_HCS1#

IDE_HIOCS16#
IDE_HINTRQ
IDE_HDMACK#
IDE_HIORDY
IDE_HDIOR#
IDE_HDIOW#
IDE_HDREQ
IDE_R_HRESET#

D

U11

62

HDD0

64

HDD1

2

HDD2

5

HDD3

7

HDD4

11

HDD5

13

HDD6

15

HDD7

14

HDD8

12

HDD9

10

HDD10

6

HDD11

3

HDD12

1

HDD13

63

HDD14

61

HDD15

50

HDA0

51

HDA1

49

HDA2

48

HCS0#

47

HCS1#

52

HIOCS16#

53

HINTRQ

54

HDMACK#

55

HIORDY

58

HDIOR#

59

HDIOW#

60

HDMARQ

16

HRESET#

46

HPDIAG#

45

UAO

43

UAI

88SA8040_TQFP64~D

IDE_DDACK#<22>

+5VMOD

1

C554
1000P_0402_50V7K~D

2

+5VMOD

1

C552
1000P_0402_50V7K~D

2

D

+1.8VRUN

1

C281

2

4.7U_0805_10V4Z~D

E

0.1U_0402_16V4Z~D

1

C259

2

0.1U_0402_16V4Z~D

1

C278

2

F

Pleace near U178

SATA_RXP0

32

TX_P

SATA

TX_M

RX_P

RX_M

RST#

T0
T1
T2
T3
T4
T5
T6

T7
CNFG2
CNFG1
CNFG0

ATAIOSEL

XTLIN/OSC

Parallel ATA

UART

+3VRUN

1

C555

0.1U_0402_16V4Z~D

2

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

XTLOUT

Config & Debug

ISET
VDDIO_0
VDDIO_1

VDD_0
VDD_1
VDD_2

VAA1
VAA2

Power

VSS1

VSS2
GND_0
GND_1
GND_2

IDE_DIORDY

1 2

R512 4.7K_0402_5%~D

1 2

R510 22_0402_5%~D

1

2

C553

0.1U_0402_16V4Z~D

1

2

SATA_RXN0

31

SATA_TXP0

27

SATA_TXN0

28

PLTRST#

17

T0

33

T1

34

T2

35

T3

36
37

T5

38

T6

39
40

CNFG2

20

CNFG1

19

CNFG0IDE_HDD7 IDE_HDD8

18

ATAIOSEL

21

IDE_XTLIN

22

IDE_XTLOUT_R

23

12.1K_0603_1%~D

26

R186

4
44
9
41
56
24
29

25
30
8
42
57

RPDDACK#

C559
1U_0603_10V4Z~D

C551
1U_0603_10V4Z~D

E

1 2

12

1

C272

2

0.01U_0402_16V7K~D

1

C274
10U_0805_10V4M~D

2

1

C557
10U_0805_10V4M~D

2

SATA_TXP0 <22>
SATA_TXN0 <22>

PLTRST# <10,21,23,34>

R182

10K_0402_5%~D

+3VRUN +3VRUN

1

2

PWR_VAA

1

C271

2

0.1U_0402_16V4Z~D

1 2

1

C260

C277

2

1000P_0402_50V7K~D

2.2U_0805_6.3V6K~D

F

+1.8VRUN

L20

BLM31A260SPT_1206~D

C256

G

Sets maximum transfer rate and UDMA mode

CNFG0CNFG2 CNFG1

*

000

INT PDINT PD

001
010
100

110
110
0 1 1 Reserved
1 1 1 Reserved

CNFG2
CNFG1
CNFG0

+3VRUN

1

1

1

2

2

2

4.7U_0805_10V4Z~D

SATA_RXN0

SATA_RXP0 SATA_RXP0_C

C258

C282

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

NOTE

Device Mode 100MB/s
Device Mode 133MB/s
Device Mode 150MB/s

Host Mode 100MB/s

Host Mode 133MB/s
Host Mode 150MB/s

+3VRUN +3VRUN +3VRUN

12

R205
10K_0402_5%~D

@

12

R206
10K_0402_5%~D

@

12

R211
10K_0402_5%~D

@

12

R212
10K_0402_5%~D

IDE_XTLOUT_R

12

R204
1M_0402_5%~D

@

1 2

@

25MHZ_20P_1BG25000CK1A

Y3

3

OUT

2

GND

25MHZ_30P_1XSA025000AVH~D

1

C280
12P_0402_50V8J~D

2

@

Y1

VDD

OE

25MHz refere n c e clock T[4:3] = 01

C2703900P_0402_50V7K~D

SATA_RXN0_C

12

C2623900P_0402_50V7K~D

12

SATA_RXN0_C <22>

SATA_RXP0_C <22>

Place near connector side.

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SATA Bridge

TOBAGO-LA2151

G

H

12

R213
10K_0402_5%~D

@

12

R207
10K_0402_5%~D

@

IDE_XTLOUTIDE_XTLIN

PWR_VAA

4
1

25 51Monday, October 18, 2004

H

12

R190

@

0_0402_5%~D

1

C279

12P_0402_50V8J~D

2

@

0.6

of

5

4

3

2

1

C524

0.1U_0402_16V4Z~D

9

DVDD11DVDD2

+VDDA

1

C500

2

1

C169

2

2.2U_0805_6.3V6K~D

38

LINE_IN_L

AVDD125AVDD2

LINE_IN_R

CD_GND

AUX_R

VIDEO_L
VIDEO_R

PHONE

PC_BEEP

HP_OUT_L

HP_COMM

HP_OUT_R

MONO_OUT

LOUT_L

LOUT_R

AVSS126AVSS2

STAC9751TG_TQFP48~D

42

1

2

0.1U_0402_16V4Z~D

CD_L

CD_R

AUX_L

MIC1
MIC2

1 2

1

C505

2

0.047U_0402_16V4Z~D

+VDDA

LINE_IN_L

23

LINE_IN_R

24
18

19

20

14

15

CNB_MICIN

21
22
16
17

9750_PHONE

13

PC_BEEP

12

HP_OUT_L

39

HP_COMM

40

HP_OUT_R

41

37

35

36

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+5VSUS

1

C486

C492

2

1U_0603_10V4Z~D@

0.01U_0402_16V7K~D @

ICH_RST_AUDIO#

ICH_SYNC_AUDIO

ICH_SDOUT_AUDIO

1

C499

2

@

2

AUDIO_AVDD_ON<35>

1

C516
10P_0402_50V8J~D@

1 2

C507
10P_0402_50V8J~D@

1 2

C501
10P_0402_50V8J~D@

1 2

1

C503

C513

2

@

@

27P_0402_50V8J

27P_0402_50V8J

2

C201

1

2.2U_0805_6.3V6K~D

CLK_CODEC_14M<6>

5

AUDIO_AVDD_ON TPS793475_BYPASS

R157

33_0402_5%~D

1 2

R155

33_0402_5%~D

1 2

R160

33_0402_5%~D

1 2

1

2

27P_0402_50V8J

2

2

C181

C200

0.1U_0402_16V4Z~D

1

1

1U_0603_10V4Z~D

Pop C491 for Crystal,
Pop R153 for CLK input

R153

0_0402_5%~D

22P_0402_50V8J~D

@

22P_0402_50V8J~D

@

1

C498

D D

C C

B B

A A

2

0.1U_0402_16V4Z~D@

ICH_AC_BITCLK<22>

MDC_AC_BITCLK<29>

ICH_AC_SDIN0<22>

Place closely pin 5

ICH_SDOUT_AUDIO

12

R488
47_0402_5%~D

@

1

C495
22P_0402_50V8J~D

2

@

Place closely pin 2

CLK_CODEC_14M

12

R472
33_0402_5%~D

@

1

C484
22P_0402_50V8J~D

2

@

ICH_RST_AUDIO#<22>
ICH_SYNC_AUDIO<22>
ICH_SDOUT_AUDIO<22>

12

C491

12

C490

12

R150

0_0402_5%~D

2

SPK_SHUTDOWN#<27>

U22

TPS793333DBVR_SOT23-5~D@

C176

C194 1000P_0402_50V7K~D
C191 1000P_0402_50V7K~D
C196 0.1U_0402_16V4Z~D

5

IN1OUT
GND

4

EN3BYPASS

+3VRUN

2

2

C506

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 2
1 2
1 2

@

AC97VREFI

+3VRUN

EAPD<27>

XTL_24M-

X5

24.576MHz_16P_3XG-24576-43E1

PACKAGE : 8X4.5X1.5mm

@

1 2

XTL_24M+

12

C487

2.2U_0805_6.3V6K~D

ICH_RST_AUDIO#
ICH_SYNC_AUDIO
ICH_SDOUT_AUDIO

R_ICH_AC_BITCLK

R_ICH_AC_SDIN0

SPK_SHUTDOWN#

R486

10K_0402_5%~D

1 2

EAPD

C523

W=30 mil

2

1

AFLT1
AFLT2
VREFOUT

CAP2

R485

1K_0402_5%~D@

1 2
1 2

R484

1K_0402_5%~D@

4

+VDDA=3.3V

1

2

0.1U_0402_16V4Z~D@

U10

11

RESET#

10

SYNC

5

SDATA_OUT

6

BIT_CLK

8

SDATA_IN

29

AFLT1
AFLT2
VREFOUT
VREF

CAP2
GPIO0/NC

GPIO1/NC

SPDIF
EAPD

NC/BPCFG

NC/FLTIN

NC/FLTOUT
CID1

CID0
XTL_OUT

XTL_IN

STAC9751

DVSS14DVSS2

7

30
28
27

32
43

44

48
47

31

33

34
46

45

3

2

+3VRUN

L47

BLM31A260SPT_1206~D

CBS_SPK<31>

SN74LVC2G86DCTR_SSOP8~D

SPKR<23>

+VDDA

1 2

0_0402_5%~D

@

12

12

R529

0_0402_5%~D

R530

C511

0.33U_0603_10V7K~D

1 2
1 2

0_0402_5%~D

C526

0.1U_0402_16V4Z~D

Noise Concem, pop it.

C525

1 2

0.1U_0402_16V4Z~D

1 2

R476
0_0402_5%~D

2

C189
1000P_0402_50V7K~D

1

2

C179
1000P_0402_50V7K~D

1

U28A

1
2

BEEP<34>

1

5

U30

P

NC

A2Y

G

NC7SZ04P5X_SC70-5~D

3

R528

C510 1U_0603_10V4Z~D@

1 2

C512 1U_0603_10V4Z~D@

1 2

+VDDA

L48
BLM11A121S_0603~D

1 2

8

P

1A

7

1Y

1B

G

4

4

HP_OUT_L <27>

HP_OUT_R <27>

AUD_LINE_OUT_L <27>

AUD_LINE_OUT_R <27>

Z2401

Z2402

2

8

5

P

2A

2Y

6

2B

G

U28B

4

SN74LVC2G86DCTR_SSOP8~D

EMICIN <27>

EXTMIC_BIAS <27>

EMICIN <27>

1

C539

0.1U_0402_16V4Z~D

2

3

45

2

31

single gate TTL

R496

10K_0402_5%~D

1 2

Z2404Z2403 PC_BEEP

8.2K_0402_5%~D

@

R162

C529

0.1U_0402_16V4Z~D

1 2

12

2

C518
1000P_0402_50V7K~D

1

@

TRACE>15 mil

CLOCK SOURCE

14.318 MHz
27 MHz
48 MHz

24.576 MHz

Pin46
CID1

OPEN

1K

Pin45
CID0

OPENOPEN

1K

OPEN

1K1K

Pin3
XTL_OUT

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
AC97 Codec

TOBAGO-LA2151

26 51Monday, October 18, 2004

1

of

GND
GND
GND
GND

0.6

5

4

3

2

1

G

U5

SHDNR#
SHDNL#

INR
INL

C1P
C1N

C113

13

D

S

+VDDA

10

19

SVDD

PVDD

PGND

PVss

SVss

SGND

2

5

7

17

1

2

JSPK

1

1

2

2

3

3

4

4

5

5

6

6

MOLEX_53398-0490~D

AUD_LINE_OUT_R<26>

AUD_LINE_OUT_L<26>

SPK_SHUTDOWN#

Q42

2N7002_SOT23~D

4

1

C114
1U_0603_10V4Z~D

2

11

OUTR

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

MAX4411ETP-T_TQFN20~D

1 2

1 2

1 2

1 2

2

NB_MUTE<34>

G

C536

0.1U_0603_50V4Z~D
C199

0.1U_0805_25V7K~D

C535

0.1U_0603_50V4Z~D
C206

0.1U_0805_25V7K~D

13

D

Q43

S

2N7002_SOT23~D

HP_SPK_L1

HP_SPK_R1

1

2

+5VSUS

12

EMICIN<26>

L16

BLM11A121S_0603~D

12

12

L15

BLM11A121S_0603~D

1K_0402_5%~D

1 2

R136

100_0402_5%~D

2

C108

1

R143

100P_0402_50V8J~D

C109

2

1

EMICIN_R

100P_0402_50V8J~D

C154

100P_0402_50V8J~D

EXTMIC_BIAS<26>

1

2

C157

1

2

C163

2

1

100P_0402_50V8J~D

4.7U_0805_10V4Z~D

LINE OUT

L45

1 2

W=40mils

C534

0.1U_0402_16V4Z~D
U27

7

RIN+

17

RIN-

9

LIN+

5

LIN-

16

15

6

VDD

PVDD1

+5VAMPVCC

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BLM21AF121SN1D_0805~D

1

2

AUD_GAIN0

2

AUD_GAIN1

3

INT_SPK_R1

18

INT_SPK_R2

14

INT_SPK_L1

4

INT_SPK_L2

8

Will Change to 3W pe r c hannel device (TPA2008D2)

12

NC

19

SHUTDOWN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

BYPASS

GND41GND311GND213GND1

TPA6017A2PWPR_TSSOP20~D

20

3

BYPASS

10

+5VRUN

C485
10U_0805_10V4M~D

1

C537

0.47U_0603_16V4Z~D

2

1

C502

0.1U_0402_16V4Z~D

2

1

C533

0.1U_0402_16V4Z~D

@

2

EXTMIC_BIAS

L17

BLM11A121S_0603~D

12

12

L19

BLM11A121S_0603~D

HP_SPK_L2

HP_SPK_R2

HP_NB_SENSE<34>

+5VAMPVCC

1

2

2

C153

100P_0402_50V8J~D

C494

0.1U_0402_16V4Z~D

JAUDIO

AUD_GAIN0
AUD_GAIN1

A1
A2
A6

A3
A4
A5

B1
B2
B6

B3
B4
B5

0

1

0

11

789

+5VAMPVCC

12

12

10dB

15.6dB

21.6dB

10

11

R165
10K_0402_5%~D

R171
10K_0402_5%~D@

6dB

FOX_JA8333L-2ST-FR~D

Gain Setting

12

12

IMPEDANCE

EMIC_IN

R149

2K_0402_5%~D

1 2

2

1

*

2

C177

1

100P_0402_50V8J~D

GAIN0 INPUTAV(inv)GAIN1

0

0

1

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
AMP and PHONE JACK

TOBAGO-LA2151

27 51Monday, October 18, 2004

1

R164
10K_0402_5%~D

R170
10K_0402_5%~D@

90K ohm

70K ohm

45K ohm

25K ohm

of

0.6

+VDDA

12

D D

HP_OUT_R<26>
HP_OUT_L<26>

C C

R132
100K_0402_5%~D

HP_NB_SENSE

C148

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1 2
1 2

C147

1

2

AUD_LINE_IN_R
AUD_LINE_IN_L

C146
1U_0603_10V4Z~D

14
18

15
13

1
3

1U_0603_10V4Z~D

Speaker Connector

INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2

15 mils trace

1

1

C568

2

@

0.1U_0402_16V4Z~D

R156
100K_0402_5%~D

1 2

13

D

Q15

S

2N7002_SOT23~D

C567

@

0.1U_0402_16V4Z~D

2

B B

+3VRUN

SPK_SHUTDOWN#<26>

A A

EAPD<26>

5

2

G

1

C566

2

@

0.1U_0402_16V4Z~D

HP_NB_SENSE

1

C565

2

@

0.1U_0402_16V4Z~D

2

5

D D

L51 DLW 21SN900SQ2_0805~D

USBP2-<23>

USBP2+<23>

CBS_CAD15<31>

C C

USBP4-<23>

USBP4+<23>

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L21 DLW 21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L7 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

@

R520

R519

@

R217

R218

@

R27

R26

2

2

3

3

2

2

3

3

2

2

3

3

4

USBP2_D-

USBP2_D+

CBS_CAD13_L

CBS_CAD15_L

USBP4_D-

USBP4_D+

USBP2_D- <29>

USBP2_D+ <29>

CBS_CAD13_L <32>CBS_CAD13<31>

CBS_CAD15_L <32>

USBP4_PWR

USBP5_PWR

USBP6_PWR

3

USBP7_PWR

R14

1 2

0_0805_5%~D

R22

1 2

0_0805_5%~D

PJP21

PAD-OPEN 4x4m

R96

1 2

0_0805_5%~D

R109

1 2

0_0805_5%~D

2

USB PORT#

1

12

C18

C288

@

PJP22

PAD-OPEN 4x4m

1

+

C19

2

0.1U_0402_16V4Z~D

150U_D_6.3VM_R55~D

1

+

C292

2

0.1U_0402_16V4Z~D

150U_D_6.3VM_R55~D

12

C66

150U_D_6.3VM_R55~D

C78

@

150U_D_6.3VM_R55~D

USBP4_VCC

2

USBP4_D­USBP4_D+
USBP4_GND

USBP5_VCC
USBP5_D­USBP5_D+
USBP5_GND

1

2

1

1

+

C76

2

2

0.1U_0402_16V4Z~D

1

1

+

C90

2

2

0.1U_0402_16V4Z~D

USBP7_VCC
USBP7_D­USBP7_D+
USBP7_GND

USBP6_VCC
USBP6_D­USBP6_D+
USBP6_GND

JUSB1

A1

A_VCC

A2

A_D-

A3

A_D+

A4

A_GND

B1

B_VCC

B2

B_D-

B3

B_D+

B4

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB11123-8Z1-TR~D

A1
A2
A3
A4

B1
B2
B3
B4

9
10
11
12

JUSB2

A_VCC
A_D­A_D+
A_GND

B_VCC
B_D­B_D+
B_GND

G1
G2
G3
G4

FOX_UB11123-8Z1-TR~D

0
1
2
3
4
5
6
7

Reserve
Reserve
BlueTooth
NEW Connector
JUSB1(UP)
JUSB1(LOW)
JUSB2(LOW)
JUSB2(UP)

1

DESTINATION

L8 DLW21SN900SQ2_0805~D

USBP5-<23>

USBP5+<23>

B B

USBP6-<23>

USBP6+<23>

USBP7-<23>

A A

USBP7+<23>

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L13 DLW 21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L14 DLW 21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

5

2

@

2

3

3

R29

R28

2

@

2

3

3

R56

R55

2

@

2

3

3

R66

R62

USBP5_D-

USBP5_D+

USBP6_D-

USBP6_D+

USBP7_D-

USBP7_D+

4

+5VSUS

USB_BACK_EN#<34>

1

1

2

1

2

C13
10U_0805_10V4M~D

2

USB_SIDE_EN#<34>

1

C342
10U_0805_10V4M~D

2

C9

0.1U_0402_16V4Z~D

+5VSUS

C343

0.1U_0402_16V4Z~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USB_BACK_EN#

USB_SIDE_EN#

U14

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

U17

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

2

USBP4_PWR USBP5_PWR

8

OC1#

7

OUT1

6

OUT2

5

OC2#

8

OC1#

7

OUT1

6

OUT2

5

OC2#

USB_OC4#

USB_OC5#

USBP6_PWRUSBP7_PWR

USB_OC7#

USB_OC6#

USB_OC4# <23>

USB_OC5# <23>

USB_OC7# <23>

USB_OC6# <23>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
USB 2.0 Port

TOBAGO-LA2151

28 51Monday, October 18, 2004

1

of

0.6

5

4

3

2

+5VRUN

1

LCM & Direct play SW & T PAD

12

D D

KSO17<34>
M_LED_A<35>
M_LED_B<35>
M_LED_C<35>

LID_CL#<34>

KSO17
M_LED_A
M_LED_B
M_LED_C
LID_CL#
TP_CLK

+5VALW

C561

0.1U_0402_16V4Z~D

1

2

JLCM

112
334
556
778
9910

11

12

11

13

14

13
151516

17

17

18

19

19

20

JST_BM20B-SRDS-G-TFC

2
4
6
8
10
12
14
16
18
20

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6

1

C275

0.1U_0402_16V4Z~D

2

KSI0 <35,36>
KSI1 <35,36>
KSI2 <35,36>
KSI3 <35,36>
KSI4 <35,36> DAT_SM2 <35>
KSI5 <35,36>
KSI6 <35,36>

+5VRUN

TP_DATA
TP_CLKTP_DATA

1

C562

2

10P_0402_50V8J~D

L50

BLM11A601S_0603~D

L49

BLM11A601S_0603~D

1

C560

2

10P_0402_50V8J~D

0402 Resistor reserve for ESD

12

4.7K_0402_5%~D

12
12

1

2

10P_0402_50V8J~D

R515

C558

R517

4.7K_0402_5%~D

DAT_SM2
CLK_SM2

1

C563

2

10P_0402_50V8J~D

CLK_SM2 <35>

C C

0.1U_0402_16V4Z~D

COEX2_WLAN_ACTIVE<33>

COEX1_BT_ACTIVE<33>

COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE

T31 PAD~D

@

Place near BT

B B

ICH_SDOUT_MDC

MDC_SDIN

4

C93
10P_0402_50V8J~D@

1 2

C82
10P_0402_50V8J~D@

1 2

C73
10P_0402_50V8J~D@

1 2

ICH_SDOUT_MDC<22>

ICH_SYNC_MDC<22>

ICH_RST_MDC#<22>

R91

33_0402_5%~D

ICH_AC_SDIN1<22>

A A

5

1 2

ICH_SDOUT_MDC

ICH_SYNC_MDC

ICH_RST_MDC#

BT_ACTIVE<39>

HW_RADIO_DIS#<33,35>

USBP2_D-<28>
USBP2_D+<28>

JMDC

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

HW_RADIO_DIS#
COEX3

USBP2_D­USBP2_D+

12

R518

10K_0402_5%~D

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

131314141515161617171818191920

1

C570

2

33P_0402_50V8J~D

2
4
6
8
10
12

20

TYCO_1-179373-2~D

Connector for MDC Rev1.5

1

C564

2

1

C596

2

@

100P_0402_50V8J~D

W=20 mil

MDC_AC_BITCLK

+3VRUN

JBT

1

1

2

2

3

3

4

4

5

11

5

11

6

12

6

12

7

7

8

8

9

9

10

10

JST_BM10B-SRSS-TB~D

ICH_SDOUT_MDC

MDC_AC_BITCLK<26>

+3VSUS

1

1

C89

C403

4.7U_0805_10V4Z~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

2

0.1U_0402_16V4Z~D

MDC_AC_BITCLK

R406

C396

R98

1 2

1 2

10_0402_5%~D@

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

2

2

C86

10P_0402_50V8J~D@

10P_0402_50V8J~D@

1

1

2

New MDC connector.

1

GND

3

IAC_SDATA0

5

GND

7

IAC_SYNC

9

IAC_SDATAIN

11 12

IAC_RESET#

IAC_BITCLK

RES
RES

3.3V
GND
GND

2
4
6
8
10

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
BT PORT and MDC

TOBAGO-LA2151

29 51Monday, October 18, 2004

1

of

0.6

5

+3VLAN

0.1U_0402_16V4Z~D

1

2

10U_0805_10V4M~D

D D

C C

B B

A A

1

C397

1

2

C399

2

0.1U_0402_16V4Z~D

PCI_AD[0..31]<21,31,33>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#<21,31,33>
PCI_C_BE2#<21,31,33>
PCI_C_BE1#<21,31,33>
PCI_C_BE0#<21,31,33>
PCI_FRAME#<21,31,33>
PCI_IRDY#<21,31,33>
PCI_TRDY#<21,31,33>

PCI_DEVSEL#<21,31,33>

PCI_STOP#<21,31,33>
PCI_PERR#<21,31,33>

PCI_SERR#<21,31,33>

PCI_PAR<21,31,33>

PCI_PIRQC#<21,31>

PCI_RST#<21,31,33>

CLK_PCI_LOM<6>

PCI_GNT4#<21>

PCI_REQ4#<21>
SYS_PME#<31,33,34>

CLKRUN#<23,31,33,34>

XI

1 2

25MHZ_20PF_1BG25000CK1A~D

C321
27P_0402_50V8J~D

1 2

R383 100_0402_5%~D

LAN_AD16

Y2

XO

LAN_AD16PCI_AD16

5

1

C301

2

PCI_AD[0..31]

122
123
124
126
127
128

116
117

118
119
121
113

12

R264

820_0402_5%~D

1

C312
27P_0402_50V8J~D

2

0.1U_0402_16V4Z~D

1

C327

2

U19

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26

1

PCI_AD25

3

PCI_AD24

6

PCI_AD23

8

PCI_AD22

9

PCI_AD21

10

PCI_AD20

11

PCI_AD19

14

PCI_AD18

15

PCI_AD17

16

PCI_AD16

33

PCI_AD15

34

PCI_AD14

36

PCI_AD13

37

PCI_AD12

38

PCI_AD11

39

PCI_AD10

41

PCI_AD9

42

PCI_AD8

45

PCI_AD7

48

PCI_AD6

49

PCI_AD5

50

PCI_AD4

51

PCI_AD3

53

PCI_AD2

54

PCI_AD1

55

PCI_AD0

4

PCI_CBE3_L

18

PCI_CBE2_L

32

PCI_CBE1_L

43

PCI_CBE0_L

20

PCI_FRAME_L

21

PCI_IRDY_L

23

PCI_TRDY_L

26

PCI_DEVSEL_L

27

PCI_STOP_L

28

PCI_PERR_L

29

PCI_SERR_L

31

PCI_PAR
PCI_INT_L

PCI_RST_L
PCI_CLK
PCI_GNT_L
PCI_REQ_L
PCI_PME_L

5

PCI_IDSEL

22

PCI_CLKRUN_L

67

XTAL_IN

66

XTAL_OUT

BCM4401_LQFP128

1

C334

2

0.1U_0402_16V4Z~D

+3VLAN

+1.8VLAN

112

44

VDDCORE1

VDDCORE217VDDCORE3

0.1U_0402_16V4Z~D

1

C350

2

+3VLAN

115

125

7

VDDBUS1

VDDBUS2

VDDBUS319VDDBUS430VDDBUS540VDDBUS652VDDBUS7

Broadcom

BCM 4401L

VSS012VSS146VSS2

111

100

4

1

C373

2

0.1U_0402_16V4Z~D

+1.8VLAN

97

106

94

NC10

VDDIO179VDDIO2

REG_AVDD196REG_AVDD2

VSS3

VSS484VSS52VSS624VSS774VSS813VSS947VSS10

120

4

VSS11

35

REG_VOUT191REG_VOUT2

92

1

2

+3VLAN

114

VESD1

C400

0.1U_0402_16V4Z~D

+3VLAN

1

2

68

65

56

VESD225VESD3

LED0_L

XTAL_AVSS

XTAL_AVDD

LED1_L
LED2_L
LED3_L

EPHY_AGND
EPHY_AVDD

EPHY_BIAS_AVDD
EPHY_BIAS_AVSS

EPHY_PLLVDD
EPHY_PLLGND

EPHY_VREF

EPHY_RDAC

EPHY_TESTMODE

EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN

VAUX_AVAIL

BOOTROM_SCL

BOOTROM_SDA

SPROM_CS

SPROM_CLK

SPROM_DOUT

SPROM_DIN

EXT_POR_L

JTAG_TDO

JTAG_TCK

JTAG_TDI

JTAG_TRST_L

JTAG_TMS

Place closely pin 118

CLK_PCI_LOM

12

R408
33_0402_5%~D

@

1

C417
22P_0402_50V8J~D

2

@

+1.8VLAN

1

C360

4.7U_0805_10V4Z~D

2

C307
1000P_0402_50V7K~D

10K_0402_5%~D

LINK_LED10#

75

LINK_LED100#

76

ACTLED#

77
78

58
57

69
70

EPHY_PLLVDD

64
63

71
72
88

62
61
59
60

104

NC0

105

NC1

103

NC2

108

NC3

102

NC4

109

NC5

110

NC6

107

NC7

87
86

NC8

85

NC9

90
93

98
95
101
99

89
83

80
82
73
81

3

0.1U_0402_16V4Z~D

1

C398

2

0.1U_0402_16V4Z~D

L27

BLM11A121S_0603~D

12

R68

R304 10K_0402_5%~D
R319 1.27K_0402_1%~D

LAN_TX+
LAN_TX­LAN_RX+
LAN_RX-

LAN_RX+
LAN_RX­LAN_TX+
LAN_TX-

12

R71
10K_0402_5%~D

L12

1 2

220n_LCN0603T-R22J-S_5%_0603~D

@
1 2
1 2

+3VLAN

12

R78
1K_0402_5%~D

SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DI

LAN_LOW_PWR <35>

EPHY_PLLVDD

C25

4.7U_0805_10V4Z~D

R30 49.9_0603_1%~D
R31 49.9_0603_1%~D12C20 0.1U_0402_16V4Z~D
R33 49.9_0603_1%~D
R32 49.9_0603_1%~D

1

2

12

+3VLAN

+1.8VLAN
+3VLAN

12
12

12

C355

+3VLAN+3VSUS

12

R74
10K_0402_5%~D

1

2

0.1U_0402_16V4Z~D

1

C295

2

15 mil

Place close
to pin 69

+1.8VLAN

2

C39
1000P_0402_50V7K~D

1

C21 0.1U_0402_16V4Z~D

1

2

1 2
1 2

C300

0.1U_0402_16V4Z~D

Place close
to pin 57

1

C356

2

1000P_0402_50V7K~D

SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DI

ACTLED#

LAN_TX+

LAN_TX­LAN_RX+

LAN_RX-

LINK_LED10#
LINK_LED100#

Place close to LAN chip

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+3VLAN

1

10U_0805_10V4M~D

2

R89

@

10K_0402_5%~D

C401

12

C30 0.01U_0402_16V7K~D

+3VLAN

@

+3VLAN

1

2

2

WLAN_LINK_80211A

WLAN_LINK_10_LDE

WLAN_ACT_LED

WLAN_LINK_80211A
WLAN_LINK_10_LDE

1

C55

0.1U_0402_16V4Z~D

2

12

R87

U1

10K_0402_5%~D

1

CS

2

SK

3

DI

4

DO

AT93C46-10SI-2.7_SO8~D

C33 0.01U_0402_16V7K~D

C32 0.01U_0402_16V7K~D

1

1

2

2

2

WLAN LOM

1

C60

0.1U_0402_16V4Z~D

2

+3VLAN

8

VCC

7

NC

6

ORG

5

GND

+3VLAN

12

12

R225

R226

200_0402_5%~D

200_0402_5%~D

13

14
11
12
10

4
6
5
3
1
2
8
7
9

16

17

C31 0.01U_0402_16V7K~D

1

2

15

1

C34

@

2

1000P_0402_50V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

LINK_LED100#

LINK_LED10#

ACTLED#

NC

1

C63

0.1U_0402_16V4Z~D

2

12

1

R430

C421

2

@

100K_0402_5%~D

0.1U_0402_16V4Z~D

1Kb

10K Pullup

4Kb

16Kb

JLOM

YELLOW

COMMON0
TRD1P
TRCT1
TRD1N
TRD2P
TRCT2
TRD2N
TRD3P
TRCT3
TRD3N
TRD4P
TRCT4
TRD4N
COMMON1

GREEN
ORANGE

TYCO_1368398-1~D

Compal Electronics, Inc.

BROADCOM 4401L LAN

TOBAGO-LA2151

1

LED (JP28)

ORANGE (100M)

GREEN (10M)

YELLOW

ORANGE/GREEN

1

C70

0.1U_0402_16V4Z~D

2

None

None

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

4 X 75 OHMS

1000pF 2KV

1

SPROM_CLKSPROM_DOUT

None

None

10K Pullup

SHIELD018SHIELD1

19

30 51Monday, October 18, 2004

TRP1P

TRP1N

TRP2P

TRP2N

TRP3P

TRP3N

TRP4P

TRP4N

202021

21

0.6

of

5

PCI_AD[0..31]<21,30,33>

D D

PCI_C_BE3#<21,30,33>
PCI_C_BE2#<21,30,33>
PCI_C_BE1#<21,30,33>
PCI_C_BE0#<21,30,33>

PCI_PAR<21,30,33>

PCI_FRAME#<21,30,33>
PCI_TRDY#<21,30,33>

C C

B B

CLK_PCI_PCM

@

10_0402_5%~D

12

R491

@

A A

4.7P_0402_50V8C~D

CK33M_CBS_TERM

C515

2

1

PCI_AD17 CBS_IDSEL

CLKRUN#<23,30,33,34>

+3VSUS

+3VSUS

100K_0402_5%~D

12

R490

CBS_GRST#

1U_0603_10V4Z~D

1

C504

2

5

PCI_IRDY#<21,30,33>
PCI_STOP#<21,30,33>
PCI_DEVSEL#<21,30,33>

1 2

PCI_PERR#<21,30,33>
PCI_SERR#<21,30,33>

PCI_REQ1#<21>
PCI_GNT1#<21>

CLK_PCI_PCM<6>

PCI_RST#<21,30,33>

R163 0_0402_5%~D@

1 2

R168 10K_0402_5%~D

1 2

PCI_PIRQD#<21,33>
PCI_PIRQC#<21,30>
PCI_PIRQB#<21,33>

+3VSUS

+3VSUS

R154 10K_0402_5%~D

1 2

R161 10K_0402_5%~D

1 2

R477 10K_0402_5%~D

1 2

SYS_PME#<30,33,34>
CBS_SPK<26>
CB_HWSPND#<34>

R487 100K_0402_5%~D

1 2

IEEE1394_TPBIAS0

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

R169100_0402_5%~D

IRQ_SERIRQ<23,34>

CBS_SPK

R139

R459

C475

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ1#
PCI_GNT1#

PCI_RST#
CBS_GRST#

56.2_0603_1%~D

12

56.2_0603_1%~D

12

Z3008

270P_0402_50V7K~D

2

1

R138

R460

R450

M2
M1
N5
N4
N2
N1

P5

P4
R4
R2
R1

T2

T1
U2
U1

V1

T7

V7

W7

R8

T8

V8

W8

R9

V9

W9
T11
V11

W11

T12
V12

W12

P2
W2
W6

T9

V6

V3
W4

V4

V5

T5

P1

W5

T6

M4
M5

K1

L4

G2

L5

J2

K4

K2

J4

H1
H2
H4
H5
G1

G4

F1

F2

F4

56.2_0603_1%~D

12

56.2_0603_1%~D

12

5.1K_0603_1%~D

1 2

4

U25A

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR

FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL

PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#

INTA#
INTB#
INTC#

UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

RI_OUT#/PME#
SPKROUT
HWSPND#
TEST

R5C841_CSP208~D

0.01U_0402_16V7K~D
C149

C152

1

1

2

2

4

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1

R5C841

CSTSCHG/BVD1(STSCHG#/RI#)

0.33U_0603_10V7K~D

CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7

CAD6/CDATA13

CAD5/CDATA6

CAD4/CDATA12

CAD3/CDATA5

CAD2/CDATA11

CAD1/CDATA4
CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CCLKRUN#/WP(IOIS16#)

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CAUDIO/BVD2(SPKR#/LED)

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19

CAD11/OE#

CAD10/CE2#

CCD1#/CD1#
CCD2#/CD2#

T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14

CBS_CC/BE3#

F16

CBS_CC/BE2#

K18

CBS_CC/BE1#

P15

CBS_CC/BE0#

V19

CBS_CPAR

N15

CBS_CFRAME#

K16

CBS_CTRDY#

L16

CBS_CIRDY#

K15

CBS_CSTOP#

M16

CBS_CDEVSEL#

L18

CBS_CBLOCK#

N19

CBS_CPERR#

N18

CBS_CSERR#

G16

CBS_CREQ#

G19

CBS_CGNT#

M15

CGNT#/WE#

CVS1/VS1#
CVS2/VS2#

4

3
2

1

R246 0_0402_5%~D

R245 0_0402_5%~D

R244 0_0402_5%~D

R243 0_0402_5%~D

E18
A18
L19

M18

H19

F19

T14
D15
R16
H16

W18
C19
N16

L29

4

3
2

1

857CM-0009~D

@

CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_INTERNAL

CBS_CINT#

CBS_CRST#

CBS_CAUDIO

CBS_CCD1#_INTERNAL
CBS_CCD2#_INTERNAL
CBS_CVS1
CBS_CVS2

CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18

5

5

6

6

7

7

8

8

12

12

12

12

3

CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <28>
CBS_CAD14 <32>
CBS_CAD13 <28>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>

CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>

CBS_CPAR <32>

CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>

CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>

R495 22_0402_5%~D

CBS_CINT# <32>

1 2

C187 0.01U_0402_16V7K~D

CBS_CAUDIO <32>

CBS_CVS1 <32>
CBS_CVS2 <32>

CBS_RSVD/D14 <32>
CBS_RSVD/D2 <32>
CBS_RSVD/A18 <32>

TPA0+
TPA0­TPB0+
TPB0-

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

12

CBS_CRST# <32>

C478

12

22P_0402_50V8J~D

C477

12

22P_0402_50V8J~D

CBS_CCLK <32>

0_0402_5%~D

R152

1 2

270P_0402_50V7K~D

@

C188

2

1

J1394

4
3
2
1

AMP_440168-2

R5C841XI

X4

24.576MHz_16P_1BG24576CKIA~D

1 2

R5C841XO

0.01U_0402_16V7K~D
10K_0603_1%~D

C185

2

R137

1

1 2

CBS_CCD2# <32>
CBS_CCD1# <32>

R166
0_0402_5%~D

1 2

270P_0402_50V7K~D

@

C208

2

1

2

+3V_PHY

R5C841XI

USBP3+<23>
USBP3-<23>

2

R5C841XO

IEEE1394_TPAP0
IEEE1394_TPAN0

IEEE1394_TPBP0
IEEE1394_TPBN0

IEEE1394_TPBIAS0

100K_0402_5%~D

12

R172

R167

SD_EN

R135

C162 0.01U_0402_16V7K~D

1 2

VPPEN0<32>
VPPEN1<32>

VCC5EN#<32>
VCC3EN#<32>

1

U25B

D11

CPS

A16
B16
A14

B12
A12

B13
A13

B10
A10

B11
A11

D12
D10

D13
B14

V14

W14

V13

W13

R13
T13

R7

100K_0402_5%~D

12

+3VSUS

10K_0402_5%~D

12

XI
XO
FIL0

TPAP0
TPAN0

TPBP0
TPBN0

TPAP1
TPAN1

TPBP1
TPBN1

TPBIAS0
TPBIAS1

VREF
REXT

USBDP
USBDM

VPPEN0
VPPEN1

VCC5EN#
VCC3EN#

REGEN#

3
4

2

R5C841

R5C841_CSP208~D

U6

VIN

VOUT

VIN/CE

VOUT

GND

RT9701CB_SOT25~D

1
5

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

SD_CLK

C135

0.01U_0402_16V7K~D

SD_DET# <32>

SD_WP <32>

SD_EN

SD_CMD <32>
SD_CLK <32>
SD_DATA0 <32>
SD_DATA1 <32>
SD_DATA2 <32>
SD_DATA3 <32>

100K_0402_5%~D

12

R146

+SD_VCC

1

1

C133

2

2

1U_0603_10V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
CardBus Controller(R5C841)

TOBAGO-LA2151

1

31 51Monday, October 18, 2004

0.6

of

5

+3VSUS

10U_0805_10V4M~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

C197

C195

C190

1

1

2

D D

C C

+3VRUN

C198

1

2

10U_0805_10V4M~D

C203

0.01U_0402_16V7K~D

1

2

0.01U_0402_16V7K~D

C211

1

2

+3VSUS

C193

+2.5V_CORE

C183

1

2

10U_0805_10V4M~D

2

1

0.01U_0402_16V7K~D

C521

0.01U_0402_16V7K~D

C202

1

2

2

+3VSUS

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

C184

0.01U_0402_16V7K~D

1

2

C205

C204

1

1

2

2

0.47U_0603_16V4Z~D

0.47U_0603_16V4Z~D

C192

C530

1

1

2

2

C522

C514

1

1

2

2

10U_0805_10V4M~D

C174

C173

1

1

2

2

0.01U_0402_16V7K~D

+3V_PHY

1

2

4

0.01U_0402_16V7K~D

1

2

0.01U_0402_16V7K~D

W10

J19
K19

R11
R12

E13

E14

E10
E11
A17
B17

D14

A15
B15

R10
T10
V10

L15

M19

F5

G5

W3

A4

R6

L1

A9
B9

D9

J1
J5
K5
E9

U25C

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3

VCC_MD3V

VCC_RIN1
VCC_RIN2

VCC_ROUT1
VCC_ROUT2

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

R5C841

R5C841_CSP208~D

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

3

L2
C1
D1
E1
C2
D2
E2
E4
E12

L44

+3VSUS

1 2

BLM21A601SPT_0805~D

2

FAN

Part Number Description

DC28A000800

Speak

Part Number Description

PK230007700

PCMCIA BODY

Part Number Description

+3V_PHY

1

1

C476

2

22U_1206_10V4Z~D

1

C489

C481

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C186

C180

2

2

1000P_0402_50V7K~D

1000P_0402_50V7K~D

Bluetooth wire set cable

Part Number Description

MDC wire set cable

Part Number Description

Media wire set cable

Part Number Description

T/P FFC cable

Part Number Description

RTC BATT

Part Number Description

1

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

SPK PACK DAQ20 2W 4OHM 18MM FG

PCMCIA FOXCONN

DC00F001700

1CA415M1-TA 68P

H-CON SET DAL30

DC025072300

MB-B/T-RTC

H-CON SET DAL30

DC025072400

MB-MDC

H-CON SET DAL30

DC025072500

MB-MEDIA-TP

FFC 6P F P1.0

NBX08001000

PAD=0.7 23mm

BATT CR2032 3V

GC20323MX00

220MAH MAXELL

JCBUS

1

CBS_CAD0
CBS_CAD1
CBS_CAD3

U23

11

B B

A A

+SD_VCC

C517

VPPEN0<31>
VPPEN1<31>

VCC3EN#<31>
VCC5EN#<31>

SD_CMD<31>

SD_DET#<31>

SD_WP<31>

0.1U_0402_16V4Z~D

+5VSUS

1

0.1U_0402_16V4Z~D

2

C508

1

2

SD_DATA1<31>
SD_DATA0<31>

SD_CLK<31>

SD_DATA3<31>
SD_DATA2<31>

R445 100_0402_5%~D

R439 100K_0402_5%~D

5

+SD_VCC

12

13
15

3
4

2
1

5

16

12

VCC3IN

VCC5IN
VCC5IN

EN0
EN1

VCC3_EN
VCC5_EN

FLG
GND

R5531V002-E2-FA_SSOP16~D

JSD

8

SDC1

7

SDC0

6

VSS2

5

CLK

4

VDD

3

VSS1

2

CMD

1

SDC3/CD

9

SDC2

10

CD#

CGND

11

COM

CGND

12

WP

MOLEX_48141-0001

VCCOUT
VCCOUT
VCCOUT

VPPOUT

9
14
12

CBS_VPP

8

C531

1

2

7

NC

6

NC

10

NC

13
14

CBS_VCC+3VSUS

0.01U_0402_16V7K~D

C527

1

1

C519

2

2

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D
C532

1

2

4

10U_0805_10V4M~D

CBS_CC/BE0#<31>

CBS_CC/BE1#<31>

CBS_CPAR<31>
CBS_CPERR#<31>
CBS_CGNT#<31>
CBS_CINT#<31>

CBS_VCC

CBS_VPP

CBS_CCLK<31>
CBS_CIRDY#<31>
CBS_CC/BE2#<31>

CBS_RSVD/D2<31>

CBS_CCLKRUN#<31>

CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9 CBS_CAD10
CBS_CAD11
CBS_CAD12 CBS_CAD13_L
CBS_CAD14 CBS_CAD15_L
CBS_CC/BE1#
CBS_CPAR

CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18 CBS_CAD19
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27 CBS_CAD28
CBS_CAD29 CBS_CAD30
CBS_RSVD/D2
CBS_CCLKRUN#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

GND

2

S1_D3

3

S1_D4

4

S1_D5

5

S1_D6

6

S1_D7

7

S1_CE1#

8

S1_A10

9

S1_OE#

10

S1_A11

11

S1_A9

12

S1_A8

13

S1_A13

14

S1_A14

15

S1_WE#

16

S1_RDY#

17

S1_VCC

18

S1_VPP

19

S1_A16

20

S1_A15

21

S1_A12

22

S1_A7

23

S1_A6

24

S1_A5

25

S1_A4

26

S1_A3

S1_INPACK#

27

S1_A2

28

S1_A1

29

S1_A0

30

S1_D0

31

S1_D1

32

S1_D2

33

S1_WP

34

GND

69

GND

71

GND

73

GND

75

GND

77

GND

79

GND

81

GND

83

GND

FOX_WZ21131-G2-P4_LT

GND

S1_CD1#

S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

S1_CE2#

S1_VS1

S1_IORD#

S1_IOWR#

S1_A17
S1_A18
S1_A19
S1_A20

S1_A21
S1_VCC
S1_VPP

S1_A22

S1_A23

S1_A24

S1_A25

S1_VS2
S1_RST

S1_WAIT#

S1_REG#

S1_BVD2
S1_BVD1

S1_D8
S1_D9

S1_D10

S1_CD2#

GND
GND
GND
GND
GND
GND
GND
GND
GND

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
72
74
76
78
80
82
84

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8

CBS_CVS1

CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#CBS_CPERR#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17

CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG

CBS_CAD31
CBS_CCD2#

CBS_CCD1# <31>

CBS_RSVD/D14 <31>

CBS_CVS1 <31>
CBS_CAD13_L <28>
CBS_CAD15_L <28>

CBS_RSVD/A18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>

CBS_VCC

CBS_VPP

CBS_CTRDY# <31>
CBS_CFRAME# <31>

CBS_CVS2 <31>
CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>

CBS_CCD2# <31>

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD14
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CBS_CAD31 <31>
CBS_CAD30 <31>
CBS_CAD29 <31>
CBS_CAD28 <31>
CBS_CAD27 <31>
CBS_CAD26 <31>
CBS_CAD25 <31>
CBS_CAD24 <31>
CBS_CAD23 <31>
CBS_CAD22 <31>
CBS_CAD21 <31>
CBS_CAD20 <31>
CBS_CAD19 <31>
CBS_CAD18 <31>
CBS_CAD17 <31>
CBS_CAD16 <31>
CBS_CAD14 <31>
CBS_CAD12 <31>
CBS_CAD11 <31>
CBS_CAD10 <31>
CBS_CAD9 <31>
CBS_CAD8 <31>
CBS_CAD7 <31>
CBS_CAD6 <31>
CBS_CAD5 <31>
CBS_CAD4 <31>
CBS_CAD3 <31>
CBS_CAD2 <31>
CBS_CAD1 <31>
CBS_CAD0 <31>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.
CardBus/SD card Socket

TOBAGO-LA2151

32 51Monday, October 18, 2004

1

0.6

of

5

PCI_AD[0..31]<21,30,31>

D D

C C

B B

Place closely pin 25

CLK_PCI_MINI

R144
10_0402_5%~D

@

1 2
2

C159

4.7P_0402_50V8C~D

1

@

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

COEX2_WLAN_ACTIVE<29>

HW_RADIO_DIS#<29,35>

PCI_C_BE3#<21,30,31>

PCI_C_BE2#<21,30,31>

PCI_C_BE1#<21,30,31>

DEBUG_ENABLE<34>

4

CLK_PCI_MINI<6>

PCI_IRDY#<21,30,31>

PCI_SERR#<21,30,31>
PCI_PERR#<21,30,31>

CLKRUN#<23,30,31,34>

+5VRUN

PCI_PIRQD#<21,31>

PCI_REQ3#<21>

R443
0_0402_5%~D

1 2

HW_RADIO_DIS#

PCI_PIRQD#

CLK_PCI_MINI
PCI_REQ3#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

DEBUG_ENABLE

+3VRUN

JPCI

1

TIP

3

8PMJ-3

5

8PMJ-6

7

8PMJ-7

9

8PMJ-8

11

LED1_GRNP

13

LED1_GRNN

15

CHSGND

17

INTB#

19

3.3V

21

RESERVED

23

GROUND

25

CLK

27

GROUND

29

REQ#

31

3.3V

33

AD31

35

AD29

37

GROUND

39

AD27

41

AD25

43

RESERVED

45

C/BE3#

47

AD23

49

GROUND

51

AD21

53

AD19

55

GROUND

57

AD17

59

C/BE2#

61

IRDY#

63

3.3V

65

CLKRUN#

67

SERR#

69

GROUND

71

PERR#

73

C/BE1#

75

AD14

77

GROUND

79

AD12

81

AD10

83

GROUND

85

AD8

87

AD7

89

3.3V

91

AD5

93

RESERVED

95

AD3

97

5V

99

AD1

101

GROUND

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND

115

SYS_AUDIO_OUT

117

SYS_AUDIO_OUT GND

119

AUDIO_GND

121

RESERVED

123

VCC5A

123

VCC5A

127

GND

AMP_1318644-1~D

3

+3VRUN

2

RING

4

8PMJ-1

6

8PMJ-2

8

8PMJ-4

10

8PMJ-5

12

LED2_YELP

14

LED2_YELN

16

RESERVED

18

5V

20

INTA#

22

RESERVED

24

3.3VAUX

26

RST#

28

3.3V

30

GNT#

32

GROUND

34

PME#

36

RESERVED

38

AD30

40

3.3V

42

AD28

44

AD26

46

AD24

48

IDSEL

50

GROUND

52

AD22

54

AD20

56

PAR

58

AD18

60

AD16

62

GROUND

64

FRAME#

66

TRDY#

68

STOP#

70

3.3V

72

DEVSEL#

74

GROUND

76

AD15

78

AD13

80

AD11

82

GROUND

84

AD9

86

C/BE0#

88

3.3V

90

AD6

92

AD4

94

AD2

96

AD0

98

RESERVED

100

RESERVED

102

GROUND

104

M66EN

AC_RESET#

RESERVED

GROUND

MCPIACT#

3.3VAUX
GND

106
108
110
112
114
116
118
120
122
124

128

AC_SDATA_OUT

AC_CODEC_ID0#

SYS_AUDIO_IN

SYS_AUDIO_IN GND

AUDIO_GND

2

LED_WLAN24
LED_WLAN5

LED_WLAN24
LED_WLAN5

PCI_PIRQB#

PCI_RST#
PCI_GNT3#
SYS_PME#

R458 0_0402_5%~D

1 2

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

DEBUG_OUT

MPCIACT#

2

C359

0.1U_0402_16V4Z~D

1

1 2

R489 100K_0402_5%~D

1 2

R478 100K_0402_5%~D

PCI_PIRQB# <21,31>

PCI_RST# <21,30,31>
PCI_GNT3# <21>

DEBUG_OUT <34>

10K_0402_5%~D

1 2

+3VSUS

+3VRUN

1

INB

2

INA

SYS_PME# <30,31,34>

1 2

100_0402_5%~D

PCI_PAR <21,30,31>

PCI_FRAME# <21,30,31>
PCI_TRDY# <21,30,31>
PCI_STOP# <21,30,31>

PCI_DEVSEL# <21,30,31>

PCI_C_BE0# <21,30,31>

R358

R462

@

10K_0402_5%~D

12

R440

COEX1_BT_ACTIVE <29>

PCI_AD19

+3VSUS

5

U7

P

4

1 2

O

G

200_0402_5%~D

TC7SH32FU_SSOP5~D

3

R145

2

C175

0.1U_0402_16V4Z~D

1

1

LED_WLAN_OUT

+3VSUS

LED_WLAN_OUT <39>

+5VRUN

2

C509

0.1U_0402_16V4Z~D

1

+3VRUN

2

C83

0.047U_0402_16V4Z~D

1

A A

2

C434

0.047U_0402_16V4Z~D

1

2

C136

0.047U_0402_16V4Z~D

1

2

C131

0.047U_0402_16V4Z~D

1

2

C143

0.047U_0402_16V4Z~D

1

2

C166

0.047U_0402_16V4Z~D

1

2

C440

0.047U_0402_16V4Z~D

1

2

C170

0.047U_0402_16V4Z~D

1

2

C77

0.047U_0402_16V4Z~D

1

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
MINIPCI

TOBAGO-LA2151

33 51Monday, October 18, 2004

1

0.6

of

R480

10K_0402_5%~D

KSO17<29>

1 2

@

1.5mm SMT~D

LCD_TST<19,23>

R456

1 2

10K_0402_5%~D

5

12

R481

10K_0402_5%~D

KSO17

R103

4.7K_0402_5%~D

J1397

+3.3VX

SATA_DET#

12

ATF_INT#
SYS_PME#

CB_HWSPND#<31>

D9

RB751V_SOD323~D

2 1

T3 PAD~D

@

1

1

2

2

3

3

T2
PAD~D

@

LCD_TST LCD_TST_SIO

+RTC_CELL

HP_NB_SENSE<27>

RUN_ON_D<37,41,43>

USB_BACK_EN#<28>

SIO_EXT_SMI#<23>
SIO_EXT_SCI#<23>
SIO_EXT_WAK#<23>
SIO_RCIN#<22>
NB_MUTE<27>
BEEP<26>

SIO_SLP_S3#<23>
SYS_PME#<30,31,33>
ATF_INT#<15>
SIO_SLP_S5#<23>

ICH_PCIE_WAKE#<18,23>

RUN_ON<19,37,38,42,44>
ICH_PME#<21>
SIO_THRM#<23>
SUS_ON<38,42>
SIO_PWRBTN#<23>

5V_CAL_SIO#<15>

R540 0_0402_5%~D

1 2

IDE_RST_MOD<25>
GC_BL_SUSPEND<18>
USB_SIDE_EN#<28>

MODC_EN#<37>
HDDC_EN#<37>

CLK_PCI_SIO<6>

CLK_SIO_14M<6>

R116

1 2

0_0402_5%~D

1 2

R114

0_0402_5%~D

@

+3VRUN

2

1

BLM11A121S_0603~D

1 2

254VCC0

C105

0.1U_0402_16V4Z~D

L46

+3VALW

D D

+3VALW

DEBUG_ENABLE<33>

DEBUG_OUT<33>

C C

B B

+3VALW

A A

CB_HWSPND#
HP_NB_SENSE
RUN_ON_D

KSO_17

USB_BACK_EN#

T5 PAD~D@
T6 PAD~D@

SIO_EXT_SMI#

SIO_EXT_SCI#

SIO_EXT_WAK#

SIO_RCIN#

NB_MUTE

BEEP

DEBUG_ENABLE

DEBUG_OUT

SIO_SLP_S3#

SYS_PME#

ATF_INT#

SIO_SLP_S5#

LID_CL_SIO#

ICH_PCIE_W AKE#

RUN_ON

ICH_PME#

SIO_THRM#

SUS_ON

SIO_PWRBTN#

SATA_DET#

5V_CAL_SIO#

IDE_RST_MOD

GC_BL_SUSPEND

USB_SIDE_EN#

MODC_EN#

HDDC_EN#

CLK_PCI_SIO

CLK_SIO_14M

2

1

4

+3VALW

+3VRUN

KPLLVCC

C488

0.1U_0402_16V4Z~D

1

C145

2

0.1U_0402_16V4Z~D

U20A

F13

SGPIO30

F14

SGPIO31

E16

SGPIO32

E15

SGPIO33

E12

SGPIO34

E13

SGPIO35

D16

SGPIO36

D15

SGPIO37

C16

SGPIO40

B16

SGPIO41

C15

SGPIO42

A16

SGPIO43

D14

SGPIO44

C14

SGPIO45

C13

SGPIO46

B14

SGPIO47

T5

LGPIO50

N6

LGPIO51

L6

LGPIO52

R6

LGPIO53

T6

LGPIO54

L7

LGPIO55

P7

LGPIO56

N7

LGPIO57

A15

LGPIO60/SPCLK

D13

LGPIO61/SPDOUT

A14

LGPIO62/SPDIN

C12

LGPIO63

B13

LGPIO64

A13

LGPIO65

D12

LGPIO66

F11

LGPIO67

B12

LGPIO70

A12

LGPIO71

C11

LGPIO72

D11

LGPIO73

E11

LGPIO74

A11

LGPIO75

F10

LGPIO76

C10

LGPIO77

L3

PCI_CLK

L4

CLOCKI

B2

GPIO83/32KHZ_OUT

E2

VCCO/BAT

M7

VCC1_1

B11

VCC1_2

R13

VCC1_3

H12

VCC1_4

E14

VCC1_5

B7

VCC1_6

A1

VCC1_7

L11

VCC1_8

G2

VCC2_1

P4

VCC2_2

J2

VCC2_3

M2

VCC2_4

R5

VCC2_5/PLL

P6

VSS13/PLL

LPC47N354_LBGA256~D

1

C110

2

0.1U_0402_16V4Z~D

3

SER_IRQ

CLKRUN#

LAD0
LAD1
LAD2
LAD3

LDRQ0#
LDRQ1#

LFRAME#

LRESET#

DLAD0
DLAD1
DLAD2
DLAD3

DLDRQ1#

DLFRAME#

DSER_IRQ

DCLKRUN#

RXD1

TXD1

DSR
RTS
CTS
DTR

DCD

IRRX

IRTX

GPIOB1/INIT

OUTD1/PE

OUTD3/ACK

GPIOB3/ALF

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

AGND

C150

J12
T4
P5

M3
R1
T1
P3

M6
R3

N4
L2

N2
P1
P2
N3

R2
T2
R4
T3

R451 10K_0402_5%~D

K1

TXD0

K5

R454 10K_0402_5%~D

K2
K4

R461 10K_0402_5%~D

K3
K6

R421 10K_0402_5%~D

B10

RI

R464 10K_0402_5%~D

L1

H15
K14
M4

J4
J5

J1
H2
H1
H3
H4
H5
H6
H8

F1
G5
G1
H7
J6

K7
J7

C2
G4
N5
R15
B15
G9
J3
N1
T10
J11
G14
B6

KAGND

F3

1

2

2

1

0.1U_0402_16V4Z~D

IRQ_SERIRQ
CLKRUN#

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LDRQ0#
LPC_LDRQ1#

LPC_LFRAME#
PLTRST_SIO#

1 2
1 2
1 2
1 2

1 2

R466

1 2

10K_0402_5%~D

1 2

BLM11A121S_0603~D

C479

10U_0805_10V4M~D

L43

EC_SCI/SPDIN

LPC47N354

MACALLEN III

CLOCK

256 - LBGA

1

2

0.1U_0402_16V4Z~D

LPC INTERFACE

COM1

GPIO10/WK_SE14/IRMODE/IRRX3B

IR

GPIOB2/SLCTIN

GPIOC0/PD0
GPIOC1/PD1
GPIOC2/PD2
GPIOC3/PD3
GPIOC4/PD4
GPIOC5/PD5
GPIOC6/PD6
GPIOC7/PD7

LPT

OUTD0/SLCT

OUTD2/BUSY

OUTD4/ERROR

GPIOB0/STROBE

GND

+3VRUN+3VALW

2

C127

1

0.1U_0402_16V4Z~D

8051
GPIO

LPC
GPIO

VCC

1

C121

C156

2

0.1U_0402_16V4Z~D

LPCPD#

@

PAD~D

IRQ_SERIRQ <23,31>

CLKRUN# <23,30,31,33>

LPC_LDRQ0# <22>
LPC_LDRQ1# <22>

LPC_LFRAME# <22>
PLTRST# <10,21,23,25>

PAD~D
PAD~D

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

PAD~D
PAD~D

2

T21

LPC_LAD[0..3] <22>

+3VRUN

+3VALW

T25
T24

T26
T19
T20
T18
T17
T16
T15
T9

T8
T11
T13
T14
T23

T27
T22

+5VSUS

5

1

U9

+3VALW

12

R482
100K_0402_5%~D

1

C482

0.047U_0402_16V4Z~D

2

4.7P_0402_50V8C~D

P

NC

4

A2Y

G

NC7SZ04P5X_SC70-5~D

3

@

R473

10_0402_5%~D

R133

10_0402_5%~D

C144

12

@

@

TXD0 DEBUG_TXD0

LID_CL_SIO#

Place closely pin L3 Place closely pin L4

CLK_PCI_SIO CLK_SIO_14M

12

R130

10_0402_5%~D

@

1

4.7P_0402_50V8C~D

C134

2

@

12

1

2

1

LID_CL#

T28

PAD

@

LID_CL# <29>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SIO (1/2)

TOBAGO-LA2151

34 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+3VALW

1 2

R412 100K_0402_5%~D

1 2

R411 100K_0402_5%~D

1 2

D D

R101 4.7K_0402_5%~D

1 2

R102 10K_0402_5%~D

SIO_IN0

SIO_IN1

SIO_IN5

SIO_IN6

VGA_IDENTIFY

LOW = Integrated

High = Discrete

C C

12

R420 10K_0402_5%~D

+5VRUN

1 2

R468 4.7K_0402_5%~D

1 2

R469 4.7K_0402_5%~D

1 2

B B

A A

R448 4.7K_0402_5%~D

1 2

R446 4.7K_0402_5%~D

R94

R405

1 2

10K_0402_5%~D

10K_0402_5%~D

@

BID0
BID1
BID2
BID3

@

1 2

R95

5

FPVCC

CLK_KBD

DAT_KBD

EMCLK

EMDAT

R404

1 2

10K_0402_5%~D

+3VRUN

1 2

10K_0402_5%~D

@

+5VALW

1 2

CLK_SM2<29>
DAT_SM2<29>

KSO[0..15]<36>

C456

1 2

C443

1 2

PBAT_PRES#<41>

THERMTRIP_SIO<15>

PS_ID_DISABLE#<40>

M_LED_C<29>
M_LED_B<29>
M_LED_A<29>

T4 PAD~D@
T7 PAD~D@

T10 PAD~D@
T12 PAD~D@

KSI[0..7]<29,36>

R410 4.7K_0402_5%~D

1 2

R122 4.7K_0402_5%~D

KSO16<36>
CAP_LED#<39>
NUM_LED#<39>
SRL_LED#<39>

PS_ID<40>

+3VALW

12

R470
10K_0402_5%~D

2@

12

R521
10K_0402_5%~D

1@

PBAT_ALARM#<41>

22P_0402_50V8J~D

22P_0402_50V8J~D

+3VRUN

R419 10K_0402_5%~D

1 2

R107 10K_0402_5%~D

1 2

R108 10K_0402_5%~D@

1 2

R418 10K_0402_5%~D

1 2

SIO_IN2

PBAT_ALARM#

SIO_IN0
SIO_IN1
SIO_IN2
FPVCC
SIO_IN5
SIO_IN6
PBAT_PRES#

THERMTRIP_SIO
H_PROCHOT_SIO#

KSO16
CAP_LED#
NUM_LED#
SRL_LED#

PS_ID
BID0

BID1
BID2
BID3
PS_ID_DISABLE#

VGA_IDENTIFY

M_LED_C
M_LED_B
M_LED_A

SIO_MSCLK
SIO_MSDAT

EMCLK
EMDAT

CLK_SM2
DAT_SM2

CLK_KBD
DAT_KBD
PBAT_ALARM#

CLK_32KX2

12

X3

32.768KHZ_12.5P_MC-306~D

3.8X12.1mm

CLK_32KX1

BID3

0
0
00 0X02

U20B

A9

IN0 (WK_EE4)

B9

IN1 (WK_EE2)

B8

IN2 (WK_EE3)

A8

IN3 (GPWKUP)

C8

IN5 (WK_SE01)

D8

IN6 (WK_SE05)

E8

IN7 (WK_EE1)

H13

GPIO0 (WK_SE02)

H11

GPIO1 (WK_SE03)

H10

GPIO2 (WK_SE04)

G10

GPIO3 (TRIGGER)

G13

GPIO7 (WK_SE06)

J14

GPIO8 (WK_SE12)/IRRX2

J16

GPIO9 (WK_SE13)/IRTX2

G11

GPIO17 (WK_SE23)/A20M

F15

GPIO20 (WK_SE25)/PS2CLK/8051RX

F12

GPIO21 (WK_SE26)/PS2DAT/8051TX

B5

GPIO84

E5

GPIO85

D5

GPIO86

A4

GPIO87

B4

GPIO90

C5

GPIO91

A3

GPIO92

A2

GPIO93

C3

GPIO96

D3

GPIO97

B1

GPIOA0

D4

GPIOA1

C1

GPIOA2

D10

MSCLK/SPCLK

E10

MSDATA/SPDOUT

G6

EMCLK

G3

EMDAT

B3

GPIO94/IMCLK

C4

GPIO95/IMDAT

M1

KCLK

M5

KDAT

G15

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6 SIO_FA11
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

GPIO6 (WK_SE11)/IRMODE/IRRX3A

G12

GPIO5 (WK_SE10)/KSO15

G16

GPIO4 (WK_SE07)/KSO14

R7

KSO13/GPIO18(WK_SE27)

T7

KSO12/OUT8/KBRST

K8

KSO11

J8

KSO10

L8

KSO9

M8

KSO8

N8

KSO7

P8

KSO6

T8

KSO5

R8

KSO4

R9

KSO3

T9

KSO2

P9

KSO1

N9

KSO0

M9

KSI7

L9

KSI6

K9

KSI5

K10

KSI4

M10

KSI3

R10

KSI2

N10

KSI1

P10

KSI0

E1

XTAL1

D1

XTAL2

LPC47N354_LBGA256~D

BID2 BID1

00
0

0

LPC47N354

MACALLEN III

GPIO

K/B

256 - LBGA

REV

BID0

X00

0
1

X01

MISC

GPIO11 (WK_SE15)/AB2A_DATA

GPIO12 (WK_SE16)/AB2A_CLK

GPIO13 (WK_SE17)/AB2B_DATA

GPIO14 (WK_SE20)/AB2B_CLK
GPIO15 (WK_SE21)/FAN_TACH1
GPIO16 (WK_SE22)/FAN_TACH2

FLASH

FPGM

TEST_PIN

XOSEL
SYSOPT0/GPIO80
SYSOPT1/GPIO81

BAT_LED

PWR_LED

GPIOA3/WINDMON

TESTA

VCC1RST#

RESET_OUT

PWRGD

ACAV_IN

POWER_SW_IN#

ALWON

OUT0

OUT1/IRQ8

OUT2/FRD

OUT3/FWR

OUT4

OUT5/KBRST

OUT6

OUT7/SMI

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

AB1A_CLK

AB1B_DATA

AB1B_CLK

AB1A_DATA

GPIO82/FAN_TACH3

GPIO19 (WK_SE24)

FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22

FRD

FWR

FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9

FCS
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0

SIO_KAH_PGM

L10
K12

XOSEL

E4

SYSOPT0

K15

SYSOPT1

K16

BAT1_LED#

J9

BAT2_LED#

J10

BIA_PWM

E3
F2

VCC1RST#

D2

RESET_OUT#

L5

RUNPWROK

K13

ACAV_IN

F4
F5

ALWON

F6

EEPROM_WC

D7
C7

HW_RADIO_DIS#

F7

LAN_LOW_PWR

A6

CHG_PBATT

E6
D6

AUDIO_AVDD_ON

C6
E7
A7
G7

BREATH_LED

G8

FAN1_PWM

F8

CLK_SMB

C9

AB1B_DATA

F9

AB1B_CLK

E9

DAT_SMB

D9

SBAT_SMBDAT

H16

SBAT_SMBCLK

H14

PBAT_SMBDAT

J15

PBAT_SMBCLK

J13

FAN1_TACH

A10
H9
A5

SIO_A20GATE

F16

SIO_FA0

N12

SIO_FA1

T13

SIO_FA2

P12

SIO_FA3

T14

SIO_FA4

T15

SIO_FA5

R16

SIO_FA6

N13

SIO_FA7

P16

SIO_FA8

M14

SIO_FA9

N15

SIO_FA10

N16
M13

SIO_FA12

L12

SIO_FA13

M15

SIO_FA14

M16

SIO_FA15

L14

SIO_FA16

L13

SIO_FA17

L15

SIO_FA18

L16

SIO_FA19

K11
R14
T16
P13

FRD#

P14

FWR#

N14

FCS#

P15

SIO_FD7

M12

SIO_FD6

R12

SIO_FD5

T12

SIO_FD4

P11

SIO_FD3

N11

SIO_FD2

M11

SIO_FD1

R11

SIO_FD0

T11

1

X030101
X040100

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+3VALW

12

R483
1K_0402_5%~D

@

R117 10K_0402_5%~D
R455 10K_0402_5%~D
R452 10K_0402_5%~D

BAT1_LED# <39>
BAT2_LED# <39>
BIA_PWM <12,18>

VCC1RST# <36>
RESET_OUT# <38>
RUNPWROK <18,38,43,45>

ACAV_IN <40,46>
ALWON <42>
EEPROM_WC <36>
HW_RADIO_DIS# <29,33>

LAN_LOW_PWR <30>
CHG_PBATT <46>

AUDIO_AVDD_ON <26>

BREATH_LED <39>
FAN1_PWM <15>

CLK_SMB <15,36>

DAT_SMB <15,36>
SBAT_SMBDAT <18>
SBAT_SMBCLK <18>
PBAT_SMBDAT <19,41,46>
PBAT_SMBCLK <19,41,46>

FAN1_TACH <15>

SIO_A20GATE <22>

SIO_FA[0..19] <36>

FRD# <36>
FWR# <36>
FCS# <36>

SIO_FD[0..7] <36>

R474

10K_0402_5%~D

12

12
1 2
1 2

1 2

R125 100_0402_5%~D

2

+3VALW

R106

DAT_SMB

CLK_SMB

AB1B_DATA

AB1B_CLK

POWER_SW#POWER_SW_IN#

POWER_SW# <15,39>

+3VALW

12

Level shifter

R104

330_0603_5%~D

C

Q11

2

B

E

MMBT3904_SOT23~D

3 1

POWER_SW_IN#

1

C130

2

1U_0603_10V4Z~D

SBAT_SMBDAT

SBAT_SMBCLK

PBAT_SMBDAT

PBAT_SMBCLK

LAN_LOW_PWR
CHG_PBATT

H_PROCHOT_SIO#

PROCHOT_SFTON

R110

1 2

56_0402_5%~D

10K_0402_5%~D

1 2

R105

10K_0402_5%~D

1 2

R99

10K_0402_5%~D

R100

10K_0402_5%~D

R119

100K_0402_5%~D

12
12

R128

@

100K_0402_5%~D

R444

8.2K_0402_5%~D

1 2

R131

8.2K_0402_5%~D

1 2

R449

8.2K_0402_5%~D

1 2

R447

8.2K_0402_5%~D

1 2

12

R409 10K_0402_5%~D

1 2

R123 10K_0402_5%~D

R93
56_0402_5%~D

1 2

+VCCP

H_PROCHOT# <7>

12

12

+RTC_CELL

+3.3VX

+5VALW

+3VALW

+VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
SIO (2/2)

TOBAGO-LA2151

35 51Monday, October 18, 2004

1

0.6

of

5

D D

4

3

2

1

KSO[0..15]<35>

KSI[0..7]<29,35>

C C

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7

B B

A A

KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16

KSO16<35> SIO_FD[0..7] <35>

KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

JKYBRD

25
24
23
22
21
20
19
18
17
16
15

30
29

14
13

28
27

12
11

26
10
9
8

31
7

32
6
5

33
4

34
3
2
1

JAE_FK2S030W11~D

1

1

1

1

1

1

1

1

1

2

2

2

2

C574 100P_0402_50V8J~D

C573 100P_0402_50V8J~D

C575 100P_0402_50V8J~D

C572 100P_0402_50V8J~D

2

C576 100P_0402_50V8J~D

1

2

2

2

C577 100P_0402_50V8J~D

C578 100P_0402_50V8J~D

C579 100P_0402_50V8J~D

1

2

C580 100P_0402_50V8J~D

1

2

2

2

C581 100P_0402_50V8J~D

C582 100P_0402_50V8J~D

C583 100P_0402_50V8J~D

1

2

C584 100P_0402_50V8J~D

1

1

1

1

2

2

2

2

C587 100P_0402_50V8J~D

C588 100P_0402_50V8J~D

C585 100P_0402_50V8J~D

C586 100P_0402_50V8J~D

1

2

C589 100P_0402_50V8J~D

1

1

1

2

C590 100P_0402_50V8J~D

1

2

C591 100P_0402_50V8J~D

1

1

1

2

2

2

2

2

C592 100P_0402_50V8J~D

C593 100P_0402_50V8J~D

C594 100P_0402_50V8J~D

C207 100P_0402_50V8J~D

C595 100P_0402_50V8J~D

+3VALW +3VALW

12

R396
0_0402_5%~D

U2

1

NC

2

A1

3

A2

4

VSS

AT24C04N-10SI-2.7_SO8~D

SUB_6782U

SMbus address A2

SIO_FA[0..19]<35>

FCS#<35>
FRD#<35>
FWR#<35>

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

FCS#
FRD#
FWR#

VCC

SDA

1

C395

0.1U_0402_16V4Z~D

2

8
7

WP

6

SCL

5

EEPROM_WC
CLK_SMB
DAT_SMB

U8

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

MX29LV008BTC-70R_TSOP40~D

EEPROM_WC <35>
CLK_SMB <15,35>
DAT_SMB <15,35>

VCC
VCC

NC

RESET#

RY/BY#

NC
NC

GND
GND

+3VALW

31
30
11

SIO_FD0

25

D0
D1
D2
D3
D4
D5
D6
D7

26
27
28
32
33
34
35

10
12
29
38

23
39

SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7

FWH_RST

R151

0_0402_5%~D

C182

VCC1RST#

12

1

1

C178

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

VCC1RST# <35>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
INT KB

TOBAGO-LA2151

36 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

Run Planes Enable

+5VALW

12

R201
100K_0402_5%~D

D D

RUN_ON__D_5V#

RUN_ON_D<34,41,43>

2N7002_SOT23~D

C C

RUN_ON_5V#

RUN_ON<19,34,38,42,44>

2N7002_SOT23~D

B B

1@

2

G

2

G

2N7002_SOT23~D

13

D

S

12

R202
100K_0402_5%~D

2N7002_SOT23~D

13

D

S

1@

Q18

Q17

+15V

12

R184
100K_0402_5%~D

1@

RUN_D_ENABLE

1@

13

D

2

G

S

Q16

+15V+5VALW

12

R223
100K_0402_5%~D

RUN_ENABLE

13

D

2

G

S

Q22

C257

C284

R219
0_0402_5%~D

1 2

1@

1

1@

2

4700P_0402_25V7K~D

1

2

4700P_0402_25V7K~D

R216

+3VSUS +VCC_CORE

12

2@

0_0402_5%~D

R536

100K_0402_5%~D

1

C571

2

0.022U_0603_50V4Z~D

12

8
7

5

+5VSUS

+1.8VSUS

+1.5VSUS

SI4810DY_SO8~D

Q23

1
2
36

4

Q24

SI3456DV-T1_TSOP6~D

D

6

S

45
2
1

G

3

Q14

SI4810DY_SO8~D

8
7

5

Q44

SI4810DY_SO8~D

8
7

5

4

4

C285

4.7U_0805_10V4Z~D

C283

4.7U_0805_10V4Z~D

1
2
36

C172

1
2
36

C493

+3VRUN

12

1

2

+5VRUN

12

1

2

+1.8VRUN

1

2

4.7U_0805_10V4Z~D

+1.5VRUN

1

2

4.7U_0805_10V4Z~D

+3VRUN Source

R222
10K_0402_5%~D

+5VRUN Source

R215
10K_0402_5%~D

+1.8VRUN Source

12

R148
10K_0402_5%~D

+1.5VRUN Source

12

R479
10K_0402_5%~D

RUN_ON_5V#

12
1

R493
47_0805_5%~D

@

Z4005

2

Q46

13

D

2N7002_SOT23~D

@

2

G

S

+5HDD Source

DTC144EKA_SOT23~D

HDDC_EN#<34>

+5VMOD Source

DTC144EKA_SOT23~D

MODC_EN#<34>

+0.9V_DDR_VTT +3VRUN +VCCP

2

G

@

Q19

12

1

R185
22_0805_5%~D

@

Z4006

2

Q20

13

D

2N7002_SOT23~D

S

Q51

47K

2

47K

2

@

47K

47K

12
11

R503
22_0805_5%~D

@

2

Q49

13

D

2N7002_SOT23~D

2

G

S

+15V

12

R507
100K_0402_5%~D

@

HDD_EN

13

+15V

12

R200
100K_0402_5%~D

2

13

C547

@

MOD_EN

C273

3

1

2

0.01U_0402_16V7K~D

3

1

2

0.01U_0402_16V7K~D

@

+5VSUS

1

G

C546

4.7U_0805_10V4Z~D

+5VSUS

1

G

C276

4.7U_0805_10V4Z~D

+1.5VRUN

2

G

6

2

D

Q50

S

SI3456DV-T1_TSOP6~D

4 5

1

2

6

2

D

Q21

S

SI3456DV-T1_TSOP6~D

4 5
1

2

12
1

R134
22_0805_5%~D

@

2

Q13

13

D

2N7002_SOT23~D

@

S

@

+5VHDD

12

R504

100K_0402_5%~D

+5VMOD

12

R198
100K_0402_5%~D

2

G

R506

0_0805_5%~D

1 2

R199

0_0805_5%~D

1 2

@

12

R492
22_0805_5%~D

@

2

Q45

13

D

2N7002_SOT23~D

@

S

+5VRUN

+5VRUN

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
POWER CONTROL

TOBAGO-LA2151

37 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

+3VRUN

+3VSUS

14

4

P

IN1

6

OUT

5

IN2

G

U21B
74VHC08MTC_TSSOP14~D

7

D D

+3VSUS

U26B
74VHC08MTC_TSSOP14~D

14

IMVP_PWRGD<10,23,45>

ITP_DBRESET#<7>

C C

IMVP_PWRGD

RESET_OUT#<35>

4

P

IN1

6

OUT

5

IN2

G

7

1
2

+3VSUS

IN1
IN2

14

P
OUT

G

7

U21A

3

74VHC08MTC_TSSOP14~D

R463
0_0402_5%~D

1 2

ICH_PWRGD <23>

100K_0402_5%~D

ICH_PWRGD

R453

2

G

+3VSUS

12

13

ICH_PWRGD#

D

Q41
2N7002_SOT23~D

S

12

R494
100K_0402_5%~D

5VRUNRC

1

C520

0.01U_0402_16V7K~D

2

ICH_PWRGD# <15>

+3VSUS

C483

0.1U_0402_16V4Z~D

1 2

8

U24A

P

7

A1Y

G

SN74LVC3G14DCTR_SSOP8~D

4

+3VSUS

8

A6Y

4

RUN_ON<19,34,37,42,44>

SUS_ON<34,42>

U24B

P

2

G

SN74LVC3G14DCTR_SSOP8~D

1.5VSUS_PWRGD

+COINCELL

+3VSUS

1

IN1

2

IN2

+3VSUS

10

IN1

9

IN2

+COINCELL

C480

0.1U_0402_16V4Z~D

1 2

U26A

14

74VHC08MTC_TSSOP14~D

P

3

OUT

G

7

14

P

8

OUT

G

U26C

74VHC08MTC_TSSOP14~D

7

JCOIN

1
2

ACES_85204-0200

@

+3VSUS

14

13

IN1

12

IN2

7

P

G

RUNPWROK

11

OUT

U26D
74VHC08MTC_TSSOP14~D

+3VSUS

8

U24C

P

5

A3Y

G

SN74LVC3G14DCTR_SSOP8~D

4

RUNPWROK <18,35,43,45>

SUSPWROK <15,23>

+1.5VSUS +3VALW +3VALW

12

330_0603_5%~D

R224

2

G

13

D

Q25
2N7002_SOT23~D

S

1.5VSUS_PWRGD

12

R227

10K_0402_5%~D

C287

12

C

Q28

2

B

MMBT3904_SOT23~D

1

2

E

3 1

B B

R230

10K_0402_5%~D

0.1U_0402_16V4Z~D

+COINCELL

12

+3.3VX

Z4012

2

3

1

D15

BAT54C_SOT23~D

R471
1K_0402_5%~D

+RTC_CELL

1

C528
1U_0603_10V4Z~D

2

RTC BATT CONN

JRTC

2

-

SUYIN_060003FA002TX00NL~D

+

+COINCELL

1

1

C238

2

0.1U_0402_16V4Z~D

RJ11 Connector

JWIRE

1

A A

5

2

ACES_85204-0200

RJ_TIP
RJ_RING

4

JPHON

1

1

2

2

3

GND1

4

GND2

SUYIN_100002FR006G202ZL~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Power Good

TOBAGO-LA2151

38 51Monday, October 18, 2004

1

of

0.6

5

4

3

2

1

H2

H1
@H_C315D98

1

D D

H11
@H_C315D118

1

H21

@H_C335O118X142

1

@H_C315D98

1

H12
2@H_C619D63

1

H22

@H_C315D118

H3

@H_C433D118

H13

@H_C433D118

1

1

1

H23

H_C291S252D165

1

H4

@H_C433D118

1

H14

2@H_C252S315D165

1

H24

H_C291C252D165

H5
@H_C315D98

1

H15
H_C315D165

1

1

H6
@H_C315D98

1

H16
@H_C433D118

1

H17

@H_C433D118

1

H8

@H_C354D98

1

H18

@H_C433D110

1

H9

@H_C354D110

1

H19

H_C260D165

1

H10

2@H_C291C315D165

1

H20

H_C102BC236D87

1

FD8

1

@FIDUCIAL MARK~D

FD17

1

FIDUCIAL MARK~D

FD10

1

@FIDUCIAL MARK~D

For VGA Board

PAD1

@PAD-2.5X3

C C

B B

PAD2

1

@PAD-2.5X3

CAP_LED#<35>

NUM_LED#<35>

SRL_LED#<35>

PAD3

1

@PAD-2.5X3

+3VRUN

47K

2

10K

1 3

1

47K

2

10K

1 3

Q6
DTA114YKA_SC59~D

PAD4

@PAD-2.5X3

2

ON/OFF Button

JPSW

2

112

POWER_SW#<15,35>

A A

CAP_LED

R_MPCI_ACT

SUYIN_127183MA010G211ZR

334
556
778
9910

4
6
8
10

1

47K

10K

1 3

R_CAP

Q30
DTA114YKA_SC59~D

R_NUM

R_SRL

R8

3.3K_0603_5%~D

SRL_LED

NUM_LEDR_BT_ACT

PAD5

1

@PAD-2.5X3

Q26
DTA114YKA_SC59~D

330_0603_5%~D

330_0603_5%~D

+5VALW

12

PAD6

@PAD-2.5X3

BT_ACTIVE<29>

R231

CAP_LED

12

R237

330_0603_5%~D

NUM_LED

12

R21

SRL_LED

12

LED_WLAN_OUT<33>

PAD7

1

@PAD-2.5X3

BLUE TOOTH LED POWER SOURCE

R4

10K_0402_5%~D

1 2

10K_0402_5%~D

1

R6

1 2

R_BT_ACT

2

B

E

2

B

C

Q4
MMBT3904_SOT23~D

3 1

+3VALW

C

Q5
MMBT3904_SOT23~D

E

3 1

R15
330_0603_5%~D

1 2

R_MPCI_ACT

Fiducial Mark

FD7

1

@FIDUCIAL MARK~D

FD13

1

FIDUCIAL MARK~D

FD1

1

@FIDUCIAL MARK~D

FD14

1

@FIDUCIAL MARK~D

FD12

1

FIDUCIAL MARK~D

FD18

1

@FIDUCIAL MARK~D

BREATH_LED<35>

FD16

1

@FIDUCIAL MARK~D

FD4

1

FIDUCIAL MARK~D

FD9

1

@FIDUCIAL MARK~D

SATA_ACT#<22>

BAT1_LED#<35>

BAT2_LED#<35>

SATA_ACT#

R3

10K_0402_5%~D

1 2

BAT1_LED#

BAT2_LED#

FD5

1

@FIDUCIAL MARK~D

FD6

1

FIDUCIAL MARK~D

FD11

1

@FIDUCIAL MARK~D

2

BREATH_LED_B

2

2

FD3

1

@FIDUCIAL MARK~D

FD15

1

FIDUCIAL MARK~D

FD2

1

@FIDUCIAL MARK~D

+3VRUN

47K

10K

1 3

2

B

+5VALW

47K

10K

1 3

+5VALW

47K

10K

1 3

DTA114YKA_SC59~D
Q1

1 2

56_0603_5%~D

+3VSUS

12

R1
56_0603_5%~D

21

D1
HT-190YG-DT_0603~D

C

Q3
MMBT3904_SOT23~D

E

3 1

DTA114YKA_SC59~D
Q2

R5

1 2

DTA114YKA_SC59~D
Q35

R265

1 2

R2

220_0603_5%~D

330_0603_5%~D

PCB

D2

HT-190YG-DT_0603~D

2 1

GREEN_LED

AMBER_LED

DAL30

LA-2151 REV 0

M/B

D3

2 1

4 3

LTST-C155KGKFKT_GRN/ORG~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Do c u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
PAD and Standoff

TOBAGO-LA2151

1

39 51Wednesday, November 03, 2004

0.6

of

5

4

3

2

1

D D

PS_ID_IN

C C

B B

PS_ID_IN

+3VALW

PR183

1 2

@ 4.7K_0402_5%~D

PR6

1 2

100K_0402_1%~D

PR10

1 2

15K_0402_1%~D

Z-series AC Adaptor
Connctor

PQ1

BSS138_SOT23~D

D

1 3

G

2

C

2

B

E

3 1

PJPDC1
HRS_HR33-DL-7~D

9

GND_4

8

GND_3

7

GND_2

6

GND_1

MH1

MH2

S

PQ2
MMBT3904_SOT23~D

Low_PWR

0_0402_5%~D

1 2

DC+_1
DC+_2

DC-_1
DC-_2

PR184

1
2
3
4
5

+5VALW

3

PD2

1

@DA204U_SOT323~D

PWR_ID

DCIN+

+3VALW

2

PR2

1 2

2.2K_0402_5%~D

+5VALW

PR7

1 2

100K_0402_1%~D

FBM-L11-160808-601LMT 0603~D

PR185

0_0402_5%~D

1 2

PR186

@0_0402_5%~D

1 2

DOCK_DC_IN

PL1

PS_ID_IN

12

PL2

FBM-L11-453215-900LMAT_1812~D

1 2

PL3
@ OC8070-A301~D

2
1 4

3

PS_ID_IN

DOCK DC_IN

PC2

0.47U_1812_50V7M~D

PS_I D <35>

PS_ID_DISABLE# <35>

ACAV_IN <35,46>

DC_IN+ Source

1
2
3 6

12

1 2

PR11

150K_0402_1%~D

PQ_G

PQ3

FDS6679Z_SO8~D

4

12

PR13

100K_0402_1%~D

PWR_SRC

12

PC7

0.1U_0603_25V7K~D

8
7

5

12

12

PC4

PC3

0.01U_0402_25V7K~D

12

PC5

0.1U_0805_50V7M~D

0.1U_0805_50V7M~D

PR12

1 2

10K_0402_1%~D

12

4.7K_0603_5%~D

+3.3VX Source

RTC_SHDN#

PR5

MAX1615EUK_SOT23-5~D

+DC_IN

12

PC6

10U_1210_25V7K~D

+3.3VX

PU1

1

IN

3

OUT

5

#SHDN

4

5/3+

GND

2

12

PC1

1U_0603_10V6K~D

THESE CAPS MUST BE
NEXT TO JCHG

A A

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Do c u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
+DCIN

TOBAGO-LA2151

1

40 51Monday, October 18, 2004

0.6

of

5

D D

+3VALW

C C

Primary Battery Connector

PJP2

12

PC10

2200P_0402_50V7K~D

BATT_PRES#

10

GND

11

GND

SUYIN_200275MR009G516ZL~D

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT_VOLT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD9

@ DA204U_SOT323~D

PR20

100_0402_5%~D

1 2

2

3

1

@ DA204U_SOT323~D

PR21

100_0402_5%~D

1 2

4

PD10

ESD Diodes

2

3

1

PR22

100_0402_5%~D

1 2

2

3

PD11

1

@ DA204U_SOT323~D

PR23

100_0402_5%~D

1 2

2

3

PD12

1

@ DA204U_SOT323~D

3

PBAT_SMBCLK <19,35,46>
PBAT_SMBDAT <19,35,46>

PBAT_ALARM# <35>

PL6

FBM-L11-453215-900LMAT_1812~D

PBATT+

1 2

PC9

0.1U_0805_50V7M~D

1 2

2

+3VALW

SUYIN_20175A-09G1
TOP view

+VCHGR

PR19

10K_0402_1%~D

12

PBAT_PRES# <35>

1

9

8

7

6

5

4

3

2

1

B B

+2.5VRUN

PU2

+3VSUS +2.5VRUNP

12

+5VSUS

12

PR25

2P5V_PWRGD

A A

PJP3

1 2

PAD-OPEN 4x4m

+2.5VRUN+2.5VRUNP

5

RUN_ON_D<34,37,43>

@10K_0402_1%~D

4

PC11

0.1U_0603_25V7K~D

PR1

8.2K_0402_5%~D

12

PC12

1U_0603_10V6K~D

12

12

PC8

0.1U_0603_25V7K~D

1

IN

OUT

2

IN

OUT

3

POK

SET

SHDN#4GND1

GND2

MAX1806EUA25_8UMAX~D

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1=R2* (Vo/ 0.8 -1), R2:25K~100K.

8
7
6
5

9

3

12

PR24

66.5K_0402_1%~D

PC13

10U_1206_6.3V7K~D

12

PR26

30.9K_0402_1%~D

12

12

PC14

0.1U_0603_25V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

2

Compal Electronics, Inc.
Battery Conn./+2.5V

TOBAGO-LA2151

41 51Monday, October 18, 2004

1

0.6

of

5

4

3

2

1

DC/DC +3V/ +5V/ +15V

PL22

FBM-L11-453215-900LMAT_1812~D

PWR_SRC

D D

Design current 3.4A for +3.3VSUSP Design current 4A for +5VSUS
Peak current 4.758A for +3VSUSP Peak current 5.7A for +5VSUSP
OCP point is from 5A to 8A OCP point is from 6A to 9A

+3VSUSP

1

+

PC32

PC31

2

C C

B B

330U_D3L_6.3V_R25~D

1 2

1

1

PC17

PC16

Place these CAPs
close to FETs

4.7U_SPC-1205P-4R7B_+40-20%~D

12

0.1U_0603_25V7K~D

12

PR34

@ 0_0603_5%~D

12

PR36

0_0603_5%~D

PL9

1 2

SUS_ON<34,38>

2

10U_1206_25V6M~D

12

PC25

PC26

2200P_0402_50V7K~D

PQ5

FDS6994S_SO8~D

4

G1

3

S1

2

G2

1

S2

SUS_ON<34,38>

2

10U_1206_25V6M~D

12

0.1U_0805_50V7M~D

5

D1

6

D1

7

D2

8

D2

ALWON<35>

THERM_STP#<15>

12

PC20

4.7U_1206_25V6K~D

0.1U_0603_25V7K~D

2K_0402_1%~D

PR47

1 2

240K_0402_5%~D

PR27

1 2

10_1206_5%~D

12

PC21

0.1U_0805_50V7M~D

PC28

PR33

0_0603_5%~D

PR41

1 2

1K_0402_1%~D

1 2

12

PR49

PR211

PC36

1 2

10_1206_5%~D

12

12

@ 1000P_0402_50V7K~D

PR32
0_0603_5%~D

1 2

VCC_MAX1999

47_0603_5%~D

12

PC24

1U_0603_10V6K~D

12

PC34

4.7U_1206_10V7K~D

20
17

6
28
26
27
24
22

7

3

4
25

PR28

PU3

V+
VCC
SHDN
BST3
DH3
LX3
DL3
OUT3
FB3
ON3

ON5
LDO3

+3VALW

12

1

PD14

2

3

RB717F_SOT323~D

SKIP

MAX1999EEI_QSOP28~D

12

MAX1999_SKIP#

0_0402_5%~D

@ 0_0402_5%~D

12

PR51

@ 0_0402_5%~D

PGOOD

PR48

PR50

LDO5

BST5

OUT5

ILIM5
ILIM3

+5VALW

12

12

PC22

4.7U_1206_25V6K~D

PR29

18

0_0603_5%~D

14
16

DH5

15

LX5

19

DL5

21
1

N.C.

9

FB5

10

PRO

11
5
8

REF

13

TON

23

GND

2

12

12

PC27

0.1U_0603_25V7K~D

1 2

1 2

1 2

PR30

0_0603_5%~D

+3VSUSP

PR42

1 2

100K_0402_1%~D

SUSPWROK_5V <44>

VCC_MAX1999

RUN_ON <19,34,37, 38,44>

PC23

1U_0603_10V6K~D

PC33

12

1U_0603_10V6K~D

Place these CAPs
close to FETs

12

PC18

PC19

0.1U_0805_50V7M~D

578

PQ4

3 6

241

578

PQ6
SI4810DY_SO8~D

3 6

241

PR37

1 2

49.9K_0402_1%~D

1 2

PR188

150K_0402_1%~D

PR203

100_0805_5%~D

1 2

PD13

12

PC15

2 1

15VS

1 4

2.2U_1206_25V7K~D

PL8

4.7uH +-30 % S T QB1252- 4722A_7A~D

3 2

VCC_MAX1999

PR39

1 2

PR40

0_0402_5%~D

1 2

@ 0_0402_5%~D

PR45

PR46

1 2

1 2

0_0402_5%~D

@0_0402_5%~D

EC11FS2_SOD106~D

1 2

1 2

12

2200P_0402_50V7K~D

SI4800DY-T1_SO8~D

PR38

68K_0402_1%~D

PR44

60.4K_0402_1%~D

+15VP

1

2

12

PR31

@ 0_0603_5%~D

12

PR35

0_0603_5%~D

12

PD35

PC156

PC30

2.2U_1206_25V7K~D

MMBZ5245B_SOT23~D

+5VSUSP

1

12

+

PC29

2

0.1U_0603_25V7K~D

330U_D3L_6.3V_R25~D

3

+15VP

+5VSUSP

+3VSUSP

A A

PJP4

1 2

PAD-OPE N 4x4m

PJP5

1 2

PAD-OPE N 4x4m
PJP6

1 2

PAD-OPE N 4x4m

(150mA,Via NO.= 2)

+15V

(6A,240mils ,Via NO.= 12)

+5VSUS

(4A,160mils ,Via NO.= 8)

+3VSUS

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Do c u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.
+3.3V/+5V/+15V

TOBAGO-LA2151

1

42 51Monday, October 18, 2004

0.6

of

A

B

C

D

+1.5VSUSP / +VCCP_1P05VP

PL23

1 1

FBM-L11-453215-900LMAT_1812~D

1 2

PWR_SRC

1

PC37

PC38

2

10U_1206_25V6M~D

Design current 3A for +1.5VSUSP
Peak current 4.034A for +1.5VSUSP
OCP point is from 4.5A to 7A

2 2

+1.5VSUSP

1

+

PC48

220U_D2_4VM~D

2

PC49

PJP7

1 2

PAD-OPEN 4x4m
PJP8

1 2

PAD-OPEN 4x4m

PJP1

1 2

PAD-OPEN 4x4m

PD17

2 1

RB751V-40_SOD323~D

3 3

+1.5VSUSP

+VCCP

4 4

4.4UH_CDRH125-4R4NC_5A_+30%-20%~D

12

0.1U_0603_25V7K~D

VCCP_PWRGD<45>

PR58

PR63

12

10.5K_0603_1%~D

12

20K_0603_1%~D

+1.5VSUS

+VCCP_1P05VP

PL11

24

13

12

PR57

0_0603_5%~D

+3VRUN

12

PR66

PC83

1000P_0402_50V7K~D

10K_0402_5%~D

1 2

RB751V-40_SOD323~D

12

PC54

@ 1000P_0402_50V7K~D

1 2

0.1U_0805_50V7M~D

FDS6994S_SO8~D

4
3
2
1

PD19

2 1

RUNPWROK<18,35,38,45>

SUSPWROK_1P8V<44>

12

PC39

2200P_0402_50V7K~D

21

PD15

RB751V-40_SOD323~D

PR216

12

5
6
7
8

0_0402_5%~D

0_0402_5%~D

PC46

0.1U_0603_25V7K~D

PR60

12

PR80

@ 0_0402_5%~D

12

12

PR81

PR54
0_0603_5%~D

1 2

PR56

0_0603_5%~D

MAX1845_VCC

PQ8

D1

G1
S1

D1

G2

D2
D2

S2

RUN_ON_D<34,37,41>

1 2

33K_0402_5%~D

12

VCCP_PWRGD

1 2
13

D

2

G

S

PR217
11K_0402_1%~D

2N7002_SOT23~D

19
18
17
16
20
15
14

11
12

PQ37

PR52

20_0603_1%~D

12

PC45

1U_0603_10V6K~D

PU5

4

V+
BST2
DH2
LX2
CS2
DL2
OUT2
FB2

7

PGOOD
ON1
ON2

6

SKIP

8

OVP

9

UVP

1 2

MAX1845_VCC

22

VCC

+5VSUS

PC44

1 2

4.7U_0805_6.3V6K~D

21

VDD

BST1

DH1

LX1
CS1
DL1

OUT1

FB1

REF

TON
ILIM1
ILIM2

GND

23

MAX1845EEI_QSOP28~D

12

PC50

@1U_0603_10V6K~D

0_0603_5%~D

25

1 2
26
27
28
24
1
2

10

12

PC53

1U_0603_10V6K~D

5
3
13

PR53

PR61

@ 0_0402_5%~D

PD16

RB751V-40_SOD323~D

PR55

1 2

0_0603_5%~D

1 2

12

PR64

12

PR67

90.9K_0402_1%~D

21

578

PQ7

12

PC47

0.1U_0603_25V7K~D

12

PR62

100K_0402_1%~D

150K_0402_1%~D

12

PR68

80.6K_0402_1%~D

IRF7811AV_SO8~D

3 6

241

1.5uH_SIL104-1R5_10A_30%~D

578

PQ9
FDS6676S_SO8~D

3 6

241

12

PC40

2200P_0402_50V7K~D

PL12

1 2

PC41

1

10U_1206_25V6M~D

1

PC43

2

2

10U_1206_25V6M~D

0.1U_0805_50V7M~D

12

PC42

Design current 5A for +VCCP_1P05VP
Peak current 7.124A for +VCCP_1P05VP
OCP point is from 7.5A to 11A

+VCCP_1P05VP

1

12

12

PC52

PR59

1K_0603_1%~D

12

PR65

20K_0603_1%~D

+

PD18

PC51

2

0.1U_0603_25V7K~D

2 1

RB751V-40_SOD323~D

330U_D2E_2.5VM_R9~D

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
+1.5VSUSP /+VCCP_1P05VP

TOBAGO-LA2151

D

43 51Monday, October 18, 2004

0.6

of

5

4

3

2

1

D D

+1.8VSUSP/ +0.9V_DDR_VTT

DDR2 Termination

PL24

PWR_SRC

Design current 7A for +1.8V_SUSP
Peak current 10.1A for +1.8VSUSP
OCP point is 12.7A for +1.8VSUSP

C C

+1.8VSUSP

1

1

+

+

PC70

PC71

2

2

330U_D3L_6.3V_R25~D

330U_D3L_6.3V_R25~D

B B

FBM-L11-453215-900LMAT_1812~D

12

PC72

0.1U_0603_25V7K~D

1 2

PC158

1000P_0402_50V7K~D

1.4UH_CEP125-1R4_15.5A_20%~D

12

PR78

1 2

27.4K_0603_1%~D

12

PR82

17.4K_0603_1%~D

1

PC55

2

10U_1206_25V6M~D

PL14

1 2

PC56

1

12

12

PC57

2

10U_1206_25V6M~D

PC58

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

21

PD20

RB751V-40_SOD323~D

5

PQ34

PQ11

D8D7D6D

S1S2S3G

IRF7821_SO8~D

4

578

FDS7788_SO8~D

3 6

241

PC68

0.1U_0603_25V7K~D

0.22U_0603_10V7K~D

12

PC155

PR73

0_0603_5%~D

PR84

@ 0_0402_5%~D

12

12

12

PR200

1 2

100K_0402_1%~D

1 2

48.7K_0402_1%~D

PR202

PC62

12

4.7U_1206_10V7K~D

20

18

19

21

23

16

15

1

3

+5VSUS

SUSPWROK_5V<42>

22

VDD

BST

DH

LX

DL

MAX8550ETI_TQFN28~D

PGND1

VOUT

FB

TON

REF

ILIM

4

+3VSUS

PR193

1 2

10_1206_5%~D

PR194

PR195

1 2

1 2

100K_0402_1%~D

12

PC74

0.1U_0603_25V7K~D

100K_0402_1%~D

SUSPWROK_5V <42>

+1.8VSUSP

12

PC63

1 2

TP0

28

2

SHDNB

OVP/ UVP

PU6

SKIP

GND

25

24

PC66

1U_0603_10V6K~D

26

17

VIN

AVDD

5

POK1

6

POK2

27

SHDNA

7

STBY

13

VTTI

14

REFIN

11

PGND2

12

VTT

9

VTTS

10

VTTR

SS

8

1 2

1000P_0402_50V7K~D

PR204

20_0603_1%~D

12

PC77

0.1U_0603_25V7K~D

PC64

1 2

1U_0603_10V6K~D

12

PC146
10U_1206_6.3V7K~D

PC152

10U_1206_6.3V7K~D

TP0

SUSPW ROK_1P 8V <43>

+0.9V_PWRGD

12

PC153

10U_1206_6.3V7K~D

V_DDR_MCH_REF <10,16,17>

12

12

PR215

0_0402_5%~D

1 2

PR213
@ 0_0402_5%~D

PJP16

1 2

PAD-OPEN 4x4m
PJP17

1 2

PAD-OPEN 4x4m

12

PC154

10U_1206_6.3V7K~D

SUSPWROK_5V <42>

+5VSUS

PR197

1 2

100K_0402_1%~D

+1.8VSUSP

+1.5VSUS

+0.9V_DDR_VTTP

12

Design current 1.05A for +0.9V_DDR_VTTP
Peak current 1.5A for +0.9V_DDR_VTTP

PC157

10U_1206_6.3V7K~D

IC

MAX8550

2N7002_SOT23~D

Pop Un-pop

PR197,
PQ36

PQ36

13

D

S

PR212

@0_0402_5%~D

2

G

PR212

12

RUN_ON <19, 34,37,38,42>

MAX8550A

PJP9

PAD-OPE N 4x4m

1 2

PJP10

PAD-OPE N 4x4m

+1.8VSUSP

A A

+0.9V_DDR_VTTP

1 2

PJP11

1 2

PAD-OPEN 4x4m

5

+1.8VSUS

(10A,320mils ,Via NO.=20)

+0.9V_DDR_VTT

(3A,200mils ,Via NO.=6)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

PR212 PR197, PQ36

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c u m en t N u m be r Re v

Date: Sheet

Compal Electronics, Inc.

+1.8VSUSP/ +0.9V_DDR_VT

TOBAGO-LA2151

1

44 51Monday, October 18, 2004

of

0.6

8

7

6

5

4

3

2

1

VID 4

VID 3

11101

1

PR190

PR100

0_0402_5%~D

1 2

1 2

12

PR103

PR191

@0_0402_5%~D

PR218

0_0402_5%~D

PR117

@0_0402_5%~D

PR119

@0_0402_5%~D

PR121

0_0402_5%~D

V I D

1

1

1

@0_0402_5%~D

12

12

PR112

12

12

12

PR122

12

0_0402_5%~D

12

@0_0402_5%~D

VID 2

0

1

MAX1987_REF

1 2

MAX1987_VCC

PR113

PR123

CLK_ENABLE#<6,11>

CLK_ENABLE#<6,11>

VID 1

1

1

The C4 Mode voltage
is 0.748V, S2 open

MAX1987_VCC

PR219

@0_0402_5%~D

1 2

12

0_0402_5%~D

12

@0_0402_5%~D

DPRSLPVR<23>

VID 5

0

H H

10
1

G G

MAX1987_REF

MAX1987_VCC

F F

PR220

1 2

@0_0402_5%~D

@0_0402_5%~D

MAX1987_VCC

E E

MAX1987_REF

MAX1987_REF

D D

C C

PBOOT voltage seeting up on 1.212V

B B

0

1

0

PR98

PR114

@0_0402_5%~D

PR126

@0_0402_5%~D

1 2

@0_0402_5%~D

12

12

+3VRUN

+3VRUN

VID 0

Vcore

0

1.484

1.308

1

1

0.956

0.748

00

PR189

@0_0402_5%~D

PR133

@0_0402_5%~D

PR135

@0_0402_5%~D

V

VCCP_PWRGD<43>

IMVP_PWRGD<10,23,38>
CLK_ENABLE#<6,11>

VID5<8>
VID4<8>
VID3<8>
VID2<8>
VID1<8>
VID0<8>

H_PSI#<8>

H_STP_CPU#<6,23>

DPRSLPVR<23>

12

PC94

PC95

270P_0402_50V7K~D

0.22U_0603_10V7K~D

PR132

@100K_0402_1%~D

1 2

2

12

12

PR136

@100K_0402_1%~D

1 2

2

PR93

VID5
VID4
VID3
VID2
VID1
VID0

PR105 @0_0402_5%~D

PR109 0_0402_5%~D

PR111 0_0402_5%~D

RUNPWROK<18,35,38,43>

12

12

PR120

100K_0402_1%~D

12

PC97

PR127

20.5K_0402_1%~D

100P_0402_50V8K~D

13

D

PQ22

G

@2N7002_SOT23~D

S

13

D

PQ24

G

@BSS138_SOT23~D

S

+3VRUN

12

12

12

PR94

10K_0402_1%~D

1.91K_0603_1%~D

PR205 0_0603_5%~D

12

PR206 0_0603_5%~D

12

PR207 0_0603_5%~D

12

PR208 0_0603_5%~D

12

PR209 0_0603_5%~D

12

PR210 0_0603_5%~D

12

12

12

PR107

@0_0402_5%~D

12

12

12

PR116 0_0402_5%~D

MAX1987_REF

12

12

PR128

2

G

PR129

@15K_0402_1%~D

13

D

PQ21
@2N7002_SOT23~D

S

2

G

12

@36K_0402_5%~D

13

D

S

+5VRUN

12

PR91

10_0805_5%~D

MAX1987_VCC

12

PC84

1U_0603_10V6K~D

PR95

PU7

10K_0402_1%~D

22

SYSOK

23

IMVPOK

24

CLKEN#

25

D5

26

D4

27

D3

28

D2

29

D1

30

D0

8

S2

7

S1

6

S0

5

B2

4

B1

3

B0

21

PSI#

44

DPSLP#

43

SUS

9

SHDN#

14

CCV

10

REF

11

ILIM

2

TON

1

TIME

12

PR130

30.9K_0402_1%~D

PQ23
@2N7002_SOT23~D

12

VCC

POS15NEG

PR134

100K_0402_1%~D

+5VRUN

36

VDD

V+

BSTM

DHM

LXM
DLM

CMP
CMN

CSP
CSN

OAIN+

OAIN-

CCI

FB

DHS
LXS
DLS

BSTS

PGND

GND

DD0#

MAX1987ETM_TQFN48

16

12

PR131

1.24K_0402_1%~D

12

CPU_PWR_SRC

42
32
34
33
35

45
46

Remote Vcore sense

48
47

20

19

17

18

39
40
38
41

37
13
31

PC88

470P_0402_50V7K~D

1 2

PR115

1M_0402_1%~D

1 2

PC85

10U_1206_6.3V7K~D

12

PR101

3.01K_0402_1%~D

12

PR110

12

3.01K_0402_1%~D

21

PR97

2.2_0603_5%~D

1 2

+VCC_CORE

PD22

RB751V-40_SOD323~D

1 2

PR102

1K_0402_1%~D

1 2

PR104

1K_0402_1%~D

1 2

PR106

1K_0402_1%~D

1 2

PR108

1K_0402_1%~D

PR124

2.2_0603_5%~D

CPU_PWR_SRC

1

PC135

2 1

12

2 1

+

PC136

2

@ 15U_D2_25M_R90~D

1 2

PD23

@EC31QS04~D

1

+

PC137

2

@ 15U_D2_25M_R90~D

PL18

1 2

PD24

@EC31QS04~D

@ 15U_D2_25M_R90~D

PL17

PC138

1

+

2

1

2

@ 15U_D2_25M_R90~D

12

12

5

D8D7D6D

PQ13

S1S2S3G

4

12

PC86

0.1U_0603_25V7K~D

12

PC96

0.1U_0603_25V7K~D

1 2

PD25

2 1

RB751V-40_SOD323~D

+5VRUN

578

D8D7D6D

S1S2S3G

578

3 6

PQ15

3 6

241

5

PQ17

@IRF7821_SO8~D

4

PQ19

IRF7832_SO8~D

241

5

D8D7D6D

S1S2S3G

IRF7821_SO8~D

4

578

@IRF7832_SO8~D

3 6

241

D8D7D6D

S1S2S3G

578

3 6

PC78

0.1U_0805_50V7M~D

PQ14

@ IRF7821_SO8~D

PQ16

IRF7832_SO8~D

5

PQ18

PC89

IRF7821_SO8~D

4

PQ20

@ IRF7832_SO8~D

241

12

PC80

PC79

10U_1210_25V7K~D

2200P_0402_50V7K~D

12

12

PC91

PC90

2200P_0402_50V7K~D

0.1U_0805_50V7M~D

12

12

PC82

PC81

10U_1210_25V7K~D

@10U_1210_25V7M~D

Output Capatitors in H/W, ESR=3m ohms

0.36U_ETQP4LR36WFC_24A_20%~D

CPU_PWR_SRC

12

12

PC92

PC93

10U_1210_25V7K~D

10U_1210_25V7K~D

@10U_1210_25V7M~D

0.36U_ETQP4LR36WFC_24A_20%~D

PL21

FBM-L11-453215-900LMAT_1812~D

1 2

1

+

2

PC159

220U_25V_M

PR96

0.001_2512_5%~D

1 2

+

1 2

PR125

0.001_2512_5%~D

PWR_SRC

+VCC_CORE

PC87

0.01U_0402_25V7K~D

+VCC_CORE

12

PC98

0.01U_0402_25V7K~D

12

Change PR130:30.9k. Delete PR128/PR129/PR132/PR133/PR136/PQ21/PQ22/PQ23/PQ24 for BANIAS and DOTHAN
PR128/PR129/PR132/PR133/PR136/PQ21/PQ22/PQ23/PQ24 are only for YONAH CPU.
TRANSITION TIMING:

A A

(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us
(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/ us
(c): EXIT SUSPEND (SUS=LOW, RUNP WROK =HIGH): 24.7mV/us

8

7

6

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

4

3

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Do c u m en t N u m be r Re v

Date: Sheet

2

Compal Electronics, Inc.
+VCORE

TOBAGO-LA2151

45 51Monday, October 18, 2004

of

1

0.6

5

+DC_IN discharge path

+DC_IN

D D

C C

B B

A A

12

PC99

10U_1210_25V7K~D

PR142

PR143

49.9K_0402_1%~D

12

PC110

1 2

0.01U_0402_25V7K~D

12

PR148

0_0402_5%~D

12

PC118

0.01U_0402_25V7K~D

PQ30

2N7002_SOT23~D

ACAV_IN<35,40>

12

PR165

100K_0402_1%~D

PC102

1 2

1U_0805_25V4Z~D

365K_0402_1%~D

1 2

12

12

PR149

0_0402_5%~D

PR150

10K_0402_1%~D

12

12

12

12

PC122

PC121

PC120

PC119

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.1U_0603_25V7K~D

Connect GND side of PC118,
PC119, PC120 to GND
through 1 via.

CHG_PBATT<35>

5

1U_0603_10V6K~D

13

D

2

G

S

2

G

PD28

2 1

RB751V-40_SOD323~D

PR161
10K_0805_5%~D

1 2

10K_0402_1%~D

13

D

PQ31

S

2N7002_SOT23~D

+5VALW

PC123

BSS138_SOT23~D

2 1

SI4825DY_SO8~D

8
7

5

PR162

12

ACAV_IN<35,40>

1 2

1U_0603_10V6K~D

PR153

59K_0402_1%~D

PQ28

2

G

PR160

1 2

100K_0402_1%~D

PD29

@B540C~D

PQ29

+VCHGR

1 2

13

D

S

4

4

100K_0402_1%~D

PR164
@0_0402_5%~D

1 2

PR154

10K_0402_1%~D

PR159

10K_0402_1%~D

4

1
2
36

PR163

1 2

1 2

12

PDS

CHVREF

PC126

PR146

1 2

0_0402_5%~D

1 2

1500P_0402_50V7K~D

Adress : 12H

PDL

3

PR138

0.01_2512_1%~D

1 2

PR139

0_0402_5%~D

1 2

PC100

1 2

@0.1U_0603_25V7K~D

29

PU8

PDS

31

PDS

CSSP

27

SRC

1

DCIN

3

ACIN

32

ACOK

6

CCS

7

CCI

8

CCV

11

DAC

4

REF

19

BATT

12

VDD

13

THM

16

INT

30

PDL

17

I.C.

GND

5

PWR_SRC +SDC_IN

FBM-L11-453215-900LMAT_1812~D

PR140

0_0402_5%~D

1 2

PR141

10K_0402_1%~D

1 2

PC101

1 2

@0.1U_0603_25V7K~D

28

CSSN

GND18IMAX

12

PC108

25

2

PR147

0_0805_5%~D

24

26
23

22

21
20

15
14
9

PR157

280K_0402_1%~D

PR158

1U_0805_25V4Z~D

DHIV

LDO

DLOV

DHI

DLO

PGND

CSIP

CSIN

SCL
SDA

VMAX

MAX1535BETJ TQFN32~D

10

12

52.3K_0402_1%~D

12

CHVREF

12

PL19

1 2

PR192

1 2

16.2K_0402_1%~D

PC109

1U_0603_10V6K~D

1 2

PR144

PC111

33_0603_5%~D

1U_0603_10V6K~D

1 2

1 2

PBAT_SMBCLK <19,35,41>
PBAT_SMBDAT <19,35,41>

PR156

12

PC127

2200P_0402_50V7K~D

ACAV_IN <35,40>

PQ25

SI4835DY_SO8~D

PC117

1 2

@1000P_0402_50V7K~D

12

PR155

102K_0402_1%~D

1 2

182K_0402_1%~D

VMAX=2.625V

PC128

+SDC_IN

36

578

578

3 6

CHVREF

1 2

0.1U_0805_50V7M~D

241

8.2U_CEP125-8R2MC_5.8A_20%~D

PQ27

FDS6670S_SO8~D

241

2 1

PC124

PD27

@ EC31QS04~D

0_0402_5%~D

1 2

@0.1U_0603_25V7K~D

2

PD30

@B540C~D

PQ33

SI4825DY_SO8~D

1
2
3 6

4

PR168

1 2

470K_0402_5%~D

PL20

1 2

PR151

1 2

1 2

PC125

@0.1U_0603_25V7K~D

21

8
7

5

PR166

0_0402_5%~D

1 2

PR167

@0_0402_5%~D

1 2

0.01_2512_1%~D

1 2

PR152

0_0402_5%~D

1 2

PR145

1

+VCHGR

PDL

+DC_IN

12

PC103

PC104

PC105

1 2

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PC112

1 2

0.1U_0805_50V7M~D

12

12

PC106

10U_1210_25V7K~D

12

PC113

10U_1210_25V7K~D

12

PC107

10U_1210_25V7K~D

@ 10U_1210_25V7K~D

+VCHGR

12

12

PC115

PC114

10U_1210_25V7K~D

12

PC116

@10U_1210_25V7K~D

@10U_1210_25V7K~D

Maximum charger voltage=13.12V
IMAX=0.654V

Maximum charger current=3.271A

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.
Charger

TOBAGO-LA2151

46 51Monday, October 18, 2004

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

1 0.1

2

3

4

5 36 H/W 01/28 Roger Rotate the Keyboard connector 180 degree

ALL H/W 01/19 Roger Rename component location for manufacture Update schematic and board file component reference

39 H/W 01/19 Roger

34 H/W 01/19 Roger Add the COM port debug circuit Add U184 for COM port debug

Title

Owner

The light of WLAN and Blue tooth LED too
dim

Change R1251 (0_0402_5%~D) to C34(1000P_0402_50V7K~D) Roger01/19H/W30 R2151 tie +3VLAN to GND via LAN transformer

Change R8, R15 from 330 ohm to 56 ohm

Reconnect keyboard signals to CN1,CN2,CN3,CN4,CN5,C207 for layout
smoothly

6 36 H/W 01/30 Roger Keep more spacing for VGA thermal solution Delete JP3 debug port to save spacing for ROM part placement 0 . 1

7 12 H/W 02/03 Roger +2.5VRUN is margin for 2N7002 Change Q7,Q27,Q31,Q33 gate voltage from +2.5VRUN to +3VRUN 0.1

8 06 H/W 02/04 Roger

C C

9 38 H/W 02/04 Roger

Change R330 and R354 to 0 ohms per Intel
review.

Resolves the issue where 1.5VSUS_PWRGD
goes high before +1.5VSUS

Change R330 and R354 from 1K to 0 ohms 0.1

Change R230 from 330 to 10K ohm and R227 from 1K to 10K ohms 0.1

Resolves the issue where +1.5VRUN drop
100 mV from +1.5VSUS to +1.5VRUN.

11 18 H/W 02/09 Roger Add a bulk cap for G_PWR_SRC Add C569 for G_PWR_SRC placement near JVID 0.1

12 39 H/W 02/09 Roger

BAT1_LED# should drive the GREEN LED,
BAT2_LED# should drive the ORANGE LED

13 21 H/W 02/09 Roger Follow X01 Gerber Gate Checklist item 11

14 38 H/W 02/09 Roger

Follow X01 Gerber Gate Checklist item 12,
ICH_PWRGD circuit match Laguna

Change R5 pin 2 connect to D3 pin4, R265 pin2 connect to D3 pin2 0.1
Change R328 from 0 ohm to 1K ohm and add note "Pop resistor to boot

from PCI".
Remove R470 and no connect U21B, RESET_OUT# connector to U21A pin 2. 0.1

15 35 H/W 02/09 Roger Change Board ID to X01 Depop R419 and populate R405

16 35 H/W 02/09 Roger

B B

17 06 H/W 02/10 Roger

18 ALL H/W 02/11 Roger

19 23 H/W 02/16 Roger

20 39 ME 02/17 Roger Change screw hole size for system assembly

21 34 H/W 02/22 Roger Depop R116 and pop R114, Depop R119 and pop R128 0.1

22 35 H/W 02/22 Roger 0.1C130 change from 100P 0603 to 1U 0603

System will auto power on when AC plug in
if RTC coin battery not implement

Reserve SSC clock for internal graphic
for clock generator ICS954206

Change connector name to match the naming
rule

+1.5VRUN leakage issue at system into S3
status

Change the power source from +RTC_CELL to
+3.3VX

Auto power on when AC plug in issue will
be using the BIOS fix

Change C130 from 1U to 100P to reduce POWER_SW_IN# rising time.
96MHz SSC clock connect to U16 pin 17,18. Add the serie damping R524,

R525, pull down resistor R522, R523.
Change JP5 to JMOD, JP6 to JWIRE, JP2 to JPSW, JP1 to JLVDS, JP4 to

JCRT
ICH6M GPIO24 connect to SIO_EXT_WAK# for option the GPIO power plane 0.1
H15 change diameter form 3 mm to 4.2 mm, H18 change diameter from 3 mm

to 2.8 mm

23 39 H/W 03/12 Roger LED_WLAN_OUT should drive green LED Change R15 from 56 ohms to 330 ohms 0.1

24 29,39 H/W 03/12 Roger

A A

Blue tooth and meida blue LED trun on
voltage Vf is 2.7 to 3.9V. +3.3V have risk
don't trun on LED.

Change Q4 pin 1 and JLCM pin19 power source from +3VALW to +5VALW 0.1

Solution Description Rev.Page#

0.1

0.1

0.1

0.1

0.1Change Q44 from SI3456 to SI4810 that have lower Rds on.10 Roger02/09H/W37

0.1

0.1

0.1

0.1

0.1

0.1

Request

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/2

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

47 51Monday, October 18, 2004

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

25 0.3

26 6 H/W 03/17 Roger

27 19 H/W 03/17 Roger

28 13 H/W 03/18 Roger

29 31 H/W 03/19 Roger

35 H/W 03/17 Roger

Title

Owner

SIO SM Bus EA measure issue for rising and
falling time

ICH SM Bus EA measure issue for rising and
falling time

LCDVDD component unnecessary for external
board

Remove CRT, LVDS, TV DAC power beads and
caps

Card bus EA measure CBS_CCLK rising and
falling failure issue

R131, R444, R447, R449 change from 22K ohms to 8.2K ohms

R270, R275 change from 100K ohms to 2.2K ohms 0.3
Depop Q8, Q9,Q10, Q37, R35, R54, R263, R272, C29, C315 on external

board and pop on internal board
Depop L9, L10, L11, L25, L26, L24, C24, C291, C293, C22, C298, C299,

C23, C323, C310, C297, C314, C331, C322, C37, C35, C305, C306, C36,
C304 on external board and pop on internal board

R495 change from 47 ohms to 22 ohms 0.3

30 27 H/W 03/23 Roger ME change audio jacks to combined jack Change JAUDIO symbol to combined two jacks, delete JHP 0.3

31 15 H/W 03/25 Roger

32 26 H/W 03/25 Roger

C C

33 25 H/W 03/25 Roger

34 26 H/W 03/25 Roger

Roger03/25H/W3935

PT layout issue list item 6, consistent
with other platforms

Layout issue list item 16, pop issue and
the static noise during post and idle in
Windows

Issue list item 8, connect UART interface
to ICH GPIO for debug

Issue list item 11, allow the capability
to disable the line in option

Issue list item 12, blue LED to dim

Change U15 pin 10 power source from +3.3VX to +RTC_CELL

Add a non-popped inverter U30 add a 0 ohm R528 around the inverter 0.3

Connect U11 pin 45 (UAO) to ICH6 pin AC18 (GPIO34). Connect U11 pin
43 (UAI) to ICH6 pin AF20 (GPIO33)

Connect a no popped 0 ohm R529 from LINE_IN_L to 9750_PHONE. Connect a
no popped 0 ohm R530 from LINE_IN_R to 9750_PHONE

LED & R58 move to collection side of BJT. Q4 pin 3 connect to GND,
JPSW pin 2 change to connect +5VALW.

03/25 Roger36 18 H/W Issue list item 9, C569 not require fo now Add non-popped symbol for C569 0.3

37 03/26 Roger29 H/W

38 03/28 Roger34 H/W

EMI request add a cap place near R518 for
blue tooth

Issue list item 7, swap SIO_PWRBTN# and
ICH_PCIE_WAKE# to fix WOL issue on Laguna

Add C570 (33P_0402_50V8J~D) 0.3
Swap SIO_PWRBTN# (U20 pin A15) and

ICH_PCIE_WAKE# (U20 pin A13)

39 35 03/28 RogerH/W Change board ID to (0010) for X02 board Pop R94, R419 and non-popped R107, R405 0.3

B B

40 6 03/28 RogerH/W

Reserved clock gernerator pin53 for 14.318
MHz for ICS 954206

41 6 H/W 04/01 Roger TV out B/W issue on UMA configuration

Add a 12.1 ohms series resistor R531 to U16 pin 53 and connect to
CLK_CODEC_14M. Isolation resistor R531 connect to CLKSEL0

Pop C329 and C333 with 27P to fine tune the crystal frequency and clock
sequence

42 15 H/W 04/02 Roger FAN RPM detect issue Change C209 to 1000P and de-popped 0.3

43 26 H/W 04/04 Roger

Solve the pop issue and the static noise
during post and idle in Windows

Pop U30 inverter and depop R528 (0_0402_5%) 0.3

44 27 H/W 04/04 Roger Tune audio amplifier gain to 21.6dB Pop R164 (10K_0402_5%) and depop R107 (10K_0402_5%) 0.3

Solution Description Rev.Page#

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

Request

45 37 H/W 04/04 Roger For the +5VHDD power source, use +5VRUN Depop Q51, Q50, R507, C547 and pop R506 ( 0_0805_5%) 0.3

46 27 H/W 04/04 Roger

47 38 H/W 04/07 Roger

A A

48 13 H/W 04/07 Roger

Dell Audio team request
PCI clocks to ICH_PWRGD timing too late

issue. SPEC is at least 99 ms
Intel Design Guide recommend populate TV

DAC & CRT DAC power inputs filtering

C535, C536 change from 0.47UF to 0.1UF and C199, C206 change from 2.2UF
to 0.1F

Change C520 form 0.1UF to 0.01UF

Change back population L9, L10, L11, L25, L26, L24, C24, C291, C293,
C22, C298, C299, C23, C323, C310, C297, C314, C331, C322, C37, C35,

0.3

0.3

0.3

C305, C306, C36, C304 on external board

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/2

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

48 51Monday, October 18, 2004

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

49 0.4

6,10,22 H/W 04/28 Roger

50 Add smart dimmer function for VGA board

51 ICH_V5REF_RUN leakage issue

52

53 39 H/W 05/19 Roger Increase breath and HDD active LED light

54 25 H/W 05/19 Roger

55 25 H/W 05/19 Roger

Title

H/W 05/17 Roger R274 burn out issue6

Owner

Modify pop option for B1 stepping Dothan
CPU for ST build

Roger05/06H/W18,35 0.4

RogerH/W 05/06

X03 issue list item7, modify the SATA
crystal circuit

X03 issue list item8,reserve oscillator
for istead of crystal for marvell 8040

Depop R305, R364, R438. Pop R329, R343, R88 for both UMA and discrete
mother board

U20 pin E3 (BIA_PWM) connect to JVID pin4 isolate by R534 and U4 pin
E25 isolate by R533

Reserve R535 for +5VRUN power source24
Change R274 (1 ohm) from 0402 to 0603 size, R273,R401(2.2 ohms) from

0402 to 0603 size.
Breath LED circuit change to like the bluetooth LED circuit, R1 & R2

change from 330 ohms to 56 ohms
Connect R190 pin1 to U11 pin23, connect pin2 to Y1 pin 2 0.4

Add a non-pop oscillator Y3 (25MHz) connect to U11 pin22, Pin23 0.4

55 24 H/W 05/19 Roger X03 issue list item8, ICH leakage issue Reserve R537 connect +5VSUS for ICH_5VREF_SUS power source 0.4

C C

56 15 H/W 06/01 Roger

57 27 H/W 06/01 Roger

58 25 H/W 06/07 Roger HDD can't detect issue

59 36 H/W 06/07 Roger

60 35 H/W 06/07 Roger

61 6 H/W 06/07 Roger

62 39 H/W 06/07 Roger

63 27 H/W 06/08 Roger

B B

64 27 H/W 06/08 Roger

OTP shutdown temperature varies. Offset 6
degree C to 79 degree C

When audio recorded, CPU fan noise will be
covered from +5VRUN

Change R249 from 13.1K ohms to 147K ohms to set VSET to 0.25V 0.4

R143 change from +5VRUN to +5VSUS 0.4
C279, C280 change to 12 PF, Add a 25M oscillator reserve for Marvel

8040

EMC request pop keyboard matrix signal
bypass caps.

Change CN1~CN6 to single 100pF cap for cost saving 0.4

Change board ID for X03 (R04) Pop R405 and de-pop R419 (BID : 0011) 0.4
X03 issue list item 19, add pull down

resistor for SRC/CLKREQ select
X03 issue list item 20, Bluetooth LED is

too bright
Audio codec and U5 (MAX4411) were unified

into the same power
Audio amplifier power and gain setting pull

up power were unified into the same power

Add R538 (0 ohm) for pull down U16 pin 56 0.4

Change R8 from 56 ohms to 1K ohms 0.4

U5 pin10, 19 and R132 pin1 change connect from +3VRUN to +VDDA 0.4

R164 pin1 and R165 change connect from +5VRUN to +5VAMPVCC 0.4

65 13 H/W 06/09 Roger UMA platform TV out water wave issue Add C598 (4.7U_0805_10V4Z) for +3VRUN_ATVBG bulk 0.4

66 29 H/W 06/09 Roger

Media board signal EMI resistors no
necessary now

Remove R188,R189,R193,R194,R195,R196,R197,R208,R209,R220,R221 0.4

67 25 H/W 06/11 Roger X03 issue list item 28 Connect R204 pin1 to U11 (Marvel 8040) pin22 0.4

68 28 H/W 06/11 Roger X03 issue list item 29,30

69 34,35 H/W 06/11 Roger X03 issue list item 31,32

70 37 H/W 06/11 Roger

71 38 H/W 06/11 Roger

A A

72 30 H/W 06/11 Roger

Supply +1.8VRUN for Graphic board from
Mother board

Reserved option to use the Sullivan/Laguna
rbatt

According to the cystal vendor measure
report

Add PJP21 between USBP4_PWR and USBP5_PWR, PJP22 between USBP7_PWR and
USBP8_PWR

Pop R116 and no-pop R114, pop R119 and no-pop R128 to change power
source from +3.3VX to +RTC_CELL

Change Q14 from SI2456 to SI4810 for larger power margin.

Add JCOIN connect to +COINCELL 0.4

Change R264 from 200 to 820 ohms to reduce the drive level 0.4

Solution Description Rev.Page#

0.4

0.4

0.4

0.4

0.4

0.4

0.4

Request

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/2

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

49 51Monday, October 18, 2004

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

73 0.4

37 H/W 06/11 Roger +5VRUN glitch when HDD shut down Populate Q50, Q51,R507,C547 and de-pop R506

Title

Owner

74 26 H/W 06/14 Roger Disable the Line In MIC function for No Pop C510 and C512 & Pop R529 and R530 0.4

75 27 H/W 06/14 Roger X03 issue list item 21 Change C147 and C148 from 1uF (0603) to 3.3uF (0603) 0.4

76 12 H/W 06/15 Roger X03 issue list item 41

Change Q33, Q7, Q31, and Q27 to BSS138 and use +2.5VRUN for gate
voltage

77 24 H/W 06/15 Roger X03 issue list item 40 Change R535 to 100 ohm per Intel spec 0.4

78 22 H/W 06/17 Roger Pop resistor for support deeper sleep Pop R121 (0_0402_5%) and R127 (56_0402_5%) 0.4

79 25 H/W 06/17 Roger Implement oscillator for Marvel 8040 De-pop Y1, R204, R190, C279, C280

80 28 H/W 07/21 Roger Move USB power jump to close bulk cap

C C

81 35 H/W 07/21 Roger Change board ID for V0.6 Depop R94, R405, R108 and pop R107, R419, R95 0 .6

82 23,34 H/W 07/27 Roger LCD_TST for panel control by ICH6-M and SIO

PJP21 connect R14 pin2 and R22 pin2. PJP22 connect R96 pin2 and R109
pin2

LCD_TST connect to ICH6-M pin AD20(GPO21) and Macallan pin B12 (LGPIO70)
isolate by R539,R540

83 9 H/W 08/01 Roger Reduce CUP core caps for cost saving Depop C428, C446, CC448, C431, C119, C118 0.6

84 13 H/W 08/29 Roger

Change +1.5VRUN_DPLLA, +1.5VRUN_DPLLB,
+1.5VRUN_HPLL, +1.5VRUN_MPLL inductance

Change L28, L33, L38, L39 to TDK 10U_MLZ2012E100PTAIN 10 UH inductance 0.6

85 39 H/W 08/11 Roger Balance LED brightness Change R5 value from 330 ohms to 220 ohms 0.6

86 6 H/W 09/03 Roger

87 36 H/W 09/23 Roger

88 39 H/W 09/23 Roger

B B

89

15 H/W 11/03 Roger Forcecon CPU fan acoustic issue Pop C538 (2200P_0402_25V7K)

Dell other project have issue at CLKSEL0
signal

SST flash ROM part have crash issue, need
to further clarify

Change the LED from non clear lens to
clear lens

Depop R532 and pop R259 0.6

Change SST 39VF080 to MXIC MX29LV008BTC-70R 0.6

Change D1, D2, D3 from HARVATEK to Lite-on

Solution Description Rev.Page#

0.4

0.4

0.6

0.6

0.6

1.0

Request

90

91

92

92 19 H/W 11/03 Roger

A A

23 H/W 11/03 Roger Intel sighting report #67725 workround

Pop R433 (100K_0402)

10 H/W 11/03 Roger Intel sighting report #68363 workround De-pop R435, R437

39 H/W 11/03 Roger Blue tooth LED is too bright Change R8 from (1K_0603) to (3.3K_0603)

fine tune G_PWR_SRC lag +3VRUN sequence
issue

Change C290 form 0.1UF to 1000PF

1.0

1.0

1.0

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/2

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

50 51Wednesday, November 03, 2004

1

of

0.6

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

1 0.1
2
3
4

46 POWER 01/30 Demon Change charger current Change PR158 from 90.9K to 52.3K
44 POWER 01/30 Demon
42 Dell request to add components Change PC15 from 4.7u to 2.2u, add PR203(100 ohm) and PC156(2.2u)
40 POWER 02/06 Demon Dell request to change component Change PR2 from 1.5k to 2.2k 0.1

Title

Owner

Change PU6 from SC1486 to MAX8550 and other component at P44Change DDR2 solution

Demon01/30POWER

5 43 POWER 02/13 Demon Dell request to change component Change PC51 from 330U 25m ohm to 330U 9m ohm 0.1
6
7

40 POWER 03/17 Demon EMI request Delete PL3 and pop PL2, add PL21 FBM-L11-453215-900LMAT_1812~D

POWER 03/17 Demon

EMI request45 Change PR97,PR124 from 0 ohm to 2.2 ohm
8 44 POWER 03/17 Demon Add PC158 1000PDouble Plus at high side gate 0.2
942
10 43

C C

4411

POWER
POWER
POWER

03/25
03/25
03/25

Demon
Demon
Demon

12 43 POWER 03/29 Demon

EMI request

EMI request

EMI request

Increase 1.5VSUS voltage spec of power

source for GMCH 1.5V Vcc power on Tobago

Add PL22 FBM-L11-453215-900LMAT_1812~D

Add PL23 FBM-L11-453215-900LMAT_1812~D
Add PL24 FBM-L11-453215-900LMAT_1812~D
Change PR58 from 10K to 11K 0.2

13 40 POWER 04/05 Demon Change PQ1 from 2N7002 to BSS138 DELL EE request 0.2
14 42 POWER 05/10 Demon DELL power team request Change PR27 from 4.7ohm to 10ohm, and add PR211 10ohm
15 46 POWER 05/10 Demon DELL request Change PU8 from MAX1535AETJ to MAX1535BETJ

44 For vender new version MAX8550ADemon05/14POWER16

17 45 POWER 05/19 Demon DELL request

Add PR212,PR215 0 ohm , and un-pop PQ36,
PR197,PR213,PR214, and change PU6 from MAX8550 to MAX8550A

Change PQ13,PQ17 from IRF7811AV to IRF7821 and PQ15,PQ19 from SI4362

to IRF7832 and un-pop PQ16,PQ20
18 44 POWER 05/31 Demon DELL request Change PC152, PC153, PC154,PC157 from 22uF to 10uF 0.3
19 48 POWER 05/31 Demon Modify layout Un-pop PQ15 and PQ17, pop PQ16 and PQ18

Modify schematic the same with Laguna

20 44 POWER 05/31 Demon

B B

and change switching frequencies from
450kHz to 300kHz

21 43 POWER 06/07 Demon DELL request, for MAX1845 negative voltage

Un-pop PR84

Add PQ37 2N7002 and PR216 33k ohm. 0.3

issue.
22 41 POWER 06/07 Demon Modify 2.5V power sequence Change PR1 from 0 ohm to 8.2k ohm and add PC8 0.1u. 0.3
23 43 POWER 06/10 Demon Change 1.55V to 1.525V Change PR58 from 11K to 10.5K. 0.3

4424 POWER 06/10 Demon For MAX8550 Add PQ36 and PR197 100k ohm, and delete PR212 0 ohm. 0.3
25 43 POWER 06/15 Demon For power sequence Pop PR60 and un-pop PR80 at External and Internal M/B. 0.3
26

43 POWER 07/08 Demon For MAX1845 OVP issue Add PR217 11k ohm.
27 45 POWER 07/08 Demon For MAX1987 C4 Voltage Add PR218 0 ohm and delete PR103 0 ohm and un-popPR219,PR220
28

45 POWER 07/21 Demon For noise issue Add a un-pop component PC159 0.4

Solution Description Rev.Page#

0.1

0.1

0.2

0.2

0.2

0.2

0.2

0.3

0.3

0.3

0.3

0.3

0.3

0.4

0.4

Request

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/2

Size Document Number Rev

TOBAGO-LA2151

Date: Sheet

51 51Monday, October 18, 2004

1

of

0.6