Compal LA-2112, Latitude D810 Schematic
5
D D
4
3
2
1
LAGUNA
REV : X03
C C
@ : Depop Component
PRELIMINARY
B B
A A
LA-2112 (8 Layer M/B for LAGUNA)
Dothan Schematic with Capture CIS and Function field
uFCPGA Dothan
10-07-2004
REV: 0.4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number R ev
Date: Sheet of
Cover Sheet
Board Number LA2112
1 82Thursday, October 28, 2004
1
0.4
5
Compal confidential
4
3
2
1
Block Diagram
D D
GUARDIAN
EMC6N300
page 39
Dothan
uFCPGA CPU
page 7,8,9
Fan Control
HA#(3..31)
CRT CONN.
& TV-OUT
VGA
page 19
Board
PCI-E 16X
VGA CONN.
C C
page 18
System Bus
400 / 533MHz
Alviso
GMCH-M
1257 FC-BGA
HD#(0..63)
page
10,11,12
13,14
Memory
BUS(DDR2)
1.8V 400 / 533MHz
SO-DIMM X2
BANK 0, 1, 2, 3
page16,17
Clock Generator
page 15
CK410M
page 6
DMI
DOCKING
PORT
PAGE 35
DOCKING
BUFFER
PAGE 34
USB
IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)
B B
CardBus Controller
PCI6515
Smart card
page31
3.3V 33MHz
page 31,32
Slot 0
page32
MINI PCI
page 33
LAN
BCM5751M
Analog Switch
Transformer
RJ45
page 30
page 30
page 30
PCI BUS
PCI-E BUS
LPC BUS
3.3V 33MHz
Macallen III
X BUS
A A
5
SST39VF080
page 38
4
COM
page 28
Touch Pad
page 38
1.5V
100MHz
LPC to X-BUS
& Super I/O
page
36,37
ICH6
3.3V 24.576MHz
609 BGA
page
20,21,22,23
ATA100 and SATA
SATA
Marvell
SATA to PATA
page 52
PATA
CDROM
USB
FDD
SATA HDD
page 24
48MHz / 480Mb
Int.KBD
page 38
FIR (LED/B)
page 40
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
USB2.0
page 27
HDD
page 52
USB
USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7
FDD
DOCK
BT
Card BUS
JUSB2 U
JUSB2 D
JUSB1 U
JUSB1 D
2
AC-LINK
AC97
Codec
STAC9751
page 25page 29
AMP& Phone
Jack
page 26
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number R ev
Date: Sheet of
MDC
page 28
Block Diagram
Board Number LA2112
DC IN
BATT
IN
1.8V / 0.9V
page
44
page
45
page
44
1.5V/1.05V(+VCCP)
page 47
VCORE
page 49
5V/3.3V/15V
page 46
CHARGER
1
page
50,51
2 82Thursday, October 28, 2004
0.4
5
D D
4
3
2
1
PM TABLE
C C
power
plane
State
S0
S1
S3
S5 S4/AC
B B
S5 S4/AC don't exist
A A
+3VALW
+5VALW
+RTC_CELL
+3.3VX
ON
ON
ON
ON
+3VSUS
+5VSUS
+1.8VSUS
+1.5VSUS
+15V
+5VRUN
+3VRUN
+2.5VRUN
+1.8VRUN
+1.5VRUN
+VCC_CORE
+VCCP
ON ON
ON
ON
OFF
OFFOFF
+0.9V_DDR_VTT
ON
OFF
OFF
OFF
PCI TABLE
PCI DEVICE
CARD BUS
DOCK
MINI PCI
IDSEL
AD17
AD24
AD19
REQ#/GNT#
1
0
3
PIRQ
D,C
A
D,B
USB TABLE
USB PORT#0DESTINATION
FDD (module bay)
1
2
DOCK
MPCI (BlueTooth)
3 NEW Connector
4
5
6
7
USB Port 2(Top)
USB Port 2(Bottom)
USB Port 1(Top)
USB Port 1(Bottom)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number R ev
Date: Sheet of
Index and Config.
Board Number LA2112
3 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
D D
+5VALW
ADAPTER
PWR_SRC
BATTERY
C C
+5VSUS
B B
RUN_ON
PL9
AUDIO_AVDD_ON
SUS_ON
(Option)
+3VALW
SUS_ON
+3VSRC
RUN_ON
G_PWR_SRC
SUSPWROK_5V
+VCC_CORE
RUN_ON
RUNPWROK
+1.5VSUS
RUN_ON SUSPWROK_5V
RUNPWROK
+VCCP
SUSPWROK_5V
+5RUN
+1.8VSUSP +0.9V_DDR_VTT
PJP11,PJP12
+5VHDD +5VMOD +5VRUN VDDA
A A
5
+15V +2.5VRUN
4
+3VRUN
L10
V3P3LAN
+3VSUS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.5VRUN
2
+1.8VSUS
RUN_ON
+1.8VRUN
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number R ev
Date: Sheet of
Power Rail
Board Number LA2112
4 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
+3VRUN
ICH_SMBCLK
D D
ICH6
ICH_SMBDATA
+3VSUS
7002
7002
CK_SCLK
CLK GEN.
CK_SDATA
DIMM0
Address 00 Address 10
CLK_SMB
DAT_SMB
C C
+3VALW
DIMM1
GUARDIAN
7002
7002
7002
7002
V_3P3_LAN
LAN_SMBCLK
LOM
LAN_SMBDATA
24C04
DOCK_SMB_CLK
SIO
DOCK_SMB_DAT
+5VALW
DOCKING
Macallen III
SBAT_SMBCLK
SBAT_SMBDAT
B B
+5VALW
2'nd
BATTERY
VGA
PBAT_SMBCLK
1'st
PBAT_SMBDAT +5VALW
A A
BATTERY
CHARGER
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number R ev
Date: Sheet of
SMBUS TOPOLOGY
Board Number LA2112
5 82Thursday, October 28, 2004
1
0.4
5
+3VRUN
R57
ICH_SMBDATA<22,33>
D D
ICH_SMBCLK<22,33>
ICH_SMBDATA
+3VRUN
ICH_SMBCLK
D
1 3
2
2
1 3
D
S
Q6
2N7002_SOT23~D
G
G
Q8
2N7002_SOT23~D
S
D
1
3
G
S
2
2N7002
FSC FSB FSA CPU
CLKSEL0 CLKSEL1 CLKSEL2
C C
00
0
1
1 1
0
0
1
11
1
0
0
1
0
1
0
0
0
1
1
1
MHz
266
133
200
166
333
100
400
SRC
MHz
100 33.30
100
100
100
100
100
100
RESERVED
12
100K_0402_5%~D
CK_VDD_A
C1247
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
12
R61
100K_0402_5%~D
CK_SDATA
CK_SCLK
1
2
4.7U_0805_6.3V6K~D
Table : ICS 954201 / Cypress CY28411
+VCCP
B B
CLKSEL0
CPU_BSEL0<8>
A A
CPU_BSEL1<8>
1 2
R643
0_0402_5%~D
CLKSEL1
1 2
R641
0_0402_5%~D
5
+VCCP
R65
1K_0402_5%~D
@
1 2
1 2
R1070
1K_0402_5%~D
R66
0_0402_5%~D
@
1 2
R95
1K_0402_5%~D
@
1 2
1 2
R1073
1K_0402_5%~D
R90
0_0402_5%~D
@
1 2
Dothan-A 400MHz, Install R65, No pop. R66, R643
Dothan-A 533MHz, Install R66, No pop. R65, R643
MCH_CLKSEL0 <10>
MCH_CLKSEL1 <10>
1
2
C1248
0.047U_0402_10V7K~D
CK_48M_SCR<31>
CK_48M_ICH<22>
CK_33M_DOCKPCI<34>
CK_33M_SIOPCI<36>
CK_33M_MINIPCI<33>
CK_33M_CBPCI<31>
CK_33M_ICHPCI<20>
+3VRUN
4
CK_SDATA <16,17>
CK_SCLK <16,17>
CK_VDD_48
1
2
C1249
4.7U_0805_6.3V6K~D
C90
27P_0402_50V8J~D
C93
27P_0402_50V8J~D
CK_48M_SCR
CK_48M_ICH
CLKSEL1
CLKSEL0
CK_33M_DOCKPCI
CK_33M_SIOPCI
CK_33M_MINIPCI
CK_33M_CBPCI
CK_33M_ICHPCI
CK_33M_LOMPCI<29>
R96
10K_0402_5%~D
1 2
CLKSEL2
R91
10K_0402_5%~D
@
1 2
R68(SIOPCI)
R1206(LOMPCI)
R83(MINIPCI)
ICS -- ICS954201BG
Cypress -- CY28411ZXC
Pericom -- PI6C410MA
4
1
2
12
12
CK_VDD_REF
C1251
0.047U_0402_10V7K~D
Place crystal within
500 mils of CK410
X1
12
14.31818MHz_20P_1BX14318CC1A~D
+3VRUN
+3VRUN
1 2
L33
BLM21PG600SN1D_0805~D
1
C992
0.1U_0402_16V4Z~D
1 2
2
1 2
L130
BLM21PG600SN1D_0805~D
1
2
C1252
0.047U_0402_10V7K~D
CK_XTAL_IN
CK_XTAL_OUT
R59 33_0402_5%~D
R62 33_0402_5%~D
12
R81 33_0402_5%~D
12
R83 12.1_0402_1%~D
12
R68 12.1_0402_1%~D
12
R79 33_0402_5%~D
12
R88 33_0402_5%~D
R177
10K_0402_5%~D
1 2
1 2
R67 475_0402_1%~D
R1206
4.7_0402_1%~D
CK_VDD_MAIN2
12
CLKSEL2
12
PCICLKF0
PCICLKF0
ICS Cypress & Pericom
12.1 Ohm 33 Ohm
4.7 Ohm
12.1 Ohm
33 Ohm
33 Ohm
3
CK_VDD_MAIN
CK_VDD_MAIN
2
C89
4.7U_0805_6.3V6K~D
1
2
C993
4.7U_0805_6.3V6K~D
1
U8
21
28
34
1
7
42
CK_VDD_REF
CK_VDD_48
3
48
11
50
49
12
16
53
5
4
3
56
9
8
46
47
39
13
29
2
45
51
6
1 2
R1107
1_0603_5%~D
1 2
R1108
2.2_0603_5%~D
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1
CK_SCLK
CK_SDATA
CLKIREF
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
C94
0.047U_0402_10V7K~D
2
1
C994
0.047U_0402_10V7K~D
2
VDD_SRC0
VDD_SRC1
VDD_SRC2
VDD_PCI0
VDD_PCI1
VDD_CPU
VDD_REF
VDD_48
XTAL_IN
XTAL_OUT
FSA/USB_48
FSB/TEST_MODE
FSC/TEST_SEL
PCI5
PCI4
PCI3
PCI2
PCIF1
PCIF0/ITP_EN
SCLOCK
SDATA
IREF
VSS_48
VSS_SRC
VSS_PCI0
VSS_CPU
VSS_REF
VSS_PCI1
ICS954201BG_TSSOP56~D
R1106
2.2_0603_5%~D
1 2
CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#
VTT_PWRGD#/PD
1
C91
0.047U_0402_10V7K~D
2
1
C995
0.047U_0402_10V7K~D
2
CK_VDD_A
VDD_A
VSS_A
PCI_STOP#
CPU_STOP#
CPU1
CPU1#
CPU0
CPU0#
SRC6
SRC6#
SRC5
SRC5#
SRC4
SRC4#
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
SRC0
SRC0#
DOT96
DOT96#
2
1
C87
0.047U_0402_10V7K~D
2
37
38
H_STP_PCI#
55
H_STP_CPU#
54
CK_CPU1
41
40
44
43
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
14
15
10
52
REF
1 2
R85 33_0402_5%~D
CK_CPU1#
1 2
R82 33_0402_5%~D
CK_CPU0
1 2
R78 33_0402_5%~D
CK_CPU0#
1 2
R71 33_0402_5%~D
CK_CPU2 CK_ITP
1 2
R1259 33_0402_5%~D
CK_CPU2#
1 2
R1260 33_0402_5%~D
SCR5
1 2
R1040 33_0402_5%~D
SRC5#
1 2
R1041 33_0402_5%~D
SRC4
1 2
R138 33_0402_5%~D
SRC4#
1 2
R143 33_0402_5%~D
SRC3
1 2
R60 33_0402_5%~D
SRC3# CLK _PCIE_VGA#
1 2
R148 33_0402_5%~D
SRC1
1 2
R64 33_0402_5%~D
SRC1#
1 2
R63 33_0402_5%~D
SRC0
1 2
R165 33_0402_5%~D
SRC0#
1 2
R166 33_0402_5%~D
CLK_ENABLE#
CLKREF
1 2
R99 12.1_0402_1%~D
1 2
R98 12.1_0402_1%~D
1 2
R551 12.1_0402_1%~D
2
1
C85
0.047U_0402_10V7K~D
2
Place near each pin
W>40 mil
Place near CK410
H_STP_PCI# <22>
H_STP_CPU# <22,49>
CLK_MCH_BCLK
CLK_MCH_BCLK#
CK_BCLK
CK_BCLK#
CK_ITP#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_VGA
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CK_14M_ICH
CK_14M_SIO
CK_14M_CODEC
1
CLK_MCH_BCLK
CLK_MCH_BCLK#
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
CK_BCLK <7>
CK_BCLK# <7>
CK_ITP <7>
CK_ITP# <7>
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>
CLK_PCIE_LOM <29>
CLK_PCIE_LOM# <29>
CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_ENABLE# <49>
CK_14M_ICH <22>
CK_14M_SIO <36>
CK_14M_CODEC <25>
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number R ev
Date: Sheet of
Clock Generator
Board Number LA2112
1
R92
49.9_0402_1%~D
R86
49.9_0402_1%~D
R84
49.9_0402_1%~D
R80
49.9_0402_1%~D
R1257
49.9_0402_1%~D
R1258
49.9_0402_1%~D
R146
1 2
49.9_0402_1%~D
R140
1 2
49.9_0402_1%~D
R153
1 2
49.9_0402_1%~D
R154
1 2
49.9_0402_1%~D
R156
1 2
49.9_0402_1%~D
R159
1 2
49.9_0402_1%~D
R114
1 2
49.9_0402_1%~D
R115
1 2
49.9_0402_1%~D
R1038
1 2
49.9_0402_1%~D
R1039
1 2
49.9_0402_1%~D
6 82Thursday, October 28, 2004
12
12
12
12
12
12
0.4
5
4
3
2
1
H_A#[3..31]<10>
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]<10>
H_ADSTB#0<10>
C C
R624
56_0402_5%~D
1 2
+VCCP
B B
H_ADSTB#1<10>
CK_BCLK<6>
CK_BCLK#<6>
H_ADS#<10>
H_BNR#<10>
H_BPRI#<10>
H_BR0#<10>
H_DEFER#<10>
H_DRDY#<10>
H_HIT#<10>
H_HITM#<10>
H_LOCK#<10>
H_RESET#<10>
H_RS#[0..2]<10>
H_TRDY#<10>
ITP_DBRESET#<42>
H_DBSY#<10>
H_DPSLP#<21>
H_DPRSTP#<21>
H_DPWR#<10>
H_PROCHOT#<37>
H_PWRGOOD<21>
H_CPUSLP#<10,21>
H_THERMDA<39>
H_THERMDC<39>
H_THERMTRIP#<39>
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CK_BCLK
CK_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
JCPUA
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
ADDR GROUP
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
U3
ADSTB0#
AE5
ADSTB1#
A16
ITP_CLK0
A15
ITP_CLK1
B15
BCLK0
B14
B11
C19
A10
B10
B17
A13
C12
A12
F23
C11
B13
B18
A18
C17
HOST CLK
BCLK1
N2
ADS#
L1
BNR#
J3
BPRI#
N4
BR0#
L4
DEFER#
H2
DRDY#
K3
HIT#
K4
CONTROL GROUP
HITM#
A4
IERR#
J2
LOCK#
RESET#
H1
RS0#
K1
RS1#
L2
RS2#
M3
TRDY#
C8
BPM0#
B8
BPM1#
A9
BPM2#
C9
BPM3#
A7
DBR#
M2
DBSY#
B7
DPSLP#
G1
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
E4
PWRGOOD
A6
SLP#
TCK
TDI
TDO
C5
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
TYCO_3-1674770-2_Dothan~D
Dothan
MISC
DATA GROUP
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
D25
J26
T24
AD20
C23
K24
W25
AE24
C22
L24
W24
AE25
C2
D3
A3
B5
D1
D4
C6
B4
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H _NMI
H_STPCLK#
H_SMI#
H_DINV#0 <10>
H_DINV#1 <10>
H_DINV#2 <10>
H_DINV#3 <10>
H_A20M# <21>
H_FERR# <21>
H_IGNNE# <21>
H_INIT# <21>
H_INTR <21>
H_NMI <21>
H_STPCLK# <21>
H_SMI# <21>
H_D#0H_A#3
A19
H_D#[0..63] <10>
H_RESET#
ITP_TDO
H_DSTBN#[0..3] <10>
H_DSTBP#[0..3] <10>
R1261
22.6_0603_1%~D
1 2
CK_ITP<6>
CK_ITP#<6>
1 2
R1262
22.6_0603_1%~D
+VCCP
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_RESET#
ITP_TCK
CK_ITP
CK_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
JITP
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
29
GND6
GND7
MOLEX_52435-2891_28P~D
30
@
+3VSUS
R743
150_0603_1%~D
1 2
+VCCP
R1263
54.9_0603_1%~D
1 2
R1160
54.9_0402_1%~D
1 2
+VCCP
R618
39.2_0603_1%~D
1 2
R619
150_0603_1%~D
1 2
R615
680_0402_5%~D
1 2
R617
27.4_0603_1%~D
1 2
+VCCP
1
C914
0.1U_0402_10V6K~D
2
Place near JITP
ITP_DBRESET#
ITP_TDO
@
H_RESET#
ITP_TMS
ITP_TDI
This shall place near CPU
ITP_TRST#
ITP_TCK
A A
5
TEST1
R1120
1K_0402_5%~D@
1 2
+VCCP
+VCCP
R12
56_0402_5%~D
H_THERMTRIP#
1 2
R17
200_0402_5%~D
H_PWRGOOD
1 2
4
Add pullups for PWRGOOD and THERMTRIP per INTEL
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DELL CONFIDENTIAL/PROPRIETARY
Title
Dothan Processor in mFCPGA479
Size Document Number R ev
Board Number LA2112
2
Date: Sheet of
7 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
+VCC_CORE
AC26
AD26
AE7
AF6
F26
P23
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
L21
M22
N21
P22
R21
T22
U21
D18
D20
D22
E17
E19
E21
F18
C16
C14
P25
P26
AB2
AB1
E26
AF7
AC1
B1
N1
W4
K6
L5
M6
N5
P6
R5
T6
D6
D8
E5
E7
E9
F6
F8
E1
E2
F2
F3
G3
G4
H4
B2
C3
JCPUB
VCCSENSE
VSSSENSE
VCCA0
VCCA1
VCCA2
VCCA3
VCCQ0
VCCQ1
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
GTLREF
BSEL0
BSEL1
COMP0
COMP1
COMP2
COMP3
RSVD
RSVD
RSVD
RSVD
RSVD
A2
VSS
A5
VSS
A8
VSS
A11
VSS
A14
VSS
A17
VSS
A20
VSS
A23
VSS
A26
VSS
B3
VSS
B6
VSS
B9
VSS
B12
Dothan
TYCO_3-1674770-2_Dothan~D
VSS
B16
VSS
B19
VSS
B22
VSS
B25
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C13
VSS
C15
VSS
C18
VSS
C21
VSS
C24
VSS
D2
VSS
D5
VSS
D7
VSS
D9
VSS
D11
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E10
VSS
E12
VSS
E14
VSS
E16
VSS
E18
VSS
E20
VSS
E22
VSS
POWER, GROUNG, RESERVED SIGNALS AND NC
E25
VSS
F1
VSS
F4
VSS
F5
VSS
F7
VSS
F9
VSS
F11
VSS
F13
VSS
F15
VSS
F17
VSS
F19
VSS
F21
VSS
F24
VSS
G2
VSS
G6
VSS
G22
VSS
G23
VSS
G26
VSS
H3
VSS
H5
VSS
H21
VSS
H25
VSS
J1
VSS
J4
VSS
J6
VSS
J22
VSS
J24
VSS
K2
VSS
K5
VSS
K21
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L22
VSS
L25
VSS
M1
VSS
Dothan-A2 w/ 533Mhz supports both 1.5V and 1.8V.
Dothan-B step w/533Mhz supports only 1.5V
+1.8VRUN
2 1
D D
+1.5VRUN
B_VID1
OPEN~D
12
R646
54.9_0402_1%~D
2 1
12
27.4_0402_1%~D
+VCCP
For test only ,Cmos output
CPU Voltage ID
VID0
VID1
VID2
VID3
VID4
VID5
C C
B B
Layout close CPU
V_CPU_GTLREF
RN9
10K_1206_8P4R_5%~D@
B_VID6
OPEN~D
2
2
1
1
+VCCP
2
2
1
1
OPEN OPEN OPEN OPEN OPEN OPEN
R_A
12
R50
1K_0603_1%~D
R_B
12
R51
2K_0603_1%~D
4 5
B_VID4
OPEN~D
12
12
1 8
2 7
3 6
2
2
1
1
R333
B_VID3
OPEN~D
10K_0402_5%~D@
10K_0402_5%~D@
R746
B_VID2
OPEN~D
2
2
1
1
12
R644
27.4_0402_1%~D
R645
2
2
1
1
OPEN
PJP17
PAD-OPEN 2x2m~D
PJP16
PAD-OPEN 2x2m~D
SHORT
VID0 <49>
VID1 <49>
VID2 <49>
VID3 <49>
VID4 <49>
VID5 <49>
B_VID5
OPEN~D
2
2
1
1
12
R647
54.9_0402_1%~D
+1.8VS_PROC
1
1
C997
C998
2
2
10U_0805_6.3V6M~D
0.01U_0402_16V7K~D
H_PSI#<49>
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
54.9_0603_1%~D@
54.9_0603_1%~D@
+VCC_CORE
V_CPU_GTLREF
CPU_BSEL0<6>
CPU_BSEL1<6>
R634
1 2
1 2
R635
+VCCP
VCCSENSE
VSSSENSE
H_PSI#
VID0
VID1
VID2
VID3
VID4
VID5
CPU_BSEL0
CPU_BSEL1
COMP0
COMP1
COMP2
COMP3
AA11
AA13
AA15
AA17
AA19
AA21
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC11
AC13
AC15
AC17
AC19
AD10
AD12
AD14
AD16
AD18
AE11
AE13
AE15
AE17
AE19
AF10
AF12
AF14
AF16
AF18
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AB6
AB8
AC9
AD8
AE9
AF8
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
JCPUC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
POWER, GROUND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Dothan
TYCO_3-1674770-2_Dothan~D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Dothan Processor in mFCPGA479
Size Document Number R ev
Board Number LA2112
Date: Sheet of
8 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
+VCC_CORE
1
C415
10U_0805_4VAM~D
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C403
10U_0805_4VAM~D
C404
10U_0805_4VAM~D
C376
10U_0805_4VAM~D
D D
C C
1
C386
10U_0805_4VAM~D
2
1
C418
10U_0805_4VAM~D
2
1
C440
10U_0805_4VAM~D
2
1
C414
10U_0805_4VAM~D
2
1
C412
10U_0805_4VAM~D
2
1
C413
10U_0805_4VAM~D
2
1
C396
10U_0805_4VAM~D
2
1
C445
10U_0805_4VAM~D
2
1
C406
10U_0805_4VAM~D
2
1
C378
10U_0805_4VAM~D
2
1
C387
10U_0805_4VAM~D
2
1
C398
10U_0805_4VAM~D
2
1
C395
10U_0805_4VAM~D
2
1
C405
10U_0805_4VAM~D
2
1
C439
10U_0805_4VAM~D
2
1
C444
10U_0805_4VAM~D
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C925
10U_0805_4VAM~D
C427
10U_0805_4VAM~D
C441
10U_0805_4VAM~D
1
C926
10U_0805_4VAM~D
2
1
C379
10U_0805_4VAM~D
2
1
C394
10U_0805_4VAM~D
2
10uF 0805 X6S -> 105 degree
1
C927
10U_0805_4VAM~D
2
1
C373
10U_0805_4VAM~D
2
1
C372
10U_0805_4VAM~D
2
1
C928
10U_0805_4VAM~D
2
1
C438
10U_0805_4VAM~D
2
1
C374
10U_0805_4VAM~D
2
High Frequence Decoupling
1
C929
10U_0805_4VAM~D
2
1
C377
10U_0805_4VAM~D
2
1
C426
10U_0805_4VAM~D
2
Near VCORE regulator.
+VCC_CORE
1
1
+
C942
2
1
+
C731
150U_D2_4VK~D
2
+
2
330U_D_2VM~D
9mOhm
7343
PS CAP
C943
330U_D_2VM~D
B B
A A
C941
@
330U_D_2VM~D
9mOhm
7343
PS CAP
+VCCP
1
+
2
@
9mOhm
7343
PS CAP
1
C732
0.1U_0402_10V6K~D
2
1
+
C944
2
330U_D_2VM~D
ESR <= 3m ohm
Capacitor > 880uF
1
C733
0.1U_0402_10V6K~D
2
1
C734
0.1U_0402_10V6K~D
2
1
C735
0.1U_0402_10V6K~D
2
1
C736
0.1U_0402_10V6K~D
2
1
C737
0.1U_0402_10V6K~D
2
1
C738
0.1U_0402_10V6K~D
2
1
C739
0.1U_0402_10V6K~D
2
1
C740
0.1U_0402_10V6K~D
2
1
C741
0.1U_0402_10V6K~D
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
CPU Bypass
Size Document Number R ev
Board Number LA2112
Date: Sheet of
9 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
DMI_TXN0
DMI_TXN0<22>
DMI_TXN1
DMI_TXN1<22>
D D
C C
Layout Guide will show
these signals routed
differentially.
B B
A A
H_A#[3..31]<7>
H_REQ#[0..4]<7>
H_ADSTB#0<7>
H_ADSTB#1<7>
CLK_MCH_BCLK#<6>
CLK_MCH_BCLK<6>
H_DSTBN#[0..3]<7>
H_DSTBP#[0..3]<7>
H_DINV#0<7>
H_DINV#1<7>
H_DINV#2<7>
H_DINV#3<7>
H_RESET#<7>
H_ADS#<7>
H_TRDY#<7>
H_DPWR#<7>
H_DRDY#<7>
H_DEFER#<7>
H_HITM#<7>
H_HIT#<7>
H_LOCK#<7>
H_BR0#<7>
H_BNR#<7>
H_BPRI#<7>
H_DBSY#<7>
H_RS#[0..2]<7>
H_CPUSLP#<7, 21>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_R_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP# H_R_CPUSLP#
Note:
"Do not install R10 for Dothan-A,
Install R10 for Dothan-B"
U68A
G9
HA3#
C9
HA4#
E9
HA5#
B7
HA6#
A10
HA7#
F9
HA8#
D8
HA9#
B10
HA10#
E10
HA11#
G10
HA12#
D9
HA13#
E11
HA14#
F10
HA15#
G11
HA16#
G13
HA17#
C10
HA18#
C11
HA19#
D11
HA20#
C12
HA21#
B13
HA22#
A12
HA23#
F12
HA24#
G12
HA25#
E12
HA26#
C13
HA27#
B11
HA28#
D13
HA29#
A13
HA30#
F13
HA31#
A11
HPCREQ#
A7
HREQ#0
D7
HREQ#1
B8
HREQ#2
C7
HREQ#3
A8
HREQ#4
B9
HADSTB#0
E13
HADSTB#1
AB1
HCLKN
AB2
HCLKP
G4
HDSTBN#0
K1
HDSTBN#1
R3
HDSTBN#2
V3
HDSTBN#3
G5
HDSTBP#0
K2
HDSTBP#1
R2
HDSTBP#2
W4
HDSTBP#3
H8
HDINV#0
K3
HDINV#1
T7
HDINV#2
U5
HDINV#3
H10
HCPURST#
F8
HADS#
B5
HTRDY#
G6
HDPWR#
F7
HDRDY#
E6
HDEFER#
F6
HEDRDY#
D6
HHITM#
D4
HHIT#
B3
HLOCK#
E7
HBREQ0#
A5
HBNR#
D5
HBPRI#
C6
HDBSY#
G8
HCPUSLP#
A4
HRS0#
C5
HRS1#
B4
HRS2#
ALVISO-915PM-B0_BGA1257~D
R10
0_0402_5%~D
1 2
Alviso
HOST
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
H_D#0
E4
H_D#1
E1
H_D#2
F4
H_D#3
H7
H_D#4
E2
H_D#5
F1
H_D#6
E3
H_D#7
D3
H_D#8
K7
H_D#9
F2
H_D#10
J7
H_D#11
J8
H_D#12
H6
H_D#13
F3
H_D#14
K8
H_D#15
H5
H_D#16
H1
H_D#17
H2
H_D#18
K5
H_D#19
K6
H_D#20
J4
H_D#21
G3
H_D#22
H3
H_D#23
J1
H_D#24
L5
H_D#25
K4
H_D#26
J5
H_D#27
P7
H_D#28
L7
H_D#29
J3
H_D#30
P5
H_D#31
L3
H_D#32
U7
H_D#33
V6
H_D#34
R6
H_D#35
R5
H_D#36
P3
H_D#37
T8
H_D#38
R7
H_D#39
R8
H_D#40
U8
H_D#41
R4
H_D#42
T4
H_D#43
T5
H_D#44
R1
H_D#45
T3
H_D#46
V8
H_D#47
U6
H_D#48
W6
H_D#49
U3
H_D#50
V5
H_D#51
W8
H_D#52
W7
H_D#53
U2
H_D#54
U1
H_D#55
Y5
H_D#56
Y2
H_D#57
V4
H_D#58
Y7
H_D#59
W1
H_D#60
W3
H_D#61
Y3
H_D#62
Y6
H_D#63
W2
H_VREF
J11
H_XRCOMP
C1
H_XSCOMP
C2
H_YRCOMP
T1
H_YSCOMP
L1
H_SWNG0
D1
H_SWNG1
P1
12
R13
24.9_0603_1%~D
H_D#[0..63] <7>
H_SWNG1
C743
H_SWNG0
C744
0.1U_0402_16V4Z~D
+VCCP
12
R660
54.9_0603_1%~D
12
R11
24.9_0603_1%~D
+VCCP
R649
221_0603_1%~D
1
R650
2
100_0603_1%~D
0.1U_0402_16V4Z~D
+VCCP
R652
221_0603_1%~D
1
R653
2
100_0603_1%~D
12
R661
54.9_0603_1%~D
C745
12
12
12
12
+VCCP
R656
100_0402_1%~D
1
R657
2
200_0402_1%~D
0.1U_0402_10V6K~D
Layout Guide
will show these
signals routed
differentially.
+1.8VSUS
12
12
12
Layout Note:
Rote as short
as possible
M_CLK_DDR0<16>
M_CLK_DDR1<16>
M_CLK_DDR3<17>
M_CLK_DDR4<17>
M_CLK_DDR#0<16>
M_CLK_DDR#1<16>
M_CLK_DDR#3<17>
M_CLK_DDR#4<17>
DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>
DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<16,17>
R8 80.6_0603_1%~D
1 2
V_DDR_MCH_REF<16,17,48>
R9
80.6_0603_1%~D
12
12
R699
R648
40.2_0603_1%~D
40.2_0603_1%~D
DMI_TXN2<22>
DMI_TXN3<22>
DMI_TXP0<22>
DMI_TXP1<22>
DMI_TXP2<22>
DMI_TXP3<22>
DMI_RXN0<22>
DMI_RXN1<22>
DMI_RXN2<22>
DMI_RXN3<22>
DMI_RXP0<22>
DMI_RXP1<22>
DMI_RXP2<22>
DMI_RXP3<22>
M_OCDOCMP0
M_OCDOCMP1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
M_ODT0<16>
M_ODT1<16,17>
M_ODT2<17>
M_ODT3<17>
C753
0.1U_0402_16V4Z~D
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR3
M_CLK_DDR4
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#3
M_CLK_DDR#4
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
1
2
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMR COMPN
SMRCOMPP
1
C752
2
0.1U_0402_16V4Z~D
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
DMIDDR MUXING
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO-915PM-B0_BGA1257~D
U68B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
CFG/RSVD
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN
CLK
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC
NC10
NC11
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
D37
C37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
PM_EXTTS#0
PM_EXTTS#1
CFG0
MCH_CLKSEL1
MCH_CLKSEL0
CFG5
CFG6
CFG7
CFG9
CFG12
CFG13
CFG16
CFG18
CFG19
THERMTRIP_MCH#
PM_EXTTS#0
PM_EXTTS#1
THERMTRIP_MCH#
IMVP_PWRGD
PLTRST_R#
+1.5VRUN
R898
10K_0402_5%~D
R899
10K_0402_5%~D
CFG0 <12>
MCH_CLKSEL1 <6>
MCH_CLKSEL0 <6>
CFG5 <12>
CFG6 <12>
CFG7 <12>
CFG9 <12>
CFG12 <12>
CFG13 <12>
CFG16 <12>
CFG18 <12>
CFG19 <12>
R1113
56_0402_5%~D
1 2
PM_BMBUSY# <22>
THERMTRIP_MCH# <39>
IMVP_PWRGD <22,42,49>
1 2
R1030 100_0603_1%~D
+2.5VRUN
12
12
+VCCP
PLTRST_MCH# <20>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Alviso(1 of 5)
Size Document Number R ev
Board Number LA2112
Date: Sheet of
10 82Thursday, October 28, 2004
1
0.4
5
D D
4
3
2
1
DDR_A_BS#0<16>
DDR_A_BS#1<16>
DDR_A_BS#2<16>
DDR_A_DM[0..7]<16>
DDR_A_DQS[0..7]<16>
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
C C
B B
DDR_A_DQS#[0..7]<16>
DDR_A_MA[0..13]<16>
DDR_A_CAS#<16,17>
DDR_A_RAS#<16>
DDR_A_WE#<16>
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
DDR_A_WE#
U68C
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
AK35
SA_DQS0#
AP34
SA_DQS1#
AN30
SA_DQS2#
AN23
SA_DQS3#
AN8
SA_DQS4#
AM5
SA_DQS5#
AH1
SA_DQS6#
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
AM18
SA_MA5
AL19
SA_MA6
AP20
SA_MA7
AM19
SA_MA8
AL20
SA_MA9
AM16
SA_MA10
AN20
SA_MA11
AM20
SA_MA12
AM15
SA_MA13
AN15
SA_CAS#
AP16
SA_RAS#
AF29
SA_RCVENIN#
AF28
SA_RCVENOUT#
AP15
SA_WE#
ALVISO-915PM-B0_BGA1257~D
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
DDR MEMORY SYSTEM A
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
DDR_B_BS#0<17>
DDR_B_BS#1<17>
DDR_B_BS#2<17>
DDR_B_DM[0..7]<17>
DDR_B_DQS[0..7]<17>
DDR_B_DQS#[0..7]<17>
DDR_B_MA[0..13]<17>
DDR_B_CAS#<17>
DDR_B_RAS#<17>
DDR_B_WE#<16,17>
DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
DDR_B_WE#
U68D
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SB_DM0
AK34
SB_DM1
AK27
SB_DM2
AK24
SB_DM3
AJ10
SB_DM4
AK5
SB_DM5
AE7
SB_DM6
AB7
SB_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
AF35
SB_DQS0#
AK33
SB_DQS1#
AK28
SB_DQS2#
AJ23
SB_DQS3#
AL10
SB_DQS4#
AH7
SB_DQS5#
AF7
SB_DQS6#
AB5
SB_DQS7#
AH17
SB_MA0
AK17
SB_MA1
AH18
SB_MA2
AJ18
SB_MA3
AK18
SB_MA4
AJ19
SB_MA5
AK19
SB_MA6
AH19
SB_MA7
AJ20
SB_MA8
AH20
SB_MA9
AJ16
SB_MA10
AG18
SB_MA11
AG20
SB_MA12
AG15
SB_MA13
AH14
SB_CAS#
AK14
SB_RAS#
AF15
SB_RCVENIN#
AF14
SB_RCVENOUT#
AH16
SB_WE#
ALVISO-915PM-B0_BGA1257~D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
DDR SYSTEM MEMORY B
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR_B_D0
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <17>DDR_A_D[0..63] <16>
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Alviso(2 of 5)
Size Document Number R ev
Board Number LA2112
Date: Sheet of
11 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
CLK_MCH_3GPLL#<6>
D D
C C
B B
CLK_MCH_3GPLL<6>
+VCCP
AB29
AC29
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO-915PM-B0_BGA1257~D
MISC
TVVGALVDS
U68G
D36
EXP_COMPI
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
EXP_ICOMPO
PCI - EXPRESS GRAPHICS
PEGCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
24.9_0603_1%~D
1 2
PEG_RXN[0..15]
PEG_RXP[0..15]
PEG_TXN[0..15]
PEG_TXP[0..15]
R44
+1.5VRUN_PCIE
PEG_RXN[0..15] <18>
PEG_RXP[0..15] <18>
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
PEG_TXN[0..15] <18>
PEG_TXP[0..15] <18>
CFG[2:0]
CFG5
CFG6
CFG7
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
Refer to sheet 6 for FSB
frequency select
Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I
*
*
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
*
Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V
*
*
Low = 1.05V (Default)
High = 1.2V
+VCCP
R20 10K_0402_5%~D
CFG0<10>
R52 2.2K_0402_5%~D@
CFG5<10>
R55 2.2K_0402_5%~D
CFG6<10>
R56 2.2K_0402_5%~D@
CFG7<10>
R74 2.2K_0402_5%~D@
CFG9<10>
R906 2.2K_0402_5%~D@
CFG12<10>
R907 2.2K_0402_5%~D@
CFG13<10>
R97 2.2K_0402_5%~D@
*
CFG16<10>
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CFG[17:3] have internal pull-up
*
+2.5VRUN
R118 1K_0402_5%~D@
CFG18<10>
CFG19<10>
*
1 2
1 2
R125 1K_0402_5%~D@
CFG[19:18] have internal pull-down
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Alviso(3 of 5)
Size Document Number R ev
Board Number LA2112
Date: Sheet of
12 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
POWER
VTT8
N11
VTT9
M11
D D
+VCCP
1
C805
C1023
2
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
1
C810
C C
2
0.47U_0603_16V7K~D
1
1
C808
2
2
0.47U_0603_16V7K~D
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
1
Y9
W9
U9
2
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1
1
C807
C806
2
0.22U_0603_10V7K~D
0.22U_0603_10V7K~D
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
ALVISO-915PM-B0_BGA1257~D
U68F
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
Note : All VCCSM pin
shorted internally.
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
1
1
C811
C812
2
2
10U_0805_4VAM~D
10U_0805_4VAM~D
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
1
2
1
2
+1.8VSUS
C98
330U_D2E_2.5VM~D@
1
2
W=20 mils
C30
0.1U_0402_10V6K~D
C45
0.1U_0402_10V6K~D
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17
AC1
AC2
B23
C35
AA1
AA2
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
POWER
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
ALVISO-915PM-B0_BGA1257~D
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCDQ_TVDAC
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
+VCCP
1
1
C20
2
2
C1219
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
1
1
C37
C38
2
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
+
+1.5VRUN
+1.5VRUN_HPLL
+1.5VRUN_MPLL
Remove L6, C48, C51, Connect DPLLB directly to +1.5vrun
Remove L29, C47, C8, Connect DPLLA directly to +1.5vrun
Steven-01/09/2004
U68E
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCHV0
VCCHV1
VCCHV2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
F17
E17
D18
C18
F18
E18
H18
G18
D19
H17
B26
B25
A25
A35
B22
B21
A21
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
H20
F19
E19
G19
+2.5VRUN
1
C71
2
0.1U_0402_16V4Z~D
+VCCP
1
+
C1186
2
100U_D_6.3VM~D
+1.5VRUN
1
Close B26,B25,A25
C1266
10U_0805_4VAM~D
@
2
1
+
C62
C1021
2
220U_D2_4VM_R45~D
1
1
C1022
2
2
10U_0805_4VAM~D
10U_0805_4VAM~D
C364
0.1U_0402_16V4Z~D
BLM18PG181SN1_0603~D
BLM21PG300SN1_0805~D
R89
3GRLL_R
BLM18PG181SN1_0603~D
1
C359
2
10U_0805_4VAM~D
0.5_0805_1%~D
1 2
1
2
1
2
Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.
L43
12
L146
12
+1.5VRUN+1.5VRUN_3GPLL
12
L147
C362
0.1U_0402_16V4Z~D
+2.5VRUN
C367
0.1U_0402_16V4Z~D
+1.5VRUN+1.5VRUN_PCIE
C77
1
0.1U_0402_16V4Z~D
2
1
C370
0.1U_0402_16V4Z~D
2
@
1
2
+1.5VRUN+1.5VRUN_DDRDLL
1
C76
2
0.1U_0402_16V4Z~D
B B
1
2
0.1U_0402_16V4Z~D
+2.5VRUN
C287
10U_0805_4VAM~D@
1
1
C783
2
2
0.01U_0402_16V7K~D
@
1
C288
C327
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
10U_0805_4VAM~D
C1264
1
1
2
2
C1265
4.7U_0805_6.3V6K~D@
+VCCP
BLM21PG300SN1_0805~D
+1.5VRUN
A A
12
1
+
C1008
C1007
2
150U_D2_2VM_R15~D
1
2
0.1U_0402_16V4Z~D
+1.5VRUN
+1.5VRUN_HPLL
L7
L9
BLM21PG300SN1_0805~D
+1.5VRUN_MPLL
12
1
+
C1009
C1010
2
150U_D2_2VM_R15~D
1
2
0.1U_0402_16V4Z~D
C1005
10U_0805_4VAM~D
1
C1006
2
10U_0805_4VAM~D
W=20 mils
1
1
C81
2
2
10U_0805_4VAM~D
1
C80
2
0.1U_0402_16V4Z~D
1
C113
C112
2
0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Alviso(4 of 5)
Size Document Number R ev
Board Number LA2112
Date: Sheet of
13 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
+VCCP
D D
C C
B B
A A
AA12
AA13
AA14
AB14
AA15
AB15
AA16
AB16
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
AA21
AB21
AA22
AB22
AA23
AB23
AA24
AB24
AA25
AB25
AA26
AB26
M12
W12
M13
W13
M14
W14
M15
W15
M16
W16
W25
M26
W26
L12
N12
P12
R12
T12
U12
V12
L13
N13
P13
R13
T13
U13
V13
Y12
Y13
L14
N14
P14
R14
T14
U14
V14
Y14
L15
N15
P15
R15
T15
U15
V15
Y15
L16
N16
P16
R16
T16
U16
V16
Y16
R17
Y17
R21
Y21
Y22
Y23
Y24
Y25
Y26
V25
L26
N26
P26
R26
T26
U26
V26
5
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
ALVISO-915PM-B0_BGA1257~D
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
NCTF
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
U68H
+1.8VSUS
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
+VCCP
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
U68J
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
AA10
Y1
VSS271
D2
VSS270
G2
VSS269
J2
VSS268
L2
VSS260
P2
VSS259
T2
VSS258
V2
VSS257
AD2
VSS256
AE2
VSS255
AH2
VSS254
AL2
VSS253
AN2
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS
ALVISO-915PM-B0_BGA1257~D
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
F11
H11
Y11
VSSALVDS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
U68I
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
AL24
AN24
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
W28
AA28
AB28
AC28
W29
AA29
AD29
AG29
AJ29
AM29
AA30
AB30
AC30
AE30
AP30
M31
W31
AD31
AG31
AL31
AA32
AB32
VSS267
VSS266
A26
VSS265
E26
VSS264
G26
VSS263
J26
VSS262
B27
VSS261
E27
VSS129
G27
VSS128
VSS127
VSS126
VSS125
VSS
VSS124
VSS123
VSS122
VSS121
VSS120
E28
VSS119
VSS118
VSS117
VSS116
VSS115
A29
VSS114
D29
VSS113
E29
VSS112
F29
VSS111
G29
VSS110
H29
VSS109
L29
VSS108
P29
VSS107
U29
VSS106
V29
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
C30
VSS98
Y30
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
D31
VSS91
E31
VSS90
F31
VSS89
G31
VSS88
H31
VSS87
J31
VSS86
K31
VSS85
L31
VSS84
VSS83
N31
VSS82
P31
VSS81
R31
VSS80
T31
VSS79
U31
VSS78
V31
VSS77
VSS76
VSS75
VSS74
VSS73
A32
VSS72
C32
VSS71
Y32
VSS70
VSS69
VSS68
ALVISO-915PM-B0_BGA1257~D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Alviso(5 of 5)
Size Document Number R ev
Board Number LA2112
Date: Sheet of
14 82Thursday, October 28, 2004
1
0.4
5
FAN1 Control and Tachometer
+15V
R130
D D
FAN1_PWM<37>
100K_0402_5%~D
1 2
1
C128
2
1U_0805_10V6K~D
R128
FAN1VREF
FAN1_VFB
1 2
150K_0402_5%~D
8
5
P
IN+
6
IN-
G
4
C127
2200P_0603_50V7K~D
1 2
R129
100K_0402_5%~D
12
RB751V_SOD323~D
U49B
LM358M_SO8~D
7
O
1
C121
2
FAN1_ON
D9
4
0.1U_0603_50V4Z~D
G
3
2 1
+5VRUN
6
2
1
D
Q15
S
SI3456DV-T1_TSOP6~D
4 5
C476
1000P_0603_50V7K~D
FAN1_VOUT
1
+
C479
2
47U_D_16VM_R70~D
+5VRUN
1
2
1
2
C1242
@
1000P_0402_50V7K~D
R110
1 2
10K_0402_5%~D@
R109
1K_0402_5%~D@
1 2
FAN1_TACH_FB
PMBT2222_SOT23~D@
FAN1TACH_ON
JFAN1
1
1
2
2
3
3
MOLEX_53398-0371~D
FAN1
3
Q11
2
+3VRUN
12
R117
10K_0402_5%~D
3 1
1 2
R1074
0_0402_5%~D
FAN1_TACH <37>
2
C
B
E 3
2
2222 SYMBOL(SOT23-NEW)
1
1
C C
R437
100K_0402_5%~D
FAN2_PWM<37>
B B
A A
1 2
1
C478
2
1U_0805_10V6K~D
R435
FAN2VREF
FAN2_VFB
1 2
150K_0402_5%~D
3
2
2200P_0603_50V7K~D
1 2
100K_0402_5%~D
+15V
8
P
IN+
IN-
G
4
C110
R436
12
RB751V_SOD323~D
FAN2 Control and Tachometer
+5VRUN
6
2
1
U49A
LM358M_SO8~D
FAN2_ON
1
O
D10
G
3
2 1
D
Q17
S
SI3456DV-T1_TSOP6~D
4 5
1
1
+
C495
2
2
47U_D_16VM_R70~D
C472
@
+5VRUN
R163
10K_0402_5%~D@
1 2
1
2
1000P_0603_50V7K~D
C1243
1000P_0402_50V7K~D
R168
1K_0402_5%~D@
1 2
FAN2_5V
FAN2_TACH_FB
PMBT2222_SOT23~D@
FAN2TACH_ON
JFAN2
1
1
2
2
3
3
MOLEX_53398-0371~D
FAN2
Q18
2
+3VRUN
12
R174
10K_0402_5%~D
3 1
1 2
R1075
0_0402_5%~D
FAN2_TACH <37>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ITP Debug CONN. & FAN
Size Document Number R ev
Board Number LA2112
Date: Sheet of
15 82Thursday, October 28, 2004
1
0.4
5
4
3
2
1
DDR_A_DQS#[0..7]<11>
DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_MA[0..13]<11>
D D
+1.8VSUS
2.2U_0603_6.3V6K~D
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
C1045
1
2
0.1U_0402_16V4Z~D
1
2
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
1
2
B B
A A
C145
DDR_CS3_DIMMB#<10,17>
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C167
C118
DDR_B_WE#<11,17>
5
C1046
1
1
2
2
0.1U_0402_16V4Z~D
C1171
C1172
1
2
0.1U_0402_16V4Z~D
1
1
2
2
C1024
C138
DDR_A_MA5
DDR_A_MA8
56_0404_4P2R_5%~D
DDR_A_MA1
DDR_A_MA3
56_0404_4P2R_5%~D
DDR_A_RAS#
DDR_CS0_DIMMA#
56_0404_4P2R_5%~D
DDR_A_BS#0
DDR_A_MA10
56_0404_4P2R_5%~D
DDR_B_WE#
DDR_A_WE#
56_0404_4P2R_5%~D
DDR_CS1_DIMMA#
DDR_CS3_DIMMB#
56_0404_4P2R_5%~D
C1047
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0805_6.3V6K~D
1
2
C1173
1
2
0.1U_0402_16V4Z~D
1
2
C1025
RN62
1 4
2 3
RN44
1 4
2 3
RN59
1 4
2 3
RN43
1 4
2 3
RN58
1 4
2 3
RN81
2 3
1 4
2.2U_0603_6.3V6K~D
C1049
C1048
1
2
0.1U_0402_16V4Z~D
C1174
1
2
0.1U_0402_16V4Z~D
1
1
2
2
C1027
C1026
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
1
2
RN61
RN47
RN46
RN60
RN45
RN128
RN75
C1028
Layout Note:
Place near JDIM1
10P_0402_50V8J~D
1
C1169
@
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C1029
C1030
DDR_A_BS#2
14
DDR_CKE0_DIMMA
23
56_0404_4P2R_5%~D
DDR_A_MA7
14
DDR_A_MA6
23
56_0404_4P2R_5%~D
DDR_A_MA9
14
DDR_A_MA12
23
56_0404_4P2R_5%~D
DDR_A_MA4
14
DDR_A_MA2
23
56_0404_4P2R_5%~D
DDR_A_MA0
14
DDR_A_BS#1
23
56_0404_4P2R_5%~D
M_ODT0
14
DDR_A_MA13
23
56_0404_4P2R_5%~D
DDR_CKE1_DIMMA
14
DDR_A_MA11
23
56_0404_4P2R_5%~D
M_CLK_DDR0
M_CLK_DDR#0
0.1U_0402_16V4Z~D
1
2
C1031
4
0.1U_0402_16V4Z~D
1
2
C1032
M_CLK_DDR1
10P_0402_50V8J~D
1
C1170
@
2
M_CLK_DDR#1
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length Max=1.3"
DDR_CKE0_DIMMA<10>
DDR_A_BS#2<11>
DDR_A_BS#0<11>
DDR_A_WE#<11>
DDR_A_CAS#<11,17>
DDR_CS1_DIMMA#<10>
M_ODT1<10,17>
CK_SDATA<6,17>
CK_SCLK<6,17>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+3VRUN
CK_SDATA
CK_SCLK
+1.8VSUS +1.8VSUS
JDIM1
1
VREF
3
C1176
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
FOX_AS0A426-M2SN-7F~D
DIMMA
STANDARD
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
0.1U_0402_16V4Z~D
2.2U_0805_10V6K~D
C1175
1
1
2
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
V_DDR_MCH_REF
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
10K_0402_5%~D
10K_0402_5%~D
12
R134
V_DDR_MCH_REF <10,17,48>
C114
R119
12
0.1U_0402_16V4Z~D
4.7U_0805_6.3V6K~D
C1168
1
2
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_CKE1_DIMMA <10>
DDR_A_BS#1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
1
2
DELL CONFIDENTIAL/PROPRIETARY
Title
DDRII-SODIMM SLOT1
Size Document Number R ev
Board Number LA2112
Date: Sheet of
16 82Thursday, October 28, 2004
1
0.4
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