Compal LA-2111 Schematic

5

D D

4

3

2

1

LAGUNA

REV : X00

C C

@ : Depop Component

PRELIMINARY

B B

Dothan Schematic with Capture CIS and Function field

uFCPGA Dothan

A A

02-07-2004

REV: 0.3

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Cover Sheet

Board Number LA2111

161Monday, February 09, 2004

1

of

0.3

5

Compal confidential

4

3

2

1

Block Diagram

D D

GUARDIAN
EMC6N300

page 39

Dothan

uFCPGA CPU

page 7,8,9

Fan Control

HA#(3..31)

CRT CONN.

& TV-OUT

VGA

page 19

Board

PCI-E 16X

VGA CONN.

C C

page 18

System Bus

400 / 533MHz

Alviso

GMCH-M

1257 FC-BGA

HD#(0..63)

page
10,11,12
13,14

Memory
BUS(DDR2)

1.8V 400 / 533MHz

SO-DIMM X2

BANK 0, 1, 2, 3

page16,17

Clock Generator

page 15

CK410M

page 6

DMI

DOCKING
PORT

PAGE 35

DOCKING
BUFFER

PAGE 34

USB

IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)

B B

CardBus Controller

PCI6515

Smart card

page31

3.3V 33MHz

page 31,32

Slot 0

page32

MINI PCI

page 33

LAN
BCM5751M

Analog Switch

Transformer

RJ45

page 30

page 30

page 30

PCI BUS

PCI-E BUS

LPC BUS

3.3V 33MHz

Macallen III

X BUS

A A

5

SST39VF080

page 38

4

COM

page 28

Touch Pad

page 38

1.5V
100MHz

LPC to X-BUS
& Super I/O

page
36,37

ICH6

3.3V 24.576MHz

609 BGA

page
20,21,22,23

ATA100 and SATA

SATA

Marvell
SATA to PATA

page 52

PATA

CDROM
USB

FDD
SATA HDD

page 24

48MHz / 480Mb

Int.KBD

FIR (LED/B)

page 38

page 40

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USB2.0

page 27

HDD

USB

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

page 52

FDD
DOCK
BT
Card BUS
JUSB1 U
JUSB1 D
JUSB2 U
JUSB2 D

AC-LINK

MDC

page 28

AC97
Codec

STAC9751

page 25page 29

AMP& Phone
Jack

page 26

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Block Diagram

Board Number LA2111

DC IN

BATT
IN

1.8V / 0.9V

page
44

page
45

page
44

1.5V/1.05V(+VCCP)

page 47

VCORE

page 49

5V/3.3V/15V

page 46

CHARGER

1

page
50,51

261Monday, February 09, 2004

of

0.3

5

D D

4

3

2

1

PM TABLE

C C

power
plane

State

S0

S1

S3

S5 S4/AC

B B

S5 S4/AC don't exist

+3VALW
+5VALW

ON

ON

ON

ON

+3VSUS
+5VSUS
+1.8VSUS
+1.5VSUS

ON ON

ON

ON

OFF

OFFOFF

+5VRUN
+3VRUN
+2.5VRUN
+1.8VRUN
+1.5VRUN
+VCC_CORE
+VCCP
+15V

+RTC_CELL

+0.9V_DDR_VTT

ON

OFF

OFF

OFF

PCI TABLE

PCI DEVICE

CARD BUS

DOCK

MINI PCI

IDSEL

AD17

AD24

AD19

REQ#/GNT#

1

0

3

PIRQ

D,C

A

D,B

USB TABLE

USB PORT#0DESTINATION

FDD (module bay)
1
2

MPCI (BlueTooth)

DOCK

3 NEW Connector
4

USB Port 1(Top)

USB Port 1(Bottom)5
6 USB Port 2(Top)
7 USB Port 2(Bottom)

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Index and Config.

Board Number LA2111

361Monday, February 09, 2004

1

of

0.3

5

4

3

2

1

D D

+5VALW

ADAPTER

PWR_SRC

BATTERY

C C

+5VSUS

SUS_ON

+3VALW

SUS_ON

+3VSRC

G_PWR_SRC

RUNPWROK

+VCC_CORE

+1.5VSUS

RUNPWROK

+VCCP

SUSPWROK_5V

+5RUN

+1.8VSUSP +0.9V_DDR_VTT

B B

+5VHDD +5VMOD +5VRUN VDDA

A A

RUN_ON

PL9

+15V +2.5VRUN

(Option)

AUDIO_AVDD_ON

+3VRUN

L10

RUN_ON

V3P3LAN

SUSPWROK_5V

+3VSUS

RUN_ON

RUN_ON SUSPWROK_5V

+1.5VRUN

PJP11,PJP12

+1.8VSUS

RUN_ON

+1.8VRUN

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Power Rail

Board Number LA2111

461Monday, February 09, 2004

1

of

0.3

5

4

3

2

1

+3VRUN

ICH_SMBCLK

D D

ICH6

ICH_SMBDATA

+3VSUS

7002

7002

CK_SCLK

CLK GEN.

CK_SDATA

DIMM0

Address 00 Address 10

DIMM1

7002

7002

LAN_SMBCLK

LOM

LAN_SMBDATA

7002

CLK_SMB
DAT_SMB

C C

+3VALW

GUARDIAN

V_3P3_LAN

7002

24C04

DOCK_SMB_CLK

SIO

DOCK_SMB_DAT

+5VALW

DOCKING

Macallen III

SBAT_SMBCLK
SBAT_SMBDAT

B B

+5VALW

2'nd
BATTERY

VGA

PBAT_SMBCLK

1'st

PBAT_SMBDAT +5VALW

A A

BATTERY

CHARGER

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

SMBUS TOPOLOGY

Board Number LA2111

561Monday, February 09, 2004

1

of

0.3

5

+3VRUN

ICH_SMBDATA<<22,33>>

D D

ICH_SMBCLK<<22,33>>

ICH_SMBDATA

+3VRUN

ICH_SMBCLK

D

1 3

1 3

D

D
1

3

G

S

2

2N7002

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

C C

0
0
0
1
1
1

00

1

0

0

1
11
0

0

0

1
0

1

1

11

MHz

266
133
200
166
333
100
400

SRC
MHz

100 33.30
100
100
100
100
100
100

RESERVED

R57

S

Q6
2N7002_SOT23~D

G

2

2

G

Q8
2N7002_SOT23~D

S

12

100K_0402_5%~D

CK_VDD_A

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

C1247

12

R61

100K_0402_5%~D

CK_SDATA

CK_SCLK

1

2

4.7U_0805_6.3V6K~D

Table : ICS 954201 / Cypress CY28411

+VCCP

B B

CLKSEL0

CPU_BSEL0<<8>>

A A

CPU_BSEL1<<8>>

1 2

R643
0_0402_5%~D@

CLKSEL1

1 2

R641

0_0402_5%~D@

5

+VCCP

R65
1K_0402_5%~D

@

1 2

1 2

R1070
1K_0402_5%~D

R66
0_0402_5%~D

1 2

R95
1K_0402_5%~D

@

1 2

1 2

R1073
1K_0402_5%~D

R90
0_0402_5%~D

1 2

Dothan-A 400MHz, Install R65, No pop. R66, R643
Dothan-A 533MHz, Install R66, No pop. R65, R643

MCH_CLKSEL0 <<10>>

MCH_CLKSEL1 <<10>>

1

2

C1248

0.047U_0402_16V7K~D

CK_48M_SCR<<31>>

CK_33M_CBPCI<<31>>

CK_33M_SIOPCI<<36>>

CK_33M_MINIPCI<<33>>

CK_33M_DOCKPCI<<34>>

CK_33M_ICHPCI<<20>>

4

CK_SDATA <<16,17>>

CK_SCLK <<16,17>>

CK_VDD_48

C1249

4.7U_0805_6.3V6K~D

33P_0402_50V8J~D

33P_0402_50V8J~D

CK_48M_ICH<<22>>

CK_33M_LOMPCI<<29>>

+3VRUN

R96
10K_0402_5%~D

1 2

CLKSEL2

R91
10K_0402_5%~D

@

1 2

4

1

1

2

2

C1251

C90

12

C93

12

CK_48M_SCR
CK_48M_ICH

CLKSEL1
CLKSEL0

CK_33M_CBPCI
CK_33M_SIOPCI
CK_33M_MINIPCI
CK_33M_DOCKPCI
CK_33M_ICHPCI

+3VRUN

1

C992

2

0.1U_0402_16V4Z~D

1 2

BLM21PG600SN1D_0805~D

CK_VDD_REF

0.047U_0402_16V7K~D

Place crystal within
500 mils of CK410

CK_XTAL_IN

X1

12

14.31818MHz_20P_1BX14318CC1A~D

+3VRUN

CK_XTAL_OUT

R59 33_0402_5%~D
R62 33_0402_5%~D

R81 33_0402_5%~D
R83 33_0402_5%~D
R68 33_0402_5%~D
R79 33_0402_5%~D
R88 33_0402_5%~D

1 2

PCICLK4

R1206
33_0402_5%~D

1 2

1 2

L33

BLM21PG600SN1D_0805~D

CK_VDD_MAIN2

L130

1

2

C1252

0.047U_0402_16V7K~D

1 2

1 2

12

CLKSEL2

12

12
12
12
12
12

R177

10K_0402_5%~D

PCICLKF0

1 2

R67 475_0402_1%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

CK_VDD_MAIN

CK_VDD_REF

R1107
1_0402_5%~D

CK_VDD_48

R1108

2.2_0402_5%~D

PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLKF1

CK_SCLK

CK_SDATA

CLKIREF

3

CK_VDD_MAIN

2

C89
10U_0805_6.3V6M~D

1

2

C993
10U_0805_6.3V6M~D

1

U8

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

VDD_CPU

48

VDD_REF

11

VDD_48

50

XTAL_IN

49

XTAL_OUT

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

5

PCI5

4

PCI4

3

PCI3

56

PCI2

9

PCIF1

8

PCIF0/ITP_EN

46

SCLOCK

47

SDATA

39

IREF

13

VSS_48

29

VSS_SRC

2

VSS_PCI0

45

VSS_CPU

51

VSS_REF

6

VSS_PCI1

CY28411ZCT_TSSOP56~D

1

C94

0.047U_0402_16V7K~D

2

1

C994

0.047U_0402_16V7K~D

2

R1106

2.2_0402_5%~D

1 2

CPU_2_ITP/SRC_7
CPU_2_ITP/SRC7#

VTT_PWRGD#/PD

1

C91

0.047U_0402_16V7K~D

2

1

C995

0.047U_0402_16V7K~D

2

CK_VDD_A

37

VDD_A

38

VSS_A

55

PCI_STOP#

54

CPU_STOP#

41

CPU1

40

CPU1#

44

CPU0

43

CPU0#

36
35

33

SRC6

32

SRC6#

31

SRC5

30

SRC5#

26

SRC4

27

SRC4#

24

SRC3

25

SRC3#

22

SRC2

23

SRC2#

19

SRC1

20

SRC1#

17

SRC0

18

SRC0#

14

DOT96

15

DOT96#

10
52

REF

2

1

C87

0.047U_0402_16V7K~D

2

H_STP_PCI#
H_STP_CPU#

CK_CPU1

1 2

R85 33_0402_5%~D

CK_CPU1#

1 2

R82 33_0402_5%~D

CK_CPU0
CK_CPU0#

CK_CPU2
CK_CPU2#

1 2

R78 33_0402_5%~D

1 2

R71 33_0402_5%~D

1 2

R93 33_0402_5%~D

1 2

R87 33_0402_5%~D

SCR5

1 2

R1040 33_0402_5%~D

SRC5#

1 2

R1041 33_0402_5%~D

SRC4

1 2

R138 33_0402_5%~D

SRC4#

1 2

R143 33_0402_5%~D

SRC3

1 2

R60 33_0402_5%~D

SRC3#

1 2

R148 33_0402_5%~D

SRC1

1 2

R64 33_0402_5%~D

SRC1#

1 2

R63 33_0402_5%~D

SRC0

1 2

R165 33_0402_5%~D

SRC0#

1 2

R166 33_0402_5%~D

CLK_ENABLE#
CLKREF

1 2

R99 12.1_0402_1%~D

1 2

R98 12.1_0402_1%~D

1 2

R551 12.1_0402_1%~D

2

1

C85

0.047U_0402_16V7K~D

2

Place near each pin
W>40 mil

Place near CK410

H_STP_PCI# <<22>>

H_STP_CPU# <<22,49>>

CLK_MCH_BCLK
CLK_MCH_BCLK#

CK_BCLK
CK_BCLK#

CK_ITP
CK_ITP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CK_14M_ICH

CK_14M_SIO

CK_14M_CODEC

CLK_MCH_BCLK <<10>>
CLK_MCH_BCLK# <<10>>

CK_BCLK <<7>>
CK_BCLK# <<7>>

CK_ITP <<7>>
CK_ITP# <<7>>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Board Number LA2111

Date: Sheet of

CLK_MCH_BCLK
CLK_MCH_BCLK#
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL

CLK_MCH_3GPLL#
CLK_PCIE_LOM
CLK_PCIE_LOM#

CLK_MCH_3GPLL <<12>>

CLK_MCH_3GPLL# <<12>>

CLK_PCIE_SATA <<21>>
CLK_PCIE_SATA# <<21>>

CLK_PCIE_VGA <<18>>

CLK_PCIE_VGA# <<18>>

CLK_PCIE_LOM <<29>>
CLK_PCIE_LOM# <<29>>

CLK_PCIE_ICH <<22>>
CLK_PCIE_ICH# <<22>>

CLK_ENABLE# <<49>>

CK_14M_ICH <<22>>

CK_14M_SIO <<36>>

CK_14M_CODEC <<25>>

Clock Generator

1

R92

12

49.9_0402_1%~D
R86

12

49.9_0402_1%~D
R84

12

49.9_0402_1%~D
R80

12

49.9_0402_1%~D
R77

12

49.9_0402_1%~D
R70

12

49.9_0402_1%~D

R146

1 2

49.9_0402_1%~D

R140

1 2

49.9_0402_1%~D

R153

1 2

49.9_0402_1%~D

R154

1 2

49.9_0402_1%~D

R156

1 2

49.9_0402_1%~D

R159

1 2

49.9_0402_1%~D

R114

1 2

49.9_0402_1%~D

R115

1 2

49.9_0402_1%~D

R1038

1 2

49.9_0402_1%~D

R1039

1 2

49.9_0402_1%~D

661Monday, February 09, 2004

1

0.3

5

4

3

2

1

H_A#[3..31]<<10>>

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<<10>>

H_ADSTB#0<<10>>

C C

R624

56_0402_5%~D

1 2

+VCCP

B B

H_ADSTB#1<<10>>

CK_BCLK<<6>>
CK_BCLK#<<6>>

H_ADS#<<10>>

H_BNR#<<10>>

H_BPRI#<<10>>

H_BR0#<<10>>

H_DEFER#<<10>>

H_DRDY#<<10>>

H_HIT#<<10>>
H_HITM#<<10>>

H_LOCK#<<10>>
H_RESET#<<10>>

H_RS#[0..2]<<10>>

H_TRDY#<<10>>

ITP_DBRESET#<<42>>

H_DBSY#<<10>>

H_DPSLP#<<21>>
H_DPRSTP#<<21>>

H_DPWR#<<10>>

H_PROCHOT#<<37>>
H_PWRGOOD<<21>>

H_CPUSLP#<<10,21>>

H_THERMDA<<39>>
H_THERMDC<<39>>
H_THERMTRIP#<<39>>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22

H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CK_BCLK
CK_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

JCPUA

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

ADDR GROUP

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

U3

ADSTB0#

AE5

ADSTB1#

A16

ITP_CLK0

A15

ITP_CLK1

B15

BCLK0

B14

BCLK1

N2

ADS#

L1

BNR#

J3

BPRI#

N4

BR0#

L4

DEFER#

H2

DRDY#

K3

HIT#

K4

HITM#

A4

IERR#

J2

LOCK#

B11

RESET#

H1

RS0#

K1

RS1#

L2

RS2#

M3

TRDY#

C8

BPM0#

B8

BPM1#

A9

BPM2#

C9

BPM3#

A7

DBR#

M2

DBSY#

B7

DPSLP#

G1

DPRSTP#

C19

DPWR#

A10

PRDY#

B10

PREQ#

B17

PROCHOT#

E4

PWRGOOD

A6

SLP#

A13

TCK

C12

TDI

A12

TDO

C5

TEST1

F23

TEST2

C11

TMS

B13

TRST#

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

AMP_1473129-1_Dothan~D

Dothan

DATA GROUP

HOST CLK

CONTROL GROUP

MISC

THERMAL
DIODE

LEGACY CPU

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#

H_SMI#

H_DINV#0 <<10>>
H_DINV#1 <<10>>
H_DINV#2 <<10>>
H_DINV#3 <<10>>

H_A20M# <<21>>

H_FERR# <<21>>

H_IGNNE# <<21>>

H_INIT# <<21>>

H_INTR <<21>>

H_NMI <<21>>

H_STPCLK# <<21>>

H_SMI# <<21>>

H_D#0H_A#3

A19

H_D#[0..63] <<10>>

H_RESET#

ITP_TDO

H_DSTBN#[0..3] <<10>>

H_DSTBP#[0..3] <<10>>

R621

22.6_0603_1%~D

1 2

CK_ITP<<6>>
CK_ITP#<<6>>

1 2

R620

22.6_0603_1%~D

+VCCP

ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_RESET#
ITP_TCK

CK_ITP
CK_ITP#

ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

29

JITP

28

VTT1

27

GND6

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

GND7

MOLEX_52435-2891_28P~D

30

+3VSUS

+VCCP

+VCCP

+VCCP

R743

150_0603_1%~D

1 2

R622

54.9_0603_1%~D

1 2

R1160

54.9_0402_1%~D

1 2

R618

39.2_0603_1%~D

1 2

R619

150_0603_1%~D

1 2

This shall place near CPU

R615

680_0402_5%~D

1 2

R617

27.4_0603_1%~D

1 2

1

C914

0.1U_0402_10V7K~D

2

ITP_DBRESET#

ITP_TDO

H_RESET#

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near JITP

A A

5

TEST1

R1120
1K_0402_5%~D@

1 2

+VCCP

+VCCP

R12
56_0402_5%~D

H_THERMTRIP#

1 2

R17
200_0402_5%~D

H_PWRGOOD

1 2

4

Add pullups for PWRGOOD and THERMTRIP per INTEL

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Title

Dothan Processor in mFCPGA479

Size Document Number Rev

Board Number LA2111

2

Date: Sheet of

761Monday, February 09, 2004

1

0.3

5

4

3

2

1

Dothan-A2 w/ 533Mhz supports both 1.5V and 1.8V.
Dothan-B step w/533Mhz supports only 1.5V

+1.8VRUN

2 1

+1.5VRUN

12

PAD-OPEN 2x2m~D

2 1

PAD-OPEN 2x2m~D

2

1

12

R646

27.4_0402_1%~D

D D

+VCCP

For test only ,Cmos output

CPU Voltage ID

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

C C

B B

Layout close CPU

12

R341 0_0402_5%~D

12

R337 0_0402_5%~D

12

R338 0_0402_5%~D

12

R339 0_0402_5%~D

12

R340 0_0402_5%~D

12

R747 0_0402_5%~D

V_CPU_GTLREF

2

1

+VCCP

RN9

10K_1206_8P4R_5%~D@

VID0
VID1
VID2
VID3
VID4
VID5

R_A

R50
1K_0603_1%~D

R_B

R51
2K_0603_1%~D

2

2

1

1

B_VID4
OPEN~D

B_VID6
OPEN~D

2

1

OPEN OPEN OPEN OPEN OPEN OPEN

12

12

12

12

1 8

2 7

3 6

4 5

2

2

1

1

10K_0402_5%~D@

R333

B_VID3
OPEN~D

R746

10K_0402_5%~D@

2

2

1

1

B_VID2
OPEN~D

R644

B_VID1
OPEN~D

2

2

1

1

12

R645

54.9_0402_1%~D

27.4_0402_1%~D

OPEN

PJP17

PJP16

SHORT

B_VID5
OPEN~D

2

1

R647

54.9_0402_1%~D

+1.8VS_PROC

1

C997

2

0.01U_0402_16V7K~D

VID0 <<49>>
VID1 <<49>>
VID2 <<49>>
VID3 <<49>>
VID4 <<49>>
VID5 <<49>>

Resistor placed within

0.5" of CPU pin.Trace

12

should be at least 25
miles away from any
other toggling signal.

1

C998

2

10U_0805_6.3V6M~D

H_PSI#<<49>>

54.9_0603_1%~D@

1 2
1 2

54.9_0603_1%~D@

+VCC_CORE

V_CPU_GTLREF

CPU_BSEL0<<6>>
CPU_BSEL1<<6>>

R634

R635

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
H_VID0

H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

CPU_BSEL0
CPU_BSEL1

COMP0
COMP1
COMP2
COMP3

AC26

AD26

AE7
AF6

F26

P23

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16

L21
M22
N21

P22
R21

T22
U21

D18
D20
D22

E17

E19

E21

F18

C16

C14

P25

P26
AB2
AB1

E26
AF7
AC1

B1

N1

W4

K6

L5
M6
N5

P6
R5

T6

D6
D8

E5

E7

E9

F6

F8

E1

E2

F2

F3
G3
G4
H4

B2
C3

JCPUB

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

VCCQ0
VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF

BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD
RSVD

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Dothan

AMP_1473129-1_Dothan~D

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

+VCC_CORE

W21

AA11
AA13
AA15
AA17
AA19
AA21

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC11
AC13
AC15
AC17
AC19

AD10
AD12
AD14
AD16
AD18

AE11
AE13
AE15
AE17
AE19

AF10
AF12
AF14
AF16
AF18

M21
M24

F20
F22

G5

G21

H6

H22

J5

J21

K22

U5
V6

V22

W5

Y6
Y22
AA5
AA7
AA9

AB6
AB8

AC9

AD8

AE9

AF8

M4

M5

N3

N6
N22
N23
N26

P2

P5
P21
P24

R1

R4

R6
R22
R25

T3

T5
T21
T23

JCPUC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

AMP_1473129-1_Dothan~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Dothan Processor in mFCPGA479

Size Document Number Rev

Board Number LA2111

Date: Sheet of

861Monday, February 09, 2004

1

0.3

5

4

3

2

1

+VCC_CORE

1

C415
10U_0805_4VAM~D

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C403
10U_0805_4VAM~D

C404
10U_0805_4VAM~D

C376
10U_0805_4VAM~D

D D

C C

1

C386
10U_0805_4VAM~D

2

1

C418
10U_0805_4VAM~D

2

1

C440
10U_0805_4VAM~D

2

1

C414
10U_0805_4VAM~D

2

1

C412
10U_0805_4VAM~D

2

1

C413
10U_0805_4VAM~D

2

1

C396
10U_0805_4VAM~D

2

1

C445
10U_0805_4VAM~D

2

1

C406
10U_0805_4VAM~D

2

1

C378
10U_0805_4VAM~D

2

1

C387
10U_0805_4VAM~D

2

1

C398
10U_0805_4VAM~D

2

1

C395
10U_0805_4VAM~D

2

1

C405
10U_0805_4VAM~D

2

1

C439
10U_0805_4VAM~D

2

1

C444
10U_0805_4VAM~D

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C925
10U_0805_4VAM~D

C427
10U_0805_4VAM~D

C441
10U_0805_4VAM~D

1

C926
10U_0805_4VAM~D

2

1

C379
10U_0805_4VAM~D

2

1

C394
10U_0805_4VAM~D

2

10uF 0805 X6S -> 105 degree

1

C927
10U_0805_4VAM~D

2

1

C373
10U_0805_4VAM~D

2

1

C372
10U_0805_4VAM~D

2

1

C928
10U_0805_4VAM~D

2

1

C438
10U_0805_4VAM~D

2

1

C374
10U_0805_4VAM~D

2

High Frequence Decoupling

1

C929
10U_0805_4VAM~D

2

1

C377
10U_0805_4VAM~D

2

1

C426
10U_0805_4VAM~D

2

Near VCORE regulator.

+VCC_CORE

1

1

+

+

C942

B B

A A

C941

330U_D2E_2.5VM_R9~D

2

9mOhm
7343
PS CAP

+VCCP

1

2

+

C731
150U_D2_4VK~D

2

330U_D2E_2.5VM_R9~D

9mOhm
7343
PS CAP

C943

330U_D2E_2.5VM_R9~D

9mOhm
7343
PS CAP

1

2

1

1

+

C944

2

2

220U_D2_2VM~D

@

C732

0.1U_0402_10V7K~D

+

ESR <= 3m ohm
Capacitor > 880uF

1

C733

0.1U_0402_10V7K~D

2

1

C734

0.1U_0402_10V7K~D

2

1

C735

0.1U_0402_10V7K~D

2

1

C736

0.1U_0402_10V7K~D

2

1

C737

0.1U_0402_10V7K~D

2

1

C738

0.1U_0402_10V7K~D

2

1

C739

0.1U_0402_10V7K~D

2

1

C740

0.1U_0402_10V7K~D

2

1

C741

0.1U_0402_10V7K~D

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

CPU Bypass

Size Document Number Rev

Board Number LA2111

Date: Sheet of

961Monday, February 09, 2004

1

0.3

5

4

3

2

1

U68B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12

DMIDDR MUXING

CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CFG/RSVD

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

PM

RSTIN#

DREF_CLKN

DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN

CLK

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC

NC9
NC10
NC11

ALVISO_BGA1257~D

PM_EXTTS#0

PM_EXTTS#1

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
D37
C37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0
MCH_CLKSEL1
MCH_CLKSEL0

CFG5

CFG6

CFG7

CFG9

CFG12

CFG13

CFG16

CFG18

CFG19

THERMTRIP_MCH#

PM_EXTTS#0
PM_EXTTS#1
THERMTRIP_MCH#
IMVP_PWRGD
PLTRST_R#

+1.5VRUN

R898

10K_0402_5%~D

R899

10K_0402_5%~D

CFG0 <<12>>
MCH_CLKSEL1 <<6>>

MCH_CLKSEL0 <<6>>

CFG5 <<12>>
CFG6 <<12>>
CFG7 <<12>>

CFG9 <<12>>

CFG12 <<12>>
CFG13 <<12>>

CFG16 <<12>>
CFG18 <<12>>

CFG19 <<12>>

R1113
56_0402_5%~D

1 2

PM_BMBUSY# <<22>>

THERMTRIP_MCH# <<39>>

IMVP_PWRGD <<22,42,49>>

1 2

R1030 100_0603_1%~D

+2.5VRUN

12

12

+VCCP

PLTRST_MCH# <<20>>

M_ODT0<<16>>
M_ODT1<<16,17>>
M_ODT2<<17>>
M_ODT3<<17>>

M_OCDOCMP0
M_OCDOCMP1

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1

M_CLK_DDR3
M_CLK_DDR4

M_CLK_DDR#0
M_CLK_DDR#1

M_CLK_DDR#3
M_CLK_DDR#4

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

1

C753

C752

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

DMI_TXN0<<22>>

DDR_CKE0_DIMMA<<16>>
DDR_CKE1_DIMMA<<16>>
DDR_CKE2_DIMMB<<17>>
DDR_CKE3_DIMMB<<17>>

DDR_CS0_DIMMA#<<16>>
DDR_CS1_DIMMA#<<16>>
DDR_CS2_DIMMB#<<17>>
DDR_CS3_DIMMB#<<16,17>>

1 2

V_DDR_MCH_REF<<16,17,48>>

12

R699

DMI_TXN1<<22>>
DMI_TXN2<<22>>
DMI_TXN3<<22>>

DMI_TXP0<<22>>
DMI_TXP1<<22>>
DMI_TXP2<<22>>
DMI_TXP3<<22>>

DMI_RXN0<<22>>
DMI_RXN1<<22>>
DMI_RXN2<<22>>
DMI_RXN3<<22>>

DMI_RXP0<<22>>
DMI_RXP1<<22>>
DMI_RXP2<<22>>
DMI_RXP3<<22>>

M_CLK_DDR0<<16>>
M_CLK_DDR1<<16>>

M_CLK_DDR3<<17>>
M_CLK_DDR4<<17>>

M_CLK_DDR#0<<16>>
M_CLK_DDR#1<<16>>

M_CLK_DDR#3<<17>>
M_CLK_DDR#4<<17>>

12

40.2_0603_1%~D

R10
0_0402_5%~D

@

1 2

U68A

G9

HA3#

C9

HA4#

E9

HA5#

B7

HA6#

A10

HA7#

F9

HA8#

D8

HA9#

B10

HA10#

E10

HA11#

G10

HA12#

D9

HA13#

E11

HA14#

F10

HA15#

G11

HA16#

G13

HA17#

C10

HA18#

C11

HA19#

D11

HA20#

C12

HA21#

B13

HA22#

A12

HA23#

F12

HA24#

G12

HA25#

E12

HA26#

C13

HA27#

B11

HA28#

D13

HA29#

A13

HA30#

F13

HA31#

A11

HPCREQ#

A7

HREQ#0

D7

HREQ#1

B8

HREQ#2

C7

HREQ#3

A8

HREQ#4

B9

HADSTB#0

E13

HADSTB#1

AB1

HCLKN

AB2

HCLKIN

G4

HDSTBN#0

K1

HDSTBN#1

R3

HDSTBN#2

V3

HDSTBN#3

G5

HDSTBP#0

K2

HDSTBP#1

R2

HDSTBP#2

W4

HDSTBP#3

H8

HDINV#0

K3

HDINV#1

T7

HDINV#2

U5

HDINV#3

H10

HCPURST#

F8

HADS#

B5

HTRDY#

G6

HDPWR#

F7

HDRDY#

E6

HDEFER#

F6

HEDRDY#

D6

HHITM#

D4

HHIT#

B3

HLOCK#

E7

HBREQ0#

A5

HBNR#

D5

HBPRI#

C6

HDBSY#

G8

HSLPCPU#

A4

HRS0#

C5

HRS1#

B4

HRS2#

ALVISO_BGA1257~D

Alviso

HOST

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP

HXSWING
HYSWING

H_D#0

E4

H_D#1

E1

H_D#2

F4

H_D#3

H7

H_D#4

E2

H_D#5

F1

H_D#6

E3

H_D#7

D3

H_D#8

K7

H_D#9

F2

H_D#10

J7

H_D#11

J8

H_D#12

H6

H_D#13

F3

H_D#14

K8

H_D#15

H5

H_D#16

H1

H_D#17

H2

H_D#18

K5

H_D#19

K6

H_D#20

J4

H_D#21

G3

H_D#22

H3

H_D#23

J1

H_D#24

L5

H_D#25

K4

H_D#26

J5

H_D#27

P7

H_D#28

L7

H_D#29

J3

H_D#30

P5

H_D#31

L3

H_D#32

U7

H_D#33

V6

H_D#34

R6

H_D#35

R5

H_D#36

P3

H_D#37

T8

H_D#38

R7

H_D#39

R8

H_D#40

U8

H_D#41

R4

H_D#42

T4

H_D#43

T5

H_D#44

R1

H_D#45

T3

H_D#46

V8

H_D#47

U6

H_D#48

W6

H_D#49

U3

H_D#50

V5

H_D#51

W8

H_D#52

W7

H_D#53

U2

H_D#54

U1

H_D#55

Y5

H_D#56

Y2

H_D#57

V4

H_D#58

Y7

H_D#59

W1

H_D#60

W3

H_D#61

Y3

H_D#62

Y6

H_D#63

W2

H_VREF

J11

H_XRCOMP

C1

H_XSCOMP

C2

H_YRCOMP

T1

H_YSCOMP

L1

H_SWNG0

D1

H_SWNG1

P1

D D

C C

Layout Guide will show
these signals routed
differentially.

B B

A A

H_A#[3..31]<<7>>

H_REQ#[0..4]<<7>>

H_ADSTB#0<<7>>
H_ADSTB#1<<7>>

CLK_MCH_BCLK#<<6>>
CLK_MCH_BCLK<<6>>

H_DSTBN#[0..3]<<7>>

H_DSTBP#[0..3]<<7>>

H_DINV#0<<7>>
H_DINV#1<<7>>
H_DINV#2<<7>>
H_DINV#3<<7>>

H_RESET#<<7>>

H_ADS#<<7>>
H_TRDY#<<7>>
H_DPWR#<<7>>
H_DRDY#<<7>>
H_DEFER#<<7>>

H_HITM#<<7>>
H_HIT#<<7>>
H_LOCK#<<7>>

H_BR0#<<7>>

H_BNR#<<7>>

H_BPRI#<<7>>
H_DBSY#<<7>>

H_RS#[0..2]<<7>>

H_CPUSLP#<<7,21>>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP_H_PCREQ#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RESET#
H_ADS#

H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
TP_H_EDRDY#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

H_R_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_CPUSLP# H_R_CPUSLP#

Note:
"Do not install R10 for Dothan-A,
Install R10 for Dothan-B"

12

R13

24.9_0603_1%~D

H_D#[0..63] <<7>>

H_SWNG1

1

2

C743

0.1U_0402_16V4Z~D

H_SWNG0

1

2

C744

0.1U_0402_16V4Z~D

+VCCP

12

R661

R660

54.9_0603_1%~D

12

R11

24.9_0603_1%~D

+VCCP

12

R649

221_0603_1%~D

12

R650

100_0603_1%~D

+VCCP

12

R652

221_0603_1%~D

12

R653

100_0603_1%~D

12

54.9_0603_1%~D

C745

0.1U_0402_10V6K~D

1

2

Layout Guide
will show these
signals routed
differentially.

+VCCP

12

R656

100_0402_1%~D

12

R657

200_0402_1%~D

+1.8VSUS

R8 80.6_0603_1%~D

12

R9

80.6_0603_1%~D

Layout Note:
Rote as short
as possible

R648

40.2_0603_1%~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Alviso(1 of 5)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

10 61Monday, February 09, 2004

1

0.3

5

D D

4

3

2

1

DDR_A_BS#0<<16>>
DDR_A_BS#1<<16>>
DDR_A_BS#2<<16>>

DDR_A_DM[0..7]<<16>>

DDR_A_DQS[0..7]<<16>>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

C C

B B

DDR_A_DQS#[0..7]<<16>>

DDR_A_MA[0..13]<<16>>

DDR_A_CAS#<<16,17>>
DDR_A_RAS#<<16>>

DDR_A_WE#<<16>>

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#

DDR_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#

DDR_A_WE#

AK15
AK16

AL21
AJ37

AP35

AL29

AP24

AK36
AP33
AN29
AP23

AM8
AM4

AK35
AP34
AN30
AN23

AN8
AM5
AH1

AL17
AP17
AP18
AM17
AN18
AM18

AL19
AP20
AM19

AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4
AJ2
AD3

AJ1
AE5

AE4

U68C

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8

SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42

DDR MEMORY SYSTEM A

SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO_BGA1257~D

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

DDR_B_BS#0<<17>>
DDR_B_BS#1<<17>>
DDR_B_BS#2<<17>>

DDR_B_DM[0..7]<<17>>

DDR_B_DQS[0..7]<<17>>

DDR_B_DQS#[0..7]<<17>>

DDR_B_MA[0..13]<<17>>

DDR_B_CAS#<<17>>
DDR_B_RAS#<<17>>

DDR_B_WE#<<16,17>>

DDR_B_BS#0
DDR_B_BS#1 DDR_B_D1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#

TP_MB_RCVENIN#

TP_MB_RCVENOUT#

DDR_B_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24

AJ10

AF34
AK32

AJ28
AK23
AM10

AF35
AK33
AK28

AJ23

AL10

AH17
AK17
AH18

AJ18
AK18

AJ19
AK19
AH19

AJ20
AH20

AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

AK5
AE7
AB7

AH6
AF8
AB4

AH7
AF7
AB5

U68D

SB_BS0#
SB_BS1#
SB_BS2#

SD_DM0
SD_DM1
SD_DM2
SD_DM3
SD_DM4
SD_DM5
SD_DM6
SD_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8

SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41

DDR SYSTEM MEMORY B

SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

ALVISO_BGA1257~D

AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AE31

SBDQ0

AE32

DDR_B_D[0..63] <<17>>DDR_A_D[0..63] <<16>>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Alviso(2 of 5)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

11 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

U68G

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

CLK_MCH_3GPLL#<<6>>

D D

C C

B B

CLK_MCH_3GPLL<<6>>

+VCCP

AB29
AC29

A15
C16
A17

J18
B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

J20

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

EXP_ICOMPO

MISC

TVVGALVDS

PCI - EXPRESS GRAPHICS

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PEGCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

24.9_0603_1%~D

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_TXN[0..15]

PEG_TXP[0..15]

R44

+1.5VRUN_PCIE

PEG_RXN[0..15] <<18>>

PEG_RXP[0..15] <<18>>

This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.

PEG_TXN[0..15] <<18>>

PEG_TXP[0..15] <<18>>

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG[13:12]
CFG16

(FSB Dynamic
ODT)

CFG18
(VCC Select)

CFG19
(VTT Select)

Refer to sheet 6 for FSB
frequency select

Low = DMI x 2
High = DMI x 4
Low = DDR-II
High = DDR-I

*

*

Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane

*

High = Normal Operation

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)

Low = Disabled
High = Enabled
Low = 1.05V (Default)
High = 1.5V

*

*

Low = 1.05V (Default)
High = 1.2V

+VCCP

R20 10K_0402_5%~D

CFG0<<10>>

R52 2.2K_0402_5%~D@

CFG5<<10>>

R55 2.2K_0402_5%~D

CFG6<<10>>

R56 2.2K_0402_5%~D@

CFG7<<10>>

R74 2.2K_0402_5%~D@

CFG9<<10>>

R906 2.2K_0402_5%~D@

CFG12<<10>>

R907 2.2K_0402_5%~D@

CFG13<<10>>

R97 2.2K_0402_5%~D@

*

CFG16<<10>>

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG[17:3] have internal pull-up

*

+2.5VRUN

R118 1K_0402_5%~D@

CFG18<<10>>
CFG19<<10>>

*

1 2
1 2

R125 1K_0402_5%~D@

CFG[19:18] have internal pull-down

ALVISO_BGA1257~D

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Alviso(3 of 5)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

12 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

U68F

K13

VTT0

J13

VTT1

K12

VTT2

W11

VTT3

V11

VTT4

U11

VTT5

T11

VTT6

R11

VTT7

P11

POWER

VTT8

N11

VTT9

M11

1

2

C807

VTT10

L11

VTT11

K11

VTT12

W10

VTT13

V10

VTT14

U10

VTT15

T10

VTT16

R10

VTT17

P10

VTT18

N10

VTT19

M10

VTT20

K10

VTT21

J10

VTT22

Y9

VTT23

W9

VTT24

U9

VTT25

R9

VTT26

P9

VTT27

N9

VTT28

M9

VTT29

L9

VTT30

J9

VTT31

N8

VTT32

M8

VTT33

N7

VTT34

M7

VTT35

N6

VTT36

M6

VTT37

A6

VTT38

N5

VTT39

M5

VTT40

N4

VTT41

M4

VTT42

N3

VTT43

M3

VTT44

N2

VTT45

M2

VTT46

B2

VTT47

V1

VTT48

N1

VTT49

M1

VTT50

G1

VTT51

1

C806

2

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D

D D

+VCCP

1

C805

C1023

2

4.7U_0805_6.3V6K~D

2.2U_0805_6.3V6K~D

1

C810

C C

2

0.47U_0603_16V7K~D

1

1

C808

2

2

0.47U_0603_16V7K~D

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

ALVISO_BGA1257~D

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

Note : All VCCSM pin
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

1

1

C812

C811

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3

1

2

1

2

+1.8VSUS

1

+

C98

2

330U_D2E_2.5VM~D@

W=20 mils

+VCCP

1

1

C30

C20

2

2

C1219

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C37

0.1U_0402_10V7K~D

C45

C38

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+1.5VRUN

+1.5VRUN_HPLL
+1.5VRUN_MPLL

Remove L6, C48, C51, Connect DPLLB directly to +1.5vrun
Remove L29, C47, C8, Connect DPLLA directly to +1.5vrun
Steven-01/09/2004

M29

M28

M27

W20

W18

T29
R29
N29

K29

J29
V28
U28
T28
R28
P28
N28

L28
K28

J28
H28
G28
V27
U27
T27
R27
P27
N27

L27
K27

J27
H27
K26
H26
K25

J25
K24
K23
K22
K21

U20
T20
K20
V19
U19
K19

V18
T18
K18
K17

AC2
AC1
B23
C35
AA1
AA2

U68E

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

POWER

ALVISO_BGA1257~D

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_CRTDAC0
VCCA_CRTDAC1

VSSA_CRTDAC

VCCA_TVBG
VSSA_TVBG

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GBG
VSSA_3GBG

VCC_SYNC

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

H20
F19

E19
G19

+1.5VRUN
+2.5VRUN
+2.5VRUN

+2.5VRUN

C71

0.1U_0402_16V4Z~D

1

2

+VCCP

C1186

100U_D_6.3VM~D

+1.5VRUN

1

+

2

1

Close B26,B25,A25

C1266
10U_0805_4VAM~D

@

2

1

+

C62

2

220U_D3L_6.3VM_R55~D

C1021

L43

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

R89

0.5_0805_1%~D

0.1U_0402_16V4Z~D

1 2

1

1

C359

2

2

10U_0805_4VAM~D

1

1

C1022

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

C364

3GRLL_R

BLM18PG181SN1_0603~D

1

2

Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.

12

L146

12
+1.5VRUN+1.5VRUN_3GPLL

12

L147

C362

0.1U_0402_16V4Z~D

+2.5VRUN

C367

0.1U_0402_16V4Z~D

1

2

1

2

+1.5VRUN+1.5VRUN_DDRDLL

+1.5VRUN+1.5VRUN_PCIE

C76

1

C77

2

0.1U_0402_16V4Z~D

C370

0.1U_0402_16V4Z~D

@

0.1U_0402_16V4Z~D

1

2

B B

+VCCP

BLM18PG181SN1_0603~D

+1.5VRUN

A A

1 2

C1007

470U_D2_2.5VM~D

1

1

+

C1008

2

2

0.1U_0402_16V4Z~D

+1.5VRUN

BLM18PG181SN1_0603~D

1 2

+1.5VRUN_HPLL

L7

+1.5VRUN_MPLL

L9

C1005

10U_0805_4VAM~D

1

2

C1009

470U_D2_2.5VM~D

1

1

+

C1010

2

2

0.1U_0402_16V4Z~D

C1006

1

C81

2

10U_0805_4VAM~D

W=20 mils

1

1

C80

C112

2

2

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C113

2

0.1U_0402_16V4Z~D

+2.5VRUN

1

2

C287

1

2

10U_0805_4VAM~D@

C783

@

1

C327

0.1U_0402_16V4Z~D

1

C288

2

2

0.1U_0402_16V4Z~D

1

2

0.01U_0402_16V7K~D

C1264

1

1

2

2

10U_0805_4VAM~D

C1265

4.7U_0805_6.3V6K~D@

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Alviso(4 of 5)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

13 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

+VCCP

D D

C C

B B

A A

M12

W12
M13

W13

AA12
AA13

M14

W14

AA14
AB14

M15

W15

AA15
AB15

M16

W16

AA16
AB16

AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20

AA21
AB21

AA22
AB22

AA23
AB23

AA24
AB24

AA25
AB25

AA26
AB26

W25
M26

W26

L12
N12

P12
R12
T12
U12
V12

L13
N13

P13
R13
T13
U13
V13

Y12
Y13
L14
N14

P14
R14
T14
U14
V14

Y14

L15
N15

P15
R15
T15
U15
V15

Y15

L16
N16

P16
R16
T16
U16
V16

Y16

R17
Y17

R21
Y21

Y22

Y23

Y24

Y25

Y26

V25
L26
N26

P26
R26
T26
U26
V26

5

U68H

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10

VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71

NCTF

VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

ALVISO_BGA1257~D

+1.8VSUS

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+VCCP

AA10

AD2
AE2
AH2
AL2
AN2

AA3
AB3
AC3

AF4
AN4

AL5
AP5

AA6
AC6
AE6

AA7
AG7
AK7
AN7

AL8

AA9
AC9
AE9
AH9
AN9
D10

Y10

H11
Y11

U68I

Y1

VSS271

D2

VSS270

G2

VSS269

J2

VSS268

L2

VSS260

P2

VSS259

T2

VSS258

V2

VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSS

ALVISO_BGA1257~D

A3
C3

AJ3

C4
H4

L4
P4
U4
Y4

E5

W5

B6

J6

L6
P6
T6

AJ6

G7
V7

C8
E8

L8
P8
Y8

A9
H9
K9
T9
V9

L10

F11

VSSALVDS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

B36
AA11

AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

AL24

AN24

W27
AA27
AB27
AF27
AG27

AJ27
AL27

AN27

W28
AA28
AB28
AC28

W29
AA29
AD29
AG29

AJ29

AM29

AA30
AB30
AC30
AE30
AP30

M31

W31
AD31
AG31

AL31

AA32
AB32

U68J

VSS267
VSS266

A26

VSS265

E26

VSS264

G26

VSS263

J26

VSS262

B27

VSS261

E27

VSS129

G27

VSS128
VSS127
VSS126
VSS125

VSS

VSS124
VSS123
VSS122
VSS121
VSS120

E28

VSS119
VSS118
VSS117
VSS116
VSS115

A29

VSS114

D29

VSS113

E29

VSS112

F29

VSS111

G29

VSS110

H29

VSS109

L29

VSS108

P29

VSS107

U29

VSS106

V29

VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99

C30

VSS98

Y30

VSS97
VSS96
VSS95
VSS94
VSS93
VSS92

D31

VSS91

E31

VSS90

F31

VSS89

G31

VSS88

H31

VSS87

J31

VSS86

K31

VSS85

L31

VSS84
VSS83

N31

VSS82

P31

VSS81

R31

VSS80

T31

VSS79

U31

VSS78

V31

VSS77
VSS76
VSS75
VSS74
VSS73

A32

VSS72

C32

VSS71

Y32

VSS70
VSS69
VSS68

ALVISO_BGA1257~D

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Alviso(5 of 5)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

14 61Monday, February 09, 2004

1

0.3

5

FAN1 Control and Tachometer

+15V

R130

D D

FAN1_PWM<<37>>

100K_0402_5%~D

1 2

C128

FAN1VREF
FAN1_VFB

1

2

1U_0805_10V6K~D

R128

1 2

150K_0402_5%~D

8

5

P

IN+

6

IN-

G

4

C127

2200P_0603_50V7K~D @

1 2

R129

100K_0402_5%~D

12

RB751V_SOD323~D

U49B
LM358M_SO8~D

7

O

1

C121

2

FAN1_ON

D9

0.1U_0402_25V4K~D

2 1

4

+5VRUN

Q15

SI3456DV-T1_TSOP6~D

6

2

1

G

3

S

4 5

1

+

2

D

C476

0.47U_0603_16V7K~D

FAN1_VOUT

C479

47U_D_16VM_R70~D

3

Q11

2

1 2

+3VRUN

R1074
0_0402_5%~D

12

R117
10K_0402_5%~D

FAN1_TACH <<37>>

3 1

+5VRUN

R110

10K_0402_5%~D@

1 2

R109

1K_0402_5%~D@

@

1 2

FAN1_TACH_FB

C1242

1000P_0402_50V7K~D

1

2

1

2

PMBT2222_SOT23~D@

FAN1TACH_ON

JFAN1

1

1

2

2

3

3

MOLEX_53398-0390~D

FAN1

2

C

B

E3

2

2222 SYMBOL(SOT23-NEW)

1

1

C C

R437

100K_0402_5%~D

FAN2_PWM<<37>>

B B

1 2

C478

FAN2VREF

3

FAN2_VFB

1

2

1U_0805_10V6K~D

R435

1 2

150K_0402_5%~D

2

C110

2200P_0603_50V7K~D@

1 2

R436

100K_0402_5%~D

FAN2 Control and Tachometer

+15V

8

U49A
LM358M_SO8~D

P

IN+

O

IN-

G

4

12

RB751V_SOD323~D

FAN2_ON

1

D10

+5VRUN

2

1

G

3

2 1

Q17

SI3456DV-T1_TSOP6~D

6

D

S

4 5

1

+

2

C495

47U_D_16VM_R70~D

1

C472

2

0.47U_0603_16V7K~D

1

2

C1243

@

1000P_0402_50V7K~D

+5VRUN

R163

10K_0402_5%~D@

1 2

FAN2_5V
FAN2_TACH_FB

R168

1K_0402_5%~D@

1 2

PMBT2222_SOT23~D@

FAN2TACH_ON

JFAN2

1

1

2

2

3

3

MOLEX_53398-0390~D

FAN2

Q18

2

+3VRUN

12

R174
10K_0402_5%~D

3 1

1 2

R1075
0_0402_5%~D

FAN2_TACH <<37>>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ITP Debug CONN. & FAN

Size Document Number Rev

Board Number LA2111

Date: Sheet of

15 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

DDR_A_DQS#[0..7]<<11>>

DDR_A_D[0..63]<<11>>
DDR_A_DM[0..7]<<11>>
DDR_A_DQS[0..7]<<11>>

DDR_A_MA[0..13]<<11>>

D D

+1.8VSUS

0.1U_0402_16V4Z~D

2.2U_0805_6.3V6K~D

1

2

1

2

C1025

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

C1173

1

2

RN62

RN44

RN59

RN43

RN58

RN81

0.1U_0402_16V4Z~D

C1048

0.1U_0402_16V4Z~D

1

2

C1026

1

2

2.2U_0603_6.3V6K~D
C1049

1

2

C1174

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C1027

+0.9V_DDR_VTT

RN46

RN60

RN45

RN128

RN75

2.2U_0603_6.3V6K~D
C1047

1

2

0.1U_0402_16V4Z~D

C1172

1

2

0.1U_0402_16V4Z~D

1

2

C1024

2.2U_0805_6.3V6K~D

2.2U_0805_6.3V6K~D

C1045

C1046

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C1171

1

2

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

1

2

B B

A A

C145

DDR_CS3_DIMMB#<<10,17>>

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

1

2

DDR_B_WE#<<11,17>>

C167

0.1U_0402_16V4Z~D

1

2

5

0.1U_0402_16V4Z~D

1

2

C138

C118

DDR_A_MA5
DDR_A_MA8

56_0404_4P2R_5%~D

DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5%~D

DDR_A_RAS#
DDR_CS0_DIMMA#

56_0404_4P2R_5%~D

DDR_A_BS#0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_B_WE#
DDR_A_WE#

56_0404_4P2R_5%~D

DDR_CS1_DIMMA#
DDR_CS3_DIMMB#

56_0404_4P2R_5%~D

0.1U_0402_16V4Z~D

1

2

C1028

RN61

14
23

56_0404_4P2R_5%~D

RN47

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

Layout Note:
Place near JDIM1

M_CLK_DDR0

10P_0402_50V8J~D

1

C1169

2

M_CLK_DDR#0

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C1029

C1030

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1

M_CLK_DDR1

10P_0402_50V8J~D

1

C1170

2

M_CLK_DDR#1

DDR_CKE0_DIMMA<<10>>

DDR_A_BS#2<<11>>

DDR_A_BS#0<<11>>
DDR_A_WE#<<11>>

DDR_A_CAS#<<11,17>>

DDR_CS1_DIMMA#<<10>>

0.1U_0402_16V4Z~D

1

1

2

2

C1032

C1031

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMM0,all
trace length Max=1.3"

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

M_ODT1<<10,17>>

CK_SDATA<<6,17>>

CK_SCLK<<6,17>>

3

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59

CK_SDATA
CK_SCLK

+3VRUN

+1.8VSUS +1.8VSUS

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DIMMA

NC/CKE1

NC/A15
NC/A14

NC/A13

0.1U_0402_16V4Z~D

81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

2.2U_0805_10V6K~D

C1175

1

1

2

2

C1176

FOX_AS0A426-M2S

STANDARD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

VDD

VDD

VDD

VDD

RAS#

VDD
ODT0

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2

V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

10K_0402_5%~D

10K_0402_5%~D

12

R119

R134

M_CLK_DDR0 <<10>>

M_CLK_DDR#0 <<10>>

DDR_CKE1_DIMMA <<10>>

DDR_A_BS#1 <<11>>

DDR_A_RAS# <<11>>
DDR_CS0_DIMMA# <<10>>

M_ODT0 <<10>>

M_CLK_DDR1 <<10>>

M_CLK_DDR#1 <<10>>

12

2.2U_0805_6.3V6K~D

0.1U_0402_16V4Z~D

1

1

C1168

2

2

V_DDR_MCH_REF <<10,17,48>>

C114

DELL CONFIDENTIAL/PROPRIETARY

Title

DDRII-SODIMM SLOT1

Size Document Number Rev

Board Number LA2111

Date: Sheet of

16 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

D D

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26

C C

DDR_B_D27
DDR_CKE2_DIMMB

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2

DDR_B_MA13
M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35

B B

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#

A A

DDR_B_MA9
DDR_B_MA12

DDR_CKE3_DIMMB
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

M_ODT2
DDR_B_MA13

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

DDR_B_D36

DDR_B_D37

DDR_B_DM4

DDR_B_D38

DDR_B_D39

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D46

DDR_B_D47

DDR_B_D52

DDR_B_D53

M_CLK_DDR4

M_CLK_DDR#4

DDR_B_DM6

DDR_B_D54

DDR_B_D55

DDR_B_D60

DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D62

DDR_B_D63

DDR_B_BS#2

M_ODT3

5

DDR_CKE2_DIMMB

4

3

2

1

5

4

JVID

3

2

1

1

1

+3VRUN

1

D D

PEG_TXP0

PEG_TXP[0..15]

<12>>

C C

PEG_TXN[0..15]

<12>>

B B

A A

PEG_TXP[0..15]

PEG_TXN[0..15]

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXN0

PEG_TXN1

PEG_TXN2

PEG_TXN3

PEG_TXN4

PEG_TXN5

PEG_TXN6

PEG_TXN7

PEG_TXN8

PEG_TXN9

PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXN0
PEG_TXP1

PEG_TXN1
PEG_TXP2

PEG_TXN2
PEG_TXP3

PEG_TXN3
PEG_TXP4

PEG_TXN4
PEG_TXP5

PEG_TXN5
PEG_TXP6

PEG_TXN6
PEG_TXP7

PEG_TXN7
PEG_TXP8

PEG_TXN8
PEG_TXP9

PEG_TXN9
PEG_TXP10

PEG_TXN10
PEG_TXP11

PEG_TXN11
PEG_TXP12

PEG_TXN12
PEG_TXP13

PEG_TXN13
PEG_TXP14

PEG_TXN14
PEG_TXP15

PEG_TXN15

1

C182

2

0.047U_0402_16V4Z~D

C371 0.1U_0402_16V4Z~D

1 2

C384 0.1U_0402_16V4Z~D

1 2

C389 0.1U_0402_16V4Z~D

1 2

C400 0.1U_0402_16V4Z~D

1 2

C408 0.1U_0402_16V4Z~D

1 2

C411 0.1U_0402_16V4Z~D

1 2

C417 0.1U_0402_16V4Z~D

1 2

C423 0.1U_0402_16V4Z~D

1 2

C425 0.1U_0402_16V4Z~D

1 2

C429 0.1U_0402_16V4Z~D

1 2

C431 0.1U_0402_16V4Z~D

1 2

C433 0.1U_0402_16V4Z~D

1 2

C435 0.1U_0402_16V4Z~D

1 2

C437 0.1U_0402_16V4Z~D

1 2

C443 0.1U_0402_16V4Z~D

1 2

C447 0.1U_0402_16V4Z~D

1 2

+1.8VSUS

1

C95

C498

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

C375 0.1U_0402_16V4Z~D

1 2

C385 0.1U_0402_16V4Z~D

1 2

C399 0.1U_0402_16V4Z~D

1 2

C402 0.1U_0402_16V4Z~D

1 2

C409 0.1U_0402_16V4Z~D

1 2

C416 0.1U_0402_16V4Z~D

1 2

C419 0.1U_0402_16V4Z~D

1 2

C424 0.1U_0402_16V4Z~D

1 2

C428 0.1U_0402_16V4Z~D

1 2

C430 0.1U_0402_16V4Z~D

1 2

C432 0.1U_0402_16V4Z~D

1 2

C434 0.1U_0402_16V4Z~D

1 2

C436 0.1U_0402_16V4Z~D

1 2

C442 0.1U_0402_16V4Z~D

1 2

C446 0.1U_0402_16V4Z~D

1 2

C453 0.1U_0402_16V4Z~D

1 2

1 2

JVID PIN.201, PIN.202, PIN.203 and
PIN.204 will contact to GND

2

+3VSUS

PJP18

PAD-OPEN 4x4m

RUNPWROK<<37,42,47,49>>

DVI_TX0+<<35>>
DVI_TX0-<<35>>

DVI_TX1+<<35>>
DVI_TX1-<<35>>

DVI_TX2+<<35>>
DVI_TX2-<<35>>

DVI_CLK+<<35>>
DVI_CLK-<<35>>

VDDM

+15V

+2.5VRUN

DVI_TX0+
DVI_TX0-

DVI_TX1+
DVI_TX1-

DVI_TX2+
DVI_TX2-

DVI_CLK+
DVI_CLK-

PEG_A_TXP_0
PEG_A_TXN_0

PEG_A_TXP_1
PEG_A_TXN_1

PEG_A_TXP_2
PEG_A_TXN_2

PEG_A_TXP_3
PEG_A_TXN_3

PEG_A_TXP_4
PEG_A_TXN_4

PEG_A_TXP_5
PEG_A_TXN_5

PEG_A_TXP_6
PEG_A_TXN_6

PEG_A_TXP_7
PEG_A_TXN_7

PEG_A_TXP_8
PEG_A_TXN_8

PEG_A_TXP_9
PEG_A_TXN_9

PEG_A_TXP_10
PEG_A_TXN_10

PEG_A_TXP_11
PEG_A_TXN_11

PEG_A_TXP_12
PEG_A_TXN_12

PEG_A_TXP_13
PEG_A_TXN_13

PEG_A_TXP_14
PEG_A_TXN_14

PEG_A_TXP_15
PEG_A_TXN_15

RUNPWROK

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

147

149

149

151

151

153

153

155

155

157

157

159

159

161

161

163

163

165

165

167

167

169

169

171

171

173

173

175

175

177

177

179

179

181

181

183

183

185

185

187

187

189

189

191

191

193

193

195

195

197

197

199

199

201

201

203

203

205

205

JAE_WB3M200VD1~D

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

122

122

124

124

126

126

128

128

130

130

132

132

134

134

136

136

138

138

140

140

142

142

144

144

146

146

148

148

150

150

152

152

154

154

156

156

158

158

160

160

162

162

164

164

166

166

168

168

170

170

172

172

174

174

176

176

178

178

180

180

182

182

184

184

186

186

188

188

190

190

192

192

194

194

196

196

198

198

200

200

202

202

204

204

206

206

+5VALW
SBAT_SMBCLK
SBAT_SMBDAT

TV_Y
TV_CVBS
TV_C
VSYNC

HSYNC
VGA_BLU
VGA_GRN
VGA_RED
CLK_DDC2

DAT_DDC2
DVI_DETECT
DVI_SCLK
DVI_SDAT
PLTRST_VGA#

CLK_PCIE_VGA
CLK_PCIE_VGA#

PEG_RXP0
PEG_RXN0

PEG_RXP1
PEG_RXN1

PEG_RXP2
PEG_RXN2

PEG_RXP3
PEG_RXN3

PEG_RXP4
PEG_RXN4

PEG_RXP5
PEG_RXN5

PEG_RXP6
PEG_RXN6

PEG_RXP7
PEG_RXN7

PEG_RXP8
PEG_RXN8

PEG_RXP9
PEG_RXN9

PEG_RXP10
PEG_RXN10

PEG_RXP11
PEG_RXN11

PEG_RXP12
PEG_RXN12

PEG_RXP13
PEG_RXN13

PEG_RXP14
PEG_RXN14

PEG_RXP15
PEG_RXN15

+1.5VRUN

THERMATRIP_VGA#
+5VRUN
FPBACK_EN

2

C511

1

0.1U_0603_25V7M~D

ICH_PCIE_WAKE#

+5VALW

SBAT_SMBCLK <<37,45>>

SBAT_SMBDAT <<37,45>>
TV_Y <<19,35>>
TV_CVBS <<19,35>>
TV_C <<19,35>>

VSYNC <<19,35>>

HSYNC <<19,35>>
VGA_BLU <<19,35>>
VGA_GRN <<19,35>>
VGA_RED <<19,35>>

CLK_DDC2 <<19,35>>

DAT_DDC2 <<19,35>>

DVI_SCLK <<35>>

DVI_SDAT <<35>>

PLTRST_VGA# <<20>>

CLK_PCIE_VGA <<6>>
CLK_PCIE_VGA# <<6>>

THERMATRIP_VGA# <<39>>

+5VRUN

FPBACK_EN <<36>>

2

2

C558

C186

1

1

0.1U_0603_25V7M~D

0.1U_0603_25V7M~D

ICH_PCIE_WAKE# <<22,36>>

C494

2

1

0.1U_0603_25V7M~D

DVI_DETECT <<35>>

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

G_PWR_SRC

1

+

C1290
15U_D2_25M_R90~D

2

@

12

R15

100K_0402_5%~D

PEG_RXP[0..15]

PEG_RXN[0..15]

PEG_RXP[0..15] <<12>>

PEG_RXN[0..15] <<12>>

2

C28

C668

1

0.1U_0603_25V7M~D

PWR_SRC G_PWR_SRC

1
2
3 6

2

G

4

12

R196
100K_0402_5%~D

AGP_PWRON# GPWR_SRC_ON

13

D

S

0.1U_0603_25V7M~D

2

R571

1

1 2

100K_0402_5%~D

RUN_ON<<28,36,41,42,45,46,48>>

Q56

8
7

5

SI4435DY_SO8~D

Q73
2N7002_SOT23~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

VGA connector

Size Document Number Rev

Board Number LA2111

Date: Sheet of

18 61Monday, February 09, 2004

1

0.3

5

TV_C<<18,35>>

D D

C C

VGA_RED<<18,35>>

VGA_GRN<<18,35>>

VGA_BLU<<18,35>>

B B

A A

TV_CVBS<<18,35>>

TV_Y<<18,35>>

Note : R1, R2, R3, R14, R303, R304 no stuff,
It's stuff on VGA board
Bill 11/12

VGA_RED

VGA_GRN

VGA_BLU

5

12

C6

R3

75_0402_1%~D@

82P_0402_50V8J~D

12

C4

R2

75_0402_1%~D@

82P_0402_50V8J~D

12

R1

C2

75_0402_1%~D@

82P_0402_50V8J~D

12

12

R14

R303

75_0402_1%~D@

75_0402_1%~D@

L3

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

CLOSE TO JTV1

1

2

1

2

1

2

L2

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

L1

1.8UH_MDF1608A1R8K_10%_0603~D

1 2

12

R304

75_0402_1%~D@

DAT_DDC2<<18,35>>

HSYNC<<18,35>>

VSYNC<<18,35>>

C17

@

CLK_DDC2<<18,35>>

SPDIF<<25>>

1

2

22P_0402_50V8J~D

4

1

C7

2

82P_0402_50V8J~D

1

C5

2

82P_0402_50V8J~D

1

C3

2

82P_0402_50V8J~D

C354

1

C660

2

@

22P_0402_50V8J~D

1

C13

C15

2

33P_0402_50V8J~D

4

0.1U_0402_16V4Z~D

33P_0402_50V8J~D

2

1

@

1

2

SVIDEO_C
SVIDEO_CVBS

SVIDEO_Y

+5VRUN

5

1

U40

P

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5~D

3

1

C289

2

22P_0402_50V8J~D

BLM11A121S_0603~D

1 2

BLM11A121S_0603~D

1 2

SPDIF_DOCKSPDIF

4

L5

BLM18BB600SN1D_0603~D

1 2

L104

BLM18BB600SN1D_0603~D

1 2

L105

BLM18BB600SN1D_0603~D

1 2

CRT_VCC

12

R16

@

1K_0402_5%~D

L4

L19

1

C12

2

22P_0402_50V8J~D

SPDIF<<25>>

SPDIF_DOCK <<35>>

12

@

R6

1K_0402_5%~D

1

C39

2

22P_0402_50V8J~D

C349

SPDIF

3

D70
DA204U_SOT323~D

1

@

+3VRUN

2

3

+5VRUN

2

1

0.1U_0402_16V4Z~D

5

P

A2Y

G

3

SN74AHCT1G125DCKR_SC70-5~D

1

U39

OE#

SPDIF_SHDN

4

SPDIF_SHDN <<25,36>>

R347

SP_DIFBSP_DIF

12

220_0603_1%~D

Overlap L126 & L57 for Pop Option

C290

0.01U_0402_16V7K~D

12

R311

D4, D5, D6 should be pulled up for Int. GFX.

D4
DA204U_SOT323~D

1

@

+3VRUN

2

3

1

C10
10P_0402_50V8J~D

2

@

R4

R5

1 2

2.2K_0603_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

2.2K_0603_5%~D

3

1

2

1

C11
10P_0402_50V8J~D

2

@

D5
DA204U_SOT323~D

@

3

1

2

0.1U_0402_16V4Z~D

D1
DA204U_SOT323~D

1

@

2

3

12

110_0603_1%~D

D6
DA204U_SOT323~D

1

@

2

3

C661
10P_0402_50V8J~D

@

M_SEN#<<35>>

1

C16

2

2

L126

@

1 2

BLM11A121S_0603~D

L57

4 5

1 8

TA08F010_4P~D

1 2

R1233
0_0402_5%~D

@

2

D2
DA204U_SOT323~D

1

@

2

3

+5VRUN

21

D3

RB751V_SOD323~D

1

JP2

2
4
6
7
5
3
1
8
9

FOX_MH11777-WRUR6~D

SP_DIF_DSP_DIF_C

SP_DIF_E

1

C14
300P_1808_3000V8K~D

2

@

DDA204U

A2

K1

CRT_VCC

A1

Evaluate Package

+3VSUS

12

R7

10K_0402_5%~D

JVGA

6

11

1
7

16

12

17
2
8

13

18
3

19
9

14

4

10
15

5

FOX_DS01A91-WD37~D

C9

1

2

0.01U_0402_16V7K~D

RED

GREEN
JVGA_HS

BLUE
CRT_VCC
JVGA_VS
M_ID2#

DELL CONFIDENTIAL/PROPRIETARY

Title

TV_OUT and CRT

Size Document Number Rev

Board Number LA2111

Date: Sheet of

1

K2

19 61Monday, February 09, 2004

0.3

5

RN118

+3VRUN

D D

+3VRUN

+3VRUN

+3VRUN

C C

+3VRUN

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

RN117

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

RN6

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

RN130

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

RN121

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

RN1

8.2K_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

PCI_PERR#
PCI_DEVSEL#
PCI_STOP#
ICH_GPIO5_PIRQH#

PCI_REQ1#
PCI_IRDY#
PCI_PLOCK#
ICH_GPIO4_PIRQG#

PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQA#

ICH_GPIO3_PIRQF#
PCI_REQB#
PCI_REQ3#
PCI_SERR#

PCI_FRAME#
PCI_TRDY#
PCI_REQ0#
PCI_REQ4#

PCI_REQ2#
PCI_REQ5#
ICH_GPIO2_PIRQE#
IDE_IRQ

PCI_AD[0..31]<<31,33,34>>

PCI_FRAME#<<31,33,34,35>>

PCI_PIRQA#<<34>>
PCI_PIRQB#<<33>>
PCI_PIRQC#<<31>>
PCI_PIRQD#<<31,33>>

IDE_IRQ <<21,24>>

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#

PCI_PIRQA#

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U59B

E2

AD[0]

E5

AD[1]

C2

AD[2]

F5

AD[3]

F3

AD[4]

E9

AD[5]

F2

AD[6]

D6

AD[7]

E6

AD[8]

D3

AD[9]

A2

AD[10]

D2

AD[11]

D5

AD[12]

H3

AD[13]

B4

AD[14]

J5

AD[15]

K2

AD[16]

K5

AD[17]

D4

AD[18]

L6

AD[19]

G3

AD[20]

H4

AD[21]

H2

AD[22]

H5

AD[23]

B3

AD[24]

M6

AD[25]

B2

AD[26]

K6

AD[27]

K3

AD[28]

A5

AD[29]

L1

AD[30]

K4

AD[31]

J3

FRAME#

N2

PIRQ[A]#

L2

PIRQ[B]#

M1

PIRQ[C]#

L3

PIRQ[D]#

AC5

SATA[1]RXN/RSVD[1]

AD5

SATA[1]RXP/RSVD[2]

AF4

SATA[1]TXN/RSVD[3]

AG4

SATA[1]TXP/RSVD[4]

AC9

SATA[3]RXN/RSVD[5]

AD9

SATA[3]RXP/RSVD[6]

AF8

SATA[3]TXN/RSVD[7]

AG8

SATA[3]TXP/RSVD[8]

U3

TP[3]/RSVD[9]

REQ[0]#

PCI

GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#

REQ[4]#/GPI[40]

GNT[4]#/GPO[48]

REQ[5]#/GPI[1]

GNT[5]#/GPO[17]

REQ[6]#/GPI[0]

GNT[6]#/GPO[16]

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PLTRST#

PCICLK

Interrupt I/F

PME#

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]

PIRQ[G]#GPI[4]

PIRQ[H]#/GPI[5]

RESERVED

ICH6_BGA609~D

PAR

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

J6
H6
G4
G2

A3
E1
R2
C3
E3
C5
G5
J1
J2

R5
G6
P6

D9
C7
C6
M3

3

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#

PCI_REQ3#
PCI_GNT3#
PCI_REQ4#

PCI_REQ5#
PCI_GNT5#
PCI_REQB#

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PLTRST#
CK_33M_ICHPCI
ICH_PME#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

PCI_REQ0# <<34>>
PCI_GNT0# <<34,35>>
PCI_REQ1# <<31>>
PCI_GNT1# <<31>>

PCI_REQ3# <<33>>
PCI_GNT3# <<33>>

PCI_C_BE0# <<31,33,34>>
PCI_C_BE1# <<31,33,34>>
PCI_C_BE2# <<31,33,34>>
PCI_C_BE3# <<31,33,34>>

PCI_IRDY# <<31,33,34,35>>
PCI_PAR <<31,33,34>>

PCI_DEVSEL# <<31,33,34>>
PCI_PERR# <<31,33,34>>

PCI_PLOCK# <<34>>

PCI_SERR# <<31,33,34>>

PCI_STOP# <<31,33,34>>

PCI_TRDY# <<31,33,34>>

PLTRST# <<22>>

CK_33M_ICHPCI <<6>>

ICH_PME# <<36>>

2

PLTRST_DELAY#<<22>>

PLTRST_DELAY#

PLTRST#

12

R1252
0_0402_5%~D

R1251
0_0402_5%~D

@

1 2

4
5

+3VSUS

1

IN1

2

IN2

U25B

IN1

6

OUT

IN2

74VHC08MTC_TSSOP14~D

+3VSUS

5

1

P

4

OE#

A2Y

G

U178
SN74AHCT1G125DCKR_SC70-5~D

3

+3VSUS

5

1

P

4

OE#

A2Y

G

U179
SN74AHCT1G125DCKR_SC70-5~D

3

14

U25A

P

3

OUT

G

74VHC08MTC_TSSOP14~D

7

PCIRSTB2#

PCIRSTB5#

PCIRSTB6#

0.1U_0402_16V4Z~D

33_0402_5%~D

PCIRSTB1#

1 2

33_0402_5%~D

1 2

R1246 33_0402_5%~D @

1 2

R1247 33_0402_5%~D @

1 2

R558 33_0402_5%~D

1 2

R1123 33_0402_5%~D

1 2

R1221

33_0402_5%~D

1 2

R1243

33_0402_5%~D

1 2

C213

R559

R1050

1

12

PLTRST_LOM# <<29>>

PLTRST_VGA# <<18>>

PLTRST_LOM# <<29>>

PLTRST_VGA# <<18>>

PLTRST_SIO# <<36>>

PLTRST_MCH# <<10>>

PLTRST_SATA# <<52>>

PLTRST_LPC# <<29>>

Internal Pull-up.
Sample high destination is LPC.

PCI_GNT5#

B B

A A

12

R1109
0_0402_5%~D@

PCI_PCIRST#

U25C

10

IN1

OUT

9

IN2

74VHC08MTC_TSSOP14~D
U25D

13

IN1

OUT

12

IN2

74VHC08MTC_TSSOP14~D

PCIRSTB3#

8

PCIRSTB4#

11

R560

33_0402_5%~D

1 2

R561

33_0402_5%~D

1 2

CK_33M_ICHPCI

R250
10_0402_5%~D

@

1 2

CLK_ICH_TERM

1

@

C241

8.2P_0402_50V8J~D

2

PCIRST_DOCK# <<34>>

PCIRST_CB# <<31,33>>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ICH6(1/4)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

20 61Monday, February 09, 2004

1

0.3

5

C586

12P_0603_50V8J~D

12

Package

R1161
33_0402_5%~D

1 2

R1162
33_0402_5%~D

1 2

R1163
33_0402_5%~D

1 2

R294
10_0402_5%~D

@

9.6X4.06 mm

12P_0603_50V8J~D

ICH_AC_SDOUT_R

ICH_AC_SYNC_R

ICH_AC_RST_R#

C581

INTRUDER#<<39>>

D D

+RTC_CELL

12

R26
100K_0402_5%~D

INTRUDER#

ICH_SDOUT_AUDIO<<25>>

ICH_SYNC_AUDIO<<25>>

ICH_RST_AUDIO#<<25>>

C C

ICH_AC_BITCLK<<25>>

B B

1 2

X5

32.768KHZ_12.5P_MC-306~D

1 2

12

+RTC_CELL

ICH_SYNC_MDC<<28>>

ICH_RST_MDC#<<28>>

ICH_SDOUT_MDC<<28>>

1 2

R227
180K_0402_5%~D

CMOS_CLR
SHORT PADS~D

1

1

C220

0.1U_0402_10V6K~D

1 2

ICH_RTCX1

ICH_RTCX2

2

ICH_AC_SDIN0<<25>>
ICH_AC_SDIN1<<28>>

IDE_DIORDY<<24>>
IDE_IRQ<<20,24>>
IDE_DDACK#<<24>>

2

CLK_PCIE_SATA#<<6>>
CLK_PCIE_SATA<<6>>

12

R467

10M_0402_5%~D

1 2
1 2

R299

1 2

33_0402_5%~D

SATA_ACT#<<40>>

IDE_DIOW#<<24>>

IDE_DIOR#<<24>>

R29833_0402_5%~D
R22433_0402_5%~D

4

ICH_RTCRST#
INTRUDER#

1 2

1 2

R1216

0_0402_5%~D

ICH_AC_BITCLK
ICH_AC_SYNC_R

ICH_AC_RST_R#
ICH_AC_SDIN0

ICH_AC_SDIN1

ICH_AC_SDOUT_R

SATA_ACT#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2_C
SATA_TXP2_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R300

24.9_0603_1%~D

IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#

AC19

AG11

AF11

AF16
AB16
AB15
AC14
AE16

AA2
AA3

AA5

D12
D11

C13
C12

C11

C10

AE3
AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

Y1
Y2

B12
F13
F12
B11
E12

E11

E13

B9
A10
F11

F10
B10

C9

U59A

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LANRXD[0]

LANRXD[1]
LANRXD[2]

LANTXD[0]
LANTXD[1]
LANTXD[2]

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN[0]

ACZ_SDIN[1]
ACZ_SDIN[2]

ACZ_SDO

SATALED#

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH6_BGA609~D

RTC

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LPC

LDRQ[0]#

LDRQ[1]#/GPI[41]

LFRAME#/FWH[4]

LAN

A20GATE

A20M#

CPUSLP#

CPU

DPRSLP#/TP[4]

DPSLP#/TP[2]

FERR#

CPUPWRGD/GPO[49]

IGNNE#

INIT3_3V#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DA[0]
DA[1]
DA[2]

DCS1#
DCS3#

SATAAC-97/AZALIA

DD[0]
DD[1]

IDE

DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]

DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

DDREQ

3

LPC_LAD0

P2

LPC_LAD1

N3

LPC_LAD2

N5

LPC_LAD3

N4

LPC_LDRQ0#

N6

LPC_LDRQ1#

P4

LPC_LFRAME#

P3

SIO_A20GATE

AF22

H_A20M#

AF23

ICH_CPUSLP#

AE27

DPRSLP#

AE24

H_DPSLP#

AD27

FERR#

AF24

H_PWRGOOD

AG25

H_IGNNE#

AG26
AE22

H_INIT#

AF27

H_INTR

AG24

SIO_RCIN#

AD23

H_NMI

AF25

NMI

AG27
AE26
AE23

AC16
AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

H_SMI#
H_STPCLK#
THRMTRIP_ICH#

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

RDDREQ

RDDREQ <<24>>

LPC_LAD[0..3] <<29,36>>

Note : R940, Do not populate for
Dothan-A.

LPC_LDRQ0# <<36>>
LPC_LDRQ1# <<36>>

LPC_LFRAME# <<29,36>>

R1248 0_0402_5%~D

1 2

R940 0_0402_5%~D@

R25 56_0402_5%~D

R1049 75_0402_5%~D

IDE_DA[0..2] <<24>>

IDE_DCS1# <<24>>
IDE_DCS3# <<24>>

IDE_DD[0..15] <<24>>

12

12

1 2

H_CPUSLP#

H_DPRSTP#

2

SIO_A20GATE <<37>>
H_A20M# <<7>>

H_CPUSLP# <<7,10>>
H_DPRSTP# <<7>>

H_DPSLP# <<7>>
H_FERR# <<7>>
H_PWRGOOD <<7>>
H_IGNNE# <<7>>
H_INIT# <<7>>

H_INTR <<7>>

SIO_RCIN# <<36>>
H_NMI <<7>>

H_SMI# <<7>>
H_STPCLK# <<7>>

+VCCP

1

+3VRUN

R472

IDE_DIORDY

H_FERR#

H_DPRSTP#

4.7K_0402_5%~D

R485

56_0402_5%~D

R1205

56_0402_5%~D@

12

+VCCP

12

12

R1248 must be stuff for Dothan-A, no-stuff
for Dothan-B

ICH_AC_BITCLK_TERM

2

C283
10P_0402_50V8J~D

1

@

R511
0_0402_5%~D

1 2

IDE_RST_MOD

A A

+3VRUN

R500

@

1 2

10K_0402_5%~D

IDE_RST_MOD_SFTON

3 1

E

B

2

+5VMOD

R515
1K_0402_5%~D

@

1 2

C

Q64
MMBT3904_SOT23~D@

IDE_RST_MOD_5V <<24>>IDE_RST_MOD<<36>>

SATA_TXN0_C

SATA_TXP0_C

SATA_TXN2_C

SATA_TXP2_C

1 2

C464 3900P_0402_50V7K~D

1 2

C465 3900P_0402_50V7K~D

1 2

C482 3900P_0402_50V7K~D

1 2

C484 3900P_0402_50V7K~D

SATA_TXN0

SATA_TXP0

SATA_TXN2

SATA_TXP2

SATA_TXN0 <<52>>

SATA_TXP0 <<52>>

SATA_TXN2 <<24>>

SATA_TXP2 <<24>>

SATA_RXN0_C

SATA_RXP2_C SATA_RXP2

C461 3900P_0402_50V7K~D

1 2

C463 3900P_0402_50V7K~D

1 2

C467 3900P_0402_50V7K~D

1 2

C469 3900P_0402_50V7K~D

1 2

SATA_RXN0

SATA_RXP0SATA_RXP0_C

SATA_RXN2SATA_RXN2_C

SATA_RXN0 <<52>>

SATA_RXP0 <<52>>

SATA_RXN2 <<24>>

SATA_RXP2 <<24>>

Near Device side.Near ICH6 side.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ICH6(2/4)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

21 61Monday, February 09, 2004

1

0.3

5

D D

+3VSUS

R245

10K_0402_5%~D

ICH_SMBDATA<<6,33>>

ICH_SMBCLK<<6,33>>

C C

+3VSUS

12

12

R475

10K_0402_5%~D

10K_0402_5%~D

R496

10K_0402_5%~D

R486

1 2

1 2

ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK0
ICH_SMLINK1

(PCI Express Wake Event)

+3VRUN

B B

CK_14M_ICH<<6>>

R241

100K_0402_5%~D

CK_48M_ICH<<6>>

1 2

1K_0402_5%~D

12

@

+3VRUN

@

DPRSLPVR<<49>>

A A

R460

KAPALUA system can't boot issue
May need pulldown for DPRSLPVR in case

the ICH6m does not set this value in time
for boot.

5

CLKRUN#

CK_14M_ICH

CK_48M_ICH

R260

@

@

C257

R265

@

1 2

1 2

10_0402_5%~D

10_0402_5%~D

CK_14M_ICH_TERM

CK_48M_ICH_TERM

@

2

2

C270

1

1

4.7P_0402_50V8C~D

4.7P_0402_50V8C~D

12

R35
10K_0402_5%~D

+3VSUS

+3VSUS

+3VSUS

+3VSUS

+3VSUS

4

12

33_0402_5%~D

R1164

SPKR<<25>>

PM_BMBUSY#<<10>>

+3VRUN

SIO_EXT_SMI#<<36>>

SIO_EXT_WAK#<<36>>

SIO_EXT_SCI#<<36>>

H_STP_PCI#<<6>>

H_STP_CPU#<<6,49>>

R945 10K_0402_5%~D@

+3VSUS

R918
10K_0402_5%~D

1 2

R919
10K_0402_5%~D

1 2

R920
10K_0402_5%~D

1 2

R921
10K_0402_5%~D

1 2

R923
680_0402_5%~D

1 2

4

PLTRST_DELAY#<<20>>

CLKRUN#<<31,33,36>>

ICH_PCIE_WAKE#<<18,36>>

IRQ_SERIRQ<<29,31,36>>

SIO_THRM#<<36>>

IMVP_PWRGD<<10,42,49>>

SIO_SLP_S3#<<36>>
SIO_SLP_S5#<<36>>

ICH_PWRGD<<39,42>>

SIO_PWRBTN#<<36>>

SUSPWROK<<32,39,42>>

LINKALERT#

SYS_RESET#

USB2P0_SMI#

ICH_BATLOW#

ICH_PCIE_WAKE#

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR

SYS_RESET#
PM_BMBUSY#

R1168 10K_0402_5%~D

1 2

SIO_EXT_SMI#
USB2P0_SMI#
SIO_EXT_WAK#

SIO_EXT_SCI#
H_STP_PCI#

H_STP_CPU#

LCD_BIST_EN
PLTRST_DELAY#

CLKRUN#

IRQ_SERIRQ
SIO_THRM#
IMVP_PWRGD
CK_14M_ICH
CK_48M_ICH

ICH_SUSCLK

SIO_SLP_S3#
SIO_SLP_S5#
ICH_PWRGD
DPRSLPVR
ICH_BATLOW#
SIO_PWRBTN#
PLTRST#
SUSPWROK

+3VRUN

+3VRUN

+3VRUN

3

+3VSUS

12

R239

10K_0402_5%~D

12

R243

R922

8.2K_0402_5%~D

1 2

R924
10K_0402_5%~D

1 2

R926
10K_0402_5%~D

1 2

3

AF17
AE18
AF18
AG18

AG21

AD19
AE19

AC21
AB21
AD22

AD20
AD21

AF19
AF20
AC18

AB20
AC20
AF21

AE20

U59C

T2

Y4

W5

Y5
W4
U6

F8
W3
U2

R1
W6
M2

R6

V3

P5
R3

T3

U5

E10
A27

V6

T4

T5

T6

AA1

V2
U1

V5

Y3

10K_0402_5%~D

RI#
SATA[0]GP/GPI[26]

SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

SUS_STAT#/LPCPD#
SYS_RESET#
BM_BUSY#/GPI[6]
GPI[7]

GPI[8]
SMBALERT#/GPI[11]
GPI[12]

GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]

GPO[21]
GPO[23]

GPIO[24]
GPIO[25]

GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

WAKE#
SERIRQ
THRM#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
RSMRST#

SIO_THRM#

MCH_SYNC#

IRQ_SERIRQ

H25

PERn[1]

H24

PERp[1]

G27

PETn[1]

G26

PETp[1]

K25

PERn[2]

K24

PERp[2]

J27

PETn[2]

J26

PETp[2]

M25

PERn[3]

M24

PERp[3]

L27

PETn[3]

GPIO

DMI_ZCOMP
DMI_IRCOMP
OC[4]#/GPI[9]

OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

CLOCK

USB

POWER MGT

ICH6_BGA609~D

L26

PETp[3]

P24

PERn[4]

P23

PERp[4]

N27

PCI-EXPRESSDIRECT MEDIA INTERFACE

PETn[4]

N26

PETp[4]

T25

DMI[0]RXN

T24

DMI[0]RXP

R27

DMI[0]TXN

R26

DMI[0]TXP

V25

DMI[1]RXN

V24

DMI[1]RXP

U27

DMI[1]TXN

U26

DMI[1]TXP

Y25

DMI[2]RXN

Y24

DMI[2]RXP

W27

DMI[2]TXN

W26

DMI[2]TXP

AB24

DMI[3]RXN

AB23

DMI[3]RXP

AA27

DMI[3]TXN

AA26

DMI[3]TXP

AD25

DMI_CLKN

AC25

DMI_CLKP

F24
F23
C23

D23
C25
C24

C27

OC[0]#

B27

OC[1]#

B26

OC[2]#

C26

OC[3]#

C21

USBP[0]N

D21

USBP[0]P

A20

USBP[1]N

B20

USBP[1]P

D19

USBP[2]N

C19

USBP[2]P

A18

USBP[3]N

B18

USBP[3]P

E17

USBP[4]N

D17

USBP[4]P

B16

USBP[5]N

A16

USBP[5]P

C15

USBP[6]N

D15

USBP[6]P

A14

USBP[7]N

B14

USBP[7]P

A22

USBRBIAS#

B22

USBRBIAS

ICH_RI#

12

10K_0402_5%~D

R242

Check List suggest pop
10/16

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PCIE_TXN1_C
PCIE_TXP1_C

DMI_RXN0
DMI_RXP0
DMI_TXN0

DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1

DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2

DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3

DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP

USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USBP0­USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

2

PCIE_RXN1 <<29>>
PCIE_RXP1 <<29>>

DMI_RXN0 <<10>>

DMI_RXP0 <<10>>
DMI_TXN0 <<10>>
DMI_TXP0 <<10>>

DMI_RXN1 <<10>>

DMI_RXP1 <<10>>
DMI_TXN1 <<10>>
DMI_TXP1 <<10>>

DMI_RXN2 <<10>>

DMI_RXP2 <<10>>
DMI_TXN2 <<10>>
DMI_TXP2 <<10>>

DMI_RXN3 <<10>>

DMI_RXP3 <<10>>
DMI_TXN3 <<10>>
DMI_TXP3 <<10>>

R471 24.9_0603_1%~D

1 2

1 2

22.6_0603_1%~D

2

CLK_PCIE_ICH# <<6>>
CLK_PCIE_ICH <<6>>

+1.5VRUN

USBP0- <<27>>
USBP0+ <<27>>
USBP1- <<27>>
USBP1+ <<27>>
USBP2- <<27>>
USBP2+ <<27>>
USBP3- <<31>>
USBP3+ <<31>>
USBP4- <<27>>
USBP4+ <<27>>
USBP5- <<27>>
USBP5+ <<27>>
USBP6- <<27>>
USBP6+ <<27>>
USBP7- <<27>>
USBP7+ <<27>>

R540

1

C982

0.1U_0402_16V4Z~D

1 2

1 2

C983

0.1U_0402_16V4Z~D

USB_OC4#
USB_OC5#
USB_OC2#
USB_OC3#

USB_OC0#
USB_OC1#
USB_OC6#
USB_OC7#

PCIE_TXN1 <<29>>
PCIE_TXP1 <<29>>

RN120

10K_1206_8P4R_5%~D

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

RN131

10K_1206_8P4R_5%~D

USB_OC5# <<27>>
USB_OC4# <<27>>

+3VSUS

USB_OC0# <<24>>
USB_OC6# <<27>>PLTRST#<<20>>

USB_OC7# <<27>>

DELL CONFIDENTIAL/PROPRIETARY

Title

ICH6(3/4)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

22 61Monday, February 09, 2004

1

0.3

5

Near PIN F27(C968),

L170
BLM21PG600SN1D_0805~D

1 2

+3VRUN

+5VRUN

1 2

1 2

21

D16
RB751V_SOD323~D

@

2

C254
1U_0805_10V6K~D

1

+3VSUS+5VSUS

21

D28

2

C285
1U_0805_10V6K~D

1

D D

C C

R256

1K_0402_5%~D@

R297

10_0402_5%~D@

+1.5VRUN

ICH_V5REF_RUN

2

C260

0.1U_0402_16V4Z~D

1

RB751V_SOD323~D@

ICH_V5REF_SUS

2

C284

0.1U_0402_16V4Z~D

1

+1.5VRUN_L

2

C916

0.1U_0402_16V4Z~D

1

P27(C949), AB27(C950)

1

+

C585

2

220U_D2_4M_R45~D

Replacing by this circuit?

Near PIN AG5

Near PIN AG9

C962

Near PIN
E26, E27

+1.5VRUN

+1.5VRUN

+1.5VRUN

2

1

0.1U_0402_16V4Z~D

+3VSUS

Near PIN A17

ICH_V5REF_RUN

R1077
10_0402_5%~D

ICH_V5REF_SUS

R1078
10_0402_5%~D

+3VRUN

L78

ICH6_VCCPLL_R ICH6_VCCPLL

BLM11A601S_0603~D

1 2

1

2

C937

C621

5

0.1U_0402_16V4Z~D

1

2

0.01U_0402_16V7K~D

Near PIN
AB27

R1204
1_0603_5%~D

1 2

1 2

1 2

+5VSUS

+5VALW

B B

+1.5VRUN

A A

4

2

2

C968

C950

1

1

0.1U_0402_16V4Z~D

C964

C1241

2

C973

1

0.1U_0402_16V4Z~D

Near PIN AE1

2

C267

1

0.1U_0402_16V4Z~D

4

2

C949

1

0.1U_0402_16V4Z~D

2

1

0.1U_0402_16V4Z~D

2

1

0.1U_0402_16V4Z~D

ICH6_VCCPLL

+3VRUN

+3VRUN

+3VSUS

2

C638

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

U59E

AA22

VCC1_5[1]

AA23

VCC1_5[2]

AA24

VCC1_5[3]

AA25

VCC1_5[4]

AB25

VCC1_5[5]

AB26

VCC1_5[6]

AB27

VCC1_5[7]

F25

VCC1_5[8]

F26

VCC1_5[9]

F27

VCC1_5[10]

G22

VCC1_5[11]

G23

VCC1_5[12]

G24

VCC1_5[13]

G25

VCC1_5[14]

H21

VCC1_5[15]

H22

VCC1_5[16]

J21

VCC1_5[17]

J22

VCC1_5[18]

K21

VCC1_5[19]

K22

VCC1_5[20]

L21

VCC1_5[21]

L22

VCC1_5[22]

M21

VCC1_5[23]

M22

VCC1_5[24]

N21

VCC1_5[25]

N22

VCC1_5[26]

N23

VCC1_5[27]

N24

VCC1_5[28]

N25

VCC1_5[29]

P21

VCC1_5[30]

P25

VCC1_5[31]

P26

VCC1_5[32]

P27

VCC1_5[33]

R21

VCC1_5[34]

R22

VCC1_5[35]

T21

VCC1_5[36]

T22

VCC1_5[37]

U21

VCC1_5[38]

U22

VCC1_5[39]

V21

VCC1_5[40]

V22

VCC1_5[41]

W21

VCC1_5[42]

W22

VCC1_5[43]

Y21

VCC1_5[44]

Y22

VCC1_5[45]

AA6

VCC1_5[46]

AB4

VCC1_5[47]

AB5

VCC1_5[48]

AB6

VCC1_5[49]

AC4

VCC1_5[50]

AD4

VCC1_5[51]

AE4

VCC1_5[52]

AE5

VCC1_5[53]

AF5

VCC1_5[54]

AG5

VCC1_5[55]

AA7

VCC1_5[56]

AA8

VCC1_5[57]

AA9

VCC1_5[58]

AB8

VCC1_5[59]

AC8

VCC1_5[60]

AD8

VCC1_5[61]

AE8

VCC1_5[62]

AE9

VCC1_5[63]

AF9

VCC1_5[64]

AG9

VCC1_5[65]

AC27

VCCDMIPLL

E26

VCC3_3[1]

AE1

VCCSATAPLL

AG10

VCC3_3[22]

A13

VCCLAN3_3/VCCSUS3_3[1]

F14

VCCLAN3_3/VCCSUS3_3[2]

G13

VCCLAN3_3/VCCSUS3_3[3]

G14

VCCLAN3_3/VCCSUS3_3[4]

A11

VCCSUS3_3[1]

U4

VCCSUS3_3[2]

V1

VCCSUS3_3[3]

V7

VCCSUS3_3[4]

W2

VCCSUS3_3[5]

Y7

VCCSUS3_3[6]

A17

VCCSUS3_3[7]

B17

VCCSUS3_3[8]

C17

VCCSUS3_3[9]

F18

VCCSUS3_3[10]

G17

VCCSUS3_3[11]

G18

VCCSUS3_3[12]

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]

COREIDE

VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]

PCI/IDE RBP

VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

VCC3_3[11]
VCC3_3[10]

VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]

PCIUSB

VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

VCCSUS1_5[3]
VCCSUS1_5[2]

VCCSUS1_5[1]

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]

USB CORE

VCC1_5[69]
VCC1_5[68]

VCC1_5[67]

VCC2_5[4]
VCC2_5[2]

V5REF_SUS
VCCUSBPLL

VCCSUS3_3[20]

V_CPU_IO[3]
V_CPU_IO[2]
V_CPU_IO[1]

VCCSUS3_3[19]
VCCSUS3_3[18]
VCCSUS3_3[17]
VCCSUS3_3[16]
VCCSUS3_3[15]
VCCSUS3_3[14]
VCCSUS3_3[13]

ICH6_BGA609~D

PCIE

SATA

VCCLAN1_5/VCCSUS1_5[2]
VCCLAN1_5/VCCSUS1_5[1]

V5REF[2]
V5REF[1]

VCCRTC

3

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

U7
R7

G19
G20

F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

G8
AB18

P7
AA18

A8
F21
A25

A24
AB3
G11

G10
AG23

AD26
AB22

G16
G15
F16
F15
E16
D16
C16

+1.5VRUN

2

C255

1

2

C227

1

+1.5VSUS

1

2

C234

0.1U_0402_16V4Z~D

+1.5VRUN

ICH_V5REF_RUN

ICH_V5REF_SUS

+1.5VRUN
+3VSUS

+RTC_CELL

+1.5VRUN

+VCCP

1

2

C237

0.1U_0402_16V4Z~D

2

C277

1

0.1U_0402_16V4Z~D

2

C963

1

0.1U_0402_16V4Z~D

Near PIN U7

Near PIN AG23

+3VRUN

Near PIN
AG13, AG16

0.1U_0402_16V4Z~D

+3VRUN

2

C957

1

Near PIN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

A2-A6, D1-H1

2

1

1

2

C961

0.1U_0402_16V4Z~D

+2.5VRUN

1

2

Near PIN AB18

+3VRUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C265

0.1U_0402_16V4Z~D

C975

C253

1 2

C235

1 2

+1.5VRUN

+1.5VSUS

0.1U_0402_16V4Z~D

@

2

C582

0.1U_0402_16V4Z~D

1 2

C583

0.1U_0402_16V4Z~D

1 2

C252

0.1U_0402_16V4Z~D

1 2

C231

0.1U_0402_16V4Z~D

1 2

C236

0.1U_0402_16V4Z~D

1 2

C251

0.1U_0402_16V4Z~D

1 2

C229

0.1U_0402_16V4Z~D

1 2

C232

0.1U_0402_16V4Z~D

1 2

C958

0.1U_0402_16V4Z~D

1 2

C967

0.1U_0402_16V4Z~D

1 2

C970

0.01U_0402_16V7K~D

1 2

Near PIN A25

C952

0.01U_0402_16V7K~D

1 2

Near PIN AA19

+3VSUS

C226

0.1U_0402_16V4Z~D

1 2

C665

0.1U_0402_16V4Z~D

1 2

C264

0.1U_0402_16V4Z~D

1 2

C266

0.1U_0402_16V4Z~D

1 2

Near PIN A24

Near PIN AG10

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

1

U59D

E27

Y6
Y27
Y26
Y23
W7

W25
W24
W23

W1

V4
V27
V26
V23

U25
U24
U23
U15
U13

T7

T27
T26
T23
T16
T15
T14
T13
T12

T1

R4

R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12

N7

N17
N16
N15
N14
N13
N12
N11

N1

M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13

K7
K27
K26
K23

K1

J4
J25
J24
J23

H27
H26
H23

G9

G7
G21
G12

G1

ICH6_BGA609~D

VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

+RTC_CELL

1

2

C976

0.1U_0402_16V4Z~D

1

2

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]

VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

C977

0.1U_0402_16V4Z~D

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

DELL CONFIDENTIAL/PROPRIETARY

Title

ICH6(4/4)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

23 61Monday, February 09, 2004

1

0.3

5

IDE_DD[0..15]<<21>>

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9

IDE_RST_MOD_5V<<21>>

+3VALW

IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DDACK#
IDE_DIOR#

IDE_DIOW#
IDE_DIORDY
RDDREQ
IDE_IRQ

USB_IDE#<<36>>

IDE_RST_MOD_5V

R105

100K_0402_5%~D

1 2

BAY_MODPRES#<<36>>

+3VALW

SATA_RXP2<<21>>
SATA_RXN2<<21>>

SATA_TXP2<<21>>
SATA_TXN2<<21>>

R75

1 2

470_0603_5%~D

R102

33_0402_5%~D

1 2

1 2

100K_0402_5%~D

R111

D D

IDE_DA[0..2]<<21>>

IDE_DCS1#<<21>>
IDE_DCS3#<<21>>

IDE_DDACK#<<21>>
IDE_DIOR#<<21>>

IDE_DIOW#<<21>>
IDE_DIORDY<<21>>

RDDREQ<<21>>
IDE_IRQ<<20,21>>

C C

B B

4

SATA_RXP2
SATA_RXN2

SATA_TXP2
SATA_TXN2

IDE_DCS3#
IDE_DA2
IDE_DA0
IDE_DA1

CSEL2
IDE_DIOR#
IDE_DIOW#
IDE_DD15

IDE_DD1
IDE_DD2
IDE_DD12
IDE_DD11

IDE_DD5
IDE_DD6
IDE_DD8
MOD_RST
USB_IDE#
CD_AUDIORET
BAY_MODPRES#

3

JP6

69

72

G71G

M1

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68

M2

G73G

70

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

DASP#

25

25

27

27

29

29

PDIAG#

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

74

SATA_DET#
MOD_PIN15

USBP0_D+
USBP0_D-

IDE_DCS1#

IDE_IRQ
IDE_DDACK#
IDE_DIORDY

RDDREQ
IDE_DD0
IDE_DD14
IDE_DD13

IDE_DD3
IDE_DD4
IDE_DD10
IDE_DD9

IDE_DD7

INT_CD_R
INT_CD_L

@

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68

1

C693

@

2

0.1U_0402_16V4Z~D

JAE_WM1F068N1A~D

C108

0.1U_0402_16V4Z~D

1

2

@

1

C69

C73

2

4.7U_1206_16V6K~D

0.1U_0402_16V4Z~D

R54 0_0402_5%~D

1

C97

2

0.1U_0402_16V4Z~D

+5VMOD +3VMOD

1

1

2

2

C1188

C1187

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

SATA_DET# <<36>>

USB_OC4#

12

1

2

C74

0.1U_0402_16V4Z~D

USB_OC0# <<22>>

2

1

1

C72

2

2

0.1U_0402_16V4Z~D

USBP0_D+ <<27>>
USBP0_D- <<27>>

1

1

2

3

6

WF1F068N1A

4

5

TOP VIEW

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

DVD MODULE

Size Document Number Rev

Board Number LA2111

Date: Sheet of

24 61Monday, February 09, 2004

1

0.3

5

+5VSUS

2

1

1

C651

D D

C C

B B

A A

2

0.1U_0402_16V4Z~D@

ICH_SDOUT_AUDIO

R264

47_0402_5%~D @

1 2

ICH_AC_SDOUT_TERM

1

C262
22P_0402_50V8J~D

2

@

C647

0.01U_0402_16V7K~D @

ICH_RST_AUDIO#

ICH_SYNC_AUDIO

ICH_SDOUT_AUDIO

ICH_AC_BITCLK<<21>>

MDC_AC_BITCLK<<28>>

ICH_AC_SDIN0<<21>>

C643

2

1U_0805_10V6K~D@

1

@

12

CK_14M_CODEC_TERM

1

2

5

AUDIO_AVDD_ON<<37>>

C1267
10P_0402_50V8J~D@

1 2

C1268
10P_0402_50V8J~D@

1 2

C1269
10P_0402_50V8J~D@

1 2

1

C274

C273

2

@

27P_0603_50V8J~D

2

C658

1

2.2U_0805_16VFZ~D

CK_14M_CODEC

R1060
33_0402_5%~D@

C27

22P_0402_50V8J~D@

33_0402_5%~D

AUDIO_AVDD_ON TPS793475_BYPASS

R763

1 2

R284

33_0402_5%~D

1 2

R285

33_0402_5%~D

1 2

1

2

27P_0603_50V8J~D

2

CK_14M_CODEC<<6>>

0.1U_0402_16V4Z~D

2

C655

1

1

0.1U_0402_16V4Z~D

C652

U62

IN1OUT

2

GND
EN3BYPASS

TPS793333DBVR_SOT23-5~D

@

Note : C281, C282 close
Pin1 and Pin9.
12/12 Bill

+3VRUN

2

C281

1

0.1U_0402_16V4Z~D

ICH_RST_AUDIO#<<21>>
ICH_SYNC_AUDIO<<21>>
ICH_SDOUT_AUDIO<<21>>

C653 820P_0603_50V7K~D

1 2

C654 820P_0603_50V7K~D

1 2

C650 0.1U_0603_16V7K~D

1 2

@

SPK_SHUTDOWN#<<26>>

SPDIF_SHDN<<19,36>>

SPDIF<<19>>
EAPD<<26>>

22P for
Crystal Only

C1055

@

1 2

22P_0402_50V8J~D

C1056

@

1 2

22P_0402_50V8J~D

R927

0_0402_5%~D

1 2

12

C282

XTL_24M-

X7

24.576 MHz_20P_1BX24576CC1A~D

XTL_24M+

4

5

4

2

2

C280

1

1

0.1U_0402_16V4Z~D

2.2U_0805_16VFZ~D

@

ICH_RST_AUDIO#
ICH_SYNC_AUDIO
ICH_SDOUT_AUDIO

R_ICH_AC_BITCLK

R_ICH_AC_SDIN0

AFLT1
AFLT2
VREFOUT
AC97VREFI

CAP2
SPK_SHUTDOWN#

SPDIF_SHDN

SPDIF
EAPD

12

R764
10K_0402_5%~D

R553
1K_0402_5%~D@

1 2
1 2

R552
1K_0402_5%~D@

@

PACKAGE : 8X4.5X1.5mm

XTL_24M-

4

1

C645

2

0.1U_0402_16V4Z~D@

W=30 mil

11
10

29
30
28
27

32
43

44

48
47

31

33

34
46

45

12

R37
0_0402_5%~D

U9

RESET#
SYNC

5

SDATA_OUT

6

BIT_CLK

8

SDATA_IN

AFLT1
AFLT2
VREFOUT
VREF

CAP2
GPIO0/NC

GPIO1/NC

SPDIF
EAPD

NC/BPCFG

NC/FLTIN

NC/FLTOUT
CID1

CID0

3

XTL_OUT

2

XTL_IN

VDDA=3.3V

12

R792

C648

102K_0603_1%~D@

12

0.1U_0402_16V4Z~D

R793

280K_0603_0.1%~D@

9

DVDD11DVDD2

STAC9751

DVSS14DVSS2

7

3

VDDA

1 2

1

1

1

2

C649

C36

2

2.2U_0805_16VFZ~D

0.1U_0402_16V4Z~D

1

C44

2

2

0.047U_0402_16V4Z~D

+3VRUN

L10

BLM31A260SPT_1206~D

SN74LVC2G86DCTR_SSOP8~D

U57A

SPKR<<22>>

BEEP<<36>>

CBS_SPK<<31>>

1

1A

2

1B

VDDA

L76
BLM11A121S_0603~D

1 2

8

P

7

1Y

G

4

2

Z2401

Z2402

8

5

P

2A

2Y

6

2B

G

U57B

4

SN74LVC2G86DCTR_SSOP8~D

1

C612

0.1U_0402_16V4Z~D

2

3

R530

10K_0402_5%~D

1 2

1

single gate TTL

R531

C618

0.1U_0402_16V4Z~D

1 2

12

Z2404Z2403 PC_BEEP

8.2K_0402_5%~D

@

2

45

31

2

C619
1000P_0402_50V7K~D

1

@

TRACE>15 mil

VDDA

38

23

LINE_IN_L

AVDD125AVDD2

AVSS126AVSS2

42

24

LINE_IN_R

18

CD_L

19

CD_GND

20

CD_R

14

AUX_L

15

AUX_R

21

MIC1

22

MIC2

16

VIDEO_L

17

VIDEO_R

13

PHONE

12

PC_BEEP

39

HP_OUT_L

40

HP_COMM

41

HP_OUT_R

37

MONO_OUT

35

LOUT_L

36

LOUT_R

STAC9751TG_TQFP48~D

CNB_MICIN

BPASS_GND

PC_BEEP

HP_OUT_L

HP_COMM

HP_OUT_R

C642

0.22U_0603_10V7M~D

1 2

C1053

1 2

0.1U_0402_16V4Z~D

Noise Concem, Keep it.

C1054

1 2

0.1U_0402_16V4Z~D

1 2

R1079
0_0402_5%~D

2

C656
1000P_0402_50V7K~D

1

2

C657
1000P_0402_50V7K~D

1

NB_MICIN <<26>>

HP_OUT_L <<26>>

HP_OUT_R <<26>>

AUD_LINE_OUT_L <<26>>

AUD_LINE_OUT_R <<26>>

CLOCK SOURCE

14.318 MHz
27 MHz
48 MHz

24.576 MHz

Pin46
CID1

OPEN

1K

Pin45
CID0

OPENOPEN

1K

OPEN

1K1K

Pin3
XTL_OUT

GND
GND
GND
GND

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

AC97

Size Document Number Rev

Board Number LA2111

Date: Sheet of

25 61Monday, February 09, 2004

1

0.3

5

INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2

D D

C C

B B

A A

1

2

C1284

0.1U_0402_16V4Z~D

HP_OUT_R<<25>>
HP_OUT_L<<25>>

SPK_SHUTDOWN#<<25>>

1

2

C1285

0.1U_0402_16V4Z~D

SPK_SHUTDOWN#

EAPD<<25>>

C1286

2

G

1

2

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

1 2
1 2

1U_0603_10V6K~D

+3VRUN

R936
100K_0402_5%~D

1 2

13

D

Q110

S

2N7002_SOT23~D

+3VRUN

12

C1058

C1059

1

C1060
1U_0603_10V6K~D

2

1

2

C1287

0.1U_0402_16V4Z~D

R929
10K_0402_5%~D

HP_NB_SENSE

AUD_LINE_IN_R
AUD_LINE_IN_L

HP_NB_SENSE

U152

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

C1061

1U_0603_10V6K~D

AUD_LINE_OUT_R<<25>>

AUD_LINE_OUT_L<<25>>

13

D

2

G

S

4

60mil single end
connection near JACK

TRACE>15 mil

RBAT connector
was removed

+3VRUN

10

19

SVDD

PVDD

PGND

PVss

SVss

SGND

2

5

7

17

1

2

Q111

2N7002_SOT23~D

NB_MUTE<<36>>

COINCELL

1

C1057
1U_0603_10V6K~D

2

11

OUTR

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

MAX4411ETP-T_TQFN20~D

C1066

1 2

0.47U_0603_16V4Z~D
C1067

1 2

0.1U_0603_16V7K~D

C1068

1 2

0.47U_0603_16V4Z~D
C1069

1 2

0.1U_0603_16V7K~D

13

D

2

G

S

2N7002_SOT23~D

Q112

INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1

COINCELL

C1062

0.1U_0402_16V4Z~D

W=40mils

1

2

U18

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

7

JSPK

1

7

1

2

2

3

3

4

4

5

5

6

6

8

MOLEX_53398-0690~D

8

HP_MAX_R
HP_MAX_L

+5VAMPVCC

16

15

6

VDD

PVDD1

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

GND41GND311GND213GND1

TPA6017A2PWPR_TSSOP20~D

20

3

NB_MICIN<<25>>

L48

1 2

BLM21AF121SN1D_0805~D

2
3

18

14

4

8

12

NC

10

1

C1063
10U_0805_10V4M~D

2

AUD_GAIN0
AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

INT_SPK_L1

INT_SPK_L2

BYPASS

1

C1070

0.47U_0603_16V4Z~D

2

R1059
100_0402_5%~D

1 2

1

C1228
1000P_0402_50V7K~D

2

+5VRUN

L45

12

BLM11A121S_0603~D

BLM11A121S_0603~D

BLM11A121S_0603~D

Bypassed the
tantalum
capacitors

1

C1064

0.1U_0402_16V4Z~D

2

Added new
Amplifier, same as
Nimitz

1

C1071

0.1U_0402_16V4Z~D

@

2

C1226

EMICIN

L73

L74

1

C1065

0.1U_0402_16V4Z~D

2

2

1

2

C1227

1000P_0402_50V7K~D

C579

HP_NB_SENSE<<36>>

12
12

LINE OUT

1

2

4.7U_0805_10V4Z~D

2

1

100P_0603_50V8J~D

HP_SPK_R2
HP_SPK_L2

+5VRUN

C580

12

R1057

1.33K_0603_1%~D

12

L11
BLM11A121S_0603~D

12

R1058

1.2K_0402_5%~D

2

1

100P_0603_50V8J~D

2

C584

1

100P_0603_50V8J~D

2

C595

1

100P_0603_50V8J~D

GAIN0 INPUTAV(inv)GAIN1

0
0
1

*

AUD_GAIN0
AUD_GAIN1

1
2
6
3
4
5

1
2
6
3
4
5

1

JMIC

FOX_JA6333L-50T-TR~D

JAUDO

7

8

FOX_JA9333L-10T-TR~D

+5VRUN

12

R932
10K_0402_5%~D

12

R934
10K_0402_5%~D@

6dB

0

10dB

1

15.6dB

0

21.6dB

11

Gain Setting

12

R933
10K_0402_5%~D@

12

R935
10K_0402_5%~D

IMPEDANCE

90K ohm
70K ohm
45K ohm
25K ohm

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

AMP and PHONE JACK

Size Document Number Rev

Board Number LA2111

Date: Sheet of

26 61Monday, February 09, 2004

1

0.3

5

USBP0-<<22>>

USBP0+<<22>>

D D

C C

B B

USBP1-<<22>>

USBP1+<<22>>

USBP2-<<22>>

USBP2+<<22>>

CBS_CAD13<<31>>

CBS_CAD15<<31>>

USBP4-<<22>>

USBP4+<<22>>

USBP5-<<22>>

USBP5+<<22>>

USBP6-<<22>>

USBP6+<<22>>

USBP7+<<22>>

USBP7-<<22>>

@

L21 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L41 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L22 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L23 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L28 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L13 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L129 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

L131 DLW21SN900SQ2_0805~D

1

1

4

4

0_0402_5%~D

1 2

0_0402_5%~D

1 2

R348

R349

@

R350

R351

@

R352

R353

@

R354

R355

@

R356

R357

@

R358

R359

@

R890

R891

@

R950

R951

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

1

C22
47P_0402_50V8J~D

2

@

1

C169
47P_0402_50V8J~D

2

@

1

C24
47P_0402_50V8J~D

2

@

1

C26
47P_0402_50V8J~D

2

@

1

C79
47P_0402_50V8J~D

2

@

1

C18
47P_0402_50V8J~D

2

@

1

C990
47P_0402_50V8J~D

2

@

1

C1077
47P_0402_50V8J~D

2

@

4

1

C21
47P_0402_50V8J~D

2

@

1

C161
47P_0402_50V8J~D

2

@

1

C23
47P_0402_50V8J~D

2

@

1

C25
47P_0402_50V8J~D

2

@

1

C75
47P_0402_50V8J~D

2

@

1

C19
47P_0402_50V8J~D

2

@

1

C991
47P_0402_50V8J~D

2

@

1

C1078
47P_0402_50V8J~D

2

@

USBP0_D-

USBP0_D+

PLACE CHOKE
NEAR
CONNECTOR

USBP1_D-

USBP1_D+

USBP2_D-

USBP2_D+

CBS_CAD13_L

CBS_CAD15_L

USBP4_D-

USBP4_D+

USBP5_D-

USBP5_D+

USBP6_D-

USBP6_D+

USBP7_D+

USBP7_D-

USBP0_D- <<24>>

USBP0_D+ <<24>>

USBP1_D- <<35>>

USBP1_D+ <<35>>

USBP2_D- <<28>>

USBP2_D+ <<28>>

CBS_CAD13_L <<32>>

CBS_CAD15_L <<32>>

USBP4_PWR

USBP5_PWR

3

BLM21PG600SN1D_0805~D

1 2

1 2

BLM21PG600SN1D_0805~D

USBP6_PWR

USBP7_PWR

L58

L60

L63

BLM21PG600SN1D_0805~D

1 2

1 2

L127

BLM21PG600SN1D_0805~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

C304

150U_D_6.3VM_R55~D

C300

150U_D2_6.3VM~D

C330

C1216

1

+

2

1

+

2

+5VSUS

1

2

+5VSUS

1

2

C302

0.1U_0402_16V4Z~D

C301

0.1U_0402_16V4Z~D

C329

150U_D_6.3VM_R55~D

C988

150U_D_6.3VM_R55~D

1

2

1

2

1

+

C321

2

1

+

C989

2

1

C331
10U_1206_16V4Z~D

2

1

2

USBP4_VCC
USBP4_D­USBP4_D+

USBP5_VCC
USBP5_D­USBP5_D+

1

2

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

USB_BACK_EN#<<36>>

USB_SIDE_EN#<<36>>

C1
10U_1206_16V4Z~D

2

USBP6_VCC
USBP6_D­USBP6_D+

USBP7_VCC
USBP7_D­USBP7_D+

JUSB1

A1

A_VCC

A2

A_D-

A3

A_D+

A4

A_GND

B1

B_VCC

B2

B_D-

B3

B_D+

B4

B_GND

9

G1

10

G2

11

G3

12

G4

FOX_UB11123-8Z1-TR~D

A1
A2
A3
A4

B1
B2
B3
B4

9
10
11
12

USB_BACK_EN#

USB_SIDE_EN#

USB PORT#

JUSB2

A_VCC
A_D­A_D+
A_GND

B_VCC
B_D­B_D+
B_GND

G1
G2
G3
G4

FOX_UB11123-8Z1-TR~D

U155

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

U156

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

1

DESTINATION

0
1
2

FDD (module bay)

DOCK

MPCI (BlueTooth)
3 NEW Connector
4
5

USB Port 1(Top)

USB Port 1(Bottom)

6 USB Port 2(Top)
7

OC1#
OUT1
OUT2
OC2#

OC1#
OUT1
OUT2
OC2#

USB Port 2(Bottom)

USB_OC4#

8
7
6
5

8
7
6
5

USB_OC5#

USB_OC6#

USB_OC7#

USB_OC4# <<22>>

USBP4_PWR
USBP5_PWR

USB_OC5# <<22>>

USB_OC6# <<22>>

USBP6_PWR
USBP7_PWR

USB_OC7# <<22>>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

USB 2.0

Size Document Number Rev

Board Number LA2111

Date: Sheet of

27 61Monday, February 09, 2004

1

0.3

5

D D

C1076

0.47U_0603_16V7K~D

1 2

C C

COEX2_WLAN_ACTIVE<<33>>

COEX1_BT_ACTIVE<<33>>

Z3702

C1074

0.1U_0402_16V4Z~D

1 2

TXD0<<36>>
RTS0#<<36>>
DTR0#<<36>>
DCD0#<<36>>

RXD0<<36>>
CTS0#<<36>>
DSR0#<<36>>

+5VSUS

5NC1

U154

P

4

A2Y

G

SN74AHCT1G04DCKR_SC70-5~D@

3

COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE

3243C1+

3243C1­3243C2+

3243C2­TXD0
RTS0#
DTR0#
DCD0#

RXD0
CTS0#
DSR0#

+5VSUS

RUN_ON<<18,36,41,42,45,46,48>>

RI0# <<36>>

U153

28

C1+

24

C1-

1

C2+

2

C2-

14

T1IN

13

T2IN

12

T3IN

19

R1OUT

18

R2OUT

17

R3OUT

16

R4OUT

15

R5OUT

20

R2OUTB

23

FORCEON

22

FORCEOFF#

MAX3243CAI_SSOP28~D

HW_RADIO_DIS#<<33,37>>

Place near BT

B B

ICH_AC_SDIN1<<21>>

A A

ICH_SDOUT_MDC

ICH_SYNC_MDC

ICH_RST_MDC#

R235

33_0402_5%~D

1 2

C1270
10P_0402_50V8J~D@

1 2

C1271
10P_0402_50V8J~D@

1 2

C1272
10P_0402_50V8J~D@

1 2

ICH_SDOUT_MDC<<21>>
ICH_SYNC_MDC<<21>>
ICH_RST_MDC#<<21>>

ICH_SDOUT_MDC
ICH_SYNC_MDC

MDC_SDIN
ICH_RST_MDC#

4

+5VSUS

1

C1072

0.1U_0402_16V4Z~D

2

26

3243V+

27

VCC

V+

T1OUT
T2OUT
T3OUT

R1IN
R2IN
R3IN
R4IN
R5IN

INVALID#

GND

BT_ACTIVE<<40>>

USBP2_D-<<27>>
USBP2_D+<<27>>

1
3
5
7
9

11

3

V-

9
10
11
4
5
6
7
8

21
25

0.1U_0402_16V4Z~D

HW_RADIO_DIS#
COEX3

USBP2_D­USBP2_D+

JMDC

GND1
IAC_SDATA_OUT
GND2
IAC_SYNC
IAC_SDATA_IN
IAC_RESET#

3243V-

TXD0#
RTS0
DTR0
DCD0
RI0
RXD0#
CTS0
DSR0

131314141515161617171818191920

0.47U_0603_16V7K~D

0.47U_0603_16V7K~D

C669

R765

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

20

C1073

1 2

C1075

1 2

+3VRUN

1

2

10

9
8
7
6
5
4
3
2
1

12

10K_0402_5%~D

2
4
6
8
10
12

TYCO_1-179397-2~D

JBT

10
9
8
7

12

6

12

11

5

11
4
3
2
1

JST_BM10B-SRSS-TB~D

W=20 mil

MDC_AC_BITCLK

Connector for MDC Rev1.5

3

R937

RTS0

TXD0#

DTR0

33_0402_5%~D

1 2

R938

33_0402_5%~D

1 2

R939

33_0402_5%~D

1 2

2

DCD0
DSR0
RXD0#
RTS0F
TXD0F#
CTS0
DTR0F
RI0

CN13

270P_1206_8P4C_50V8K~D

4 5
3 6
2 7
1 8

CN14

270P_1206_8P4C_50V8K~D

4 5
3 6
2 7
1 8

1

JSIO

1

1

6

6

2

2

7

7

3

3

8

8

4

4

9

9

5

5

12

12

13

13

10

10

11

11

FOX_DS00191-WH37~D

TOP view

1

1 2453

single gate TTL

10

FOX_HS6210_10P

ICH_SDOUT_MDC
MDC_AC_BITCLK

R236

10_0402_5%~D@

C224

10P_0402_50V8J~D@

New MDC connector.

1

R484

1 2

1 2

10_0402_5%~D@

MDC_AC_BITCLK_TERM

ICH_AC_SDOUT_MDCTERM

2

2

C590

10P_0402_50V8J~D@

1

1

GND

3

IAC_SDATA0

5

GND

7

IAC_SYNC

9

IAC_SDATAIN

11 12

IAC_RESET#

IAC_BITCLK

RES
RES

3.3V
GND
GND

2
4
6
8
10

C588

+3VSUS

1

2

4.7U_1206_16V6K~D

MDC_AC_BITCLK<<25>>

1

C589

2

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

BT PORT and MDC

Size Document Number Rev

Board Number LA2111

Date: Sheet of

28 61Monday, February 09, 2004

1

0.3

5

Layout Notice : Place as close
chip as possible.

+3VSRC

D D

ENAB_3VLAN<<41>>

C C

V_3P3_LAN

V_3P3_LAN

B B

Q104

SI3456DV-T1_TSOP6~D

D

6

S

VAUX_LAN

45
2
1

CK_33M_LOMPCI<<6>>

LPC_LAD[0..3]<<21,36>>

TPM_EN#<<37>>

R1032 0_0402_5%~D@

R1182

4.7K_0402_5%~D

R963 4.7K_0402_5%~D

1 2

G

3

1 2
1 2
1 2

1 2

1 2

5751_SI
SCLK
5751_SO
CS#

LPC_LFRAME#<<21,36>>
PLTRST_LPC#<<20>>
IRQ_SERIRQ<<22,31,36>>

1 2

LAN_SMBCLK<<33>>
LAN_SMBDATA<<33>>

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

R11800_0402_5%~D
R11024.7K_0402_5%~D
R11034.7K_0402_5%~D@
R11044.7K_0402_5%~D@

L132

BLM31A260SPT_1206~D

1 2

K10

M11

L11

K9
L5

H11

M9

L8
L9

J11

N13

G12
H13
G13
D10

D9
K11
L10
E12
E11
F11
C12

H2

J2

A2

2

1

C1082

C1083

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

U164A

LCLK
LAD0
LAD1
LAD2
LAD3
LFRAME
LRESET
SERIRQ
EXPORT
BSAFE_GPIO0
BSAFE_GPIO1

GPIO0_TST_CLKOUT
GPIO1
GPIO2
SMB_CLK
SMB_DATA
EECLK
EEDATA
SI
SCLK
SO
CS

PWR_IND
ATTN_IND
ATTN_BTTN

2

2

1

1

C1085

C1084

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

BCM5751M

BroadSAFE

Msic

Hot Plug

Support

Media

Power

Regulator

PCI-ETEST

LINK_10#

LINK_10#<<30>>

LINK_100#<<30>>
LAN_ACT#<<30>>

+3VRUN

R969

A A

200_0603_1%~D

25MHz_20P_1BX25000CK1A~D

1 2

2

X8

C1122

1

22P_0402_50V8J~D

LINK_100#
LAN_ACT#

XTALI
XTALO

R1035

1 2

4.7K_0402_5%~D

C1121

XTALO

XTALI

2

1

22P_0402_50V8J~D

5

12

X'tal capactiors value fellow Kapalua

@

R1036

A11
B11
A12
B10

A9

B9
C10

P12
N12

F4

1 2

4.7K_0402_5%~D

LINKLED
SPD100LED
SPD1000LED
TRAFFICLED

WL_ACTIVITY
WL_LINK5G
WL_LINK2.4G

XTALI
XTALO

REFCLK_SEL

BCM5751MKFB_FPBGA196~D

LED

Clock

Bias

Layout Notice : No high
speed signal should be
routed near RDAC or on
adjacent layer to RDAC

2

1

C1086

Control

Control

PCIE_TXDN
PCIE_TXDP
PCIE_RXDN
PCIE_RXDP

VAUXPRSNT

2

1

0.1U_0402_16V4Z~D

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

LOW_PWR

VMAIN_ON

VAUX_ON

PERST

REGSUP12

REGCTL12

REGSEN12

REGOUT25
REGSUP25

WAKE

REFCLK-

REFCLK+

TCK
TDO

TMS

TRST

RDAC

4

V_3P3_LAN

TST

TDI

4

E13
E14
D13
D14
C13
C14
B13
B14

L6
N14

M13
C2

K14
J13
J14

M14
L14

P6
N6
N10
P10
A6

P8
N8

J12
D8

D7
H12
D6
C11
D12

A10

MMJT9435

B

1C4

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_TX1+
LAN_TX1­LAN_TX0+
LAN_TX0-

PLTRST_LOM#

REGCTL

PCIE_RXN1_C
PCIE_RXP1_C

PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

LAN_AUXPWR

R965

1 2

1.15K_0603_1%~D

R966

1 2

C

2

E

3

V_3P3_LAN
REGCTL_PNP
V_1P2_LAN

LAN_TX3+ <<30>>
LAN_TX3- <<30>>
LAN_TX2+ <<30>>
LAN_TX2- <<30>>
LAN_TX1+ <<30>>
LAN_TX1- <<30>>
LAN_TX0+ <<30>>
LAN_TX0- <<30>>

LAN_LOW_PWR <<37>>

PLTRST_LOM# <<20>>

R1033 0_0402_5%~D

1 2

V_2P5_LAN
V_3P3_LAN

C1113

0.1U_0402_16V4Z~D

1 2
1 2

C1114

0.1U_0402_16V4Z~D

PCIE_WAKE# <<36>>
CLK_PCIE_LOM# <<6>>
CLK_PCIE_LOM <<6>>

1 2

4.7K_0402_5%~D

4.7K_0402_5%~D

12

R1034

4.7K_0402_5%~D

V_3P3_LAN

0.1U_0402_16V4Z~D

C1120

2

1

R1051

1 2

1_1210_5%~D

Z4011

1

Q113
MMJT9435_SOT223~D

2 3

4

V_3P3_LAN

REGCTL_PNP

V_1P2_LAN

PCIE_RXN1 <<22>>
PCIE_RXP1 <<22>>
PCIE_TXN1 <<22>>
PCIE_TXP1 <<22>>

R964

V_3P3_LAN

U157

8

SO

7

GND

6

VCC

5

WP#

AT45DB011B-SI_SO8~D

3

Layout Notice : 3.3V filter. Place as close
chip as possible.

V_3P3_LAN

V_1P2_LAN

Layout Notice : Place as close
chip as possible.

SI

SCK

RESET#

CS#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1
2
3
4

C1110

C1104

C1098

0.1U_0402_16V4Z~D

2

1

2

1

5751_SO5751_SI
SCLK

CS#

2

1

2

1

V_2P5_LAN

0.1U_0402_16V4Z~D

V_3P3_LAN

0.1U_0402_16V4Z~D

3

0.1U_0402_16V4Z~D

C1100

C1111

C1105

V_3P3_LAN

C1099

C1101

2

1

2

1

R970

4.7U_0805_10V4Z~D

2

1

10U_0805_10V4M~D

2

1

22U_1206_10V4Z~D

C1291

4.7U_0805_10V4Z~D

V_3P3_LAN

12

1K_0402_5%~D

V_3P3_LAN

V_1P2_LAN

Layout Notice : Filter place as close
chip as possible.

22U_1206_10V4Z~D

22U_1206_10V4Z~D

C1292

2

2

1

12

1

R968

1K_0402_5%~D

2

2

1

1

C1080

C1079

C1190

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

Notice : 4.7u 6.3V capactor Thickness 1.25mm

Layout Notice : Filter place as close
chip as possible.

V_2P5_LAN

V_1P2_LAN

BLM11A601S_0603~D

4.7U_0805_6.3V6K~D

BLM11A601S_0603~D

4.7U_0805_6.3V6K~D

BLM11A601S_0603~D

4.7U_0805_6.3V6K~D

4.7U_0805_6.3V6K~D

BLM11A601S_0603~D

0.1U_0402_16V4Z~D

BLM11A601S_0603~D

0.1U_0402_16V4Z~D

L149

BLM11A601S_0603~D

0.1U_0402_16V4Z~D

L152

C1210

L153

C1212

L154

C1119

R1245

0_0603_5%~D

C1215

@

12

L150

L151

12

12

12

12

0.1U_0402_16V4Z~D

12

12

2

1

2

1

2

1

1

2

2

1

C1207

C1208

C1209

C1191

2

2

1

C1192

0.1U_0402_16V4Z~D

2

1

2

1

2

1

AVDDL

2

C1211

0.1U_0402_16V4Z~D

1

GPHY_PLLVDD

2

C1213

0.1U_0402_16V4Z~D

1

PCIE_PLLVDD

2

C1214

0.1U_0402_16V4Z~D

1

PCIE_SDS_VDD

2

C1135

0.1U_0402_16V4Z~D

1

2

1

2

0.1U_0402_16V4Z~D

V_2P5_LAN

C1205

2

1

XTALVDD

AVDD

AVDD1

@

0.1U_0402_16V4Z~D

V_1P2_LAN+3VRUN

C1088

4.7U_0805_6.3V6K~D

0.1U_0402_16V4Z~D

C1206

2

1

V_3P3_LAN

V_2P5_LAN

V_3P3_LAN

PCIE_SDS_VDD

PCIE_PLLVDD

GPHY_PLLVDD

1

Layout Notice : 1.2V filter. Place as close
chip as possible.

C1092

0.1U_0402_16V4Z~D

2

1

Analog
power

Clamp

2

2

1

1

C1093

C1094

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

BCM5751M

PLL

Don't care

BIAS

1

GND

C1095

0.1U_0402_16V4Z~D

2

2

1

1

C1089

0.1U_0402_16V4Z~D

V_1P2_LAN

+3VRUN

XTALVDD

AVDDL

AVDD
AVDD1

+3VRUN

V_2P5_LAN

L139

BLM11A601S_0603~D

1 2

V_BIAS

1

C1123

0.1U_0402_16V4Z~D

2

Title

Size Document Number Rev

Date: Sheet of

2

2

1

1

C1091

C1090

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

U164B

B8

VDDC_0

E5

VDDC_1

E6

VDDC_2

E7

VDDC_3

E8

VDDC_4

E9

VDDC_5

E10

VDDC_6

F5

VDDC_7

F10

VDDC_8

G4

VDDC_9

J5

VDDC_10

J10

VDDC_11

K5

VDDC_12

K6

VDDC_13

K7

VDDC_14

K8

VDDC_15

K4

VDDC_16

J4

VDDC_17

D11

VDDIO_0

G11

VDDIO_1

K12

VDDIO_2

Digial power

A7

VDDIO-PCI_0

B3

VDDIO-PCI_1

C5

VDDIO-PCI_2

E1

VDDIO-PCI_3

E4

VDDIO-PCI_4

G1

VDDIO-PCI_5

K3

VDDIO-PCI_6

L4

VDDIO-PCI_7

P2

VDDIO-PCI_8

A8

VDDP_0

D5

VDDP_1

P13

VDDP_2

H14

XTALVDD

M12

WOL_VAUX

P14

WOL_INRSH_ON

M6

PCIE_SDS_VDD

F12

AVDDL_0

F13

AVDDL_1

A13

AVDD_0

F14

AVDD_1

M8

PCIE_PLLVDD

G14

GPHY_PLLVDD

P1

VESD1

G2

VESD2

A1

VESD3

L3

DC_31

M1

DC_32

M2

DC_33

M3

DC_34

M4

DC_35

M5

DC_36

M7

DC_37

N2

DC_38

N3

DC_39

N4

DC_40

N5

DC_41

N7

DC_42

P3

DC_43

P4

DC_44

P5

DC_45

P7

DC_46

A14

BIASVDD

BCM5751MKFB_FPBGA196~D

DELL CONFIDENTIAL/PROPRIETARY

BCM5751M

Board Number LA2111

2

1

C1096

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8

DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30

29 61Monday, February 09, 2004

0.1U_0402_16V4Z~D

2

2

1

1

C1097

0.1U_0402_16V4Z~D

B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9

K13
L7
L12
L13
M10
N11
P11

A3
A4
A5
B1
B2
B5
B6
C1
C3
C4
C6
C7
C8
C9
D1
D2
D3
D4
E3
F1
F2
F3
G3
H1
H3
H4
J1
J3
K1
L1
L2

0.3

5

0.1U_0402_16V4Z~D
C1126

0.1U_0402_16V4Z~D
C1127

0.1U_0402_16V4Z~D
C1128

T331

1

2

3

0.1U_0402_16V4Z~D
C1129

1:1

V_2P5_LAN

D D

SW_LAN_TX3-

SW_LAN_TX3+

12

R981

0_0402_5%~D

C1130

0.01U_0402_16V7K~D

TRM_CT

2

1

1 2
1 2
1 2
1 2

T1

4

1:1

C C

SW_LAN_TX2-

SW_LAN_TX2+

C1131

2

1

0.01U_0402_16V7K~D

5

6

T2 T6

7

1:1

SW_LAN_RX-

SW_LAN_RX+

B B

SW_LAN_TX+

C1132

C1133

2

1

0.01U_0402_16V7K~D

2

1

0.01U_0402_16V7K~D

8

9

T3 T7

10

1:1

11

12 13

T4 T8

GB1G04-LP-T_24P~D

4

R971 49.9_0603_1%~D

1 2

R972 49.9_0603_1%~D

1 2

R973 49.9_0603_1%~D

1 2

R974 49.9_0603_1%~D

1 2

R975 49.9_0603_1%~D

1 2

R976 49.9_0603_1%~D

1 2

R977 49.9_0603_1%~D

1 2

R978 49.9_0603_1%~D

1 2

Layout Notice : Place
termination as close as
ASIC as possible

Z2805

24

NB_LAN_TX3-

23

NB_LAN_TX3+

T5

22

21

20

19

18

17

16

15

14

Z2806

NB_LAN_TX2-

NB_LAN_TX2+

Z2807

NB_LAN_RX-

NB_LAN_RX+

Z2808

NB_LAN_TX-SW_LAN_TX-

NB_LAN_TX+

LAN_TX0­LAN_TX0+
LAN_TX1­LAN_TX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

L140

V_3P3_LAN

Layout Notice : Place bead as
close PI3L500 as possible

@

BLM11A601S_0603~D

0.047U_0402_16V7K~D

LAN_TX0-<<29>>
LAN_TX0+<<29>>

LAN_TX1-<<29>>
LAN_TX1+<<29>>

LAN_TX2-<<29>>
LAN_TX2+<<29>>

LAN_TX3-<<29>>
LAN_TX3+<<29>>

LAN_TX0- LAN_TX0-R
LAN_TX0+ LAN_TX0+R

LAN_TX1- LAN_TX1-R
LAN_TX1+ LAN_TX1+R

LAN_TX2- LAN_TX2-R
LAN_TX2+ LAN_TX2+R

LAN_TX3- LAN_TX3-R
LAN_TX3+ LAN_TX3+R

DOCKED

DOCKED<<35,37>>

3

R1105

1 2

0_0805_5%~D

1 2

C1124

@

1 2

L156 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L157 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L158 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L159 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L160 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L161 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L162 15N_LQG18HN15NJ00D_300mA_5%_0603~D

1 2

L163 15N_LQG18HN15NJ00D_300mA_5%_0603~D

LAN_SW_VCC

1

2

C1125

0.1U_0603_16V7K~D

LAN_ACT#<<29>>
LINK_10#<<29>>
LINK_100#<<29>>

FROM NIC DOCKED

1

2

1: TO DOCK
0: TO RJ45

LAN_ACT#
LINK_10#
LINK_100#

2

56

U167

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

17

SEL

19

LED0

20

LED1

54

LED2

5

NC

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

12

12

R1093

R1092

10K_0402_5%~D

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

V_3P3_LAN

12

R1094

10K_0402_5%~D

LAN ANALOG
SWITCH

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

0LED1

23

1LED1

52

2LED1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

0LED2

26

1LED2

51

2LED2

PI3L500E_TQFN56~D

55

10K_0402_5%~D

1

SW_LAN_TX­SW_LAN_TX+

SW_LAN_RX­SW_LAN_RX+

SW_LAN_TX2­SW_LAN_TX2+

SW_LAN_TX3­SW_LAN_TX3+

NB_LAN_ACTLED_YEL#

LED_10_GRN#
LED_100_ORG#

DOCK_LAN_TX­DOCK_LAN_TX+

DOCK_LAN_RX­DOCK_LAN_RX+

DOCK_LAN_TX2­DOCK_LAN_TX2+

DOCK_LAN_TX3­DOCK_LAN_TX3+

DOCK_LAN_ACTLED_YEL#

DOCK_LED_10#
DOCK_LED_100#

JLOM1

NB_LAN_TX+
NB_LAN_TX­NB_LAN_RX+
NB_LAN_TX2+
NB_LAN_TX2­NB_LAN_RX­NB_LAN_TX3+
NB_LAN_TX3-

RJ_TIP
RJ_RING

18

18

16

2

1

P1_1

2

P1_2

3

P1_3

4

P1_4

5

P1_5

6

P1_6

7

P1_7

8

P1_8

RJ45/LED

11

P2_1

10

P2_2

FOX_JM34F23-SBM4~D

V_3P3_LAN

NB_LAN_ACTLED_YEL# NB_LAN_ACTLED_YEL_R#

LED_10_GRN#

LED_100_ORG#

DOCK_LAN_TX- <<35>>
DOCK_LAN_TX+ <<35>>

DOCK_LAN_RX- <<35>>
DOCK_LAN_RX+ <<35>>

DOCK_LAN_TX2- <<35>>
DOCK_LAN_TX2+ <<35>>

DOCK_LAN_TX3- <<35>>
DOCK_LAN_TX3+ <<35>>

DOCK_LAN_ACTLED_YEL# <<35>>
DOCK_LED_10# <<35>>
DOCK_LED_100# <<35>>

TO
RJ45

NB_LAN_ACTLED_YEL_R#

17

YEL

LED_10_GRN_R#

15

GRN

LED_100_ORG_R#

14

ORG

19

MH1

20

MH2

21

MH3

12

12

13

SHG1

RJ11

R1095

1 2

330_0402_5%~D

R1096

1 2

330_0402_5%~D

R1097

1 2

330_0402_5%~D

LED_10_GRN_R#

LED_100_ORG_R#

TO
DOCK

RJ_TIP

A A

RJ_RING

J_RJ1

2
1

JST_SM02B-SRSS

5

GND
CHASIS

C1134

1000P_1808_3KV7K~D

1 2

4

12

12

12

12

R997 75_0603_5%~D

R998 75_0603_5%~D

R999 75_0603_5%~D

R1000 75_0603_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

LAN TRANSFOMER

Size Document Number Rev

Board Number LA2111

Date: Sheet of

30 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

PCI_AD[0..31]<<20,33,34>>

D D

PCI_C_BE3#<<20,33,34>>

R1017

C1138

12

CK33M_CBS_TERM

2

1

PCI_C_BE2#<<20,33,34>>
PCI_C_BE1#<<20,33,34>>
PCI_C_BE0#<<20,33,34>>

PCI_PAR<<20,33,34>>
PCI_FRAME#<<20,33,34,35>>

PCI_TRDY#<<20,33,34>>
PCI_IRDY#<<20,33,34,35>>
PCI_STOP#<<20,33,34>>
PCI_DEVSEL#<<20,33,34>>

1 2

PCI_PERR#<<20,33,34>>
PCI_SERR#<<20,33,34>>

PCI_REQ1#<<20>>
PCI_GNT1#<<20>>

PCIRST_CB#<<20,33>>

CBS_GRST#<<36>>

PCI_DATA<<32>>
PCI_CLOCK<<32>>
PCI_LATCH<<32>>

C C

PCI_AD17

CK_33M_CBPCI<<6>>

10_0402_5%~D@

B B

4.7P_0402_50V8C~D@

R1015100_0402_5%~D

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_PAR
PCI_FRAME#

PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
CBS_IDSEL

PCI_PERR#
PCI_SERR#

PCI_REQ1#
PCI_GNT1#

PCIRST_CB#
CBS_GRST#

PCI_DATA
PCI_CLOCK
PCI_LATCH

SCR_IF_RST
SCR_IF_CLK
SCR_IF_FCB

SCR_DETECT_C

U162A

M1

AD31

M2

AD30

M3

AD29

M6

AD28

M5

AD27

N1

AD26

N2

AD25

N3

AD24

P3

AD23

R1

AD22

R2

AD21

P5

AD20

PCI6515

R3

AD19

T1

AD18

T2

AD17

W4

AD16

W7

AD15

R8

AD14

U8

AD13

V8

AD12

W9

AD11

V9

AD10

U9

AD9

R9

AD8

V10

AD7

U10

AD6

R10

AD5

W11

AD4

V11

AD3

U11

AD2

P11

AD1

R11

AD0

P2

C/BE3#

U5

C/BE2#

V7

C/BE1#

W10

C/BE0#

U7

PAR

R6

FRAME#

W5

TRDY#

V5

IRDY#

V6

STOP#

U6

DEVSEL#

N5

IDSEL

R7

PERR#

W6

SERR#

L3

REQ#

L2

GNT#

L1

PCLK

K3

PRST#

K5

GRST#

B9

DATA

A9

CLOCK

C9

LATCH

PCI6515ZHK_PBGA257~D

@

22K_0402_5%~D

12

R1021

A_CAD31 // A_D10

A_CAD30 // A_D9
A_CAD29 // A_D1
A_CAD28 // A_D8
A_CAD27 // A_D0
A_CAD26 // A_A0
A_CAD25 // A_A1
A_CAD24 // A_A2
A_CAD23 // A_A3
A_CAD22 // A_A4
A_CAD21 // A_A5
A_CAD20 // A_A6

A_CAD19 // A_A25

A_CAD18 // A_A7
A_CAD17 // A_A24
A_CAD16 // A_A17

A_CAD15 // A_IOWR#

A_CAD14 // A_A9

A_CAD13 // A_IORD#

A_CAD12 // A_A11

A_CAD11 // A_OE#

A_CAD10 // A_CE2#

A_CAD9 // A_A10

A_CAD8 // A_D15

A_CAD7 // A_D7

A_CAD6 // A_D13

A_CAD5 // A_D6

A_CAD4 // A_D12

A_CAD3 // A_D5

A_CAD2 // A_D11

A_CAD1 // A_D4
A_CAD0 // A_D3

A_CC/BE3# // A_REG#

A_CC/BE2# // A_A12

A_CC/BE1# // A_A8

A_CC/BE0# // A_CE1#

A_CPAR // A_A13

A_CFRAME# // A_A23

A_CTRDY# // A_A22

A_CIRDY# // A_A15

A_CSTOP# // A_A20

A_CDEVSEL# // A_A21

A_CBLOCK# // A_A19

A_CPERR# // A_A14

A_CSERR# // A_WAIT#

A_CREQ# // A_INPACK#

A_CSTSCHG // A_BVD1(STSCHG#/RI#)

@

470P_0402_50V7K~D

C1143

2

1

A_CGNT# // A_WE#

A_CCLKRUN# // A_WP(IOIS16#)

A_CCLK // A_A16

A_CINT# // A_READY(IREQ#)

A_CRST# // A_RESET

A_CAUDIO // A_BVD2(SPKR#)

A_CCD1# A_CD1#

A_CCD2# // A_CD2#

A_CVS1 // A_VS1#
A_CVS2 // A_VS2#

A_RSVD // A_D14

A_RSVD // A_D2

A_RSVD // A_A18

@

22K_0402_5%~D

12

R1022

C1144

2

1

@

56P_0402_50V8J~D

+VCC_SC

C1145

2

1

0.1U_0603_50V4Z~D

CBS_CAD31

C10

CBS_CAD30

A10

CBS_CAD29

F11

CBS_CAD28

E11

CBS_CAD27

C11

CBS_CAD26

B13

CBS_CAD25

C13

CBS_CAD24

A14

CBS_CAD23

B14

CBS_CAD22

B15

CBS_CAD21

E14

CBS_CAD20

A16

CBS_CAD19

D19

CBS_CAD18

E17

CBS_CAD17

F15

CBS_CAD16

H19

CBS_CAD15

J17

CBS_CAD14

J15

CBS_CAD13

J18

CBS_CAD12

K15

CBS_CAD11

K17

CBS_CAD10

K18

CBS_CAD9

L15

CBS_CAD8

L18

CBS_CAD7

L19

CBS_CAD6

M17

CBS_CAD5

M18

CBS_CAD4

N19

CBS_CAD3

M15

CBS_CAD2

N17

CBS_CAD1

N18

CBS_CAD0

P19

CBS_CC/BE3#

E13

CBS_CC/BE2#

E18

CBS_CC/BE1#

H18

CBS_CC/BE0#

L17

CBS_CPAR

H14

CBS_CFRAME#

E19

CBS_CTRDY#

G15

CBS_CIRDY#

F17

CBS_CSTOP#

G18

CBS_CDEVSEL#

F19

CBS_CBLOCK#

H15

CBS_CPERR#

G19

CBS_CSERR#

C12

CBS_CREQ#

C14

CBS_CGNT#

G17

CBS_CSTSCHNG

A12

CBS_CCLKRUN#

A11

CBS_CCLK_INTERNAL

F18

CBS_CINT#

E12

CBS_CRST#

C15

CBS_CAUDIO

B12

CBS_CCD1#_INTERNAL

N15

CBS_CCD2#_INTERNAL

B11

CBS_CVS1

A13

CBS_CVS2

B16

CBS_RSVD/D14

M19

CBS_RSVD/D2

B10

CBS_RSVD/A18

H17

E-T_6900-10~D

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

CBS_CAD31 <<32>>
CBS_CAD30 <<32>>
CBS_CAD29 <<32>>
CBS_CAD28 <<32>>
CBS_CAD27 <<32>>
CBS_CAD26 <<32>>
CBS_CAD25 <<32>>
CBS_CAD24 <<32>>
CBS_CAD23 <<32>>
CBS_CAD22 <<32>>
CBS_CAD21 <<32>>
CBS_CAD20 <<32>>
CBS_CAD19 <<32>>
CBS_CAD18 <<32>>
CBS_CAD17 <<32>>
CBS_CAD16 <<32>>
CBS_CAD15 <<27>>
CBS_CAD14 <<32>>
CBS_CAD13 <<27>>
CBS_CAD12 <<32>>
CBS_CAD11 <<32>>
CBS_CAD10 <<32>>
CBS_CAD9 <<32>>
CBS_CAD8 <<32>>
CBS_CAD7 <<32>>
CBS_CAD6 <<32>>
CBS_CAD5 <<32>>
CBS_CAD4 <<32>>
CBS_CAD3 <<32>>
CBS_CAD2 <<32>>
CBS_CAD1 <<32>>
CBS_CAD0 <<32>>

CBS_CC/BE3# <<32>>
CBS_CC/BE2# <<32>>
CBS_CC/BE1# <<32>>
CBS_CC/BE0# <<32>>

CBS_CPAR <<32>>
CBS_CFRAME# <<32>>

CBS_CTRDY# <<32>>
CBS_CIRDY# <<32>>
CBS_CSTOP# <<32>>
CBS_CDEVSEL# <<32>>
CBS_CBLOCK# <<32>>

CBS_CPERR# <<32>>
CBS_CSERR# <<32>>

CBS_CREQ# <<32>>
CBS_CGNT# <<32>>

CBS_CSTSCHNG <<32>>
CBS_CCLKRUN# <<32>>

R1016 47_0402_5%~D

CBS_CINT# <<32>>
CBS_CRST# <<32>>
CBS_CAUDIO <<32>>

CBS_CVS1 <<32>>
CBS_CVS2 <<32>>

CBS_RSVD/D14 <<32>>
CBS_RSVD/D2 <<32>>
CBS_RSVD/A18 <<32>>

JP5

+3V_CBSD

+3V_CBSD

R1037

1 2

10K_0402_5%~D

CBS_SPK<<25>>

CK_48M_SCR<<6>>

@

R1010

1 2

CK_48M

@

C1136

2

1

12

R1018

1 2

@

C1140

2

1

0_0402_5%~D

@

270P_0402_25V8K~D

C1141

CBS_CCLK <<32>>
CBS_CCD2# <<32>>
CBS_CCD1# <<32>>

R1019
0_0402_5%~D

1 2

270P_0402_25V8K~D

2

1

R1007

4.7K_0402_5%~D

1 2

R1008

1 2

4.7K_0402_5%~D

R1011

10_0402_5%~D

4.7P_0402_50V8C~D

USBP3+<<22>> USBP3-<<22>>

220_0402_5%~D

1 2

R1012
220_0402_5%~D

1 2

SYS_PME#<<33,34,36>>

USBP3+ USBP3-CBS_CAD13 CBS_CAD15

R1046220_0402_5%~D

12

PHY_TEST_MA

TI_SUSPEND#

CBS_SPK

CK_48M_SCR

CBS_SCL

CBS_SDA

SYS_PME#

USB_ENABLE

USB_ENABLE

+3VSUS +3VSUS

8

1

U172A

P

1OE

0.1U_0402_16V4Z~D

1A21B

C1218

1

G

SN74CB3Q3306APWR_TSSOP8~D

4

2

P12

U12

V12

W12

P17

R12

H3

F1

G2

G3

L5

E10

3

U162B

TEST0
TEST1
TEST2
TEST3
TEST4

RSVD

J5

SUSPEND#

SPKROUT

CLK_48

SCL

SDA

RI_OUT# // PME#

A_USB_EN#

PCI6515

PCI6515ZHK_PBGA257~D

SC_GPIO1
SC_GPIO2
SC_GPIO3
SC_GPIO4
SC_GPIO5
SC_GPIO6

SC_GPIO0

SC_FCB
SC_RFU

SC_CD#
SC_CLK

SC_DATA

SC_RST
SC_OC#

SC_PWR_CTRL

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

A4
C5
E6
B5
A5
C6

B4
E3
D1

F3
E2
E1
F5
F2

G5

G1
H5
H2
H1
J1
J2
J3

SCR_IF_FCB
SCR_IF_RFU

SCR_DETECT_C
SCR_IF_CLK
SCR_IF_DATA
SCR_IF_RST

PCI_PIRQD#
PCI_PIRQC#

IRQ_SERIRQ
CBS_RI#

SCR_DETECT_C <<37>>

PCI_PIRQD# <<20,33>>
PCI_PIRQC# <<20>>

R1044 10K_0402_5%~D

IRQ_SERIRQ <<22,29,36>>

R1045 10K_0402_5%~D

1 2

R1013 10K_0402_5%~D@

R1014

12

0_0402_5%~D

CBS_RI#

7

8

P

2OE

2A52B
G

SN74CB3Q3306APWR_TSSOP8~D

4

12

12

U172B

6

+3V_CBSD

CLKRUN# <<22,33,36>>

10K_0402_5%~D

R1048

1 2

A A

@

22K_0402_5%~D

12

R1009

5

4

C1142

2

1

SCR_IF_DATA
SCR_IF_RFU

100P_0402_50V8K~D

@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Card Bus TI6515(1/2)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

31 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

C1204

1

2

0.047U_0402_16V4Z~D

+3V_CBSD

0.047U_0402_16V4Z~D

C1158

1

2

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16

CBS_CAD15_L

CBS_CAD14

CBS_CAD13_L

CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CBS_CAD31 <<31>>
CBS_CAD30 <<31>>
CBS_CAD29 <<31>>
CBS_CAD28 <<31>>
CBS_CAD27 <<31>>
CBS_CAD26 <<31>>
CBS_CAD25 <<31>>
CBS_CAD24 <<31>>
CBS_CAD23 <<31>>
CBS_CAD22 <<31>>
CBS_CAD21 <<31>>
CBS_CAD20 <<31>>
CBS_CAD19 <<31>>
CBS_CAD18 <<31>>
CBS_CAD17 <<31>>
CBS_CAD16 <<31>>
CBS_CAD15_L <<27>>
CBS_CAD14 <<31>>
CBS_CAD13_L <<27>>
CBS_CAD12 <<31>>
CBS_CAD11 <<31>>
CBS_CAD10 <<31>>
CBS_CAD9 <<31>>
CBS_CAD8 <<31>>
CBS_CAD7 <<31>>

CBS_CAD6 <<31>>

CBS_CAD5 <<31>>

CBS_CAD4 <<31>>

CBS_CAD3 <<31>>
CBS_CAD2 <<31>>
CBS_CAD1 <<31>>
CBS_CAD0 <<31>>

L143

+3VRUN

0.1U_0402_16V4Z~D

1

2

C1250

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

R1029

CBS_VCC

C1203

+3V_CBSD

+3V_CBSD

220_0402_5%~D

1 2

0.1U_0402_16V4Z~D

1

2

D D

CBS_VCC

C1147

C C

B B

A A

+VCC_SC

PCI_DATA<<31>>
PCI_CLOCK<<31>>
PCI_LATCH<<31>>

C1148

1

2

CBS_VPP

C1202

1

2

0.1U_0603_50V4Z~D
C1222

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C1149

1

1

2

2

SUSPWROK<<22,39,42>>

+VCC_SC

C1201

U162C

J6

VCC1

L6

VCC2

P6

VCC3

P8

VCC4

P10

VCC5

L14

VCC6

J14

VCC7

F14

VCC8

F12

VCC9

F9

VCC10

F6

VCC11

U19

VCC12

P13

VCC13

P14

VCC14

U15

VCC15

A15

VCCA1

J19

VCCA2

P1

VCCP1

W8

VCCP2

G6

SC_VCC_5V

K1

VR_PORT1

K19

VR_PORT2

P15

VR_PORT3

K2

VR_EN#

H6

GND1

K6

GND2

N6

GND3

P7

GND4

P9

GND5

M14

GND6

K14

GND7

G14

GND8

F13

GND9

F10

GND10

F7

GND11

R17

GND12

U18

GND13

U13

GND14

U14

GND15

R14

GND16

U161

3

DATA

4

CLOCK

5

LATCH

12

RESET#

15

OC#

21

SHDN#

8

AVPP

19

BVPP

9

AVCC

10

AVCC

17

BVCC

18

BVCC

TPS2224ADBR_SSOP24~D

PCI6515

PCI6515ZHK_PBGA257~D

20

12V

7

12V

14

3.3V

13

3.3V

GND

5V
5V
5V

NC
NC
NC
NC

+5VSUS

24
2
1

11

23
22
16
6

C1197

B2

NC1

B1

NC2

D3

NC3

C2

NC4

C1

NC5

D2

NC6

U1

NC7

T3

NC8

U2

NC9

V1

NC10

U3

NC11

V2

NC12

W2

NC13

U4

NC14

V3

NC15

W3

NC16

V4

NC17

U16

NC18

V17

NC19

W18

NC20

U17

NC21

V18

NC22

V19

NC23

T17

NC24

D18

NC25

C19

NC26

D17

NC27

C18

NC28

B19

NC29

C17

NC30

B18

NC31

A18

NC32

C16

NC33

B17

NC34

A17

NC35

A3

NC36

C4

NC37

B3

NC38

A2

NC39

C3

NC40

E5

NC41

V14

NC42

W14

NC43

V16

NC44

W16

NC45

V13

NC46

W13

NC47

V15

NC48

W15

NC49

R13

NC50

W17

NC51

N14

NC52

E8

NC53

C7

NC54

B7

NC55

A6

NC56

A8

NC57

B6

NC58

A7

NC59

E7

NC60

B8

NC61

F8

NC62

C8

NC63

P18

NC64

T18

NC65

T19

NC66

R19

NC67

R18

NC68

E9

NC69

+3VSUS

0.1U_0402_16V4Z~D

C1198

1

2

0.1U_0402_16V4Z~D

1

2

CBS_CC/BE0#<<31>>

CBS_CC/BE1#<<31>>

CBS_CPAR<<31>>

CBS_CPERR#<<31>>
CBS_CGNT#<<31>>
CBS_CINT#<<31>>

CBS_VCC

CBS_VPP

CBS_CCLK<<31>>
CBS_CIRDY#<<31>>
CBS_CC/BE2#<<31>>

CBS_RSVD/D2<<31>>

CBS_CCLKRUN#<<31>>

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5

CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11

CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR

CBS_CPERR#
CBS_CGNT#
CBS_CINT#

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#

CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22

CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26

CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#

1 2

BLM21A601SPT_0805~D

0.1U_0402_16V4Z~D

C1150

1

2

JCBUS

1

A_CAD0

2

A_CAD1

3

A_CAD3

4

A_CAD5

5

GND0

6

A_CAD7

7

A_PCI_C/BE0#

8

A_CAD9

9

A_CAD11

10

GND1

11

A_CAD12

12

A_CAD14

13

A_PCI_C/BE1#

14

A_CPAR

15

GND2

16

A_CPERR#

17

A_CGNT#

18

A_CINT#

19

+AVCC0

20

GND3

21

+AVPP0

22

A_CCLK

23

A_CIRDY

24

A_PCI_C/BE2#

25

GND4

26

A_CAD18

27

A_CAD20

28

A_CAD21

29

A_CAD22

30

GND5

31

A_CAD23

32

A_CAD24

33

A_CAD25

34

A_CAD26

35

GND6

36

A_CAD27

37

A_CAD29

38

CB_A_D2

39

A_CCLKRUN#

40

GND7

FOX_QT60080A-B121C_LT~D

10U_0805_10V4M~D

C1151

1

2

GND15

A_CCD1#

A_CAD2
A_CAD4
A_CAD6

GND14

CB_A_D14

A_CAD8

A_CAD10

A_CVS1

GND13
A_CAD13
A_CAD15
A_CAD16

CB_A_A18

GND12

A_CBLOCK#

A_CSTOP#

A_CDEVSEL#

+AVCC1

GND11

+AVPP1

A_CTRDY#

A_CFRAME#

A_CAD17

GND10
A_CAD19

A_CVS2

A_CRST#

A_CSERR#

GND9

A_CREQ#

A_PCI_C/BE3#

A_CAUDIO

A_CSTSCHG

GND8
A_CAD28
A_CAD30
A_CAD31
A_CCD2#

C1152

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4M~D

C1154

C1153

1

1

2

2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6

CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1

CBS_CAD13_L
CBS_CAD15_L
CBS_CAD16
CBS_RSVD/A18

CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17

CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#

CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG

CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#

0.047U_0402_16V4Z~D

C1155

1

2

C1156

1

2

CBS_CCD1# <<31>>

CBS_RSVD/D14 <<31>>

CBS_CVS1 <<31>>

CBS_RSVD/A18 <<31>>
CBS_CBLOCK# <<31>>

CBS_CSTOP# <<31>>
CBS_CDEVSEL# <<31>>

CBS_CTRDY# <<31>>
CBS_CFRAME# <<31>>

CBS_CVS2 <<31>>
CBS_CRST# <<31>>
CBS_CSERR# <<31>>

CBS_CREQ# <<31>>
CBS_CC/BE3# <<31>>
CBS_CAUDIO <<31>>
CBS_CSTSCHNG <<31>>

CBS_CCD2# <<31>>

1

2

0.047U_0402_16V4Z~D

CBS_VCC
CBS_VPP

C1157

0.047U_0402_16V4Z~D

1

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Card Bus TI6515(2/2)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

32 61Monday, February 09, 2004

1

0.3

5

PCI_AD[0..31]<<20,31,34>>

D D

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

CK_33M_MINIPCI

R443
10_0402_5%~D

COEX2_WLAN_ACTIVE<<28>>

1 2

C C

CK_33M_MINPCI_TERM

2

C493

4.7P_0402_50V8C~D

1

B B

+3VRUN

2

C491

0.047U_0402_16V7K~D

1

2

C496

0.047U_0402_16V7K~D

1

2

C565

0.047U_0402_16V7K~D

1

+3VRUN

2

C574

0.047U_0402_16V7K~D

1

2

C497

0.047U_0402_16V7K~D

1

2

C568

0.047U_0402_16V7K~D

1

+3VRUN

A A

2

C488

0.047U_0402_16V7K~D

1

2

C504

0.047U_0402_16V7K~D

1

5

2

C572

<BOM Structure>

0.047U_0402_16V7K~D

1

4

3

2

LED_WLAN24_RADIOSTATE
LED_WLAN5

+3VRUN+3VRUN

PCI_C_BE3#<<20,31,34>>

PCI_C_BE2#<<20,31,34>>

PCI_C_BE1#<<20,31,34>>

DEBUG_EN_CARD<<36>>

HW_RADIO_DIS#<<28,37>>

CK_33M_MINIPCI<<6>>

PCI_IRDY#<<20,31,34,35>>

PCI_SERR#<<20,31,34>>
PCI_PERR#<<20,31,34>>

PCI_PIRQD#<<20,31>>

PCI_REQ3#<<20>>

CLKRUN#<<22,31,36>>

+5VRUN

R768
0_0402_5%~D

1 2

JPCI

1

TIP

3

8PMJ-3

5

8PMJ-6

7

8PMJ-7

9

8PMJ-8

11

HW_RADIO_DIS#

PCI_PIRQD#

PCI_REQ3#
PCI_AD31

PCI_AD29
PCI_AD27

PCI_AD25
PCI_C_BE3#

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C_BE2#
PCI_IRDY#

CLKRUN#
PCI_SERR# PCI_STOP#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

DEBUG_EN_CARD

LED1_GRNP

13

LED1_GRNN

15

CHSGND

17

INTB#

19

3.3V

21

RESERVED

23

GROUND

25

CLK

27

GROUND

29

REQ#

31

3.3V

33

AD31

35

AD29

37

GROUND

39

AD27

41

AD25

43

RESERVED

45

C/BE3#

47

AD23

49

GROUND

51

AD21

53

AD19

55

GROUND

57

AD17

59

C/BE2#

61

IRDY#

63

3.3V

65

CLKRUN#

67

SERR#

69

GROUND

71

PERR#

73

C/BE1#

75

AD14

77

GROUND

79

AD12

81

AD10

83

GROUND

85

AD8

87

AD7

89

3.3V

91

AD5

93

RESERVED

95

AD3

97

5V

99

AD1

101

GROUND

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND

115

SYS_AUDIO_OUT

117

SYS_AUDIO_OUT GND

119

AUDIO_GND

121

RESERVED

123

VCC5A

AMP_1318644-1~D

AC_SDATA_OUT

AC_CODEC_ID0#

SYS_AUDIO_IN

SYS_AUDIO_IN GND

RING

8PMJ-1
8PMJ-2
8PMJ-4

8PMJ-5
LED2_YELP
LED2_YELN

RESERVED

INTA#

RESERVED

3.3VAUX
RST#

3.3V

GNT#

GROUND

PME#

RESERVED

AD30

3.3V
AD28
AD26
AD24

IDSEL

GROUND

AD22
AD20

PAR
AD18
AD16

GROUND

FRAME#

TRDY#
STOP#

3.3V
DEVSEL#
GROUND

AD15
AD13
AD11

GROUND

AD9

C/BE0#

3.3V

AD6
AD4
AD2

AD0
RESERVED
RESERVED

GROUND

M66EN

AC_RESET#

RESERVED

GROUND

AUDIO_GND

MCPIACT#

3.3VAUX

2

4
6
8
10
12
14
16
18

5V

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

LED_WLAN24_RADIOSTATE
LED_WLAN5

PCI_PIRQB#

PCIRST_CB#CK_33M_MINIPCI
PCI_GNT3#
SYS_PME#

R766 0_0402_5%~D

1 2

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

DEBUG_OUT_CARD

MPCIACT#

V_3P3_LAN

2

C209

0.1U_0402_16V4Z~D

1

V_3P3_LAN

R1231
0_0402_5%~D

1 2

Q114

D

+3VSUS

S

13

2N7002_SOT23~D@

G

2

G

2

Q116

NIC_MINI_SMBCLK

13

D

S

2N7002_SOT23~D@

D

1 3

1 3

D

ICH_SMBDATA<<6,22>> LAN_SMBDATA <<29>>

ICH_SMBCLK<<6,22>>

ICH_SMBDATA

ICH_SMBCLK

S

G

2

2

G

S

R1055
10K_0402_5%~L

1 2

Q115
2N7002_SOT23~D

Q117
2N7002_SOT23~D

R1056
10K_0402_5%~L

1 2

LAN_SMBDATANIC_MINI_SMBDAT

LAN_SMBCLK

LAN_SMBCLK <<29>>

1 2

R1232
0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

+3VRUN

5

U173

1

P

INB

2

INA

G

TC7SH32FU_SSOP5~D

3

1 2

R1158 100K_0402_5%~D

1 2

R1159 100K_0402_5%~D

PCI_PIRQB# <<20>>

PCIRST_CB# <<20,31>>
PCI_GNT3# <<20>>

SYS_PME# <<31,34,36>>

R767

@

10K_0402_5%~D

12

1 2

R447

100_0402_5%~D

PCI_PAR <<20,31,34>>

PCI_FRAME# <<20,31,34,35>>
PCI_TRDY# <<20,31,34>>
PCI_STOP# <<20,31,34>>

PCI_DEVSEL# <<20,31,34>>

PCI_C_BE0# <<20,31,34>>

DEBUG_OUT_CARD <<36>>

R201

10K_0402_5%~D

1 2

1

R1124

1 2

200_0402_5%~D

LED_WLAN_OUT

LED_WLAN_OUT <<40>>

4

O

+5VRUN

V_3P3_LAN

2

C483

0.1U_0402_16V4Z~D

1

COEX1_BT_ACTIVE <<28>>

2

C140

0.1U_0402_16V4Z~D

1

PCI_AD19

+3VSUS

DELL CONFIDENTIAL/PROPRIETARY

Title

Mini PCI Socket

Size Document Number Rev

Board Number LA2111

Date: Sheet of

33 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

+5VRUN

D24

2 1

+5V_QDOCK1

RB751V_SOD323~D

QUIETE#

D D

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27

PCI_AD25
PCI_AD24

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

D23

2 1

RB751V_SOD323~D

U34

39

OE1

VCC2

OE229VCC1

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

12

A8

13

A9

14

A10
A11
A12
A13
A14
A15

NC1
NC2

GND1
GND2

B10
B11
B12
B13
B14
B15

15
16
17
18
19

1

11

QS32X245Q2_QVSOP40~D

+5V_QDOCK

C40

0.1U_0402_16V4Z~D

40
30

38

B0

37

B1

36

B2

35

B3

34

B4

33

B5

32

B6

31

B7

28

B8

27

B9

26
25
24
23
22
21

10
20

1 2

DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26PCI_AD26
DOCK_AD25
DOCK_AD24

DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16

12

R38
1K_0402_5%~D

U33

PCI_REQ0#<<20>>

PCI_GNT0#<<20,35>>
SYS_PME#<<31,33,36>>

PCI_PLOCK#<<20>>

PCIRST_DOCK#<<20>>

CK_33M_DOCKPCI<<6>>

QBUFEN#<<37>>

PCI_REQ0#
PCI_GNT0#
SYS_PME#
PCI_AD24
PCI_PLOCK#

PCIRST_DOCK#
CK_33M_DOCKPCI

QBUFEN#

12

R40

@

33_0402_5%~D

2
3
4
5
6
7
8
9

19

QS3245_QSOP20~D

A0
A1
A2
A3
A4
A5
A6
A7

OE#

GND

VCC

20
18

B0

17

B1

16

B2

15

B3

14

B4

13

B5

12

B6

11

B7

10

1

2

DOCK_REQ0#
DOCK_GNT0#
DOCK_SPME#
DOCK_PCI_IDSEL
DOCK_LOCK#

DOCK_PCIRST#
DOCK33M

C43

0.1U_0402_16V4Z~D

1 2

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7

R39

0_0402_5%~D

DOCK_CLK_SPCI <<35>>

DOCK_AD[0..31] <<35>>

U36

39

OE1

C C

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_AD[0..31]<<20,31,33>>

B B

PCI_C_BE0#<<20,31,33>>
PCI_C_BE1#<<20,31,33>>
PCI_C_BE2#<<20,31,33>>
PCI_C_BE3#<<20,31,33>>
PCI_DEVSEL#<<20,31,33>>
PCI_STOP#<<20,31,33>>

PCI_PIRQA#<<20>>

PCI_FRAME#<<20,31,33,35>>
PCI_PAR<<20,31,33>>
PCI_IRDY#<<20,31,33,35>>
PCI_PERR#<<20,31,33>>
PCI_TRDY#<<20,31,33>>
PCI_SERR#<<20,31,33>>

PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_DEVSEL#
PCI_STOP#

PCI_PIRQA#
PCI_FRAME#

PCI_PAR
PCI_IRDY#
PCI_PERR#
PCI_TRDY#
PCI_SERR#

OE229VCC1

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

12

A8

13

A9

14

A10

15

A11

16

A12

17

A13

18

A14

19

A15

1

NC1

11

NC2

QS32X245Q2_QVSOP40~D

U35

39

OE1
OE229VCC1

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

12

A8

13

A9

14

A10

15

A11

16

A12

17

A13

18

A14

19

A15

1

NC1

11

NC2

VCC2

GND1
GND2

VCC2

GND1
GND2

40
30

38

B0

37

B1

36

B2

35

B3

34

B4

33

B5

32

B6

31

B7

28

B8

27

B9

26

B10

25

B11

24

B12

23

B13

22

B14

21

B15

10
20

40
30

38

B0

37

B1

36

B2

35

B3

34

B4

33

B5

32

B6

31

B7

28

B8

27

B9

26

B10

25

B11

24

B12

23

B13

22

B14

21

B15

10
20

QS32X245Q2_QVSOP40~D

C659

0.1U_0402_16V4Z~D

1 2

DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9

DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0

C41

0.1U_0402_16V4Z~D

1 2

DOCK_C_BE0#
DOCK_C_BE1#
DOCK_C_BE2#
DOCK_C_BE3#
DOCK_DEVSEL#
DOCK_STOP#

DOCK_PIRQA#
DOCK_FRAME#

DOCK_PAR
DOCK_IRDY#
DOCK_PERR#
DOCK_TRDY#
DOCK_SERR#

CK_33M_DOCKPCI_TERM

1

C42

@

22P_0402_50V8J~D

2

+3VRUN

1

C31

4

0.1U_0402_16V4Z~D

2

QUIETE#

R36
100K_0402_5%~D

1 2

DOCK_PCI_EN#<<35>>
QBUFEN#<<37>>

DOCK_PCI_EN#
QBUFEN#

5

1

P

INB

2

INA

G

3

U3

O

TC7SH32FU_SSOP5~D

DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15

DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23

DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

DOCK_C_BE0#
DOCK_C_BE1#
DOCK_C_BE2#
DOCK_C_BE3#

DOCK_DEVSEL#
DOCK_STOP#

DOCK_PIRQA#
DOCK_FRAME#

DOCK_SERR#
DOCK_IRDY#
DOCK_PERR#
DOCK_TRDY#
DOCK_PAR

DOCK_REQ0#
DOCK_GNT0#
DOCK_SPME#

DOCK_LOCK#
DOCK_PCIRST#

DOCK_PCI_IDSEL

DOCK_C_BE0# <<35>>
DOCK_C_BE1# <<35>>
DOCK_C_BE2# <<35>>
DOCK_C_BE3# <<35>>

DOCK_DEVSEL# <<35>>
DOCK_STOP# <<35>>

DOCK_PIRQA# <<35>>
DOCK_FRAME# <<35>>

DOCK_SERR# <<35>>
DOCK_IRDY# <<35>>
DOCK_PERR# <<35>>
DOCK_TRDY# <<35>>
DOCK_PAR <<35>>

DOCK_REQ0# <<35>>
DOCK_GNT0# <<35>>
DOCK_SPME# <<35>>

DOCK_LOCK# <<35>>
DOCK_PCIRST# <<35>>

DOCK_PCI_IDSEL <<35>>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

DOCKING BUFFER

Size Document Number Rev

Board Number LA2111

Date: Sheet of

34 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

Q34

1
2
3

2

G

DOCK_PWR_SRC

C341

0.1U_0402_16V4Z~D

8
7
6
5

4

12

R343
100K_0402_5%~D

Z3307

13

D

Q38
2N7002_SOT23~D

S

2

1

DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31

JDOCKA

1

S1

2

S2

DVI_CLK-<<18>>

DVI_CLK+<<18>>

DVI_TX4-

D D

PS_ID_IN<<44>>

DOCK_CLK_SPCI<<34>>

DOCK_PIRQA#<<34>>

DOCK_SMB_CLK<<37>>

DOCK_SMB_DAT<<37>>

C C

CLK_SM1<<37>>
DAT_SM1<<37>>

DVI_TX4+

DVI_TX3+
DVI_TX3-

DVI_TX5+
DVI_TX5-

DVI_TX2+<<18>>

DVI_TX2-<<18>>

DVI_TX1+<<18>>

DVI_TX1-<<18>>

DVI_TX0+<<18>>

DVI_TX0-<<18>>

DOCK_AD31

3

S3

4

S4

5

S5

6

S6

7

S7

8

S8

9

S9

10

S10

11

S11

12

S12

13

S13

15

S15

17

S17

18

S18

19

S19

20

S20

21

S21

22

S22

23

S23

24

S24

25

S25

26

S26

27

S27

28

S28

29

S29

30

S30

31

S31

32

S32

33

S33

34

S34

35

S35

36

S36

37

S37

38

S38

39

S39

40

S40

41

S41

42

S42

43

S43

45

S45

47

S47

48

S48

49

S49

50

S50

51

S51

52

S52

53

S53

54

S54

55

S55

AMP_1473681~D

S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122

S125
S126
S127
S128

M136

69

S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99

VGA_RED

70
71
72
73
74
75
76
77
78
79
80
81
82
83

DOCK_AD8

84

DOCK_C_BE0#

85
86
87

DOCK_AD14

88

DOCK_AD15

89
90
91
92
93
94
95

DOCK_AD19

96

DOCK_AD20

97
98
99

DOCK_AD27

100

DOCK_AD28

101

DOCK_AD30

102
103
104

USBP1_D-

105

USBP1_D+

106
107
108
109
110
111

V_2P5_LAN

112
113
114
115
116
117
118
119
120
121
122

125
126
127
128

136

0_0402_5%~D

R34

12

M_SEN# <<19>>

D_SERIRQ <<36>>
DOCK_PCI_IDSEL <<34>>

D_DLRQ1# <<36>>
D_LFRAME# <<36>>

DVI_SCLK <<18>>
DVI_SDAT <<18>>
DVI_DETECT <<18>>

DOCK_C_BE0# <<34>>

DOCK_DEVSEL# <<34>>
DOCK_IRDY# <<34>>

DOCK_GNT0# <<34>>
USBP1_D- <<27>>

USBP1_D+ <<27>>

DOCK_SMB_INT# <<37>>

CLK_KBD <<37>>
DAT_KBD <<37>>

C32

0.01U_0402_16V7K~D

1 2

C33

0.01U_0402_16V7K~D

1 2

DOCK_LAN_TX3- <<30>>
DOCK_LAN_TX3+ <<30>>
DOCK_LAN_TX2- <<30>>
DOCK_LAN_TX2+ <<30>>

DOCK_RING

D_LAD1<<36>>
D_LAD2<<36>>
D_LAD3<<36>>

DOCK_PAR<<34>>
DOCK_SERR#<<34>>
DOCK_LOCK#<<34>>

DOCK_FRAME#<<34>>

DOCK_C_BE2#<<34>>

DOCK_SPME#<<34>>

DOCK_PCI_EN#<<34>>

SPDIF_DOCK<<19>>

DOCK_LED_10#<<30>>
DOCK_LED_100#<<30>>

+3VRUN

C34

0.01U_0402_16V7K~D

12

C35

0.01U_0402_16V7K~D

12

DOCK_LAN_RX-<<30>>
DOCK_LAN_RX+<<30>>
DOCK_LAN_TX-<<30>>
DOCK_LAN_TX+<<30>>

DOCK_DET# DOCK_DET#
VGA_GRN

VGA_BLU
D_LAD1

D_LAD2
D_LAD3

DOCK_AD1
DOCK_AD0

DOCK_AD3
DOCK_AD4
DOCK_AD7

DOCK_AD9
DOCK_AD10
DOCK_AD11

DOCK_C_BE2#
DOCK_AD16

DOCK_AD22
DOCK_AD23
DOCK_AD24

DOCK_AD29

TV_C

SPDIF_DOCK
DOCK_LED_10#

DOCK_LED_100#
DOCK_OWNS_PCI

12

R752
100K_0402_5%~D@

DOCK_TIP

PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR

B B

PCI_GNT0#<<20,34>>

TV_C<<18,19>>

TV_Y<<18,19>>

TV_CVBS<<18,19>>

A A

VGA_RED<<18,19>>

VGA_GRN<<18,19>>

VGA_BLU<<18,19>>

PCI_GNT0#

5

PCI_IRDY#<<20,31,33,34>>

PCI_FRAME#<<20,31,33,34>>

U163

1

NC

2

IN A

3

GND

TC7SH04FU_SSOP5~D

PCI_IRDY#
PCI_FRAME#

TV_C

TV_Y

TV_CVBS

VGA_RED

VGA_GRN

VGA_BLU

VCC

OUT Y

5

4

+3VRUN

5

1

P

B

2

A

G

3

+3VRUN

Z3305

U14

Z3306

4

O

TC7SH08FU_SSOP5~D

DOCK_RING
DOCK_TIP

4

+3VRUN

5

U17

1

P

B

2

A

G

TC7SH08FU_SSOP5~D

3

JST_SM07B-SRSS-TB~D

O

7
6
5
4

1

DOCK_OWNS_PCI

4

J_WIRE

7
6
5
4

9
8

1

+5VALW

R377
100K_0402_5%~D

1 2

DOCK_DET#

9
8

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

JDOCKB

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

174

S174

175

S175

176

S176

177

S177

178

S178

179

S179

180

S180

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

193

S193

194

S194

195

S195

196

S196

204

M204

AMP_1473681~D

2

DOCK_PWR_EN<<37>>

3

205

S205

206

S206

207

S207

208

S208

209

S209

210

S210

211

S211

212

S212

213

S213

214

S214

215

S215

216

S216

217

S217

218

S218

220

S220

222

S222

223

S223

224

S224

225

S225

226

S226

227

S227

228

S228

229

S229

230

S230

231

S231

232

S232

233

S233

234

S234

235

S235

236

S236

237

S237

238

S238

239

S239

240

S240

241

S241

242

S242

243

S243

244

S244

245

S245

246

S246

247

S247

248

S248

250

S250

252

S252

253

S253

254

S254

255

S255

256

S256

257

S257

258

S258

259

S259

+3VALW

R362
100K_0402_5%~D

1 2

13

Q43
DTC144EKA_SOT23~D

HSYNC
VSYNC

D_LAD0
DOCK_SIO_ALERT#

DOCK_AD2
DOCK_AD5
DOCK_AD6

DOCK_AD12
DOCK_AD13
DOCK_C_BE1#

DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#

DOCK_AD17
DOCK_AD18
DOCK_AD21

DOCK_C_BE3#
DOCK_AD25
DOCK_AD26

DOCK_REQ0#
DOCK_PCIRST#

TV_CVBS
TV_Y

DOCK_LAN_ACTLED_YEL#
R_PIDEACT

PWR_SRC

0.47U_0603_16V7K~D

DOCK_PWR_EN

DAT_DDC2 <<18,19>>

CLK_DDC2 <<18,19>>

HSYNC <<18,19>>
VSYNC <<18,19>>

DOCK_SIO_ALERT# <<36>>

DOCK_PERR# <<34>>
DOCK_STOP# <<34>>
DOCK_TRDY# <<34>>

DOCK_REQ0# <<34>>
DOCK_PCIRST# <<34>>

R_PIDEACT <<40>>

2

C348

1

1 2

2

3

D76
SM05_SOT23

1

U41
SN74AHCT1G08DCKR_SC70-5~D

3

2

G

B

4

Y

1

A

P

5

+3VSUS

1 2

R616

0_0402_5%~D@

D_CLKRUN# <<36>>
D_LAD0 <<36>>

DOCK_C_BE1# <<34>>

DOCK_C_BE3# <<34>>

DOCK_LAN_ACTLED_YEL# <<30>>

FDS4435_SO8~D

R346
100K_0402_5%~D

G_DOC_PWRSRC

DOCKED <<30,37>>

Z3308

R363

1 2

100K_0402_5%~D

2

JDOCKC

P1

P1

P2

P2

P3

P3

P4

P4

MH1

MH1

MH5

SHLD1

MH6

SHLD2

MH9

SHLD5

MH10

SHLD6

MH3

MH3

MH13

MH13

MH15

MH15

AMP_1473681~D

DOCK_PWR_SRC

DELL CONFIDENTIAL/PROPRIETARY

Title

DOCKING CONN.

Size Document Number Rev

Board Number LA2111

Date: Sheet of

P5

P5

P6

P6

P7

P7

P8

P8

MH2

MH2

MH7

SHLD3

MH8

SHLD4

MH11

SHLD7

MH12

SHLD8

MH4

MH4

MH14

MH14

MH16

MH16

DOCK_AD[0..31] <<34>>

NB

DOCK_DC_IN

PWR_SRC

DOCK_DC_IN <<44>>

2

C291

0.1U_0805_50V7M~D

1

no power dock

self power dock

1

35 61Monday, February 09, 2004

0.3

+3VALW

R497

D D

+3VALW

DEBUG_EN_CARD<<33>>

DEBUG_OUT_CARD<<33>>

C C

B B

12

10K_0402_5%~D

KSO_17<<40>>

SATA_DET#<<24>>

5

12

R270

10K_0402_5%~D

KSO_17

R1172

4.7K_0402_5%~D

1 2

R361
0_0402_5%~D

0_0402_5%~D

100K_0402_5%~D

12

R269

10K_0402_5%~D

RB751V_SOD323~D

12

R360

+3VALW

R784

12

R271

10K_0402_5%~D

D27

2 1

J1397

1.5mm SMT~D

1

1

2

2

3

3

12

1 2

+RTC_CELL

+3.3VX

R1054

12

10K_0402_5%~D

R228 0_0402_5%~D@

R1239 0_0402_5%~D

CBS_GRST#<<31>>
RUN_ON_D

VAUX_EN<<41,46>>
USB_BACK_EN#<<27>>

SIO_EXT_SMI#<<22>>
SIO_EXT_SCI#<<22>>
SIO_EXT_WAK#<<22>>
SIO_RCIN#<<21>>
NB_MUTE<<26>>
BEEP<<25>>

PCIE_WAKE#<<29>>

SPDIF_SHDN<<19,25>>

DOCK_SIO_ALERT#<<35>>

SIO_PWRBTN#<<22>>
RUN_ON<<18,28,41,42,45,46,48>>
ICH_PME#<<20>>
SIO_THRM#<<22>>
SUS_ON<<41,42,46>>
ICH_PCIE_WAKE#<<18,22>>

5V_CAL_SIO#<<39>>

IDE_RST_MOD<<21>>
FPBACK_EN<<18>>
USB_SIDE_EN#<<27>>

MODC_EN#<<41>>
HDDC_EN#<<41>>

1 2

+3VRUN

PCIE_WAKE#
DOCK_SIO_ALERT#
ATF_INT#
SYS_PME#
DEBUG_ENABLE

HP_NB_SENSE<<26>>

BAY_MODPRES#<<24>>
USB_IDE#<<24>>

SIO_SLP_S3#<<22>>
SYS_PME#<<31,33,34>>
ATF_INT#<<39>>
SIO_SLP_S5#<<22>>

CK_33M_SIOPCI<<6>>

CK_14M_SIO<<6>>

12

L47

BLM11A121S_0603~D

1 2

CBS_GRST#
HP_NB_SENSE
RUN_ON_D
VAUX_EN
KSO17
USB_BACK_EN#
BAY_MODPRES#
USB_IDE#

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAK#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT

PCIE_WAKE#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S5#
SPDIF_SHDN
LID_CL_SIO#
DOCK_SIO_ALERT#

SIO_PWRBTN#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
ICH_PCIE_WAKE#
SATA_DET#
5V_CAL_SIO#

IDE_RST_MOD
FPBACK_EN
USB_SIDE_EN#

MODC_EN#
HDDC_EN#

CK_33M_SIOPCI
CK_14M_SIO

254VCC0

+3VALW

2

C219

0.1U_0402_16V4Z~D

1

+3VRUN

2

C269

0.1U_0402_16V4Z~D

1

4

VAUX_EN

KPLLVCC

R1238
100K_0402_5%~D

1 2

U27A

F13
F14
E16
E15
E12
E13

D16
D15

C16
B16
C15
A16
D14
C14
C13
B14

T5

N6

L6

R6

T6
L7
P7

N7

A15
D13
A14
C12
B13
A13
D12
F11

B12
A12
C11
D11
E11
A11
F10
C10

L3
L4
B2

E2

M7
B11
R13
H12
E14

B7
A1

L11

G2

P4
J2

M2

R5

P6

LPC47N354_LBGA256~D

SGPIO30
SGPIO31
SGPIO32
SGPIO33
SGPIO34
SGPIO35
SGPIO36
SGPIO37

SGPIO40
SGPIO41
SGPIO42
SGPIO43
SGPIO44
SGPIO45
SGPIO46
SGPIO47

LGPIO50
LGPIO51
LGPIO52
LGPIO53
LGPIO54
LGPIO55
LGPIO56
LGPIO57

LGPIO60/SPCLK
LGPIO61/SPDOUT
LGPIO62/SPDIN
LGPIO63
LGPIO64
LGPIO65
LGPIO66
LGPIO67

LGPIO70
LGPIO71
LGPIO72
LGPIO73
LGPIO74
LGPIO75
LGPIO76
LGPIO77

PCI_CLK
CLOCKI
GPIO83/32KHZ_OUT

VCCO/BAT

VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5
VCC1_6
VCC1_7
VCC1_8

VCC2_1
VCC2_2
VCC2_3
VCC2_4

VCC2_5/PLL

VSS13/PLL

LPC47N354

MACALLEN III

8051
GPIO

LPC
GPIO

CLOCK

VCC

256 - LBGA

3

EC_SCI/SPDIN

SER_IRQ

CLKRUN#

LDRQ0#

LPC INTERFACE

LDRQ1#

LFRAME#

LRESET#

DLAD0
DLAD1
DLAD2
DLAD3

DLDRQ1#

DLFRAME#

DSER_IRQ

DCLKRUN#

COM1

GPIO10/WK_SE14/IRMODE/IRRX3B

IR

GPIOB2/SLCTIN

GPIOB1/INIT

GPIOC0/PD0
GPIOC1/PD1
GPIOC2/PD2
GPIOC3/PD3
GPIOC4/PD4
GPIOC5/PD5
GPIOC6/PD6
GPIOC7/PD7

LPT

OUTD0/SLCT

OUTD1/PE

OUTD2/BUSY

OUTD3/ACK

OUTD4/ERROR

GPIOB0/STROBE

GPIOB3/ALF

GND

VSS10
VSS11
VSS12

LAD0
LAD1
LAD2
LAD3

RXD1

TXD1

DSR
RTS
CTS
DTR

DCD

IRRX

IRTX

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

AGND

2

LPCPD#

J12

IRQ_SERIRQ

T4

CLKRUN#

P5

LPC_LAD0

M3

LPC_LAD1

R1

LPC_LAD2

T1

LPC_LAD3

P3

LPC_LDRQ0#

M6

LPC_LDRQ1#

R3

LPC_LFRAME#

N4

PLTRST_SIO#

L2

D_LAD0

N2

D_LAD1

P1

D_LAD2

P2

D_LAD3

N3

D_DLRQ1#

R2

D_LFRAME#

T2

D_SERIRQ

R4

D_CLKRUN#

T3

RXD0

K1

TXD0

K5

DSR0#

K2

RTS0#

K4

CTS0#

K3

DTR0#

K6

RI0#

B10

RI

DCD0#

L1

D_IRMODE

H15

IRRX

K14

IRTX

M4

J4
J5

J1
H2
H1
H3
H4
H5
H6
H8

F1
G5
G1
H7
J6

K7
J7

C2
G4
N5
R15
B15
G9
J3
N1
T10
J11
G14
B6

KAGND

F3

1 2

BLM11A121S_0603~D

L42

IRQ_SERIRQ <<22,29,31>>

CLKRUN# <<22,31,33>>

LPC_LAD[0..3] <<21,29>>

LPC_LDRQ0# <<21>>
LPC_LDRQ1# <<21>>

LPC_LFRAME# <<21,29>>
PLTRST_SIO# <<20>>

D_LAD0 <<35>>
D_LAD1 <<35>>
D_LAD2 <<35>>
D_LAD3 <<35>>

D_LFRAME# <<35>>
D_SERIRQ <<35>>

D_CLKRUN# <<35>>

RXD0 <<28>>
TXD0 <<28>>
DSR0# <<28>>
RTS0# <<28>>
CTS0# <<28>>
DTR0# <<28>>

DCD0# <<28>>

D_IRMODE <<40>>
IRRX <<40>>
IRTX <<40>>

CK_33M_SIOPCI
CK_14M_SIO

R510

D_CLKRUN#
D_SERIRQ

+3VRUN

12

R274
100K_0402_5%~D

D_DLRQ1# <<35>>

+3VALW

12

R1171
10K_0402_5%~D

RI0# <<28>>

+3VALW

12

R282
100K_0402_5%~D

R283

LID_CL_SIO#

12

12

R514

10_0402_5%~D@

10_0402_5%~D@

10_0402_5%~D

1

C272

0.047U_0402_16V7K~D

2

12

12

1

R275
100K_0402_5%~D

LID_CL#

+3VRUN

12

R276
100K_0402_5%~D

LID_CL# <<38>>

+3VRUN+3VALW

1

0.1U_0402_16V4Z~D

1

1

2

C599

0.1U_0402_16V4Z~D

C609

2

2

0.1U_0402_16V4Z~D

2

C608

0.1U_0402_16V4Z~D

3

2

C602

1

1

0.1U_0402_16V4Z~D

2

1

C1283

2

10U_0805_10V4M~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C600

CK_14M_SIO_TERM

CK_33M_SIOPCI_TERM

2

2

C606

1

4.7P_0402_50V8C~D@

1

4.7P_0402_50V8C~D@

DELL CONFIDENTIAL/PROPRIETARY

Title

SIO (1/2)

Size Document Number Rev

Board Number LA2111

Date: Sheet of

1

36 61Monday, February 09, 2004

0.3

1

1

C607

C591

C1282

2

2

0.1U_0402_16V4Z~D

A A

5

10U_0805_10V4M~D

4

5

CLK_SM1<<35>>
DAT_SM1<<35>>

CLK_SM2<<38>>
DAT_SM2<<38>>

CLK_KBD<<35>>
DAT_KBD<<35>>

KSO[0..15]<<38>>

C596

1 2

C597

1 2

KSI[0..7]<<38,40>>

DOCK_SMB_INT#<<35>>

THERMTRIP_SIO<<39>>

SCR_DETECT_C<<31>>

PS_ID_DISABLE#<<44>>

TPM_EN#<<29>>

R1244
10K_0402_5%~D

1 2

DOCKED<<30,35>>

SBAT_ALARM#<<45>>
SBAT_PRES#<<45,51>>
PBAT_PRES#<<45>>

KSO16<<38>>
CAP_LED#<<40>>
NUM_LED#<<40>>
SRL_LED#<<40>>
CHG_SBATT<<50,51>>

PS_ID<<44>>

CLK_SM1
DAT_SM1

CLK_SM2
DAT_SM2

12

X6

32.768KHZ_12.5P_MC-306~D

3.8X12.1mm

CLK_32KX1

R1121
10K_0402_5%~D

SCR_DETECT_C

+3VRUN

+3VALW

+3VALW

D D

+5VALW

C C

For SMSC issue, add schematic at bring-up.
Bill 10/31
For layout space, change to 0402 0 ohm.
Bill 11/04
Macallan III rev A IMCLK/IMDAT pair did not
work properly. MacIII RevB has solved this
issue. Delete R1198 - R1203 and connect
directly.
Steven 01/09/2004

B B

A A

1 2

R1126
100K_0402_5%~D

1 2

R1081

1.5K_0603_5%~D

1 2

R1127
100K_0402_5%~D

1 2

R506

1 2

4.7K_0402_5%~D

12

R759

100K_0402_5%~D

@

+5VRUN

R478

4.7K_0402_5%~D

DAT_KBD
CLK_KBD
CLK_SM1
DAT_SM1 CLK_32KX2

R286

@

BID0
BID1
BID2
BID3

+3VALW+3VALW

R229

R1101

1 2

10K_0402_5%~D

4.7K_0402_5%~D

10K_0402_5%~D

1 2

PS_ID

DOCK_SMB_INT#

+3VALW

R797

1 2

12

R253

1 2

4.7K_0402_5%~D

R278

R280

1 2

10K_0402_5%~D

@

5

IN1

SBAT_LOW

1 2

10K_0402_5%~D

SBAT_ALARM#
PBAT_ALARM#

CHG_SBATT
FPVCC

12

R494

4.7K_0402_5%~D

R266

1 2

10K_0402_5%~D

10K_0402_5%~D

@

+3VALW

PBAT_ALARM#<<45>>

12

R240

4.7K_0402_5%~D

22P_0402_50V8J~D

22P_0402_50V8J~D

+3VRUN

1 2

R287 10K_0402_5%~D

1 2

R279 10K_0402_5%~D@

1 2

R281 10K_0402_5%~D

1 2

R267 10K_0402_5%~D

1 2

4

CHG_SBATT

DOCKED
IN1
DOCK_SMB_INT#
FPVCC
SBAT_ALARM#
SBAT_PRES#
PBAT_PRES#

THERMTRIP_SIO
H_PROCHOT_SIO#
SCR_DETECT_C

KSO16
CAP_LED#
NUM_LED#
SRL_LED#
CHG_SBATT
PS_ID

BID0
BID1
BID2
BID3

SIO_MSCLK
SIO_MSDAT

CLK_KBD
DAT_KBD
PBAT_ALARM#

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6 SIO_FA11
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

0
0

U27B

A9

IN0 (WK_EE4)

B9

IN1 (WK_EE2)

B8

IN2 (WK_EE3)

A8

IN3 (GPWKUP)

C8

IN5 (WK_SE01)

D8

IN6 (WK_SE05)

E8

IN7 (WK_EE1)

H13

GPIO0 (WK_SE02)

H11

GPIO1 (WK_SE03)

H10

GPIO2 (WK_SE04)

G10

GPIO3 (TRIGGER)

G13

GPIO7 (WK_SE06)

J14

GPIO8 (WK_SE12)/IRRX2

J16

GPIO9 (WK_SE13)/IRTX2

G11

GPIO17 (WK_SE23)/A20M

F15

GPIO20 (WK_SE25)/PS2CLK/8051RX

F12

GPIO21 (WK_SE26)/PS2DAT/8051TX

B5

GPIO84

E5

GPIO85

D5

GPIO86

A4

GPIO87

B4

GPIO90

C5

GPIO91

A3

GPIO92

A2

GPIO93

C3

GPIO96

D3

GPIO97

B1

GPIOA0

D4

GPIOA1

C1

GPIOA2

D10

MSCLK/SPCLK

E10

MSDATA/SPDOUT

G6

EMCLK

G3

EMDAT

B3

GPIO94/IMCLK

C4

GPIO95/IMDAT

M1

KCLK

M5

KDAT

G15

GPIO6 (WK_SE11)/IRMODE/IRRX3A

G12

GPIO5 (WK_SE10)/KSO15

G16

GPIO4 (WK_SE07)/KSO14

R7

KSO13/GPIO18(WK_SE27)

T7

KSO12/OUT8/KBRST

K8

KSO11

J8

KSO10

L8

KSO9

M8

KSO8

N8

KSO7

P8

KSO6

T8

KSO5

R8

KSO4

R9

KSO3

T9

KSO2

P9

KSO1

N9

KSO0

M9

KSI7

L9

KSI6

K9

KSI5

K10

KSI4

M10

KSI3

R10

KSI2

N10

KSI1

P10

KSI0

E1

XTAL1

D1

XTAL2

LPC47N354_LBGA256~D

BID2 BID1

0

0

0

0

LPC47N354

MACALLEN III

GPIO

K/B

256 - LBGA

BID0BID3

REV

0

M00

1

M01

MISC

GPIO11 (WK_SE15)/AB2A_DATA

GPIO12 (WK_SE16)/AB2A_CLK

GPIO13 (WK_SE17)/AB2B_DATA

GPIO14 (WK_SE20)/AB2B_CLK
GPIO15 (WK_SE21)/FAN_TACH1
GPIO16 (WK_SE22)/FAN_TACH2

00 01 X00

4

3

FPGM

TEST_PIN

XOSEL
SYSOPT0/GPIO80
SYSOPT1/GPIO81

BAT_LED

PWR_LED

GPIOA3/WINDMON

TESTA

VCC1RST#

RESET_OUT

PWRGD

ACAV_IN

POWER_SW_IN#

ALWON

OUT0

OUT1/IRQ8

OUT2/FRD

OUT3/FWR

OUT4

OUT5/KBRST

OUT6

OUT7/SMI

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

AB1A_CLK

AB1B_DATA

AB1B_CLK

AB1A_DATA

GPIO82/FAN_TACH3

GPIO19 (WK_SE24)

FA10
FA11
FA12
FA13
FA14
FA15

FLASH

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

FA16
FA17
FA18
FA19
FA20
FA21
FA22

FWR

3

FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9

FRD
FCS

FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0

2

+3VALW

12

R273
1K_0402_5%~D

@

R272

SIO_KAH_PGM

L10
K12

XOSEL

E4

SYSOPT0

K15

SYSOPT1

K16

BAT1_LED#

J9

BAT2_LED#

J10
E3
F2

VCC1RST#

D2

RESET_OUT#

L5

RUNPWROK

K13

ACAV_IN

F4
F5

ALWON

F6

EEPROM_WC

D7

DOCK_PWR_EN

C7

HW_RADIO_DIS#

F7

LAN_LOW_PWR

A6

CHG_PBATT

E6

SBAT_LOW

D6

AUDIO_AVDD_ON

C6
E7

QBUFEN#

A7

FAN2_PWM

G7

BREATH_LED

G8

FAN1_PWM

F8

CLK_SMB

C9

DOCK_SMB_DAT

F9

DOCK_SMB_CLK

E9

DAT_SMB

D9

SBAT_SMBDAT

H16

SBAT_SMBCLK

H14

PBAT_SMBDAT

J15

PBAT_SMBCLK

J13

FAN1_TACH

A10

FAN2_TACH

H9
A5

SIO_A20GATE

F16

SIO_FA0

N12

SIO_FA1

T13

SIO_FA2

P12

SIO_FA3

T14

SIO_FA4

T15

SIO_FA5

R16

SIO_FA6

N13

SIO_FA7

P16

SIO_FA8

M14

SIO_FA9

N15

SIO_FA10

N16
M13

SIO_FA12

L12

SIO_FA13

M15

SIO_FA14

M16

SIO_FA15

L14

SIO_FA16

L13

SIO_FA17

L15

SIO_FA18

L16

SIO_FA19

K11
R14
T16
P13

FRD#

P14

FWR#

N14

FCS#

P15

SIO_FD7

M12

SIO_FD6

R12

SIO_FD5

T12

SIO_FD4

P11

SIO_FD3

N11

SIO_FD2

M11

SIO_FD1

R11

SIO_FD0

T11

SIO_FA[0..19] <<38>>

FRD# <<38>>
FWR# <<38>>
FCS# <<38>>

SIO_FD[0..7] <<38>>

10K_0402_5%~D

12

R221 10K_0402_5%~D
R41 10K_0402_5%~D
R1110 10K_0402_5%~D

BAT1_LED# <<40>>
BAT2_LED# <<40>>

VCC1RST# <<38>>
RESET_OUT# <<42>>
RUNPWROK <<18,42,47,49>>

ACAV_IN <<44,50,51>>
ALWON <<46>>
EEPROM_WC <<38>>

DOCK_PWR_EN <<35>>
HW_RADIO_DIS# <<28,33>>
LAN_LOW_PWR <<29>>
CHG_PBATT <<50,51>>
SBAT_LOW <<51>>
AUDIO_AVDD_ON <<25>>

QBUFEN# <<34>>
FAN2_PWM <<15>>
BREATH_LED <<40>>
FAN1_PWM <<15>>

CLK_SMB <<38,39>>
DOCK_SMB_DAT <<35>>
DOCK_SMB_CLK <<35>>
DAT_SMB <<38,39>>
SBAT_SMBDAT <<18,45>>
SBAT_SMBCLK <<18,45>>
PBAT_SMBDAT <<45,50>>

PBAT_SMBCLK <<45,50>>
FAN1_TACH <<15>>
FAN2_TACH <<15>>

SIO_A20GATE <<21>>

12
1 2
1 2

1 2

R1080 10K_0402_5%~D

POWER_SW#POWER_SW_IN#

+3VALW

12

Q72

2

B

MMBT3904_SOT23~D

E

3 1

Level shifter

R544

1K_0402_5%~D

C

POWER_SW# <<39,40>>

H_PROCHOT_SIO#

PROCHOT_SFTON

H_PROCHOT#

DAT_SMB

CLK_SMB

POWER_SW_IN#

SBAT_SMBDAT

SBAT_SMBCLK

PBAT_SMBDAT

PBAT_SMBCLK

DOCK_SMB_DAT

DOCK_SMB_CLK

LAN_LOW_PWR
CHG_PBATT

R547
56_0402_5%~D

1 2

R745
56_0402_5%~D

1 2

1

2

1

+VCCP

+VCCP

H_PROCHOT# <<7>>

R1083

10K_0402_5%~D

1 2

R1084

10K_0402_5%~D

1 2

R1082
100K_0402_5%~D

1 2

C1246
1U_0603_10V4Z~D

R509

8.2K_0402_5%~D

1 2

R517

8.2K_0402_5%~D

1 2

R520

8.2K_0402_5%~D

1 2

R524

8.2K_0402_5%~D

1 2

R480

10K_0402_5%~D

1 2

R481

10K_0402_5%~D

1 2

+3VALW

12

R563

10K_0402_5%~D@

1 2

+3VALW

+3.3VX

+5VALW

+5VALW

R564
100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

SIO (2/2)

Size Document Number Rev

Board Number LA2111

2

Date: Sheet of

37 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

VCC

SDA

+3VALW

1

C212

0.1U_0402_16V4Z~D

2

8
7

WP

6

SCL

5

EEPROM_WC
CLK_SMB
DAT_SMB

EEPROM_WC <<37>>
CLK_SMB <<37,39>>
DAT_SMB <<37,39>>

+3VALW

12

R555
0_0402_5%~D

U23

1

D D

+5VRUN

L40

BLM31A260SPT_1206~D

12

1

C200

2

10
11
12

JPALM

1
2
3
4
5
6
7
8
9

13

1
2
3
4
5
6
7
8
9
10
11
12

14

0.1U_0402_16V4Z~D

MOUSEVDD
MOUSEDAT

MOUSECLK
TP_Z

TP_V+
TP_Y
TP_X
TP_GND

LID_CL#<<36>>

LID_CL#

+5VRUN

12

12

R192

R193

4.7K_0402_5%~D

C196

4.7K_0402_5%~D

10P_0402_50V8J~D

1

C195

2

10P_0402_50V8J~D

DAT_SM2<<37>>
CLK_SM2<<37>>

C C

DAT_SM2
CLK_SM2

BLM11A601S_0603~D

1 2
1 2

BLM11A601S_0603~D

1

2

L39

L38

1

10P_0402_50V8J~D

1

C187

2

2

10P_0402_50V8J~D

C188

NC

2

A1

3

A2

4

VSS

AT24C04N-10SI-2.7_SO8~D

SUB_6782U

SMbus address A2

13

14

MOLEX_53398-1290~D

Keep no nosie coupled,

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7

B B

KSO[0..15]<<37>>

KSI[0..7]<<37,40>>

A A

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO6
KSO8
KSO3

KSO2
KSO0
KSO12
KSO16

KSO16<<37>>

KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

CN7

CN12

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

@

CN11

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

CN10

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

CN9

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

CN8

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

JKYBRD

JAE_FK2S030W11~D

1

C205
100P_0603_50V8J~D

@

2

25
24
23
22
21
20
19
18
17
16
15

30
29

14
13

28
27

12
11

26
10
9
8

31
7

32
6
5

33
4

34
3
2
1

Especially the TP_GND

SIO_FA[0..19]<<37>>

TP_V+
TP_X
TP_GND
TP_Y
TP_Z

G

2N7002

C633

VCC1RST#

12

0.1U_0402_16V4Z~D

1

2

+3VALW

C634

0.1U_0402_16V4Z~D

1

2

SIO_FD[0..7] <<37>>

VCC1RST# <<37>>

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8KSO1
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

FCS#<<37>>
FRD#<<37>>
FWR#<<37>>

FCS#
FRD#
FWR#

D

S

U61

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

MX29LV008T/B_TSOP40~D

C

1
B
2

VCC
VCC
VPP

RP#/RESET#
WP#/RY/BY#

GND
GND

E
3

31
30
11

SIO_FD0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC
NC

SIO_FD1

26

SIO_FD2

27

SIO_FD3

28

SIO_FD4

32

SIO_FD5

33

SIO_FD6

34

SIO_FD7

35

FWH_RST

10
12
29
38

23
39

R289

0_0402_5%~D

DTC114

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

INT KB

Size Document Number Rev

Board Number LA2111

Date: Sheet of

38 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

+3VSUS

12

R1240
100K_0402_5%~D

ICH_PWRGD#

13

D D

ICH_PWRGD<<22,42>>

2

G

D

Q128

2N7002_SOT23~D

S

H_THERMDA<<7>>

+3VSUS

12

R112

8.2K_0402_5%~D

+VCCP

R107

2.2K_0402_5%~D

1 2

MMBT3904_SOT23~D

Q9

H_THERMTRIP#<<7>>

THERMATRIP1#

C

2

B

1

C84

E

3 1

0.1U_0402_16V4Z~D

2

H_THERMDC<<7>>

+3VSUS

+RTC_CELL

0.1U_0402_16V4Z~D

C C

+VCCP

R106

2.2K_0402_5%~D

1 2

MMBT3904_SOT23~D

THERMTRIP_MCH#<<10>>

B B

+3VSUS

12

R108

8.2K_0402_5%~D

+3VSUS

THERMATRIP2#

C

2

B

Q7

1

C86

E

3 1

0.1U_0402_16V4Z~D

2

2200P_0402_25V7K~D

R45

49.9_0603_1%~D

1 2

C64

0.1U_0402_16V4Z~D

1

C66

2

12

R69

30.1K_0603_1%~D

12

R72

12.1K_0603_1%~D

1

C63

2

1

2

SUSPWROK<<22,32,42>>

ICH_PWRGD#

POWER_SW#<<37,40>>

THERMATRIP_VGA#<<18>>

1 2

R49 8.2K_0402_5%~D

1

2

DAT_SMB<<37,38>>
CLK_SMB<<37,38>>

THERMATRIP_VGA#

C68

2200P_0402_25V7K~D

1 2

R43 1K_0402_5%~D

1 2

R46 1K_0402_5%~D

1 2

R47 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#

1

1 2

C67

2

0.1U_0402_16V4Z~D

U70

1

THDAT_SMB

2

THCLK_SMB

13

SMBADDRSEL

18

REM_DIODE2_P

17

REM_DIODE2_N

4

+3VSUS

11

VSUS_PWRGD

10

+RTC_PWR3V

5

+3V_PWROK

21

POWER_SW

6

THERMTRIP1

7

THERMTRIP2

8

THERMTRIP3

22

VSET

14

HW_LOCK

3

VSS

EMC6N300_SSOP24~D

ATF_INT

VCP

RESSERVED

REM_DIODE1_N
REM_DIODE1_P

THERMTRIP_SIO

THERM_STP

INTRUDER

+5VSUS

12

9

R76

2.21K_0603_1%~D

23

1

C70

2

16

19
20

15
24

2200P_0402_25V7K~D

+3VALW

12

12

R48

1K_0402_5%~D

2N7002_SOT23~D

R103
100K_0402_5%~D

ATF_INT# <<36>>

12

R104
10KB_0603_1%_TSM1A103F34D3R~D

13

D

Q5

2

G

S

1

C78

2

2200P_0402_25V7K~D

THERMTRIP_SIO <<37>>
THERM_STP# <<46>>
INTRUDER# <<21>>

E

B

2

+5VSUS

12

R1061
10K_0402_5%~D

31

Q3

C

MMBT3904_SOT23~D

5V_CAL_SIO# <<36>>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Thermtrip

Size Document Number Rev

Board Number LA2111

Date: Sheet of

39 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

OUT

GNDIN

1

32

12

12

+3VALW

R320
150_0603_5%~D

1 2

Z3901

C

Q26
MMBT3904_SOT23~D

E

3 1

R_BREATH_LED

DTA114YKA

R328

470_0603_5%~D

R329

470_0603_5%~D

R327

470_0603_5%~D

BAT1_LED

LED_WLAN_OUT<<33>>

CAP_LED

12

NUM_LEDR_NUM

12

SRL_LED

12

+3VRUN

47K

Q29

1 3

R_PIDEACT

DTA114YKA_SC59~D

R314

470_0603_5%~D

ACTLED

12

R_PIDEACT <<35>>

SATA_ACT#<<21>>

2

10K

+3VRUN

+3VRUN

D D

47K

Q31

1 3

R_CAP

R_SRL

470_0603_5%~D

470_0603_5%~D

DTA114YKA_SC59~D

R312

R313

2

B

CAP_LED#<<37>>

47K

10K

+5VALW

47K

10K

R321

10K_0402_5%~D

1 2

2

1 3

2

1 3

NUM_LED#<<37>>

SRL_LED#<<37>>

C C

BAT1_LED#<<37>>

BAT2_LED#<<37>>

B B

BREATH_LED<<37>>

2

2

2

10K

47K

Q32

10K

Q30
DTA114YKA_SC59~D

10K

Q28
DTA114YKA_SC59~D

BREATH_LED_B

DTA114YKA_SC59~D

1 3

47K

Q27
DTA114YKA_SC59~D

1 3

R_BAT1_LED

R_BAT2_LED BAT2_LED

BAT1_LED
BAT2_LED
R_BREATH_LED
ACTLED

R450

47_0805_5%~D

IRRX<<36>>

R_BT_MPCI_ACT
LED_WLAN_OUT

CAP_LED
NUM_LED
SRL_LED

IRVCC

12

2

C570

C571

1

0.1U_0402_16V4Z~D

1

2

4.7U_1206_16V6K~D

JLED1

7

1

7

1

2

2

3

3

4

4

5

5

6

6

8

MOLEX_53398-0690~D

8

JSW1

1
3
5
7
9

11
13
15

SUYIN_127178MS016G200ZR~D

+3VRUN

U52

2

IRED_C

4

RXD

6

VCC

8

GND

TFDU6102-TR3_8P

1
3
5
7
9
11
13
15

2
4
6

8
10
12
14
16

R455

1.8_1206_5%~D

IRED_A

SD/MODE

MODE

2
4
6
8
10
12
14
16

TXD

Z3903

12

@

R454

12

0_0402_5%~D

1
3
5
7

R453

1K_0402_5%~D

KSO_17
KSI4
KSI5
KSI6

POWER_SW#
POWER_SW_EMI

R456

1.8_1206_5%~D

12

IR_ANODE

IRTX <<36>>

12

KSO_17 <<36>>
KSI4 <<37,38>>
KSI5 <<37,38>>
KSI6 <<37,38>>

POWER_SW# <<37,39>>

1

C573

2

4.7U_1206_16V6K~D

SD_MODE

R451

1K_0402_5%~D

12

0_0402_5%~D @

1 2

R214

R452

0_0402_5%~D

+5VALW

12

D_IRMODE <<36>>

+3VALW

R422
150_0603_5%~D

1 2

A A

BT_ACTIVE<<28>>

BT_ACTIVE

5

R421

10K_0402_5%~D

1 2

BT_MPCI_ACTIVE

2

B

E

Z3902

C

Q50
MMBT3904_SOT23~D

3 1

R1186
470_0402_5%~D

1 2

R_BT_MPCI_ACT

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

JLED/IR/PS2

Size Document Number Rev

Board Number LA2111

Date: Sheet of

40 61Monday, February 09, 2004

1

0.3

5

+3VSRC

Run Planes Enable

+15V+5VALW

Q120

2

G

12

R1129
100K_0402_5%~D

RUN_ENABLE

1

13

D

2

S

C1253

12

R1242

4700P_0402_25V7K~D

100K_0402_5%~D@

D D

100K_0402_5%~D

RUN_ON_5V#

RUN_ON<<18,28,36,42,45,46,48>>

2N7002_SOT23~D

C C

12

R1128

13

D

2N7002_SOT23~D

2

G

S

Q61

Wait change Q55, Q57 to FDC653N.

R612

12

200K_0402_5%~D

SUS_ON

2

G

PWR_SRC

11
12

R610
100K_0402_5%~D

13

D

Q80
2N7002_SOT23~D

S

R1193
0_0402_5%~D

1 2

12

R611
470K_0402_5%~D

PWR_SRC

12

R609
100K_0402_5%~D

B B

VAUX_EN<<36,46>>

A A

N21917830

13

D

2

Q81

G

S

2N7002_SOT23~D

SUS_ON<<36,42,46>>

5

4

C475

4.7U_1206_16V6K~D

C471

C485

2

G

+3VRUN

12

1

R113
10K_0402_5%~D

2

+5VRUN

1

12

R426
10K_0402_5%~D

2

4.7U_1206_16V6K~D

1

1
2
36

C480

2

4.7U_1206_16V6K~D

+1.8VRUN

1

12

R441

10K_0402_5%~D

2

4.7U_1206_16V6K~D

12

R606
200K_0402_5%~D

13

D

Q78

S

2N7002_SOT23~D

Q12

SI4810DY_SO8~D

8
7

5

+5VSUS

+1.5VSUS

+1.5VSUS

+1.8VSUS

ENAB_3VLAN <<29>>

PWR_SRC

2

G

1
2
36

4

Q54

D

SI3456DV-T1_TSOP6~D

6

S

45
2
1

G

3

Q131

D

SI3456DV-T1_TSOP6~D

6

S

45
2

@

1

G

3

Q55

SI4800DY-T1_SO8~D

8
7

5

6
2

1

12
11

R605
100K_0402_5%~D

13

D

S

Q57

D

SI3456DV-T1_TSOP6~D

S

G

3

SUS_ON#

Q79

R608

2N7002_SOT23~D

4

4

45

12

200K_0402_5%~D

+3VRUN Source

+5VRUN Source

+1.5VRUN Source

+1.5VRUN

12

R439
10K_0402_5%~D

+1.8VRUN Source

+3VSRCPWR_SRC

R607

8
7

5

12

470K_0402_5%~D

Q77

SI4810DY_SO8~D

4

1

C680

2

0.1U_0402_16V4Z~D

3

RUN_ON_5V#

SUS_ON#

+VCC_CORE

12
1

Z4005

2

13

D

2

G

S

+0.9V_DDR_VTT +3VRUN

12

Z4006

2

G

12

R1249
22_0805_5%~D

Q129

13

D

2N7002_SOT23~D

S

1

2

13

R536
47_0805_5%~D

Q67
2N7002_SOT23~D

+1.5VSUS +1.8VSUS

2

G

R199
22_0805_5%~D

Q19

D

2N7002_SOT23~D

S

2

G

12

13

D

S

12
1

R603
22_0805_5%~D

Z4007

2

Q76

13

D

2N7002_SOT23~D

2

G

S

R1250
47_0805_5%~D

Q130
2N7002_SOT23~D

2

+5HDD Source

DTC144EKA_SOT23~D

HDDC_EN#<<36>>

Q69

47K

2

47K

+5VMOD Source

+3VSUS
1
2

+3VSUS Source

36

1

C681

4.7U_1206_16V6K~D

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

MODC_EN#<<36>>

Q16

DTC144EKA_SOT23~D

47K

2

47K

2

+1.5VRUN +VCCP +1.8VRUN

12
1

Z4009

22

13

D

2

G

S

Q66

6

2

1

SI3456DV-T1_TSOP6~D

D

S

+5VHDD

4 5

1

C629

2

4.7U_1206_16V6K~D

6

2

Q4

D

SI3456DV-T1_TSOP6~D

S

+5VMOD

4 5

1

12

2

+15V

12

R534
100K_0402_5%~D

HDD_EN

13

+15V

12

R440
100K_0402_5%~D

2

13

2

G

MOD_EN

C489

12
1

R770
22_0805_5%~D

Z4008

2

Q83

13

D

2N7002_SOT23~D

S

1

C620

2

0.01U_0402_16V7K~D

3

1

2

0.01U_0402_16V7K~D

+5VSUS

G

3

+5VSUS

1

G

C477

4.7U_1206_16V6K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

POWER CONTROL

Size Document Number Rev

Date: Sheet of

R771
22_0805_5%~D

Q84
2N7002_SOT23~D

+5VRUN

1 2

R1181

0_0805_5%~D@

12

R535

100K_0402_5%~D

MOD_EN

R438
100K_0402_5%~D

Board Number LA2111

1

12
1

R772
47_0805_5%~D

Z4010

Q85

13

D

2N7002_SOT23~D

2

G

S

Delete +3VHDD Source.
Bill 11/06

+3VSUS

6

2

1

D

Q2

G

3

S

4 5

1

C53

2

4.7U_1206_16V6K~D

1

SI3456DV-T1_TSOP6~D

+3VMOD

12

R292
100K_0402_5%~D

41 61Monday, February 09, 2004

0.3

5

4

3

2

1

+3VSUS

U12B

IMVP_PWRGD<<10,22,49>>

IMVP_PWRGD

ITP_DBRESET#<<7>>

D D

C C

4

IN1

5

IN2

RESET_OUT#<<37>>

74VHC08MTC_TSSOP14~D

6

OUT

+3VSUS

5

U180

1

P

A

4

Y

2

B

G

SN74AHCT1G08DCKR_SC70-5~D

3

ICH_PWRGD <<22,39>>

+3VRUN

12

R202
100K_0402_5%~D

5VRUNRC

1

C55

0.1U_0603_25V7M~D

2

+3VSUS

C58

0.1U_0603_25V7M~D

1 2

8

P

7

A1Y

G

U21A

4

SN74LVC3G14DCTR_SSOP8~D

+3V_PWROK#

+3VSUS

A6Y

SUS_ON<<36,41,46>>

8

P

2

G

U21B

4

SN74LVC3G14DCTR_SSOP8~D

RUN_ON<<18,28,36,41,45,46,48>>

1.5VSUS_PWRGD

10

1
2

9

+3VSUS

14

P

IN1

OUT

IN2

G

7

+3VSUS

IN1

OUT

IN2

C54

0.47U_0603_16V7K~D

1 2

U12A
74VHC08MTC_TSSOP14~D

3

+3VSUS

13

IN1

12

IN2

8

U12C
74VHC08MTC_TSSOP14~D

RUNPWROK

11

OUT

U12D
74VHC08MTC_TSSOP14~D

RUNPWROK <<18,37,47,49>>

SUSPWROK <<22,32,39>>

+1.5VSUS +3VALW

12

R1229

12

R1230

10K_0402_5%~D

B B

A A

C1289

0.1U_0603_16V7K~D

10K_0402_5%~D

1

2

C

2

B

E

3 1

Q127
MMBT3904_SOT23~D

+3VSUS

8

P

5

A3Y

G

U21C

4

SN74LVC3G14DCTR_SSOP8~D

1.5VSUS_PWRGD

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Power Sequence

Size Document Number Rev

Board Number LA2111

Date: Sheet of

42 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

Fiducial Mark

CF2

1

FIDUCIAL MARK~D

CF6

1

FIDUCIAL MARK~D

CF10

1

FIDUCIAL MARK~D

PCB Fiducial Mark (SMD40M80)

FD2

1

FIDUCIAL MARK~D

FD8

1

FIDUCIAL MARK~D

PCB Fiducial Mark (FIDUCIAL)

CF3

1

FIDUCIAL MARK~D

CF7

1

FIDUCIAL MARK~D

CF11

1

FIDUCIAL MARK~D

FD3

1

FIDUCIAL MARK~D

FD9

1

FIDUCIAL MARK~D

CF4

1

FIDUCIAL MARK~D

CF8

1

FIDUCIAL MARK~D

CF12

1

FIDUCIAL MARK~D

FD10

1

FIDUCIAL MARK~D

H7

H_C276D110

1

H16

H_C276D87

1

H2
H_T315B276D87

1

H3

H_T315B276D87

1

H4

H_T315B276D87

1

H5

C382D382N~D

1

CPU Side Docking Side

H11

H_T236B276D87

1

H17

H_T236B276D110

1

H12

H_T315B276D110

1

H18

H_C276D110

1

H13

H_C276D110

1

H19

H_C276D110

1

H14

H_C276D110

1

H20

H_T236B276D110

1

H15

H_C276D110

1

H25

H_C276D110

1

H6

H_O463X408D433X378

1

CF1

1

FIDUCIAL MARK~D

CF5

1

FIDUCIAL MARK~D

CF9

1

FIDUCIAL MARK~D

H1

H_T315B276D87

1

D D

M/B Side

FD7

1

C C

H22

H_C176BC256D146

1

H10

H_O148X128D118X98

1

H27

H_C236D110

1

H28

H_C236D110

1

FIDUCIAL MARK~D

MDC Side M/B Support Hold

EMI Clip

CLP1
EMI_CLIP

B B

CLP5
EMI_CLIP

CLP7
EMI_CLIP

CLP9
EMI_CLIP

GND

GND

GND

GND

1

1

1

1

1

1

1

1

1

CLP2
EMI_CLIP

GND

CLP4
EMI_CLIP

GND

CLP6
EMI_CLIP

GND

CLP8
EMI_CLIP

GND

CLP10
EMI_CLIP

GND

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

PAD and Standoff

Size Document Number Rev

Board Number LA2111

Date: Sheet of

43 61Monday, February 09, 2004

1

0.3

5

D D

PR218

1 2

@ 4.7K_0402_5%~D

PS_ID_IN<<35>>

C C

PS_ID_IN

PR226

1 2

100K_0402_5%~D

PR227

1 2

15K_0603_5%~D

MMBT3904_SOT23~D

PQ45

2N7002_SOT23~D

PQ46

1 3

2

B

D

G

2

C

E

3 1

0_0402_5%~D

S

1 2

PR231

4

+5VALW

+5VALW

PR228

100K_0402_5%~D

2

3

@ DA204U_SOT323~D
PD35

1

1 2

PR229

0_0402_5%~D

1 2

PR230

@ 0_0402_5%~D

1 2

3

PWR_SRC

+3VALW+3VALW

Follow DS2501controllor reccomendation,
so change from 1.5k to 2.2k ohms.
0205/04-Modify by Joseph

PR219

1 2

2.2K_0402_5%~D

PS_ID <<37>>

1

PC174

2

PS_ID_DISABLE# <<37>>

0.1U_0603_25V7K~D

1 2

10K_0402_5%~D

PR197

2

+3.3VX Source

PU13

1

IN

RTC_SHDN#

5

MAX1615EUK_SOT23-5~D

#SHDN

1

COINCELL

12

R215
1K_0402_5%~D

+3.3VX

+3.3VX

3

OUT

4

5/3+

GND

2

PC10

12

1U_0805_10V7K~D

Z4012

2

3

1

D75
BAT54C_SOT23~D

+RTC_CELL

1

C1050

2

1U_0603_6.3V6M~D

Add 0.1uF 11/07

ACAV_IN <<37,50,51>>

DOCK_DC_IN<<35>>

1 2

PR11

150K_0402_5%~D

DC_IN+ Source

PQ1

FDS6679Z_SO8~D

1
2
3 6

12

PQ_G

PR13

8
7

5

4

12

100K_0402_5%~D

12

PC6

0.01U_0402_25V7K~D

THE POINT

NOTE: "THE POINT LOCATED
AT PS MODULE

+DC_IN

12

12

12

PC8

PC7

0.1U_0805_50V7M~D

PR12

3

4.7K_0805_5%

0.1U_0805_50V7M~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

PC9

2

10U_1210_25V7K

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet of

+DCIN

Board Number LA2111

1

44 61Monday, February 09, 2004

0.3

PL1

BLM11A121S_0603~D

Z-series AC Adaptor
Connctor

B B

A A

PJPDC1
FOXCONN_JPD1138-506 DC-IN

9

GND_4

8

GND_3

7

GND_2

6

GND_1

5

Low_PWR

DC+_1
DC+_2
DC-_1
DC-_2

MH1

MH2

PWR_ID

1
2

DCIN+

3
4
5

DCIN-

PS_ID_IN

12

PL2

PL3

PL4

PS_ID_IN <<35>>

DOCK DC_IN

PC5

3

4

@ FBM-L11-453215-900LMAT_1812~D

1 2

OC8070-A301~D

2
1 4

@ FBM-L11-453215-900LMAT_1812~D

1 2

0.47U_1812_50V7M~D

5

+3VALW

4

3

2

1

ESD Diodes

2

2

3

Secondary Battery Connector

D D

PC2

2200P_0402_50V7K~D

12

10
11

PJP1

BATT_PRES#

GND
GND

SUYIN_200025MR009G500NL~D

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT_VOLT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4301
Z4302
Z4303

Update PJP1 symbol -01/29/2004

PD1

@ DA204U_SOT323~D

PR2

100_0402_5%~D

1 2

+3VALW

1

PD2

@ DA204U_SOT323~D

PR3

100_0402_5%~D

1 2

3

1

2

PR4

100_0402_5%~D

1 2

3

PD3

1

@ DA204U_SOT323~D

100_0402_5%~D

1 2

ESD Diodes

2

3

2

3

C C

Primary Battery Connector

PJP2

12

PC4

2200P_0402_50V7K~D

BATT_PRES#

10

GND

11

GND

SUYIN_200275MR009G516ZL~D

BATT1+

BATT2+
SMB_CLK
SMB_DAT

SYSPRES#

BATT_VOLT

BATT1­BATT2-

1
2
3
4
5
6
7
8
9

Z4304
Z4305
Z4306

PD5

@ DA204U_SOT323~D

PR7

100_0402_5%~D

1 2

PD6

1

@ DA204U_SOT323~D

PR8

100_0402_5%~D

1 2

1

PR9

100_0402_5%~D

1 2

3

PD7

1

@ DA204U_SOT323~D

100_0402_5%~D

1 2

2

PR5

2

PR10

3

PD4

1

@ DA204U_SOT323~D

2

3

PD8

1

@ DA204U_SOT323~D

SBAT_SMBCLK <<18,37>>
SBAT_SMBDAT <<18,37>>

SBAT_ALARM# <<37>>

PBAT_SMBCLK <<37,50>>
PBAT_SMBDAT <<37,50>>

PBAT_ALARM# <<37>>

PL21

FBM-L11-453215-900LMAT_1812~D

1 2

PC1

1 2

0.1U_0805_50V7M~D

FBM-L11-453215-900LMAT_1812~D

1 2

PC3

1 2

0.1U_0805_50V7M~D

PL22

+3VALW

SBATT+

PBATT+

PR1

10K_0402_5%~D

+3VALW

PR6

12

12

10K_0402_5%~D

SBAT_PRES# <<37,51>>

PBAT_PRES# <<37>>

9

8

7

6

5

4

3

2

1

SUYIN_20175A-09G1
TOP view

B B

+2.5VRUN

PU2

+3VSUS +2.5VRUNP

12

+3VSUS

12

PR38

2P5V_PWRGD

A A

PJP5

1 2

PAD-OPEN 4x4m

+2.5VRUN+2.5VRUNP

RUN_ON<<18,28,36,41,42,46,48>>

1 2

PR233

27K_0402_5%~D

Add Delay schematic, the value wait change.

10K_0402_5%~D

12/16 Change to PWR materials

12

PC33

PC32

0.1U_0805_25V7K~D

RUN_ON_2.5

1

PC176

2

0.1U_0603_25V7K~D

1U_0805_10V7K~D

Change PR233 to achieve proper 1ms powerup delay.

Modify PR233 from 10 k to 27k by Joseph. -02/05

5

4

1

IN

OUT

2

IN

OUT

3

POK

SET

SHDN#4GND1

GND2

MAX1806EUA25_8UMAX~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

R1=R2* (Vo/ 0.8 -1), R2:25K~100K.

8
7
6
5

9

3

PR37

66.5K_0402_1%

PR39

30.9K_0402_1%~D

12

PC34

10U_1206_6.3V7K~D

12

12

12

PC35

0.1U_0805_25V7K~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet of

Battery Conn./+2.5V

Board Number LA2111

45 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

DC/DC +3V/ +5V/ +15V

Reserve Jump for EMI test

PJP21

1

+

2

330U_D3L_6.3VM_R25~D

12

PAD-OPEN 4x4m

12

PC53

0.1U_0805_50V7M~D

SUS_ON<<36,41,42>>
VAUX_EN<<36,41>>

PWR_SRC

D D

Design current 3.4A for +3.3VSRC
Peak current 4.758A for +3VSRCP

+3VSRCP

PC52

C C

B B

3V_5V_PWR_SRC

1

PC36

2

PC168

10U_1206_25V6M

10U_1206_25V6M

Place these CAPs
close to FETs

4.7U_SPC-1205P-4R7B_+40-20%~D

PR45

@ 0_0402_5%~D

1 2

PR47

1 2

0_0402_5%~D

0.1U_0603_25V7K~D

PC56

12

1 2

1
2

1

2

PL10

3

G

I1

O

I0

P

5

PU4
TC7SH32FU_SSOP5~D

+3.3VX

PR40

VCC_MAX1999

1 2

4.7_1206_5%~D

12

12

PC42

PC41

12

12

PC46

PC47

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PQ6
FDS6994S_SO8~D

5

4

D1

G1

3

6

S1

D1

2

7

G2

D2

8

1

D2

S2

4

SUS_ON<<36,41,42>>

PR56

240K_0402_5%~D

ALWON<<37>>

THERM_STP#<<39>>

4.7U_1206_25V6K~D

0.1U_0805_50V7M~D

PC49

0.1U_0805_50V7M~D

PR183

0_0603_5%~D

FB3

PR55

2K_0402_1%~D

1 2

1 2

1K_0402_5%~D

12

12

PC57

@ 1000P_0402_50V7K~D

PR61

1 2

PR43
0_0603_5%~D

1 2

12

PR41

47_0603_5%~D

12

1

PC45

2

1U_0603_6.3V6M~D

20
17

6

BST3

28

DH3 DL5

26
27
24
22

7
3

4

25

Change PC55 from 10U to 4.7U

12

PC55

4.7U_1206_10V7K

PU3

V+
VCC
SHDN
BST3
DH3
LX3
DL3
OUT3
FB3
ON3

ON5
LDO3

+3VALW

PR54

1

PD12

2

RB717F_SOT323~D

SKIP

MAX1999EEI_QSOP28~D

12

MAX1999_SKIP#

0_0402_5%~D

12

Adding SKIP control

@ 0_0402_5%~D

3

LDO5
BST5

DH5

LX5

DL5

OUT5

N.C.
FB5

PRO

ILIM5
ILIM3

REF
TON
GND

PGOOD

PR51

12

PR217

@ 0_0402_5%~D

12

+5VALW

12

PC43

4.7U_1206_10V7K

BST_5BST_3

PR42

18

0_0603_5%~D

BST5

14

1 2

DH5

1 2

16
15
19
21

1
9
10

11
5
8
13
23
2

PR184

LX5

0_0603_5%~D

FB5
PRO#

ILIM5
ILIM3
REF

TON

12

PC54

1U_0805_10V7K~D

VCC_MAX1999

RUN_ON <<18,28,36,41,42,45,48>>

1

PC44

2

1U_0603_6.3V6M~D

PC48

0.1U_0805_50V7M~D

1 2

+3VSRCP

PR48

1 2

100K_0402_5%~D

Place these CAPs
close to FETs

12

PC39

0.1U_0805_50V7M~D

578

PQ5
SI4800DY-T1_SO8~D

3 6

241

578

PQ36
SI4810DY_SO8~D

3 6

241

SUSPWROK_5V <<48>>

ILIM5
ILIM3
PRO#
TON

PC40

12

PD11

2 1

2200P_0402_50V7K~D

EC11FS2_SOD106~D

15VS

1 4

PR49

1 2

49.9K_0402_1%~D

PR57

1 2

150K_0402_1%~D

12

PC38

2.2U_1206_25V7M

PL9

7.3uH_STQ125A-7322H_7A_+-30%~D

3 2

REF

PR50

68K_0402_1%~D

1 2

PR58

1 2

60.4K_0402_1%~D

Modify by Joseph 01/28/04

PR245

100_0805_5%

1 2

PD34

2

MMBZ5245B_SOT23~D

Design current 4A for +5VSUS
Peak current 5.7A for +5VSUSP

PR44

1 2

@ 0_0402_5%~D

PR46

1 2

0_0402_5%~D

VCC_MAX1999

PR52

@ 0_0402_5%~D

1 2

PR53

0_0402_5%~D

1 2

PR59

PR60

1 2

1 2

0_0402_5%~D

@ 0_0402_5%~D

PC51

+15VP

1

12

PC196

+5VSUSP

PC50

330U_D3L_6.3VM_R25~D

2.2U_1206_25V7M

1

+

2

3

12

0.1U_0805_50V7M~D

+15VP

+5VSUSP

+3VSRCP

A A

PJP6

2 1

PAD-OPEN 2x2m~D

PJP7

1 2

PAD-OPEN 4x4m
PJP8

1 2

PAD-OPEN 4x4m

5

(150mA,Via NO.= 2)

+15V

(6A,240mils ,Via NO.= 12)

+5VSUS

(4A,160mils ,Via NO.= 8)

+3VSRC

+3VSRCP:
OCP: (((Ilim3 / 10) /Low-side MOSFET Rdson) +0.5* IL)*(+-1.07)
Ilimit3=REF(60.4K/60.4K+68K)=0.94V
Low side MOSFET Rdson:22.75m ohms at 100C
iL=((Vin-Vo) / L)*Ton=((19.5-3.3) / 4.7u )* ((1/300K) * 3.3/19.5))=1.944 A
OCP TYP: 5.1A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+5VSUSP
OCP: (((Ilim5 / 10) /Low-side MOSFET Rdson) +0.5* IL)*(+-1.07)
Ilimit5=REF(150K/150K+49.9K)=1.5V
Low side MOSFET Rdson: SI4810DY =25m ohms at 100C
iL=((Vin-Vo) / L)*Ton=((19.5-5) / 7.3u )* ((1/200K) * 5/19.5))=2.546 A
OCP TYP: 7.273A

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet of

+3.3V/+5V/+15V

Board Number LA2111

1

46 61Monday, February 09, 2004

0.3

A

B

C

D

+1.5VSUSP / +VCCP_1P05VP

Reserve Jump for EMI test

1 1

1

PC58

PC59

2

10U_1206_25V6M

Design current 3A for +1.5VSUSP

2 2

+1.5VSUSP

12/12 Depopulate PD30, PD31

3 3

4 4

12/10 Modify PL12 for hight limiation

12

PJP9

1 2

PAD-OPEN 4x4m
PJP10

1 2

PAD-OPEN 4x4m

12

PR76

10K_0402_1%~D

12

PR80

20K_0402_1%~D

PD30

@ RB751V-40_SOD323~D

1

+

2 1

PC77

220U_D_2.5VM~D

+1.5VSUSP

+VCCP

PC79

2

0.1U_0805_25V7K~D

PL12

5uH-SIL1035_5.5A_30%~D

1 2

12

PR77

0_0402_5%~D

12

PC69

@ 1000P_0402_50V7K~D

12/18 Delete PR232 not need.

VCCP_PWRGD<<49>>

SUSPWROK_1P8V<<48>>

+1.5VSUS

+VCCP_1P05VP

12

1 2

0.1U_0805_50V7M~D

FDS6994S_SO8~D

4
3
2
1

RUNPWROK<<18,37,42,49>>

PQ8

PC60

2200P_0402_50V7K~D

21

PD13

RB751V-40_SOD323~D

1.5V_BST2

12

PC71

5

D1

G1

6

S1

D1

7

G2

D2

8

D2

S2

PR79

0_0402_5%~D

PD36

0.1U_0805_50V7M~D
PR68

0_0603_5%~D

1 2

12

2 1

RB751V-40_SOD323~D

12/12 New VCCP powergood solution

12

PC175

1000P_0402_50V7K~D

1.5V_V+ 1.05V_BST

PR66
0_0603_5%~D

1.5V_BST

12

1.5V_DH

1.5V_LX

1.5V_DL

1.5V_OUT

1.5V_FB

MAX1845_VCC

PR65

20_0603_1%~D

12

PC68

1U_0603_10V6K~D

PU5

4

V+

19

BST2

18

DH2

17

LX2

16

CS2

20

DL2

15

OUT2

14

FB2

7

PGOOD

11

ON1

12

ON2

6

SKIP

8

OVP

9

UVP

+5VSUS

1 2

MAX1845_VCC

22

VCC

GND

23

+1.5VSUSP
OCP: (((Ilim2 / 10) /Low-side MOSFET Rdson) +0.5* IL)
Ilimit3=REF(80.6K/80.6K+100K)=0.8925 V
Low side MOSFET Rdson: 22.75m ohms at 100C
iL=((Vin-Vo) / L)*Ton=((19.5-1.5) / 5u )* ((1/255K) * 1.5/19.5))=1.23 A
OCP TYP: 4.462A

PC66

1 2

4.7U_0805_6.3V6K~D

21

25

VDD

BST1

26

DH1

27

LX1

28

CS1

24

DL1

1

OUT1

2

FB1

10

REF

5

TON

3

ILIM1

13

ILIM2

MAX1845EEI_QSOP28~D

1.05V_DH

PC70

1U_0603_6.3V6M~D

PR67
0_0603_5%~D

1 2

1.05V_LX

1.05V_DL

1.05V_OUT

1.05V_FB

MAX1845_REF

1

PR64

2

1 2

@ 0_0402_5%~D

21

PD28

RB751V-40_SOD323~D

12

PC72

0.1U_0805_50V7M~D

12

12

PR69

1 2

0_0603_5%~D

12

PR62

150K_0402_1%~D

12

PR63

90.9K_0402_1%~D

1.05V_BST2

PR70

100K_0402_1%~D

PR71

80.6K_0402_1%~D

+VCCP_1P05VP
OCP: (((Ilim1 / 10) /Low-side MOSFET Rdson) +0.5* IL)
Ilimit3=REF(90.9K/90.9K+150K)=0.754V
Low side MOSFET Rdson: FDS6676SS=0.01125 at 100C
iL=((Vin-Vo) / L)*Ton=((19.5-1.05) / 1.5u )* ((1/345K) * 1.05/19.5))=1.92 A
OCP TYP: 7.66 A

1.5V_VCCP_PWR_SRC

578

PQ7
IRF7811AV_SO8~D

3 6

241

578

PQ9
FDS6676S_SO8~D

3 6

241

12

12

PC62

PC63

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PL13

1.5uH_SIL104-1R5_10A_30%~D

1 2

1

1

PC64

PC61

2

2

10U_1206_25V6M

10U_1206_25V6M

Design current 5A for +VCCP_1P05VPPeak current 4.034A for +1.5VSUSP

Peak current 7.124A for +VCCP_1P05VP

12

PR72

1K_0402_1%~D

12

PR75

20K_0402_1%~D

PJP22

PAD-OPEN 4x4m

12

PC75

0.1U_0805_25V7K~D

PWR_SRC

12

1

+

PC74

2

330U_D2E_2.5VM_R9~D

Change PC74 to ESR= 9m ohms

+VCCP_1P05VP

PD31

2 1

@ RB751V-40_SOD323~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

Title

+1.5VSUSP /+VCCP_1P05VP

Size Document Number Rev

Board Number LA2111

Date: Sheet of

D

47 61Monday, February 09, 2004

0.3

5

4

3

2

1

+1.8VSUSP/ +0.9V_DDR_VTT

Reserve Jump for EMI test

D D

PWR_SRC

Update design current to 10.6A -0128/04

Design current 10.6A for +1.8V_SUSP

+1.8VSUSP

C C

1

+

PC185

2

330U_D2E_2.5VM~D

B B

PC186

1

2

330U_D2E_2.5VM~D

PJP26

1.8V_0.9V_PWR_SRC

1 2

PAD-OPEN 4x4m

0130/2004-Modify by Joseph.

12

+

PC188

0.1U_0805_25V7K~D

12

PR240

27.4K_0603_1%~D

12

PR243

17.4K_0402_1%~D

1

2

PC177

10U_1206_25V6M

1.4UH_CEP125-1R4_15.5A_20%~D

1 2

1

2

PC178

10U_1206_25V6M

PL24

12

12

PC179

PC180

0.1U_0805_25V7K~D

PR247

PC197

2200P_0603_50V7K~D

578

PQ47

12

PQ48

@ 4.7_1206_5%~D

12

@ 1000P_0603_50V7K~D

IRF7821_SO8~D

3 6

241

578

FDS7788_SO8~D

3 6

241

0202/04-Modify by Joseph

21

PD38

RB751V-40_SOD323~D

PC183

0.1U_0805_50V7M~D

0.22U_0603_10V7M~D

12

12

PC193

0128/04-Modify by Joseph for updated OCP.
0202/04-Modify by Joseph

PR238

0_0603_5%~D

1.8V_DH

1.8V_LX

1.8V_DL

1.8V_FB

PR241

@ 0_0402_5%~D

1.8V_REF

PR242

1 2

100K_0402_1%~D

1 2

12

12

DDR2 Termination

+5VSUS

PC181

1 2

4.7U_0805_6.3V6K~D

PU14

20

BST

18

DH

19

LX

21

DL

23

PGND1

16

VOUT

15

FB

1

TON

3

REF

PR244

48.7K_0402_1%~D

+3VSUS

PR235

1 2

10_0603_5%~D

1.8_VDD

PC182

1 2

1U_0603_6.3V6M~D

17

VIN

AVDD

5

POK1

6

POK2

27

SHDNA

7

STBY

13

VTTI

14

REFIN

11

PGND2

12

VTT

9

VTTS

10

VTTR

SS

MAX8550ETI_TQFN28~D

1.8V_0.9V_PWR_SRC

12

PC187

0.1U_0603_25V7K~D

PC195

1 2

1U_0603_6.3V6M~D

22

2

VDD

ILIM

4

25

26

28

SHDNB

OVP/ UVP

SKIP

GND

8

24

PC194

1 2

1000P_0402_50V7K~D

PR236

100K_0402_5%~D

PR246

20_1206_5%

PR237

1 2

1 2

100K_0402_5%~D

SUSPWROK_1P8V <<47>>

SUSPWROK_5V <<46>>

12

+1.8VSUSP

12

PC189

0.1U_0805_25V7K~D

Install jumper on PJP30 pad.

+0.9V_PWRGD RUN_ON <<18,28,36,41,42,45,46>>

PC184

10U_1206_6.3V7K~D

1

2

PC190

22U_1206_6.3VAM~D

PJP30

AGND GND

2 1

PAD-OPEN 2x2m~D

12

1

1

2

2

PC191

PC192

PC198

22U_1206_6.3VAM~D

22U_1206_6.3VAM~D

V_DDR_MCH_REF <<10,16,17>>

2N7002_SOT23~D

PJP31

2 1

PAD-OPEN 2x2m~D

PJP32

2 1

PAD-OPEN 2x2m~D

1

2

@ 22U_1206_6.3VAM~D

+5VSUS

PR239

1 2

100K_0402_5%~D

13

D

PQ49

2

G

S

+1.8VSUSP

+1.5VSUS

+0.9V_DDR_VTTP

Change from 22uF to 10uF for cost down.

0202/04-Modify by Joseph
0205/04- Reserve PC198. Modify by Joseph

0202/04-Modify by Joseph
Install jumper on PJP32 pad and depop PJP31
0207/2004

PJP27

PAD-OPEN 4x4m

1 2

PJP28

PAD-OPEN 4x4m

+1.8VSUSP

+0.9V_DDR_VTTP

A A

1 2

PJP29

1 2

PAD-OPEN 4x4m

5

+1.8VSUS

(10A,320mils ,Via NO.=20)

+0.9V_DDR_VTT

(2A,200mils ,Via NO.=4)

+1.8VSUSP
OCP: (((Ilim / 10) /Low-side MOSFET Rdson) +0.5* IL)
Ilimit=REF(53.6K/53.6K+100K)=0.6979 V
Low side MOSFET Rdson:6.5m ohms at 100C
iL=((Vin-Vo) / L)*Ton=((19.5-1.8) / 1.4u )* ((1/450K) * 1.8/19.5))=2.59A
OCP TYP: 11.37A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Title

+1.8VSUSP/ +0.9V_DDR_VT

Size Document Number Rev

Board Number LA2111

2

Date: Sheet of

1

48 61Monday, February 09, 2004

0.1

8

H H

VID 50VID 4

0

10
1

G G

F F

E E

Change from 47p to 270p -1212

D D

C C

DPRSLPVR<<22>>

CLK_ENABLE#<<6>>

CLK_ENABLE#<<6>>

B B

Change PR125:30.1k. Delete PR129/PQ21/PQ40/PQ20/PQ41/PR124/PR205/PR203
and PR201 for BANIAS and DOTHAN

PR129/PQ21/PQ40/PQ20/PQ41/PR124/PR205/PR203 and PR201 are only for YONAH CPU.

A A

TRANSITION TIMING:
(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us
(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/us
(c): EXIT SUSPEND (SUS=LOW, RUNPWROK=HIGH): 24.7mV/us

V I D

VID 2

VID 3

1

11101

1

1

1

H_PSI#<<8>>

H_STP_CPU#<<6,22>>

1

PC123

2

PC124

270P_0402_50V7K~D

@ 100K_0402_5%~D

PR205

@ 0_0402_5%~D

PR206

@ 0_0402_5%~D

@ 100K_0402_5%~D

8

1 2

1 2

+3VRUN

+3VRUN

0

1

1

1

VCCP_PWRGD<<47>>

0.22U_0603_10V7M~D

PR129

12

12

PR203

Vcore

VID 0

VID 1

0

1.484

1.308

1

1

1

0.956

0.748

0

00

PR105

IMVP_PWRGD<<10,22,42>>
CLK_ENABLE#<<6>>

PR114

0_0402_5%~D

DPRSLPVR<<22>>

RUNPWROK<<18,37,42,47>>

MAX1987_REF

12

12

PR120

100K_0402_1%~D

12

12

PC129

PR122

20.5K_0402_1%~D

100P_0402_50V8K~D

2

G

13

D

PQ21

2

G

@ 2N7002_SOT23~D

S

13

D

PQ41

2

G

@ BSS138_SOT23~D

S

V

+3VRUN

12

PR107

10K_0402_5%~D

1.91K_0603_1%~D

VID5<<8>>
VID4<<8>>
VID3<<8>>
VID2<<8>>
VID1<<8>>
VID0<<8>>

PR202

@ 0_0402_5%~D

12
12
12

12

PR124

@ 15K_0402_1%~D

13

D

PQ20
@ 2N7002_SOT23~D

S

2

G

7

12

12

PR106

10K_0402_5%~D

VID5
VID4
VID3
VID2
VID1
VID0

MAX1987_S2
MAX1987_S1
MAX1987_S0

PBOOT_B2
PBOOT_B1
PBOOT_B0

MAX1987_PSI#

12

MAX1987_DPSLP#

PR116
0_0402_5%~D
PR117
0_0402_5%~D

12

PR201

@ 36K_0402_5%

13

D

PQ40
@ 2N7002_SOT23~D

S

7

PR125

+5VRUN

PR104

10_0805_5%~D

PC106

1U_0603_6.3V6M~D

30.9K_0402_1%~D

12

12

MAX1987_VCC

1

2

PU7

22

SYSOK

23

IMVPOK

24

CLKEN#

25

D5

26

D4

27

D3

28

D2

29

D1

30

D0

8

S2

7

S1

6

S0

5

B2

4

B1

3

B0

21

PSI#

44

DPSLP#

43

SUS

9

SHDN#

14

CCV

10

REF

11

ILIM

2

TON

1

TIME

+5VRUN

12

36

VCC

VDD

V+

BSTM

DHM
LXM
DLM

CMP
CMN

CSP
CSN

OAIN+

OAIN-

CCI

FB

DHS

LXS

DLS

BSTS

PGND

GND

DD0#

POS15NEG

MAX1987ETM_TQFN48~D

16

12

PR123

1.24K_0402_1%~D

Change PR123 from 2.47K to 1.24K

12

Deeper Mode (C3) offset -1.2%

PR130

100K_0402_1%~D

MAX1987_S0

MAX1987_S1

MAX1987_S2

6

12

PC105

10U_1206_6.3V7K~D

CPU_PWR_SRC

42

MAX1987_BSTM

32
34

MAX1987_LXM

33

MAX1987_DLM

35

MAX1987_CMP

45

+VCC_CORE

46

MAX1987_CSP

48

+VCC_CORE

47

MAX1987_OAIN+

20

MAX1987_OAIN-

19

470P_0402_50V7K~D

17

MAX1987_FB

18

39

MAX1987_LXS

40

MAX1987_DLS

38

MAX1987_BSTS

41

37
13
31

MAX1987_FB

MAX1987_PSI#

PR222

@ 0_0402_5%~D

12

PR135

0_0402_5%~D

12

PR137

0_0402_5%~D

12

PR223

@ 0_0402_5%~D

12

PR139

@ 0_0402_5%~D

12

PR224

@ 0_0402_5%~D

12

6

21

PD16

RB751V-40_SOD323~D

MAX1987_BSTMB

PR108

0_0603_5%~D

1 2

1 2

PC117

1 2

PR118

1M_0402_1%~D

1 2

PR214

0_0603_5%~D

1 2

PR204

@ 0_0402_5%~D

PR143

10K_0402_5%~D

PSI need pull high

MAX1987_VCC

MAX1987_VCC

PR213

0_0603_5%~D

MAX1987_DHM

PR110

1 2

3.01K_0402_1%

MAX1987_DHS

12

PR121

0_0603_5%~D

MAX1987_BSTSB

MAX1987_DPSLP#MAX1987_PSI#

12

12

MAX1987_REF

12

Remote Vcore sense

PR127

3.01K_0402_1%

PC125

0.1U_0805_50V7M~D

PD19

RB751V-40_SOD323~D

MAX1987_VCC

The C4 Mode voltage is 0.748V, S2 open

MAX1987_VCC

PC112

12

12

2 1

+5VRUN

0.1U_0805_50V7M~D

PR111

1K_0402_1%~D

1 2

PR112

1K_0402_1%~D

1 2

PR113

1K_0402_1%~D

1 2

PR115

1K_0402_1%~D

1 2

MAX1987_OAIN-

5

+VCC_CORE

MAX1987_CSP

MAX1987_CMP

+VCC_CORE

+VCC_CORE

PR134

@ 0_0402_5%~D

12

PR136

@ 0_0402_5%~D

12

PR138

0_0402_5%~D

12

5

IRF7811AV_SO8~D

MAX1987_DHM

MAX1987_LXM

SI4362DY_SO8~D

MAX1987_DLM

IRF7811AV_SO8~D

MAX1987_DHS

MAX1987_LXS

SI4362DY_SO8~D

MAX1987_DLS

12

PR131

0_0402_5%~D

12

PR140

@ 0_0402_5%~D

578

PQ14

578

PQ15

PQ17

PQ18

MAX1987_VCC

12

PR132

0_0402_5%~D

12

PR141

@ 0_0402_5%~D

4

3

Reserve Jump for EMI test

PWR_SRC

PC107

12

12

PC108

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PD17

2 1

@ EC31QS04~D

12

PC119

PC118

0.1U_0805_50V7M~D

PD18

2 1

@ EC31QS04~D

PC110

0.36U_ETQP4LR36WFC_24A_20%~D

12

2200P_0402_50V7K~D

3

578

PQ42

MAX1987_DHM

3 6

241

3 6

241

578

MAX1987_DHS

3 6

241

578

3 6

241

12

PR133

@ 0_0402_5%~D

PBOOT_B0

PBOOT_B1

PBOOT_B2

12

PBOOT voltage seeting up on 1.212V

PR142

@ 0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

@ IRF7811AV_SO8~D

3 6

241

578

PQ16
SI4362DY_SO8~D

3 6

241

578

PQ43
@ IRF7811AV_SO8~D

3 6

241

578

PQ19
SI4362DY_SO8~D

3 6

241

4

PAD-OPEN 4x4m

PAD-OPEN 4x4m

1

1

PC109

PC111

2

2

10U_1210_25V7K

10U_1210_25V7K

PL18

1 2

DCR=1.1 m ohms

1

1

PC121

PC122

2

2

10U_1210_25V7K

10U_1210_25V7K

PL19

0.36U_ETQP4LR36WFC_24A_20%~D

1 2

PJP24

PJP25

1

2

@ 10U_1210_25V7K

1

PC120

2

@ 10U_1210_25V7K

2

12

12

1

1

+

+

PC171

PC170

2

2

@ 15U_D2_25M_R90~D

@ 15U_D2_25M_R90~D

PR109

0.001_2512_5%~D

1 2

MAX1987_CMP

CPU_PWR_SRC

CPU_PWR_SRC

Reserve PC170 PC171 PC172 PC173 for audio noise issue

+VCC_CORE

+VCC_CORE

PC115

Output Capatitors 330uF_9m ohms place H/W, spec ESR=3m ohms

CPU_PWR_SRC

1

1

+

+

PC173

PC172

2

2

@ 15U_D2_25M_R90~D

@ 15U_D2_25M_R90~D

PR119

0.001_2512_5%~D

1 2

MAX1987_CSP

+VCC_CORE

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Board Number LA2111

Date: Sheet of

2

+VCC_CORE

12

PC128

0.01U_0603_50V7K~D

+VCORE

1

12

0.01U_0603_50V7K~D

49 61Monday, February 09, 2004

1

0.3

5

4

3

2

1

PR144

PR145

0_0402_5%~D

PC133

@ 0.1U_0603_25V7M~D

31
27

1
3

32

6
7
8

11

4
19
12
13

16
30
17

0.01_2512_1%~D

1 2

1 2

CSSP

2

1

PU8

PDS
SRC
DCIN
ACIN
ACOK
CCS
CCI
CCV
DAC
REF
BATT
VDD
THM

INT
PDL
I.C.

29

5

CSSP

GND

CSSN

28

CSSN

GND18IMAX

PR160

182K_0402_1%~D

PR146

PC134

DHIV

DLOV

PGND

CSIP
CSIN

VMAX

10

1 2

D D

C C

12

12

PR152

0_0402_5%~D

PR153

0_0402_5%~D

12

12

PC151

PC150

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

Connect GND side of PC150, PC151, PC152 to GND through 1 via.

B B

+DC_IN

12

PC131

10U_1210_25V7K~D

PC132

PR147

365K_0402_1%~D

1 2

PR149

49.9K_0402_1%~D

12

PC142

0.01U_0402_25V7K~D

1 2

ACAV_IN<<37,44,51>>

MAX1535_CCS
MAX1535_CCI
MAX1535_CCV

+VCHGR

1 2

13

D

S

TM

PR195

10K_0402_1%~D

1 2

TH

PR194

1 2

10K_0402_1%~D

MAX1535_DAC
CHVREF

12

PD29

+5VALW

PC155

1 2

1U_0805_10V7K~D

PQ39

2N7002_SOT23~D

1

2

G

1 2

100K_0402_5%~D

PR193

59K_0402_1%~D

PR196

PR154

10K_0402_5%~D

12

12

12

PC154

PC153

PC152

0.1U_0603_25V7K~D

1000P_0402_50V7K~D

1U_0805_10V7K~D

RB715F_SOT323

CHG_SBATT<<37,51>>
CHG_PBATT<<37,51>>

2
3

1 2

1U_0805_25V4Z~D

PC166

1500P_0402_50V7K~D

PR209

0_0402_5%~D

1 2

1 2

Adress : 12H

+SDC_IN CHAGER_SRC

0_0402_5%~D

change PR221 and PR148 by Dell request

1 2

1 2

@ 0.1U_0603_25V7M~D

PC140

1U_0805_25V4Z~D

25

2

LDO

PR212

0_0805_5%~D

DLOV

24

26

DHI

23

DLO

22

21
20

15

SCL

14

SDA

9

MAX1535A_QFN32~D

PR159

280K_0402_1%~D

FBM-L11-453215-900LMAT_1812~D

PR148

PR221

10K_0402_1%~D

1 2

1 2

16.2K_0402_1%~D

12

1U_0603_10V6K~D

PR150

33_0402_5%~D

1 2

12

DLO

CSIP
CSIN

PBAT_SMBCLK <<37,45>>
PBAT_SMBDAT <<37,45>>

CHVREF

12

VMAX=2.625V
Maximum charger voltage=13.12V

IMAX=1.6135V
Maximum charger current=8A

PL23

1 2

ACAV_IN <<37,44,51>>

SI4835DY_SO8~D

PC141

1 2

PC143

0.1U_0603_25V7K~D

12

PR157

102K_0402_1%

PR158

1 2

182K_0402_1%~D

Add PD37, PR234 to fix MAX1535A Charger issue when battery undervoltage
is defected. Will waiting MAX1535B and delete those -0108

+5VSUS

21

PD37

1SS355_SOD323~D

+VCHGR

12

PC149

10U_1210_25V7K~D

PR234

1 2

100K_0402_1%~D

PR151

1 2

PR156

12

PC136

PC137

2200P_0402_50V7K~D

36

36

241

PQ22

578

MAX1535_LX

578

PQ23

CHVREF

12

FDS6670S_SO8~D

3 6

241

PC167

1 2

@ 1000P_0402_50V7K~D

241

PQ44
SI4835DY_SO8~D

PD21

@ EC31QS04~D

578

PL20

5.6U_CEP125-5R6MC_8.8A_20%~D

2 1

PR155

0_0402_5%~D

1 2

1 2

PC156

PC164

@ 0.1U_0603_25V7K~D

@ 0.1U_0603_25V7K~D

0.01_2512_1%~D

CHG_CS

12

0_0402_5%~D

1 2

1 2

0.1U_0805_50V7M~D

PC145

1 2

0.1U_0805_50V7M~D

12

PC138

PC139

10U_1210_25V7K~D

12

1 2

PC146

10U_1210_25V7K~D

12

12

PC165

10U_1210_25V7K~D

10U_1210_25V7K~D

12

12

PC148

PC147

10U_1210_25V7K~D

10U_1210_25V7K~D

Maximum Battery Charge current = 6.2A
when system off

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Charger

Board Number LA2111

50 61Monday, February 09, 2004

1

0.1

5

4

3

2

1

+DC_IN discharge path

D D

PQ38

D2

S2

G2

D2

S1

D1
D1

G1

FDS4935_SO8~D

12

0.1U_0603_25V7K~D

100K_0402_5%~D

12

PQ32

4

CHG_SBAT

1

CHG_SBATT_N

2
3
4

PR166

100K_0402_5%~D

12

PC160

0.1U_0603_25V7K~D

1 2

CHG_SBATT_N

PC161

1 2

PR169

12

CHG_PBAT

36
2
1

CHG_PBATT_N

3 6
2
1

8
7

+VCHGR

CHG_SBAT_N

13

D

PQ28

CHG_SBATT<<37,50>>

C C

CHG_PBATT<<37,50>>

2

G

G

2

+VCHGR

2N7002_SOT23~D

S

S

PQ29
2N7002_SOT23~D

D

1 3

CHG_PBAT_N

6
5

PR165

10K_0402_5%~D

PR168

10K_0402_5%~D

SI4835DY_SO8~D

5
7

8

ACAV_IN<<37,44,50>>

PQ33

4

SI4835DY_SO8~D

@ 100K_0402_5%~D

SBATT+

PBATT+

5
7

8

+SDC_IN

2

PR164

G

12

PQ30

SI4835DY_SO8~D

1
2
3 6

4

13

D

PQ25
2N7002_SOT23~D

S

8
7

5

PR161

10K_0402_5%~D

2

G

2
3

1 2
13

D

PQ26
2N7002_SOT23~D

S

PD24

RB715F_SOT323

@ 15MQ040N_SMA~D

SI4835DY_SO8~D

8
7

5

PR162

10K_0402_5%~D

2 1

SI4835DY_SO8~D

8
7

5

SBAT_G

1

B540C~D

2 1

SI4835DY_SO8~D

8
7

5

PD22

2 1

PQ24

12

PD23

B540C~D

PQ27

4

PR167

1 2

33K_0402_5%~D

PD25

PQ31

4

1
2
36

4

PR163

100K_0402_5%~D

1
2
36

1
2
36

PWR_SRC

12

PC159

PC158

12

1 2

0.1U_0805_50V7M~D

2200P_0402_50V7K~D

PWR_SRC

PR172

12

47K_0402_1%~D

470K_0402_5%~D

PU10A
LM393M_SO8

P

O

G

1

PR176

470K_0402_5%~D

1 2

2

G

12

PR173

10K_0402_5%~D

12

13

D

PQ34
2N7002_SOT23~D

S

PR171

PR170

470K_0402_5%~D

B B

SBATT+

PR177

147K_0402_1%~D

1 2

PBATT+

PC162

1 2

+3VALW

@ 0.1U_0603_25V7K~D

PU11

5

TC7SH32FU_SSOP5~D

2

A A

SBAT_LOW<<37>>
SBAT_PRES#<<37,45>>

5

P

I0

4

O

1

I1

G

3

2N7002_SOT23~D

PQ35

13

D

2

G

S

PR179

1 2

42.2K_0402_1%~D
PR180

10K_0402_5%~D

1 2

1 2

PR181

100K_0402_5%~D

PR182

1 2

32.4K_0402_1%~D

5
6

+3VALW

4

8

+

-

4

P

O

G

PU10B
LM393M_SO8

PC163

7

1 2

0.1U_0603_25V7K~D

1

PD27

2
3

RB715F_SOT323

PR175

47K_0402_1%~D

1 2

PR178

100K_0402_5%~D

1 2

+3VALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

PBATT+

8

3

+

2

-

4

3

PD26

2
3

RB715F_SOT323

2

PBAT_G

1

PR174

1 2

33K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Selector

Board Number LA2111

51 61Monday, February 09, 2004

1

0.3

A

1 1

B

C

D

E

F

G

H

Pin Name Pin No. Settings
SATATEST0
SATATEST1
SATATEST2

SATATEST3 SATATEST4

00
0

*

1
11

1
0

25MHz
30MHz
40MHz

20MHz

SATATEST3
SATATEST4
SATATEST5
SATATEST6
SATATEST7

CFG0
CFG1
CFG2

+3VRUN

R1145

2 2

3 3

4 4

10K_0402_5%~D@

1 2

R1149

4.7K_0402_5%~D

1 2

R1173
100_0402_5%~D@

1 2

R1174
10K_0402_5%~D

1 2

R1187
10K_0402_5%~D@

1 2

510_0402_5%~D@

IDE_HDREQ

IDE_HINTRQ

ATAIOSEL

IDE_HIORDY

UAI

IDE_HIOCS16#

IDE_HDD7

+5VHDD

R1178

1 2

1 2

HDD Connector

IDE_HRESET#
IDE_HDD7 IDE_HDD8
IDE_HDD6
IDE_HDD5
IDE_HDD4 IDE_HDD11
IDE_HDD3 IDE_HDD12
IDE_HDD2 IDE_HDD13
IDE_HDD1 IDE_HDD14
IDE_HDD0 IDE_HDD15

IDE_HDREQ
IDE_HDIOW#

12

IDE_HDIOR#
IDE_HIORDY
IDE_HDMACK#
IDE_HINTRQ
IDE_HDA1
IDE_HDA0 IDE_HDA2
IDE_HCS0#

+5VHDD

R1208

5.6K_0402_5%~D

R1209
10K_0402_5%~D

JP1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

SGND

49

SGND

B1

50

SGND

B2

SGND

FOX_HH99227-S9~D

+5VHDD

2

2

C637

C632

IDE_HDD9
IDE_HDD10

SEC_CSEL

IDE_HCS1#

45
46
47
48

1

0.1U_0402_16V4Z~D

1

0.1U_0402_16V4Z~D

R1153
470_0402_5%~D

1 2

12

+5VHDD

R1197

R1207

33_0402_5%~D

1 2

12

PAD~D
PAD~D

R1155

10K_0402_5%~D

IDE_HRESET# IDE_R_HRESET#

10K_0402_5%~D

12

R1179

10K_0402_5%~D@

C1262

33P_0402_50V8J~D

T378
T379

1

2

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

IDE_HDA0
IDE_HDA1
IDE_HDA2
IDE_HCS0#
IDE_HCS1#

IDE_HIOCS16#
IDE_HINTRQ
IDE_HDMACK#
IDE_HIORDY
IDE_HDIOR#
IDE_HDIOW#
IDE_HDREQ

1 2

1M_0402_5%~D

PU / PD is internal pull-up or pull-down 100Kohm

U175

62

HDD0

64

HDD1

2

HDD2

5

HDD3

7

HDD4

11

HDD5

13

HDD6

15

HDD7

14

HDD8

12

HDD9

10

HDD10

6

HDD11

3

HDD12

1

HDD13

63

HDD14

61

HDD15

50

HDA0

51

HDA1

49

HDA2

48

HCS0#

47
52

53
54
55
58
59
60
16
46

45

UAI

43

X9
25MHZ_20PF_1BG25000CK1A~D

XTLOUTXTLIN

1 2

R1156

Parallel ATA

HCS1#
HIOCS16#

HINTRQ
HDMACK#
HIORDY
HDIOR#
HDIOW#
HDMARQ
HRESET#
HPDIAG#

UART

UAO
UAI

88SA8040_TQFP64~D

1

33P_0402_50V8J~D

2

C1263

Int. PU/PD
33
34
35
36
37
38
39
40
20
19

PD
PU
PD
PD
PD
PU
PD
PD
PD
PU

18 PD

SATA

TX_M
RX_P
RX_M

CNFG2
CNFG1
CNFG0

ATAIOSEL

XTLIN/OSC

XTLOUT

Config & Debug

VDDIO_0
VDDIO_1

VDD_0
VDD_1
VDD_2

Power

GND_0
GND_1
GND_2

TX_P

RST#

ISET

VAA1
VAA2

VSS1
VSS2

NC
NC
NC
1

0

*

00

NC
0
NC
NC
NC
0

1
1
11
0
111

NC

SATA_RXP0

32

SATA_RXN0

31

SATA_TXP0

27

SATA_TXN0

28

PLTRST_SATA#

17

SATATEST0

33

T0

SATATEST1

34

T1

SATATEST2

35

T2

SATATEST3

36

T3

SATATEST4

37

T4

SATATEST5

38

T5

SATATEST6

39

T6

SATATEST7

40

T7

20
19
18
21

22
23

26
4
44
9
41
56
24
29

25
30
8
42
57

CNFG2
CNFG1
CNFG0
ATAIOSEL

XTLIN
XTLOUT

12.1K_0603_1%~D

R1154

VAA

12

1 2

SATA_RXP0 <<21>>
SATA_RXN0 <<21>>
SATA_TXP0 <<21>>
SATA_TXN0 <<21>>

PLTRST_SATA# <<20>>

PAD~D

T334

PAD~D

T335

PAD~D

T336

PAD~D

T337

PAD~D

T338

PAD~D

T339

PAD~D

T340

PAD~D

T341

PAD~D

T376

PAD~D

T377

L169
BLM31A260SPT_1206~D

VAA

1

2

C1273

4.7U_0805_10V4Z~D

00

1
00
0

+1.8VRUN+3VRUN

1

2

C1274

0.1U_0402_16V4Z~D

CNFG0CNFG2 CNFG1

NOTE
Device Mode 100MB/s

1

Device Mode 133MB/s
Device Mode 150MB/s

00

Host Mode 100MB/s

1

Host Mode 133MB/s

0

Host Mode 150MB/s

11

Reserved
Reserved

CNFG1

+3VRUN

+3VRUN +1.8VRUN

1

1

2

2

C1276

0.1U_0402_16V4Z~D

C1275

1

2

4.7U_0805_10V4Z~D

1 2

1 2

1 2

1 2

1 2

1 2

C1277

0.1U_0402_16V4Z~D

12

R1170
10K_0402_5%~D@

R1175
10K_0402_5%~D@

R1169
10K_0402_5%~D

R1196
10K_0402_5%~D

R1176
10K_0402_5%~D@

R1177
10K_0402_5%~D

C1278

4.7U_0805_10V4Z~D

R1151

1

2

10K_0402_5%~D

SATATEST0

SATATEST2

SATATEST3

SATATEST6

SATATEST1

SATATEST5

1

1

2

2

C1280

C1279

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Sets maximum transfer rate and UDMA mode

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

E

F

Title

SATA Bridge

Size Document Number Rev

Board Number LA2111

Date: Sheet of

G

52 61Monday, February 09, 2004

H

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

1

2

3

4

5

6

7

8

C C

9

10

11

12

13

14

20 H/W 12/10 Bill VGA and LOM PLTRST# delay. U25 Pin1 & Pin2 net name change to "PLTRST_DELAY#"

22 H/W 12/10 Bill VGA and LOM PLTRST# delay. U59 Pin AD21 add net name "PLTRST_DELAY#"

29 H/W 12/10 Bill LOM isolation LRESET and PERST. U164 Pin.M9 change net name to "PLTRST#".

32 M/E 12/11 Bill Cardbus connector change. Cardbus connector change to FOXCONN QT600806-7121.

39 H/W 12/11 CS Populate Q9 Needed for full guardian.

10,22,42 H/W 12/11 CS

42

42

42

42

42

9

33

Title

H/W

H/W

H/W

H/W

H/W

H/W

H/W

12/11

12/11

12/11

12/11

12/11

12/11

12/11

Owner

Bill12/10H/W13 Power drop issue.

Delete R22 and connect IMVP_PWRGD directly
to MCH and ICH

CS

CS

CS

CS

CS

CS

Delete R1228
Change U12 pin 10 to 1.5VSUS_PWRGD.

Eliminate the need for U42D.
Delete R753, C922, U67, R21, and C921

Change R1229 voltage to +3VALW
Delete R1190, C1281, R1188, Q124, R1189,

Q123, and R1195.

Add a No-Pop 0-ohm resistor connecting pin

L43, L146 and L147 material change from BLM11A601S to
BLM21PG600SN1D(3000mA).

Resistor not needed.

Not used.

Simplifying the SUSPWROK logic, and this gate can be removed.

Not used.
This will eliminate the glitch at the output of 1.5VSUS_PWRGD (U21 pin

5).
We are now using SUSPWROK_1P8V signal to enable the 1.5V rail.

Delete C944Remove C944 capacitor at +VCC_CORE.

Add R1231CS
3 of Q114 to Pin 3 of Q115. This is for
future testing of the SMBUS to the LOM
without the isolation. There is a push on
the Dell side to remove this Isolation.

Solution Description Rev.Page#

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Request

B B

15

33

H/W

CS12/11

Add a No-Pop 0-ohm resistor connecting pin

Add R1232

0.2
3 of Q116 to Pin 3 of Q117. This is for
future testing of the SMBUS to the LOM
without the isolation. There is a push on
the Dell side to remove this Isolation.

16

17

18

13

H/W

12/11

GF

21 H/W 12/11 GF

No stuff C287 and C1265. Change C1264
to 10uf

Can we delete some 0-ohm ser. Resistors on
CPU interface?

Add a NO POP 0-Ohm resistor between pin 1

Modify OK.

Modify OK.

Add R1233CS12/11H/W19

0.2

0.2

0.2
and pin 8 of L57 for a ground connection
when L57 is removed.

19

A A

20

M/E38 12/12 Bill Change JPLAM cconnector. Change Pin define and connector library.

M/E40 12/12 Bill Change JLED1 and JSW1 cconnector. Change Pin define and connector library.

0.2

0.2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 1/5

Size Document Number Rev

Board Number LA2111

Date: Sheet of

53 61Monday, February 09, 2004

1

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

21

22

H/W19 12/12 Bill

H/W42 12/12 Bill Delete R1132, R1131, R1130, Q122, Q121,

Owner

Remove Q125, Q126, U176, U177, R1222 and
R1223 for Docking connector shift-up 1mm.

C1254, and U174 and use VCCP_PWRGD

Layout space issue, delete that component and add R1234, R1235, R1236
and R1237 for isolation int. GFX.

Using new MAX1845 solution with Diode between PGOOD and ON1 for VCCP
Powergood.

generated by MAX1845.

H/W36 12/12 CS

Add a No Pop 100K-ohm pulldown resistor to
VAUX_EN signal for potential SMSC floating

Add R123823

pins on power down. Nimitz team
reccomended this pulldown for safety.

H/W36 12/12 CS

Add a o-ohm resistor in parallel with R228
connected to +3.3VX.

Add R123924

H/W36 12/12 CS No pop R22825 No Pop R228. Change Macallan VCC0 voltage

from +RTC_CELL to +3.3VX per D'05
reccomendation.. CMOS settings are now
stored in ICH6, thus the RTC rail doesn't

C C

26

27

40 M/E 12/15 Bill M/E request change JLED1 connector. Connector change to MOLEX_53398-0690.

28

29

30

31

32

B B

7

19

39 H/W 12/17

33

H/W 12/15 CS Change R1160 to 54.9 ohms per Intel.7

H/W

H/W

12/15

12/16

12/17M/E43

CS / GFGFChange R17 to 200 ohms per Intel.

CS

Bill

need to power this signal.

Change R1082 pullup voltage to +3.3VXCS12/12H/W37 Modify it.

R971-978 should be 0603 package. PN12/15H/W30

Change from 0402 package to 0603 package.

Change from 220 Ohm to 54.9 Ohm.

Change from 330 Ohm to 220 Ohm.

Move D4, D5, D6 back to +3vrun
Invert ICH_PWRGD signal with a 7002 FET

and a 100K pullup to +3VSUS. Name the

Modify done

Modify done

signal ICH_PWRGD# and connect it to pin 1
of R47.

Add 2 screw on HDD side Add H27, H28

Solution Description Rev.Page# Title

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Request

34

35

36

37

38

33 H/W 12/17 CS No Pop Q114 and Q116. Following Azeda and using only one level of isolation for SMBUS.

28 M/E 12/17 Bill Change BT connector. Change Pin define, to be change to 9 pin connector.

RUN_ENABLE singal reserve voltage issue. Add R1242 no pop.Bill12/18H/W41

28 H/W 12/18 Bill Swap JBT pin define. For layout route easy, change pin define.

20 H/W 12/18 CS U164 pin M9 PLTRST# signal should be

Add U179, R1243

0.2

0.2

0.2

0.2

0.2
bufferred here for sufficient signal drive
strength.

A A

39

20 H/W 12/18 CS Regulatory team has reported damage to

Q43 change to DTC144EKA_SOT23

0.2
FETs in the Dock area, want to ensure
proper rating of near 3KV.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2/5

Size Document Number Rev

Board Number LA2111

Date: Sheet of

54 61Monday, February 09, 2004

1

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

41

39 H/W 12/19 Bill

42 37 H/W 12/21 CS

H/W38 12/18 Bill Remove BIOS debug connector. For layout space issue, delete it. 0.240

Owner

Delete R1241 and signal "+3V_PWROK#" same
as Tobago, Sullivan, Azeda

No Pop R1202 and R1203, Populate R1198,
R1199, R1200, and R1201

Modify Done

Modify Done

H/W 12/21 Bill3743 Change Board ID R286 no stuff, R287 stuff.

44 12/21

45

46

47

C C

48 13 H/W 12/24 Bill Add +VCCP_CRT and +1.5VRUN_TV. For layout easy control.

38 M/E

31 M/E

29 H/W

12/21 Bill

Bill

PN12/24 Change to 1210 Size

37 H/W 12/24 CS

Change JPLAM connector to Molex_53398-1290. For M/E request, change it.

Change JP5 connector to Molex_53398-0990. For M/E request, change Samrt-Card connector.
Dell LOM team requests to make notation

0.5W capacity on R1051
U27 GPIO20 is actually an open drain

signal, so CHG_SBATT should be pulled high.

Add Pop resister R1244, non-pop R759.

49 26 H/W 12/24 Bill Change Audio jack location. Audio jack from JP8 change to JAUDO, JAUDIOD change to JMIC

50 19 H/W 12/24 Bill JVGA connector footprint error. Footprint change, change pin 16, 17 to NC, Pin 17, 18 to GND.

51 43 M/E 12/24 Bill Add screw H24 For M/E request add H24.

52 27 H/W 12/24 Bill Change USBP7 pair for layout issue. Exchange USBP7+/USBP7- and USBP7_D+/USBP7_D-.

53 52 M/E 12/24 Bill Change HDD connector. Change HDD same Nimiz.

54 29/22 H/W 12/24 Bill Change net name for PCIE pair. Add net name singal easy control for PCIE.

Solution Description Rev.Page# Title

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Request

55 35 H/W 12/25 Bill R616 add @. Same as LBK.

B B

56 6/10/12

13/19

H/W 12/29 Bill Int. GFX disable. No stuff R1071, R1072R1133, R1134, R1135, R1136, R1137, R1138, R1139,

R1140, R1141, R1142, R1210, L8, C201, C207, C245, R1234, R1235, R1236,

0.2

0.2

R1237. Stuff R1211, R1212, R1213, R1214.

57 13 H/W 12/29 Bill Change Inductor Change L6, L9, L29, L7 from BLM11A601S to BLM18PG181SN1.

58

13 H/W 01/02 GF Change Inductor Change L43, L146, L147 from BLM21PG600SN1D to BLM18PG181SN1.

59 37 H/W 01/02 Bill Change Board ID R279, R286 no stuff, R278, R287 stuff.

60 43 EMI 01/02 Bill Add EMI Clip Add EMI Clip 7 pcs.

61 13 H/W 01/02 Bill Change R1212 pin 2 to GND. Follow Intel check list, change VCC_SYNC to GND for int. GFX disable.

62 37 H/W 01/05 PN Change R1121 pu-high to +3VRUN Modify.

A A

63 10 H/W 01/06 GF

Remove R1213 and connect DREFCLK directly
to +1.5vrun

Modify.

0.2

0.3

0.3

0.3

0.3

0.3

0.3

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 3/5

Size Document Number Rev

Board Number LA2111

Date: Sheet of

55 61Monday, February 09, 2004

1

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

65

6 H/W

66 12 H/W Remove R1071, R1072, R1118, R1119

68

12 Remove R1064, R1065, R1066. Connect

H/W10 01/06 GF

01/06

01/06

H/W1267 Remove R1133, R1134, R1135

01/06

01/06H/W

Owner

GF

GF

GF

GF

Remove R1214 and connect DREFCLK# directly
to GND

Remove R178 and connect DREF_SSCLKP
directly to +1.5vrun

Modify.64

Modify.

Modify.

Modify.

Modify.
TV_YR, TV_CVBS_R, TV_C_R directly to
ground

69

70

C C

71

72

73 12 H/W

74 12 Remove R1067, R1068, R1069

75 13 H/W Remove L164-L168, C1229-C1240.

76 Connect Alviso pins F17, E17, D18,C18,

12 H/W

12 H/W Remove R1136-R1140.

12 H/W

12 H/W Remove R1063, connect directly to +vccp.

H/W 01/06

13

H/W 01/06

01/06

01/06

01/06

01/06

GF

GF01/06

GF

GF

GF

GF

GF

GF

Remove R1062.Connect pin J18 directly
to gnd.

Connect Alviso pins blue/blue#, red/red#,
green/green# directly to +vccp

Remove R1141, R1142. Connect these pins
directly to gnd.

Modify.

Modify.

Modify.01/06

Modify.

Modify.

Modify.

Modify.

Modify.
F18, E18, H18, D19, H17 directly to gnd.
(VCCA_TVDAC A,B,C and VCCA_TVBG)

Solution Description Rev.Page# Title

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

Request

77

B B

78

79

80

81

82

83

84

A A

85

13

13

13 H/W Remove R1192, R1191, D80, D79 0.3

42

42

42

42

42

42

H/W Remove R1210. Connect directly to gnd.

H/W

H/W

H/W

H/W

01/06

01/06

01/06

01/06

01/06

01/06

GF

GF

GF

CS

CS

CS

Remove L8, C201, C207, C245. Connect
pins E19 and F19 directly to +VCCP

Delete R24

Delete All 4 instances of U42
Add a single 5-pin AND gate to replace

U42A.(Or an unused AND gate if nearby)
Connect RESET_OUT# to the second input
pin.

H/W

H/W

H/W

01/06

01/06

01/06

CS

CS

CS

Delete R23

Delete R1225 and R1227

Connect RUN_ON to pin 2 of U12.

Modify.

Modify.

Modify.

Modify.

Modify.

Modify.

Modify.

Modify.

Modify.

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 4/5

Size Document Number Rev

Board Number LA2111

Date: Sheet of

56 61Monday, February 09, 2004

1

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

87

27 H/W

H/W41 01/06 CS Delete R1194 Modify.86

01/06 CS

Owner

Populate 0-Ohm Resistors or USB filters
instead of the Inductors (No POP L21, L41

Modify.
L22, L23, L28, L13, L129, and L131

Populate R348 - 359 ad R890, R891, R950,
and R951) Please do this for M01 board
build and for X00 Schematic

88 27

01/06H/W Modify.

CS

Remove L59, L62, L61, and L128 and
replace all with 0-Ohm resistors for M01
Build and for X00 Schematic

89

90

C C

91

91

92

93

7 H/W 01/09 Steven Del T332, T333 from schematic.

10 H/W 01/09 Steven Del T380, T381, T300, T6 from schematic.

11 H/W 01/09 Steven Del T2, T3, T4, T5 from schematic.

19 H/W 01/09 Steven Del T375 from schematic.

21 H/W 01/09 Steven Del T155 from schematic.

28 H/W 01/09 Steven Del T280 from schematic.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.
Del T255, T259, T342, T344, T345, T346,

94

36 H/W 01/09 Steven

T347, T348, T349, T350, T351, T352, T353,
T354, T355, T356, T357, T358, T359, T360,
T361, T362, T363, T364 from schematic.

Del T366, T367, T368, T370, T372, T373,

95

B B

37 H/W 01/09 Steven

T257, T258, T343, T365, T369, T374 from
schematic.

Delete R1198, R1199, R1200, R1201, R1202,

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

We add test point for SST2 now. So we remove the test point symbol.

That will avoid test point double layered.

R1203 and connect directly. Macallan III

96

rev A IMCLK/IMDAT pair did not work
properly. MacIII RevB has solved this

Modify.37 H/W 01/09 CS
issue.

Solution Description Rev.Page# Title

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

Request

97 12 H/W 01/09 GF Remove R1215 from schematic. Modify.

0.3

Remove L29, C47, C8, Connect DPLLA directly

98 13 H/W 01/09 GF

to +1.5vrun
Remove L6, C48, C51, Connect DPLLB directly

Modify.

0.3

to +1.5vrun

99 13 H/W 01/09 GF Change C811 to the same component as C812. Modify.

100 13 H/W 01/09 GF No stuff C783 to support ext. vga. Modify.

A A

0.3

0.3

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 5/5

Size Document Number Rev

Board Number LA2111

Date: Sheet of

57 61Monday, February 09, 2004

1

0.3

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

101 18 H/W 01/09 CS

102 18 H/W 01/12 CF

103 7 H/W 01/13 CF

Owner

Add an 15U 25V De-pop capacitor C1290 in
G_PWR_SRC for improve this power plane
stablility

Add a no stuff cap. for add a CPU bulk
decoupling pads back to layout.

Remove C450, C452 non-use item for saving
Layout space

Modify.

Modify. 0.3

Modify. 0.3

104 43 H/W 01/17 CF Delete H23 from M/B. Modify. 0.3

105 16, 17 H/W 01/19 Bill DDR termination swap. For layout routing easy, swap pin define. 0.3

106 6 H/W 01/27 GF Change BOM to support Dothan 533Mhz No stuff R65, pop. R66. 0.3

107 29 H/W 01/27 PN Change C1111 from 10uF to 22uF (1206) Modify. 0.3

C C

108 8 H/W 01/27 GF Short PJP16 and open PJP17 for X00 build. Modify. 0.3

109 29 H/W 01/27 PN

110 32 H/W 01/28 GF

Populate R1180 to allow activating TPM
mode.

changing C1201, C1202 to be the same as
0402 package as C1203 to save board space.

Modify. 0.3

Modify. 0.3

111 10 H/W 01/28 GF Intel recommends pop C745 with 0.1uf cap. Modify. 0.3

112 36 H/W 01/28 CS Populate R1238 for eliminate glitch.. Modify. 0.3

113 15 H/W 01/29 CS

114 29 H/W 01/29 PN

115 29 H/W 01/30 PN

B B

116 29 H/W 01/30 PN L149, C1209 nopop. Modify. 0.3

C479 and C495 change to 47UF like Nimitz
for cost savings.

V_2P5_LAN needs bigger bulk caps, add 2
more 22uF caps C1291, C1292

L155 replaced by 0 ohm resistor (R1245,
0Ohm 0603), C1215 and C1135 nopop.

Modify. 0.3

Modify. 0.3

Modify. 0.3

Solution Description Rev.Page# Title

0.3

Request

117 40 H/W 02/02 CS no pop R454 Modify. 0.3

118 40 H/W 02/02 CS

Change U52 from the discontinued TFDU6101E
to the new TFDU6102.

0.3Modify.

Add a no pop 33-ohm resistor (R1246) to
PLTRST_LOM# and connect to PCIRSTB2# for
pop option.

Modify.119 20 H/W 02/02 CS 0.3

Add a no pop 33-ohm resistor (R1247) to

120 20 H/W Modify.02/02 CS 0.3

PLTRST_VGA# and connect to PCIRSTB2# for
pop option.

121 41 H/W 02/02 CS Q55 change to DI4810.-02/02 Modify. 0.3

122 Removed F14 connect from L151 Pin 1CS02/02H/W29 0.3Modify.

A A

123 Change R1230 from 330 to 1K42 H/W 02/02 CS 0.3Modify.

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2/2

Size Document Number Rev

Board Number LA2111

Date: Sheet of

58 61Monday, February 09, 2004

1

0.1

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

124 43 H/W 02/02

125 16 H/W 02/02 CS

126 16 H/W 02/02 GF

127 17 H/W 02/02 GF

Owner

CS Modify. 0.3

Change H6 to H_O463X408D433X378
Change H10 to H_O148X128D118X98

change C1047, C1049 to 0603 size for avoid
highlimit issue in DIMM region.

Change C1048, C1046, C1045 and C1168
voltage rating to 6.3V for saving cost.

Change C143, C153, C1042-C1044 and C1177
voltage rating for save cost

Modify. 0.3

Modify. 0.3

Modify. 0.3

128 43 H/W 02/03 Steven Add 3 EMI clip. Modify. 0.3

129 29 H/W 02/04 PN

130 21 H/W 02/04 GF

Pop R1102. Depop R1103, R1104

Populate R1248

Modify. 0.3

Modify. 0.3
Add a 0 ohm series termination R1251

131 20 H/W 02/04 CS Modify. 0.3

C C

between the ICH and U25A. This way we
can go back to the origional M00 design

132 29 H/W 02/04 PN L149 and C1209 and connect U164 pin F14. Modify. 0.3

Move SATA clock pair to SRC4 pair on

133 6 H/W 02/04 CS

134 21 H/W 02/04 CS

135 21 H/W 02/04 CS

CK410. and connect PCIE_VGA clock to SRC3,
PCIE_LOM clock to SRC1

Follow Issue list 1648 to remove the note
of R940.

Follow Issue list 1646 to remove the note
of R1248.

Modify. 0.3

Modify. 0.3

Modify. 0.3

136 20 H/W 02/05 GF Add a pop resister R1252 Modify. 0.3

H/W21137 Steven02/05 Currect the Note of R940 and R1248. Modify. 0.3

SWAP RN118, RN117, RN6, RN130, RN121, RN1,

H/W138 20,22,28 02/05 Steven

B B

139 43 H/W 02/06 ME

140 41 H/W 02/06 CS

141 35 H/W 02/07 CS

RN120, RN131, C13, C14 pin connect for
layout routing.

Modify H1, H2, H3, H4, H12, H20 as ME
request

Change R605 to 100K for proper voltage
level during low battery charge state.

Add D76 in Q43 DOCKED for potection ESD
damage.

Modify. 0.3

Modify. 0.3

Modify. 0.3

Modify.

142 41 H/W 02/07 CS Change Q55 to DI4800 for cost saving. Modify. 0.3

143 Modify.

Steven02/07H/W41 0.3

Add a no-pop Q131 3456 parallel with Q55
for this build.

144 02/07 Steven Remove a no use EMI clip CLP3 Modify.43 H/W 0.3

Solution Description Rev.Page# Title

0.3

Request

145 30 02/07 Steven Change RJ1 connector from 5PIN to 2PIN. Modify.H/W 0.3

A A

Modify.Change smart card connector as ME request.ME02/07146 H/W41 0.3

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Changed-List History 2/2

Size Document Number Rev

Board Number LA2111

Date: Sheet of

59 61Monday, February 09, 2004

1

0.1

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Request

TitleItem Issue DescriptionDate

1

D D

2

3

P47

P48

P47

4

5

6

7

C C

P47

P49 Dell

8

9

10

11

P45 12/16/2003 Compal Change to Power materials Change C1288 to PC176, R1224 to PR233.

P47 Deleted because PR105 had existed.

P50

12

13

14

15

B B

16

17

18

19

20

P46

P47

P48

P48

P48

P48

P44

P45

21

22

23

A A

P48

P48

+1.5VSUSP / +VCCP_1P05VP

+1.8VSUSP/ +0.9V_DDR_VTT

+1.5VSUSP / +VCCP_1P05VP

+1.5VSUSP / +VCCP_1P05VP

+1.5VSUSP / +VCCP_1P05VP

+1.5VSUSP / +VCCP_1P05VP

+VCORE

+1.5VSUSP / +VCCP_1P05VP

Battery Conn./+2.5V

+1.5VSUSP / +VCCP_1P05VP

Charger

+1.8VSUSP/ +0.9V_DDR_VTT

+3.3V/+5V/+15V

+1.5VSUSP / +VCCP_1P05VP

+1.8VSUSP/ +0.9V_DDR_VTT

+1.8VSUSP/ +0.9V_DDR_VTT

+1.8VSUSP/ +0.9V_DDR_VTT

+1.8VSUSP/ +0.9V_DDR_VTT

+DCIN

Battery Conn./+2.5V

Charger

+1.8VSUSP/ +0.9V_DDR_VTT

+1.8VSUSP/ +0.9V_DDR_VTT

12/09/2003 0.1Dell PL12 choke had height limitation on secondary side Change PL12 from CDRH125 4.4uH_5A to SIL1035 5uH_5.5A

12/09/2003 Compal

12/12/2003 Dell

12/12/2003 DellP47

12/12/2003

12/12/2003

12/12/2003

12/12/2003

01/08/2004 Dell

01/27/2004

01/28/2004

02/02/2004

02/02/2004

02/02/2004

02/02/2004

02/05/2004

02/05/2004

02/05/2004

02/05/2004

02/06/2004

02/07/2004

Owner

Change SC1486 to SC1486A for DDR2 (REFIN
threshold voltage change from 0.8V to 0.5V)

Add a diode between the PU5 PGOOD signal and ON1 signal,
so that when ON1 is low, PGOOD is low. And when ON1 is high,
PGOOD is released and can go high.

Change PR232 pull-up voltage to +3VSUS.

DellP47

DellP47

Dell

Dell X01Adding +15V current limit Add PC196 PR245 and Change PC38

Dell Change PC74 ESR from SER 15m to 9 m ohms. Change PC74 from 330u_15m to 330u_9m. X01

Dell Adding PJP31, PJP32 Jump, +1.8VSUS or 1.5VRUN

Dell Modify +1.8VSUS Regulator OCP Change PR244 from 53.6K to 48.7K. X01

Dell Modify Bypass capacitor Power supply for DL Gate driver

Dell Reserve PC198 for the future cost down. Add @ PC198. X01

Dell Change PR219 to 2.2Kohms per AC Adapter group reccomendation. Change PR219 from 1.5K to 2.2K ohms. X01

Dell Change PR233 to achieve proper 1ms powerup delay. Change PR233 from 10k to 27kohms. X01

Dell Add note to +VCHGR rail - "Maximum Battery Charge current = 6.2A P50

Compal Change 1.8V Regulator switch frequence from 450k to 300kHz depopulate PR241 X01

Dell Install jumper on PJP32 pad to connect to 1.5VSUS PopPJP32 pad and depop PJP31. X01

Change MAX1845_PWRGD signal name to VCCP_PWRGD

Depopulate PD30 and PD31Dell

Change PC123 from 47pF to 270pF

Change SUSPWROK_1.5V signal to SUSPWROK_1P8V. To match other D'05 platforms, this change will also reduce the

Delete PR232, not neededDell12/18/2003

Add PD37, PR234 to fix MAX1535A Charger issue when battery
undervoltage is defected. Will waiting MAX1535B
and delete it.

input voltage for VTTI of Max8550

of MAX8550

when system off"

Change PU6 from SC1486 to SC1486A version

This is a new VCCP powergood solution. Changing to match Azeda.

Change PR232 pull-up voltage from +5VSUS to +3VSUS.

Implementing new powergood solution for VCCP.

Don't use for cost down

Improve noise immunity with a reduction in the transient response speed.

amount of logic gates for power sequencing circuitry.

Add PD37, PR234 X00

Delete SC1486A regulator and adding MAX8550
Regulator for DDR2 power source.

Adding PJP31, PJP32 Jump. X01

Change PC181 from 1uF to 4.7uF. X01

Add note to Charger circuit X01

Solution Description Rev.Page#

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

X01P48 Implement MAX8550 regulator

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Power-Changed-List History

Size Document Number Rev

Board Number LA2111

Date: Sheet of

60 61Monday, February 09, 2004

1

0.1

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Request

TitleItem Issue DescriptionDate

D D

24

25

C C

P47

P50

+1.5VSUSP / +VCCP_1P05VP

Charger

02/09/2004 X01Compal

Owner

Compal02/09/2004

Bypass power derating

Change PC68 from 1uF_6.3v to 1uF_10vBypass power derating

Change PC141 from 1uF_6.3v to 1uF_10v

Solution Description Rev.Page#

X01

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Power-Changed-List History

Size Document Number Rev

Board Number LA2111

Date: Sheet of

61 61Monday, February 09, 2004

1

0.1