Compal LA-2101 Schematic
A
1 1
B
C
D
E
SAPPORO 150A+G
2 2
LA-2101 REV0.1 Schematic
3 3
Portability Prescott/Northwood
RC300ML(RX300ML)+IXP150+ATI M11P/M10C(128MB VRAM)
2003-11-10
4 4
Compal Electronics, Inc.
Title
Cover Page
Size Document Number Rev
B
152Tuesday, November 18, 2003
A
B
C
D
Date: Sheet
E
of
0.1
A
B
C
D
E
DAL01 LA-2101 BLOCK DIAGRAM
4 4
Northwood-MT
Prescott-MT
(uFCBGA/uFCPGA-478)
LCD Conn 1
page 23
CRT & TV-OUT Conn.
W/EXT VGA CHIP
3 3
LCD Conn 2
page 23
page 23
ATI-M11P/M10C
page 17,18,19,20
W/INT VGA
533MHz(0.8V)
AGP 8X BUS
FSB
ATI-RC300ML
(ATI-RX300ML)
VGA M9 Embeded
868 pin u-BGA
VGA DDR x2 CHB
page 22 page 21
Mini PCI
RJ-45
PAGE 28
2 2
1 1
Port 1
PAGE 32
Slot 0
PAGE 30
SD Co nn
PAGE 30
CB PWR SW
ENE CP2211
PAGE 30
LAN
RTL8100C
IEEE1394
TSB43AB21A
CARDBUS
ENE 712/1410
VGA DDR x2 CHA
PAGE 31
PAGE 28
PAGE 32
PAGE 29
33MHz (3.3V)
Super I/O
LPC47N217
REV B
PCI BUS
PAGE 36
LPC BUS 33MHz (3.3V)
266MHz(3.3V)
A-Link
ATI-SB150
BGA 457 pin
Embedded
Controller
NS PC87591L
PAGE 4,5,6
533MHz
PAGE 7,8,9,10,11,12
PAGE 24,25,26,27
PAGE 39
Thermal Sensor
266/333MHz
(2.5V)
Memory Bus
480MHz(5V)
Primary
ATA-100 (5V)
Secondary
ATA-100 (5V)
AC-LINK
24.576MHz
ADM1032
PAGE 5
USB 2.0 P ort *3
0, 2, 4
AC97 CODEC
Clock Gener a tor
ICS951402AGT
SO-DIMM x 2(DDR)
BANK 0,1,2,3
PAGE 37
IDE HDD
IDE ODD
ALC 250
MDC
Connecto r
PAGE 35
PAGE 35
PAGE 33
PAGE 38
PAGE16
PAGE 13,14,15
CPU VID
PAGE 5
Audio Amp lifier
TPA0232
PAGE 34
Programming Clock Gen
FANController
RTC Ba t t e ry
DC/DC Inte rfac e
PAGE 36
PAGE 42
PAGE 24
PAGE 43
LID/Kill Switch
Power Buttom
DCIN&DETECTOR
BATT CONN/OTP
CHARGER
3V/5V/12V
DDR_2.5V/1.25V, 1.8 V
1.5V/VGA_CORE
CPU_CORE
Direct Board (LS - 1911)
Connecto r
VR/CIR Board (LS - 1913)
Connecto r
TP Board (LS-2101)
Connecto r
PAGE 41
PAGE 44
PAGE 45
PAGE 46
PAGE 47
PAGE 48
PAGE 48
PAGE 50,51,52
PAGE 40
PAGE 40
PAGE 40
FIR
PAGE 37
A
Parallel
PAGE 38
B
Scan K B
PAGE 39
BIOS(1M)
& I/O PORT
PAGE 40
Compal Electronics, Inc.
Title
Block Digram
Size Document Number Rev
Custom
C
D
Date: Sheet
252Tuesday, November 18, 2003
E
0.1
of
A
B
C
D
E
Voltage Rails
STATE
Power Plane Descripti on
1 1
2 2
VIN
B+
+CPU_CORE
+CPUVID
+VGA_CORE ON OFF OFF1.0V/1.2V switched power rail for VGA chip
+1.25VS 1.25V switched power rail
+1.5VS
+1.8VS 1.8VS switched power rail OFFOFFON
+2.5VALW 2.5V always on power rail ON*ONON
+2.5V
+3VALW
+3V
+3VS
+5V
+5VS
+12VALW
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power ci rcuit.
Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
AGP 4X/8X
2.5V power rail
2.5V switched power rail+2.5VS
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V power rail ON
5V switched power rail
12V always on power r ail
RTC power
S1 S3 S5
ON
ON ONONON
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON ON
ON
ON
ON
ON
ON+5VALW
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON*ON
OFF
OFF
ON*
OFF
OFF
ON*
ON
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
SIGNAL
SLP_S3# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH
LOW
LOW
LOW LOW
AD_BID
0 V
HIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
0 V 0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
ON ON
ON
OFF
OFF
OFF
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
max
External PCI Devices
Device IDSEL# REQ# / G NT # Interrupts
VGA
CardBus
LAN
Mini-PCI
1394
3 3
SD
AD16
AD20
AD19
AD18
AD16 0
AD20
2
3 PIRQD
1/4
2
PIRQA
PIRQA
PIRQC/PIRQD
PIRQA
PIRQB
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
EC SM Bus1 address
Device
Smart Batte r y
EEPROM(24C16/0 2)
(24C04)
4 4
IXP150 SM Bus address
Device
Clock Generator
(ICS951402AGT)
DDR DIMM0
DDR DIMM2
Address Address
1010 000X b
1011 000Xb
Address
1101 001Xb
1010 000Xb
1010 001Xb
A
EC SM Bus2 address
Device
ADM1032
ICS960011
B
1001 110X b0001 011X b
1101 110X b
Compal Electronics, Inc.
Title
Size Document Number Rev
B
C
D
Date: Sheet
LA-2101
Notes
0.1
of
352Tuesday, November 18, 2003
E
5
JCPU1A
H_A#[3..31]7
D D
H_REQ#[0..4]7
C C
+CPU_CORE
+CPU_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number CommendCommend
Northwood
Pin name
FERR#B6
AA20
ITPCLKOUT0
ITPCLKOUT1AB22
A A
AD20 Connect to CPU
AF23
H_REQ#[0..4]
H_ADS#7
R67 51_0402_5%
1 2
1 2
R87 51_0402_5%
H_BR0#7
H_BPRI#7
H_BNR#7
H_LOCK#7
CLK_BCLK16
CLK_BCLK#16
H_HIT#7
H_HITM#7
H_DEFER#7
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND BOOTSELECTVSSAD1 CPU determine
Connect to GNDVSSAE26 float
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
H_IERR#
CLK_BCLK
CLK_BCLK#
FOX_PZ47803-274A-42_Prescott
Prescott
Pin name
FERR#/PBE#
TESTHI6Pull-up56ohm
TESTHI7Pull-up 56ohm
VIDPWRGDNCAD2
VID5floatNCAD3
VCCIOPLLVCCA
VCCAVCCIOPLL Connect to CPU
OPTIMIZED/
COMPAT#
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
AF22
BCLK0
AF23
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
Pull-up 62ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Pull-up 8.2Kohm
to +VCCVID
Pull-up1Kohm to
+3VRUN & connect
to PWRIC
Connect to +VCCVIDVCCVIDLBfloatNCAF3
Filter
Filter
CON
TROL
4
A10
A12
A14
A16
A18
A20A8AA10
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
HOST
ADDR
CONTROL
CLK
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
H1H4H23
H26
A11
A13
4
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
A15
A17
A19
A21
A24
A26A3A9
AA1
PrescottNorthwood
Depop Pop
Depop
Depop
3
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
C10
C12
C14
C16
C18
C20C8D11
D13
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
POWER
Northwood-MT
Prescott-MT
GND POWER
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
F13
F15
F17
R42
0_0402_5%
R_C
VCC_80
F19
F9
12
1 2
R45
0_0402_5%
Pop: Northwood
Depop: Prescott
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
BOOTSELECT
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
AD1
AD18
AD21
AD23
AD4
AD8
PopPop
D15
D17
VCC_68
VCC_69
VCC_78
VCC_79
E20E8F11
D19D7D9
E10
VCC_73
VCC_70
VCC_71
VCC_72
HOST
ADDR
VCC_74
VCC_75
VCC_76
VCC_77
E12
E14
E16
E18
H_BOOTSELECT 50
2
+CPU_CORE
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
+CPU_CORE
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_D#[0..63] 7
1
PopPop
PopPop
Pop
Pop
DepopPop
DepopPop
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
2
Title
Prescott Processor in uFCPGA478 (1/2)
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
452Saturday, November 22, 2003
1
0.1
5
4
3
2
1
AF26
F25
F5
VSS_125
VSS_126
VSS_127
VSS_128
SKTOCC#
REF
OPTIMIZED/COMPAT#
ITP
DATA
ADDR
DATA
MISC
VCCVID
AF4
Trace >= 25mils
1
C35
0.1U_0402_10V6K
2
H_VID_PWRGD
H_SKTOCC#
DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
+CPUVID
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
RE
Pop: Prescott
Depop: Northwood
@680_0603_5%
1 2
R126
@0_0402_5%
1 2
+CPU_GTLREF
H_TESTHI0
H_TESTHI1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_GHI#
H_DPSLPR#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_PROCHOT#
R_E
R76
H_GHI#
R80 0_0402_5%
Place decoupling cap 220PF near CPU.
C76
1 2
220P_0402_50V7K
R_G
R127 0_0402_5%
1 2
R123 56_0402_5%
1 2
R59 56_0402_5%
1 2
R111 56_0402_5%
1 2
R79 56_0402_5%
1 2
R73 56_0402_5%
1 2
R58 56_0402_5%
1 2
R89 300_0402_5%
1 2
R124 56_0402_5%
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
R62130_0402_5%
12
H_SLP# 24
+CPUVID
1 2
Pop: Northwood
Depop: Prescott
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_ADSTB#0 7
H_ADSTB#1 7
+CPU_CORE
H_PROCHOT# 45
CPU_GHI# 25
+CPU_CORE
+CPU_CORE
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26B4B8
C11
C13
C15
C17
C19C2C22
C25C5C7C9D10
D12
D14
D16
D18
D20
D21
D24D3D6D8E1
E11
E13
E15
E17
E19
E23
E26E4E7E9F10
F12
F14
F16
JCPU1B
+CPUVID
CLK_ITP
CLK_ITP#
H_TRDY#7
H_A20M#24
H_IGNNE#24
H_SMI#24
H_PWRGOOD24
H_STPCLK#24
H_INTR24
H_NMI24
H_INIT#24
H_RESET#7
H_THERMTRIP#6
H_VCCA
H_VSSA
H_FERR#24
H_DBSY#7
H_DRDY#7
H_RS#[0..2]
BSEL012,16
BSEL112,16
1 2
R70
51.1_0603_1%
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PWRGOOD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TMS
ITP_TRST#
VCCVIDLB
@0_0402_5%
CLK_ITP
CLK_ITP#
COMP0
COMP1
R44
R112
51.1_0603_1%
1 2
1 2
FOX_PZ47803-274A-42_Prescott
AB23
AB25
AD20
AE23
AD22
AC26
AD26
G5
AB2
W5
AD6
AD5
AC6
AB5
AC4
AA5
AB4
AF3
L24
F1
F4
J6
C6
B6
B2
B5
Y4
D1
E5
H5
H2
B3
C4
A2
Y6
D4
C1
D5
F7
E6
A5
A4
P1
RS#0
RS#1
RS#2
RSP#
TRDY#
CON
TROL
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LEGACY
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
VSS_57
VSS_58
ITP
CLK
VSS_129
VSS_130
F8
G21
VSS_59
VSS_60
VSS_61
MISC
THER
MAL
MISC
ITP
MISC
VSS_131
VSS_132
VSS_133
G24G3G6J2J22
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
GROUND
Northwood-MT
Prescott-MT
GROUND MISC
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VID0
AE5
J25J5K21
K24K3K6L1L23
L26L4M2
M22
M25M5N21
N24N3N6P2P22
P25P5R1
R23
R26R4T21
T24T3T6U2U22
U25U5V1
V23
V26V4W21
W24W3W6Y2Y22
H_VID050
H_VID150
H_VID250
H_VID350
H_VID450
H_VID550
Y25
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
AE4
Y5
H_THERMTRIP#
1 2
R61 56_0402_5%
H_PWRGOOD
1 2
D D
R119 300_0402_5%
H_RESET#
1 2
R120 51_0402_5%
H_RS#[0..2]7
Place near CPU
JTAG PULL DOWN
RP4
1K_8P4R_1206_5%
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI
1 8
2 7
3 6
4 5
Close to the CPU
+CPU_CORE
R82 51_0402_5%
1 2
R78 51_0402_5%
1 2
R75 51_0402_5%
1 2
R81 51_0402_5%
1 2
R77 51_0402_5%
1 2
R74 51_0402_5%
VCCSENSE50
VSSSENSE50
C80
Trace >= 25mils
+
33U_D2_8M_R35
Pop: Prescott
Depop: Northwood
1 2
Note: Please change to 10uH, DC current
C C
B B
of 100mA parts and close to cap
+CPU_CORE
L5 LQG21F4R7N00_0805
1 2
L6 LQG21F4R7N00_0805
1 2
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
R571 @100K_0402_0.5%
R570 @100K_0402_0.5%
1 2
1 2
1 2
F18F2F22
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VIDPWRGD
VID5
VID1
VID2
VID3
VID4
AE3
AE2
AE1
AD2
AD3
VID PWRGD Circuit
Thermal Sensor
H_THERMDA
1
C45
2200P_0402_50V7K
A A
EC_SMB_CK236,39
EC_SMB_DA236,39
2
H_THERMDC
5
U4
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
+3VS
1
C47
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
12
R93
@10K_0402_5%
1
6
4
5
C736
0.1U_0402_16V4Z
H_VID_PWRGD
SN74LVC125APWLE_TSSOP14
+3V POWER
4
U44A
+3V
1
2
1
P
OE#
IO
G
12
R627
10K_0402_5%
1 2
R628 0_0402_5%
14
23
7
VID_PWRGD 50
VCORE_ENLL 50
GTL Reference Voltage
Layout note :
1. Place R_A and R_B near CPU (Within 1.5").
2. +CPU_GTLREF Trace wide 12mils(min),Space 15mils
+CPU_CORE
12
R109
49.9_0603_1%
R_A
12
R110
R_B
100_0603_1%
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
3
+CPU_GTLREF
1
C69
1U_0603_10V4Z
2
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
+3VS
12
R135
4.7K_0402_5%
R134
2
PM_STPCPU#24,50
1 2
4.7K_0402_5%
2
H_DPSLPR#
1
Q6
2
3
MMBT3904_SOT23
1
Q5
3
MMBT3904_SOT23
Title
Size Document Number Rev
C
Date: Sheet
VID PULL HIGH
H_VID5
1 2
R57 1K_0402_5%
H_VID4
1 2
R47 1K_0402_5%
RP3
H_VID3
H_VID2
H_VID1
H_VID0
1K_8P4R_1206_5%
Compal Electronics, Inc.
Prescott Processor in uFCPGA478 (2/2)
LA-2101
1
+3VS
45
36
27
18
552Saturday, November 22, 2003
0.1
of
5
4
3
2
1
+CPU_CORE
1
C549
D D
C C
22U_1206_10V4Z
2
+CPU_CORE
1
C595
22U_1206_10V4Z
2
+CPU_CORE
1
C56
22U_1206_10V4Z
2
+CPU_CORE
1
C17
22U_1206_10V4Z
2
1
C567
22U_1206_10V4Z
2
1
C618
22U_1206_10V4Z
2
1
C68
22U_1206_10V4Z
2
1
C16
22U_1206_10V4Z
2
1
C585
22U_1206_10V4Z
2
1
C643
22U_1206_10V4Z
2
1
C15
22U_1206_10V4Z
2
Place 11 North of Socket(Stuff 8)
1
C606
22U_1206_10V4Z
2
1
C624
22U_1206_10V4Z
2
1
C641
22U_1206_10V4Z
2
Place 12 Inside Socket(Stuff all)
1
C655
22U_1206_10V4Z
2
1
C597
22U_1206_10V4Z
2
1
C617
22U_1206_10V4Z
2
Place 9 South of Socket(Unstuff all)
1
C14
22U_1206_10V4Z
2
1
C22
22U_1206_10V4Z
2
1
C21
22U_1206_10V4Z
2
1
C18
22U_1206_10V4Z
2
1
C642
22U_1206_10V4Z
2
1
C20
22U_1206_10V4Z
2
1
C507
22U_1206_10V4Z
2
1
C654
22U_1206_10V4Z
2
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239
Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32
1
C518
22U_1206_10V4Z
2
22uF depop reference
Springdale Customer Schematic R1.2 page82
1
C57
22U_1206_10V4Z
2
1
C525
22U_1206_10V4Z
2
1
C50
22U_1206_10V4Z
2
1
C542
22U_1206_10V4Z
2
+CPU_CORE
B B
1
+
C119
470U_D2_2.5VM
2
+CPU_CORE
1
+
C53
470U_D2_2.5VM
2
+CPU_CORE
A A
1
+
C62
470U_D2_2.5VM
2
1
+
C100
470U_D2_2.5VM
2
1
+
C9
470U_D2_2.5VM
2
1
+
C37
470U_D2_2.5VM
2
5
470uF _ERS10m ohm* 15, ESR=0.5m ohm
1
+
C96
470U_D2_2.5VM
2
1
+
C79
@470U_D2_2.5VM
2
**
1
+
C29
470U_D2_2.5VM
2
1
+
C30
@470U_D2_2.5VM
2
1
+
C43
470U_D2_2.5VM
2
4
1
+
C71
470U_D2_2.5VM
2
1
+
C51
470U_D2_2.5VM
2
1
+
C64
470U_D2_2.5VM
2
MAINPWON44,45,47
1
Q30
2
MMBT3904_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
3
12
C491
MMBT3904_SOT23
0.1U_0402_16V4Z
2
+CPU_CORE
12
R485
470_0402_5%
R60
330_0402_5%
1
Q39
2
1 2
3
Title
Size Document Number Rev
Custom
Date: Sheet of
H_THERMTRIP#
*01
CPU Decoupli n g
LA-2101
H_THERMTRIP# 5
1
652Saturday, November 22, 2003
0.1
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
D D
H_ADSTB#05
C C
H_ADSTB#15
H_ADS#4
H_BNR#4
H_BPRI#4
H_DEFER#4
H_DRDY#5
H_DBSY#5
H_BR0#4
H_LOCK#4
H_RESET#5
H_RS#25
NB_SUS_STAT#25
NB_RST#17,24
NB_PWRGD9,27
1 2
1 2
L13
1 2
H_RS#15
H_RS#05
H_TRDY#5
H_HIT#4
H_HITM#4
1U_0603_10V4Z
0.1U_0402_10V6K
C724
12
R613
1 2
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+CPU_CORE
PLACE CLOSE TO U27 Ball
1 2
12
1
2
W28, USE 20/20
WIDTH/SPACE
C378
1U_0603_10V4Z
1
2
C363 CLOSE
TO Ball W28
C339
220P_0402_50V7K
B B
R292
49.9_0402_1%
R303
100_0402_1%
330_0402_5%
+CPU_CORE
+1.8VS
R308 24.9_0402_1%
R309 49.9_0402_1%
HB-1M2012-121JT03_0805
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
NB_SUS_STAT#
COMP_N
COMP_P
CPVDD
C282
CPVSS
1 2
NB_GTLREF
12
R232
4.7K_0402_5%
U46A
M28
CPU_A3#
P25
CPU_A4#
M25
CPU_A5#
N29
CPU_A6#
N30
CPU_A7#
M26
CPU_A8#
N28
CPU_A9#
P29
CPU_A10#
P26
CPU_A11#
R29
CPU_A12#
P30
CPU_A13#
P28
CPU_A14#
N26
CPU_A15#
N27
CPU_A16#
M29
CPU_REQ0#
N25
CPU_REQ1#
R26
CPU_REQ2#
L28
CPU_REQ3#
L29
CPU_REQ4#
R27
CPU_ADSTB0#
U30
CPU_A17#
T30
CPU_A18#
R28
CPU_A19#
R25
CPU_A20#
U25
CPU_A21#
T28
CPU_A22#
V29
CPU_A23#
T26
CPU_A24#
U29
CPU_A25#
U26
CPU_A26#
V26
CPU_A27#
T25
CPU_A28#
V25
CPU_A29#
U27
CPU_A30#
U28
CPU_A31#
T29
CPU_ADSTB1#
L27
CPU_ADS#
K25
CPU_BNR#
H26
CPU_BPRI#
J27
CPU_DEFER#
L26
CPU_DRDY#
G27
CPU_DBSY#
F25
CPU_BR0#
K26
CPU_LOCK#
A17
CPU_CPURSET#
G25
CPU_RS2#
G26
CPU_RS1#
J25
CPU_RS0#
F26
CPU_TRDY#
J26
CPU_HIT#
H25
CPU_HITM#
A9
CPU_RSET
AH5
SUS_STAT#
AG5
SYSRESET#
C7
POWERGOOD
V28
CPU_COMP_N
W29
CPU_COMP_P
H23
CPVDD
J23
CPVSS
W28
CPU_VREF
Y29
THERMALDIODE_N
Y28
THERMALDIODE_P
B17
TESTMODE
CHS-216IGP9050A21_BGA718
PART 1
OF 6
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_DSTBN0#
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
CPU_DSTBN1#
AGTL+ I/F
PENTIUM
CPU_DSTBN2#
MISC.
CPU_DSTBN3#
H_A#[3..31] 4
H_REQ#[0..4] 4
H_D#[0..63] 4
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBP0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_DSTBP1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
IV
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_DSTBP2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_DSTBP3#
L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29
B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27
F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22
B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_DINV#0 5
H_DSTBN#0 5
H_DSTBP#0 5
H_DINV#1 5
H_DSTBN#1 5
H_DSTBP#1 5
H_DINV#2 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#3 5
H_DSTBN#3 5
H_DSTBP#3 5
+CPU_CORE
C303
A A
5
4
22U_1206_10V4Z
0.1U_0402_10V6K
1
1
2
C306
C307
2
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
1
C305
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C280
2
1
1
C304
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C265
2
1
C248
2
0.1U_0402_10V6K
1
C257
0.1U_0402_10V6K
2
2
Title
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-AGTL+
LA-2101
1
752Saturday, November 22, 2003
of
0.1
5
D D
DDR_SBS013,14
DDR_SBS113,14
DDR_SMA1513,14
DDR_SRAS#13,14
DDR_SCAS#13,14
DDR_SWE#13,14
C C
DDR_CLK013
DDR_CLK0#13
DDR_CLK113
DDR_CLK1#13
DDR_CLK314
DDR_CLK3#14
DDR_CLK414
DDR_CLK4#14
DDR_SCKE013,14
DDR_SCKE113,14
DDR_SCKE214
DDR_SCKE314
DDR_SCS#013,14
DDR_SCS#113,14
DDR_SCS#214
B B
+1.8VS
DDR_SCS#314
L10
1 2
HB-1M2012-121JT03_0805
4
U46B
DDR_SMA0
DDR_SMA1
DDR_SMA2 DDR_DQ2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM7
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_SCKE0
DDR_SCKE1
DDR_SCKE2
DDR_SCKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
MPVDD
C229
MPVSS
1 2
1U_0603_10V4Z
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
AH7
AJ8
AF9
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
CHS-216IGP9050A21_BGA718
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM I/F
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
3
DDR_DQ0
AG6
DDR_DQ1
AJ7
AJ9
DDR_DQ3
AJ10
DDR_DQ4
AJ6
DDR_DQ5
AH6
DDR_DQ6
AH8
DDR_DQ7
AH9
DDR_DQ8
AE7
DDR_DQ9
AE8
DDR_DQ10
AE12
DDR_DQ11
AF12
DDR_DQ12
AF7
DDR_DQ13
AF8
DDR_DQ14
AE11
DDR_DQ15
AF11
DDR_DQ16
AJ12
DDR_DQ17
AH12
DDR_DQ18
AH14
DDR_DQ19
AH15
DDR_DQ20
AH11
DDR_DQ21
AJ13
DDR_DQ22
AJ15
DDR_DQ23DDR_DM6
AJ16
DDR_DQ24
AF18
DDR_DQ25
AG20
DDR_DQ26
AG21
DDR_DQ27
AF22
DDR_DQ28
AF19
DDR_DQ29
AF20
DDR_DQ30
AE22
DDR_DQ31
AF23
DDR_DQ32
AJ21
DDR_DQ33
AJ22
DDR_DQ34
AJ24
DDR_DQ35
AK25
DDR_DQ36
AH21
DDR_DQ37
AH22
DDR_DQ38
AH24
DDR_DQ39
AJ25
DDR_DQ40
AK26
DDR_DQ41
AK27
DDR_DQ42
AJ28
DDR_DQ43
AH29
DDR_DQ44
AH25
DDR_DQ45
AJ26
DDR_DQ46
AJ29
DDR_DQ47
AH30
DDR_DQ48
AF29
DDR_DQ49
AE29
DDR_DQ50
AB28
DDR_DQ51
AA28
DDR_DQ52
AE28
DDR_DQ53
AD28
DDR_DQ54
AC29
DDR_DQ55
AB29
DDR_DQ56
AC26
DDR_DQ57
AB25
DDR_DQ58
Y26
DDR_DQ59
W26
DDR_DQ60
AE26
DDR_DQ61
AD26
DDR_DQ62
AA26
DDR_DQ63
Y27
C164 0.47U_0603_16V7K
AF6
1 2
C379 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
R243 49.9_0402_1%
1 2
DDR_DM[0..7]
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_SMA[0..12]
2
DDR_DM[0..7] 13,14
DDR_DQ[0..63] 13,14
DDR_DQS[0..7] 13,14
DDR_SMA[0..12] 13,14
1
+2.5V+2.5V
2
C748
0.1U_0402_10V6K
0.1U_0402_10V6K
A A
5
4
L
1
DDR_VREF
2
C744
1
DDR_VREF trace width of
20mils and space
20mils(min)
12
R647
1K_0603_1%
12
R636
1K_0603_1%
3
Title
Size Document Number Rev
2
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-DDR I/F
LA-2101
1
852Saturday, November 22, 2003
0.1
of
5
4
3
2
1
A_AD[0..31]12,24
A_CBE#[0..3]24
D D
C C
?
B B
A_PAR12,24
A_STROBE#24
A_ACAT#24
A_END#24
PCI_PIRQA#17,24,29,32
+1.5VS
A_DEVSEL#24
A_SBREQ#24
A_SBGNT#24
AGP_GNT#17
AGP_REQ#17
R589
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
1 2
+3VS
1 2
169_0402_1%
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
1 2
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
AGP_COMP
R174 0_0402_5%
A_OFF#24
POP For 150G
DEPOP For 150A
AGP8X_DET#
12
R188
10K_0402_5%
U46C
AK5
ALINK_AD0
AJ5
ALINK_AD1
AJ4
ALINK_AD2
AH4
ALINK_AD3
AJ3
ALINK_AD4
AJ2
ALINK_AD5
AH2
ALINK_AD6
AH1
ALINK_AD7
AG2
ALINK_AD8
AG1
ALINK_AD9
AG3
ALINK_AD10
AF3
ALINK_AD11
AF1
ALINK_AD12
AF2
ALINK_AD13
AF4
ALINK_AD14
AE3
ALINK_AD15
AE4
ALINK_AD16
AE5
ALINK_AD17
AE6
ALINK_AD18
AC2
ALINK_AD19
AC4
ALINK_AD20
AB3
ALINK_AD21
AB2
ALINK_AD22
AB5
ALINK_AD23
AB6
ALINK_AD24
AA2
ALINK_AD25
AA4
ALINK_AD26
AA5
ALINK_AD27
AA6
ALINK_AD28
Y3
ALINK_AD29
Y5
ALINK_AD30
Y6
ALINK_AD31
AG4
ALINK_CBE#0
AE2
ALINK_CBE#1
AC3
ALINK_CBE#2
AA3
ALINK_CBE#3
AD5
PCI_PAR/ALINK_NC
AC6
PCI_FRAME#/ALINK_STROBE#
AC5
PCI_IRDY#/ALINK_ACAT#
AD2
PCI_TRDY#/ALINK_END#
W4
INTA#
AD3
ALINK_DEVSEL#
AD6
PCI_STOP#/ALINK_OFF#
W5
ALINK_SBREQ#
W6
ALINK_SBGNT#
R196
V5
PCI_REQ#0/ALINK_NC
V6
PCI_GNT#0/ALINK_NC
K5
AGP2_GNT#/AGP3_GNT
K6
AGP2_REQ#/AGP3_REQ
M5
AGP8X_DET#
J6
AGP_VREF/TMDS_VREF
J5
AGP_COMP
CHS-216IGP9050A21_BGA718
POP For 150G
DEPOP For 150A
PART 3 OF 6
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
PCI Bus 0 / A-Link I/F
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
+1.5VS
12
R588
@1K_0402_1%
+AGP_VREF
AGPREF_8X
12
R153
@1K_0402_1%
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP2_CBE#2/AGP3_CBE2
AGP_PAR
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
AGP_ST0
AGP_ST1
AGP_ST2
POP For 150A
DEPOP For 150G
2
C698
0.1U_0402_10V6K
1
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
E5
E6
T3
U2
G3
H2
R3
M1
L3
H1
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
C3
C2
D4
E4
F6
F5
G6
G5
L6
M6
L5
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF0
AGP_AD_STBS0
AGP_AD_STBF1
AGP_AD_STBS1
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SB_STBF 17
AGP_SB_STBS 17
AGP_AD_STBF0 17
AGP_AD_STBS0 17
AGP_AD_STBF1 17
AGP_AD_STBS1 17
AGP_IRDY# 17
AGP_TRDY# 17
AGP_STOP# 17
AGP_PAR 17
AGP_FRAME# 17
AGP_DEVSEL# 17
AGP_DBI_HI 17
AGP_DBI_LO 17
AGP_RBF# 17
AGP_WBF# 17
AGPAND LVDS MUXED SIGNALS
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA1
AGP_SBA0
R573 @0_0402_5%
1 2
R591 @0_0402_5%
1 2
R590 @0_0402_5%
1 2
R572 @0_0402_5%
1 2
R593 @0_0402_5%
1 2
R592 @0_0402_5%
1 2
ENBKL#
ENVDD 17,23
AGP_STP# 17,25
AGP_BUSY# 17,25
NB_EDID_DAT
1 2
R575 @2.2K_0402_5%
NB_EDID_CLK
1 2
R574 @2.2K_0402_5%
NB_EDID_DAT 23
+3VS
NB_EDID_CLK 23
+3VS
POP For 150A
DEPOP For 150G
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
+3VS
R168
@10K_0402_5%
NB_PWRGD7,27
@2N7002_SOT23
ENBKL#
2
G
Q10
1 2
13
D
S
AGP_AD[0..31] 17
AGP_SBA[0..7] 17
AGP_C/BE#[0..3] 17
AGP_ST[0..2] 17
+3VS
R161
@10K_0402_5%
1 2
13
D
2
G
S
@2N7002_SOT23
R151
1 2
@0_0402_5%
Q8
ENBKL 17,39
POP For 150A
DEPOP For 150G
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK B US
LA-2101
952Saturday, November 22, 2003
1
0.1
of
5
4
3
2
1
+2.5VS
12
L45
KC FBM-L11-201209-221LMAT_0805
C745
0.1U_0402_10V6K
1
1
C727
2
2
NB_CRT_R23
NB_CRT_G23
NB_CRT_B23
CRT_HSYNC23
CRT_VSYNC23
1 2
CLK_NB_BCLK16
CLK_NB_BCLK#16
CLK_AGP_66M16
CLK_MEM16
1
C741
0.1U_0402_10V6K
2
1
C726
0.1U_0402_10V6K
2
@10K_0402_5%
PLLVDD_18
PLLVSS_18
CRT_HSYNC
CRT_VSYNC
NB_RSET
RC300M_X1
CLK_NB_BCLK
CLK_NB_BCLK#
1 2
1 2
1 2
1 2
CLK_AGP_66M
CLK_MEM
1 2
D D
KC FBM-L11-201209-221LMAT_0805
L11
+1.8VS
REFCLK1_NB16
CLK_AGP_66M
C C
12
R594
@10_0402_5%
C702
@15P_0402_50V8J
CLK_MEM
12
R595
@10_0402_5%
C703
@15P_0402_50V8J
1 2
0.1U_0402_10V6K
L48
+1.8VS
KC FBM-L11-201209-221LMAT_0805
L42
+1.8VS
KC FBM-L11-201209-221LMAT_0805
1 2
R600
1
C261
2
1 2
0.1U_0402_10V6K
1 2
47_0402_5%
10K_0402_5%
1
1
C746
2
2
C729
10U_0805_10V4Z
0.1U_0402_10V6K
R274 715_0402_1%
R599
56_0402_5%
1 2
+3VS
R614
1 2
L43
1 2
FBM-11-160808-121-T_0603
U46D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
R605
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
R607@10K_0402_5%
D8
ALINK_CLK
R611@10K_0402_5%
B2
AGPCLKOUT
R585@10K_0402_5%
B3
AGPCLKIN
A3
EXT_MEM_CLK
R609@10K_0402_5%
D7
USBCLK
B7
REF27
C5
OSC
CHS-216IGP9050A21_BGA718
R602
@10K_0402_5%
1 2
+3VS
1
C723
0.1U_0402_10V6K
2
PART 4 OF 6
LVDS
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
@10K_0402_5%
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
TV_CRMA
E15
C_R
TV_LUMA
C15
Y_G
TV_COMPS
D15
3VDDCCL
D6
3VDDCDA
C6
D5
A8
B8
R204
1 2
TXB0-_NB 23
TXB0+_NB 23
TXB1-_NB 23
TXB1+_NB 23
TXB2-_NB 23
TXB2+_NB 23
TXBCLK-_NB 23
TXBCLK+_NB 23
TXA0-_NB 23
TXA0+_NB 23
TXA1-_NB 23
TXA1+_NB 23
TXA2-_NB 23
TXA2+_NB 23
TXACLK-_NB 23
TXACLK+_NB 23
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
TV_CRMA 23
TV_LUMA 23
1 2
R242 75_0603_1%
3VDDCCL 23
3VDDCDA 23
R603 1K_0402_5%
R192
@10K_0402_5%
1 2
1
C735
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C225
2
0.1U_0402_10V6K
+3VS
KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
1
C731
C734
2
10U_0805_10V4Z
1
C215
C224
2
10U_0805_10V4Z
1 2
L44
1
2
KC FBM-L11-201209-221LMAT_0805
1 2
L12
1
2
+1.8VS
+1.8VS
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-2101
1
10 52Saturday, November 22, 2003
0.1
of
5
4
3
2
1
+1.5VS +2.5V
D D
C C
B B
+CPU_CORE
+3VS
U46E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
CHS-216IGP9050A21_BGA718
CORE PWR
CPU I/F PWRALINK PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
PART 5
OF 6
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR MEM I/F PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
POP For 150G
DEPOP For 150A
R608 0_0603_5%
1 2
1 2
R610 @0_0603_5%
+1.8VS
POP For 150A
+1.5VS
+3VS
DEPOP For 150G
C790
100U_D2_6.3VM
0.1U_0402_10V6K
1
C202
2
+2.5V
1
2
C214
0.1U_0402_10V6K
+1.5VS
C137
47U_B_6.3VM
+1.5VS
A A
C279
47U_B_6.3VM
1
+
C163
2
0.1U_0402_10V6K
1
+
C182
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C156
2
0.1U_0402_10V6K
1
C181
2
1
C142
2
0.1U_0402_10V6K
1
C262
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C155
2
1
2
0.1U_0402_10V6K
1
2
1
C169
2
0.1U_0402_10V6K
1
C249
C256
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C151
2
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C168
2
0.1U_0402_10V6K
C255
C240
0.1U_0402_10V6K
1
C154
2
1
1
C239
2
2
0.1U_0402_10V6K
1
C183
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C200
2
1
C209
2
0.1U_0402_10V6K
U46F
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7 J8
VSS VSS
CHS-216IGP9050A21_BGA718
10U_0805_10V4Z
0.1U_0402_10V6K
1
+
C258
C252
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C201
2
2
PART 6 OF 6
GND
+1.8VS
1
C263
2
1
C241
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C212
C213
2
0.1U_0402_10V6K
R23
VSS
R7
VSS
R8
VSS
T12
VSS
T13
VSS
T14
VSS
T15
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T27
VSS
T4
VSS
U15
VSS
U16
VSS
U7
VSS
U8
VSS
V15
VSS
V16
VSS
V27
VSS
V4
VSS
V7
VSS
V8
VSS
W15
VSS
W16
VSS
W27
VSS
Y1
VSS
Y23
VSS
Y24
VSS
Y30
VSS
Y4
VSS
Y7
VSS
Y8
VSS
R19
VSS
R18
VSS
R17
VSS
R16
VSS
R15
VSS
R14
VSS
R13
VSS
R12
VSS
R1
VSS
P4
VSS
P27
VSS
P16
VSS
P15
VSS
N8
VSS
N24
VSS
N23
VSS
N16
VSS
N15
VSS
M4
VSS
M27
VSS
M16
VSS
M15
VSS
L8
VSS
L7
VSS
L25
VSS
L24
VSS
L23
VSS
K4
VSS
K27
VSS
0.1U_0402_10V6K
1
C288
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C216
2
2
1
C199
2
0.1U_0402_10V6K
1
C184
C186
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C203
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C211
2
1
2
1
C247
2
1
C198
2
0.1U_0402_10V6K
1
C289
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C204
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C254
2
C130
10U_0805_10V4Z
1
C352
C180
2
0.1U_0402_10V6K
1
1
C238
2
2
0.1U_0402_10V6K
+3VS
1
C178
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C353
2
0.1U_0402_10V6K
1
C253
C237
2
0.01U_0402_16V7Z
0.1U_0402_10V6K
1
C179
2
1
C329
2
0.1U_0402_10V6K
0.01U_0402_16V7Z
1
2
1
C170
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C330
2
1
C230
2
0.1U_0402_10V6K
1
C172
2
1
2
12
C271
4.7U_0805_10V4Z
1
C171
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C317
C354
0.1U_0402_10V6K
2
12
C707
4.7U_0805_10V4Z
0.1U_0402_10V6K
1
C140
2
1
C308
2
0.1U_0402_10V6K
1
C141
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C293
2
0.1U_0402_10V6K
1
2
1
C322
2
0.1U_0402_10V6K
1
C150
2
0.1U_0402_10V6K
1
C309
2
1
1
2
2
0.1U_0402_10V6K
C272
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-PO WE R
LA-2101
1
11 52Tuesday, November 18, 2003
0.1
of
5
4
3
2
1
A_AD[0..31]9,24
R142 10K_0402_5%
A_AD31
D D
C C
B B
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
R163 4.7K_0402_5%
R587 4.7K_0402_5%
R147 10K_0402_5%
1 2
R158 @4.7K_0402_5%
R568 @10K_0402_5%
1 2
R584 4.7K_0402_5%
R144 10K_0402_5%
1 2
R155 @4.7K_0402_5%
R143 10K_0402_5%
1 2
R154 @4.7K_0402_5%
R565 10K_0402_5%
1 2
R582 @4.7K_0402_5%
R566 10K_0402_5%
1 2
R567 10K_0402_5%
1 2
R583 @4.7K_0402_5%
R145 10K_0402_5%
1 2
R156 @4.7K_0402_5%
R146 10K_0402_5%
1 2
R157 @4.7K_0402_5%
R564 @4.7K_0402_5%
R581 4.7K_0402_5%
1 2
R569 10K_0402_5%
1 2
D22
2 1
CH751H-40_SC76
D59
2 1
CH751H-40_SC76
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 5,16
+3VS
BSEL0 5,16
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcShortReset#
DEFAULT: 1
0: TEST MOD E
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0: PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTE RNAL CLK GE N E NABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
R149 @4.7K_0402_5%
A_AD18
A_AD17
A_PAR9,24
R160 4.7K_0402_5%
R563 @4.7K_0402_5%
R580 4.7K_0402_5%
A_PAR
R159 @4.7K_0402_5%
R148 4.7K_0402_5%
+3VS
+3VS
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
+3VS
0: DEBUG MODE
1: NORMAL
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-SYSTEM ST RA P
LA-2101
12 52Saturday, November 22, 2003
1
0.1
of
A
1 1
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMA[0..12]
2 2
DDR_SCKE18,14
DDR_SBS08,14
DDR_SWE#8,14
DDR_SCS#08,14
DDR_SMA158,14
3 3
4 4
A
DDR_DQ[0..63] 8,14
DDR_DQS[0..7] 8,14
DDR_DM[0..7] 8,14
DDR_SMA[0..12] 8,14
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SMA15
RP21
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP24
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP28
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
Layout note
B
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_CLK08
DDR_CLK0#8
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
DDR_CKE1
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_BS0
DDR_WE#
DDR_CS#0 DDR_CS#1
DDR_SMAA15
DDR_DQ33
DDR_DQ37
DDR_DQS4 DDR_DM4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
SMDATA14,16,25
SMCLK14,16,25
B
+3VS
C
+2.5V +2.5V +2.5V
JP24
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5747-3-111
Layout note
Place Add/Command resisotrs
Close to Pin, max L = 300 mils
C
DU/RESET#
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
VSS
DM8
VDD
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CB4
74
CB5
76
78
80
CB6
82
84
CB7
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
CK1
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_CKE0
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4
DDR_SMAA2
DDR_SMAA0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_DQ32
DDR_DQ36
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_CLK1# 8
DDR_DQ48
DDR_DQ52
DDR_DM6DDR_DQS6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
D
DDR_CLK1 8
E
C105
0.1U_0402_10V6K
C101
0.1U_0402_10V6K
DDRA_VREF trace width of
L
20mils and space 20mils(min)
10_0804_8P4R_5%
10_0804_8P4R_5%
10_0804_8P4R_5%
E
RP20
RP25
RP29
2
1
DDRA_VREF
2
1
18
27
36
45
18
27
36
45
18
27
36
45
12
R133
1K_0603_1%
12
R132
1K_0603_1%
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
F
DDR_SCKE0 8,14
DDR_SBS1 8,14
DDR_SRAS# 8,14
DDR_SCAS# 8,14
DDR_SCS#1 8,14
F
G
Title
Size Document Number Rev
Date: Sheet
G
Comp a l Electro nics , In c .
DDR-SODIMM SLOT0
LA-2101
H
13 52Saturday, November 22, 2003
of
H
0.1
A
+1.25VS
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
1 1
2 2
3 3
4 4
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
DDR_SCKE08,13
DDR_SCKE18,13
DDR_SCS#18,13
DDR_SCS#08,13
DDR_SCKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#2
DDR_SMA15
RP6
56_0804_8P4R_5%
RP8
56_0804_8P4R_5%
RP10
56_0804_8P4R_5%
RP12
56_0804_8P4R_5%
RP14
56_0804_8P4R_5%
RP18
33_0804_8P4R_5%
RP23
33_0804_8P4R_5%
RP27
33_0804_8P4R_5%
RP31
33_0804_8P4R_5%
RP5
18
27
36
45
56_0804_8P4R_5%
RP7
18
27
36
45
56_0804_8P4R_5%
RP9
18
27
36
45
56_0804_8P4R_5%
RP11
18
27
36
45
56_0804_8P4R_5%
RP13
18
27
36
45
56_0804_8P4R_5%
18
27
36
45
RP22
18
27
36
45
33_0804_8P4R_5%
RP26
18
27
36
45
33_0804_8P4R_5%
RP30
18
27
36
45
33_0804_8P4R_5%
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_SCS#28 DDR_SCS#3 8
DDR_SCKE2
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3
B
+2.5V
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_CLK38
DDR_CLK3#8
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
*27 *27
R267
1 2
10_0402_5%
DDR_SBS08,13
DDR_SCS#2 DDR_CS#2 DDR_SCS#3
1 2
10_0402_5%
R291
DDR_SWE#8,13
DDR_SMA158,13
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
SMDATA13,16,25
SMCLK13,16,25
DDR_CKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0 DDR_SRAS#
DDR_SWE#
DDR_SMA15
DDR_DQ33
DDR_DQ37
DDR_DQS4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
+3VS
C
JP23
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5763-3-111
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
VSS
DM8
VDD
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CB4
74
CB5
76
78
80
CB6
82
84
CB7
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
CK1
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_CKE2 DDR_SCKE2DDR_SCKE3
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SCAS#
DDR_CS#3
DDR_DM4
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ46
DDR_DM6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
10_0402_5%
DDR_DQ32
DDR_DQ36
DDR_DQ42
DDR_DQ48
DDR_DQ52
+3VS
R226
DDR_SBS1 8,13
DDR_SRAS# 8,13
DDR_SCAS# 8,13
R28810_0402_5%
DDR_CLK4# 8
DDR_CLK4 8
Layout note
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
DDRB_VREF trace width of
L
20mils and space
20mils(min)
12
12
*27
2
C690
0.1U_0402_10V6K
1
DDRB_VREF
2
C692
0.1U_0402_10V6K
1
DDR_DQ33
DDR_DQ37
DDR_DQS4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
DDR_SCKE2 8DDR_SCKE38
+2.5V+2.5V
12
R556
1K_0603_1%
12
R561
1K_0603_1%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
DDR_SMA[0..12]
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
RP34
RP36
RP38
RP41
RP43
+1.25VS
RP33
18
27
36
45
56_0804_8P4R_5%
RP35
18
27
36
45
56_0804_8P4R_5%
RP37
18
27
36
45
56_0804_8P4R_5%
RP40
18
27
36
45
56_0804_8P4R_5%
RP42
18
27
36
45
56_0804_8P4R_5%
E
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
DDR_SMA[0..12] 8,13
DDR_DQS[0..7] 8,13
DDR_DQ[0..63] 8,13
DDR_DM[0..7] 8,13
DDR_DQ32
DDR_DQ36
DDR_DM4
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ52
DDR_DM6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
DDR-SODIMM SLOT1
LA-2101
14 52Saturday, November 22, 2003
E
0.1
of
A
Layout note :
Distribute as close as possible
to DDR-SODIMM0.
+2.5V
B
C
D
E
Layout note :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V
1
2
1
C242
0.1U_0402_10V6K
2
1
C737
0.1U_0402_10V6K
2
1
C91
2
1000P_0402_50V7K
1
2
1
2
1000P_0402_50V7K
1
C90
2
1000P_0402_50V7K
C267
0.1U_0402_10V6K
C742
0.1U_0402_10V6K
1
C133
2
1
C463
0.1U_0402_10V6K
2
1
C770
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C268
2
1000P_0402_50V7K
1
2
1
2
C390
C812
0.1U_0402_10V6K
C781
0.1U_0402_10V6K
1000P_0402_50V7K
1
2
1 1
1
+
C798
220U_D2_4VM
2
1
C424
0.1U_0402_10V6K
2
1
+
C686
220U_D2_4VM
2
1
C124
0.1U_0402_10V6K
2
1
C128
0.1U_0402_10V6K
2
1
+
C685
220U_D2_4VM
2
1
C136
0.1U_0402_10V6K
2
1
C135
0.1U_0402_10V6K
2
1
C159
0.1U_0402_10V6K
2
1
C158
0.1U_0402_10V6K
2
1
C185
0.1U_0402_10V6K
2
1
C196
0.1U_0402_10V6K
2
1
C206
0.1U_0402_10V6K
2
1
C233
0.1U_0402_10V6K
2
1
C227
0.1U_0402_10V6K
2
1
C357
0.1U_0402_10V6K
2
1
C358
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C388
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
+
C797
220U_D2_4VM
2
1
C725
0.1U_0402_10V6K
2
Layout note :
for EMI solution
1
C207
0.1U_0402_10V6K
2
1
C730
0.1U_0402_10V6K
2
+2.5V
Layout note :
Place one cap close to every 2 pull up resistors termination to
2 2
+1.25VS
1
C104
0.1U_0402_10V6K
2
+1.25VS
1
C143
0.1U_0402_10V6K
2
+1.25VS
1
C243
0.1U_0402_10V6K
3 3
2
+1.25VS
1
C110
0.1U_0402_10V6K
2
1
C148
0.1U_0402_10V6K
2
1
C251
0.1U_0402_10V6K
2
1
C103
0.1U_0402_10V6K
2
1
C166
0.1U_0402_10V6K
2
1
C284
0.1U_0402_10V6K
2
1
C109
0.1U_0402_10V6K
2
1
C176
0.1U_0402_10V6K
2
1
C292
0.1U_0402_10V6K
2
1
C116
0.1U_0402_10V6K
2
1
C165
0.1U_0402_10V6K
2
1
C283
0.1U_0402_10V6K
2
1
C127
0.1U_0402_10V6K
2
1
C175
0.1U_0402_10V6K
2
1
C291
0.1U_0402_10V6K
2
1
C115
0.1U_0402_10V6K
2
1
C188
0.1U_0402_10V6K
2
1
C126
0.1U_0402_10V6K
2
1
C195
0.1U_0402_10V6K
2
1
C144
0.1U_0402_10V6K
2
1
C187
0.1U_0402_10V6K
2
1
C149
0.1U_0402_10V6K
2
1
C194
0.1U_0402_10V6K
2
C92
1000P_0402_50V7K
1
C450
2
1000P_0402_50V7K
1
C704
0.1U_0402_10V6K
2
1
C792
0.1U_0402_10V6K
2
1
C462
2
1
C711
0.1U_0402_10V6K
2
1
C795
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C461
2
1
C722
0.1U_0402_10V6K
2
1
C807
0.1U_0402_10V6K
2
+1.25VS
1
C314
0.1U_0402_10V6K
2
+1.25VS
1
C363
0.1U_0402_10V6K
2
+1.25VS
4 4
1
C442
0.1U_0402_10V6K
2
1
C321
0.1U_0402_10V6K
2
1
C370
0.1U_0402_10V6K
2
1
C446
0.1U_0402_10V6K
2
A
1
C313
0.1U_0402_10V6K
2
1
C387
0.1U_0402_10V6K
2
1
C441
0.1U_0402_10V6K
2
1
C320
0.1U_0402_10V6K
2
1
C401
0.1U_0402_10V6K
2
1
C445
0.1U_0402_10V6K
2
1
C337
0.1U_0402_10V6K
2
1
C386
0.1U_0402_10V6K
2
1
C457
0.1U_0402_10V6K
2
1
C347
0.1U_0402_10V6K
2
1
C400
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
B
1
C336
0.1U_0402_10V6K
2
1
C420
0.1U_0402_10V6K
2
1
C346
0.1U_0402_10V6K
2
1
C431
0.1U_0402_10V6K
2
1
C364
0.1U_0402_10V6K
2
1
C419
0.1U_0402_10V6K
2
1
C371
0.1U_0402_10V6K
2
1
C430
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
DDR SODIMM Decoupling
LA-2101
E
15 52Tuesday, November 18, 2003
of
0.1
A
B
C
D
E
F
G
H
L14
1 2
U18
6
XIN
7
XOUT
35
SCLK
34
SDATA
10
VTTPWRGD/PD#
45
CPU_STP#
12
PCI_STOP#
26
24/48#SEL
11
PCI33/66#SEL
48MHz_1
28
48MHz_0
4
FS2/REF2
3
FS1/REF1
2
FS0/REF0
38
IREF
+3V_CLK
42
8
Width=40 mils
C310
10U_0805_10V4Z
13
48
303129
VDDSD
VDDPCI
VDD48M
VDDCPU
VDDAGP
GNDREF
GNDXTAL
GNDPCI
GNDPCI
GND48M
5
181924
252733
0.1U_0402_10V6K
1
C290
2
+3VS_VDDA
1
9
VDDA
VDDPCI
VDDREF
VDDXTAL
VSSA
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDSD
GNDAGP
GNDCPU
ICS951402AGT_TSSOP48
46
41
1
C274
2
0.1U_0402_10V6K
36
C275
0.1U_0402_10V6K
VSSA
37
CLK_CPU_CLK
40
CLK_CPU_CLK#
39
44
43
47
32
14
15
16
17
20
21
22
23
0.1U_0402_10V6K
1
C276
2
1
2
CLK_NB
CLK_NB#
MEM_66M
AGP_66M
AGP_EXT_66M
FS3
FS4
1
2
C366
10U_0805_10V4Z
1
C392
2
0.1U_0402_10V6K
+3VS_VDDA
1
2
R265 33_0402_5%
R266 33_0402_5%
R263 33_0402_5%
R264 33_0402_5%
R262 33_0402_5%
R239 33_0402_5%
R240 33_0402_5%
R332 33_0402_5%
0.1U_0402_10V6K
1
C277
0.1U_0402_10V6K
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
POP For 150G
DEPOP For 150A
1
C773
2
0.1U_0402_10V6K
L15
1 2
CHB2012U121_0805
1
1
C391
C380
0.1U_0402_10V6K
2
2
CLK_BCLK
R235 49.9_0402_1%
1 2
R236 49.9_0402_1%
1 2
CLK_BCLK#
R237 49.9_0402_1%
1 2
R238 49.9_0402_1%
1 2
+3VS
CLK_BCLK 4
CLK_BCLK# 4
CLK_NB_BCLK 10
CLK_NB_BCLK# 10
CLK_MEM 10
CLK_AGP_66M 10
CLK_AGP_EXT_66M 1 7
CLK_ALINK_SB 24
+3VS
HB-1M2012-121JT03_0805
1 1
R363 @10_0402_5%
SYS_XCLK36
+3VS
12
12
R228
R343
10K_0402_5%
2 2
10K_0402_5%
R256 10K_0402_5%
R255 @10K_0402_5%
SD_CLKIN29
REFCLK1_NB10
CLK_14M_SIO36
CLK_SB_14M25
R254 33_0402_5%
R658 20_0402_5%
R663 33_0402_5%
R664 33_0402_5%
1 2
C410 10P_0402_50V8K
1 2
12
Y1
XTALOUT_CLK
1 2
C411
14.31818MHZ_20P_6X1430004201
10P_0402_50V8K
SMCLK13,14,25
SMDATA13,14,25
VTT_PWRGD25,27
1 2
1 2
1 2
1 2
1 2
1 2
XTALIN_CLK
12
VTT_PWRGD
PCI33/66#
CLK_48M
FS2
FS1
FS0
CLK_IREF
R253
475_0402_1%
1 2
R321
@1M_0402_5%
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
3 3
4 4
A
0 0 0 1 0
0 0 0 0 1
**
0 0 0 0 0
Note: 0 = PULL LOW
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
BSEL15,12
BSEL05,12
133
10K_0402_5%
*
Spreaf OFF OR
Center spr e a d +/-0. 3 %
+3VS +3VS
12
12
R362
R357
10K_0402_5%
C
D47 CH751H-40_SC76
D46 CH751H-40_SC76
133
100 100
B
A-LINK FREQ
PCI33/66# = HIGH
**
PCI33/66# = LOW 33MHZ
10K_0402_5%
21
21
R342
+3V_CLK
12
66MHZ
12
R341
10K_0402_5%
D
FS1
FS0
FS2
FS3
FS4
PCI33/66#
12
R314
4.7K_0402_5%
+3V_CLK
12
12
12
R313
4.7K_0402_5%
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
E
R315
@10K_0402_5%
R329
10K_0402_5%
12
@10K_0402_5%
12
R316
R331
10K_0402_5%
12
@10K_0402_5%
12
R317
R333
10K_0402_5%
12
R327
10K_0402_5%
12
R330
@10K_0402_5%
F
Title
Size Document Number Rev
Date: Sheet
G
Compal Electronics, Inc.
Clock Generator
LA-2101
16 52Saturday, November 22, 2003
H
of
0.1
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