Page 1
A
1 1
B
C
D
E
SAPPORO 150A+G
2 2
LA-2101 REV0.1 Schematic
3 3
Portability Prescott/Northwood
RC300ML(RX300ML)+IXP150+ATI M11P/M10C(128MB VRAM)
2003-11-10
4 4
Compal Electronics, Inc.
Title
Cover Page
Size Document Number Rev
B
152Tuesday, November 18, 2003
A
B
C
D
Date: Sheet
E
of
0.1
Page 2
A
B
C
D
E
DAL01 LA-2101 BLOCK DIAGRAM
4 4
Northwood-MT
Prescott-MT
(uFCBGA/uFCPGA-478)
LCD Conn 1
page 23
CRT & TV-OUT Conn.
W/EXT VGA CHIP
3 3
LCD Conn 2
page 23
page 23
ATI-M11P/M10C
page 17,18,19,20
W/INT VGA
533MHz(0.8V)
AGP 8X BUS
FSB
ATI-RC300ML
(ATI-RX300ML)
VGA M9 Embeded
868 pin u-BGA
VGA DDR x2 CHB
page 22 page 21
Mini PCI
RJ-45
PAGE 28
2 2
1 1
Port 1
PAGE 32
Slot 0
PAGE 30
SD Co nn
PAGE 30
CB PWR SW
ENE CP2211
PAGE 30
LAN
RTL8100C
IEEE1394
TSB43AB21A
CARDBUS
ENE 712/1410
VGA DDR x2 CHA
PAGE 31
PAGE 28
PAGE 32
PAGE 29
33MHz (3.3V)
Super I/O
LPC47N217
REV B
PCI BUS
PAGE 36
LPC BUS 33MHz (3.3V)
266MHz(3.3V)
A-Link
ATI-SB150
BGA 457 pin
Embedded
Controller
NS PC87591L
PAGE 4,5,6
533MHz
PAGE 7,8,9,10,11,12
PAGE 24,25,26,27
PAGE 39
Thermal Sensor
266/333MHz
(2.5V)
Memory Bus
480MHz(5V)
Primary
ATA-100 (5V)
Secondary
ATA-100 (5V)
AC-LINK
24.576MHz
ADM1032
PAGE 5
USB 2.0 P ort *3
0, 2, 4
AC97 CODEC
Clock Gener a tor
ICS951402AGT
SO-DIMM x 2(DDR)
BANK 0,1,2,3
PAGE 37
IDE HDD
IDE ODD
ALC 250
MDC
Connecto r
PAGE 35
PAGE 35
PAGE 33
PAGE 38
PAGE16
PAGE 13,14,15
CPU VID
PAGE 5
Audio Amp lifier
TPA0232
PAGE 34
Programming Clock Gen
FANController
RTC Ba t t e ry
DC/DC Inte rfac e
PAGE 36
PAGE 42
PAGE 24
PAGE 43
LID/Kill Switch
Power Buttom
DCIN&DETECTOR
BATT CONN/OTP
CHARGER
3V/5V/12V
DDR_2.5V/1.25V, 1.8 V
1.5V/VGA_CORE
CPU_CORE
Direct Board (LS - 1911)
Connecto r
VR/CIR Board (LS - 1913)
Connecto r
TP Board (LS-2101)
Connecto r
PAGE 41
PAGE 44
PAGE 45
PAGE 46
PAGE 47
PAGE 48
PAGE 48
PAGE 50,51,52
PAGE 40
PAGE 40
PAGE 40
FIR
PAGE 37
A
Parallel
PAGE 38
B
Scan K B
PAGE 39
BIOS(1M)
& I/O PORT
PAGE 40
Compal Electronics, Inc.
Title
Block Digram
Size Document Number Rev
Custom
C
D
Date: Sheet
252Tuesday, November 18, 2003
E
0.1
of
Page 3
A
B
C
D
E
Voltage Rails
STATE
Power Plane Descripti on
1 1
2 2
VIN
B+
+CPU_CORE
+CPUVID
+VGA_CORE ON OFF OFF1.0V/1.2V switched power rail for VGA chip
+1.25VS 1.25V switched power rail
+1.5VS
+1.8VS 1.8VS switched power rail OFFOFFON
+2.5VALW 2.5V always on power rail ON*ONON
+2.5V
+3VALW
+3V
+3VS
+5V
+5VS
+12VALW
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power ci rcuit.
Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
AGP 4X/8X
2.5V power rail
2.5V switched power rail+2.5VS
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V power rail ON
5V switched power rail
12V always on power r ail
RTC power
S1 S3 S5
ON
ON ONONON
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON ON
ON
ON
ON
ON
ON+5VALW
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON*ON
OFF
OFF
ON*
OFF
OFF
ON*
ON
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
SIGNAL
SLP_S3# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH
LOW
LOW
LOW LOW
AD_BID
0 V
HIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
0 V 0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
ON ON
ON
OFF
OFF
OFF
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
max
External PCI Devices
Device IDSEL# REQ# / G NT # Interrupts
VGA
CardBus
LAN
Mini-PCI
1394
3 3
SD
AD16
AD20
AD19
AD18
AD16 0
AD20
2
3 PIRQD
1/4
2
PIRQA
PIRQA
PIRQC/PIRQD
PIRQA
PIRQB
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
EC SM Bus1 address
Device
Smart Batte r y
EEPROM(24C16/0 2)
(24C04)
4 4
IXP150 SM Bus address
Device
Clock Generator
(ICS951402AGT)
DDR DIMM0
DDR DIMM2
Address Address
1010 000X b
1011 000Xb
Address
1101 001Xb
1010 000Xb
1010 001Xb
A
EC SM Bus2 address
Device
ADM1032
ICS960011
B
1001 110X b0001 011X b
1101 110X b
Compal Electronics, Inc.
Title
Size Document Number Rev
B
C
D
Date: Sheet
LA-2101
Notes
0.1
of
352Tuesday, November 18, 2003
E
Page 4
5
JCPU1A
H_A#[3..31]7
D D
H_REQ#[0..4]7
C C
+CPU_CORE
+CPU_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number CommendCommend
Northwood
Pin name
FERR#B6
AA20
ITPCLKOUT0
ITPCLKOUT1AB22
A A
AD20 Connect to CPU
AF23
H_REQ#[0..4]
H_ADS#7
R67 51_0402_5%
1 2
1 2
R87 51_0402_5%
H_BR0#7
H_BPRI#7
H_BNR#7
H_LOCK#7
CLK_BCLK16
CLK_BCLK#16
H_HIT#7
H_HITM#7
H_DEFER#7
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND BOOTSELECTVSSAD1 CPU determine
Connect to GNDVSSAE26 float
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
H_IERR#
CLK_BCLK
CLK_BCLK#
FOX_PZ47803-274A-42_Prescott
Prescott
Pin name
FERR#/PBE#
TESTHI6Pull-up56ohm
TESTHI7Pull-up 56ohm
VIDPWRGDNCAD2
VID5floatNCAD3
VCCIOPLLVCCA
VCCAVCCIOPLL Connect to CPU
OPTIMIZED/
COMPAT#
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
AF22
BCLK0
AF23
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
Pull-up 62ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
Pull-up 8.2Kohm
to +VCCVID
Pull-up1Kohm to
+3VRUN & connect
to PWRIC
Connect to +VCCVIDVCCVIDLBfloatNCAF3
Filter
Filter
CON
TROL
4
A10
A12
A14
A16
A18
A20A8AA10
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
HOST
ADDR
CONTROL
CLK
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
H1H4H23
H26
A11
A13
4
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
A15
A17
A19
A21
A24
A26A3A9
AA1
PrescottNorthwood
Depop Pop
Depop
Depop
3
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
C10
C12
C14
C16
C18
C20C8D11
D13
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
POWER
Northwood-MT
Prescott-MT
GND POWER
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
F13
F15
F17
R42
0_0402_5%
R_C
VCC_80
F19
F9
12
1 2
R45
0_0402_5%
Pop: Northwood
Depop: Prescott
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
BOOTSELECT
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
AD1
AD18
AD21
AD23
AD4
AD8
PopPop
D15
D17
VCC_68
VCC_69
VCC_78
VCC_79
E20E8F11
D19D7D9
E10
VCC_73
VCC_70
VCC_71
VCC_72
HOST
ADDR
VCC_74
VCC_75
VCC_76
VCC_77
E12
E14
E16
E18
H_BOOTSELECT 50
2
+CPU_CORE
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
+CPU_CORE
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_D#[0..63] 7
1
PopPop
PopPop
Pop
Pop
DepopPop
DepopPop
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
2
Title
Prescott Processor in uFCPGA478 (1/2)
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
452Saturday, November 22, 2003
1
0.1
Page 5
5
4
3
2
1
AF26
F25
F5
VSS_125
VSS_126
VSS_127
VSS_128
SKTOCC#
REF
OPTIMIZED/COMPAT#
ITP
DATA
ADDR
DATA
MISC
VCCVID
AF4
Trace >= 25mils
1
C35
0.1U_0402_10V6K
2
H_VID_PWRGD
H_SKTOCC#
DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
+CPUVID
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
RE
Pop: Prescott
Depop: Northwood
@680_0603_5%
1 2
R126
@0_0402_5%
1 2
+CPU_GTLREF
H_TESTHI0
H_TESTHI1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_GHI#
H_DPSLPR#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_PROCHOT#
R_E
R76
H_GHI#
R80 0_0402_5%
Place decoupling cap 220PF near CPU.
C76
1 2
220P_0402_50V7K
R_G
R127 0_0402_5%
1 2
R123 56_0402_5%
1 2
R59 56_0402_5%
1 2
R111 56_0402_5%
1 2
R79 56_0402_5%
1 2
R73 56_0402_5%
1 2
R58 56_0402_5%
1 2
R89 300_0402_5%
1 2
R124 56_0402_5%
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
R62130_0402_5%
12
H_SLP# 24
+CPUVID
1 2
Pop: Northwood
Depop: Prescott
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_ADSTB#0 7
H_ADSTB#1 7
+CPU_CORE
H_PROCHOT# 45
CPU_GHI# 25
+CPU_CORE
+CPU_CORE
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26B4B8
C11
C13
C15
C17
C19C2C22
C25C5C7C9D10
D12
D14
D16
D18
D20
D21
D24D3D6D8E1
E11
E13
E15
E17
E19
E23
E26E4E7E9F10
F12
F14
F16
JCPU1B
+CPUVID
CLK_ITP
CLK_ITP#
H_TRDY#7
H_A20M#24
H_IGNNE#24
H_SMI#24
H_PWRGOOD24
H_STPCLK#24
H_INTR24
H_NMI24
H_INIT#24
H_RESET#7
H_THERMTRIP#6
H_VCCA
H_VSSA
H_FERR#24
H_DBSY#7
H_DRDY#7
H_RS#[0..2]
BSEL012,16
BSEL112,16
1 2
R70
51.1_0603_1%
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PWRGOOD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TMS
ITP_TRST#
VCCVIDLB
@0_0402_5%
CLK_ITP
CLK_ITP#
COMP0
COMP1
R44
R112
51.1_0603_1%
1 2
1 2
FOX_PZ47803-274A-42_Prescott
AB23
AB25
AD20
AE23
AD22
AC26
AD26
G5
AB2
W5
AD6
AD5
AC6
AB5
AC4
AA5
AB4
AF3
L24
F1
F4
J6
C6
B6
B2
B5
Y4
D1
E5
H5
H2
B3
C4
A2
Y6
D4
C1
D5
F7
E6
A5
A4
P1
RS#0
RS#1
RS#2
RSP#
TRDY#
CON
TROL
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LEGACY
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
VSS_57
VSS_58
ITP
CLK
VSS_129
VSS_130
F8
G21
VSS_59
VSS_60
VSS_61
MISC
THER
MAL
MISC
ITP
MISC
VSS_131
VSS_132
VSS_133
G24G3G6J2J22
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
GROUND
Northwood-MT
Prescott-MT
GROUND MISC
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VID0
AE5
J25J5K21
K24K3K6L1L23
L26L4M2
M22
M25M5N21
N24N3N6P2P22
P25P5R1
R23
R26R4T21
T24T3T6U2U22
U25U5V1
V23
V26V4W21
W24W3W6Y2Y22
H_VID050
H_VID150
H_VID250
H_VID350
H_VID450
H_VID550
Y25
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
AE4
Y5
H_THERMTRIP#
1 2
R61 56_0402_5%
H_PWRGOOD
1 2
D D
R119 300_0402_5%
H_RESET#
1 2
R120 51_0402_5%
H_RS#[0..2]7
Place near CPU
JTAG PULL DOWN
RP4
1K_8P4R_1206_5%
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI
1 8
2 7
3 6
4 5
Close to the CPU
+CPU_CORE
R82 51_0402_5%
1 2
R78 51_0402_5%
1 2
R75 51_0402_5%
1 2
R81 51_0402_5%
1 2
R77 51_0402_5%
1 2
R74 51_0402_5%
VCCSENSE50
VSSSENSE50
C80
Trace >= 25mils
+
33U_D2_8M_R35
Pop: Prescott
Depop: Northwood
1 2
Note: Please change to 10uH, DC current
C C
B B
of 100mA parts and close to cap
+CPU_CORE
L5 LQG21F4R7N00_0805
1 2
L6 LQG21F4R7N00_0805
1 2
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
R571 @100K_0402_0.5%
R570 @100K_0402_0.5%
1 2
1 2
1 2
F18F2F22
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VIDPWRGD
VID5
VID1
VID2
VID3
VID4
AE3
AE2
AE1
AD2
AD3
VID PWRGD Circuit
Thermal Sensor
H_THERMDA
1
C45
2200P_0402_50V7K
A A
EC_SMB_CK236,39
EC_SMB_DA236,39
2
H_THERMDC
5
U4
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
+3VS
1
C47
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
12
R93
@10K_0402_5%
1
6
4
5
C736
0.1U_0402_16V4Z
H_VID_PWRGD
SN74LVC125APWLE_TSSOP14
+3V POWER
4
U44A
+3V
1
2
1
P
OE#
IO
G
12
R627
10K_0402_5%
1 2
R628 0_0402_5%
14
23
7
VID_PWRGD 50
VCORE_ENLL 50
GTL Reference Voltage
Layout note :
1. Place R_A and R_B near CPU (Within 1.5").
2. +CPU_GTLREF Trace wide 12mils(min),Space 15mils
+CPU_CORE
12
R109
49.9_0603_1%
R_A
12
R110
R_B
100_0603_1%
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
3
+CPU_GTLREF
1
C69
1U_0603_10V4Z
2
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
+3VS
12
R135
4.7K_0402_5%
R134
2
PM_STPCPU#24,50
1 2
4.7K_0402_5%
2
H_DPSLPR#
1
Q6
2
3
MMBT3904_SOT23
1
Q5
3
MMBT3904_SOT23
Title
Size Document Number Rev
C
Date: Sheet
VID PULL HIGH
H_VID5
1 2
R57 1K_0402_5%
H_VID4
1 2
R47 1K_0402_5%
RP3
H_VID3
H_VID2
H_VID1
H_VID0
1K_8P4R_1206_5%
Compal Electronics, Inc.
Prescott Processor in uFCPGA478 (2/2)
LA-2101
1
+3VS
45
36
27
18
552Saturday, November 22, 2003
0.1
of
Page 6
5
4
3
2
1
+CPU_CORE
1
C549
D D
C C
22U_1206_10V4Z
2
+CPU_CORE
1
C595
22U_1206_10V4Z
2
+CPU_CORE
1
C56
22U_1206_10V4Z
2
+CPU_CORE
1
C17
22U_1206_10V4Z
2
1
C567
22U_1206_10V4Z
2
1
C618
22U_1206_10V4Z
2
1
C68
22U_1206_10V4Z
2
1
C16
22U_1206_10V4Z
2
1
C585
22U_1206_10V4Z
2
1
C643
22U_1206_10V4Z
2
1
C15
22U_1206_10V4Z
2
Place 11 North of Socket(Stuff 8)
1
C606
22U_1206_10V4Z
2
1
C624
22U_1206_10V4Z
2
1
C641
22U_1206_10V4Z
2
Place 12 Inside Socket(Stuff all)
1
C655
22U_1206_10V4Z
2
1
C597
22U_1206_10V4Z
2
1
C617
22U_1206_10V4Z
2
Place 9 South of Socket(Unstuff all)
1
C14
22U_1206_10V4Z
2
1
C22
22U_1206_10V4Z
2
1
C21
22U_1206_10V4Z
2
1
C18
22U_1206_10V4Z
2
1
C642
22U_1206_10V4Z
2
1
C20
22U_1206_10V4Z
2
1
C507
22U_1206_10V4Z
2
1
C654
22U_1206_10V4Z
2
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239
Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32
1
C518
22U_1206_10V4Z
2
22uF depop reference
Springdale Customer Schematic R1.2 page82
1
C57
22U_1206_10V4Z
2
1
C525
22U_1206_10V4Z
2
1
C50
22U_1206_10V4Z
2
1
C542
22U_1206_10V4Z
2
+CPU_CORE
B B
1
+
C119
470U_D2_2.5VM
2
+CPU_CORE
1
+
C53
470U_D2_2.5VM
2
+CPU_CORE
A A
1
+
C62
470U_D2_2.5VM
2
1
+
C100
470U_D2_2.5VM
2
1
+
C9
470U_D2_2.5VM
2
1
+
C37
470U_D2_2.5VM
2
5
470uF _ERS10m ohm* 15, ESR=0.5m ohm
1
+
C96
470U_D2_2.5VM
2
1
+
C79
@470U_D2_2.5VM
2
**
1
+
C29
470U_D2_2.5VM
2
1
+
C30
@470U_D2_2.5VM
2
1
+
C43
470U_D2_2.5VM
2
4
1
+
C71
470U_D2_2.5VM
2
1
+
C51
470U_D2_2.5VM
2
1
+
C64
470U_D2_2.5VM
2
MAINPWON44,45,47
1
Q30
2
MMBT3904_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
3
12
C491
MMBT3904_SOT23
0.1U_0402_16V4Z
2
+CPU_CORE
12
R485
470_0402_5%
R60
330_0402_5%
1
Q39
2
1 2
3
Title
Size Document Number Rev
Custom
Date: Sheet of
H_THERMTRIP#
*01
CPU Decoupli n g
LA-2101
H_THERMTRIP# 5
1
652Saturday, November 22, 2003
0.1
Page 7
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
D D
H_ADSTB#05
C C
H_ADSTB#15
H_ADS#4
H_BNR#4
H_BPRI#4
H_DEFER#4
H_DRDY#5
H_DBSY#5
H_BR0#4
H_LOCK#4
H_RESET#5
H_RS#25
NB_SUS_STAT#25
NB_RST#17,24
NB_PWRGD9,27
1 2
1 2
L13
1 2
H_RS#15
H_RS#05
H_TRDY#5
H_HIT#4
H_HITM#4
1U_0603_10V4Z
0.1U_0402_10V6K
C724
12
R613
1 2
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+CPU_CORE
PLACE CLOSE TO U27 Ball
1 2
12
1
2
W28, USE 20/20
WIDTH/SPACE
C378
1U_0603_10V4Z
1
2
C363 CLOSE
TO Ball W28
C339
220P_0402_50V7K
B B
R292
49.9_0402_1%
R303
100_0402_1%
330_0402_5%
+CPU_CORE
+1.8VS
R308 24.9_0402_1%
R309 49.9_0402_1%
HB-1M2012-121JT03_0805
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
NB_SUS_STAT#
COMP_N
COMP_P
CPVDD
C282
CPVSS
1 2
NB_GTLREF
12
R232
4.7K_0402_5%
U46A
M28
CPU_A3#
P25
CPU_A4#
M25
CPU_A5#
N29
CPU_A6#
N30
CPU_A7#
M26
CPU_A8#
N28
CPU_A9#
P29
CPU_A10#
P26
CPU_A11#
R29
CPU_A12#
P30
CPU_A13#
P28
CPU_A14#
N26
CPU_A15#
N27
CPU_A16#
M29
CPU_REQ0#
N25
CPU_REQ1#
R26
CPU_REQ2#
L28
CPU_REQ3#
L29
CPU_REQ4#
R27
CPU_ADSTB0#
U30
CPU_A17#
T30
CPU_A18#
R28
CPU_A19#
R25
CPU_A20#
U25
CPU_A21#
T28
CPU_A22#
V29
CPU_A23#
T26
CPU_A24#
U29
CPU_A25#
U26
CPU_A26#
V26
CPU_A27#
T25
CPU_A28#
V25
CPU_A29#
U27
CPU_A30#
U28
CPU_A31#
T29
CPU_ADSTB1#
L27
CPU_ADS#
K25
CPU_BNR#
H26
CPU_BPRI#
J27
CPU_DEFER#
L26
CPU_DRDY#
G27
CPU_DBSY#
F25
CPU_BR0#
K26
CPU_LOCK#
A17
CPU_CPURSET#
G25
CPU_RS2#
G26
CPU_RS1#
J25
CPU_RS0#
F26
CPU_TRDY#
J26
CPU_HIT#
H25
CPU_HITM#
A9
CPU_RSET
AH5
SUS_STAT#
AG5
SYSRESET#
C7
POWERGOOD
V28
CPU_COMP_N
W29
CPU_COMP_P
H23
CPVDD
J23
CPVSS
W28
CPU_VREF
Y29
THERMALDIODE_N
Y28
THERMALDIODE_P
B17
TESTMODE
CHS-216IGP9050A21_BGA718
PART 1
OF 6
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_DSTBN0#
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
CPU_DSTBN1#
AGTL+ I/F
PENTIUM
CPU_DSTBN2#
MISC.
CPU_DSTBN3#
H_A#[3..31] 4
H_REQ#[0..4] 4
H_D#[0..63] 4
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBP0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_DSTBP1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
IV
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_DSTBP2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_DSTBP3#
L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29
B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27
F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22
B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_DINV#0 5
H_DSTBN#0 5
H_DSTBP#0 5
H_DINV#1 5
H_DSTBN#1 5
H_DSTBP#1 5
H_DINV#2 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#3 5
H_DSTBN#3 5
H_DSTBP#3 5
+CPU_CORE
C303
A A
5
4
22U_1206_10V4Z
0.1U_0402_10V6K
1
1
2
C306
C307
2
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
1
C305
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C280
2
1
1
C304
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C265
2
1
C248
2
0.1U_0402_10V6K
1
C257
0.1U_0402_10V6K
2
2
Title
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-AGTL+
LA-2101
1
752Saturday, November 22, 2003
of
0.1
Page 8
5
D D
DDR_SBS013,14
DDR_SBS113,14
DDR_SMA1513,14
DDR_SRAS#13,14
DDR_SCAS#13,14
DDR_SWE#13,14
C C
DDR_CLK013
DDR_CLK0#13
DDR_CLK113
DDR_CLK1#13
DDR_CLK314
DDR_CLK3#14
DDR_CLK414
DDR_CLK4#14
DDR_SCKE013,14
DDR_SCKE113,14
DDR_SCKE214
DDR_SCKE314
DDR_SCS#013,14
DDR_SCS#113,14
DDR_SCS#214
B B
+1.8VS
DDR_SCS#314
L10
1 2
HB-1M2012-121JT03_0805
4
U46B
DDR_SMA0
DDR_SMA1
DDR_SMA2 DDR_DQ2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM7
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_SCKE0
DDR_SCKE1
DDR_SCKE2
DDR_SCKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
MPVDD
C229
MPVSS
1 2
1U_0603_10V4Z
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
AH7
AJ8
AF9
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
CHS-216IGP9050A21_BGA718
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM I/F
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
3
DDR_DQ0
AG6
DDR_DQ1
AJ7
AJ9
DDR_DQ3
AJ10
DDR_DQ4
AJ6
DDR_DQ5
AH6
DDR_DQ6
AH8
DDR_DQ7
AH9
DDR_DQ8
AE7
DDR_DQ9
AE8
DDR_DQ10
AE12
DDR_DQ11
AF12
DDR_DQ12
AF7
DDR_DQ13
AF8
DDR_DQ14
AE11
DDR_DQ15
AF11
DDR_DQ16
AJ12
DDR_DQ17
AH12
DDR_DQ18
AH14
DDR_DQ19
AH15
DDR_DQ20
AH11
DDR_DQ21
AJ13
DDR_DQ22
AJ15
DDR_DQ23DDR_DM6
AJ16
DDR_DQ24
AF18
DDR_DQ25
AG20
DDR_DQ26
AG21
DDR_DQ27
AF22
DDR_DQ28
AF19
DDR_DQ29
AF20
DDR_DQ30
AE22
DDR_DQ31
AF23
DDR_DQ32
AJ21
DDR_DQ33
AJ22
DDR_DQ34
AJ24
DDR_DQ35
AK25
DDR_DQ36
AH21
DDR_DQ37
AH22
DDR_DQ38
AH24
DDR_DQ39
AJ25
DDR_DQ40
AK26
DDR_DQ41
AK27
DDR_DQ42
AJ28
DDR_DQ43
AH29
DDR_DQ44
AH25
DDR_DQ45
AJ26
DDR_DQ46
AJ29
DDR_DQ47
AH30
DDR_DQ48
AF29
DDR_DQ49
AE29
DDR_DQ50
AB28
DDR_DQ51
AA28
DDR_DQ52
AE28
DDR_DQ53
AD28
DDR_DQ54
AC29
DDR_DQ55
AB29
DDR_DQ56
AC26
DDR_DQ57
AB25
DDR_DQ58
Y26
DDR_DQ59
W26
DDR_DQ60
AE26
DDR_DQ61
AD26
DDR_DQ62
AA26
DDR_DQ63
Y27
C164 0.47U_0603_16V7K
AF6
1 2
C379 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
R243 49.9_0402_1%
1 2
DDR_DM[0..7]
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_SMA[0..12]
2
DDR_DM[0..7] 13,14
DDR_DQ[0..63] 13,14
DDR_DQS[0..7] 13,14
DDR_SMA[0..12] 13,14
1
+2.5V+2.5V
2
C748
0.1U_0402_10V6K
0.1U_0402_10V6K
A A
5
4
L
1
DDR_VREF
2
C744
1
DDR_VREF trace width of
20mils and space
20mils(min)
12
R647
1K_0603_1%
12
R636
1K_0603_1%
3
Title
Size Document Number Rev
2
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-DDR I/F
LA-2101
1
852Saturday, November 22, 2003
0.1
of
Page 9
5
4
3
2
1
A_AD[0..31]12,24
A_CBE#[0..3]24
D D
C C
?
B B
A_PAR12,24
A_STROBE#24
A_ACAT#24
A_END#24
PCI_PIRQA#17,24,29,32
+1.5VS
A_DEVSEL#24
A_SBREQ#24
A_SBGNT#24
AGP_GNT#17
AGP_REQ#17
R589
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
1 2
+3VS
1 2
169_0402_1%
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
1 2
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
AGP_COMP
R174 0_0402_5%
A_OFF#24
POP For 150G
DEPOP For 150A
AGP8X_DET#
12
R188
10K_0402_5%
U46C
AK5
ALINK_AD0
AJ5
ALINK_AD1
AJ4
ALINK_AD2
AH4
ALINK_AD3
AJ3
ALINK_AD4
AJ2
ALINK_AD5
AH2
ALINK_AD6
AH1
ALINK_AD7
AG2
ALINK_AD8
AG1
ALINK_AD9
AG3
ALINK_AD10
AF3
ALINK_AD11
AF1
ALINK_AD12
AF2
ALINK_AD13
AF4
ALINK_AD14
AE3
ALINK_AD15
AE4
ALINK_AD16
AE5
ALINK_AD17
AE6
ALINK_AD18
AC2
ALINK_AD19
AC4
ALINK_AD20
AB3
ALINK_AD21
AB2
ALINK_AD22
AB5
ALINK_AD23
AB6
ALINK_AD24
AA2
ALINK_AD25
AA4
ALINK_AD26
AA5
ALINK_AD27
AA6
ALINK_AD28
Y3
ALINK_AD29
Y5
ALINK_AD30
Y6
ALINK_AD31
AG4
ALINK_CBE#0
AE2
ALINK_CBE#1
AC3
ALINK_CBE#2
AA3
ALINK_CBE#3
AD5
PCI_PAR/ALINK_NC
AC6
PCI_FRAME#/ALINK_STROBE#
AC5
PCI_IRDY#/ALINK_ACAT#
AD2
PCI_TRDY#/ALINK_END#
W4
INTA#
AD3
ALINK_DEVSEL#
AD6
PCI_STOP#/ALINK_OFF#
W5
ALINK_SBREQ#
W6
ALINK_SBGNT#
R196
V5
PCI_REQ#0/ALINK_NC
V6
PCI_GNT#0/ALINK_NC
K5
AGP2_GNT#/AGP3_GNT
K6
AGP2_REQ#/AGP3_REQ
M5
AGP8X_DET#
J6
AGP_VREF/TMDS_VREF
J5
AGP_COMP
CHS-216IGP9050A21_BGA718
POP For 150G
DEPOP For 150A
PART 3 OF 6
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
PCI Bus 0 / A-Link I/F
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
+1.5VS
12
R588
@1K_0402_1%
+AGP_VREF
AGPREF_8X
12
R153
@1K_0402_1%
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP2_CBE#2/AGP3_CBE2
AGP_PAR
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
AGP_ST0
AGP_ST1
AGP_ST2
POP For 150A
DEPOP For 150G
2
C698
0.1U_0402_10V6K
1
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
E5
E6
T3
U2
G3
H2
R3
M1
L3
H1
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
C3
C2
D4
E4
F6
F5
G6
G5
L6
M6
L5
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF0
AGP_AD_STBS0
AGP_AD_STBF1
AGP_AD_STBS1
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SB_STBF 17
AGP_SB_STBS 17
AGP_AD_STBF0 17
AGP_AD_STBS0 17
AGP_AD_STBF1 17
AGP_AD_STBS1 17
AGP_IRDY# 17
AGP_TRDY# 17
AGP_STOP# 17
AGP_PAR 17
AGP_FRAME# 17
AGP_DEVSEL# 17
AGP_DBI_HI 17
AGP_DBI_LO 17
AGP_RBF# 17
AGP_WBF# 17
AGPAND LVDS MUXED SIGNALS
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA1
AGP_SBA0
R573 @0_0402_5%
1 2
R591 @0_0402_5%
1 2
R590 @0_0402_5%
1 2
R572 @0_0402_5%
1 2
R593 @0_0402_5%
1 2
R592 @0_0402_5%
1 2
ENBKL#
ENVDD 17,23
AGP_STP# 17,25
AGP_BUSY# 17,25
NB_EDID_DAT
1 2
R575 @2.2K_0402_5%
NB_EDID_CLK
1 2
R574 @2.2K_0402_5%
NB_EDID_DAT 23
+3VS
NB_EDID_CLK 23
+3VS
POP For 150A
DEPOP For 150G
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
+3VS
R168
@10K_0402_5%
NB_PWRGD7,27
@2N7002_SOT23
ENBKL#
2
G
Q10
1 2
13
D
S
AGP_AD[0..31] 17
AGP_SBA[0..7] 17
AGP_C/BE#[0..3] 17
AGP_ST[0..2] 17
+3VS
R161
@10K_0402_5%
1 2
13
D
2
G
S
@2N7002_SOT23
R151
1 2
@0_0402_5%
Q8
ENBKL 17,39
POP For 150A
DEPOP For 150G
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK B US
LA-2101
952Saturday, November 22, 2003
1
0.1
of
Page 10
5
4
3
2
1
+2.5VS
12
L45
KC FBM-L11-201209-221LMAT_0805
C745
0.1U_0402_10V6K
1
1
C727
2
2
NB_CRT_R23
NB_CRT_G23
NB_CRT_B23
CRT_HSYNC23
CRT_VSYNC23
1 2
CLK_NB_BCLK16
CLK_NB_BCLK#16
CLK_AGP_66M16
CLK_MEM16
1
C741
0.1U_0402_10V6K
2
1
C726
0.1U_0402_10V6K
2
@10K_0402_5%
PLLVDD_18
PLLVSS_18
CRT_HSYNC
CRT_VSYNC
NB_RSET
RC300M_X1
CLK_NB_BCLK
CLK_NB_BCLK#
1 2
1 2
1 2
1 2
CLK_AGP_66M
CLK_MEM
1 2
D D
KC FBM-L11-201209-221LMAT_0805
L11
+1.8VS
REFCLK1_NB16
CLK_AGP_66M
C C
12
R594
@10_0402_5%
C702
@15P_0402_50V8J
CLK_MEM
12
R595
@10_0402_5%
C703
@15P_0402_50V8J
1 2
0.1U_0402_10V6K
L48
+1.8VS
KC FBM-L11-201209-221LMAT_0805
L42
+1.8VS
KC FBM-L11-201209-221LMAT_0805
1 2
R600
1
C261
2
1 2
0.1U_0402_10V6K
1 2
47_0402_5%
10K_0402_5%
1
1
C746
2
2
C729
10U_0805_10V4Z
0.1U_0402_10V6K
R274 715_0402_1%
R599
56_0402_5%
1 2
+3VS
R614
1 2
L43
1 2
FBM-11-160808-121-T_0603
U46D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
R605
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
R607@10K_0402_5%
D8
ALINK_CLK
R611@10K_0402_5%
B2
AGPCLKOUT
R585@10K_0402_5%
B3
AGPCLKIN
A3
EXT_MEM_CLK
R609@10K_0402_5%
D7
USBCLK
B7
REF27
C5
OSC
CHS-216IGP9050A21_BGA718
R602
@10K_0402_5%
1 2
+3VS
1
C723
0.1U_0402_10V6K
2
PART 4 OF 6
LVDS
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
@10K_0402_5%
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
TV_CRMA
E15
C_R
TV_LUMA
C15
Y_G
TV_COMPS
D15
3VDDCCL
D6
3VDDCDA
C6
D5
A8
B8
R204
1 2
TXB0-_NB 23
TXB0+_NB 23
TXB1-_NB 23
TXB1+_NB 23
TXB2-_NB 23
TXB2+_NB 23
TXBCLK-_NB 23
TXBCLK+_NB 23
TXA0-_NB 23
TXA0+_NB 23
TXA1-_NB 23
TXA1+_NB 23
TXA2-_NB 23
TXA2+_NB 23
TXACLK-_NB 23
TXACLK+_NB 23
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
TV_CRMA 23
TV_LUMA 23
1 2
R242 75_0603_1%
3VDDCCL 23
3VDDCDA 23
R603 1K_0402_5%
R192
@10K_0402_5%
1 2
1
C735
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C225
2
0.1U_0402_10V6K
+3VS
KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
1
C731
C734
2
10U_0805_10V4Z
1
C215
C224
2
10U_0805_10V4Z
1 2
L44
1
2
KC FBM-L11-201209-221LMAT_0805
1 2
L12
1
2
+1.8VS
+1.8VS
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-2101
1
10 52Saturday, November 22, 2003
0.1
of
Page 11
5
4
3
2
1
+1.5VS +2.5V
D D
C C
B B
+CPU_CORE
+3VS
U46E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
CHS-216IGP9050A21_BGA718
CORE PWR
CPU I/F PWRALINK PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
PART 5
OF 6
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR MEM I/F PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
POP For 150G
DEPOP For 150A
R608 0_0603_5%
1 2
1 2
R610 @0_0603_5%
+1.8VS
POP For 150A
+1.5VS
+3VS
DEPOP For 150G
C790
100U_D2_6.3VM
0.1U_0402_10V6K
1
C202
2
+2.5V
1
2
C214
0.1U_0402_10V6K
+1.5VS
C137
47U_B_6.3VM
+1.5VS
A A
C279
47U_B_6.3VM
1
+
C163
2
0.1U_0402_10V6K
1
+
C182
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C156
2
0.1U_0402_10V6K
1
C181
2
1
C142
2
0.1U_0402_10V6K
1
C262
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C155
2
1
2
0.1U_0402_10V6K
1
2
1
C169
2
0.1U_0402_10V6K
1
C249
C256
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C151
2
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C168
2
0.1U_0402_10V6K
C255
C240
0.1U_0402_10V6K
1
C154
2
1
1
C239
2
2
0.1U_0402_10V6K
1
C183
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C200
2
1
C209
2
0.1U_0402_10V6K
U46F
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7 J8
VSS VSS
CHS-216IGP9050A21_BGA718
10U_0805_10V4Z
0.1U_0402_10V6K
1
+
C258
C252
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C201
2
2
PART 6 OF 6
GND
+1.8VS
1
C263
2
1
C241
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C212
C213
2
0.1U_0402_10V6K
R23
VSS
R7
VSS
R8
VSS
T12
VSS
T13
VSS
T14
VSS
T15
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T27
VSS
T4
VSS
U15
VSS
U16
VSS
U7
VSS
U8
VSS
V15
VSS
V16
VSS
V27
VSS
V4
VSS
V7
VSS
V8
VSS
W15
VSS
W16
VSS
W27
VSS
Y1
VSS
Y23
VSS
Y24
VSS
Y30
VSS
Y4
VSS
Y7
VSS
Y8
VSS
R19
VSS
R18
VSS
R17
VSS
R16
VSS
R15
VSS
R14
VSS
R13
VSS
R12
VSS
R1
VSS
P4
VSS
P27
VSS
P16
VSS
P15
VSS
N8
VSS
N24
VSS
N23
VSS
N16
VSS
N15
VSS
M4
VSS
M27
VSS
M16
VSS
M15
VSS
L8
VSS
L7
VSS
L25
VSS
L24
VSS
L23
VSS
K4
VSS
K27
VSS
0.1U_0402_10V6K
1
C288
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C216
2
2
1
C199
2
0.1U_0402_10V6K
1
C184
C186
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C203
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C211
2
1
2
1
C247
2
1
C198
2
0.1U_0402_10V6K
1
C289
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C204
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C254
2
C130
10U_0805_10V4Z
1
C352
C180
2
0.1U_0402_10V6K
1
1
C238
2
2
0.1U_0402_10V6K
+3VS
1
C178
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C353
2
0.1U_0402_10V6K
1
C253
C237
2
0.01U_0402_16V7Z
0.1U_0402_10V6K
1
C179
2
1
C329
2
0.1U_0402_10V6K
0.01U_0402_16V7Z
1
2
1
C170
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C330
2
1
C230
2
0.1U_0402_10V6K
1
C172
2
1
2
12
C271
4.7U_0805_10V4Z
1
C171
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C317
C354
0.1U_0402_10V6K
2
12
C707
4.7U_0805_10V4Z
0.1U_0402_10V6K
1
C140
2
1
C308
2
0.1U_0402_10V6K
1
C141
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C293
2
0.1U_0402_10V6K
1
2
1
C322
2
0.1U_0402_10V6K
1
C150
2
0.1U_0402_10V6K
1
C309
2
1
1
2
2
0.1U_0402_10V6K
C272
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-PO WE R
LA-2101
1
11 52Tuesday, November 18, 2003
0.1
of
Page 12
5
4
3
2
1
A_AD[0..31]9,24
R142 10K_0402_5%
A_AD31
D D
C C
B B
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
R163 4.7K_0402_5%
R587 4.7K_0402_5%
R147 10K_0402_5%
1 2
R158 @4.7K_0402_5%
R568 @10K_0402_5%
1 2
R584 4.7K_0402_5%
R144 10K_0402_5%
1 2
R155 @4.7K_0402_5%
R143 10K_0402_5%
1 2
R154 @4.7K_0402_5%
R565 10K_0402_5%
1 2
R582 @4.7K_0402_5%
R566 10K_0402_5%
1 2
R567 10K_0402_5%
1 2
R583 @4.7K_0402_5%
R145 10K_0402_5%
1 2
R156 @4.7K_0402_5%
R146 10K_0402_5%
1 2
R157 @4.7K_0402_5%
R564 @4.7K_0402_5%
R581 4.7K_0402_5%
1 2
R569 10K_0402_5%
1 2
D22
2 1
CH751H-40_SC76
D59
2 1
CH751H-40_SC76
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 5,16
+3VS
BSEL0 5,16
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcShortReset#
DEFAULT: 1
0: TEST MOD E
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0: PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTE RNAL CLK GE N E NABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
R149 @4.7K_0402_5%
A_AD18
A_AD17
A_PAR9,24
R160 4.7K_0402_5%
R563 @4.7K_0402_5%
R580 4.7K_0402_5%
A_PAR
R159 @4.7K_0402_5%
R148 4.7K_0402_5%
+3VS
+3VS
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
+3VS
0: DEBUG MODE
1: NORMAL
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI RC300M-SYSTEM ST RA P
LA-2101
12 52Saturday, November 22, 2003
1
0.1
of
Page 13
A
1 1
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMA[0..12]
2 2
DDR_SCKE18,14
DDR_SBS08,14
DDR_SWE#8,14
DDR_SCS#08,14
DDR_SMA158,14
3 3
4 4
A
DDR_DQ[0..63] 8,14
DDR_DQS[0..7] 8,14
DDR_DM[0..7] 8,14
DDR_SMA[0..12] 8,14
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SMA15
RP21
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP24
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP28
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
Layout note
B
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_CLK08
DDR_CLK0#8
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
DDR_CKE1
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_BS0
DDR_WE#
DDR_CS#0 DDR_CS#1
DDR_SMAA15
DDR_DQ33
DDR_DQ37
DDR_DQS4 DDR_DM4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
SMDATA14,16,25
SMCLK14,16,25
B
+3VS
C
+2.5V +2.5V +2.5V
JP24
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5747-3-111
Layout note
Place Add/Command resisotrs
Close to Pin, max L = 300 mils
C
DU/RESET#
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
VSS
DM8
VDD
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CB4
74
CB5
76
78
80
CB6
82
84
CB7
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
CK1
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_CKE0
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4
DDR_SMAA2
DDR_SMAA0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_DQ32
DDR_DQ36
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_CLK1# 8
DDR_DQ48
DDR_DQ52
DDR_DM6DDR_DQS6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
D
DDR_CLK1 8
E
C105
0.1U_0402_10V6K
C101
0.1U_0402_10V6K
DDRA_VREF trace width of
L
20mils and space 20mils(min)
10_0804_8P4R_5%
10_0804_8P4R_5%
10_0804_8P4R_5%
E
RP20
RP25
RP29
2
1
DDRA_VREF
2
1
18
27
36
45
18
27
36
45
18
27
36
45
12
R133
1K_0603_1%
12
R132
1K_0603_1%
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
F
DDR_SCKE0 8,14
DDR_SBS1 8,14
DDR_SRAS# 8,14
DDR_SCAS# 8,14
DDR_SCS#1 8,14
F
G
Title
Size Document Number Rev
Date: Sheet
G
Comp a l Electro nics , In c .
DDR-SODIMM SLOT0
LA-2101
H
13 52Saturday, November 22, 2003
of
H
0.1
Page 14
A
+1.25VS
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
1 1
2 2
3 3
4 4
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
DDR_SCKE08,13
DDR_SCKE18,13
DDR_SCS#18,13
DDR_SCS#08,13
DDR_SCKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#2
DDR_SMA15
RP6
56_0804_8P4R_5%
RP8
56_0804_8P4R_5%
RP10
56_0804_8P4R_5%
RP12
56_0804_8P4R_5%
RP14
56_0804_8P4R_5%
RP18
33_0804_8P4R_5%
RP23
33_0804_8P4R_5%
RP27
33_0804_8P4R_5%
RP31
33_0804_8P4R_5%
RP5
18
27
36
45
56_0804_8P4R_5%
RP7
18
27
36
45
56_0804_8P4R_5%
RP9
18
27
36
45
56_0804_8P4R_5%
RP11
18
27
36
45
56_0804_8P4R_5%
RP13
18
27
36
45
56_0804_8P4R_5%
18
27
36
45
RP22
18
27
36
45
33_0804_8P4R_5%
RP26
18
27
36
45
33_0804_8P4R_5%
RP30
18
27
36
45
33_0804_8P4R_5%
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_SCS#28 DDR_SCS#3 8
DDR_SCKE2
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3
B
+2.5V
DDR_DQ1
DDR_DQ4
DDR_DQS0
DDR_DQ3
DDR_DQ2
DDR_DQ13
DDR_DQ15
DDR_DQS1
DDR_DQ14
DDR_DQ10
DDR_CLK38
DDR_CLK3#8
DDR_DQ17
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ29
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
*27 *27
R267
1 2
10_0402_5%
DDR_SBS08,13
DDR_SCS#2 DDR_CS#2 DDR_SCS#3
1 2
10_0402_5%
R291
DDR_SWE#8,13
DDR_SMA158,13
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
SMDATA13,16,25
SMCLK13,16,25
DDR_CKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0 DDR_SRAS#
DDR_SWE#
DDR_SMA15
DDR_DQ33
DDR_DQ37
DDR_DQS4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
+3VS
C
JP23
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5763-3-111
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
VSS
DM8
VDD
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
D
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CB4
74
CB5
76
78
80
CB6
82
84
CB7
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
CK1
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ0
DDR_DQ6
DDR_DM0
DDR_DQ5
DDR_DQ7
DDR_DQ12
DDR_DQ8
DDR_DM1
DDR_DQ9
DDR_DQ11
DDR_DQ20
DDR_DQ16
DDR_DM2
DDR_DQ22
DDR_DQ19
DDR_DQ24
DDR_DQ28
DDR_DM3
DDR_DQ26
DDR_DQ27
DDR_CKE2 DDR_SCKE2DDR_SCKE3
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SCAS#
DDR_CS#3
DDR_DM4
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ46
DDR_DM6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
10_0402_5%
DDR_DQ32
DDR_DQ36
DDR_DQ42
DDR_DQ48
DDR_DQ52
+3VS
R226
DDR_SBS1 8,13
DDR_SRAS# 8,13
DDR_SCAS# 8,13
R28810_0402_5%
DDR_CLK4# 8
DDR_CLK4 8
Layout note
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
DDRB_VREF trace width of
L
20mils and space
20mils(min)
12
12
*27
2
C690
0.1U_0402_10V6K
1
DDRB_VREF
2
C692
0.1U_0402_10V6K
1
DDR_DQ33
DDR_DQ37
DDR_DQS4
DDR_DQ39
DDR_DQ35
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ58
DDR_SCKE2 8DDR_SCKE38
+2.5V+2.5V
12
R556
1K_0603_1%
12
R561
1K_0603_1%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
DDR_SMA[0..12]
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
RP34
RP36
RP38
RP41
RP43
+1.25VS
RP33
18
27
36
45
56_0804_8P4R_5%
RP35
18
27
36
45
56_0804_8P4R_5%
RP37
18
27
36
45
56_0804_8P4R_5%
RP40
18
27
36
45
56_0804_8P4R_5%
RP42
18
27
36
45
56_0804_8P4R_5%
E
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
DDR_SMA[0..12] 8,13
DDR_DQS[0..7] 8,13
DDR_DQ[0..63] 8,13
DDR_DM[0..7] 8,13
DDR_DQ32
DDR_DQ36
DDR_DM4
DDR_DQ38
DDR_DQ34
DDR_DQ44
DDR_DQ40
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ52
DDR_DM6
DDR_DQ54
DDR_DQ50
DDR_DQ61
DDR_DQ60
DDR_DM7
DDR_DQ57
DDR_DQ59
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
DDR-SODIMM SLOT1
LA-2101
14 52Saturday, November 22, 2003
E
0.1
of
Page 15
A
Layout note :
Distribute as close as possible
to DDR-SODIMM0.
+2.5V
B
C
D
E
Layout note :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V
1
2
1
C242
0.1U_0402_10V6K
2
1
C737
0.1U_0402_10V6K
2
1
C91
2
1000P_0402_50V7K
1
2
1
2
1000P_0402_50V7K
1
C90
2
1000P_0402_50V7K
C267
0.1U_0402_10V6K
C742
0.1U_0402_10V6K
1
C133
2
1
C463
0.1U_0402_10V6K
2
1
C770
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C268
2
1000P_0402_50V7K
1
2
1
2
C390
C812
0.1U_0402_10V6K
C781
0.1U_0402_10V6K
1000P_0402_50V7K
1
2
1 1
1
+
C798
220U_D2_4VM
2
1
C424
0.1U_0402_10V6K
2
1
+
C686
220U_D2_4VM
2
1
C124
0.1U_0402_10V6K
2
1
C128
0.1U_0402_10V6K
2
1
+
C685
220U_D2_4VM
2
1
C136
0.1U_0402_10V6K
2
1
C135
0.1U_0402_10V6K
2
1
C159
0.1U_0402_10V6K
2
1
C158
0.1U_0402_10V6K
2
1
C185
0.1U_0402_10V6K
2
1
C196
0.1U_0402_10V6K
2
1
C206
0.1U_0402_10V6K
2
1
C233
0.1U_0402_10V6K
2
1
C227
0.1U_0402_10V6K
2
1
C357
0.1U_0402_10V6K
2
1
C358
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C388
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
+
C797
220U_D2_4VM
2
1
C725
0.1U_0402_10V6K
2
Layout note :
for EMI solution
1
C207
0.1U_0402_10V6K
2
1
C730
0.1U_0402_10V6K
2
+2.5V
Layout note :
Place one cap close to every 2 pull up resistors termination to
2 2
+1.25VS
1
C104
0.1U_0402_10V6K
2
+1.25VS
1
C143
0.1U_0402_10V6K
2
+1.25VS
1
C243
0.1U_0402_10V6K
3 3
2
+1.25VS
1
C110
0.1U_0402_10V6K
2
1
C148
0.1U_0402_10V6K
2
1
C251
0.1U_0402_10V6K
2
1
C103
0.1U_0402_10V6K
2
1
C166
0.1U_0402_10V6K
2
1
C284
0.1U_0402_10V6K
2
1
C109
0.1U_0402_10V6K
2
1
C176
0.1U_0402_10V6K
2
1
C292
0.1U_0402_10V6K
2
1
C116
0.1U_0402_10V6K
2
1
C165
0.1U_0402_10V6K
2
1
C283
0.1U_0402_10V6K
2
1
C127
0.1U_0402_10V6K
2
1
C175
0.1U_0402_10V6K
2
1
C291
0.1U_0402_10V6K
2
1
C115
0.1U_0402_10V6K
2
1
C188
0.1U_0402_10V6K
2
1
C126
0.1U_0402_10V6K
2
1
C195
0.1U_0402_10V6K
2
1
C144
0.1U_0402_10V6K
2
1
C187
0.1U_0402_10V6K
2
1
C149
0.1U_0402_10V6K
2
1
C194
0.1U_0402_10V6K
2
C92
1000P_0402_50V7K
1
C450
2
1000P_0402_50V7K
1
C704
0.1U_0402_10V6K
2
1
C792
0.1U_0402_10V6K
2
1
C462
2
1
C711
0.1U_0402_10V6K
2
1
C795
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C461
2
1
C722
0.1U_0402_10V6K
2
1
C807
0.1U_0402_10V6K
2
+1.25VS
1
C314
0.1U_0402_10V6K
2
+1.25VS
1
C363
0.1U_0402_10V6K
2
+1.25VS
4 4
1
C442
0.1U_0402_10V6K
2
1
C321
0.1U_0402_10V6K
2
1
C370
0.1U_0402_10V6K
2
1
C446
0.1U_0402_10V6K
2
A
1
C313
0.1U_0402_10V6K
2
1
C387
0.1U_0402_10V6K
2
1
C441
0.1U_0402_10V6K
2
1
C320
0.1U_0402_10V6K
2
1
C401
0.1U_0402_10V6K
2
1
C445
0.1U_0402_10V6K
2
1
C337
0.1U_0402_10V6K
2
1
C386
0.1U_0402_10V6K
2
1
C457
0.1U_0402_10V6K
2
1
C347
0.1U_0402_10V6K
2
1
C400
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
B
1
C336
0.1U_0402_10V6K
2
1
C420
0.1U_0402_10V6K
2
1
C346
0.1U_0402_10V6K
2
1
C431
0.1U_0402_10V6K
2
1
C364
0.1U_0402_10V6K
2
1
C419
0.1U_0402_10V6K
2
1
C371
0.1U_0402_10V6K
2
1
C430
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
DDR SODIMM Decoupling
LA-2101
E
15 52Tuesday, November 18, 2003
of
0.1
Page 16
A
B
C
D
E
F
G
H
L14
1 2
U18
6
XIN
7
XOUT
35
SCLK
34
SDATA
10
VTTPWRGD/PD#
45
CPU_STP#
12
PCI_STOP#
26
24/48#SEL
11
PCI33/66#SEL
48MHz_1
28
48MHz_0
4
FS2/REF2
3
FS1/REF1
2
FS0/REF0
38
IREF
+3V_CLK
42
8
Width=40 mils
C310
10U_0805_10V4Z
13
48
303129
VDDSD
VDDPCI
VDD48M
VDDCPU
VDDAGP
GNDREF
GNDXTAL
GNDPCI
GNDPCI
GND48M
5
181924
252733
0.1U_0402_10V6K
1
C290
2
+3VS_VDDA
1
9
VDDA
VDDPCI
VDDREF
VDDXTAL
VSSA
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDSD
GNDAGP
GNDCPU
ICS951402AGT_TSSOP48
46
41
1
C274
2
0.1U_0402_10V6K
36
C275
0.1U_0402_10V6K
VSSA
37
CLK_CPU_CLK
40
CLK_CPU_CLK#
39
44
43
47
32
14
15
16
17
20
21
22
23
0.1U_0402_10V6K
1
C276
2
1
2
CLK_NB
CLK_NB#
MEM_66M
AGP_66M
AGP_EXT_66M
FS3
FS4
1
2
C366
10U_0805_10V4Z
1
C392
2
0.1U_0402_10V6K
+3VS_VDDA
1
2
R265 33_0402_5%
R266 33_0402_5%
R263 33_0402_5%
R264 33_0402_5%
R262 33_0402_5%
R239 33_0402_5%
R240 33_0402_5%
R332 33_0402_5%
0.1U_0402_10V6K
1
C277
0.1U_0402_10V6K
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
POP For 150G
DEPOP For 150A
1
C773
2
0.1U_0402_10V6K
L15
1 2
CHB2012U121_0805
1
1
C391
C380
0.1U_0402_10V6K
2
2
CLK_BCLK
R235 49.9_0402_1%
1 2
R236 49.9_0402_1%
1 2
CLK_BCLK#
R237 49.9_0402_1%
1 2
R238 49.9_0402_1%
1 2
+3VS
CLK_BCLK 4
CLK_BCLK# 4
CLK_NB_BCLK 10
CLK_NB_BCLK# 10
CLK_MEM 10
CLK_AGP_66M 10
CLK_AGP_EXT_66M 1 7
CLK_ALINK_SB 24
+3VS
HB-1M2012-121JT03_0805
1 1
R363 @10_0402_5%
SYS_XCLK36
+3VS
12
12
R228
R343
10K_0402_5%
2 2
10K_0402_5%
R256 10K_0402_5%
R255 @10K_0402_5%
SD_CLKIN29
REFCLK1_NB10
CLK_14M_SIO36
CLK_SB_14M25
R254 33_0402_5%
R658 20_0402_5%
R663 33_0402_5%
R664 33_0402_5%
1 2
C410 10P_0402_50V8K
1 2
12
Y1
XTALOUT_CLK
1 2
C411
14.31818MHZ_20P_6X1430004201
10P_0402_50V8K
SMCLK13,14,25
SMDATA13,14,25
VTT_PWRGD25,27
1 2
1 2
1 2
1 2
1 2
1 2
XTALIN_CLK
12
VTT_PWRGD
PCI33/66#
CLK_48M
FS2
FS1
FS0
CLK_IREF
R253
475_0402_1%
1 2
R321
@1M_0402_5%
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
3 3
4 4
A
0 0 0 1 0
0 0 0 0 1
**
0 0 0 0 0
Note: 0 = PULL LOW
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
BSEL15,12
BSEL05,12
133
10K_0402_5%
*
Spreaf OFF OR
Center spr e a d +/-0. 3 %
+3VS +3VS
12
12
R362
R357
10K_0402_5%
C
D47 CH751H-40_SC76
D46 CH751H-40_SC76
133
100 100
B
A-LINK FREQ
PCI33/66# = HIGH
**
PCI33/66# = LOW 33MHZ
10K_0402_5%
21
21
R342
+3V_CLK
12
66MHZ
12
R341
10K_0402_5%
D
FS1
FS0
FS2
FS3
FS4
PCI33/66#
12
R314
4.7K_0402_5%
+3V_CLK
12
12
12
R313
4.7K_0402_5%
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
E
R315
@10K_0402_5%
R329
10K_0402_5%
12
@10K_0402_5%
12
R316
R331
10K_0402_5%
12
@10K_0402_5%
12
R317
R333
10K_0402_5%
12
R327
10K_0402_5%
12
R330
@10K_0402_5%
F
Title
Size Document Number Rev
Date: Sheet
G
Compal Electronics, Inc.
Clock Generator
LA-2101
16 52Saturday, November 22, 2003
H
of
0.1
Page 17
5
4
3
2
1
AGP_AD[0..31]9
AGP_SBA[0..7]9
D D
C C
B B
A A
AGP_C/BE#[0..3]9
AGP_ST[0..2]9
R496 @10K_0402_5%
+1.5VS
R495 @10K_0402_5%
Pull High for AGP 4X
CLK_AGP_EXT_66M16
NB_RST#7,24
+1.5VS
+1.5VS
R510
324_0402_1%
1 2
+AGP_VREF
R506
100_0402_1%
1 2
AGP_SUS_STAT#25
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
12
12
C537
1 2
@10P_0402_50V8K
1 2
R488
10_0402_5%
AGP_SB_STBF9
AGP_SB_STBS9
R508
47_0402_5%
(15mil)
1 2
AGP_DBI_HI9
AGP_DBI_LO9
AGP8X_DET#
HIGH:
AGP2.0
*27 *27
R13
10K_0402_5%
AGP_DBI_HI
AGP_DBI_LO
R477
1 2
@10_0402_5%
AGP_REQ#9
AGP_GNT#9
AGP_PAR9
AGP_STOP#9
AGP_DEVSEL#9
AGP_TRDY#9
AGP_IRDY#9
AGP_FRAME#9
PCI_PIRQA#9,24,29,32
AGP_WBF#9
AGP_STP#9,25
AGP_BUSY#9,25
AGP_RBF#9
AGP_AD_STBF09
AGP_AD_STBF19
AGP_AD_STBS09
AGP_AD_STBS19
R492 10K_0402_5%
+3VS
R494 @10K_0402_5%
(15mil)
CRMA23
LUMA23
75_0402_1%
R14
10K_0402_5%
1 2
1 2
R12 1K_0402_5%
AGP_SUS_STAT#
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
CLK_AGP_EXT_66M
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
PCI_PIRQA#
AGP_WBF#
STP_AGP#
AGP_BUSY#
AGP_RBF#
AGP_AD_STBF0
AGP_AD_STBF1
AGP_AD_STBS0
AGP_AD_STBS1
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SB_STBF
AGP_SB_STBS
C603 0.1U_0402_10V6K
1 2
+AGP_VREF
AGP_DBI_HI
AGP_DBI_LO
12
12
R15
715_0402_1%
1 2
CRMA
LUMA
COMPS
12
R30
SSIN
SSOUT
XTALIN
1 2
R470
1 2
0_0402_5%
U3A
H29
AD0
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AH30
STP_AGP#
AH29
AGP_BUSY#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
M29
AD_STBS_0
V26
AD_STBS_1
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB29
SB_STBF
AB28
SB_STBS
M26
AGPREF
M27
AGPTEST
AB25
DBI_HI
AB26
DBI_LO
AC25
AGP8X_DET#
AE11
DMINUS
AF11
DPLUS
AK21
R2SET
AJ23
C_R
AJ22
Y_G
AK22
COMP_B
AJ24
H2SYNC
AK24
V2SYNC
AG23
DDC3CLK
AG24
DDC3DATA
AK25
SSIN
AJ25
SSOUT
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
AG26
SUS_STAT#
SA002160E00(0301021300)
M10-P/(M9+X)
(1/6)
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV PORT / EXT TMDS / GPIO /
ROM
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
PCI/AGPAGP8XCLK
LVDSTMDSDAC1
BLON/(BLON#)
THRM
SSC DAC2
TEST_MCLK/(NC)
TEST_YCLK/(NC)
PLLTEST/(NC)
RSTB_MSK/(NC)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
VREFG/(NC)
ROMCS#
DVOMODE
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AG4
AF5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
2.2K_0402_5%
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AE10
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
R463 100K_0402_5%
AF12
AK27
R
AJ27
G
AJ26
B
DACA_HSYNC
AG25
DACA_VSYNC
AH25
AH26
AF25
AF24
AF26
B6
E8
AE25
AG29
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N
VREFG
STRAP_R
STRAP_S
+3VS
R478
1 2
STRAP_T
DVOMODE
1 2
R466 0_0402_5%
TXOUT0-
TXOUT0- 23
TXOUT0+
TXOUT0+ 23
TXOUT1-
TXOUT1- 23
TXOUT1+
TXOUT1+ 23
TXOUT2-
TXOUT2- 23
TXOUT2+
TXOUT2+ 23
TXCLK-
TXCLK- 23
TXCLK+
TXCLK+ 23
TZOUT0-
TZOUT0- 23
TZOUT0+
TZOUT0+ 23
TZOUT1-
TZOUT1- 23
TZOUT1+
TZOUT1+ 23
TZOUT2-
TZOUT2- 23
TZOUT2+
TZOUT2+ 23
TZCLK-
TZCLK- 23
TZCLK+
TZCLK+ 23
ENVDD
ENVDD 9,23
ENBKL
ENBKL 9,39
R
G
B
1 2
R472 499_0402_1%
1 2
1 2
1K_0402_5%
(15mil)
AGP_RSET
DDC_DATA
DDC_CLK
R479 10K_0402_5%
R41
POWER_SEL
XTALIN_SS
R487
2.2K_0402_5%
1 2
R23
G23
B23
DACA_HSYNC 23
DACA_VSYNC 23
DDC_DATA 23
DDC_CLK 23
+3VS
POWER_SEL 49
(25 mil)
EDID_DATA 23
EDID_CLK 23
+3VS
12
12
AGP, DAC & LVDS INTERFACE
ID_Disable
GPIO8
STRAP_A
VGA_Disable
GPIO7
STRAP_B
GPIO4
STRAP_D
GPIO5
X1
4
VDD
1
OE
27MHZ_15P
GPIO6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO9
GPIO11
GPIO12
GPIO13
STRAP_E
STRAP_F
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_O
STRAP_L
STRAP_M
STRAP_N
STRAP_R
STRAP_S
STRAP_T
DRAM128M
3.3V OSC out for W180
OUT
GND
R458
1K_0402_1%
R465
1K_0402_1%
+3VS
VGA_XCLK36
12
R54
10K_0402_5%
1
C28
0.1U_0402_10V6K
2
For VGA DDR spread sprum
+3VS
R105 10K_0402_5%
R106 10K_0402_5%
1
12
12
8
R476 @10K_0402_5%
R22 @10K_0402_5%
R459 @10K_0402_5%
R460 @10K_0402_5%
R23 @10K_0402_5%
R3 10K_0402_5%
R18 @10K_0402_5%
R4 10K_0402_5%
R19 @10K_0402_5%
R6 @10K_0402_5%
R21 @10K_0402_5%
R5 @10K_0402_5%
R20 @10K_0402_5%
R457 @10K_0402_5%
R43 @10K_0402_5%
R53 @10K_0402_5%
R46 @10K_0402_5%
R454 @10K_0402_5%
R461 10K_0402_5%
R16 @10K_0402_5%
R17 10K_0402_5%
R455 @10K_0402_5%
R462 @10K_0402_5%
R468 @10K_0402_5%
R471 10K_0402_5%
R S
0 0
4Mx32 Samsung
0 1
4Mx32 Hynix
1 0
8Mx32 Samsung
1 1
8Mx32 Hynix
*
Ra
FREQOUT
3
1 2
R469 261_0402_1%
2
150_0402_5%
R92 @10_0402_5%
1 2
0.1U_0402_10V6K
1
1
C61
2
2
6
0.1U_0402_10V6K
U2
VDD
CLKOUT
X2FS1
SS%
GND
W180-01GT_SO8
3
5
27
4
SS%
X1/CLK
FS2
R467
Rb
C58
1 2
R486
1 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
0.1U_0402_10V6K
R91
10K_0402_5%
12
C530
@15P_0402_50V8J
FREQOUT
1
C55
2
22_0402_5%
R84 @10K_0402_5%
XTALIN
L4
1 2
1
2.2U_0603_6.3V4Z
C65
FCM2012C-800_0805
2
XTALIN_SSFREQOUT
12
+3VS
+3VS
R484 @10_0402_5%
+3VS
EXT_SSIN
12
EXT_SSIN 36
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
5
4
3
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, In c.
ATI M10-P & M9+X (AGP BU S)
LA-2101
1
17 52Saturday, November 22, 2003
0.1
of
Page 18
5
4
3
2
1
MEMORY
D D
INTERFACE A
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
C C
B B
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
NMDA[0..63]21
NMAA[0..13]21
NDQMA[0..7]21
NDQSA[0..7]21
U3B
M10-P/(M9+X)
DQA0
(2/6)
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
SA002160E00(0301021300)
NMDA[0..63]
NMAA[0..13] NMAB[0..13]
NDQMA[0..7]
NDQSA[0..7]
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
MEMORY
INTERFACE A
AA10
AA11
AA12/(AA13)
AA13/(AA12)
AA14/(NC)
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
DIMA0
DIMA1
MVREFD
MVREFS/(NC)
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
NMAA1
B22
NMAA2
B23
NMAA3
B24
NMAA4
C23
NMAA5
C22
NMAA6
F22
NMAA7
F21
NMAA8
C21
NMAA9
A24
NMAA10
C24
NMAA11
A25
NMAA12
E21
NMAA13
B20
C19
NDQMA0
J25
NDQMA1
F29
NDQMA2
E25
NDQMA3
A27
NDQMA4
F15
NDQMA5
C15
NDQMA6
C11
NDQMA7
E11
NDQSA0
J27
NDQSA1
F30
NDQSA2
F24
NDQSA3
B27
NDQSA4
E16
NDQSA5
B16
NDQSA6
B11
NDQSA7
F10
NMRASA#
A19
NMCASA#
E18
NMWEA#
E19
NMCSA0#
E20
NMCSA1#
F20
NMCKEA
B19
NMCLKA0
B21
NMCLKA0#
C20
NMCLKA1
C18
NMCLKA1#
A18
D30
B13
MVREFD
B7
MVREFS
B8
NMRASA# 21
NMCASA# 21
NMWEA# 21
NMCSA0# 21
NMCSA1# 21
NMCKEA 21
NMCLKA0 21
NMCLKA0# 21
NMCLKA1 21
NMCLKA1# 21
NMAA0
E22
NMDB[0..63]22
NMAB[0..13]22
NDQMB[0..7]22
NDQSB[0..7]22
U3C
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
SA002160E00(0301021300)
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
NMDB[0..63]
NDQMB[0..7]
NDQSB[0..7]
M10-P/(M9+X)
(3/6)
AB12/(AB13)
AB13/(AB12)
MEMORY INTERFACE
B
MEMVMODE0
MEMVMODE1
AB10
AB11
AB14/(NC)
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB0
DIMB1
MEMTEST
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
NMAB1
M1
NMAB2
M3
NMAB3
L3
NMAB4
L2
NMAB5
M2
NMAB6
M5
NMAB7
P6
NMAB8
N3
NMAB9
K2
NMAB10
K3
NMAB11
J2
NMAB12
P5
NMAB13
P3
P2
NDQMB0
E6
NDQMB1
B2
NDQMB2
J5
NDQMB3
G3
NDQMB4
W6
NDQMB5
W2
NDQMB6
AC6
NDQMB7
AD2
NDQSB0
F6
NDQSB1
B3
NDQSB2
K6
NDQSB3
G1
NDQSB4
V5
NDQSB5
W1
NDQSB6
AC5
NDQSB7
AD1
NMRASB#
R2
NMCASB#
T5
NMWEB#
T6
NMCSB0#
R5
NMCSB1#
R6
NMCKEB
R3
NMCLKB0
N1
NMCLKB0#
N2
NMCLKB1
T2
NMCLKB1#
T3
R122 4.7K_0402_5%
1 2
C6
R540 4.7K_0402_5%
1 2
C7
E3
AA3
R532 47_0402_1%
1 2
C8
NMAB0
N5
(15mil)
NMRASB# 22
NMCASB# 22
NMWEB# 22
NMCSB0# 22
NMCSB1# 22
NMCKEB 22
NMCLKB0 22
NMCLKB0# 22
NMCLKB1 22
NMCLKB1# 22
+1.8VS
+2.5VS
12
R543
A A
MVREFD
0.1U_0402_10V6K
C668
5
(25 mil)
1
2
1K_0402_1%
12
R538
1K_0402_1%
MVREFS
0.1U_0402_16V4Z
C669
(25 mil)
1
2
4
+2.5VS
12
12
R544
1K_0402_1%
R539
1K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI M10-P/M9+X DDR-A
LA-2101
1
18 52Saturday, November 22, 2003
of
0.1
Page 19
5
4
3
2
1
POWER INTERFACE
U3D
M10-P/(M9+X)
VDDR1
(4/6)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
TPVDD
TPVSS
AVDD
A2VDD
A2VDD
A2VDDQ
A2VSSN
A2VSSN
A2VSSQ
AVSSN
AVSSQ
VDDRH0
VDDRH1
VSSRH0
VSSRH1
MPVDD
MPVSS
PVDD
PVSS
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
I/O
POWER
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)
LVDDR_18
LVDDR_18
LPVDD
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
VDD1DI
VDD2DI
VSS1DI
VSS2DI
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
+1.5VS
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
+2.5VS
D D
C C
B B
AC11
AC20
AK12
AJ12
AH24
AG21
AH21
AF22
AH22
AJ21
AF23
AH23
AD24
B1
B30
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
D5
D8
D11
D13
D14
D17
D20
D23
D26
E27
F4
G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
T4
T7
T8
V4
V7
V8
D19
R4
H11
H20
L23
P8
Y23
Y8
F18
N6
F19
M6
A7
A6
AK28
AJ28
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
AC10
AC9
AD10
AD9
AG7
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
AE20
AE17
AF21
AE15
AJ20
AF20
AF15
AE19
AE16
AJ19
AE24
AE22
AE23
AE21
AF13
AF14
AG13
AG14
AH12
+2.5VDDRH
+1.5VS
+VDD_MEMPLL1.8
+VDD_PLL1.8
+3VS
+VDD_PNLIO2.5
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_PNLIO1.8
22U_1206_10V4Z
2.2U_0603_6.3V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
POWER Sequence
3.3VS --> 2.5VS --> 1.8VS --> +VGA_Core --> +1.5VS
The differ between +2.5VS and +1.8VS should not be greater th an 1 .2 V
+1.5VS
1
C644
C569
2
0.1U_0402_10V6K
+VDD_DAC2.5
(20 mil)
1
C519
2
+VDD_PNLPLL1.8
(20 mil)
1
C521
C527
2
0.1U_0402_10V6K
+VDD_DAC1.8
(20 mil)
1
C522
2
+VDD_PNLIO1.8
(20 mil)
1
C520
2
+VDD_PNLIO2.5
(20 mil)
1
C561
2
0.1U_0402_10V6K
1
C598
2
1 2
CHB1608U301_0603
1
C528
0.1U_0402_10V6K
2
1
2
1 2
CHB1608U301_0603
1
C529
0.1U_0402_10V6K
2
1
C546
2
0.1U_0402_10V6K
1
C548
2
0.1U_0402_10V6K
1
2
1
2
L27
1
C635
2
0.1U_0402_10V6K
L24
L26
1 2
CHB1608U301_0603
C531
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C543
2
0.1U_0402_10V6K
1
C547
2
0.01U_0402_16V7Z
1
C632
C630
2
0.01U_0402_16V7Z
+2.5VS
+1.8VS
+1.8VS
C544
0.1U_0402_10V6K
L34
1 2
CHB1608U301
L59
1 2
@CHB1608U301
0.1U_0402_10V6K
1
C607
2
10U_0805_10V4Z
0.1U_0402_10V6K
1
2
1
2
0.1U_0402_10V6K
+2.5VDDRH
+VDD_PLL1.8
C513
+VDD_MEMPLL1.8
C85
L25
1 2
CHB1608U301
+2.5VS
+3VS
C619
1
2
1U_0603_10V4Z
1
2
1
2
0.1U_0402_10V6K
1
1
C587
2
2
(20 mil)
C586
(20 mil)
(20 mil)
+1.8VS
C559
22U_1206_10V4Z
0.01U_0402_16V7Z
1
C571
C579
2
0.1U_0402_10V6K
L36
1 2
CHB1608U301_0603
1
C592
0.1U_0402_10V6K
2
L23
1 2
CHB1608U301_0603
1
C523
0.1U_0402_10V6K
2
1 2
CHB1608U301_0603
1
2.2U_0603_6.3V4Z
C88
2
+3VS
1
C554
2
0.1U_0402_10V6K
1
C573
2
0.1U_0402_10V6K
L7
0.1U_0402_10V6K
1
C552
2
0.1U_0402_10V6K
1
C545
2
+2.5VS
+1.8VS
+1.8VS
0.01U_0402_16V7Z
1
1
C557
2
2
0.01U_0402_16V7Z
1
C553
2
0.1U_0402_10V6K
+1.5VS
1
C556
2
0.1U_0402_10V6K
1
C558
2
12
C626
4.7U_0805_10V4Z
1
2
A A
5
SA002160E00(0301021300)
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
ATI M10-P/M9+X POWER-A
LA-2101
1
19 52Tuesday, November 18, 2003
0.1
of
Page 20
5
U3E
M10-P/(M9+X)
(5/6)
A10
VSS
A16
D D
C C
B B
A A
+VGA_CORE
22U_1206_10V4Z
22U_1206_10V4Z
22U_1206_10V4Z
+2.5VS
+2.5VS
1
C524
2
1
C671
2
1
C46
2
22U_1206_10V4Z
1
C2
2
0.1U_0402_10V6K
1
C647
2
0.1U_0402_10V6K
1
C636
2
1
C616
2
0.1U_0402_10V6K
1
C634
2
0.1U_0402_10V6K
1
C577
2
0.1U_0402_10V6K
VSS
A2
VSS
A22
VSS
A29
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE27
VSS
AG11
VSS
AG15
VSS
AG18
VSS
AG22
VSS
AG27
VSS
AG5
VSS
AG9
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
C1
VSS
C28
VSS
C3
VSS
C30
VSS
D10
VSS
D12
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D4
VSS
D6
VSS
D9
VSS
E4
VSS
F27
VSS
SA002160E00(0301021300)
0.1U_0402_10V6K
1
C600
2
0.1U_0402_10V6K
1
C620
2
0.1U_0402_10V6K
1
C637
2
CORE POWER
1
C608
2
0.1U_0402_10V6K
1
C589
2
0.1U_0402_10V6K
1
C660
2
0.1U_0402_10V6K
As close as ppossible to related pin
5
H4
VSS
H8
VSS
H9
VSS
H12
VSS
H14
VSS
H18
VSS
H21
VSS
H23
VSS
H27
VSS
K1
VSS
K23
VSS
K24
VSS
K27
VSS
K30
VSS
K7
VSS
K8
VSS
L4
VSS
M30
VSS
M7
VSS
M8
VSS
N23
VSS
N24
VSS
N27
VSS
P4
VSS
R23
VSS
R24
VSS
R30
VSS
R7
VSS
R8
VSS
T1
VSS
T27
VSS
U23
VSS
U4
VSS
U8
VSS
V30
VSS
W23
VSS
W24
VSS
W27
VSS
W7
VSS
W8
VSS
Y4
VSS
G9
VSS
G12
VSS
G16
VSS
G18
VSS
G21
VSS
G24
VSS
0.1U_0402_10V6K
1
C599
2
0.1U_0402_10V6K
1
C565
2
0.1U_0402_10V6K
1
C662
2
4
C572
0.01U_0402_16V7Z
C633
0.01U_0402_16V7Z
C656
0.01U_0402_16V7Z
4
1
2
1
2
1
2
POWER
INTERFACE
0.01U_0402_16V7Z
1
C582
0.01U_0402_16V7Z
C639
0.01U_0402_16V7Z
C661
C555
2
0.01U_0402_16V7Z
1
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
2
1
C629
2
1
C631
2
0.01U_0402_16V7Z
1
C570
2
0.1U_0402_10V6K
1
C666
2
3
1
+
C560
2
100U_D2_10M_R45
1
C594
2
0.1U_0402_10V6K
+VGA_CORE
0.01U_0402_16V7Z
1
C610
2
U3F
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
P18
VDDC
P19
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U17
VDDC
U18
VDDC
U19
VDDC
V12
VDDC
V13
VDDC
V14
VDDC
V17
VDDC
V18
VDDC
V19
VDDC
W12
VDDC
W13
VDDC
W14
VDDC
W17
VDDC
W18
VDDC
W19
VDDC
AB22
VDDC
AB9
VDDC
J10
VDDC
J12
VDDC
J14
VDDC
J15
VDDC
J16
VDDC
J17
VDDC
J19
VDDC
J21
VDDC
K22
VDDC
K9
VDDC
M22
VDDC
M9
VDDC
P22
VDDC
P9
VDDC
R22
VDDC
R9
VDDC
T22
VDDC
T9
VDDC
U22
VDDC
U9
VDDC
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
VDDC
SA002160E00(0301021300)
10U_0805_10V4Z
M10-P/(M9+X)
(6/6)
+VGA_CORE_CI
C623
2
M10-P&M9+X
COMMON
CORE POWER
M10-P
ONLY
M9+X
ONLY
(20 mil)
1
2
As close as ppossible to related pin
1
C645
2
0.01U_0402_16V7Z
1
C640
2
2
0.1U_0402_10V6K
1
C568
2
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
VDDC
VDDC
VDDC
VDDC
VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
C593
0.1U_0402_10V6K
2
AD15
AD13
AC17
AC15
AC13
T12
M15
W16
R19
R12
R13
T13
R14
T14
N15
P15
R15
T15
U15
V15
W15
H16
M16
N16
P16
R16
T16
U16
V16
R17
T17
R18
T18
T19
AA22
AA9
J11
J13
J18
J20
J22
J9
L22
L9
N22
N9
W22
W9
1
+VGA_CORE
+VGA_CORE_CI
L38
1 2
CHB1608U301
1
C578
0.1U_0402_10V6K
2
Title
Size Document Number Rev
Date: Sheet
480MIL
+VGA_CORE
Comp a l Electro nics , In c .
ATI M10-P/M9+X POWER-B
LA-2101
1
20 52Tuesday, November 18, 2003
0.1
of
Page 21
5
4
3
2
1
VGA DDR FOR CHANNEL A
+2.5VS +2.5VS
22U_1206_10V4Z
1
D D
22U_1206_10V4Z
C721
2
1
C689
2
0.1U_0402_10V6K
As close as ppossible to related pin
1
C697
2
0.1U_0402_10V6K
1
C696
2
1
C705
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C712
2
1
C714
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C715
2
1
C710
2
0.1U_0402_10V6K
22U_1206_10V4Z
1
C152
2
22U_1206_10V4Z
1
C683
2
1
C118
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C117
2
0.1U_0402_10V6K
1
C129
2
0.1U_0402_10V6K
As close as ppossible to related pin
1
C134
2
1
C138
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C139
2
1
C131
2
0.1U_0402_10V6K
NMCLKA0
C701
NMCLKA0#
NMCSA1#
NMAA[0..13]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
NMRASA#18
NMCASA#18
NMWEA#18
NMCSA0#18
NMCKEA18
1
2
R562
56.2_0402_1%
R560
56.2_0402_1%
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NDQMA2
NDQMA1
NDQMA0
NDQMA3
NDQSA2
NDQSA1
NDQSA0
NDQSA3
VREF_1
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
B4
B11D4D5D6D9
U8
VSSQ
VSSQ
VSSQ
VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSSQ
VSSQ
VSS TH
VSS TH
VSSQ
VSSQ
VSS TH
VSS TH
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J9
VSSQ
VSSQ
VSSQ
B7
DQ0
C6
DQ1
B6
DQ2
B5
DQ3
C2
DQ4
D3
DQ5
D2
DQ6
E2
DQ7
K13
DQ8
K12
DQ9
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
VSS TH
K4D263238A-GC_FBGA144
NMDA23
NMDA22
NMDA21
NMDA20
NMDA19
NMDA18
NMDA17
NMDA16
NMDA15
NMDA14
NMDA13
NMDA12
NMDA11
NMDA10
NMDA9
NMDA8
NMDA7
NMDA6
NMDA5
NMDA4
NMDA3
NMDA2
NMDA1
NMDA0
NMDA31
NMDA30
NMDA29
NMDA28
NMDA27
NMDA26
NMDA25
NMDA24
+2.5VS+2.5VS
12
R136
1K_0402_1%
12
R138
1K_0402_1%
NMCLKA118
NMCLKA1#18
1
C107
0.1U_0402_10V6K
2
NMCLKA1
10P_0402_50V8K
NMCLKA1#
(25mil)
C106
NMCSA1#
1
2
R140
56.2_0402_1%
R139
56.2_0402_1%
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13NMAA13
NDQMA6
NDQMA5
NDQMA4
NDQMA7
NDQSA6
NDQSA5
NDQSA4
NDQSA7
VREF_2
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
B4
B11D4D5D6D9
U42
VSSQ
VSSQ
VSSQ
VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSSQ
VSSQ
VSS TH
VSS TH
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS TH
VSS TH
J9
VSSQ
VSSQ
VSSQ
B7
DQ0
C6
DQ1
B6
DQ2
B5
DQ3
C2
DQ4
D3
DQ5
D2
DQ6
E2
DQ7
K13
DQ8
K12
DQ9
J13
DQ10
J12
DQ11
G13
DQ12
G12
DQ13
F13
DQ14
F12
DQ15
F3
DQ16
F2
DQ17
G3
DQ18
G2
DQ19
J3
DQ20
J2
DQ21
K2
DQ22
K3
DQ23
E13
DQ24
D13
DQ25
D12
DQ26
C13
DQ27
B10
DQ28
B9
DQ29
C9
DQ30
B8
DQ31
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
VSS TH
K4D263238A-GC_FBGA144
NMDA55
NMDA54
NMDA53
NMDA52
NMDA51
NMDA50
NMDA49
NMDA48
NMDA47
NMDA46
NMDA45
NMDA44
NMDA43
NMDA42
NMDA41
NMDA40
NMDA39
NMDA38
NMDA37
NMDA36
NMDA35
NMDA34
NMDA33
NMDA32
NMDA63
NMDA62
NMDA61
NMDA60
NMDA59
NMDA58
NMDA57
NMDA56
+2.5VS+2.5VS
NMAA[0..13]18
NMDA[0..63]18
NDQMA[0..7]18
NDQSA[0..7]18
C C
12
R554
1K_0402_1%
12
R555
1K_0402_1%
B B
1
C687
0.1U_0402_10V6K
2
NMCLKA018
NMCLKA0#18
NMCSA1#18
(25mil)
10P_0402_50V8K
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
VGA DDR FOR CHANNEL A
LA-2101
1
21 52Saturday, November 22, 2003
0.1
of
Page 22
5
4
3
2
1
+2.5VS
0.1U_0402_10V6K
1
22U_1206_10V4Z
D D
C78
2
1
C66
2
0.1U_0402_10V6K
1
C70
2
0.01U_0402_16V7Z
1
C73
2
0.01U_0402_16V7Z
C67
1
2
22U_1206_10V4Z
1
C658
2
1
C63
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C60
2
1
C72
2
0.01U_0402_16V7Z
22U_1206_10V4Z
+2.5VS
1
C49
2
0.1U_0402_10V6K
1
C32
2
0.1U_0402_10V6K
As close as ppossible to related pin
NMAB[0..13]18
NMDB[0..63]18
NDQMB[0..7]18
NDQSB[0..7]18
C C
+2.5VS
R118
1K_0402_1%
1 2
(25mil)
1
R117
1K_0402_1%
1 2
B B
C74
0.1U_0402_10V6K
2
NMCLKB018 NMCLKB118
10P_0402_50V8K
NMCLKB0#18
NMCSB1#18
NMAB[0..13]
NMDB[0..63]
NDQMB[0..7]
NDQSB[0..7]
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB0
NDQMB3
NDQMB2
NDQMB1
NDQSB0
NDQSB3
NDQSB2
NDQSB1
VREF_3
56.2_0402_1%
56.2_0402_1%
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
NMRASB#18
NMCASB#18
NMWEB#18
NMCSB0#18
NMCLKB0
NMCKEB18
R113
R114
1
C81
2
NMCSB1# NMCSB1#
B4
B11D4D5D6D9
U39
VSSQ
VSSQ
VSSQ
VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSSQ
VSSQ
VSS TH
VSS TH
VSSQ
VSSQ
VSS TH
VSS TH
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J9
VSSQ
VSSQ
VSSQ
B7
DQ0
C6
DQ1
B6
DQ2
B5
DQ3
C2
DQ4
D3
DQ5
D2
DQ6
E2
DQ7
K13
DQ8
K12
DQ9
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
VSS TH
K4D263238A-GC_FBGA144
NMDB0
NMDB2
NMDB1
NMDB7
NMDB6
NMDB5
NMDB3
NMDB4
NMDB27
NMDB30
NMDB28
NMDB25
NMDB31
NMDB29
NMDB24
NMDB26
NMDB18
NMDB16
NMDB19
NMDB17
NMDB20
NMDB21
NMDB22
NMDB23
NMDB8
NMDB10
NMDB9
NMDB11
NMDB12
NMDB13
NMDB15
NMDB14
+2.5VS
+2.5VS
R83
1K_0402_1%
1 2
R90
1K_0402_1%
1 2
10P_0402_50V8K
NMCLKB1#18
1
2
NMCLKB1
R96
NMCLKB1#NMCLKB0#
VGA DDR FOR CHANNEL B
0.01U_0402_16V7Z
C34
1
C38
2
0.01U_0402_16V7Z
1
C33
2
As close as ppossible to related pin
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB5
NDQMB6
NDQMB7
NDQMB4
NDQSB5
NDQSB6
NDQSB7
56.2_0402_1%
56.2_0402_1%
NDQSB4
VREF_4
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
(25mil)
C44
0.1U_0402_10V6K
R97
1
C48
2
1
2
22U_1206_10V4Z
1
C27
2
B4
B11D4D5D6D9
U35
VSSQ
VSSQ
VSSQ
VSSQ
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
B3
H12
H3
B12
B2
H13
H2
B13
N13
M13
L9
M10
M2
L2
L3
N2
N12
M11
M12
C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
VSSQ
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#
CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS TH
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
1
C36
2
0.1U_0402_10V6K
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
0.1U_0402_10V6K
1
C40
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
J9
1
C39
2
0.01U_0402_16V7Z
VSSQ
VSSQ
NMDB41
B7
NMDB43
C6
NMDB40
B6
NMDB42
B5
NMDB44
C2
NMDB46
D3
NMDB45
D2
NMDB47
E2
NMDB54
K13
NMDB55
K12
NMDB53
J13
NMDB52
J12
NMDB50
G13
NMDB51
G12
NMDB49
F13
NMDB48
F12
NMDB58
F3
NMDB57
F2
NMDB56
G3
NMDB59
G2
NMDB60
J3
NMDB61
J2
NMDB63
K2
NMDB62
K3
NMDB35
E13
NMDB33
D13
NMDB32
D12
NMDB34
C13
NMDB37
B10
NMDB38
B9
NMDB36
C9
NMDB39
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
K4D263238A-GC_FBGA144
+2.5VS
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Comp a l Electro nics , In c .
VGA DDR FOR CHA NNEL B
LA-2101
1
22 52Saturday, November 22, 2003
0.1
of
Page 23
A
B
C
D
E
POP For 150A
DEPOP For 150G
12
R24
75_0603_1%
R3875_0603_1%
12
R3975_0603_1%
12
R4075_0603_1%
12
12
12
R474
75_0603_1%
1 2
C19
0.1U_0402_16V4Z
0_0402_5%
0_0402_5%
@0_0402_5%
@0_0402_5%
A
1 2
@0_0402_5%
R27
1 2
@0_0402_5%
R26
1 2
0_0402_5%
R28
1 2
0_0402_5%
R29
POP For 150G
DEPOP For 150A
INVT_PWM39
IB+
+3VS
R171
1 2
1 2
1 2
R31
R32
R33
12
R473
U1
1 2
21
@0_0402_5%
@0_0402_5%
@0_0402_5%
1 2
1 2
1 2
18P_0402_50V8K
+CRT_VCC
1
2 4
OE#
AY
GP
3 5
10K_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
D28
CH751H-40_SC76
R35
R36
R37
75_0603_1%
12
C7
270P_0402_50V7K
R172
DISPOFF#
1
C145
2
220P_0402_50V7K
R1045, R1047, R1049, R1060, R1061
POP For 150A
DEPOP For 150G
12
12
C533
18P_0402_50V8K
DACA_HSYNC_1
+CRT_VCC
1 2
C526
0.1U_0402_16V4Z
2 4
TV_LUMA10
TV_CRMA10
1 1
LUMA17
CRMA17
2 2
3 3
4 4
NB_CRT_R10
NB_CRT_G10
NB_CRT_B10
DACA_HSYNC17
DACA_VSYNC17
CRT_HSYNC10
CRT_VSYNC10
R25
75_0603_1%
B+
BKOFF#39
R17
G17
B17
R475
75_0603_1%
1 2
R51
SN74AHCT1G125GW_SOT353-5
1 2
R52
1 2
R71
1 2
R72
R1175_0603_1%
12
R1075_0603_1%
12
12
L40 CHB2012U170_0805
1 2
1 2
L41 CHB2012U170_0805
TV-OUT Conn.
C517 22P_0402_50V8J
1 2
1 2
L1 CHB1608B121_0603
1 2
L2 CHB1608B121_0603
1 2
C514
12
C6
22P_0402_50V8J
270P_0402_50V7K
DAC_BRIG39
1 2
0_0402_5%
L31
1 2
FCM2012C-800_0805
L30
1 2
FCM2012C-800_0805
L29
1 2
FCM2012C-800_0805
12
C535
C534
18P_0402_50V8K
R456
1K_0402_5%
1 2
1
DACA_VSYNC_1
OE#
AY
U32
GP
SN74AHCT1G125GW_SOT353-5
3 5
R1051, R1052, R1053, R1056, R1058
POP For 150G
DEPOP For 150A
12
DISPOFF#
D2
DAN217_SOT23
2
12
C511
15P_0402_50V8J
L3 CHB1608B121_0603
1 2
L28 CHB1608B121_0603
1 2
D50
@DAN217_SOT23
LUMA_1
CRMA_1
C515
330P_0402_50V7K
1
2
3
4
5
6
7
DAN217_SOT23
1
3
CRT_R
CRT_G
CRT_B
12
C510
15P_0402_50V8J
12
C3
@68P_0402_50V8K
B
1
2
3
2
12
C516
330P_0402_50V7K
JP3
1
2
3
4
5
6
7
ACES_85204-0700
B+
Use for B+ discharge
C682
10U_1210_35V4Z
D3
2
1
3
D4
DAN217_SOT23
2
12
C509
15P_0402_50V8J
DACA_HSYNC_2
DACA_VSYNC_2
12
C508
@68P_0402_50V8K
1
D51
@DAN217_SOT23
3
R558
100K_0402_5%
1 2
1
+3VS
3
+3VS
JP15
1. Y ground
1
1
2. C ground
2
2
3. Y (luminance+sync)
3
3
4. C (crominance)
4
4
SUYIN_030008FR004T100ZL
+5VS +CRT_VCC+R_CRT_VCC
D5
2 1
FUSE_1A
CH491D_SOT23
0.1U_0402_16V4Z
1
C505
2
220P_0402_50V7K
C512
220P_0402_50V7K
F1
21
C506
1
2
+3VS
1 2
R121 0_0805_5%
0.1U_0402_16V4Z
C566 @0.1U_0402_16V4Z
PCIRST#24,28,29,31,32,36,39
ENVDD9,17
12
CRT_VCC
1
C4
2
220P_0402_50V7K
C
LVDS Conn.
+VGA_EDID
C93
12
ENVDD
ENVDD
10K_0402_5%
12
+LCDVDD
EDID_DATA17
1
2
R497
EDID_CLK17
+3VS
EDID_CLK
EDID_DATA
TXOUT0-17
TXOUT0+17
TXOUT2+17
TXOUT2-17
TXOUT1+17
TXOUT1-17
TXCLK+17
TXCLK-17
TZCLK-17
TZCLK+17
TZOUT0-17
TZOUT0+17
TZOUT2-17
TZOUT2+17
TZOUT1-17
TZOUT1+17
POP For 150G
DEPOP For 150A
EDID_CLK
EDID_DATA
U34
5
4
3
@TC7SH08FU_SSOP5
1 2
0_0402_5%
R498
1 2
JP2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
ACES_87213-2200
C87 47P_0402_50V8J
1 2
C82 47P_0402_50V8J
1 2
+LCDVDD
12
R88
220_0402_5%
13
D
2
G
Q2
S
2N7002_SOT23
22K
2
22K
+5V
R509
10K_0402_5%
1 2
R514
47K_0402_5%
13
DTC124EK_SOT23
R507 @0_0805_5%
1 2
DTC124EK_SOT23
Q40
CRT Conn.
JP14
SUYIN_7849S-15G2T-HC
6
11
1
7
12
+CRT_VCC
2
8
13
3
9
14
4
10
15
5
DDC_DATA_1
DDC_CLK_1
THIS SHEE T OF ENGIN EERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONIC S, INC. AN D CONTAI NS CONFI DENTIAL
AND TRADE SECRET INF ORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL EC TR ON IC S, I NC . N EI TH ER T HI S SH EE T N OR T HE IN FO RMA TI ON I T C ON TA IN S
MAY BE USE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOU T PRI OR WRITTEN C ONSENT OF COMPAL ELECT RONI CS, INC.
R464
4.7K_0402_5%
1 2
+CRT_VCC
4.7K_0402_5%
1 2
2N7002_SOT23
+3VS +3VS +3VS
R49
R34
100K_0402_5%
1 2
2
G
Q38
1 3
D
S
Q1
2N7002_SOT23
1 3
R50
R48
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
2
G
D
S
POP For 150A
DEPOP For 150G
D
1 2
C621
@0.1U_0402_16V4Z
+12VALW
R103
100K_0402_5%
1 2
13
22K
2
22K
Q41
Width: 40mils
+NB_EDID+3VS
+LCDVDD
NB_EDID_CLK9
12
NB_EDID_DAT9
TXBCLK+_NB10
+LCDVDD+LCDVDD
POP For 150A
DEPOP For 150G
NB_EDID_CLK
NB_EDID_DAT
12
12
R104
1000P_0402_50V7K
200K_0402_5%
1 2
0_0402_5%
R56
1 2
0_0402_5%
R55
1 2
@0_0402_5%
R66
1 2
@0_0402_5%
R65
C596 @4.7U_0805_10V4Z
1 2
JP1
1
1
2
NB_EDID_CLK
NB_EDID_DAT
TXB2+_NB10
TXB2-_NB10
TXBCLK-_NB10
TXB0-_NB10
TXB0+_NB10
TXB1+_NB10
TXB1-_NB10
TXA2-_NB10
TXA2+_NB10
TXACLK+_NB10
TXACLK-_NB10
TXA0+_NB10
TXA0-_NB10
TXA1-_NB10
TXA1+_NB10
C605 @47P_0402_50V8J
1 2
C612 @47P_0402_50V8J
1 2
+3VS
13
D
2
G
S
C52
12
POP For 150G
DEPOP For 150A
Q3
SI2302DS-T1_SOT23
C581
0.1U_0402_16V4Z
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
12
C31
4.7U_0805_10V4Z
+LCDVDD
12
C550
4.7U_0805_10V4Z
DDC_DATA 17
DDC_CLK 17
3VDDCDA 10
3VDDCCL 10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
@ACES_87213-2200
Compal Electronics, In c.
Title
CRT,TV-OUT & LV D S C onnector
Size Document Number Rev
C
Date: Sheet
LA-2101
23 52Saturday, November 22, 2003
E
of
0.1
Page 24
5
A_AD[0..31]9,12
A_CBE#[0..3]9
+CPU_CORE
R199
56_0402_1%
D D
H_FERR#5
C C
20M_0603_5%
12P_0402_50V8K
1
C813
2
32.768KHZ_12.5P_1TJS125DJ2A073
B B
R688
1 2
RTCX1RTCX2
4
1
IN
NC
3
2
+3VS
PM_STPCPU#
H_INIT#
H_A20M#
H_SLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
Y3
OUT
NC
1 2
Q15 MMBT3904_SOT23
R310 8.2K_0402_5%
12P_0402_50V8K
1
C814
2
A_AD[0..31]
A_CBE#[0..3]
+CPU_CORE
12
2
3 1
+3VS
PCI_STP#
R617 200_0402_5%
R618 200_0402_5%
R200 200_0402_5%
R202 200_0402_5%
R616 200_0402_5%
R203 200_0402_5%
R615 200_0402_5%
R201 200_0402_5%
12
R689
R197
470_0402_5%
12
12
R304
10K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
20M_0603_5%
PM_DPRSLPVR50
+3VS
+3VS
12
R210
330_0402_5%
H_CPUFERR#
A_SERR#
12
R323
4.7K_0402_5%
100K_0402_5%
+CPU_CORE
R259
PULL DOWN FOR S3
12
CLK_ALINK_SB16
R311 8.2K_0402_5%
1 2
CLK_ALINK_SB
12
R244
@10_0402_5%
1
C259
@15P_0402_50V8J
2
A_STROBE#9
A_DEVSEL#9
A_ACAT#9
A_SBREQ#9
A_SBGNT#9
PM_STPCPU#5,50
PCI_PIRQA#9,17,29,32
PCI_PIRQB#29
PCI_PIRQC#31
PCI_PIRQD#28,31
4.7K_0402_5%
H_PWRGOOD5
H_SLP#5
H_IGNNE#5
H_A20M#5
H_STPCLK#5
R275 0_0402_5%
1 2
R250 10K_0402_5%
1 2
R258 10K_0402_5%
1 2
R231 1K_0402_1%
1 2
RTC Battery
12
+RTCVCC
12
+RTCBATT
+RTCBATT
3
C484
0.1U_0402_16V4Z
1
D49
BAS40-04_SOT23
2
CHGRTC
BATT1
-+
Place J1 close
to DDR-SODIMM
+SB_VBAT
R432 220_0402_5%
1 2
C488
1
W=20mils
2
1U_0603_10V4Z
A A
RTCBATT
R431 220_0402_5%
1 2
JOPEN1
No short
1 2
A_END#9
A_OFF#9
R225
H_INIT#5
A_PAR9,12
H_INTR5
H_NMI5
H_SMI#5
+3VS
12
SB_PCI_RST#
R417
10K_0402_5%
4
CLK_ALINK_SB
NBRST#
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
PM_STPCPU#
PCI_STP#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
RTCX1
RTCX2
CPURSTIN#
H_A20M#
H_CPUFERR#
GPIO0
SB_APIC_D0
SB_APIC_D1
U47A
B22
PCICLKF
R22
A_RST#
H22
A_AD0
P23
A_AD1
L23
A_AD2
N23
A_AD3
N22
A_AD4
M23
A_AD5
M22
A_AD6
K22
A_AD7
M21
A_AD8
M20
A_AD9
L21
A_AD10
K21
A_AD11
L20
A_AD12
N21
A_AD13
K23
A_AD14
K20
A_AD15
F23
A_AD16
G21
A_AD17
F20
A_AD18
H21
A_AD19
F22
A_AD20
F21
A_AD21
G20
A_AD22
E21
A_AD23
E20
A_AD24
D23
A_AD25
D22
A_AD26
E22
A_AD27
D20
A_AD28
C23
A_AD29
D21
A_AD30
C22
A_AD31
L22
A_CBE#0
J23
A_CBE#1
G22
A_CBE#2
E23
A_CBE#3
H20
A_STROBE#
J21
A_DEVSEL#
G23
A_ACAT#
H23
A_END#
J20
A_PAR
J22
A_OFF#
P22
A_SERR#
B21
A_SBREQ#
B20
A_SBGNT#
N20
CPU_STP#/DPSLP#
R23
PCI_STP#
C20
A_INTA#
P20
INTB#
B23
INTC#
P21
INTD#
AC12
X1
AC11
X2
B18
CPURSTIN#
E4
CPU_PWRGD
B17
INTR/LINT0
B16
NMI/LINT1
C17
INIT
C16
SMI#
F19
SLP#
D17
IGNNE#
D18
A20M#
E19
FERR#
E16
STPCLK#
E17
SSMUXSEL/GPIO0
E18
DPRSLPVR
C19
APIC_D0
C18
APIC_D1
B19
APIC_CLK
South bridge SB200
+3VALW
147
U24A
PG
21
OI
SN74LVC14APWLE_TSSOP14
SB_PCI_RST# 35
SB200 SB
Part 1 of 3
A-LINK INTERFACE
PCI INTERFACE
REQ#4/PLLBP33/PDMAREQ1#
XTAL
GNT#4/PLLBP50/PDMAGNT1#
LPC
CPU
RTC_ALE/USBOC4#/GPIO3
RTC_WR#/RTC_CLKOUT
RTC_CS#/USBOC3#/GPIO2
RTC
C469 0.1U_0402_16V4Z
147
U24B
PG
PCIRST#
43
OI
SN74LVC14APWLE_TSSOP14
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK_FB
PCI CLKS
PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24/RTC_AD7
AD25/RTC_AD6
AD26/RTC_AD5
AD27/RTC_AD4
AD28/RTC_AD3
AD29/RTC_AD2
AD30/RTC_AD1
AD31/RTC_AD0
CBE#0/ROMA10
CBE#1/ROMA1
CBE#2/ROMWE#
CBE#3/RTC_RD#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR
STOP#
PERR#
SERR#
REQ#0
REQ#1
REQ#2
REQ#3/PDMAREQ0#
GNT#0
GNT#1
GNT#2
GNT#3/PDMAGNT0#
CLKRUN#
GPIO1/ROMCS#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#0
LDRQ#1
SERIRQ
USBOC5#/GPM1
VBAT
RTC_GND
PCIRST# 23,28,29,31,32,36,39
3
Layout note:
Trace length of PCI_CLK_R + PCI_ CL K_ FB s h ou l d
be less than 200 mils.
R623 33_0402_5%
B15
D16
A14
A15
A16
A17
D15
A18
A19
C15
B1
C1
A1
D2
B2
C2
A2
D3
C3
A3
D4
B4
C4
A4
D5
B5
C8
D8
B8
A8
C9
D9
B9
A9
C10
B10
D11
A10
C11
B11
D12
A11
B3
C5
A7
D10
B7
A6
C7
D7
A5
B6
C6
D6
B12
C12
D13
A12
C13
A13
B13
C14
D14
B14
A20
AB5
Y14
AA14
AB14
AA13
AB13
AC14
Y13
AC13
AA2
AB7
AB8
AC8
AC10
AB11
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCI_CLK_R
PCI_CLK_FB
SB_PCI_RST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PM_CLKRUN#
GPIO1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
LPC_DRQ1#
SIRQ
OVCUR#5
OVCUR#4
OVCUR#3
1 2
R622 33_0402_5%
1 2
R620 33_0402_5%
1 2
R621 33_0402_5%
1 2
R624 33_0402_5%
1 2
R625 33_0402_5%
1 2
R222 33_0402_5%
1 2
PCI_AD[0..31]
PCI_C/BE#[0..3]
R374 10K_0402_5%
+SB_VBAT
12
R268
1K_0402_5%
NBRST#
1
2
R247 @0_0402_5%
PCI_FRAME# 28,29,31,32
PCI_DEVSEL# 28,29,31,32
PCI_IRDY# 28,29,31,32
PCI_TRDY# 28,29,31,32
PCI_PAR 28,29,31,32
PCI_STOP# 28,29,31,32
PCI_PERR# 28,29,31,32
PCI_SERR# 28,29,31,32
PCI_REQ#0 32
PCI_REQ#1 31
PCI_REQ#2 29
PCI_REQ#3 28
PCI_GNT#0 32
PCI_GNT#1 31
PCI_GNT#2 29
PCI_GNT#3 28
PM_CLKRUN# 28,29,31,32,36,39
12
LPC_AD0 36,39
LPC_AD1 36,39
LPC_AD2 36,39
LPC_AD3 36,39
LPC_FRAME# 36,39
LPC_DRQ1# 36
SERIRQ 29,36,39
USB_OC4# 37
+3VALW
C285 0.1U_0402_16V4Z
U15
5
4
3
TC7SH08FU_SSOP5
CLK_PCI_MINI 31
CLK_PCI_CB 29
CLK_PCI_LPC 39
CLK_PCI_1394 32
CLK_PCI_LAN 28
CLK_PCI_SIO 36
C236 22P_0402_50V8J
1 2
PCI_AD[0..31] 27,28,29,31,32
PCI_C/BE#[0..3] 28,29,31,32
+3V
NB_RST#
NB_RST# 7,17
2
RP58
4 5
3 6
2 7
1 8
8.2K _8P4R_0804_5%
RP57
4 5
3 6
2 7
1 8
8.2K _8P4R_0804_5%
R249
1 2
8.2K_0402_5%
R325
1 2
8.2K_0402_5%
R221
1 2
8.2K_0402_5%
R324
1 2
8.2K_0402_5%
RP17
4 5
3 6
2 7
1 8
8.2K _8P4R_0804_5%
RP16
4 5
3 6
2 7
1 8
8.2K _8P4R_0804_5%
R246
1 2
8.2K_0402_5%
R234
1 2
8.2K_0402_5%
RP47
4 5
3 6
2 7
1 8
15K_0804_8P4R_5%
RP48
10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
12
12
1 2
12
12
C11 @220P_0402_50V7K
12
C13 @220P_0402_50V7K
12
C10 @220P_0402_50V7K
12
C12 @220P_0402_50V7K
SIRQ
LPC_DRQ0#
LPC_FRAME#
LPC_DRQ1#
PM_CLKRUN#
GPIO0
OVCUR#5
OVCUR#3
H_A20M#
H_INIT#
H_INTR
H_NMI
PCI_SERR#
PCI_PERR#
PCI_TRDY#
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ#0
PCI_REQ#3
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_REQ#2
PCI_REQ#1
PCI_REQ#4
PCI_GNT#4
LPC_AD0
LPC_AD1
LPC_AD3
LPC_AD2
R213 4.7K_0402_5%
R276 10K_0402_5%
R367 10K_0402_5%
R377 10K_0402_5%
Place Caps Close to CPU Socket
+3VS
1
+3V
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
SB200M(1/4)- PC I/ CP U/L PC
LA-2101
1
24 52Saturday, November 22, 2003
0.1
of
Page 25
5
4
3
2
1
U47B
OSCLIN
P3
R322
1 2
12.4K_0603_1%
D D
IAC_BITCLK
12
R272
@10_0402_5%
1
C278
@15P_0402_50V8J
2
CLK_SB_14M
12
R224
@10_0402_5%
1
C235
@15P_0402_50V8J
2
R285
1 2
12
R371
10K_0402_5%
15K_0402_5%
R287
1 2
15K_0402_5%
R300
1 2
15K_0402_5%
R293
1 2
15K_0402_5%
RP32
1 8
2 7
3 6
4 5
R282
1 2
15K_0402_5%
R284
1 2
15K_0402_5%
R281
1 2
15K_0402_5%
R283
1 2
15K_0402_5%
1 2
X3
4
OUT
VDD
1
GND
OE
48MHZ_4P_FN4800002
GHI#
5
AGP_STP#9,17
Q24 MMBT3904_SOT23
C C
USB20P5+
USB20P5-
+3V
B B
+3V
1
C439
0.1U_0402_10V6K
2
A A
USB_OC0#37
USBP4+37
USBP4-37
USBP2+37
USBP2-37
USBP0+37
USBP0-37
USB20P2+
USB20P2ÂUSB20P4ÂUSB20P4+ PCI_ACT_REQ#
USB20P3+
USB20P3-
15K_0804_8P4R_5%
R37310K_0402_5%
3
2
3 1
USB20P1+
USB20P1ÂUSB20P0+
USB20P0-
R375 100K_0402_5%
1 2
OVCUR#1
R365 10K_0402_5%
AGP_STP#
1 2
R337
0_0402_5%
+3V
12
**
R390
470_0402_5%
2
R358 10K_0402_5%
+3V
R319 10K_0402_5%
EC_RSMRST#39
CLK_SB_14M16
R370 10K_0402_5%
+3V
EC_FLASH#40
USB_OC2#37
D48
2 1
CH751H-40_SC76
1 2
CPU_GHI# 5
R376
33_0402_5%
SUSCLK27
PIDERST#35
SIDERST#35
*
+3VS
R207 1K_0402_5%
12
OSCLIN
MII_TXD327
MII_TXD227
MII_TXD127
MII_TXD027
MII_TXEN27
SB_EEDO27
SB_EECLK27
SPKR34
1 2
USB_RCOMP
OVCUR#0
12
12
EC_RSMRST#
CLK_SB_14M
12
FLASH#
OVCUR#2
OVCUR#1
AGP_STP#_R
AGP_BUSY#_R
GHI#
USB20P5+
USB20P5-
USB20P4+
USB20P4-
USB20P3+
USB20P3-
USB20P2+
USB20P2-
USB20P1+
USB20P1-
USB20P0+
USB20P0-
SPKR
VTT_PWRGD 16,27
USBCLK/CLK48
R1
USB_RCOMP
P1
USB_VREFOUT
N4
USB_ATEST1
N3
USB_ATEST0
P4
USBOC0#/GPM7
M2
USB_HSDP5+
M1
USB_FLDP5+
N2
USB_HSDM5-
N1
USB_FLDM5-
L4
USB_HSDP4+
L3
USB_FLDP4+
M4
USB_HSDM4-
M3
USB_FLDM4-
K2
USB_HSDP3+
K1
USB_FLDP3+
L2
USB_HSDM3-
L1
USB_FLDM3-
H2
USB_HSDP2+
H1
USB_FLDP2+
J2
USB_HSDM2-
J1
USB_FLDM2-
G3
USB_HSDP1+
J3
USB_FLDP1+
H3
USB_HSDM1-
K3
USB_FLDM1-
F1
USB_HSDP0+
F2
USB_FLDP0+
G1
USB_HSDM0-
G2
USB_FLDM0-
R5
MCOL
W1
MCRS
V4
MDCK
V2
MDIO
T1
RX_CLK
T3
RXD3
U2
RXD2
T5
RXD1
W4
RXD0
T2
RX_DV
U1
RX_ERR
T4
TX_CLK
U4
TXD3
V1
TXD2
U3
TXD1
V3
TXD0
W2
TX_EN
W3
PHY_PD
U5
PHY_RST#
Y7
CLK_25M
P2
EE_CS
R3
EE_DI
R2
EE_DO
R4
EE_CK
AB9
RSMRST#
A23
OSC_IN
W6
SIO_CLK
AB2
BLINK/GPM0
AA3
FANOUT1/USBOC2#/GPM2
W11
32KHZ_IN/GPM3
AB1
USBOC1#/GPM4
Y4
SPEAKER/GPM5
AA1
FANOUT0/GPM6
AC1
GPIO_X0/AGP_STP#
AC6
GPIO_X1/AGP_BUSY#
AC2
GPIO_X2/GHI#
AC3
GPIO_X3/VGATE
AC4
GPIO_X4
AC5
GPIO_X5
South bridge SB200
Q17 2N7002_SOT23
D
S
1 3
G
2
4
SB200 SB
TALERT#/ETH_TALERT#
Part 2 of 3
AGP_BUSY#AGP_BUSY#_R
PME#/EXT_EVNT0#
RI#/EXT_EVNT1#
PCI_REQACT#
GA20_IN/GEVNT0#
KB_RST#/GEVNT1#
SMB_ALERT#/GEVNT2#
LPC_PME#/GEVNT3#
LPC_SMI#/GEVNT4#
GEVENT5#/ETH_VALERT#
GEVENT6#/ETH_FALERT#
GEVENT7#/ETH_CALERT#
GPOC1#/SDA0
GPOC3#/SDA1
RTC_IRQ#/PWR_STRP
USB INTERFACE
ETHERNET MIIEEPROMCLK / RST
SECONDARY ATA 66/100 PRIMARY ATA 66/100 ACPI / WAKE UP EVENTS
GPIOGPIO_XTRA
AC97
AGP_BUSY# 9,17
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
GPOC0#/SCL0
GPOC2#/SCL1
PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#
SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT
4.7K_0402_5%
SUS_STAT# SUS_STAT#
SB_EC_THERM#
AB4
SB_PM_BATLOW#
AC9
RI#
AC7
PM_SLP_S3#
AA11
PM_SLP_S5#
AB10
PBTN_OUT#
AA10
SB_PWRGD
Y11
PCI_ACT_REQ#
C21
SUS_STAT#
Y10
SB_TEST1
AA5
TEST1
SB_TEST0
AA6
TEST0
SB_GA20
Y5
SB_KBRST#
AA4
SB_AC_IN
AB3
SB_EC_SWI#
Y6
LPC_SMI#
W5
SB_EC_SMI#
Y8
SB_SCI#
AA7
SB_LID_OUT#
AB6
SMB_CK_CLK2
AA12
SMB_CK_DAT2
W12
SMB_CK_CLK2_SB
Y12
SMB_CK_DAT2_SB
AB12
PWR_STRP
AA8
IDE_PDIORDY
AB17
INT_IRQ14
AC16
IDE_PDA0
AB15
IDE_PDA1
AB16
IDE_PDA2
AC15
IDE_PDDACK#
Y16
IDE_PDDREQ
AA17
IDE_PDIOR#
AA16
IDE_PDIOW#
AC17
IDE_PDCS1#
Y15
IDE_PDCS3#
AA15
IDE_PDD0
AC18
IDE_PDD1
AA18
IDE_PDD2
AC19
IDE_PDD3
AA19
IDE_PDD4
AC20
IDE_PDD5
AA20
IDE_PDD6
AC21
IDE_PDD7
AB21
IDE_PDD8
AA21
IDE_PDD9
Y20
IDE_PDD10
AB20
IDE_PDD11
Y19
IDE_PDD12
AB19
IDE_PDD13
Y18
IDE_PDD14
AB18
IDE_PDD15
Y17
IDE_SDIORDY
AA23
INT_IRQ15
AA22
IDE_SDA0
AC23
IDE_SDA1
Y21
IDE_SDA2
AB23
IDE_SDDACK#
Y22
IDE_SDDREQ
W21
IDE_SDIOR#
Y23
IDE_SDIOW#
W20
IDE_SDCS1#
AC22
IDE_SDCS3#
AB22
IDE_SDD0
W23
IDE_SDD1
V21
IDE_SDD2
V23
IDE_SDD3
U21
IDE_SDD4
U23
IDE_SDD5
T21
IDE_SDD6
T23
IDE_SDD7
R21
IDE_SDD8
R20
IDE_SDD9
T22
IDE_SDD10
T20
IDE_SDD11
U22
IDE_SDD12
U20
IDE_SDD13
V22
IDE_SDD14
V20
IDE_SDD15
W22
IAC_BITCLK ICH_AC_BITCLK
E1
E2
Y1
Y2
Y3
E3
V5
E5
+2.5V
R185
1 2
1 2
1 2
R270 22_0402_5%
+2.5V +2.5V
4.7K_0402_5%
R186
1 2
2
Q14 MMBT3904_SOT23
3 1
3
PM_SLP_S3# 39
PM_SLP_S5# 39
PBTN_OUT# 39
SB_PWRGD 27
SMCLK 13,14,16
SMDATA 13,14,16
PWR_STRP 27
IDE_PDIORDY 35
INT_IRQ14 35
IDE_PDA0 35
IDE_PDA1 35
IDE_PDA2 35
IDE_PDDACK# 35
IDE_PDDREQ 35
IDE_PDIOR# 35
IDE_PDIOW# 35
IDE_PDCS1# 35
IDE_PDCS3# 35
IDE_PDD[0..15] 35
IDE_SDIORDY 35
INT_IRQ15 35
IDE_SDA0 35
IDE_SDA1 35
IDE_SDA2 35
IDE_SDDACK# 35
IDE_SDDREQ 35
IDE_SDIOR# 35
IDE_SDIOW# 35
IDE_SDCS1# 35
IDE_SDCS3# 35
IDE_SDD[0..15] 35
R277
22_0402_5%
SB_EC_THERM# EC_THRM#
D43 CH751H-40_SC76
SB_EC_SWI#
SB_GA20 GATEA20
SB_KBRST#
SB_EC_SMI#
SB_SCI# EC_SCI#
SB_LID_OUT#
IAC_SDATAO
IAC_SDATAI0
IAC_SDATAI1
IAC_SDATAI2
IAC_SYNC
IAC_RST#
SPDIF_OUT
12
10K_0402_5%
R175
ICH_AC_BITCLK 33,38
ICH_AC_SDOUT 27,33,38
ICH_AC_SDIN0 33
ICH_AC_SDIN1 38
ICH_AC_SYNC 27,33,38
ICH_AC_RST# 33,38
SPDIF_OUT 27
AGP_SUS_STAT# 17 NB_SUS_STAT# 7
2 1
D44 CH751H-40_SC76
2 1
D41 CH751H-40_SC76
2 1
D40 CH751H-40_SC76
2 1
D39 CH751H-40_SC76
2 1
D42 CH751H-40_SC76
2 1
D37 CH751H-40_SC76
2 1
D33 CH751H-40_SC76
2 1
PM_SLP_S3#
PBTN_OUT#
PM_SLP_S5#
SB_PM_BATLOW#
SB_EC_SMI#
SB_SCI#
SB_EC_SWI#
SB_LID_OUT#
AGP_BUSY#_R
SB_KBRST#
SB_EC_THERM#
*
RI#
SB_AC_IN
SB_GA20
LPC_SMI#
GHI#
AGP_STP#_R
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_CLK2
SMB_CK_DAT2_SB
IAC_RST#
AGP_STP#
AGP_BUSY#
SB_TEST1
SB_TEST0
ICH_AC_BITCLK
IAC_SDATAI2
IAC_SDATAI1
IAC_SDATAI0
2
EC_SWI#
KBRST#
ACINSB_AC_IN
EC_SMI#
EC_LID_OUT#
1 8
2 7
3 6
4 5
RP49 10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP61
1 8
2 7
3 6
4 5
RP60
1 2
R379 10K_0402_5%
1 2
R372 10K_0402_5%
1 2
R230 10K_0402_5%
4 5
3 6
2 7
1 8
RP50 10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP39 2.2K_0804_8P4R_5%
1 2
R347
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
4.7K_0402_5%
R184
1 2
2
Q13 MMBT3904_SOT23
3 1
+3VALW
10K_0804_8P4R_5%
10K_0804_8P4R_5%
8.2K_0402_5%
R3858.2K_0402_5%
R2068.2K_0402_5%
R3878.2K_0402_5%
R3868.2K_0402_5%
R2458.2K_0402_5%
R3828.2K_0402_5%
R3888.2K_0402_5%
R3838.2K_0402_5%
+2.5V+3VS
EC_THRM# 39
EC_SWI# 39
GATEA20 39
KBRST# 39
ACIN 39,40,44
EC_SMI# 39
EC_SCI# 39
EC_LID_OUT# 39
+3V
+3VS
+3V
+3VS
R183
4.7K_0402_5%
1 2
R182
10K_0402_5%
1 2
*27
*27
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(2/4) - IDE/USB/MII
LA-2101
1
25 52Saturday, November 22, 2003
of
0.1
Page 26
5
4
3
2
1
+3VS +3VS
22U_1206_10V4Z
1
C315
D D
C C
+3V
FBM-10-201209-260-T_0805
B B
+3V
FBM-10-201209-260-T_0805
+2.5VS
FBM-10-201209-260-T_0805
A A
R312
1 2
R299
1 2
22U_1206_10V4Z
R215
1 2
22U_1206_10V4Z
22U_1206_10V4Z
22U_1206_10V4Z
22U_1206_10V4Z
+3V_AVDDC
C226
+2.5V_AVDDCK
2
+2.5VS
1
C355
2
+2.5V
1
C408
2
+3V
0.1U_0402_10V6K
1
C409
2
1
C344
1U_0603_10V4Z
2
0.1U_0402_10V6K
1
1
C351
2
2
0.1U_0402_10V6K
1
C197
2
1U_0603_10V4Z
C412
0.1U_0402_10V6K
C381
C426
C343
1
C287
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C340
C341
2
0.1U_0402_10V6K
1
1
C397
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C433
2
2
0.1U_0402_10V6K
1
C382
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
1
C326
2
2
0.1U_0402_10V6K
1
C222
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C286
2
1
C383
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C425
2
1
C428
2
1
C312
2
1
1
C300
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C331
2
2
1
C434
0.1U_0402_10V6K
2
1
C435
0.1U_0402_10V6K
2
0.01U_0402_16V7Z
1
C373
2
0.1U_0402_10V6K
1
C301
2
0.01U_0402_16V7Z
1
C231
2
0.1U_0402_10V6K
1
C299
C298
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C393
C332
2
2
0.1U_0402_10V6K
12
C374
1000P_0402_50V7K
1
C342
0.1U_0402_10V6K
2
12
C245
1000P_0402_50V7K
0.1U_0402_10V6K
1
2
C394
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C295
C296
C297
2
2
0.1U_0402_10V6K
1
1
C333
0.1U_0402_10V6K
2
2
ATI request
+3V
1
C406
2
ATI request
10U_0805_10V4Z
ATI request
+3V_AVDDUSB
47U_B_6.3VM
ATI request
+2.5V_AVDDCK
22U_1206_10V4Z
1
C311
2
0.1U_0402_10V6K
1
2
+3V_AVDDC
1
C359
2
1
+
C223
2
1
C193
2
0.1U_0402_10V6K
1
1
C361
2
2
0.1U_0402_10V6K
0.01U_0402_16V7Z
0.01U_0402_16V7Z
C414
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C405
2
+3VS
1
C327
2
0.01U_0402_16V7Z
+2.5VS
C334
C319
1
1
C372
C416
2
2
0.1U_0402_10V6K
ATI request
0.01U_0402_16V7Z
1
C302
C318
2
ATI request
0.01U_0402_16V7Z
1
1
C395
C396
2
2
0.01U_0402_16V7Z
+2.5V
1
C328
2
0.1U_0402_10V6K
+3VS+3V_AVDDUSB
+3VALW
12
C460
4.7U_0805_10V4Z
0.1U_0402_10V6K
1
1
C432
1
2
C417
0.1U_0402_10V6K
2
2
1
C360
2
0.01U_0402_16V7Z
1
1
C384
0.01U_0402_16V7Z
2
2
ATI request
CLOSE TO
L6,H6,J6
1
1
2
2
D32
2 1
CH751H-40_SC76
C348
0.1U_0402_10V6K
1
C404
0.01U_0402_16V7Z
2
+5VS
12
R271
1K_0402_5%
1
C210
2
1U_0603_10V4Z
+2.5V
+3V_AVDDC
+3V_AVDDUSB
+2.5VS
+5VS_VREF
+2.5V_AVDDCK
+2.5VALW
+3VALW
0.1U_0402_10V6K
+2.5VS
+3V
C436
1
1
2
2
E11
E12
E15
E7
E8
F11
F12
F15
F16
F17
F7
F8
G18
G19
H18
H19
M18
M19
N18
N19
T18
T19
U18
U19
V17
V18
W17
W18
J10
J11
J13
J14
K15
K9
L15
L9
N15
N9
P15
P9
R10
R11
R13
R14
P6
R6
V13
W13
V12
L6
H6
J6
P5
T6
U6
V9
V10
V11
W9
W10
F4
J4
K5
F3
K4
L5
D19
D1
A21
Y9
AA9
C447
0.1U_0402_10V6K
U47C
SB200 SB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
VDD_USB
VDD_USB
VDD_USB
AVDDC
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
AVDDTX0
AVDDTX1
AVDDTX2
AVDDRX0
AVDDRX1
AVDDRX2
VREF_CPU
5V_VREF
AVDD_CK
S5_2.5V
S5_3.3V
South bridge SB200
Part 3 of 3
POWER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_USB
VSS_USB
AVSSC
AVSSRX2
AVSSRX1
AVSSRX0
AVSSTX2
AVSSTX1
AVSSTX0
AVSSCK
E10
E13
E14
E6
E9
F10
F13
F14
F18
F6
F9
G6
J12
J15
J18
J19
J9
K10
K11
K12
K13
K14
K18
K19
L10
L11
L12
L13
L14
L18
L19
M10
M11
M12
M13
M14
M15
M6
M9
N10
N11
N12
N13
N14
N6
P10
P11
P12
P13
P14
P18
P19
R12
R15
R18
R19
R9
V14
V15
V16
V19
V6
V7
V8
W14
W15
W16
W19
W7
W8
H5
G5
N5
M5
J5
G4
K6
H4
F5
A22
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(3/4) - P W R
LA-2101
26 52Tuesday, November 18, 2003
1
0.1
of
Page 27
5
4
3
2
1
+3VALW +3V +3V
12
D D
PCI_AD2624,28,29,31,32
+3VS
12
R261
@10K_0402_5%
12
R252
10K_0402_5%
PWR_STRP25
SB_EEDO25
SB_EECLK25
ICH_AC_SYNC25,33,38
ICH_AC_SDOUT25,33,38
SPDIF_OUT25
MII_TXEN25
MII_TXD325
MII_TXD225
MII_TXD125
MII_TXD025
SUSCLK25
R369
10K_0402_5%
12
R366
@10K_0402_5%
REQUIRED SYSTEM STRAPS
C C
STRAP
HIGH
STRAP
LOW
+3VALW+3VS
1K_0402_5%
R421
12
C476 0.1U_0402_16V4Z
U26
5
1
2
3
TC7SH08FU_SSOP5
R416 @0_0402_5%
12
R420
B B
VCORE_PWRGD50
10K_0402_5%
R422
@1M_0402_5%
12
MANUAL
PWR ON
DEFAULT
PWR
ON
4
12
R339
@10K_0402_5%
12
R328
10K_0402_5%
IGN DEBUG SPEEDSTEP FREQLTCH
EEDO
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
R415
1 2
330K_0402_5%
C475
0.1U_0402_10V6K
VTT_PWRGD 16,25
12
R338
@10K_0402_5%
12
R318
10K_0402_5%
EECK
ROM ON
PCI BUS
ROM ON
LPC
BUS
DEFAULT
147
PG
1
2
SN74LVC14APWLE_TSSOP14
+3VS
12
R251
@10K_0402_5%
R233
10K_0402_5%
1 2
AC_SYNC
INIT ACTIVE
HIGH
INIT ACTIVE
LOW (PIII)
DEFAULT DEFAULT
65
OI
U24C
+3VS +3VS
12
R280
@10K_0402_5%
12
R279
10K_0402_5%
33MHz NB
BUS
HI SPEED
A-LINK
DEFAULT
147
PG
89
OI
330K_0402_5%
U24D
SN74LVC14APWLE_TSSOP14
+3VS
*
12
R391
1K_0402_5%
13
D
Q25
2
G
2N7002_SOT23
S
SIO 24MHzUSE
SIO 48MHzAUTO
R396
1 2
12
12
R269
@10K_0402_5%
12
R273
10K_0402_5%
0.47U_0603_16V7K
R395
47K_0402_5%
CPU_STP#
ENABLE
SPEED
STEP
DISABLE
SPEED
STEP
DEFAULT
1
C466
2
NB_PWRGD 7,9
+3V +3V +3V +3V +3V
12
R361
10K_0402_5%
12
R360
@10K_0402_5%
TX_EN
DISABLE
CPU FREQ
SETTING
DEFAULT
ENABLE CPU
FREQSETTING
147
PG
1011
OI
U24E
SN74LVC14APWLE_TSSOP14
12
R340
10K_0402_5%
12
R355
@10K_0402_5%
+3VALW+3VALW +3VALW +3VALW
147
PG
1213
OI
U24F
SN74LVC14APWLE_TSSOP14
12
R356
10K_0402_5%
12
R348
@10K_0402_5%
ETHERNET T XD[3:0 ]AC_SDOUT SPDIF_OUTPWR_STRP
PROCESSOR FR E Q M U L T I PLIER
R393 47_0603_5%
1 2
12
R353
10K_0402_5%
12
R349
@10K_0402_5%
12
R392
@10K_0402_5%
12
R384
10K_0402_5%
12
R381
@10K_0402_5%
SB_PWRGD 25
+3VALW
12
R364
10K_0402_5%
12
R354
@10K_0402_5%
32KHZ_S5
32KHZ
OUTPUT
FROM SB200
(INT RTC)
DEFAULT
32KHZ INPUT
TO SB200
(EXT RTC)
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EIT HER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(4/4) - STRAPS
LA-2101
27 52Saturday, November 22, 2003
1
0.1
of
Page 28
5
4
3
2
1
TRACE=20mil
+2.5V_LAN
R499 0_0805_5%
PCI_AD0
PCI_AD1
D D
C C
B B
A A
PCI_AD[0..31]24,27,29,31,32
IDSEL:PCI_AD17
+3V
PCI_AD[0..31]
PCI_C/BE#024,29,31,32
PCI_C/BE#124,29,31,32
PCI_C/BE#224,29,31,32
PCI_C/BE#324,29,31,32
PCI_AD19 LAN_IDSEL
PCI_PAR24,29,31,32
PCI_FRAME#24,29,31,32
PCI_IRDY#24,29,31,32
PCI_TRDY#24,29,31,32
PCI_DEVSEL#24,29,31,32
PCI_STOP#24,29,31,32
PCI_PERR#24,29,31,32
PCI_SERR#24,29,31,32
PCI_REQ#324
PCI_GNT#324
PCI_PIRQD#24,31
LAN_PME#29,31,32,39
PCIRST#23,24,29,31,32,36,39
CLK_PCI_LAN24
PM_CLKRUN#24,29,31,32,36,39
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
1 2
R545 100_0402_5%
CLK_PCI_LAN
+3V
47
46
45
43
42
41
40
39
36
35
34
33
32
30
29
28
15
14
13
12
11
10
9
8
96
93
92
91
89
87
86
85
38
27
17
84
98
24
18
19
20
21
23
25
26
83
82
80
79
57
81
97
50
6
22
37
49
90
95
CLK_PCI_LAN
U40
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
PCI I/F
C/BE#1
C/BE#2
C/BE#3
IDSEL
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
REQ#
GNT#
INTA#
INTB#
PME#
RST#
PCICLK
CLKRUN#
VDD
VDD
VDD
Power
VDD
VDD
VDD
RTL8101L_LQFP100
12
R537
@10_0402_5%
12
C667
@10P_0402_50V8K
ISOLATE#
AC_RST#
AC_SYNC
AC_DOUT
AC-Link
ROMCS/OEB
0.1U_0402_16V4Z
+2.5V_DLAN
48
VDD25
94
VDD25
AVDD25
AVDD
AVDD
AVDD
Power
EEDO
EEDI
EESK
EECS
LED0
LED1
LED2
TXD+
TXD-
RXIN+
RXIN-
LAN I/F
LWAKE
RTSET
RTT3
VCTRL
AC_DIN
AC_BCK
GPIO0
GPIO1
DGND1
DGND2
DGND3
DGND4
DGND5
AGND1
AGND2
AGND3
+2.5V_LAN
58
+3V_LAN_VDD1
59
+3V_LAN_VDD2
70
+3V_LAN_VDD3
75
LAN_EEDO
52
LAN_EEDI
53
LAN_EECLK
54
LAN_EECS
55
ACTIVITY#
78
LINK10_100#
77
76
LAN_TD+
72
LAN_TD-
71
LAN_RD+
68
LAN_RD-
67
LAN_X1
61
X1
LAN_X2
60
X2
64
74
65
63
56
1
3
4
5
7
100
99
51
69
NC
2
16
31
44
88
62
66
73
12
12
C657
C622
0.1U_0402_16V4Z
TRACE=20mil
1 2
R100 1K_0402_5%
1 2
R101 15K_0402_5%
1 2
R102 5.6K_0603_1%
LAN_X1 LAN_X2
12
C583
27P_0402_50V8J
22U_1206_10V4Z
4
3
2
1
1 2
R502
5.6K_0402_5%
2
Y2
25MHZ_20PF_6X25000017
Place closed to
RTL8101L pin58
5
6
7
8
12
C551
0.1U_0402_16V4Z
C588
27P_0402_50V8J
0.1U_0402_16V4Z
+3V
+2.5V_LAN
1
2
U37
DO
DI
SK
CS
AT93C46-10SI-2.7_SO8
B
10K
C576
0.1U_0402_16V4Z
TRACE=20mil
TRACE=20mil
TRACE=20mil
GND
NC
NC
VCC
+3V
+3VS
+3V
31
E
47K
C
C590
1 2
Q42
@2SB1197K_SOT23
reserve transistor for ver.C
12
C42
@22U_1206_10V4Z
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
C575
12
12
C574
C584
R500
49.9_0402_1%
12
12
12
C580
0.1U_0402_16V4Z
LAN_TD+
LAN_TD-
R501
49.9_0402_1%
RTL8101L has internal
+2.5V generator at pin58
+2.5V_LAN
1 2
L35
LQG21N4R7K10_0805
TRACE=30mil
49.9_0402_1%
Closed to RTL8101L Closed to Bothhand TS6121
Q44
DTA114YKA_SOT23
E
3 1
+3V
ACTIVITY#
+3V
LINK10_100#
E
3 1
47K
B
2
C
47K
B
10K
2
Q43
DTA114YKA_SOT23
C
10K
R516 300_0402_5%
Termination plane should be coupled to chassis ground
LAN Realtek RT8101L
+3V
Layout Note
TS6121 pls close to
conn.
LAN_RD+
LAN_RD-
12
R86
1 2
12
R85
49.9_0402_1%
12
C41
0.1U_0402_16V4Z
1 2
R526 300_0402_5%
RJ45_RX-
RJ45_RX+
RJ45_TXÂRJ45_TX+
12
R64
75_0402_5%
RJ45_PR
12
12
R63
75_0402_5%
1000P_1206_2KV7K
U36
1
TD+
3
TD-
2
CT
7
CT
6
RD+
8 9
RD- RX-
TS6121C_16P
C609
0.1U_0402_16V4Z
JP17
12
Amber LED+
11
Amber LED-
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
C5
@0.1U_0402_16V4Z
1 2
1
2
TX+
TX-
CT
CT
RX+
75_0402_5%
SHLD4
SHLD3
SHLD2
SHLD1
C564
16
14
15
10
11
R69
16
15
14
13
TYCO_1566203-1
LANGND
C8
4.7U_0805_10V4Z
RJ45_TX+
RJ45_TX-
RJ45_RX+
RJ45_RX-
12
12
R68
75_0402_5%
RJ45_PR
C652
0.1U_0402_16V4Z
C673
0.1U_0402_16V4Z
5
C672
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C613
0.1U_0402_16V4Z
C663
0.1U_0402_16V4Z
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
2
Compal Electronics, Inc.
Title
LAN REALTEK RTL8101L
Size Document Number Rev
LA-2101
Date: Sheet of
28 52Saturday, November 22, 2003
1
0.1
Page 29
5
4
3
2
1
+3VS
+S1_VCC
D D
VPPD030
VPPD130
VCCD0#30
VCCD1#30
N12
M12
N13
M13
U7
VPPD0
VPPD1
VCCD0#
VCCD1#
C2
AD31
C1
AD30
D4
AD29
D2
AD28
D1
AD27
E4
AD26
E3
AD25
E2
AD24
F2
AD23
F1
AD22
G2
AD21
G3
AD20
H3
AD19
H4
AD18
J1
AD17
J2
AD16
N2
AD15
M3
AD14
N3
AD13
K4
AD12
M4
AD11
K5
AD10
L5
AD9
M5
AD8
K6
AD7
M6
AD6
N6
AD5
M7
AD4
N7
AD3
L7
AD2
K7
AD1
N8
AD0
E1
CBE3#
J3
CBE2#
N1
CBE1#
N5
CBE0#
G4
PCIRST#
J4
FRAME#
K1
IRDY#
K3
TRDY#
L1
DEVSEL#
L2
STOP#
L3
PERR#
M1
SERR#
M2
PAR
A1
PCIREQ#
B1
PCIGNT#
H1
PCICLK
L8
RIOUT#_PME#
L11
SUSPEND#
F4
IDSEL
K8
MFUNC0
N9
MFUNC1
K9
MFUNC2
N10
MFUNC3
L10
MFUNC4
N11
MFUNC5
M11
MFUNC6
M10
GRST#
J9
MFUNC7
E7
VCC_SD
G5
GND_SD
E8
SDCD#
H7
MSINS#
MSCLK
SDCLK
E9F6E5F8H5H8J8G7F9G8H9
SDCMD
+3VS
1 2
12
R129
@10_0402_5%
1
C95
@18P_0402_50V8K
2
PCI_PIRQA#9,17,24,32
PCI_PIRQB#24
SERIRQ24,36,39
SD_OC#30
+SD3_VCC
PCI_AD[0..31]
PM_CLKRUN#24,28,31,32,36,39
PCI_AD20
PCI_PIRQA#
PCI_PIRQB#
SDLED#41
C708 1U_0603_10V4Z
PCI_C/BE#324,28,31,32
PCI_C/BE#224,28,31,32
PCI_C/BE#124,28,31,32
PCI_C/BE#024,28,31,32
PCIRST#23,24,28,31,32,36,39
PCI_FRAME#24,28,31,32
PCI_IRDY#24,28,31,32
PCI_TRDY#24,28,31,32
PCI_DEVSEL#24,28,31,32
PCI_STOP#24,28,31,32
PCI_PERR#24,28,31,32
PCI_SERR#24,28,31,32
PCI_PAR24,28,31,32
PCI_REQ#224
PCI_GNT#224
CLK_PCI_CB24
PCM_PME#28,31,32,39
R579 0_0402_5%
R152 @10K_0402_5%
R601 0_0402_5%
R164 0_0402_5%
R596 @10K_0402_5%
R167 0_0402_5%
R169 0_0402_5%
R187 0_0402_5%
12
MMC_DET#30
PCI_AD[0..31]24,27,28,31,32
CLK_PCI_PCM
C C
IDSEL:PCI_AD20
R606
10K_0402_5%
B B
A A
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCIRST#
CLK_PCI_PCM
1 2
R125 100_0402_5%
12
12
12
12
12
12
12
PCIRST#
12
PCM_ID
G13
A7
VCCA2
SDWP
SDCLKI
B4
VCCA1
CARDBUS
SD
MSBS
MSPWREN#
0.1U_0402_16V4Z
1
C700
2
K2
N4
L6
C8
L9
H11
D12
VCC3
VCC4
VCC5
VCC9
VCC6
VCC7
VCC8
VCC10
CAD15/IOWR#
CCBE3#/REG#
CCBE0#/CE1#
CRST#/RESET
CFRAME#/A23
CDEVSEL#/A21
CSERR#/WAIT#
CREQ#/INPACK#
CSTSCHG/BVD1_STSHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CINT#/READY_IREQ#
CAUDIO/BVD2_SPKR#
SDPWREN33#
MSDATA3
MSDATA2
MSDATA1
MSDATA0
G9
1
C718
2
0.1U_0402_16V4Z
+3VS
G1
F3
VCC2
VCC1
B2
CAD31/D10
C3
CAD30/D9
B3
CAD29/D1
A3
CAD28/D8
C4
CAD27/D0
A6
CAD26/A0
D7
CAD25/A1
C7
CAD24/A2
A8
CAD23/A3
D8
CAD22/A4
A9
CAD21/A5
C9
CAD20/A6
A10
CAD19/A25
B10
CAD18/A7
D10
CAD17/A24
E12
CAD16/A17
F10
E13
CAD14/A9
F13
CAD13/IORD#
F11
CAD12/A11
G10
CAD11/OE#
G11
CAD10/CE2#
G12
CAD9/A10
H12
CAD8/D15
H10
CAD7/D7
J11
CAD6/D13
J12
CAD5/D6
K13
CAD4/D12
J10
CAD3/D5
K10
CAD2/D11
K12
CAD1/D4
L13
CAD0/D3
B7
A11
CCBE2#/A12
E11
CCBE1#/A8
H13
B9
B11
A12
CIRDY#/A15
A13
CTRDY#/A22
B13
C12
CSTOP#/A20
C13
CPERR#/A14
A5
D13
CPAR/A13
B8
C11
CGNT#/WE#
B12
CCLK/A16
C5
D5
D11
D6
M9
SPKROUT
B5
A4
CCD2#/CD2#
L12
CCD1#/CD1#
D9
CVS2/VS2#
C6
CVS1/VS1#
D3
GND1
H2
GND2
L4
GND3
M8
GND4
K11
GND5
F12
GND6
C10
GND7
B6
GND8
J13
CRSV1/D14
E10
CRSV2/A18
A2
CRSV3/D2
H6
RSVD4
J7
RSVD3
J6
RSVD2
J5
RSVD1
E6
SDDAT0
F7
SDDAT1
F5
SDDAT2
G6
SDDAT3
CB712_ LFBGA_169P
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
S1_REG#
S1_A12
S1_A8
S1_CE1#
S1_RST
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
A16_CLK
S1_BVD1
S1_WP
S1_A19
S1_RDY#
PCM_SPK#
S1_BVD2
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D14
S1_A18
S1_D2
S1_IOWR# 30
S1_IORD# 30
S1_REG# 30
S1_WAIT# 30
S1_INPACK# 30
S1_WE# 30
S1_BVD1 30
S1_WP 30
S1_RDY# 30
PCM_SPK# 34
S1_BVD2 30
S1_VS2 30
S1_VS1 30
SD_DAT0 30
SD_DAT1 30
SD_DAT2 30
SD_DAT3 30
R189
47K_0402_5%
R604 10_0402_5%
1
2
0.1U_0402_16V4Z
+3VS
1
2
0.1U_0402_16V4Z
S1_A[0..25]
S1_D[0..15]
R208
47K_0402_5%
12
R586
47K_0402_5%
12
C108
10P_0402_50V8K
0.1U_0402_16V4Z
C684
0.1U_0402_16V4Z
C717
+S1_VCC
12
+S1_VCC
12
C713 @10P_0402_50V8K
12
0.1U_0402_16V4Z
1
1
C699
C694
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C691
C716
2
2
0.1U_0402_16V4Z
S1_A[0..25] 30
S1_D[0..15] 30
Reserved layout
for debug used.
12
R190
47K_0402_5%
S1_OE# 30
S1_CE2# 30
Reserved layout
for debug used.
12
R598
@47K_0402_5%
S1_CE1# 30
S1_RST 30
S1_A23
S1_A16
1 2
S1_CD2# 30
12
S1_CD1# 30
C157
10P_0402_50V8K
Close to CB712
CD1# and CD2#
1
C688
2
1
C706
2
1
C695
2
0.1U_0402_16V4Z
1
C709
2
0.1U_0402_16V4Z
SD_CLK30
SD_CMD30
SD_CLKIN16
R577 0_0402_5%
5
12
12
R576
@10K_0402_5%
SD_WP30
SD_PWREN#30
THIS SHEET OF ENGINEERI NG DRAW ING IS T HE PROPR IETARY PR OPERTY OF C OMP AL E L EC TR O N IC S, IN C . AN D C O NT AI N S C ON F ID EN T I AL
AND TRADE SECRET INFOR MATION . THIS SH EET MAY NOT BE T RANSFER ED FRO M THE C U ST O DY O F TH E C OM PE TE N T DI V IS IO N O F R &D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECT RONI CS, IN C. NEI THER T HIS SH E ET N O R TH E I NF O RM AT I ON I T C ON T AI N S
4
MAY BE USED BY OR DISCLOSED TO AN Y THIR D PARTY W ITHOU T PRIOR W RI T TE N C ON S EN T OF CO MP AL E L EC T RO N IC S , IN C .
3
2
Title
PCMCIA Controller ENE CB1410 & CB71 2
Size Document Number Rev
Custom
Date: Sheet
LA-2101
of
29 52Saturday, November 22, 2003
1
0.1
Page 30
CARDBUS SOCKET
SD SOCKET
S1_A[0..25]29
S1_D[0..15]29
S1_CE1#29
S1_OE#29
S1_WE#29
S1_RDY#29
+S1_VCC
+S1_VPP
S1_WP29
S1_A[0..25]
S1_D[0..15]
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP S1_CD2#
JP26
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
FOXCONN_1CA415M1-TA_68P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
72
74
76
78
80
82
84
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
PCMCIA Power Controller
+S1_VCC
13
40mil
12
11
+S1_VPP
20mil
10
1
2
15
14
8
C1610.1U_0402_16V4Z
C1620.1U_0402_16V4Z
C1324.7U_0805_10V4Z
C1600.1U_0402_16V4Z
C1674.7U_0805_10V4Z
R150
10K_0402_5%
+5VS
+5VS
+3VS
U9
9
12V
5
5V
6
5V
3
3.3V
4
3.3V
1 2
GND
7
VCC
VCC
VCC
VPP
VCCD0
VCCD1
VPPD0
VPPD1
OC
SHDN
CP-2211_SSOP16
16
VCCD0# 29
VCCD1# 29
VPPD0 29
VPPD1 29
S1_CD1# 29
S1_CE2# 29
S1_VS1 29
S1_IORD# 29
S1_IOWR# 29
+S1_VCC
+S1_VPP
S1_VS2 29
S1_RST 29
S1_WAIT# 29
S1_INPACK# 29
S1_REG# 29
S1_BVD2 29
S1_BVD1 29
S1_CD2# 29
1 2
C121 0.1U_0402_16V4Z
C120 0.1U_0402_16V4Z
1 2
C273 10U_1206_16V4Z
1 2
C122 0.01U_0402_16V7Z
1 2
C260 1U_0603_10V4Z
Close to chip
SD_CLK29
1 2
R578 22_0402_5%
C776
@10P_0402_50V8K
Close to SD socket
+3VS
R193
10K_0402_5%
1 2
SD_PWREN#29
12
2
C173
0.1U_0402_16V4Z
1
SD_WP29
SD_DAT129
SD_DAT029
SD_CMD29
SD_DAT329
SD_DAT229
MMC_DET#29
U10
1
GND
2
3
4 5
TPS2041ADR_SO8
OUT
IN
OUT
IN
OUT
EN# OC#
+SD3_VCC
12
12
12
12
R644
43K_0402_5%
SD_OC# 29
12
R653
43K_0402_5%
R649
R676
R673
43K_0402_5%
43K_0402_5%
43K_0402_5%
2
C772
0.1U_0402_16V4Z
1
8
7
6
+3VS
10K_0402_5%
1 2
Close to SD socket
R166
+3VS
12
R669
43K_0402_5%
JP4
11 10
Wr_Pt Wr_Pt_Vss
8
DAT1
7
DAT0
6
Vss2
5
SDCLK
4
Vdd
3
Vss1
2
CMD
1
DAT3
9
DAT2
SD_SOCKET
+SD3_VCC
C760
4.7U_0805_10V4Z
VSS
MMC_DET#
12
R674
43K_0402_5%
12
13
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISIO N OF R&D
DEPARTMENT EXCEP T AS AUTH ORI ZE D BY C OM PAL ELE CTRO NI CS, IN C. N EI THER THI S SH EET NOR THE I NF ORM ATI ON IT CON TAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.
Compal Electronics, Inc.
Title
PCMCIA/SD SOCKET
Size Document Number Rev
Custom
LA-2101
Date: Sheet
30 52Saturday, November 22, 2003
of
0.1
Page 31
WL_OFF#39
KILL_SW#39,41
+3VS_MINIPCI
+3VS
0_0603_5%
CLK_PCI_MINI
12
R306
@33_0402_5%
12
C368
@10P_0402_50V8K
L16
1 2
+3V
C422 0.1U_0402_16V4Z
U20
5
1
2
W=40mils
CLK_PCI_MINI24
3
TC7SH08FU_SSOP5
PCI_REQ#124
PCI_C/BE#324,28,29,32
PCI_C/BE#224,28,29,32
PCI_IRDY#24,28,29,32
PM_CLKRUN#24,28,29,32,36,39
PCI_SERR#24,28,29,32
PCI_PERR#24,28,29,32
PCI_C/BE#124,28,29,32
+5VS_MINIPCI
4
PCI_PIRQD#24,28
+5VS
+5VS_MINIPCI
CLK_PCI_MINI
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
1 2
L9 0_0603_5%
LAN RESERVED
D45
CH751H-40_SC76
W=30mils
W=30mils W=20mils
0603
PCI_AD[0..31]
PCI_AD[0..31] 24,27,28,29,32
MINI_PCI SOCKET
21
JP27
1 2
12
KEY KEY
3 4
34
5 6
56
7 8
78
9 10
910
11 12
11 12
13 14
13 14
15 16
15 16
17 18
17 18
19 20
19 20
21 22
21 22
23 24
23 24
25 26
25 26
27 28
27 28
29 30
29 30
31 32
31 32
33 34
33 34
35 36
35 36
37 38
37 38
39 40
39 40
41 42
41 42
43 44
43 44
45 46
45 46
47 48
47 48
49 50
49 50
51 52
51 52
53 54
53 54
55 56
55 56
57 58
57 58
59 60
59 60
61 62
61 62
63 64
63 64
65 66
65 66
67 68
67 68
69 70
69 70
71 72
71 72
73 74
73 74
75 76
75 76
77 78
77 78
79 80
79 80
81 82
81 82
83 84
83 84
85 86
85 86
87 88
87 88
89 90
89 90
91 92
91 92
93 94
93 94
95 96
95 96
97 98
97 98
99 100
99 100
101 102
101 102
103 104
103 104
105 106
105 106
107 108
107 108
109 110
109 110
111 112
111 112
113 114
113 114
115 116
115 116
117 118
117 118
119 120
119 120
121 122
121 122
123 124
123 124
KEYLINK_5305-4-211
TIP RING
LAN RESERVED
W=30mils
W=40mils
PCIRST#
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
C112
0.1U_0402_16V4Z
1 2
+3V
PCI_PIRQC# 24
+3V
PCIRST# 23,24,28,29,32,36,39
PCI_GNT#1 24
WLANPME# 28,29,32,39
1 2
100_0402_5%
R260
PCI_PAR 24,28,29,32
PCI_FRAME# 24,28,29,32
PCI_TRDY# 24,28,29,32
PCI_STOP# 24,28,29,32
PCI_DEVSEL# 24,28,29,32
PCI_C/BE#0 24,28,29,32
+5VS_MINIPCI
PCI_AD18
W=40mils
IDSEL : PCI_AD18
12
1 2
+3VS_MINIPCI
L17
1 2
0_0603_5%
C114
1000P_0402_50V7K
C174
0.1U_0402_16V4Z
+3VS
C146
0.1U_0402_16V4Z
1 2
C234
0.1U_0402_16V4Z
1 2
C402
0.1U_0402_16V4Z
1 2
C349
0.1U_0402_16V4Z
1 2
1
10U_1206_16V4Z
2
C217
0.1U_0402_16V4Z
1 2
+5VS_MINIPCI
C418
C324
0.1U_0402_16V4Z
1 2
+3VS_MINIPCI
1
C356
10U_1206_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
Compal Electronics, In c.
Title
MINI_PCI
Size Document Number Rev
Custom
LA-2101
Date: Sheet
of
31 52Saturday, November 22, 2003
0.1
Page 32
A
B
C
D
E
+3VS
1 2
4.7K_0402_5%
R504
1 2
10K_0402_5%
869610
CYCLEOUT/CARDBUS
DGND
DGND
DGND
REG18
R505
1 2
R503
1 2
R550
R553 4.7K_0402_5%
11
CNA
DVDD
DVDD
TEST17
TEST16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD
CPS
NC/(TPBIAS1)
NC/(TPA1+)
NC/(TPA1-)
NC/(TPB1+)
NC/(TPB1-)
R0
R1
X0
X1
FILTER0
FILTER1
SDA
SCL
PC0
PC1
PC2
TPBIAS0
TPA0+
TPA0-
TPB0 +
TPB0 -
TEST9
TEST8
TEST3
TEST2
TEST1
TEST0
DGND
TSB43AB21A_PQFP128
C591
0.1U_0402_16V4Z
4.7K_0402_5%
4.7K_0402_5%
12
15
27
39
51
59
72
88
100
7
1
2
107
108
120
106
1 2
R515
125
124
123
122
121
R116 6.34K_0603_1%
118
119
6
1394_XTLIN
5
C83
3
0.1U_0402_16V4Z
4
1 2
92
R99
91
1 2
R98
99
98
97
TPBIAS0
116
115
TPA0-
114
TPB0+
113
TPB0-
112
94
95
101
102
104
105
+3VS
1 1
2 2
IDSEL:PCI_AD16
PCI_AD16
3 3
CLK_PCI_1394
1 2
R527
PCI_AD[0..31]24,27,28,29,31
1394_IDSEL
100_0402_5%
CLK_PCI_139424
PCI_FRAME#24,28,29,31
PCI_DEVSEL#24,28,29,31
PCI_PIRQA#9,17,24,29
PM_CLKRUN#24,28,29,31,36,39
12
R552
@10_0402_5%
C675
@10P_0402_50V8K
PCI_C/BE#324,28,29,31
PCI_C/BE#224,28,29,31
PCI_C/BE#124,28,29,31
PCI_C/BE#024,28,29,31
PCI_GNT#024
PCI_REQ#024
PCI_IRDY#24,28,29,31
PCI_TRDY#24,28,29,31
PCI_STOP#24,28,29,31
PCI_PERR#24,28,29,31
1394_PME#28,29,31,39
PCI_SERR#24,28,29,31
PCI_PAR24,28,29,31
PCIRST#23,24,28,29,31,36,39
PCI_AD[0..31]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394
PCI_GNT#0
PCI_REQ#0
1394_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PIRQA#
1394_PME#
PCI_SERR#
PCI_PAR
PCIRST# TPA0+
R94
220_0402_5%
1 2
R95
220_0402_5%
1 2
U41
84
PCI_AD0
82
PCI_AD1
81
PCI_AD2
80
PCI_AD3
79
PCI_AD4
77
PCI_AD5
76
PCI_AD6
74
PCI_AD7
71
PCI_AD8
70
PCI_AD9
69
PCI_AD10
67
PCI_AD11
66
PCI_AD12
65
PCI_AD13
63
PCI_AD14
61
PCI_AD15
46
PCI_AD16
45
PCI_AD17
43
PCI_AD18
42
PCI_AD19
41
PCI_AD20
40
PCI_AD21
38
PCI_AD22
37
PCI_AD23
32
PCI_AD24
31
PCI_AD25
29
PCI_AD26
28
PCI_AD27
26
PCI_AD28
25
PCI_AD29
24
PCI_AD30
22
PCI_AD31
34
PCI_C/BE3
47
PCI_C/BE2
60
PCI_C/BE1
73
PCI_C/BE0
16
PCI_CLK
18
PCI_GNT
19
PCI_REQ
36
PCI_IDSEL
49
PCI_FRAME
50
PCI_IRDY
52
PCI_TRDY
53
PCI_DEVSEL
54
PCI_STOP
56
PCI_PERR
13
PCI_INTA/CINT
21
PCI_PME/CSTSCHG
57
PCI_SERR
58
PCI_PAR
12
PCI_CLKRUN
85
PCI_RST
14
G_RST
89
GPIO3
90
GPIO2
PLLGND1
89109
2035486278
VDDP
TSB43AB21A
/(TSB43AB22)
PCI BUS
INTERFACE
REG_EN
AGND
AGND
AGND
AGND
AGND
AGND
110
111
117
126
127
1281723303344556468758393103
VDDP
VDDP
VDDP
VDDP
AGND
DGND
DGND
REG18
0.1U_0402_16V4Z
C678
87
CYCLEIN
BIAS CURRENT
OSCILLATOR
FILTER
EEPROM 2 WIRE BUS
POWER CLASS
PHY PORT 1
DGND
DGND
DGND
DGND
+3VS
1394_PLLVDD
0.01U_0402_16V7Z
1K_0402_5%
220_0402_5%
220_0402_5%
+3VS
C601
0.1U_0402_16V4Z
1
C674
2
C681 22P_0402_50V8J
X4
24.576MHz_16P_3XG-24576-43E1
1 2
C680 22P_0402_50V8J
C602
0.1U_0402_16V4Z
L8
BLM21A601SPT_0805
1 2
C102
4.7U_0805_10V4Z
C628
0.1U_0402_16V4Z
+3VS
Place very close to U36.5
1394_XTLIN
1
2
220P_0402_50V7K
R551 @10_0402_5%
R542
56.2_0603_1%
R528
56.2_0603_1%
C627
1 2
+3VS
C676
1000P_0402_50V7K
R533
56.2_0603_1%
R523
56.2_0603_1%
R518
5.11K_0603_1%
C638
0.1U_0402_16V4Z
1394_XCLK 36
1
C670
0.33U_0603_16V4Z
2
C651
0.1U_0402_16V4Z
C59
1000P_0402_50V7K
JP21
4
4
3
3
2
2
1
1
FOX_UV31413-T1
C75
0.1U_0402_16V4Z
C86
1000P_0402_50V7K
C77
0.1U_0402_16V4Z
C84
1000P_0402_50V7K
C677
0.1U_0402_16V4Z
C54
1000P_0402_50V7K
4 4
Compal Electronics, In c.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
1394 Interface
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
32 52Saturday, November 22, 2003
E
0.1
Page 33
5
U25A
13
74HCT4066
U25C
5
74HCT4066
L18
L50
LINEIN_L
LINEIN_R
CD_L
CD_R
C_MD_SPK
R302
1 2
22_0402_5%
R296
1 2
22_0402_5%
+5VALWP
POWER ON PATH
AMP_RIGHT
U49
14
15
16
17
23
24
18
20
19
C_MIC
21
22
13
12
12
11
10
45
46
47
48
DGND
C294
@0.1U_0402_16V4Z
SUSP#35,39,40,43
EC_IDERST_1EC_IDERST
+AVDD_AC97
25
AVDD1
AUX_L
AUX_R
JD2
JD1
LINE_IN_L
LINE_IN_R
CD_L
CD_R
CD_GND
MIC1
MIC2
PHONE
PC_BEEP
RESET#
SYNC
5
SDATA_OUT
NC
XTLSEL
SPDIFI/EAPD
SPDIFO
4
DVSS1
7
DVSS2
ALC250_LQFP48
SUSP#
+5VALWP
+5VAMP
D D
+5VAMP
R424
1M_0402_5%
R698
1M_0402_5%
EC_IDERST35,39
AC97 Codec
C C
C423
0.1U_0402_16V4Z
AC97_L AMP_LEFT
12
12
R423
1M_0402_5%
AC97_R
12
12
R697
1M_0402_5%
+5VAMP
+VDDA
*
1 2
R350 0_0402_5%
@0.01U_0402_25V4Z
C784
R670
@10K_0402_5%
MONO_IN34
ICH_AC_RST#25,38
ICH_AC_SYNC25,27,38
ICH_AC_SDOUT25,27,38
R326
@0_0402_5%
1 2
R671
10K_0402_5%
1 2
2N7002_SOT23
13
D
Q54
2
G
S
5
D62 @RB751V_SOD323
12
NBA_PLUG34,40
MIC34
MD_SPK38
B B
A A
EC_IDERST_1
1
C794
0.1U_0402_10V6K
2
+5VALWP
14
1 2
7
+5VALWP
14
4 3
7
1 2
CHB2012U170_0805
1 2
@CHB2012U170_0805
1
C429
10U_1206_16V4Z
2
1 2
C775 @1U_0603_10V4Z
21
CD_GNA
1 2
C399 1U_0603_10V4Z
1 2
C413 1U_0603_10V4Z
R672
1 2
0_0402_5%
EC_IDERST
1 2
C785 1U_0603_10V4Z
R655 22_0402_5%
EAPD34
C281
@4.7U_0805_10V4Z
4
INT_CD_L
+5VAMP
INT_CD_R
+5VAMP
R692 0_0402_5%
1 2
38
AVDD2
MONO_OUT/VREFOUT3
1
LINE_OUT_L
LINE_OUT_R
HP_OUT_L
HP_OUT_R
BIT_CLK
SDATA_IN
XTL_IN
XTL_OUT
AFILT1
AFILT2
VREFOUT
VREF
DCVOL
VREFOUT2
VAUX
AVSS1
AVSS2
Adjustable O u tp u t
U17
4
2
7 1
8
@SI9182DH-AD_MSOP8
4
C824
1U_0603_10V4Z
1 2
12
1M_0402_5%
9
DVDD1
DVDD2
NC
SCK
SDA
NC
R695
R694
1M_0402_5%
12
R696
1M_0402_5%
C823
1U_0603_10V4Z
1 2
12
12
R693
1M_0402_5%
C769
0.1U_0402_16V4Z
C802 @1000P_0402_50V7K
C443 @1000P_0402_50V7K
LINEL AC97_L
35
LINER
36
37
39
41
6
8
2
3
29
30
28
27
32
31
33
34
43
44
40
26
42
1 2
C452 1U_0603_10V4Z
1 2
C809 1U_0603_10V4Z
1 2
C350 @15P_0402_50V8J
1 2
R657
1 2
R656 22_0402_5%
@1M_0402_5%
C438 1000P_0402_50V7K
C437 1000P_0402_50V7K
1 2
R359 0_0402_5%
1 2
R368 @0_0402_5%
AGND
AGND
VOUT
SENSE
GND
5
6
3
VIN
DELAY
ERROR CNOISE
ON/OFF#
+5VALWP
14
11 10
7
+5VALWP
14
8 9
7
+3VS
1
C377
10U_1206_16V4Z
2
22_0402_5%
1 2
R294 @10K_0402_5%
R298
1 2
+AUD_VREF
R336
1 2
@0_0603_5%
Place very close to U44.2
AC97_XTLIN
R297 @10_0402_5%
C759
@0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DIRECT PLAY PATH
AMP_LEFT
U25B
12
74HCT4066
AMP_RIGHT
U25D
6
74HCT4066
AC97_R
AC97_XTLIN
24.576MHz_16P_3XG-24576-43E1
+AVDD_AC97
1 2
1 2
1
C767
22P_0402_50V8J
2
1
1
C454
2
2
1U_0603_10V4Z
R654
@69.8K_0603_1%
1 2
R651
@24K _0402_1%
12
X5
C801
0.01U_0402_16V7Z
+VDDA
3
AMP_LEFT 34
AMP_RIGHT 34
ICH_AC_BITCLK 25,38
ICH_AC_SDIN0 25
1
C768
22P_0402_50V8J
2
1
C800
C811
2
1U_0603_10V4Z
0.1U_0402_16V4Z
AC97_XCLK 36
+VDDA
C362
@4.7U_0805_10V4Z
+5VALWP TO +5VLDO
CD_PLAY35,39
+5VAMP DECOUPLING
+5VLDO
1
1
C190
C177
22U_1206_10V4Z
2
2
4.7U_0805_10V4Z
Audio Signal Bias Circuit
R408 6.8K_0402_5%
LINE_IN_L34
LINE_IN_R34
1
2
INT_CD_L35
INT_CD_R35
C810
1U_0603_10V4Z
CD_AGND To CD_GNA Bypass
R407 6.8K_0402_5%
R414 6.8K_0402_5%
R413 6.8K_0402_5%
R686 20K_0402_1%
R684 20K_0402_1%
R685 6.8K_0402_5%
R687 6.8K_0402_5%
CD_AGND35
CD_PLAY
(4.5V)
1
C205
2
@4.7U_0805_10V4Z
2
10K_0402_5%
2N7002_SOT23
Q50
1
C246
2
1U_0603_10V4Z
12
12
12
12
12
12
12
12
R335
20K_0402_1%
12
R320
0_0402_5%
2
R295 10K_0402_5%
1 2
+5VALWP
12
R642
13
2
G
1
C266
2
@1U_0603_10V4Z
C448 1U_0603_10V4Z
C440 1U_0603_10V4Z
C806 1U_0603_10V4Z
C796 1U_0603_10V4Z
12
12
+12VALW
2
G
D
S
1
2
0.1U_0402_10V6K
1 2
1 2
1 2
1 2
CD_GNA
R334
6.8K_0402_5%
1
+5VALWP
*
2
*
12
R257
1K_0402_5%
2N7002_SOT23
13
D
Q18
S
1
2
C325
1U_0603_10V4Z
@1U_0805_25V4Z
SI4800DY_SO8
1
C264
2
LM431SC_SOT23
1
A
D61
U14
K
R
1 3
5
D
G
4
2
3
Q21
AOS 3401_SOT23
876
DDD
SSS
123
+5VLDO
12
R646
3.9K_0603_1%
12
R641
4.99K_0603_1%
+5VALWP DECOUPLING
+5VALWP
1
C221
C220
2
@0.1U_0402_10V6K
1
C762
2
22U_1206_10V4Z
@22U_1206_10V4Z
1
1
2
C763
C756
2
1U_0603_10V4Z
DGND To AGND Bypass
LINEIN_L
LINEIN_R
CD_L
CD_R
DGND
Analog Reference V
+AUD_VREF
C444
0.1U_0402_16V4Z
+5VALWP TO +5VLDO
+5VLDO +5VAMP
CHB2012U170_0805
CHB2012U170_0805
Compal Electronics, In c.
Title
AC97 Codec
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
1
C455
2
1U_0603_10V4Z
L49
1 2
L46
1 2
1
AGND
1U_0603_10V4Z
33 52Saturday, November 22, 2003
(4.5V)
1
C749
2
0.1
Page 34
A
Audio Amplifier
W=40Mil
C836
C830
12
4 4
VOL_AMP40
AMP_LEFT33
AMP_RIGHT33
3 3
AMP_LEFT
0.47U_0603_16V7K
AMP_RIGHT
0.47U_0603_16V7K
AMP_LEFT
0.47U_0603_16V7K
AMP_RIGHT
0.47U_0603_16V7K
INTSPK_L1
INTSPK_R1
C826
1 2
C837
1 2
C825
1 2
C835
1 2
12
12
R426
1.5K_0603_5%
fo=1/(2*3.14*R*C)=225Hz
R=1.5K / C=0.47U
NBA_PLUG
VOL_AMP
1 2
1U_0603_10V4Z
1 2
1U_0603_10V4Z
R702
1.5K_0603_5%
0.1U_0402_16V4Z
C833
C838
HP_L
HP_R
0.1U_0402_16V4Z
+5VAMP
12
C829
0.047U_0402_16V4Z
B
12
C831
4.7U_0805_10V4Z
U31
7
PVDD
18
PVDD
19
VDD
2
PC-ENABLE
3
VOLUME
4
LOUT+
21
ROUT+
5
LLINEIN
23
RLINEIN
6
LHPIN
20
RHPIN
17
CLK
SHUTDOWN#
TPA0232
SE/BTL#
PC-BEEP
BYPASS
LOUT-
ROUT-
GND
GND
GND
GND
22
15
14
11
9
16
10
LIN
8
RIN
1
12
13
24
+5VAMP
SHUTDOWN#
100K_0402_5%
NBA_PLUG
C485 0.1U_0402_16V4Z
C481
0.47U_0603_16V7K
R433
+5VAMP
1 2
INTSPK_L2
INTSPK_R2
2
1
D
S
C828
0.47U_0603_16V7K
12
R701
100K_0402_5%
Q34
2N7002_SOT23
13
1 2
2
G
12
R449
10K_0402_5%
2
C827
1
0.47U_0603_16V7K
C
R307 0_0402_5%
Left Speaker Connector
EAPD 33
Right Speaker Connector
LINE IN JACK
@V-PORT-0603-220 M-V05_0603
@V-PORT-0603-220 M-V05_0603
LINE_IN_R33
LINE_IN_L33
D
D68
INTSPK_L1
INTSPK_L2
INTSPK_R1
INTSPK_R2
L52
1 2
FBM-11-160808-700T_0603
1 2
L51
FBM-11-160808-700T_0603
2 1
D64
2 1
330P_0402_50V7K
D67
@V-PORT-0603-220 M-V05_0603
L58 FBM-11-160808-121-T_0603
2 1
1 2
1 2
L57 FBM-11-160808-121-T_0603
L55 FBM-11-160808-121-T_0603
1 2
1 2
L54 FBM-11-160808-121-T_0603
D63
@V-PORT-0603-220 M-V05_0603
2 1
LINE_IN_R-1
LINE_IN_L-1
C821
12
12
C822
330P_0402_50V7K
E
JP12
1
2
ACES_85204-0200
JP11
1
2
ACES_85204-0200
JP29
5
4
3
6
2
1
FOXCONN JA6033L-5S1-TR
HEADPHONE OUT JACK
EC Beep
BEEP#39
9 8
2 2
CardBus Beep
PCM_SPK#29
PCI Beep
SPKR25
1 1
+3V
12
R639
100K_0402_5%
10
U44C
R619
8.2K_0402_5%
1 2
OE#
IO
SN74LVC125APWLE_TSSOP14
+3V POWER
+3V
147
PG
43
OI
+3V POWER
U45B
SN74LVC14APWLE_TSSOP14
+3V
1
C728
0.22U_0603_16V4Z
2
C732
1 2
1U_0603_10V4Z
C740
1 2
1U_0603_10V4Z
1 2
C189
0.1U_0402_16V4Z
147
U45A
SN74LVC14APWLE_TSSOP14
PG
21
OI
+3V POWER
1 2
R626
560_0402_5%
1 2
R635
560_0402_5%
R633
10K_0402_5%
1U_0603_10V4Z
12
1 2
C733
1 2
R629
560_0402_5%
D31
CH751H-40_SC76
2 1
System Beep To AC97' Codec
+AVDD_AC97
12
R352
10K_0402_5%
1
2
12
R345
10K_0402_5%
1
Q23
3
MMBT3904_SOT23
C407
10U_1206_16V4Z
2
1 2
C385
1 2
1U_0603_10V4Z
R346
2.4K_0402_5%
MONO_IN
MONO_IN 33
C501
150U_D2_6.3VM
+
INTSPK_R1-2INTSPK_R1 INTSPK_R1-4
1 2
+
INTSPK_L1-2INTSPK_L1 INTSPK_L1-4
1 2
C847
150U_D2_6.3VM
R450
47_0402_5%
1 2
1 2
R451
47_0402_5%
MICROPHONE IN JACK
R706
@18K_0603_1%
+5VAMP
MIC33
1 2
1 2
R703
@18K_0603_1%
@100K_0402_5%
FBM-11-160808-700T_0603
R711
L53
1 2
INTSPK_R1-3
INTSPK_L1-3
12
NBA_PLUG33,40
L22
1 2
FBM-11-160808-700T_0603
1 2
L21
FBM-11-160808-700T_0603
C843
@1U_0603_10V4Z
MIC-1MIC
220P_0402_50V7K
C502
330P_0402_50V7K
+5VAMP
2
R707
@2.2K_0402_5%
C840
NBA_PLUG
12
12
330P_0402_50V7K
1
Q56
@2SC2411K-CQ_SOT23
3
R708
12
12
2.2K_0402_5%
1
2
JP31
5
4
3
6
2
1
FOXCONN JA6033L-5S1-TR
C503
1 2
R710 0_0402_5%
JP30
5
4
3
6
2
1
FOXCONN JA6033L-5S1-TR
+AUD_VREF
PROPRIETARY NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
A
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Compal Electronics, In c.
Title
AMP & Audio Jack
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
34 52Saturday, November 22, 2003
E
0.1
Page 35
IDE_PDD7
IDE_PDD6
IDE_PDD10
IDE_PDD4
IDE_PDD9
IDE_PDD12
IDE_PDD2
IDE_PDD3
IDE_PDD11
IDE_PDD0
IDE_PDD14
IDE_PDD1
IDE_PDIOW#25
IDE_PDDREQ25
IDE_PDA225
IDE_PDA125
IDE_PDA025
IDE_PDIOR#25
IDE_PDCS3#25
IDE_PDCS1#25
IDE_PDDACK#25
INT_IRQ1425
IDE_SDCS1#25
IDE_SDCS3#25
IDE_SDA025
IDE_SDDACK#25
IDE_SDIOW#25
IDE_SDA125
IDE_SDDREQ25
IDE_SDA225
IDE_SDIOR#25
INT_IRQ1525
IDE_PDIOW#
IDE_PDD13
IDE_PDDREQ
IDE_PDA2
IDE_PDA1
IDE_PDA0
IDE_PDIOR#
IDE_PDD15
IDE_PDCS3#
IDE_PDCS1#
IDE_PDDACK#
IDE_SDD5
IDE_SDD10
IDE_SDD9
IDE_SDD12
IDE_SDD3
IDE_SDD14
IDE_SDCS1#
IDE_SDCS3#
IDE_SDA0
IDE_SDDACK#
IDE_SDIOW#
IDE_SDD1
IDE_SDA1
IDE_SDDREQ
IDE_SDA2
IDE_SDD15
IDE_SDD13
IDE_SDIOR#
IDE_SDD11
IDE_SDD0
IDE_SDD2
IDE_SDD4
IDE_SDD6
1 8
2 7
3 6
4 5
RP67 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP66 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP65 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP64 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP63 33_0804_8P4R_5%
1 2
R690 33_0402_5%
1 8
2 7
3 6
4 5
RP62 33_0804_8P4R_5%
1 2
R437 33_0402_5%
1 8
2 7
3 6
4 5
RP46 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP45 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP44 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP54 33_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP53 33_0804_8P4R_5%
1 2
R394 33_0402_5%
1 8
2 7
3 6
4 5
RP52 33_0804_8P4R_5%
INT_IRQ15
1 2
R406 33_0402_5%
PD_D8IDE_PDD8
PD_D7
PD_D6
PD_D5IDE_PDD5
PD_D10
PD_D4
PD_D9
PD_D12
PD_D2
PD_D3
PD_D11
PD_D0
PD_D14
PD_D1
PD_PDIOW#
PD_D13
PD_PDDREQ
PD_PDA2
PD_PDA1
PD_PDA0
PD_PDIOR#
PD_D15
PD_PDCS3#
PD_PDCS1#
PD_PDDACK#
PD_IRQ14INT_IRQ14
1 2
R445 8.2K_0402_5%
SD_D7IDE_SDD7
SD_D8IDE_SDD8
SD_D5
SD_D10
SD_D9
SD_D12
SD_D3
SD_D14
SD_SDCS1#
SD_SDCS3#
SD_SDA0
SD_SDDACK#
SD_SDIOW#
SD_D1
SD_SDA1
SD_SDDREQ
SD_SDA2
SD_D15
SD_D13
SD_SDIOR#
SD_D11
SD_D0
SD_D2
SD_D4
SD_D6
SD_IRQ15
1 2
R412 8.2K_0402_5%
SB_PCI_RST#
+5VS
HDD CONNECTOR
IDE_PDD[0..15]25
+5VCD
+3VALW
10K_0402_5%
R436
G_PCI_RST#
13
D
2N7002_SOT23
2
Q32
G
S
1 2
R409 100K_0402_5%
** 1029:
Change U4D to U76D
IDE_PDD[0..15]
PIDE_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
PD_PDDREQ
PD_PDIOW#
PD_PDIOR#
PD_PDIORDY
PD_PDDACK#
PD_IRQ14
PD_PDA1
PD_PDA0
PHDD_LED#39
+5VS
@10K_0402_5%
SHDD_LED#39
SHDD_LED#
R444
*
PD_PDCS1#
1 2
100K_0402_5%
INT_CD_L33 INT_CD_R 33
CD_AGND33
R400
SD_SDCS1#
SD_SDCS3#
+5VS
IDE_SDD[0..15]25
INT_CD_L INT_CD_R
CD_AGND
SIDE_RST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_SDIOW#
SD_SDIORDY
SD_IRQ15
SD_SDA1
SD_SDA0
SW_IDE_SDCS1#
SHDD_LED#
+5VCD
R410
470_0402_5%
1 2
G_PCI_RST#
C4890.1U_0402_16V4Z
G_PCI_RST#
SN74LVC125APWLE_TSSOP14
JP10
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
ALLTOP_C17826-14401
JP28
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
ALLTOP_C12424-25001
+3VALW
1
U28A
14
P
2 3
OE#
IO
7
G
SN74LVC125APWLE_TSSOP14
4
U28B
5 6
OE#
IO
IDE_SDD[0..15]
+5VCD
PCSEL
PD_PDCS3#
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_SDDREQ
SD_SDIOR#
SD_SDDACK#
R397 100K_0402_5%
1 2
SD_SDA2
SW_IDE_SDCS3#
1 2
C477 0.1U_0402_10V6K
10K_0402_5%
R435
SW_IDE_SDCS1#
+5VCD
10K_0402_5%
R430
SW_IDE_SDCS3#
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
1 2
R446
PD_PDA2
+5VS
470_0402_5%
+5VCD
+5VCD
+5VCD
@10K_0402_5%
R398
SB_PCI_RST#24
** 1028:
Remove R825
Short when not support SW DJ
Net width should be 60mil w id e
+5VCD
C470
1000P_0402_50V7K
Place component's closely MODULE CONNECTOR.
+5VALWP
+5VALWP
Placea caps. near HDD
CONN.
+5VS
C494
1000P_0402_50V7K
1
C473
4.7U_0805_10V4Z
2
+5VS
W=80mils
PIDERST#25
SIDERST#25
1 2
R442
SUSP#33,39,40,43
*
PAD-OPEN 4x4m
1 2
U27
1
2
3 6
240K_0402_5%
C490
1 2
1U_0805_16V7K
SUSP# CD_PLAY
@DTC124EK_SOT23
1
C497
10U_1206_16V4Z
2
1
C474
1U_0805_16V7K
2
C500
0.1U_0402_16V4Z
SB_PCI_RST#
SB_PCI_RST#
74HCT08PW_TSSOP14
+5VCD
PJP15
8
7
5
SI4835DY_SO8
4
R443 10K_0402_5%
22K
2
22K
Q33
1
C496
10U_1206_16V4Z
2
C471
0.1U_0402_16V4Z
U29A
147
1
2
9
10
13
12
EC_IDERST33,39
PG
I0
3
O
I1
74HCT08PW_TSSOP14
** 1029:
Change U4D to U76D
U29C
I0
8
O
I1
10K_0402_5%
1
C480
10U_1206_16V4Z
2
1
C495
1U_0805_16V7K
2
C472
4.7U_0805_10V4Z
12 11
*27
SN74LVC125APWLE_TSSOP14
R434
13
22K
2
22K
Q35
DTC124EK_SOT23
C493
0.1U_0402_16V4Z
74HCT08PW_TSSOP14
13
U28D
OE#
IO
C479
0.1U_0402_16V4Z
2
C482
10U_1206_16V4Z
1
U29B
4
I0
PIDE_RST#
6
O
5
I1
R448 @0_0402_5%
SIDE_RST#
R427
10K_0402_5%
+5VCD
CD_PLAY 33,39
+5VALWP
2
C486
1U_0805_16V7K
1
PCMRST# 39
+3VS
R447
4.7K_0402_5%
1 2
IDE_PDIORDY25
1 2
R438 33_0402_5%
1 2
R440 10K_0402_1%
1 2
R439 5.6K_0402_5%
PD_PDIORDY
PD_D7
PD_PDDREQ
IDE_SDIORDY25
1 2
R404 33_0402_5%
+3VS
1 2
1 2
R411 10K_0402_1%
1 2
R399 5.6K_0402_5%
R405
4.7K_0402_5%
SD_SDIORDY
SD_SDDREQ
SD_D7
Compal Electronics, I n c.
Title
IDE/ FDD MODULE CONN.
Size Document Number Rev
C
LA-2101
Date: Sheet
of
35 52Saturday, November 22, 2003
0.1
Page 36
A
SUPER I/O SMsC FDC47N217
B
C
D
E
*
1 1
2 2
3 3
4 4
LPC_AD[0..3]24,39
SERIRQ24,29,39
SYS_XCLK16
EXT_SSIN17
LPC_AD[0..3]
LPC_FRAME#24,39
LPC_DRQ1#24
PCIRST#23,24,28,29,31,32,39
+3VS
+3VS
FIR_EN#37
1 2
R218 10K_0402_5%
PM_CLKRUN#24,28,29,31,32,39
CLK_PCI_SIO24
R229 10K_0402_5%
CLK_14M_SIO16
R198
+3VS
10K_0402_5%
+3VS
R181 1K_0402_5%
R180 10K_0402_5%
+3VS
R660 10_0402_5%
+3VS
1 2
1 2
R194 10K_0402_5%
10K_0402_5%
R179
10K_0402_5%
R177
12
+3V_CLK
R661 10_0402_5%
+3V_CLK
12
12
12
12
12
C787
+3V_CLK
12
1
C757
0.1U_0402_16V4Z
2
C786 10P_0402_50V8K
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#1
SIO_PD#
PM_CLKRUN#
CLK_PCI_SIO
SERIRQ
SIO_PME#
CLK_14M_SIO
RP15 4.7K_8P4R_1206_5%
PID0
45
PID1
36
PID2
27
PID3
18
FIR_EN#
BTDET#
SIO_GPIO11
SIO_SMI#
SIO_GPIO23
1 2
1 2
EC_SMB_CK25,39
EC_SMB_DA25,39
PTALIN
12
X6
14.31818MHZ_20P
PTALOUT
10P_0402_50V8K
R665@1K_0402_5%
12
R6591K_0402_5%
12
1
C782
0.1U_0402_16V4Z
2
U12
10
LAD0
12
LAD1
13
LAD2
14
LAD3
15
LFRAME#
16
LDRQ#
17
PCI_RESET#
18
LPCPD#
19
CLKRUN#
20
PCI_CLK
21
SER_IRQ
6
IO_PME#
9
CLK14
CLOCK
23
GPIO40
24
GPIO41
25
GPIO42
27
GPIO43
28
GPIO44
29
GPIO45
30
31
32
33
34
35
36
40
8
22
43
52 45
12
C7510.1U_0402_16V4Z
PCLK_SSOUT PCLK_SSOUT
PCLK_SSIN
GPIO
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23
VSS
VSS
POWER
VSS
VSS VCC
LPC47N217_STQFP64
U48
2
X1
3
X2
7
REF1
8
VDD
5
GND
6
INPUT_SEL/REF0
4
CLKIN
13
CLK0
27
SCLK
26
SDATA
28
AVDD
14
VDD
1
GND
12
GND
@ICS960011
SERIAL I/F
FIR
LPC I/F
IRMODE/IRRX3
PARALLEL I/F
24.576MHz
RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#
IRRX2
IRTX2
INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
BUSY
ACK#
ERROR#
ALF#
STROBE#
VTR
VCC
VCC
VCC
VDD
GND
CLK1
CLK2
VDD
VDD
GND
CLK3
VDD
GND
CLK4
VDD
GND
PE
RXD1
62
TXD1
63
DSR#1
64
RTS#1
1
CTS#1
2
DTR#1
3
RI#1
4
DCD#1
5
IRRX
37
IRTXOUT
38
IRMODE
39
41
42
LPD0
44
LPD1
46
LPD2
47
LPD3
48
LPD4
49
LPD5
50
LPD6
51
LPD7
53
LPTSLCT
55
LPTPE
56
LPTBUSY
57
LPTACK#
58
LPTERR#
59
LPTAFD#
60
LPTSTB#SIO_IRQ
61
7
11
26
54
C192
4.7U_0805_10V4Z
R666 10_0402_5%
10
9
11
C754 0.1U_0402_16V4Z
16
18
15
19
17
VGA_PCLK
21
20
22
24
R648 10_0402_5%
25
23
12
0.1U_0402_16V4Z
12
1 2
1 2
C753 0.1U_0402_16V4Z
1 2
C788 0.1U_0402_16V4Z
1 2
C752 0.1U_0402_16V4Z
+3V_CLK
+3V_CLK
+3V_CLK
12
+3V_CLK
1 2
R212 1K_0402_5%
LPD[0..7]
12
C153
0.1U_0402_16V4Z
AC97_XCLK 33
*27
R650 10_0402_5%
R643 10_0402_5%
1394_XCLK 32
IRRX 37
IRTXOUT 37
IRMODE 37
INIT# 38
SLCTIN# 38
LPD[0..7] 38
LPTSLCT 38
LPTPE 38
LPTBUSY 38
LPTACK# 38
LPTERR# 38
LPTAFD# 38
LPTSTB# 38
C191
12
12
12
0.1U_0402_16V4Z
C250
VGA_XCLK 17
DSR#1
CTS#1
RI#1
DCD#1
4.7K_8P4R_1206_5%
IRRX
1 2
10K_0402_5%
CLK_PCI_SIO
+3VS
12
R178
RP19
18
27
36
45
R214
@33_0402_5%
1 2
C208
1
@22P_0402_25V8K
2
+5V+3VS
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
CLK_14M_SIO
JP18
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
@96212-1011S
R241
@10_0402_5%
1 2
12
C270
@15P_0402_50V8J
Compal Electronics, In c.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
SUPER I/O
Size Document Number Rev
Custom
LA-2101
Date: Sheet
36 52Saturday, November 22, 2003
E
of
0.1
Page 37
C538
@150U_D2_6.3VM
+
1
2
+5V
12
C540
0.1U_0402_16V4Z
U33
1
GND
2
IN
3
EN1#
4
EN2#
TPS2042ADR_SO8
OC1#
OUT1
OUT2
OC2#
8
7
6
5
+USB_AS
+USB_BS
+3V
12
R490
100K_0402_5%
12
R491
100K_0402_5%
1 2
R489
47_0402_5%
1 2
R493
47_0402_5%
USB_OC2#
USB_OC4#
12
C562
0.1U_0402_16V4Z
12
C563
0.1U_0402_16V4Z
USB_OC2# 25
USB_OC4# 24
+USB_AS
12
C539
+
150U_D2_6.3VM
USBP2-25
USBP2+25
Keep 20 mils minimum spacing
USBP4-25
USBP4+25
USBP2ÂUSBP2+
USBP4-
USBP4+
C536
0.1U_0402_16V4Z
@V-PORT-0603-220 M-V05_0603
L32
2 3
1 4
@JTS0402-03_4P
L33
2 3
1 4
@JTS0402-03_4P
USB2ÂUSB2+
USB4ÂUSB4+
D9
D6
D8
@V-PORT-0603-220 M-V05_0603
2 1
2 1
D7
USB
CONNECTOR
JP16
1
2
3
4
5
6
7
SUYIN_2553A-08G1T-D_8P
8
C504
@150U_D2_6.3VM
12
C487
4.7U_0805_10V4Z
1
C834
220P_0402_50V7K
2
+
1
2
+5V
12
C842
0.1U_0402_16V4Z
+3VS
R700
47_1206_5%
1 2
12
C832
0.1U_0402_16V4Z
+IR_VCC
+IR_GND
U53
1
GND
2
3
4 5
TPS2041ADR_SO8
OUT
IN
OUT
IN
OUT
EN# OC#
FIR Module
IRRX36
FIR_EN#36
FIR_EN#
LOW FIR Poped
HIGH FIR Un-Poped
+USB_CS
8
7
6
IRRX
1 2
R205 0_0402_5%
+3V
12
R704
100K_0402_5%
U52
2
IRED_C
4
RXD
6
VCC
8
GND
TFDU6102-TR3_8P
12
C839
0.1U_0402_16V4Z
C483
22U_1206_10V4Z
+IR_ANODE
1
IRTXOUT
3
IRMODE
5
7
USB_OC0#
1 2
R699
@3.3_1206_5%
1 2
R428
3.3_1206_5%
IRTXOUT 36
IRMODE 36
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
1 2
R705
47_0402_5%
+3VS
1
2
IRED_A
TXD
SD/MODE
MODE
The component's most place
cloely IRDA MODULE.
USB_OC0# 25
+IR_ANODE
USBP0-25
USBP0+25
C24
@0.1U_0402_16V4Z
@0.1U_0402_16V4Z
USB4-
C23
USBP0ÂUSBP0+
C26
@0.1U_0402_16V4Z
C25
@0.1U_0402_16V4Z
@V-PORT-0603-220 M-V05_0603
L56
2 3
1 4
@JTS0402-03_4P
@V-PORT-0603-220 M-V05_0603
USB2-
@0.1U_0402_16V4Z
USB2+USB4+
@0.1U_0402_16V4Z
+USB_BS
+
C844
C841
12
C541
150U_D2_6.3VM
+USB_CS
+
USB0ÂUSB0+
USB0-
USB0+
2 1
12
C846
150U_D2_6.3VM
D65
USBP0+
USBP2ÂUSBP2+
USBP4ÂUSBP4+
@V-PORT-0603-220 M-V05_0603
2 1
C532
0.1U_0402_16V4Z
C845
0.1U_0402_16V4Z
USB
CONNECTOR
JP32
D66
@V-PORT-0603-220 M-V05_0603
2 1
2 1
1 2
R712 0_0402_5%
1 2
R709 0_0402_5%
1 2
R480 0_0402_5%
1 2
R481 0_0402_5%
1 2
R482 0_0402_5%
1 2
R483 0_0402_5%
1
VBUS
2
D-
3
D+
4
GND
TYCO_3-1470859-1
USB0-USBP0-
USB0+
USB2-
USB2+
USB4-
USB4+
S_GND
S_GND
5
6
Compal Electronics, In c.
Title
USB Conn.
Size Document Number Rev
Custom
LA-2101
Date: Sheet
of
37 52Saturday, November 22, 2003
0.1
Page 38
FD5
FIDUCAL
FD6
FIDUCAL
FD4
FIDUCAL
FD1
FIDUCAL
FD3
FIDUCAL
FD2
FIDUCAL
MDC CONN.
JP20
12
34
56
78
910
11 12
13 14
+3V
R519 0_0402_5%
+3VS
ICH_AC_SDOUT25,27,33
ICH_AC_RST#25,33
+3V_MDC
1
2
+3V_MDC
+3VS_MDC
1 2
L39 CHB1608B121_0603
R541
1 2
22_0402_5%
R546
1 2
22_0402_5%
C625
1U_0805_16V7K
+3VS_MDC
1
2
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
AMP 3-1565120-0 30P H:9MM
+5VS_MDC
C649
1U_0805_16V7K
1
C604
1U_0805_16V7K
2
+5VS_MDC
R521
1 2
22_0402_5%
1
C665
@15P_0402_50V8J
2
1 2
L37 CHB1608B121_0603
R517
1 2
R524 0_0402_5%
12
10K_0402_5%
1 2
R531
MD_SPK 33
+3VS
ICH_AC_SYNC 25,27,33
1 2
R525 22_0402_5%
22_0402_5%
+5VS
1
C614
2
220P_0402_50V7K
ICH_AC_SDIN1 25
ICH_AC_BITCLK 25,33
1
CF18
SMD40M80
1
CF2
SMD40M80
1
CF1
SMD40M80
1
CF22
SMD40M80
1
CF4
SMD40M80
1
CF14
SMD40M80
1
CF7
SMD40M80
1
CF5
SMD40M80
1
CF3
SMD40M80
1
CF9
SMD40M80
1
CF8
SMD40M80
1
CF21
SMD40M80
1
CF6
SMD40M80
1
CF20
SMD40M80
1
CF19
SMD40M80
1
CF24
SMD40M80
1
CF23
SMD40M80
1
CF16
SMD40M80
PARALLEL PORT
INIT#36
SLCTIN#36
LPD[0..7]36
1 2
R8
1 2
R9
LPD[0..7]
LPTINIT#
33_0402_5%
LPTSLCTIN#
33_0402_5%
1
CF13
SMD40M80
1
+5V_PRN
D1
2 1
+5VS
RB420D_SOT23
R1
33_0402_5%
LPTSTB#
LPTSTB#36
LPTAFD#36
LPTERR#36
LPTACK#36
LPTBUSY36
LPTPE36
LPTSLCT36
AFD#/3M#
FD0
LPTERR#
FD1
LPTINIT#
FD2
LPTSLCTIN#
FD3
FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
1 2
1 2
R7 33_0402_5%
12
R2
2.2K_0402_5%
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
C1
1 2
220P_0402_50V7K
JP13
SUYIN_7843S-25G2T-01
+5V_PRN
RP55
LPD0 FD0 LPD7 FD7
1 8
LPD1 FD1
2 7
LPD2 FD2
3 6
LPD3
109876
12345
4 5
FD3
68_8P4R_1206_5%
FD4
FD5
FD6
FD7
RP1
2.7K_10P8R_1206_5%
+5V_PRN
FD3
FD2 LPTSLCTIN#
FD1
FD0
+5V_PRN
1
CF11
SMD40M80
1
1 8
LPD6 FD6
2 7
LPD5 FD5
3 6
LPD4 FD4
4 5
RP56
68_8P4R_1206_5%
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
109876
RP2
2.7K_10P8R_1206_5%
12345
+5V_PRN
LPTINIT#
LPTERR#
AFD#/3M#
1
CF10
SMD40M80
1
1
CF15
SMD40M80
1
FD3
LPTSLCTIN#
FD2
LPTINIT#
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
FD1
LPTERR#
FD0
AFD#/3M#
FD4
FD5
FD6
FD7
2
3
4 5
@220P_1206_8P4C_50V8K
2
3
4 5
@220P_1206_8P4C_50V8K
2
3
4 5
@220P_1206_8P4C_50V8K
2
3
4 5
@220P_1206_8P4C_50V8K
CP2
CP1
CP3
CP4
1
CF12
SMD40M80
1
81
7
6
81
7
6
81
7
6
81
7
6
1
CF17
SMD40M80
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
Compal Electronics, In c.
Title
PARALLEL/MDC PORT
Size Document Number Rev
LA-2101
Date: Sheet of
38 52Saturday, November 22, 2003
0.1
Page 39
5
0.1U_0402_16V4Z
12
12
C739
0.1U_0402_16V4Z
+RTCVCC +51AVCC
D D
12
C369
0.1U_0402_16V4Z
+3VALW
12
C793
C765
0.1U_0402_16V4Z
12
C453
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
C758
1 2
L19
FBM-L11-160808-800LMT_0603
ECAGND
12
R631@1K_0402_5%
12
R6321K_0402_5%
1 2
1000P_0402_50V7K
+3VALW
C743
CLK_PCI_LPC24
VGA_SELECT
+3VALW
C799
1000P_0402_50V7K
1 2
@33_0402_5%
@22P_0402_25V8K
R630
C738
+3VALW
12
1
2
High for M10C
Low for M11P
+3VALW
C C
WLANPME#28,29,31,32
PCM_PME#28,29,31,32
1394_PME#28,29,31,32
LAN_PME#28,29,31,32
+3VALW
RP51
+5VALW
R675
100K_0402_5%
R668
0_0402_5%
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
10K_0804_8P4R_5%
AD_BID0
12
C791
B B
Analog Board ID definition,
Please see page 3.
+3VALW
Ra
1 2
A A
Rb
1 2
12
R6781K_0402_5%
SIO_SELECT
12
R677@1K_0402_5%
HIGH: With SIO(Default )
Low: Without SIO
+3VALW
1 2
BATT_TEMPECAGND
12
C4030.01U_0402_16V7Z
MODE#
FRD#
SELIO#
FSEL#
RP59
EC_SMB_DA2
18
EC_SMB_CK2
27
EC_SMB_DA1
36
EC_SMB_CK1
45
CRY1
20M_0603_5%
12
C345
0.1U_0402_16V4Z
10P_0402_50V8K
32.768KHZ_12.5P_1TJS125DJ2A073
5
R645
10K_0402_5%
EC_PME#
R289
1 2
4
1
IN
OUT
NC
NC
3
2
(Pin 114)
CRY2
120K_0402_5%
R286
1 2
12
C335
X2
10P_0402_50V8K
+3VS
R217 0_0402_5%
SERIRQ24,29,36
LPC_FRAME#24,36
LPC_AD024,36
LPC_AD124,36
LPC_AD224,36
LPC_AD324,36
EC_SCI#25
GATEA2025
KBRST#25
TV_OUT_EN#41
KSO1740,41
EC_IDERST33,35
TP_CLK40
TP_DATA40
LID_SW#41
HDD_LED#41
EC_SMI#25
S4_SATA42
WL_OFF#31
EC_SWI#25
S4_LATCH42
SYSON42,43
SUSP#33,35,40,43
VR_ON50
PCMRST#35
EC_RSMRST#25
SHDD_LED#35
ENBKL9,17
BKOFF#23
FSEL#40
1 2
4
R634 @0_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
EC_RST#
12
R220 4.7K_0402_5%
EC_SCI#
R216
4
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
SIO_SELECT
TP_CLK
TP_DATA
LID_SW#
HDD_LED#
EC_SMI#
SYSON
SUSP#
VR_ON
ENBKL
BKOFF#
FSEL#
ENBKL
KSI040
KSI140
KSI240
KSI340
120K_0402_5%
3
+51VDD
12
C228
0.1U_0402_16V4Z
7
8
9
15
14
13
10
18
19
22
23
31
5
6
71
72
73
74
77
78
79
80
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
105
106
107
108
109
110
111
114
115
116
117
118
119
CRY1
158
CRY2
160
62
63
69
70
75
76 143
148
149
155
156
3
4
27
28
173
174
47
PROPRIETARY NOTE
U13
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#
IOPD3/ECSCI#
GA20/IOPB5
KBRST/IOPB6
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
TINT#
TCK
TDO
TDI
TMS
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
32KX1/32KCLKIN
32KX2
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
SEL0#
SEL1#
CLK
163445
VDD
VCC1
Host interface
Key matrix scan
JTAG debug port
PS2 interface
PORTJ-2
PORTM
GND1
GND2
GND3
173546
122
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
123
VCC2
GND4
159
136
VCC3
GND5
167
157
166
VCC5
VCC4
PORTB
PORTD-1
PORTE
GND6
GND7
137
+51AVCC+3VALW
VCC6
AD Input
DA output
PWM
or PORTA
PORTC
PORTH
PORTJ-1
PORTD-2
PORTK
PORTL
AGND
96
95
AVCC
IOPB7/RING/PFAIL/RESET2
IOPD2/EXWINT24/RESET2
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46
PORTI
NC1
11
ECAGND
3
R301 0_0603_5%
161
VBAT
AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9
DA0
DA1
DA2
DA3
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPE4/SWIN
IOPE5/EXWINT40
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
IOPJ0/RD
IOPJ1/WR0
SELIO#
IOPD4
IOPD5
IOPD6
IOPD7
IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
122021858691929798
PC87591L-VPCN01 A2_LQFP176
C218 @1U_0603_10V4Z
1 2
1 2
L20 FBM-L11-160808-800LMT_060 3
12
BATT_TEMP
81
82
BATT_OVP
83
AD_BID0
84
ALI/MH#
87
88
89
INTERNET#
90
93
94
DAC_BRIG
99
EN_DFAN2#
100
IREF
101
EN_DFAN1#
102
INVT_PWM
32
BEEP#
33
PWR_SUSP_LED#
36
ACOFF
37
KILL_SW#
38
EC_ON
39
EC_LID_OUT#
40
VGA_SELECT
43
EC_URXD
153
EC_UTXD
154
EC_USCLK
162
EC_SMB_CK1
163
EC_SMB_DA1
164
165
PBTN_OUT#
168
EC_SMB_CK2
169
EC_SMB_DA2
170
FAN_SPEED1
171
EC_PME#
172
EC_THRM#
175
FAN_SPEED2
176
1
ACIN
26
CD_PLAY
29
PM_SLP_S3#
30
2
PM_SLP_S5#
44
24
25
KBA0
124
KBA1
125
KBA2
126
KBA3
127
KBA4
128
KBA5
131
KBA6
132
KBA7
133
ADB0
138
ADB1
139
ADB2
140
ADB3
141
ADB4
144
ADB5
145
ADB6
146
ADB7
147
FRD#
150
FWR#
151
SELIO#
152
41
NUM_LED#
42
CAPS_LED#
54
PADS_LED#
55
KBA8
KBA9
142
KBA10
135
KBA11
134
KBA12
130
KBA13
129
KBA14
121
KBA15
120
KBA16
113
KBA17
112
KBA18
104
KBA19
103
FSTCHG
48
EMAIL#
MODE#
+RTCVCC
1
2
C365
1U_0603_10V4Z
BATT_TEMPA 45
BATT_OVP 46
ALI/MH# 45
EMAIL# 41
MODE# 40
INTERNET# 41
DAC_BRIG 23
EN_DFAN2 42
IREF 46
EN_DFAN1 42
INVT_PWM 23
BEEP# 34
PWR_SUSP_LED# 40,41
ACOFF 46
KILL_SW# 31,41
EC_ON 41
EC_LID_OUT# 25
EC_SMB_CK1 40,45
EC_SMB_DA1 40,45
PCIRST# 23,24,28,29,31,32,36
PBTN_OUT# 25
EC_SMB_CK2 5,36
EC_SMB_DA2 5,36
FAN_SPEED1 42
EC_THRM# 25
FAN_SPEED2 42
ACIN 25,40,44
CD_PLAY 33,35
PM_SLP_S3# 25
ON/OFF 41
PM_SLP_S5# 25
R219
1 2
10K_0402_5%
PM_CLKRUN# 24,28,29,31,32,36
** 1028
FRD# 40
FWR# 40
SELIO# 40
PHDD_LED# 35
FSTCHG 46
2
KBA[0..19]40
ADB[0..7]40
1 2
R351
1 2
C415 0.22U_0603_16V4Z
KBA[0..19]
ADB[0..7]
100K_0402_5%
(ACES_85201-2405_24P)
JP9
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
6278-34P-KBCON
ADP_I 45,46
KEYBOARD CONN.
NUM_LED#
PADS_LED#
CAPS_LED#
1 2
300_0402_5%
R403
KSO15
KSO14
KSO10
KSO11
KSO8
KSO9
KSO13
KSI7
KSO3
KSO7
KSO12
KSI4
KSI6
KSI5
KSO6
KSO5
KSI3
KSI0
KSO0
KSO1
KSI1
KSI2
KSO2
KSO4
1 2
R402 300_0402_5%
1 2
300_0402_5%
R401
(Need to check layout library with KB spec)
BADDR1(KBA3) BADDR0(KBA2)
0
0
*
0
1
01
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
11
0
1
1
1 2
1 2
ENV1 (KBA1)
4.7K_0402_5%
4.7K_0402_5%
0
1
1
+5VS
ENV0 (KBA0) TRIS (KBA4)
IRE
*
OBD 0
DEV 0
PROG
SHBM(KBA5)=1: Enable shared memory with host BIOS
TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
TP_CLK KBA2
R667
TP_DATA
R662
Compal Electronics, In c.
Title
EC PC87591
Size Document Number Rev
Custom
2
Date: Sheet of
LA-2101
1
For EC Tools
JP25
1
1
2
3
4
5
6
7
8
9
10
@96212-1011S
Index
2E 2F
4E
2
3
4
5
6
7
8
9
10
NUM_LED#
PADS_LED#
CAPS_LED#
KSO15
KSO14
KSO10
KSO11
+3VS
KSO8
KSO9
KSO13
KSI7
KSO3
KSO7
KSO12
KSI4
KSI6
KSI5
KSO6
KSO5
KSI3
KSI0
KSO0
KSO1
+3VS
KSI1
KSI2
KSO2
KSO4
+3VS
I/O Address
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
EC_URXD
EC_UTXD
EC_USCLK
CP9 100P_1206_8P4C_50V8
2
3
4 5
CP10 100P_1206_8P4C_50V8
2
3
4 5
CP11 100P_1206_8P4C_50V8
2
3
4 5
CP8 100P_1206_8P4C_50V8
2
3
4 5
CP5 100P_1206_8P4C_50V8
2
3
4 5
CP6 100P_1206_8P4C_50V8
2
3
4 5
CP7 100P_1206_8P4C_50V8
2
3
4 5
Data
Reserved
0
0
0
0
KBA1
1 2
R683 1K_0402_5%
1 2
R682 @1K_0402_5%
KBA3
1 2
R681 1K_0402_5%
KBA5
1 2
R680 1K_0402_5%
1
+3VALW
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
4F
+3VALW
39 52Saturday, November 22, 2003
0.1
Page 40
FWE#
6
SN74LVC32APWLE_TSSOP14
U19B
EC_SMB_CK139,45
EC_SMB_DA139,45
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
FSEL#
FRD#
FWE#
SELIO#39
SN74LVC32APWLE_TSSOP14
4
A
5
B
C219
0.1U_0402_16V4Z
1 2
U11
8
VCC
7
WP
6
SCL
5
SDA
AT24C16AN-10SI-2.7_SO8
+3VALW
12
R290
100K_0402_5%
GND
+3VALW
O
147
PG
+5VALW
1MB Flash ROM
KBA[0..19]39
ADB[0..7]39
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
22
24
9
KBA[0..19]
ADB[0..7]
U51
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE#
OE#
WE#
SST39VF080-70_TSOP40
VCC0
VCC1
READY/BUSY#
GND0
GND1
RP#
NC0
NC1
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
NC
KBA2
SELIO#
U19A
2
G
1 3
D
Q22
2N7002_SOT23
+5VALW
1
2
3
4
31
30
25
26
27
28
32
33
34
35
10
11
12
29
38
23
39
+3VALW
147
1
PG
A
2
B
+5VALW
S
FWR# 39
12
R191
100K_0402_5%
12
R195
100K_0402_5%
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
1 2
R691
@100K_0402_5%
3
O
+3VALW
R344
100K_0402_5%
1 2
C451
1 2
1U_0603_10V4Z
SUSP# 33,35,39,43
EC_FLASH# 25
+3VALW
MODE#39
KSO1739,41
KSI339
KSI139
1
C820
0.1U_0402_16V4Z
2
+3VALW
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
AA
1 2
R380
820K_0402_5%
@120P_0402_50V8K
+5VALWP
1 2
C458
0.1U_0402_16V4Z
20
U22
3
1D
4 5
2D 2Q
VCC
7 6
3D 3Q
8 9
4D 4Q
13 12
5D 5Q
14 15
6D 6Q
17 16
7D 7Q
18 19
8D 8Q
11
CLK
1
OE
GND
10
C803
MODE#
KSO17
EC_FRDBTN#
EC_STOPBTN#
C819
CDON_LED#
2
1Q
MP3_LED#
EMAIL_LED#
PWR_LED#
BATT_LOW_LED#
BATT_CHGI_LED#
SN74HCT374PW_TSSOP20
SW/B and TP/B FFC Connector
Pin 1 Definition Same As SW/B and TP/B
VR/B FFC Connector
Pin 1 Definition Swap with VR/B
Direct CD button board
12
1
1
1
C817
C815
2
2
2
@120P_0402_50V8K
@120P_0402_50V8K
@120P_0402_50V8K
1MB BIOS Connector
KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
JP8
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
@SUYIN-80065A-040G2T
JP7
12
34
56
78
910
ACES_85201-1005
KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
FRD#
FSEL#
KBA0
PWR_LED# 41
WL_BT_LED# 41
ODD_LED# 41
1
C465
2
51ON#
EC_REVBTN#
EC_PLAYBTN#
1
C808
C816
2
@120P_0402_50V8K
@120P_0402_50V8K
+3VALW
@0.1U_0402_16V4Z
FRD# 39
FSEL# 39
TP_CLK
1 2
C789 220P_0402_50V7K
TP_DATA
1 2
C783 220P_0402_50V7K
1
2
JP5
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
ACES_85201-2005
+5VS
C421
+5VALWP
C316
2
1
2
1
SW Board Connector
TP_CLK39
TP_DATA39
PWR_SUSP_LED#39,41
ACIN25,39,44
51ON# 41,44
KSI2 39
KSI0 39
1
1
C818
2
2
@120P_0402_50V8K
NBA_PLUG33,34
1
1
1
C771
1
C774
C777
2
2
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
C766
2
1
C764
2
2
1
1
C761
C755
2
220P_0402_50V7K
220P_0402_50V7K
2
220P_0402_50V7K
220P_0402_50V7K
VR/CIR Board Connector
JP6
12
*
34
56
78
910
ACES_85201-1005
1
C750
2
220P_0402_50V7K
VOL_AMP
+3VALW
1
2
+5VS
TP_CLK
TP_DATA
PWR_LED#
PWR_SUSP_LED#
ACIN
BATT_LOW_LED#
BATT_CHGI_LED#
EMAIL_LED#
+5VALWP
CDON_LED#
MP3_LED#
1 2
L47
FCM2012C-800_0805
C804
1U_0603_10V4Z
C747
220P_0402_50V7K
VOL_AMP 34
+5VAMP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
Compal Electronics, In c.
Title
BIOS & EXT. I/O PORT
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
40 52Saturday, November 22, 2003
0.1
Page 41
5
100K_0402_5%
LID_SW#
*
R107
+3VALW
12
D11
2
3
CHN202U_SC70
@V-PORT-0603-220 M-V05_0603
1
D10
2 1
LID Switch
LID_SW#39
S4_LID_SW#42
D D
Power Button
3
2
+3VALW
D54
PSOT24C_SOT23
SW2
EC_ON39
2N7002_SOT23
3
4
+3VALW
EC_ON
D
Q46
S
1
C C
2
HCH SMT1-05
R547
4.7K_0402_5%
1 2
R529
1 2
33K_0603_1%
DTC124EK_SOT23
13
2
G
D58
1
CHN202U_SC70
2
Q47
R548
100K_0402_5%
1 2
3
2
C
22K
B
22K
51ON#
1000P_0402_50V7K
13
E
12
SW1
FR2283_2P
ON/OFFBTN# 42
ON/OFF 39
51ON# 40,44
C659
4
HDD LED
HT-191NB_BLUE_0603
HDD_LED#39 ODD_LED#40
+5VALWP +5VALWP
12
R170
300_0402_5%
21
D25
HDD_LED#
Wireless LED
300_0402_5%
D53
12
RLZ20A
2 1
WL_BT_LED#40
HT-191UD_AMBER_0603
WL_BT_LED#
3
*27
D23
@V-PORT-0603-220 M-V05_0603
2 1
+5VALWP
12
R278
21
D38
D36
2 1
ODD LED
HT-191NB_BLUE_0603
SDLED#29
SN74LVC125APWLE_TSSOP14
@V-PORT-0603-220 M-V05_0603
2
R209
300_0402_5%
21
D29
D30
ODD_LED#
SD LED Kill SWITCH
C269
0.01U_0402_16V7Z
12 11
IO
@V-PORT-0603-220 M-V05_0603
2 1
+5VS
1
2
OE#
U44D
D35
13
R227
300_0402_5%
21
D34
HT-191NB_BLUE_0603
R211
1 2
@V-PORT-0603-220 M-V05_0603
2 1
10K_0402_5%
+5VS
DS-1200-02
3
2
1
SW6
3
2
1
+3VALW
21
@V-PORT-0603-220 M-V05_0603
D56
1
R549
100K_0402_5%
1 2
KILL_SW# 31,39
Internet Button Console/E-MAIL Button TV OUT Button
B B
POWER LED
+5VALWP
12
R520
300_0402_5%
21
D14
HT-191UD_AMBER_0603
+5VALWP
12
R522
300_0402_5%
21
D15
HT-191NB_BLUE_0603
D13
D16
NDS352P_SOT23
S
Q4
D
SW3
1
2
HCH SMT1-05
1 3
51ON#
12
R108
0_0603_5%
G
2
21
D12
1N4148_SOT23
3
4
D18
1N4148_SOT23
3
2
21
+3VALW
R173 100K_0402_5%
R115 100K_0402_5%
12
12
SW4
1
2
HCH SMT1-05
EMAIL#
INTERNET#
21
D24
1N4148_SOT23
3
4
D26
1N4148_SOT23
3
2
21
EMAIL# 39INTERNET# 39
KSO17 KSI4
SW5
1
2
HCH SMT1-05
3
4
D27
@V-PORT-0603-220 M-V05_0603
2 1
TV_OUT_EN# 39KSO1739,40
@V-PORT-0603-220 M-V05_0603
2 1
A A
PWR_SUSP_LED#39,40
PWR_SUSP_LED#
@V-PORT-0603-220 M-V05_0603
PWR_LED#
2 1
PWR_LED# 40
D17
PSOT24C_SOT23
D21
PSOT24C_SOT23
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
3
2
Switchs & Connectors
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
41 52Saturday, November 22, 2003
1
0.1
Page 42
A
B
C
D
E
FAN CONN. 1
+12VALW
C650
0.1U_0402_16V4Z
1 2
1 1
EN_DFAN139
EN_DFAN1
R512
10K_0402_5%
12
FAN CONN. 2
EN_DFAN239
2 2
EN_DFAN2
R534
10K_0402_5%
12
84
3
+
2
-
1 2
R513
+12VALW
84
5
+
6
-
1 2
R535
1
U38A
LM358AMX
8.2K_0402_5%
C646
0.1U_0402_16V4Z
7
U38B
LM358AMX
8.2K_0402_5%
EN_FAN1
FAN_SPEED139
EN_FAN2
FAN_SPEED239
1 2
R536
100_0402_5%
+3VS
R511 10K_0402_5%
1 2
R128
100_0402_5%
1 2
+3VS
R130 10K_0402_5%
2
C664
0.1U_0402_16V4Z
1
1 2
R530
0_0603_5%
2
C97
0.1U_0402_16V4Z
1
R137
0_0603_5%
2
B
D52
1N4148_SOT23
12
2
B
D19
1N4148_SOT23
12
+5VALW
1
C
E
3
12
+5VALW
1
C
E
3
12
FMMT619_SOT23
Q45
FAN1
12
C615
1000P_0402_50V7K
12
C611
1000P_0402_50V7K
FMMT619_SOT23
Q7
FAN2
12
C89
1000P_0402_50V7K
12
C94
1000P_0402_50V7K
D55
CH355_SC76
2 1
D57
CH355_SC76
2 1
1
C648
10U_1206_16V4Z
2
JP19
1
2
3
ACES_85205-0300
1
C679
10U_1206_16V4Z
2
JP22
1
2
3
ACES_85205-0300
100K_0402_5%
S4_LID_SW#41
S4_SATA39
Battery mode Hibernation
RTCVREF RTCVREF RTCVREF
R557
*
S4_LATCH39
RTCVREF
+3VALW
12
12
13
2
G
R165
10K_0402_5%
@1U_0805_16V7K
1 2
R612
10K_0402_5%
1 2
Q48
2N7002_SOT23
RTCVREF
R176
1 2
10K_0402_5%
C720
12
1
2
D60
2 1
CH751H-40_SC76
R559
100K_0402_5%
C111 1U_0805_16V7K
D
S
1 2
R131
680K_0402_5%
1N4148_SOT23
1 2
R597
10K_0402_5%
12
D20
C125 0.1U_0402_10V6K
1 2
5
U6
P
2
AGY
NC7SZ14M5X_SOT23-5
3
SYSON39,43
1 2
C719 1U_0805_16V7K
U43
1
CD1#
2
D1
3
CP1
4
SD1#
5
Q1
6
Q1#
7
GND
74LCX74MTC_TSSOP14
4
VCC
CD2#
D2
CP2
SD2#
Q2
Q2#
D_SET_S4
1 2
R162
10K_0402_5%
2
Q11
2N7002_SOT23
RTCVREF
14
13
12
11
10
09
08
13
D
G
S
0.1U_0402_10V6K
1 2
C693
2N7002_SOT23
ON/OFFBTN# 41
13
D
Q49
2
2N7002_SOT23
G
S
Q12
2
G
13
D
S
1
C147
@220P_0402_50V7K
2
3 3
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SH EE T N O R T HE I NF OR MA TI O N IT C ON TA IN S
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL EL ECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Power OK/Reset/RTC battery/Lid Switch/Int. KB
LA-2101
42 52Saturday, November 22, 2003
E
0.1
Page 43
A
B
C
D
E
+3VALW TO +3V
1
C98
10U_1206_16V4Z
+3VALW
U5
8
1 1
D
7
D
6
D
5
D
SI4800DY_SO8
1
C113
10U_1206_16V4Z
2
S
S
S
G
1
2
3
4
2
2
C123
0.1U_0402_16V4Z
1
+3V
1
2
1 2
13
D
S
C99
1U_0805_16V7K
R141
95.3K_0603_1%
SYSON#
2
G
Q9
2N7002_SOT23
+5VALWP
+12VALW
U50
8
D
7
D
6
D
5
D
SI4800DY_SO8
1
C780
4.7U_1206_16V4Z
2
+5VALW TO +5V
+5V
1
S
2
S
3
S
4
G
1
2
2
C805
0.1U_0402_16V4Z
1
C779
4.7U_1206_16V4Z
R679
47K_0402_5%
1 2
13
D
2
G
Q55
S
2N7002_SOT23
1
C778
1U_0805_16V7K
2
SYSON#
+12VALW
+3VALW TO +3VS +5VALW TO +5VS
+3VS
+3VALW
U16
8
S
D
7
S
D
6
S
D
5
G
2 2
3 3
D
SI4800DY_SO8
1
C338
10U_1206_16V4Z
2
+2.5VALW
8
7
6
5
12
C459
4.7U_0805_10V4Z
1
C232
10U_1206_16V4Z
2
1
2
3
4
2
C323
0.1U_0402_16V4Z
1
+2.5VALW TO +2.5V
+2.5V
U23
1
S
D
2
S
D
3
S
D
4
G
D
SI4800DY_SO8
2
1
1
2
R248 95.3K_0603_1%
12
C468
4.7U_0805_10V4Z
C464
0.1U_0402_16V4Z
C244
1U_0805_16V7K
1 2
13
D
2
G
Q19
S
2N7002_SOT23
SUSP
R389
100K_0402_5%
1 2
13
D
Q26
S
2N7002_SOT23
2
G
1
2
SYSON#
+12VALW
C467
1U_0805_16V7K
+12VALW
+5VALWP
8
7
6
5
1
2
U30
S
D
S
D
S
D
G
D
SI4800DY_SO8
C478
4.7U_1206_16V4Z
1
2
3
4
1
C498
4.7U_1206_16V4Z
2
2
C492
0.1U_0402_16V4Z
1
H_C276D181
H5
+2.5VALW TO +2.5VS
+2.5VS+2.5VALW
U21
S
D
S
D
S
D
G
D
SI4800DY_SO8
1
2
3
4
2
1
1
C389
1U_0603_10V4Z
2
C367
0.1U_0402_16V4Z
1
2
4.7U_0805_10V4Z
C376
1
C375
4.7U_0805_10V4Z
2
R305
100K_0402_5%
1 2
13
D
2
G
Q20
S
2N7002_SOT23
+12VALW
SUSP
8
7
6
5
1
C449
2
4.7U_0805_10V4Z
4 4
H20
H_C197D98
+5VS
1
C499
1U_0805_16V7K
2
R441
6.8K_0402_5%
1 2
13
D
S
1
1
SUSP
2
G
Q31
2N7002_SOT23
H26
H_S315D142
1
H14
H_C276D181
1
H22
H_C197D98
1
+12VALW
SYSON39,42 SUSP#33,35,39,40
H23
H_S315D142
1
H25
H_S276D110
1
H24
H_C228D165
1
+3V +5V
R638
470_0805_5%
1 2
13
D
SYSON# SYSON#
2
G
Q52
S
2N7002_SOT23
R429
470_0805_5%
1 2
13
D
2
G
Q27
S
2N7002_SOT23
+5VALWP
1 2
SYSON#
13
2
1 2
H30
H_S315D142
H9
H_C276D142
H7
H_S315D142
D
G
S
1
1
1
PAD-OPEN 2x2m
2 1
SYSON
R637
10K_0402_5%
H12
H_S315D142
1
H16
H_TC197S276D110
1
H29
H_O268X228D205X165
1
PJP14
PAD-OPEN 2x2m
R640
10K_0402_5%
Q51
2N7002_SOT23
H27
H_S315D142
H13
H_C276D142
H3
H_C276D181
PJP16
R652
470_0805_5%
1 2
13
D
2
G
Q53
S
2N7002_SOT23
+5VS+3VS
R425
470_0805_5%
1 2
13
D
SUSPSUSP
2
G
Q28
S
2N7002_SOT23
H15
H_S315D142
1
1
1
2 1
H10
H_SMDC138
H1
H_C276D181
1
2 1
1
1
H_C55D55N
PJP17
PAD-OPEN 2x2m
10K_0402_5%
H8
H_S315D142
1
H11
H_C142D142N
1
H2
1
+2.5VS
1 2
13
D
S
+VGA_CORE
1 2
13
D
S
SUSP
R418
1 2
H_C55D55N
R223
470_0805_5%
SUSP
2
G
Q16
2N7002_SOT23
R453
@470_0402_5%
Q36
@2N7002
SUSP
2
G
+5VALWP
1 2
13
2
G
H28
H_S315D142
1
H6
H_C236D236N
1
H19
1
R419
10K_0402_5%
D
S
+1.8VS
1 2
13
D
S
Q29
2N7002_SOT23
H4
H_C276D181
1
2 1
PAD-OPEN 2x2m
H17
H_SMDC157
1
R452
470_0805_5%
SUSP
2
G
Q37
2N7002_SOT23
PJP12
H18
H_SMDC157
H21
H_C276D181
1
PJP13
2 1
PAD-OPEN 2x2m
1
Compal Electronics, In c.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
A
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
POWER CONTROL CKT
Size Document Number Rev
Custom
LA-2101
Date: Sheet of
43 52Saturday, November 22, 2003
E
0.1
Page 44
A
1
2
PF1
12A_65VDC_451012
21
PD1
EC10QS04_SOD106
PL1
1 2
12
PC1
1000P_0402_50V7K
12
C8B BPH 853025_2P
12
PC2
100P_0402_50V8J
PCN1
1
6
G
5
G
4
G
2
3
1 1
G
SINGA_2DC-S113L200
B
PC3
1000P_0402_50V7K
12
VIN
12
PC4
100P_0402_50V8J
PC5
1000P_0402_50V7K
C
PD2
VS
12
PR2
5.6K_0402_5%
12
PR4
1K_0402_5%
1 2
PACIN
12
PR7
10K_0402_5%
Vin Detector
High 18.764 17.901 17. 0 6 3
VIN
12
PR3
84.5K_0402_1%
1 2
PR5 22K_0402_5%
12
12
PR6
20K_0402_1%
12
PC6
0.1U_0402_16V4Z
1M_0402_1%
1 2
VS
84
3
+
2
-
PR8
10K_0402_5%
PR1
PU1A
LM393M_SO8
PG
1
O
12
RTCVREF
3.3V
RLZ4.3B_LL34
D
ACIN 25,39,40
PACIN 46,47
Low 17.745 16.903 16. 0 3 8
VIN
PD3
D
13
N2
1N4148_SOD80
1 2
12
PR10
33_1206_5%
12
PC8
0.1U_0603_25V7K
2 1
+VGA_COREP
VS
MAINPWON6,45,47
ACON46
PD8
RLZ16B_LL34
*
PJP11
+1.8VSP
1 2
12
JUMP_43X79
(1.5A,60mils ,Via NO.= 3)
+5VALWP
(6A,240mils ,Via NO.= 12)
+3VALWP
(6A,240mils ,Via NO.= 12)
(6A,240mils ,Via NO.= 12)
PJP5
1 2
12
JUMP_43X118
PJP7
1 2
12
JUMP_43X118
PJP10
1 2
12
JUMP_43X118
B
+1.8VS
+5VALW
+3VALW
+VGA_CORE
VIN
PD7
2
3
RB715F_SOT323
PD5
12
1N4148_SOD80
PR15
10K_0402_5%
VL
1
1 2
PD9
2 1
1000P_0402_50V7K
RLZ6.2C_LL34@
Precharge detector
15.34 15.90 16.48
13.13 13.71 14.20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
INC.
PD4
RB751V_SOD323
2 2
CHGRTC
3 3
+2.5VALWP
+1.25VSP
+VCCVIDP
4 4
+1.5VSP
+12VALWP
BATT+
51ON#40,41
PR19
200_0402_5%
1 2
PJP1
1 2
12
JUMP_43X118
PJP3
1 2
12
JUMP_43X118
PJP4
1 2
12
JUMP_43X79
PJP6
1 2
12
JUMP_43X39
PJP8
1 2
12
JUMP_43X118
PJP9
1 2
12
JUMP_43X39
RLZ3.6B_LL34
PD6
PR14
22K_0402_5%
1 2
RTCVREF
3.3V
12
PC13
10U_0805_10V4Z
A
12
12
12
PR13
100K_0402_5%
PU2
S-812C33AUA-C2N-T2_SOT89
3
OUT
+2.5VALW
(12A,480mils ,Via NO.=24)
(3A,120mils ,Via NO.= 6)
+1.25VS
(150mA,40mils ,Via NO.= 2)
+CPUVID
(5A,200mils ,Via NO.= 10)
+1.5VS
(120mA,20mils ,Via NO.= 1)
+12VALW
N1CHGRTCP
12
PC7
0.22U_1206_25V7K
IN
GND
1
TP0610T_SOT23
2
PQ1
S
G
2
12
PR18
200_0402_5%
12
PC12
1U_0805_25V4Z
PR9
1K_1206_5%
1 2
PR11
1K_1206_5%
N3
1 2
1K_1206_5%
1 2
6.0V
PC10
PR12
12
C
1M_0402_1%
LM393M_SO8
84
PG
+
7
O
-
PC11
0.1U_0402_16V4Z
PR16
PU1B
5
6
12
12
PR21
10K_0402_5%
1 2
RTCVREF
3.3V
PQ2
2N7002_SOT23
12
PR22
215K_0402_1%
13
D
2
G
S
Title
Size Document Number Rev
Date: Sheet
B+
12
PR17
499K_0402_1%
12
PR20
499K_0402_1%
47K_0402_5%
13
PR23
PQ3
DTC115EKA_SC59
2
12
12
PC9
1000P_0402_50V7K
PACIN
+5VALWP
Compal Electronics, Inc.
DCIN / DETECTOR
LA-2101
D
44 52Saturday, November 22, 2003
0.1
of
Page 45
A
B
C
D
PCN2
1 1
10
GND
11
GND
SUYIN_200275MR009G116ZL_RV
2 2
BATT+
BATT+
SMD
SMC
GNDÂGND-
1
2
ID
B/I
TS
AB/I
4
TS_A
5
EC_SMDA
6
EC_SMCA
7
8
9
PD13
BAS40-04_SOT23@
PR28
100_0402_5%
3
12
PR29
100_0402_5%
1
2
12
2
ALI/NIMH#
3
1K_0402_5%
12
PR31
1K_0402_5%
12
PR36
1K_0402_5%
1
1
3
PR24
12
47K_0402_5%
1 2
1
PD10
BAS40-04_SOT23@
PR34
25.5K_0402_1%
1 2
PD14
BAS40-04_SOT23@
PR26
3
2
PF2
15A_65VDC_451015
3
2
PD12
BAS40-04_SOT23@
21
VMB
+3VALWP
+3VALWP
C8B BPH 853025_2P
1 2
12
PC15
1000P_0402_50V7K
ALI/MH# 39
BATT_TEMPA 39
EC_SMB_DA1 39,40
EC_SMB_CK1 39,40
PL2
BATT+
12
PC16
0.01U_0402_25V7Z
0.22U_0805_16V7K_V2
10KB_0603_1%_TH11-3H103FT
PH2 near main Battery CONN :
BAT. thermal protection at 78 degree C
Recovery at 44 degree C
PH1 under CPU botten side :
CPU thermal protection at 84 degree C
Recovery at 44 degree C
VL VS
PC17
12
PH1
1 2
12
12
12
PR30
16.9K_0402_1%
TM_REF1
PR32
3.32K_0402_1%
12
PC18
1000P_0402_50V7K
PC14
0.1U_0603_25V7K
3
+
2
-
PR33
100K_0402_1%
12
PR35
100K_0402_1%
84
PG
O
PU3A
LM393M_SO8
12
PR27
47K_0402_1%
1 2
VL
VL
PR25
47K_0402_1%
1 2
PD11
1
1SS355_SOD323
2
12
13
PQ4
DTC115EKA_SC59
MAINPWON 6,44,47
+5VALWP
VLVL
PR37
PR38
84
PG
47K_0402_1%
1 2
7
O
PU3B
LM393M_SO8
PR40
100K_0402_1%
PD15
1SS355_SOD323
12
VL
Title
Size Document Number Rev
Date: Sheet
12
Compal Electronics, Inc.
BATTERY CONN / OTP /Throttling
LA-2101
D
45 52Saturday, November 22, 2003
0.1
of
PR112
12
A
90W
PR110
64.9K_0402_1%
1 2
12
PC90
1000P_0402_50V7K
3
2
5
6
1M_0402_1%
1 2
VS
84
PG
+
-
84
PG
+
-
PR108
12
PC89
0.1U_0603_25V7K
1
O
PU10A
LM393M_SO8
PU10B
7
O
LM393M_SO8
12
PH2
10KB_0603_1%_TH11-3H103FT
5
6
12
PR42
100K_0402_1%
47K_0402_1%
1 2
+
-
12
PR41
3.48K_0402_1%
C
PR39
1 2
14.7K_0402_1%
12
TM_REF2
PC20
1000P_0402_50V7K
VL
12
PR109
365K_0402_1%
12
PC91
10P_0402_50V8J
13
D
PQ24
2
G
2N7002_SOT23
S
B
H_PROCHOT# 5
12
0.22U_0805_16V7K_V2
PC19
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
INC.
120W
3 3
PR109 365K_0402_1% 205K_0402_1%
PR110 64.9K_0402_1% 88.7K_0402_1%
PR111 249K_0402_1% 200K_0402_1%
ADP_I39,46
1 2
VL
4 4
PR111
249K_0402_1%
100K_0402_1%
Page 46
A
P2
PQ6
SI4825DY_SO8
D
S
D
S
D
S
D
G
PD16
1SS355_SOD323
1 2
1 2
PR51
3K_0402_5%
1
2
3
4
12
PR45
200K_0402_1%
12
PR48
150K_0402_1%
13
D
2
G
S
0.1U_0402_16V4Z
VIN
1 1
2 2
12
PACIN44,47
ACON44
8
7
6
5
PR44
10K_0402_5%
ACOFF#
PACIN
ACON
IREF=1.31*Icha r ge
1
2
3
4
PQ10
2N7002_SOT23
PC26
PQ7
SI4825DY_SO8
D
S
D
S
D
S
D
G
12
12
8
7
6
5
ADP_I39,45
PR53
10K_0402_1%
IREF=0.73~3.3V
PR57
205K_0402_1%
1 2
CS
13
PQ11
2
DTC115EKA_SC59
100K_0402_1%
+3VALWP
12
PR62
47K_0402_5%
13
IREF39
P3 B+
12
PR52
33.2K_0402_1%
12
PC29
0.1U_0402_16V4Z
12
12
PR61
B
120W
90W
1 2
PC27
4700P_0402_25V7K
1 2
1000P_0402_50V7K
PC33
0.1U_0402_16V4Z
Iadp=0~5.8A
Iadp=0~4.2A
PR43
0.01_2512_1%(2W)
12
12
PR50
100K_0402_5%
PR54
10K_0402_5%
1 2
PR55
1K_0402_5%
1 2
PC30
PR59
10K_0402_5%
12
PU4
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
FB2
6
VREF
7
FB1
8
-INE1
9
+INE1
10
OUTC1
11
OUTD
12
-INC1
MB3887_SSOP24
PL3
C8B BPH 853025_2P
1 2
4.7U_1206_25V6K
24
+INC2
23
GND
22
CS
21
VCC(o)
20
OUT
0.1U_0603_25V7K
19
VH
18
VCC
17
RT
16
-INE3
15
FB3
14
CTL
13
+INC1
PC21
CS
PC28
1 2
PR56
68K_0402_5%
1 2
PR60
47K_0402_5%
1 2
ACON
12
12
PC22
4.7U_1206_25V6K
12
PR49
0_0402_5%
PC24
0.022U_0402_16V7K
1 2
1 2
PC25
0.1U_0603_25V7K
PC31
0.1U_0603_25V7K
1 2
PC32
1500P_0402_50V7K
1 2
C
12
PC23
4.7U_1206_25V6K
B++
12
PC162
2200P_0402_50V7K
36
241
N18
578
LXCHRG
12
PL4
1 2
PD17
EC31QS04
22UH_SPC-1205P-220A_2.8A_20%
PQ8
SI4835DY_SO8
D
PQ5
SI7447DP_SO8
1
ACOFF#
1 2
13
10K_0402_5%
2
3
PR46
PQ9
DTC115EKA_SC59
4
47K_0402_5%
1 2
2
CC=0.5~2.7A
CV=16.8V(12 CELLS LI-ION)
PR58
0.02_2512_1%
1 2
PC35
4.7U_1206_25V6K
12
PC34
4.7U_1206_25V6K
PR47
5
12
ACOFF 39
12
VIN
BATT+
PC36
4.7U_1206_25V6K
PC37
12
A
PQ12
DTC115EKA_SC59
12
PR67
2.2K_0402_5%
PR63
95.3K_0603_0.1%
12
PR184
95.3K_0603_0.1%
12
VMB
12
PR65
340K_0402_1%
12
PR68
PR66
499K_0402_1%
12
12
PC38
0.01U_0402_25V7Z
B
+5VALWP
PU5A
LM358A_SO8
84
3
PG
+
1
0
2
-
105K_0603_0.5%
4.2V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
INC.
C
PR64
143K_0603_0.1%
12
PR43 PR 52 PQ5
120W 0.01_2512_1% 33.2K_0402_1% SI7447DP_SO8
90W 0.015_2512_1% 29.4K_0402_1% SI4825DY_SO8
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CHARGER
LA-2101
D
46 52Saturday, November 22, 2003
0.1
of
FSTCHG39
3 3
2
OVP voltage : LI
4S3P : 17.4V--> BATT_OVP= 1.935V
(BAT_OVP=0.1111 *VMB)
BATT_OVP39
4 4
0.1U_0402_16V4Z@
Page 47
5
PC41
0.1U_0603_25V7K
B+++
D D
C C
B B
PL5
HCB4532K-800T90_1812
1 2
B+
4.7U_1206_25V6K@
+3VALWP
PC52
150U_D2E_6.3VM_R18
1
2
12
12
PR72
0.012_2512_1%
PC43
4.7U_1206_25V6K
12
PL6
12
PD21
EP10QY03
2 1
PC42
10UH_SPC-1205P-100_4.5A_20%
1
+
+
2
PC53
150U_D2E_6.3VM_R18@
+3.3V Ipeak = 6.66A ~ 10A
SI4814DY_SO8
1
2
3
4
12
PC50
47P_0402_50V8J
PR73
1M_0402_1%
1 2
PR77
3.57K_0402_1%
1 2
1 2
PQ13
D1
D1
S1/D2
G2
S1/D2
S1/D2
S2
12
PC54
100P_0402_50V8J
PR79
10K_0402_1%
1 2
PDH31
8
G1
7
6
5
PDL3
PACIN44,46
PR70
0_0402_5%
1 2
PLX3
CSH3
1 2
10K_0402_5%
VS
12
PR80
47K_0402_5%
12
PC60
0.047U_0603_50V4Z
4
BST31
PR76
PDH3
PD20
1SS355_SOD323
12
PC48
0.1U_0603_25V7K
PU6
25
BST3
27
DH3
26
LX3
24
DL3
1
CSH3
2
CSL3
3
FB3
10
SKIP#
23
SHDN#
7
TIME/ON5
28
RUN/ON3
12
PC56
680P_0402_50V7K
PR82
47K_0402_1%
12
PC61
0.047U_0603_50V4Z
VS
12
1 2
22
V+
GND
8
VL
MAINPWON 6,44,45
3
2
PD19
DAP202U_SOT323
VL
1
12
PC47
4.7U_1206_16V4Z
21
4
12OUT
VL
5
VDD
18
BST5
16
DH5
17
LX5
19
DL5
20
PGND
14
CSH5
13
CSL5
12
FB5
15
SEQ
9
REF
6
SYNC
11
RST#
MAX1902EAI_SSOP28
3
BST51
+12VALWP
12
PC49
4.7U_1206_16V4Z
12
PC55
4.7U_1206_16V4Z
POK 48
2.5VREF
PC44
0.1U_0603_25V7K
1 2
4.7U_1206_25V6K
PDH5
PLX5
10.5K_0402_1%
PC45
PR78
B+++
12
1 2
PR71
0_0402_5%
PDL5
12
12
PR81
10K_0402_1%
N4
12
PC46
4.7U_1206_25V6K@
PDH51
12
PC59
100P_0402_50V8J
2
PC40
470P_0805_100V7K
1 2
PC163
12
2200P_0402_50V7K
5
D
G
4
5
D
G
4
PR69
22_1206_5%
876
DDD
PQ14
SI4800DY-T1_SO8
SSS
123
876
DDD
PQ49
SI4810DY_SO8
SSS
123
12
150U_D2E_6.3VM_R18
+5V Ipeak = 6.66A ~ 10A
FLYBACKSNB
PC57
12
PD18
EC11FS2_SOD106
4
1
12
PC51
47P_0402_50V8J
12
PR74
2M_0402_5%
1
+
2
150U_D2E_6.3VM_R18@
PC39
4.7U_1206_25V6K
1 2
2
PT1
10uH_SDT-1205P-100-118_5A_20%
3
CSH5
12
PR75
0.012_2512_1%
1
+
2
PC58
EP10QY03
2 1
PD22
1
+5VALWP
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
5
4
3
INC.
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
5V/3.3V/12V
LA-2101
47 52Saturday, November 22, 2003
1
0.1
Page 48
A
PC63
4.7U_1206_25V6K
12
PC62
4.7U_1206_25V6K
S
2
3 6
241
5
D
578
PQ16
FDS6672A_SO8
2
12
PR87
100K_0402_5%
12
PR194
137_0402_1%
12
PR196
60.4_0402_1%
1 1
876
IRF7821_S08
+2.5VALWP
PL8
2.2UH_SPC-1205P-2R2B_13A_30%
12
12
PC152
47P_0402_50V8J
12
PR191
0_1206_5%
1 2
1 2
PD26
EC31QS04
PC158
4.7U_1206_16V4Z
1 2
PC150
220U_D2_4VM
PD25
EP10QY03
2 2
3 3
2 1
PR188
0_0402_5%
1 2
1
1
PC151
+
+
220U_D2_4VM
2
2
PR93
42.2K_0402_1%
PR94
10K_0402_1%
+3VS
100P_0402_50V8J
SSG
134
12
PU18
APL1085UC-TR_TO252
3
VOUT
VIN
ADJUST
1
PC159
DDD
PQ15
1 2
12
1 2
12
PC64
4.7U_1206_25V6K
RB751V_SOD323
0.1U_0603_25V7K
+1.8VSP
PC157
4.7U_1206_16V4Z
PD23
1U_0805_10V7K
12
PC72
POK47
B
1 2
12
PC66
1000P_0402_50V7K
PR88
0_0402_5%
1 2
PR92
15K_0402_1%
1 2
PR95
0_0402_5%
1 2
C
PL7
HCB4532K-800T90_1812
1 2
D
B+
12
PR83
1M_0402_1%
1 2
12
PR85
10_0402_5%
PC68
12
1U_0603_10V6K
1 2
PU7
23
TON1
25
VCCA1
3
VDDP1
7
BST1
6
DH1
5
LX1
2
DL1
4
ILIM1
24
VOUT1
26
FBK1
22
EN/PSV1
27
PGOOD1
1
PGND1
28
AGND1
SC1486ITSTR_TSSOP28
SC1486
PC70
10_0402_5%
1U_0603_10V6K
TON2
VCCA2
VDDP2
BST2
DH2
LX2
ILIM2
DL2
FBK2
REFOUT
PGOOD2
REFIN
PGND2
AGND2
0.1U_0402_16V4Z
750K_0402_5%
PR86
PC69
12
9
11
17
21
20
19
18
16
12
10
13
8
15
14
PR84
1 2
PC154
PC71
1000P_0402_50V7K
1 2
PR89
0_0402_5%
1 2
PR91
10.7K_0402_1%
1 2
12
12
+5VALWP
12
PC67
1U_0805_10V7K
0.1U_0603_25V7K
PR97
10K_0402_1%
PR177
10K_0402_1%
PD24
RB751V_SOD323
1 2
12
PC73
PR96
10_0402_5%
1 2
PC153
1U_0603_10V6K
1 2
12
+2.5VALWP
PQ48
2N7002_SOT23
4.7U_1206_25V6K
13
D
S
PC65
SI4814DY_SO8
1
D1
2
D1
3
G2
4
S2
+5VALWP
2
G
PQ50
2N7002_SOT23
PQ17
D
S
S1/D2
S1/D2
S1/D2
12
13
12
12
PC164
2200P_0402_50V7K
+2.5V/+1.25V
DDR Termination Voltage
12
PR90
100K_0402_5%
8
G1
7
6
5
PR190
10K_0402_1%
2
G
PL9
3UH_SPC-07040-3R0_5A_30%
1 2
+3VS
PR192
10K_0402_1%
1 2
12
PC155
0.1U_0402_16V4Z
220U_D2_4VM
0_0402_5%
PR189
PC74
+1.25V
+1.25VSP
1
+
PD31
2
EP10QY03
2 1
12
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
A
B
INC.
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDR_2.5V/1.25V/1.8V
LA-2101
D
48 52Saturday, November 22, 2003
0.1
of
Page 49
A
B
C
D
+5VALW
PR98
0_1206_5%
PC81
1 2
5
PU8
IN
1
HSD
BST
DH
LX
2
COMP
4
GND
MAX1954EUB_10UMAX
DL
PGND
FB
12
12
PC80
12
10P_0402_50V8J
10
8
9
6
7
3
21
PD27
EP10QY03
PC77
12
0.1U_0402_16V4Z
1
2
3
4
D1
G1
S1/D2
D1
S1/D2
G2
S2
S1/D2
PQ19
SI4814DY_SO8
12
PC75
22U_1210_6.3V6M
8
7
6
1 2
5
12
PL10
2.2UH_PLFC1235P-2R2A_6A_30%
PR99
8.06K_0402_1%
PR101
9.09K_0402_1%
PC76
22U_1210_6.3V6M
12
12
PC78
220U_D2_4VM@
1
+
2
+1.5V
+1.5VSP
1
+
PC79
2
220U_D2_4VM
1 1
+3VS +5VALW
12
PR198
12
10K_0402_1%
PR199
10K_0402_1%
PC160
2 2
0.1U_0402_16V4Z
1 2
2
PQ54
2N7002_SOT23
G
13
D
2
G
S
13
D
PQ53
2N7002_SOT23
S
390P_0402_50V7K
PR100
220K_0402_1%
+5VALW
PR102
0_1206_5%
1 2
5
PU9
IN
1
HSD
BST
DH
3 3
PR201
20K_0402_1%
PC161
0.1U_0402_16V4Z
4 4
12
2
4
PR203
100K_0402_5%
COMP
GND
MAX1954EUB_10UMAX
12
B
PR200
12
10K_0402_1%
13
D
PQ55
2
G
2N7002_SOT23
S
13
D
2
G
S
PQ22
2N7002_SOT23
180K_0402_1%
390P_0402_50V7K
PR104
PC88
12
12
12
PC87
15P_0402_50V8J
1 2
POWER_SEL17
A
+3VS +5VALW
2
G
PGND
+5VALW
LX
DL
FB
12
PR202
10K_0402_5%
13
D
S
10
8
9
6
7
3
PQ56
2N7002_SOT23
21
PD28
EP10QY03
PC84
12
0.1U_0402_16V4Z
1
2
3
4
SI4814DY_SO8
2
G
12
PC82
22U_1210_6.3V6M
8
G1
D1
2.2UH_SPC-1205P-2R2B_13A_30%
7
D1
S1/D2
6
G2
S2
PQ21
S1/D2
S1/D2
13
D
S
1 2
5
PQ23
2N7002_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
INC.
12
PL11
PR103
4.53K_0402_1%
PC83
22U_1210_6.3V6M
12
12
PR105
9.09K_0402_1%
12
PR106
9.09K_0402_1%
C
+1.2V/1.0V
+VGA_COREP
1
1
+
+
2
PC85
220U_D2_4VM@
2
PC86
220U_D2_4VM
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
1.5V/VGA_CORE
LA-2101
D
49 52Saturday, November 22, 2003
of
0.1
Page 50
A
1 1
H_VID45
H_VID35
H_VID25
H_VID15
H_VID05
H_VID55
PR125
PM_DPRSLPVR24
PM_STPCPU#5,24
2 2
1 2
1 2
PC102
100P_0402_50V8J
0_0402_5%
PR124
0_0402_5%
120W(4-phase) 90W(3-phase)
PR129
3 3
PR131
PR127
4 4
+3VALWP
VID_PWRGD5
360_0402_1%
20K_0402_1%
UNPOP
PR146
0_0402_5%
VR_ON39
300_0402_1%
17.4K_0402_1%
12
12
POP
1.2VDD
PC108
4.7U_1206_16V4Z
PR154
0_0402_5%
A
VCORE_ENLL5
12
PR129
360_0402_1%
12
12
PR131
20K_0402_1%
12
PR156
100K_0402_5%
1 2
12
PR144
45.3K_0402_1%
PU13
1
IN
4
PG
3
EN
MIC5258_SOT23-5
PR130
69.8K_0402_1%
7
0
LM358A_SO8
PR136
10K_0402_1%
1 2
1 2
OUT
GND
Frequency Select
PU5B
5
+
6
-
12
PR141
32.4K_0402_1%
5
2
PR133
12
100K_0402_1%
12
+3VALWP
+VCCVIDP
12
PC109
4.7U_1206_16V4Z
PR140
10K_0402_5%@
2N7002_SOT23
B
+5VALWP
+5VS
PR126
PR185
0_0603_5%
PC99
1U_0603_10V6K
12
PC100
0.047U_0603_16V7K
12
PR134 0_0402_5%@
1 2
PC105
12
220P_0402_50V9J
@
330K_0402_5%@
1 2
Panasonic ERTJ0EV334J (0402)
Locate this NTC resistor on
PCB between phase 2 and 3
for thermal compensation.
13
D
PQ29
2
G
S
1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line
(Northwood="0",Prescott="1")
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
B
0_0603_5%@
1 2
1 2
PU12
32
VCC
2
VID3
3
VID2
4
VID1
5
VID0
6
VID12.5
34
ENLL
33
DRSEN
35
DSEN#
10
OCSET
11
SOFT
9
DSV
36
FS
37
DRSV
38 14
VR-TT# NC
40
H_BOOTSELECT4
NTC
12
GND
19
GND
ISL6247_MLFP40
PR138
RAMPS
PGOODVID4
PWM1
ISEN1+
ISEN1-
PWM2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
COMP
VDIFF
1M_0402_1%
2
G
22K_0402_5%
12
PR155
100K_0402_5%
C
B+
Battery Feed
PR145 340K_0402_1%
12
1 2
2
B
Forward
PR123
10K_0402_5%
1 2
PR135
0_0402_5%@
+5VS
PR148 27K_0402_5%
1 2
2
G
C
1
3
E
PQ31
MMBT3904_SOT23
12
12
PR127
0_0402_5%@
12
Place close to IC
PC106
0.1U_0402_16V4Z
1 2
PR147
5.1K_0402_1%
1 2
13
D
PQ30
2N7002_SOT23
S
C
+5VS
PC101
2200P_0402_50V7K
PC104
1000P_0402_50V7K@
12
PC107
1U_0603_10V6K
PR151
0_0402_5%
PR152
0_0402_5%@
20K_0402_1%
1 2
12
12
22P_0402_50V8J
PR137
0_0402_5%@
12
2N7002_SOT23
12
12
PR132
PC103
1 2
PQ27
PR149
0_0402_5%
0_0402_5%@
PR122
80.6K_0402_1%
7
391
25
24
23
26
27
28
20
21
22
31
30
29
15
13
FB
16
17
VSEN
18
VRTN
8
OFS
PR142
13
D
PQ28
S
TP0610T_SOT23
PR153
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
INC.
VCORE_PWRGD 27
PWM1 51
ISEN1+ 51
ISEN1- 51
PWM2 51
ISEN2+ 51
ISEN2- 51
PWM3 52
ISEN3+ 52
ISEN3- 52
PWM4 52
ISEN4+ 52
ISEN4- 52
12
PR139
2.26K_0402_1%
S
PR150
VSSSENSE 5
PR143
16.2K_0402_1%
D
13
G
2
12
+CPU_CORE
12
Place near +VCC_CORE
output capacitor
VCCSENSE 5
Title
Size Document Number Rev
Date: Sheet
D
12
Remote
Sensing
Compal Electronics, Inc.
CPU_CORE_Controller
LA-2101
D
50 52Saturday, November 22, 2003
0.1
of
Page 51
A
B
C
D
+5VALWP
+5VS
PR186
0_0603_5%
1 1
PR187
0_0603_5%@
+5VP1
1 2
1 2
PR157
3_0402_5%
1 2
PWM1 50
12
PR158
1 2
0_0402_5%
PC116
0.1U_0402_16V4Z
1 2
1U_0805_25V4Z
PC117
1 2
PR159
499K_0402_1%
CPU_DRIVE_EN
0.22U_0805_16V7K_V2
PU14
6
BOOT
VCC
3
PWM
UGATE
7
EN
PHASE
LGATEGND
ISL6207CB-T_SO8
PC110
12
N5
PR160
1_0402_5%
PHASE1
PQ34
SI4362DY_SO8
12
2
1
8
54
5
PQ32
SI7392DP_SO8
3
241
876
876
5
DDD
D
SSG
S
134
2
5
DDD
D
PQ35
SI4362DY_SO8
SSG
S
134
2
CPU_B+
PC111
1 2
4.7U_1206_25V6K
12
PC112
4.7U_1206_25V6K
12
PC113
4.7U_1206_25V6K
12
PC141
470P_0402_50V7K
Panasonic ETQ-P4LR56WFC
PL14
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PR161
32.4K_0402_1%
12
PL13
1 2
C8B BPH 853025_2P
12
PC142
0.1U_0603_25V7K
PC119
0.01U_0402_25V7Z
12
B+
1
+
PC149
220U_25V_M
2
N6
PH3
ISEN1-50
ISEN1+50
2 2
PR163
3_0402_5%
1 2
PWM2 50
PR164
499K_0402_1%
1 2
PC125
1U_0805_25V4Z
1 2
PC120
0.22U_0805_16V7K_V2
1 2
PU15
6
BOOT
VCC
3
PWM
UGATE
7
EN
PHASE
LGATEGND
ISL6207CB-T_SO8
5
3
241
PQ36
SI7392DP_SO8
876
5
D
S
134
2
DDD
PQ39
SI4362DY_SO8
SSG
PR165
2
1_0402_5%
N7
1
8
54
12
PHASE2
PQ38
SI4362DY_SO8
876
5
DDD
D
SSG
S
134
2
12
PC121
4.7U_1206_25V6K
CPU_B+
PC123
4.7U_1206_25V6K
12
Local Transistor
Swtich Decoupling
12
PC122
4.7U_1206_25V6K
0.56UH_ETQP4LR56WFC_21A_20%
PR166
32.4K_0402_1%
12
PL15
1 2
12
820_0402_5%
PC143
470P_0402_50V7K
Panasonic ETQ-P4LR56WFC
PC126
0.01U_0402_25V7Z
12
12
PC144
0.1U_0603_25V7K
12
12
PD30
EC31QS04
+CPU_CORE
3 3
ISEN2-50
ISEN2+50
4 4
A
N8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
B
INC.
Local Transistor
Swtich Decoupling
C
PH4
820_0402_5%
12
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU_CORE_Power stage 1
LA-2101
D
51 52Saturday, November 22, 2003
0.1
of
Page 52
A
PC127
0.22U_0805_16V7K_V2
1 2
+5VP1
1 1
PWM3 50
PR169
499K_0402_1%
1U_0805_25V4Z
1 2
PC131
PR168
3_0402_5%
1 2
1 2
PU16
6
VCC
3
PWM
UGATE
7
EN
PHASE
LGATEGND
ISL6207CB-T_SO8
BOOT
2
1
8
54
PR170
1_0402_5%
N9
PHASE3
SI4362DY_SO8
PQ42
B
C
D
CPU_B+
PC129
PC128
5
PQ40
SI7392DP_SO8
12
4.7U_1206_25V6K
4.7U_1206_25V6K
12
PC130
4.7U_1206_25V6K
12
3
12
241
876
876
5
DDD
D
SSG
S
134
2
5
DDD
D
PQ43
SI4362DY_SO8
SSG
S
134
2
PL16
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PR171
32.4K_0402_1%
12
PC145
470P_0402_50V7K
12
Panasonic ETQ-P4LR56WFC
PC133
0.01U_0402_25V7Z
12
12
PC146
0.1U_0603_25V7K
N10
PH5
ISEN3-50
CPU_DRIVE_EN
2 2
PWM4 50
PR174
499K_0402_1%
1 2
ISEN3+50
PC138
1U_0805_25V4Z
PR173
3_0402_5%
1 2
1 2
6
3
7
PC134
0.22U_0805_16V7K_V2
1 2
PU17
BOOT
VCC
PWM
UGATE
EN
PHASE
LGATEGND
ISL6207CB-T_SO8
CPU_B+
5
PQ44
SI7392DP_SO8
N11
PR175
1_0402_5%
PHASE4
PQ46
SI4362DY_SO8
3
12
241
876
5
DDD
D
SSG
S
134
2
876
5
DDD
D
PQ47
SI4362DY_SO8
SSG
S
134
2
2
1
8
54
12
PC135
4.7U_1206_25V6K
PC136
12
4.7U_1206_25V6K
12
PC137
4.7U_1206_25V6K
Local Transistor
Swtich Decoupling
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PR176
32.4K_0402_1%
12
12
PL17
820_0402_5%
PC147
470P_0402_50V7K
12
PC148
0.1U_0603_25V7K
Panasonic ETQ-P4LR56WFC
PC140
0.01U_0402_25V7Z
12
+CPU_CORE
12
N12
3 3
ISEN4-50
ISEN4+50
PH6
820_0402_5%
12
PC134,PC135,PC136,PC137,PC138,PC140,
PC147,PC148,PR173,PR174,PR175,PR176,
PQ44,PQ46,PQ47,PU17,PL17,PH6
120W(4-phase)
90W(3-phase)
4 4
A
POP
UNPOP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS,
B
INC.
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CPU_CORE_Power stage 2
LA-2101
D
52 52Saturday, November 22, 2003
0.1
of
Page 53
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