Compal LA-2051 DFL10 Sapporo XA, Satellite A30 Schematic
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
MODEL NAME :
COMPAL P/N :
PCB NO :
Revision :
2 2
LA-2051
0.1A
Sapporo XA
DFL10
Sapporo XA Schematics Document
uFCBGA/uFCPGA NorthWood MT
2003 8 27 v0.1A
3 3
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Do cum e nt Number R e v
LA-2051
Dat e : Sheet
Com pal Electronics, Inc.
Cover Sheet
期四 八月
0.1A
of
151¬P , 28, 2003
E
A
B
C
D
E
Compal confidential
Block Diagram
Model : DFL10 LA-2051
1 1
Fan Control 1
+12VALW
+5VALW
Fan Control 2
+12VALW
+5VALW
page 37
page 37
CPU B ypass
page 6
+1.2VP
+CPU_CORE
TV OUT Connector
+3VS
CRT Connector
+5VS
+3VS
2 2
LVDS Conn e ctor
B+
page 17
page 18
page 18
CRT Signal
LVDS Signal
+1.5VS
+2.5V
+3VS
+CPU_CORE
USB2.0 CTRL.
NEC uPD720101
page 24
+3VS 33MHz
IDSEL:AD18
PIRQC#
Minipci CONN
WIRELESS & Dubug
+3V
+3VS
+5VS
3 3
page 25
+3V
+2.5VLAN
IDSEL:AD19
PIRQD#
LAN
RTL 8101L
page 22
RJ45
page 23
IDSEL:AD20
PIRQB#
CardBus
CB1410
+3V
+3VS
PWR Controller & Slot
+12VALW +5VALW
+3VALW
page 20
page 21
+3V
+3VS
1394 Conn.
PCI BUS
IDSEL:AD16
PIRQA#
IEEE 1394
TSB43AB21
page 19
page 19
Super I/O
LPC47N217
On/Off BTN &
User Keys
+3VALW
page 37
Power Circuit
DC/DC
4 4
page 40
A
SW Bo ard Conn
+5VALW
RTC Batt.
page 37
page 37
DC/DC Interface
Suspend
page 36
B
+3VS
Parallel
+5VS
page 34
Debug COM Port
+5V
page 34
FIR
+3VS
page 34
Nort hWood-MT -- 533
Prescot t -MT -- 533
Celeron-MT -- 400
uFCPGA CPU
System Bus
400/533 MHz
ATI RC300ML
718 pin u-BGA
A LINK
+1.5VS
66MHz
+3VS
+3VALW
+1.5VS
+1.5VALW
+CPU_CORE
VCC5REF
VCC5REFSUS
ATI IXP150
457 BGA
LPC BUS
page 34
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
478pin
page 4,5,6
HD#(0..63)HA#( 3..31)
page 7,8,9,10,11,12
page 26,27,28,29
+3VS
33MHz
Embedded Controller
NS PC87591L
+3VS
+3VALW
EC DEBUG & Int. KB
+5VALW
C
+3VALW
+3VALW
+5VALW
LID SW & Kill SW
+3VALW
+5VS
page 31
page 31
BIOS & Ext. IO
page 32
page 31
Touch Pad
page 31
LID Hibernation
+RTC_VREF
page 39
Therm al Sensor
ADM1032AR
+5VS +3VS
page 6
Memory
BUS(DDR)
48MHz
24.576MHz
IDE HDD
+5VS
+2.5V 333MHz
USB 2.0/1.1
AC-LINK
ATA100
IDE ODD
+5VCD
page 30
PIDE IRQ15SIDE IRQ14
D
Clock Generator
ICS951 402AGT
page 30
AMP TPA0232
+5VALW
INT. Speaker
page 33
Title
Size Docu ment Number Re v
Date: Sheet
page 16
DDR-DIMM X2
BANK 0, 1, 2, 3
+2.5V
+1.25VS
page 13,14,15
+5V
AC97 Codec
ALC202A
+5VALW -> +VDDA
+3VS
page 33
HeadPhone
+AUD_VREF
page 33
LA-2051
星期三 八月
page32
Compa l Electronics, Inc.
Block Di agram
27, 2003
USB Ports X3
( X1 reserve )
page 27
MDC
+5VS
+3VS
+3V
page 23
RJ11
Cable
MIC Phone
+5VDDA
LINE IN
+5VDDA
E
Cable
page 33
251,
0.1A
of
5
4
3
2
1
Power Managment table
Voltage Rails
Power Plane
VIN
D D
C C
B+
+CPU _CORE Core voltage for CPU
+1.2V
+1.25VS
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Description
Adapte r power supply (19V)
AC or battery power rail for power circuit.
The vo l tage f or Processor VID select
1.25V switched powe r r a il for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V swit c he d p o we r ra il for ATI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
S0-S1
S3
S5
N/A
N/AONN/A
N/A
N/A
N/A
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
ON
ON
OFF
OFF
OFF OFF
OFF
OFF
OFF
OFF
OFF
ONON
ON*
ON
OFF
OFF
OFF
ON*
ON
OFF
ON
OFF
ON
ON*+5VALW 5V always on power rail
OFF
ONON
ON*
ON
Signal
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
+3VALW
+5VALW
+12VALW
ON
ON ON ON
ON ON
ON OFF
OFF OFF OFF
+5V
+3V
+2.5V
ON ON
+2.5VS
+1.8VS
+5VS
+3VS
+1.5VS
+CPU_CORE
+1.25VS
OFF
OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board I D Ta ble f or AD c hanne l
Vcc 3.3V +/- 5%
External PCI Devices
Board ID
IDSEL # PIRQREQ/GNT #DEVICE
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
B B
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
N/A
AGP_DE VSEL
AD31 ( INT .)
AD30 ( INT .)
AD31 ( INT .)
AD31 ( INT .)
AD24(INT.)
AD16
AD19
AD20
AD18
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
A
A
N/A
D
B
A
C
A
D
A
C
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
Board ID
0
AD_BID
0 V
Vtyp
AD_BID
0 V 0 V
V
AD_BID
max
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1 .264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
PCB Revision
0.1
1
EXT USB AD23(EXT.) 4 A,C,D
2
3
EC SM Bus1 address
Device Address Address
Smart Battery
EEPROM(24C16)
A A
I2C / S MB U S ADDRESSING
1010 000X b
EC SM Bus2 address
Device
ADM1032
1001 100X b0001 011X b
DEVICE HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
5
A2
D2
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
5
6
7
Title
Size Do cum e nt Number R e v
2
Dat e : Sheet
Compal Electronics, Inc.
Note & Revision
LA-2051
期三 八月
1
0.1A
of
351¬P , 27, 2003
5
D D
A10
A12
A14
A16
A18
JCPU1A
HA#[3..31]7 HD#[0..63] 7
C C
H_REQ#[0..4]7
+CPU_CORE
+CPU_CORE
B B
H_REQ#[0..4]
H_ADS#7
R4 56_0402_5%
1 2
R36 51_0402_5%
1 2
H_BREQ0#7
H_BPRI#7
H_BNR#7
H_LOCK#7
CLK_CPU_BCLK16
CLK_CPU_BCLK#16
H_HIT#7
H_HITM#7
H_DEFER#7
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
CLK_CPU_BCLK
CLK_CPU_BCLK#
FOX_PZ47803-274A-42_Prescott
AB1
AC1
AA3
AC3
AF22
AF23
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
J1
K5
J4
J3
H3
G1
V5
H6
D2
G2
G4
F3
E3
E2
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
CON
HIT#
TROL
HITM#
DEFER#
A20
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
HOST
ADDR
CONTROL
CLK
VSS_0H1VSS_1H4VSS_2
H23
H26
4
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
POWER
Northwood-MT
Prescott-MT
GND
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
A11
A13
A15
A17
A19
A21
A24
A26
AA1
AA11
AA13
AA4
AA7
AA15
AA17
AA9
AA19
AA23
AA26
AB10
AB12
AB3
AB6
AB14
AB16
AB18
AB8
AB20
AB21
AB24
3
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
VCC_67
VCC_68
VCC_69
HOST
ADDR
POWER
VCC_78
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
AC2
AC5
AC7
AC11
AC13
AC15
AC17
AC19
AC9
AC22
AC25
AD10
AD12
AD14
AD16
AD18
BOOTSELECT
VSS_52
VSS_53
VSS_54
VSS_55
VCC_81
F13
AD1
AD4
AD8
AD21
AD23
VCC_79E8VCC_80
VCC_82
VCC_83
VCC_84
VCC_85
F9
F11
F15
F17
F19
E18
E20
VCC_70
VCC_77
E16
D9
VCC_71D7VCC_72
VCC_76
E14
E10
VCC_75
E12
2
+CPU_CORE
VCC_73
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
+CPU_CORE
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
1
HD#[0..63]HA#[3..31]
BOOTSELECT
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
0_0402_5%
12
R8
Compal Electronics, Inc.
Title
Prescott / P4 uFCPGA (1/2)
Size Do cum e nt Number R e v
LA-2051
Custom
2
Dat e : Sheet
期三 八月
451¬P , 27, 2003
1
0.1A
of
5
JCPU1B
+CPU_CORE
1 2
R56 51_0402_5%
D D
1 2
R59 51_0402_5%
1 2
R47 51_0402_5%
1 2
R46 51_0402_5%
1 2
R55 51_0402_5%
1 2
R57 51_0402_5%
+CPU_CORE
R2 150_0402_5%
R51 39.2_0603_1%
C C
B B
1 2
R586 75_0402_5%
R43 680_0402_5%
R52 27.4_0603_1%
+CPU_CORE
L27
1 2
LQG21F4R7N00_0805
1 2
LQG21F4R7N00_0805
L26
@33U_D2_8M_R35
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TDI
12
ITP_TMS
12
ITP_TDO
ITP_TRST#
12
ITP_TCK
12
C423
H_RS#[0..2]7
1
1
+
2
2
CLK_CPU_ITP16
CLK_CPU_ITP#16
Comp0/1 need keep 25
mils trace width
+CPU_CORE
Place near SB200
R560 56_0402_5%
1 2
R1 56_0402_5%
1 2
R66 56_0402_5%
1 2
A A
1 2
R64 300_0402_5%
H_FERR#
Place near CPU
H_THERMTRIP#
H_RESET#
H_PW RGD
PM_STPCPU#10,16,26,47
5
H_TRDY#7
H_A20M#26
H_FERR#26
H_IGNNE#26
H_SMI#26
H_PWRGD26
H_STPCLK#26
H_INTR26
H_NMI26
H_INIT#26
H_RESET#7,26
H_DBSY#7
H_DRDY#7
BSEL012,16
BSEL112,16
H_THERMDA6
H_THERMDC6
H_THERMTRIP#6
+
C422
33U_D2_8M_R35
H_RS#[0..2]
H_THERMTRIP#
VCCIOPLL
VCCA
VCCSENSE47
VSSSENSE47
1 2
+1.2V
R587 0_0402_5%
VSSA
1 2
R96 51.1_0603_1%
1 2
R11 51.1_0603_1%
If CPU is P4 , Change the
resistor R539,R540 value to
51.1_0603_1%,or prescott
61.9 _0603_1%
R7
1 2
4.7K_0402_5%
2
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PW RGD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
BSEL0
BSEL1
H_THERMDA
H_THERMDC
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
VCCSENSE
VSSSENSE
COMP0
COMP1
+3VS
12
Q2
MMBT3904_SOT23
3 1
F1
G5
F4
AB2
J6
C6
B6
B2
B5
AB23
Y4
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
AE23
A5
A4
AF3
AD22
AC26
AD26
L24
P1
R9
4.7K_0402_5%
2
3 1
4
GND
AE11
AE13
VSS_57
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
VSS_58
CON
TROL
LEGACY
ITP
CLK
VSS_129F8VSS_130
G21
H_DPSLPR#
Q1
MMBT3904_SOT23
4
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
MISC
THER
MAL
MISC
ITP
MISC
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
J22
J25
K21
G24
FOX_PZ47803-274A-42_Prescott
K24
3
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
GROUND
Northwood-MT
Prescott-MT
GROUND MISC
VID0
VID1
VID2
AE5
AE4
AE3
AE2
CPU_VID2
CPU_VID0
CPU_VID1
CPU_VID3
L23
VSS_144
L26
VSS_145L4VSS_146M2VSS_147
M22
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
VSS_181
T21
P22
N21
M25
P25
N24
Reserve
for EMI.
Near CPU.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
T24
R23
R26
3
V23
V26
U22
U25
+3VS
W21
W24
10K_1206_8P4R_5%
RP1
1 8
2 7
3 6
4 5
R6 10K_0402_5%
1 2
R5 10K_0402_5%
1 2
CPU_VID[0..5]47
Y5
Y22
Y25
VID3
CPU_VID4
AE1
VID4
F10
AD3
CPU_VID5
F12
VID5
VSS_121
2
F14
F16
F18
VSS_122
VSS_123
VSS_124
VIDPWRGD
AD2
2
R403
@33_0402_5%
AF26
F22
F25
F5
VSS_125F2VSS_126
VSS_127
VSS_128
SKTOCC#
GTLREF0
GTLREF1
GTLREF2
REF
ITP
DATA
ADDR
GTLREF3
OPTIMIZED/COMPAT#
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DATA
MISC
Pop: Prescott
Depop: Northwood
PROCHOT#
VCCVID
AF4
R12
@2.43K_0603_1%
MCERR#
1
H_SKTOCC#
DP#0
DP#1
DP#2
DP#3
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
SLP#
NC1
NC2
NC3
NC4
NC5
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
A7
AF25
AF24
AE21
12
H_GHI#
H_DPSLPR#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_GHI#
1 2
0_0402_5%
+H_GTLREF
C47
1 2
220P_0603_50V8J
R_G
R404 0_0402_5%
1 2
1 2
R408 56_0402_5%
1 2
R409 56_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
12
R410 150_0402_5%
1 2
R10 100K_0402_1%
H_PROCHOT#
H_SLP#
GTL Ref e r e n c e V o l tage
R42
R58 56_0402_5%
R60 56_0402_5%
R38 56_0402_5%
R45 56_0402_5%
R39 56_0402_5%
R35 300_0402_5%
R405 56_0402_5%
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_ADSTB#0 7
H_ADSTB#1 7
H_DBI#[0..3] 7
+3VALW
+CPU_CORE
H_PROCHOT# 26,46
H_SLP# 26
CPU_GHI# 27
+CPU_CORE
Layout note :
1. Place R_A and R_B near CPU (With in 1. 5").
+1.2V
1
C1
0.1U_0402_10V6K
2
12
+1.2V
H_VID_PWRGD 38
Compal Electronics, Inc.
Title
Prescott / P4 uFCPGA & Thermal sensor (2/2)
Size Do cum e nt Number R e v
LA-2051
Custom
Dat e : Sheet
期三 八月
+CPU_CORE
12
R74
49.9_0603_1%
12
R67
100_0603_1%
+H_GTLREF
1
C50
1U_0603_6.3V6M
2
of
551¬P , 27, 2003
1
0.1A
A
Layout n ote :
1 1
+CPU_CORE
2 2
+CPU_CORE
Place close to CPU, Use 2~3 vias per PAD.
Place 22uF caps x31 pcs, populated 14pcs.
1
C396
22U_1206_6.3V6M
2
1
C384
22U_1206_6.3V6M
2
B
1
C388
22U_1206_6.3V6M
2
1
C380
22U_1206_6.3V6M
2
C
Place on CPU inside
1
C383
22U_1206_6.3V6M
2
1
C398
22U_1206_6.3V6M
2
1
C379
22U_1206_6.3V6M
2
1
C390
22U_1206_6.3V6M
2
1
C397
22U_1206_6.3V6M
2
1
C385
22U_1206_6.3V6M
2
D
1
C389
22U_1206_6.3V6M
2
1
C381
22U_1206_6.3V6M
2
E
Layout n ote :
Place close to CPU power and
ground pin as possible
(<1inch)
For Desktop's CPU:
470uFx15/12mOhm H=1.8 each
Total 0.923m ohm
F
+CPU_CORE
+CPU_CORE
+CPU_CORE
1
+
2
1
+
2
1
+
2
G
C377
470U_D4_2.5VM
C407
470U_D4_2.5VM
C40
470U_D4_2.5VM
1
+
2
1
+
2
1
+
2
C382
470U_D2_2.5VM
C419
470U_D4_2.5VM
C48
470U_D4_2.5VM
H
1
+
2
1
+
2
1
+
2
C392
@470U_D4_2.5VM
C30
470U_D4_2.5VM
C58
470U_D4_2.5VM
+
+
1
+
2
I
1
C401
470U_D4_2.5VM
2
1
C33
470U_D4_2.5VM
2
C65
470U_D4_2.5VM
1
+
2
1
+
2
C404
470U_D4_2.5VM
C36
470U_D4_2.5VM
J
3 3
+CPU_CORE
1
C409
22U_1206_6.3V6M
2
4 4
+CPU_CORE
1
2
C412
22U_1206_6.3V6M
5 5
+CPU_CORE
1
C21
22U_1206_6.3V6M
2
+CPU_CORE
6 6
1
C74
22U_1206_6.3V6M
2
Please place these cap on the socket north side
1
C413
22U_1206_6.3V6M
2
1
C408
22U_1206_6.3V6M
2
1
C414
22U_1206_6.3V6M
2
1
C418
22U_1206_6.3V6M
2
1
C415
22U_1206_6.3V6M
2
1
C410
22U_1206_6.3V6M
2
Please place these cap on the socket sourth side
1
C22
22U_1206_6.3V6M
2
1
C75
22U_1206_6.3V6M
2
1
C23
22U_1206_6.3V6M
2
1
C20
22U_1206_6.3V6M
2
1
C19
22U_1206_6.3V6M
2
1
C416
22U_1206_6.3V6M
2
1
C72
22U_1206_6.3V6M
2
1
C411
22U_1206_6.3V6M
2
1
C417
22U_1206_6.3V6M
2
1
C73
22U_1206_6.3V6M
2
+CPU_CORE
1
C82
@0.22U_0603_10V7K
2
1
C81
@0.22U_0603_10V7K
2
+CPU_CORE
H_THERMTRIP#5 MAINPWON 41,42,44
R3 300_0402_5%
1
C80
@0.22U_0603_10V7K
2
12
H_THERMTRIP#
1
C18
@0.22U_0603_10V7K
2
C2 @1U_0603_10V6K
2SC2411K_SC59
2
Q3
CBE
1
3
12
1
C17
@0.22U_0603_10V7K
2
1
C16
@0.22U_0603_10V7K
2
CPU Temperature Sensor
7 7
H_THERMDA5
8 8
H_THERMDC5
A
H_THERMDA
C39
2200P_0402_50V7K
H_THERMDC
EC_SMC235
EC_SMD235
B
1
2
+3VS
C
R63
1 2
200_0402_5%
U4
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
+3VS_VDD
1
C42
0.1U_0402_10V6K
2
VDD1
ALERT#
THERM#
GND
12
R54
10K_0402_5%
1
6
4
5
D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
E
F
G
H
Compal Electronics, Inc.
Title
CPU Decoupling CAP.
Size Docu ment Number Re v
LA-2051
Custom
Date: Sheet
星期三 八月
27, 2003
I
of
651,
J
0.1A
5
4
3
2
1
HA#[3..31]
H_REQ# [0 ..4 ]
HD#[0..63]
U24A
M28
CPU_A3#
P25
CPU_A4#
M25
CPU_A5#
N29
CPU_A6#
N30
CPU_A7#
M26
CPU_A8#
N28
CPU_A9#
P29
CPU_A10#
P26
CPU_A11#
R29
CPU_A12#
P30
CPU_A13#
P28
CPU_A14#
N26
CPU_A15#
N27
CPU_A16#
M29
CPU_REQ0#
N25
CPU_REQ1#
R26
CPU_REQ2#
L28
CPU_REQ3#
L29
CPU_REQ4#
R27
CPU_ADSTB0#
U30
CPU_A17#
T30
CPU_A18#
R28
CPU_A19#
R25
CPU_A20#
U25
CPU_A21#
T28
CPU_A22#
V29
CPU_A23#
T26
CPU_A24#
U29
CPU_A25#
U26
CPU_A26#
V26
CPU_A27#
T25
CPU_A28#
V25
CPU_A29#
U27
CPU_A30#
U28
CPU_A31#
T29
CPU_ADSTB1#
L27
CPU_ADS#
K25
CPU_BNR#
H26
CPU_BPRI#
J27
CPU_DEFER#
L26
CPU_DRDY#
G27
CPU_DBSY#
F25
CPU_BR0#
K26
CPU_LOCK#
A17
CPU_CPURSET#
G25
CPU_RS2#
G26
CPU_RS1#
J25
CPU_RS0#
F26
CPU_TRDY#
J26
CPU_HIT#
H25
CPU_HITM#
A9
CPU_RSET
AH5
SUS_STAT#
AG5
SYSRESET#
C7
POWERGOOD
V28
CPU_COMP_N
W29
CPU_COMP_P
H23
CPVDD
J23
CPVSS
W28
CPU_VREF
Y29
THERMALDIODE_N
Y28
THERMALDIODE_P
B17
TESTMODE
CHS-216IGP9050A21_BGA718
1U_0603_10V6K
1 2
C492
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BREQ0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF
12
R469
4.7K_0402_5%
D D
H_ADSTB#05
C C
H_ADSTB#15
H_ADS#4
H_BNR#4
H_BPRI#4
H_DEFER#4
H_DRDY#5
H_DBSY#5
H_BREQ0#4
H_LOCK#4
H_RESET#5,26
H_RS#25
SUS_STAT#27
NB_RST#26
NB_PWRGD17
1 2
1 2
L31
1 2
H_RS#15
H_RS#05
H_TRDY#5
H_HIT#4
H_HITM#4
0.1U_0402_10V6K
C590
--> 412_0402_1%
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+CPU_CORE
PLACE CLOSE TO U27 Ball
W28, USE 20/20
1 2
12
WIDTH/SPACE
1
C433
1U_0603_10V6K
2
1
C441
220P_0402_25V8K
2
C363 CLOSE
TO Ball W28
B B
R428
49.9_0603_1%
R429
100_0603_1%
+CPU_CORE
12
R485
1 2
330_0402_5%
R437 24.9_0402_1%
R436 49.9_0402_1%
+1.8VS
HB-1M2012-121JT03_0805
HA#[3..31] 4
H_REQ#[0..4 ] 4
HD#[0 ..6 3 ] 4
HD#0
L30
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
PART 1 OF 6
CPU_D9#
CPU_D10#
CPU_D11#
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
MISC.
CPU_DSTBN1#
CPU_DSTBP1#
AGTL+ I/F
PENTIUM
IV
CPU_DSTBN2#
CPU_DSTBP2#
CPU_DSTBN3#
CPU_DSTBP3#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
HD#1
K29
HD#2
J29
HD#3
H28
HD#4
K28
HD#5
K30
HD#6
H29
HD#7
J28
HD#8
F28
HD#9
H30
HD#10
E30
HD#11
D29
HD#12
G28
HD#13
E29
HD#14
D30
HD#15
F29
H_DBI#0
E28
H_DSTBN#0
G30
H_DSTBP#0
G29
HD#16
B26
HD#17
C30
HD#18
A27
HD#19
B29
HD#20
C28
HD#21
C29
HD#22
B28
HD#23
D28
HD#24
D26
HD#25
B27
HD#26
C26
HD#27
E25
HD#28
E26
HD#29
A26
HD#30
B25
HD#31
C25
H_DBI#1
A28
H_DSTBN#1
D27
H_DSTBP#1
E27
HD#32
F24
HD#33
D24
HD#34
E23
HD#35
E24
HD#36
F23
HD#37
C24
HD#38
B24
HD#39
A24
HD#40
F21
HD#41
A23
HD#42
B23
HD#43
C22
HD#44
B22
HD#45
C21
HD#46
E21
HD#47
D22
H_DBI#2
D23
H_DSTBN#2
E22
H_DSTBP#2
F22
HD#48
B21
HD#49
F20
HD#50
A21
HD#51
C20
HD#52
E20
HD#53
D20
HD#54
A20
HD#55
D19
HD#56
C18
HD#57
B20
HD#58
E18
HD#59
B19
HD#60
D18
HD#61
B18
HD#62
C17
HD#63
A18
H_DBI#3
F19
H_DSTBN#3
E19
H_DSTBP#3
F18
H_DBI#0 5
H_DSTBN#0 5
H_DSTBP#0 5
H_DBI#1 5
H_DSTBN#1 5
H_DSTBP#1 5
H_DBI#2 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DBI#3 5
H_DSTBN#3 5
H_DSTBP#3 5
+CPU_CORE
22U_1206_16V4Z_V1
A A
5
4
C486
0.1U_0402_10V6K
1
1
C541
C525
2
2
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C490
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C466
2
1
C465
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C464
2
2
1
C463
2
0.1U_0402_10V6K
1
C507
0.1U_0402_10V6K
2
2
Title
Size Docu ment Number Re v
Date: Sheet
Compa l Electronics, Inc.
ATI RC300M-AGT L+
27, 2003
LA-2051
星期三 八月
of
751,
1
0.1A
5
U24B
DDR_SMA0
DDR_SMA1
DDR_SMA2 DDR_SDQ2
DDR_SMA3
DDR_SMA4
D D
DDR_SBS013
DDR_SBS113
DDR_SMA1513
DDR_SRAS#13
DDR_SCAS#13
DDR_SWE#13
C C
DDR_CLK013
DDR_CLK0#13
DDR_CLK113
DDR_CLK1#13
DDR_CLK314
DDR_CLK3#14
DDR_CLK414
DDR_CLK4#14
DDR_CKE013,14
DDR_CKE113,14
DDR_CKE214
DDR_CKE314
DDR_SCS#013,14
DDR_SCS#113,14
DDR_SCS#214
DDR_SCS#314
L34
B B
+1.8VS
1 2
HB-1M2012-121JT03_0805
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SDM0
DDR_SDM1
DDR_SDM2
DDR_SDM3
DDR_SDM4
DDR_SDM5
DDR_SDM7
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
MPVDD
C516
MPVSS
1 2
1U_0603_10V6K
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
AJ8
AF9
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
CHS-216IGP9050A21_BGA718
4
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM I/F
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
0.1U_0402_10V6K
DDR_SDQ0
AG6
DDR_SDQ1
AJ7
AJ9
DDR_SDQ3
AJ10
DDR_SDQ4
AJ6
DDR_SDQ5
AH6
DDR_SDQ6
AH8
DDR_SDQ7
AH9
DDR_SDQ8
AE7
DDR_SDQ9
AE8
DDR_SDQ10
AE12
DDR_SDQ11
AF12
DDR_SDQ12
AF7
DDR_SDQ13
AF8
DDR_SDQ14
AE11
DDR_SDQ15
AF11
DDR_SDQ16
AJ12
DDR_SDQ17
AH12
DDR_SDQ18
AH14
DDR_SDQ19
AH15
DDR_SDQ20
AH11
DDR_SDQ21
AJ13
DDR_SDQ22
AJ15
DDR_SDQ23DDR_SDM6
AJ16
DDR_SDQ24
AF18
DDR_SDQ25
AG20
DDR_SDQ26
AG21
DDR_SDQ27
AF22
DDR_SDQ28
AF19
DDR_SDQ29
AF20
DDR_SDQ30
AE22
DDR_SDQ31
AF23
DDR_SDQ32
AJ21
DDR_SDQ33
AJ22
DDR_SDQ34
AJ24
DDR_SDQ35
AK25
DDR_SDQ36
AH21
DDR_SDQ37
AH22
DDR_SDQ38
AH24
DDR_SDQ39
AJ25
DDR_SDQ40
AK26
DDR_SDQ41
AK27
DDR_SDQ42
AJ28
DDR_SDQ43
AH29
DDR_SDQ44
AH25
DDR_SDQ45
AJ26
DDR_SDQ46
AJ29
DDR_SDQ47
AH30
DDR_SDQ48
AF29
DDR_SDQ49
AE29
DDR_SDQ50
AB28
DDR_SDQ51
AA28
DDR_SDQ52
AE28
DDR_SDQ53
AD28
DDR_SDQ54
AC29
DDR_SDQ55
AB29
DDR_SDQ56
AC26
DDR_SDQ57
AB25
DDR_SDQ58
Y26
DDR_SDQ59
W26
DDR_SDQ60
AE26
DDR_SDQ61
AD26
DDR_SDQ62
AA26
DDR_SDQ63
Y27
C645 0.47U_0603_16V7K
1 2
AF6
C432 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
C489
R468 49.9_0402_1%
+SDREF
2
1
1 2
3
DDR_SDM[0..7]
DDR_SDQ[0..63]
DDR _ S DQS[0..7]
DDR_SMA[0..12]
DDR_SDM[0..7] 13
DDR_SDQ[0..63] 13
DDR_SD QS [0 ..7 ] 13
DDR_SMA[0..12] 13
2
1
+2.5V
A A
0.1U_0402_10V6K
C547
1
2
@0.1U_0402_10V6K
1
C475
2
@0.1U_0402_10V6K
5
C572
1
C450
2
@0.1U_0402_10V6K
1
1
2
C600
@0.1U_0402_10V6K
2
Title
Size Docu ment Number Re v
4
3
2
Date: Sheet
Compa l Electronics, Inc.
ATI RC300M-DDR I/F
27, 2003
LA-2051
星期三 八月
0.1A
of
851,
1
5
A_PAR12,26
A_STROBE#26
A_ACAT#26
A_END#26
PCI_PIRQA#19,20,24,26
+1.5VS
12
AGPREF_8X
12
1
+
C506
2
0.1U_0402_10V6K
1
+
C523
2
0.1U_0402_10V6K
A_AD[0..31]
A_CBE#[0..3]
R517 0_0402_5%
A_DEVSEL#26
A_OFF#26
A_SBREQ#26
A_SBGNT#26
+3VS
+1.5VS
R523
1 2
0.1U_0402_10V6K
1
C540
2
0.1U_0402_10V6K
1
1
C508
2
2
5
@52.3_0603_1%
Ra
AGP8X_DET#
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
R529
1K_0402_1%
R533
1K_0402_1%
1 2
1 2
AGPREF_8X
C530
1
C565
2
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
8.2K_0402_5%
AGP8X_DET#
C615
1 2
0.1U_0402_10V6K
AGP_COMP
+3VS
R504
@47K_0402
1 2
0.1U_0402_10V6K
1
C524
2
0.1U_0402_10V6K
1
C548
2
AK5
AJ5
AJ4
AH4
AJ3
AJ2
AH2
AH1
AG2
AG1
AG3
AF3
AF1
AF2
AF4
AE3
AE4
AE5
AE6
AC2
AC4
AB3
AB2
AB5
AB6
AA2
AA4
AA5
AA6
Y3
Y5
Y6
AG4
AE2
AC3
AA3
AD5
AC6
AC5
AD2
W4
AD3
AD6
W5
W6
R500
V5
V6
K5
K6
M5
J6
J5
1
C513
2
0.1U_0402_10V6K
1
2
U24C
ALINK_AD0
ALINK_AD1
ALINK_AD2
ALINK_AD3
ALINK_AD4
ALINK_AD5
ALINK_AD6
ALINK_AD7
ALINK_AD8
ALINK_AD9
ALINK_AD10
ALINK_AD11
ALINK_AD12
ALINK_AD13
ALINK_AD14
ALINK_AD15
ALINK_AD16
ALINK_AD17
ALINK_AD18
ALINK_AD19
ALINK_AD20
ALINK_AD21
ALINK_AD22
ALINK_AD23
ALINK_AD24
ALINK_AD25
ALINK_AD26
ALINK_AD27
ALINK_AD28
ALINK_AD29
ALINK_AD30
ALINK_AD31
ALINK_CBE#0
ALINK_CBE#1
ALINK_CBE#2
ALINK_CBE#3
PCI_PAR/ALINK_NC
PCI_FRAME#/ALINK_STROBE#
PCI_IRDY#/ALINK_ACAT#
PCI_TRDY#/ALINK_END#
INTA#
ALINK_DEVSEL#
PCI_STOP#/ALINK_OFF#
ALINK_SBREQ#
ALINK_SBGNT#
PCI_REQ#0/ALINK_NC
PCI_GNT#0/ALINK_NC
AGP2_GNT#/AGP3_GNT
AGP2_REQ#/AGP3_REQ
AGP8X_DET#
AGP_VREF/TMDS_VREF
AGP_COMP
CHS-216IGP9050A21_BGA718
8X(M9+M10@)
169_0402_1%
Ra
324_0402_1%
Rb
100_0402_1%
Rc
0.1U_0402_10V6K
1
C549
C555
2
0.1U_0402_10V6K
+1.5VS
C564
0.1U_0402_10V6K
A_AD[0..31]12,26
A_CBE#[0..3]12,26
D D
C C
?
B B
Rb
Rc
+1.5VS +3VS
C557
47U_B_6.3VM
+1.5VS
A A
C487
47U_B_6.3VM
4
PART 3 OF 6
PCI Bus 0 / A-Link I/F
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C554
2
4
1
2
1
C529
2
PIR LAYOUT 92.06.23
1
C539
2
0.1U_0402_10V6K
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
4X(NAGP@)
52.1_0402_1%
1K_0402_1%
1K_0402_1%
10U_0805_10V4Z
1
C580
2
0.1U_0402_10V6K
1
C641
2
L
C633
0.1U_0402_10V6K
C628
0.1U_0402_10V6K
Note: P L A CE CLOSE TO U27 (NB RC30 0M)
C515
1
C640
2
0.1U_0402_10V6K
1
2
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP2_CBE#2/AGP3_CBE2
AGP_PAR
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
AGP_ST0
AGP_ST1
AGP_ST2
0.1U_0402_10V6K
1
1
C638
C639
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C627
C629
2
2
0.1U_0402_10V6K
3
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
E5
E6
T3
U2
G3
H2
R3
M1
L3
H1
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
DDC_CLK
C3
DDC_DAT
C2
AGP_SBA2
D4
AGP_SBA3
E4
AGP_SBA4
F6
AGP_SBA5
F5
AGP_SBA6
G6
AGP_SBA7
G5
L6
M6
L5
0.1U_0402_10V6K
1
C617
2
0.1U_0402_10V6K
1
C630
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C618
2
0.1U_0402_10V6K
1
C631
2
0.1U_0402_10V6K
3
0.1U_0402_10V6K
1
C602
2
0.1U_0402_10V6K
1
C556
2
1
C601
2
0.1U_0402_10V6K
1
C571
2
0.1U_0402_10V6K
@10U_0805_6.3V6M
C653
2.2K_0402_5%
ENBKL# 35
ENVDD 18
AGP_STP# 27
AGP_BUSY# 27
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C589
2
@0.1U_0402_10V6K
1
1
C656
2
2
R296
@0_0402_5%
R277
@0_0402_5%
Note: P L AC E CLOSE TO U2 (NB RC30 0M)
L
+3VS
R518
1 2
1 2
1
C605
2
0.1U_0402_10V6K
1
1
C608
C620
2
2
0.1U_0402_10V6K
2
12
12
R295
@0_0402_5%
S0
S1
12
12
@SM561BS_SO8
R276
@0_0402_5%
R519
2.2K_0402_5%
+1.5VS
@0.01U_0402_16V7Z
1
C568
C498
2
@0.01U_0402_16V7Z
1
2
2
+3VS_SSVDD
@0_0402_5%
R294
2
U44
VDD
1
Xin/CLK
SSCLK
7
6
LVDS SPREAD SPECTRUM
S0
S1
Xout
SSCC
VSS
3
R293
@0_0402_5%
ATI request
@0.01U_0402_16V7Z
1
1
C610
C569
2
2
@0.01U_0402_16V7Z
1
L42
1 2
@BLM21P300S_0805
12
12
R275
@0_0402_5%
4
8
1
C657
5
@10P_0402_25V8K
12
12
2
R274
@0_0402_5%
@0.01U_0402_16V7Z
1
1
1
2
C619
C585
2
2
@0.01U_0402_16V7Z
Title
Size Docu ment Number Re v
Date: Sheet
星期三 八月
+3VS
LVDS_SSOUT AGP_SBA6
1
C651
@10P_0402_25V8K
2
LVDS_SSIN
@0.01U_0402_16V7Z
1
C514
C609
2
@0.01U_0402_16V7Z
R534
@0_0402_5%
R535
@0_0402_5%
@0.01U_0402_16V7Z
1
1
C595
2
2
@0.01U_0402_16V7Z
12
12
Compal Electronics, Inc.
ATI RC300M-AGP, ALIN K BUS
LA-2051
27, 2003
1
AGP_SBA7
1
2
951,
C558
0.1A
of
5
D D
KC FBM -L11-201209-221LMAT_0805
L37
+1.8VS
C C
CLK_ AGP_66M
12
R272
@10_0402_5%
1
C282
@15P_ 0 402_50V8J
2
CLK_MEM_66M
12
B B
R271
@10_0402_5%
1
C271
@15P_ 0 402_50V8J
2
1 2
0.1U_ 0 402_10V6K
L33
+1.8VS
REFCLK1_NB16
+3VS
1
2
1 2
KC FBM-L11-201209-221LMAT _0805
L38
+1.8VS
KC FBM-L11-201209-221LMAT _0805
wait 1% new part
X4
4
VCC
1
ST
C592
@27MH Z_20P_6N
@0.1U _0402_16V7K
4
KC FBM -L11-201209-221LMAT_0805
1
2
1
C537
2
C577
0.1U_ 0 402_10V6K
R474 715 _0402_1%
12
12
R506
1
2
27M_TV
3
2
EXCLK_27M_TV38
+1.8VS_AV DDDI
R520
@10_0402_5%
C634
@15P_ 0 402_50V8J
R497 @22_0402_5%
C550
0.1U_ 0 402_10V6K
1 2
10U_0805_10V4Z
68_0402_5%
OUT
GND
L35
+1.8VS_AVDDQ
1
C536
0.1U_ 0 402_10V6K
2
1
1
C578
2
2
INTCRT_R18
INTCRT_G18
INTCRT_B18
INTCRT_HSYNC18
INTCRT_VSYNC18
1 2
CLK_NB_BCLK16
CLK_NB_BCLK#16
CLK_AGP_66M16
CLK_MEM_66M16
27M_TV_R
12
R505
@10_0402_5%
+2.5VS
12
1
C551
0.1U_ 0 402_10V6K
2
1
C586
0.1U_ 0 402_10V6K
2
12
+2.5VS_AVDD
+PLLVDD_18
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_BCLK
CLK_NB_BCLK#
CLK_AGP_66M
CLK_MEM_66M
12
4.7K_ 0402_5%
R588
+3VS_VDDR
+3VS
+3VS
L39
1 2
1
2
U24D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
D8
ALINK_CLK
B2
AGPCLKOUT
B3
AGPCLKIN
A3
EXT_MEM_CLK
D7
USBCLK
B7
REF27
C5
OSC
CHS-216IGP9050A21_BGA718
L
FBM-11-160808-121-T_0603
C622
0.1U_ 0 402_10V6K
PART 4 OF 6
CRT
CLK. GEN.
Note: PLACE CLOSE TO U27 (NB CHIP)
RC300M_X1
R531
@1M_0402_1%
RC300M_X2
3
D12
TXOUT_U0N
E12
TXOUT_U0P
F11
TXOUT_U1N
F12
TXOUT_U1P
D13
TXOUT_U2N
D14
TXOUT_U2P
E13
TXCLK_UN
F13
TXCLK_UP
E10
TXOUT_L0N
D10
TXOUT_L0P
B9
TXOUT_L1N
C9
TXOUT_L1P
D11
TXOUT_L2N
E11
TXOUT_L2P
B10
TXCLK_LN
C10
TXCLK_LP
A12
LPVDD_18
LVDS
12
A11
LPVSS
B12
LVDDR_18
C12
LVDDR_18
B11
LVSSR
C11
LVSSR
E15
C_R
C15
Y_G
D15
COMP_B
SVID
D6
DACSCL
C6
DACSDA
D5
CPUSTOP#
A8
SYSCLK
B8
SYSCLK#
C650
1 2
12
@18P_0402_50V8K
Y5
@14.3 1818MHZ_20P_6X1430004201
C649
1 2
@18P_0402_50V8K
LCD_B0- 18
LCD_B0+ 18
LCD_B1- 18
LCD_B1+ 18
LCD_B2- 18
LCD_B2+ 18
LCD_BCLK- 18
LCD_BCLK+ 18
LCD_A0- 18
LCD_A0+ 18
LCD_A1- 18
LCD_A1+ 18
LCD_A2- 18
LCD_A2+ 18
LCD_ACLK- 18
LCD_ACLK+ 18
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
TV_CRMA 17
TV_LUMA 17
TV_COMPS 17
@2N7002_SOT 23
0.1U_ 0 402_10V6K
INTDDCCK 18
INTDDCDA 18
S
G
1 2
R457 @0_0402_5%
1 2
R461 1K_0402_5%
C591
0.1U_0402_10V6K
C566
Q45
D
13
2
0.1U_ 0 402_10V6K
1
1
C576
2
2
0.1U_ 0 402_10V6K
1
1
C567
2
2
PM_STPCPU#
2
KC FBM -L11-201209-221LMAT_0805
1 2
L32
1
C518
2
10U_0805_10V4Z
KC FBM-L11-201209-221LMAT _0805
1 2
L36
1
C587
2
10U_0805_10V4Z
PM_STPCPU# 5,16,26,47
PCIR ST# 19,20 , 21,22, 24,25, 26, 30,34, 35
+3VS
1
+1.8VS
+1.8VS
A A
THIS SHEET OF ENGI N EERING DRAW I N G IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COM PAL ELECT RONICS , INC. N EITHER THIS SH EET NOR T HE INFO RMATIO N IT CON TAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT P RIOR WR ITTEN C ONSENT OF COMPA L ELECTR ONICS, INC.
2
Title
Size Document Number R ev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-VIDEO I/F
LA-2051
八月
1
0.1A
of
10 51星期T, 27, 2003
5
4
3
2
1
+1.5VS +2.5V
U24E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
D D
C C
B B
+CPU_CORE
+3VS
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
CHS-216IGP9050A21_BGA718
CORE PWR
CPU I/F PWRALINK PWR
PART 5 OF 6
MEM I/F PWR
POWER
AGP PWR
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
+3VS
+1.8VS
U24F
PART 6 OF 6
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
GND
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7
VSS
CHS-216IGP9050A21_BGA718
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8
+2.5V
+1.8VS
0.1U_0402_10V6K
C581
10U_0805_10V4Z
A A
5
2
4
2
0.1U_0402_10V6K
C482
1
1
C575
1
C481
2
0.1U_0402_10V6K
1
1
C588
0.1U_0402_10V6K
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C429
100U_D2_10VM
1
+
C505
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C445
2
1
C570
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C462
2
1
1
C436
2
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C553
2
0.1U_0402_10V6K
C538
0.1U_0402_10V6K
1
C522
2
0.1U_0402_10V6K
1
1
C461
C446
2
2
0.1U_0402_10V6K
Title
Size Docu ment Number Re v
Date: Sheet
星期三 八月
0.1U_0402_10V6K
1
1
C457
2
0.1U_0402_10V6K
1
C437
2
2
Compa l Electronics, Inc.
ATI RC300M-POWER
LA-2051
27, 2003
1
1
C438
0.1U_0402_10V6K
2
of
11 51,
0.1A
5
4
3
2
1
A_AD[0..31]9,26
A_CBE#[0..3]9,26
R418 10K_0402_5%
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
5
R420 4.7K_0402_5%
1 2
R419 4.7K_0402_5%
1 2
R549 10K_0402_5%
1 2
R278 @4.7K_0402_5%
1 2
R544 @10K_0402_5%
1 2
R283 4.7K_0402_5%
1 2
R548 10K_0402_5%
1 2
R279 @4.7K_0402_5%
1 2
R547 10K_0402_5%
1 2
R280 @4.7K_0402_5%
1 2
R545 10K_0402_5%
1 2
R282 @4.7K_0402_5%
1 2
R543 10K_0402_5%
1 2
R541 10K_0402_5%
1 2
R286 @4.7K_0402_5%
1 2
R284 @4.7K_0402_5%
1 2
R542 10K_0402_5%
1 2
R285 @4.7K_0402_5%
1 2
R540 @4.7K_0402_5%
1 2
R287 4.7K_0402_5%
1 2
R546 @4.7K_0402_5%
1 2
R281 @4.7K_0402_5%
1 2
R536 @4.7K_0402_5%
1 2
R291 @4.7K_0402_5%
1 2
1 2
R417 10K_0402_5%
1 2
2 1
D45
RB751V_SOD323
2 1
D44
RB751V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 5,16
+3VS
BSEL0 5,16
A_AD2 9: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27 : Fr cShortReset#
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD2 4 : M OBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTH ER CPU
A_AD2 3 : C L OCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD2 1 : A UTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE# 3: NOT USED
A_CBE# 0 :NO USED
4
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
A_CBE#[0..3]
R537 @4.7K_0402_5%
A_AD18
A_AD17
A_PAR9,26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
R290 4.7K_0402_5%
1 2
R538 @4.7K_0402_5%
1 2
R289 4.7K_0402_5%
1 2
A_PAR
R288 @4.7K_0402_5%
1 2
R539 4.7K_0402_5%
1 2
+3VS
+3VS
+3VS
2
A_AD1 8 : ENABLE PHASE CAL IBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
0: DEBUG MODE
1: NORMAL
Title
Size Docu ment Number Re v
Date: Sheet
Compa l Electronics, Inc.
ATI RC300M-SYSTEM STRAP
27, 2003
LA-2051
星期三 八月
of
12 51,
1
0.1A
A
0_1206_8P4R_5%
DDR_SDQ62 DDR_DQ62
DDR_SDQS7 DDR_DQS7 DDR_SDM7 DDR_DM7
DDR_SDQ63 DDR_DQ63
1 1
DDR_SDQ55 DDR_DQ55
DDR_SDQ54 DDR_DQ54
DDR_SDQ49 DDR_DQ49 DDR_SDQ53 DDR_DQ53
DDR_SDQ48 DDR_DQ48
DDR_SDQ43
DDR_SDQ47
DDR_SDQS5 DDR_SDM5
DDR_SDQ44
DDR_SDQ41
DDR_SDQ37
DDR_SDQ39 DDR_DQ39
DDR_SDQ34 DDR_DQ34
DDR_SDQ32 DDR_DQ32
2 2
DDR_SDQ27 DDR_DQ27
DDR_SDQ18 DDR_DQ18
DDR_SDQ23 DDR_DQ23
DDR_SDQ21 DDR_DQ21
DDR_SDQ20 DDR_DQ20
DDR_SDQ10
DDR_SDQ11
3 3
DDR_SDQS1 DDR_DQS1 DDR_SDM1 DDR_DM1
DDR_SDQ9 DDR_DQ9
DDR_SDQ8 DDR_DQ8
DDR_SDQ3 DDR_DQ3
DDR_SDQ1 DDR_DQ1
DDR_SDQS0 DDR_DQS0 DDR_SDM0 DDR_DM0
DDR_SDQ5 DDR_DQ5
DDR_SDQ7
4 4
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
A
RP40
0_1206_8P4R_5%
RP43
0_1206_8P4R_5%
RP44
0_1206_8P4R_5%
RP54
0_1206_8P4R_5%
RP59
0_1206_8P4R_5%
RP64
0_1206_8P4R_5%
RP67
0_1206_8P4R_5%
RP70
0_1206_8P4R_5%
RP74
0_1206_8P4R_5%
RP82
DDR_DQ57DDR_SDQ57
DDR_DQ61DDR_SDQ61
DDR_DQS6DDR_SDQS6 DDR_SDM6 DDR_DM6
DDR_DQ43
DDR_DQ47 DDR_SDQ46
DDR_DQ44
DDR_DQ41
DDR_DQ37
DDR_DQS4DDR_SDQS4 DDR_SDM4 DDR_DM4
DDR_DQ31DDR_SDQ31
DDR_DQS3DDR_SDQS3 DDR_SDM3 DDR_DM3
DDR_DQ26DDR_SDQ26
DDR_DQ28DDR_SDQ28
DDR_DQS2DDR_SDQS2 DDR_SDM2 DDR_DM2
DDR_DQ10
DDR_DQ11
DDR_DQ7
B
DDR_SDQ58 DDR_DQ58
DDR_SDQ59 DDR_DQ59
DDR_SDQ60 DDR_DQ60
DDR_SDQ51 DDR_DQ51
DDR_SDQ50 DDR_DQ50
DDR_SDQ52 DDR_DQ52
DDR_SDQ42 DDR_DQ42
DDR_SDQ45
DDR_SDQ40
DDR_SDQ38 DDR_DQ38
DDR_SDQ35 DDR_DQ35
DDR_SDQ33 DDR_DQ33
DDR_SDQ36 DDR_DQ36
DDR_SDQ29 DDR_DQ29
DDR_SDQ25 DDR_DQ25
DDR_SDQ19 DDR_DQ19
DDR_SDQ22 DDR_DQ22
DDR_SDQ17 DDR_DQ17
DDR_SDQ16
DDR_SDQ14 DDR_DQ14
DDR_SDQ12 DDR_DQ12
DDR_SDQ4
DDR_SDQ0
DDR_SDQ6
DDR_SDQ[0..63]
DDR _ S DQS[0..7]
DDR_SDM[0..7]
DDR_SMA[0..12]
B
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
DDR_SDQ[0..63] 8
DDR_SDQS[0..7] 8
DDR_SDM[0..7] 8
DDR_SMA[0..12] 8
RP5
0_1206_8P4R_5%
RP8
0_1206_8P4R_5%
RP10
0_1206_8P4R_5%
RP12
0_1206_8P4R_5%
RP16
0_1206_8P4R_5%
RP26
0_1206_8P4R_5%
RP29
0_1206_8P4R_5%
RP31
0_1206_8P4R_5%
RP34
0_1206_8P4R_5%
RP36
0_1206_8P4R_5%
C
DDR_DQ56DDR_SDQ56
DDR_DQ46
DDR_DM5DDR_DQS5
DDR_DQ45
DDR_DQ40
DDR_DQ30DDR_SDQ30
DDR_DQ24DDR_SDQ24
DDR_DQ16
DDR_DQ15DDR_SDQ15
DDR_DQ13DDR_SDQ13
DDR_DQ2DDR_SDQ2
DDR_DQ4
DDR_DQ0
DDR_DQ6
C
D
DDR_DQ5
DDR_DQS0
DDR_DQ1
DDR_DQ3
DDR_DQ8
DDR_DQ9
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_CLK08
DDR_CLK0#8
DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ28
DDR_DQS3
DDR_DQ27 DDR_DQ29
DDR_CKE18,14
DDR_SCS#08,14
DDR_SMA158
Layout note
Place these resistors
close to DIMM0,
all trace length<500 mil
DDR_CKE1
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#0
DDR_SMA15
DDR_DQ32
DDR_DQ34
DDR_DQS4 DDR_DM4
DDR_DQ39
DDR_DQ37
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQ54
DDR_DQ55
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57 DDR_DQ58
SMDATA14,16,27
SMCLK14,16,27
+3VS
+2.5V
JP17
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5746-2-111
E
DU/RESET#
DU/BA2
VREF
VDD
DM0
DQ12
VDD
DQ13
DM1
DQ14
DQ15
VDD
VDD
DQ20
DQ21
VDD
DM2
DQ22
DQ23
DQ28
VDD
DQ29
DM3
DQ30
DQ31
VDD
DM8
VDD
VDD
VDD
CKE0
VDD
RAS#
CAS#
DQ36
DQ37
VDD
DM4
DQ38
DQ39
DQ44
VDD
DQ45
DM5
DQ46
DQ47
VDD
CK1#
DQ52
DQ53
VDD
DM6
DQ54
DQ55
DQ60
VDD
DQ61
DM7
DQ62
DQ63
VDD
VSS
DQ4
DQ5
DQ6
VSS
DQ7
VSS
VSS
VSS
VSS
VSS
CB4
CB5
VSS
CB6
CB7
VSS
VSS
VSS
BA1
VSS
VSS
VSS
CK1
VSS
VSS
VSS
SA0
SA1
SA2
F
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDR_DQ6DDR_DQ7
DDR_DQ0
DDR_DM0
DDR_DQ4
DDR_DQ2
DDR_DQ12
DDR_DQ13
DDR_DM1
DDR_DQ15
DDR_DQ14
DDR_DQ16
DDR_DQ17
DDR_DM2
DDR_DQ22DDR_DQ23
DDR_DQ19
DDR_DQ24
DDR_DQ25DDR_DQ26
DDR_DM3
DDR_DQ30DDR_DQ31
DDR_CKE0
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#1
DDR_DQ33
DDR_DQ36
DDR_DQ35
DDR_DQ38
DDR_DQ40DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ52
DDR_DM6DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ60DDR_DQ61
DDR_DQ56
DDR_DM7
DDR_DQ59
1
C679
2
0.1U_0402_10V6K
DDR_CKE0 8,14
DDR_SCS#1 8,14
DDR_CLK1# 8
DDR_CLK1 8
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
F
G
DDR_DQ[0..63]
+SDREF
DDR_SMA15 DDR_SMAA15
DDR_SWE#8
DDR_SBS08
DDR_SCAS#8
DDR_SRAS#8
DDR_SBS18
DDR_SWE#
DDR_SBS0
DDR_SMA10
DDR_SMA1
DDR_SMA3
DDR_SMA5
DDR_SMA7
DDR_SMA9
DDR_SMA12
DDR_SCAS#
DDR_SRAS#
DDR_SBS1
DDR_SMA0
DDR_SMA2
DDR_SMA4
DDR_SMA6
DDR_SMA8
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMAA[0..12]
DDR_SMAA15
10_1206_8P4R_5%
RP19
10_1206_8P4R_5%
RP27
R234 10_0402_5%
R239 10_0402_5%
10_1206_8P4R_5%
RP18
10_1206_8P4R_5%
DDR_SMA11
RP28
R238 10_0402_5%
45
36
27
18
45
36
27
18
12
12
DDR_SMAA10
DDR_SMAA1
DDR_SMAA3
DDR_SMAA5
DDR_SMAA7
DDR_SMAA12
45
36
27
18
45
36
27
18
12
DDR_SMAA9
DDR_SMAA0
DDR_SMAA2
DDR_SMAA4
DDR_SMAA6
DDR_SMAA8
DDR_SMAA11
DDR_DQ[0..63] 14
DDR_DQS[0..7] 14
DDR_DM[0..7] 14
DDR_SMAA[0..12] 14
DDR_SMAA15 14
DDR_WE# 14
DDR_BS0 14
H
DDR_CAS# 14
DDR_RAS# 14
DDR_BS1 14
Layout note
Place these resistor
close by DIMM0,
all trace length
Max=1.4"
Title
Size Docu ment Number Re v
Date: Sheet
G
Compa l Electronics, Inc.
DDR-SODIMM SLOT0
LA-2051
星期三 八月
27, 2003
0.1A
of
13 51,
H
A
+1.25VS
DDR_DQ7
DDR_DQ5
DDR_DQS0
DDR_DQ1
1 1
2 2
3 3
4 4
DDR_DQ3
DDR_DQ8
DDR_DQ9
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ28
DDR_DQ26
DDR_DQS3
DDR_DQ27
DDR_DQ31
DDR_DQ32
DDR_DQ34
DDR_DQS4
DDR_DQ39
DDR_DQ37
DDR_DQ41
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ61
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57
RP37
56_0804_8P4R_5%
RP35
56_0804_8P4R_5%
RP33
56_0804_8P4R_5%
RP32
56_0804_8P4R_5%
RP30
56_0804_8P4R_5%
RP15
56_0804_8P4R_5%
RP13
56_0804_8P4R_5%
RP11
56_0804_8P4R_5%
RP7
56_0804_8P4R_5%
RP6
56_0804_8P4R_5%
A
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
RP91
56_0804_8P4R_5%
RP84
56_0804_8P4R_5%
RP73
56_0804_8P4R_5%
RP71
56_0804_8P4R_5%
RP68
56_0804_8P4R_5%
RP58
56_0804_8P4R_5%
RP55
56_0804_8P4R_5%
RP52
56_0804_8P4R_5%
RP42
56_0804_8P4R_5%
RP41
56_0804_8P4R_5%
DDR_DQ6
18
DDR_DQ0
27
DDR_DM0
36
DDR_DQ4
45
DDR_DQ2
18
DDR_DQ12
27
DDR_DQ13
36
DDR_DM1
45
DDR_DQ15
18
DDR_DQ14
27
DDR_DQ16
36
DDR_DQ17
45
DDR_DM2
18
DDR_DQ22
27
DDR_DQ19
36
DDR_DQ24
45
DDR_DQ25
18
DDR_DM3
27
DDR_DQ29
36
DDR_DQ30
45
DDR_DQ33
18
DDR_DQ36
27
DDR_DM4
36
DDR_DQ35
45
DDR_DQ38
18
DDR_DQ40
27
DDR_DQ45
36
DDR_DM5
45
DDR_DQ42
18
DDR_DQ46
27
DDR_DQ53
36
DDR_DQ52
45
DDR_DM6
18
DDR_DQ50
27
DDR_DQ51
36
DDR_DQ60
45
DDR_DQ56
18
DDR_DM7
27
DDR_DQ59
36
DDR_DQ58
45
B
DDR_CLK38
DDR_CLK3#8
DDR_BS013
DDR_WE#13
DDR_SMAA1513
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
SMDATA13,16,27
SMCLK13,16,27
+2.5V
DDR_DQ7
DDR_DQ5
DDR_DQS0
DDR_DQ1
DDR_DQ3
DDR_DQ8
DDR_DQ9
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ28
DDR_DQ26
DDR_DQS3
DDR_DQ27
DDR_DQ31
DDR_CKE3 DDR_CKE2
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_BS0 DDR_RAS#
DDR_SCS#2 DDR_SCS#3
DDR_SMAA15
DDR_DQ32
DDR_DQ34
DDR_DQS4
DDR_DQ39
DDR_DQ37
DDR_DQ41
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ61
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57 DDR_DQ58
+3VS
C
JP20
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
S1#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DDR-SODIMM_200_STD_H4.0
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDR_DQ6
DDR_DQ0
DDR_DM0
DDR_DQ4
DDR_DQ2
DDR_DQ12
DDR_DQ13
DDR_DM1
DDR_DQ15
DDR_DQ14
DDR_DQ16
DDR_DQ17
DDR_DM2
DDR_DQ22DDR_DQ23
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DM3
DDR_DQ29
DDR_DQ30
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4
DDR_SMAA2
DDR_SMAA0
DDR_BS1
DDR_CAS#DDR_WE#
DDR_DQ33
DDR_DQ36
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ40
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ52
DDR_DM6
DDR_DQ50
DDR_DQ51
DDR_DQ60
DDR_DQ56
DDR_DM7
DDR_DQ59
+3VS
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
1
C672
0.1U_0402_10V6K
2
DDR_CKE2 8DDR_CKE38
DDR_BS1 13
DDR_RAS# 13
DDR_CAS# 13
DDR_SCS#3 8DDR_SCS#28
DDR_CKE08,13
DDR_CKE18,13
DDR_SCS#18,13
DDR_SCS#08,13
DDR_CLK4# 8
DDR_CLK4 8
D
+SDREF
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
+1.25VS
33_0804_8P4R_5%
33_0804_8P4R_5%
33_0804_8P4R_5%
DDR_DQS[0..7] 13
DDR_DQ[0..63] 13
DDR_DM[0..7] 13
DDR_SMAA[0..12] 13
DDR_CKE3 DDR_CKE2
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_BS0
DDR_WE#
DDR_SCS#2
DDR_SMAA15
DDR_CKE0
DDR_CKE1
DDR_SCS#1
DDR_SCS#0
RP24
33_0804_8P4R_5%
RP23
33_0804_8P4R_5%
RP20
33_0804_8P4R_5%
RP25
33_0804_8P4R_5%
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
DDR_SMAA[0..12]
Layout note
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
Title
Size Docu ment Number Re v
Date: Sheet
Compa l Electronics, Inc.
DDR-SODIMM SLOT1
LA-2051
星期三 八月
27, 2003
E
RP62
18
DDR_SMAA11
27
DDR_SMAA8
36
DDR_SMAA6
45
RP61
RP60
E
18
27
36
45
18
27
36
45
DDR_SMAA4
DDR_SMAA2
DDR_SMAA0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_SCS#3
14 51,
0.1A
of
A
Layout n ote :
Distribute as close as possible
to DDR-SODIMM0.
+2.5V
B
C
D
E
Layout n ote :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V
1 1
1
+
C686
150U_D2_6.3VM
2
1
C227
0.1U_0402_10V6K
2
1
C322
+
150U_D2_6.3VM
2
1
C289
0.1U_0402_10V6K
2
1
C184
0.1U_0402_10V6K
2
1
+
C93
150U_D2_6.3VM
2
1
C146
0.1U_0402_10V6K
2
1
C136
0.1U_0402_10V6K
2
1
C291
0.1U_0402_10V6K
2
1
C248
0.1U_0402_10V6K
2
1
C122
0.1U_0402_10V6K
2
1
C174
0.1U_0402_10V6K
2
1
C246
0.1U_0402_10V6K
2
1
C266
0.1U_0402_10V6K
2
1
C170
0.1U_0402_10V6K
2
1
C106
0.1U_0402_10V6K
2
1
C191
0.1U_0402_10V6K
2
1
C258
0.1U_0402_10V6K
2
1
C150
0.1U_0402_10V6K
2
1
C265
0.1U_0402_10V6K
2
1
+
C92
150U_D2_6.3VM
2
1
C113
0.1U_0402_10V6K
2
1
C139
0.1U_0402_10V6K
2
1
C277
0.1U_0402_10V6K
2
1
C151
0.1U_0402_10V6K
2
1
C247
0.1U_0402_10V6K
2
1
C274
0.1U_0402_10V6K
2
1
C137
0.1U_0402_10V6K
2
1
C111
0.1U_0402_10V6K
2
1
C226
0.1U_0402_10V6K
2
1
C165
0.1U_0402_10V6K
2
1
C185
0.1U_0402_10V6K
2
1
C245
0.1U_0402_10V6K
2
1
C261
0.1U_0402_10V6K
2
1
C171
0.1U_0402_10V6K
2
1
C290
0.1U_0402_10V6K
2
1
C292
0.1U_0402_10V6K
2
1
C176
0.1U_0402_10V6K
2
Layout n ote :
Place one cap close to every 2 pull up resistors termination to
2 2
+1.25VS
1
C283
0.1U_0402_10V6K
2
+1.25VS
1
C425
0.1U_0402_10V6K
2
+1.25VS
1
C197
0.1U_0402_10V6K
3 3
2
+1.25VS
1
C426
0.1U_0402_10V6K
2
1
C671
0.1U_0402_10V6K
2
1
C662
0.1U_0402_10V6K
2
1
C228
0.1U_0402_10V6K
2
1
C606
0.1U_0402_10V6K
2
1
C276
0.1U_0402_10V6K
2
1
C255
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
1
C149
0.1U_0402_10V6K
2
1
C263
0.1U_0402_10V6K
2
1
C287
0.1U_0402_10V6K
2
1
C209
0.1U_0402_10V6K
2
1
C132
0.1U_0402_10V6K
2
1
C474
0.1U_0402_10V6K
2
1
C424
0.1U_0402_10V6K
2
1
C156
0.1U_0402_10V6K
2
1
C483
0.1U_0402_10V6K
2
1
C625
0.1U_0402_10V6K
2
1
C635
0.1U_0402_10V6K
2
1
C281
0.1U_0402_10V6K
2
1
C449
0.1U_0402_10V6K
2
1
C434
0.1U_0402_10V6K
2
1
C510
0.1U_0402_10V6K
2
+1.25VS
1
C208
0.1U_0402_10V6K
2
+1.25VS
1
C294
0.1U_0402_10V6K
2
+1.25VS
4 4
1
C428
0.1U_0402_10V6K
2
1
C169
0.1U_0402_10V6K
2
1
C244
0.1U_0402_10V6K
2
1
C225
0.1U_0402_10V6K
2
A
1
C177
0.1U_0402_10V6K
2
1
C183
0.1U_0402_10V6K
2
1
C535
0.1U_0402_10V6K
2
1
C220
0.1U_0402_10V6K
2
1
C187
0.1U_0402_10V6K
2
1
C194
0.1U_0402_10V6K
2
1
C249
0.1U_0402_10V6K
2
1
C126
0.1U_0402_10V6K
2
1
C497
0.1U_0402_10V6K
2
1
C440
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
C528
0.1U_0402_10V6K
2
B
1
C616
0.1U_0402_10V6K
2
1
C120
0.1U_0402_10V6K
2
1
C219
0.1U_0402_10V6K
2
1
C270
0.1U_0402_10V6K
2
1
C664
0.1U_0402_10V6K
2
1
C115
0.1U_0402_10V6K
2
1
C642
0.1U_0402_10V6K
2
1
C439
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Docu ment Number Re v
Date: Sheet
Compa l Electronics, Inc.
DDR SODIMM Decoupling
LA-2051
星期三 八月
27, 2003
of
15 51,
E
0.1A
A
1 1
B
C
+3VS
HB-1M2012-121JT03_0805
L7
1 2
D
+3V_CLK
Width=40 mils
C145
10U_0805_10V4Z
0.1U_0402_10V6K
1
C141
2
+3VS_VDDA
1
C118
2
0.1U_0402_10V6K
E
0.1U_0402_10V6K
1
C95
2
1
2
0.1U_0402_10V6K
C105
1
2
F
CLK_BCLK
CLK_BCLK#
1
C89
2
0.1U_0402_10V6K
R158 @0_0402_5%
1 2
R152 @0_0402_5%
1 2
G
CLK_CPU_ITP 5
CLK_CPU_ITP# 5
H
R146 @10_0402_5%
EXCLK_CLKGEN38
+3VS
12
R577
@10K_0402_5%
R579 0_0402_5%
PM_STPCPU#5,10,26,47
2 2
3 3
PCI_STP#26
1 2
1 2
R580 0_0402_5%
CLK_SB_48M27
CLK_AUDIO_14M32
REFCLK1_NB10
CLK_SIO_14M34
CLK_SB_14M27
CLK_14M_APIC26
12
R578
@10K_0402_5%
R109 33_0402_5%
R159 @33_0402_5%
R161 56_0402_5%
R165 33_0402_5%
R174 33_0402_5%
R173 @33_0402_5%
1 2
C116 10P_0402_50V8K
C112
SMCLK13,14,27
SMDATA13,14,27
VTT_PWRGD17,27
1 2
1 2
1 2
1 2
1 2
1 2
XTALIN_CLK
1 2
12
Y2
XTALOUT_CLK
1 2
14.31818MHZ_20P_6X1430004201
10P_0402_50V8K
12
VTT_PWRGD
PCI33/66#
CLK_48M
FS2
FS1
FS0
CLK_IREF
R144
475_0402_1%
1 2
R150
@1M_0402_5%
35
34
10
45
12
26
11
27
28
38
U16
6
7
4
3
2
XIN
XOUT
SCLK
SDATA
VTTPWRGD/PD#
CPU_STP#
PCI_STOP#
24/48#SEL
PCI33/66#SEL
48MHz_1
48MHz_0
FS2/REF2
FS1/REF1
FS0/REF0
IREF
42
VDDCPU
8
48
30
VDDSD
GNDREF5GNDXTAL
18
29
VDD48M
VDDAGP
GNDPCI
GNDPCI
24
13
19
VDDPCI
GND48M
25
33
1
VDDPCI
GNDAGP
46
9
VDDA
VDDREF
VDDXTAL
VSSA
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDSD
GNDCPU
ICS951402AGT_TSSOP48
41
36
1
C104
0.1U_0402_10V6K
2
VSSA
37
CLK_BCLK
40
CLK_BCLK#
39
CLK_NB
44
CLK_NB#
43
MEM_66M
47
AGP_66M
32
31
FS3
14
FS4
15
16
17
20
21
22
23
+3VS_VDDA
1
C90
0.1U_0402_10V6K
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
C99
10U_0805_10V4Z
R148 33_0402_5%
R142 33_0402_5%
R164 33_0402_5%
R156 33_0402_5%
R168 33_0402_5%
R125 33_0402_5%
R115 33_0402_5%
0.1U_0402_10V6K
C138
R147 49.9_0402_1%
R139 49.9_0402_1%
R163 49.9_0402_1%
R155 49.9_0402_1%
1
2
1 2
1 2
1 2
1 2
1 2
CHB2012U121_0805
1
C110
0.1U_0402_10V6K
2
L4
+3VS
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_NB_BCLK 10
CLK_NB_BCLK# 10
CLK_MEM_66M 10
CLK_AGP_66M 10
CLK_ALINK_SB 26
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
0 0 0 1 0
0 0 0 0 1
**
0 0 0 0 0
Note: 0 = PULL LOW
4 4
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
*
133
133
100 100
BSEL15,12
BSEL05,12
Spreaf OFF O R
Center spread +/-0.3%
+3VS +3VS
R172
10K_0402_5%
12
12
R167
10K_0402_5%
D20 RB751V_SOD323
D21 RB751V_SOD323
21
21
+3V_CLK
R169
10K_0402_5%
12
12
R171
10K_0402_5%
FS1
FS0
FS2
FS3
FS4
PCI33/66#
12
R166
4.7K_0402_5%
12
R170
4.7K_0402_5%
12
R160
@10K_0402_5%
12
R153
10K_0402_5%
12
R124
@10K_0402_5%
12
R121
10K_0402_5%
12
R120
@10K_0402_5%
12
R123
10K_0402_5%
+3V_CLK
12
12
R127
10K_0402_5%
R133
@10K_0402_5%
A-LINK FREQ
PCI33/66# = HIGH
**
PCI33/66# = LOW 33MHZ
A
66MHZ
B
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
C
D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
Clock Generator
27, 2003
LA-2051
G
星期三 八月
0.1A
of
16 51,
H
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