COMPAL LA-1911-REV Schematics

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1 1

B

C

D

E

SAPPORO 150 (DAL00)

2 2

LA-1911 REV1.0 Schematic

3 3

4 4

A

Desktop Prescott/Northwood uFCPGA-478 CPU

Springdale(865PE)+ICH5+nVIDIA NV34M(64MB VRAM)

2003-08-06

Compal Electronics, Inc.

Title

Cover Page

Size Document Number Rev

B

B

C

D

Date: Sheet of

0.2

1 57Friday, August 08, 2003

E

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[e-mail]

B

C

D

E

DAL00 LA-1911 BLOCK DIAGRAM

4 4

Desktop Northwood
Desktop Prescott

(uFCBGA/uFCPGA-478)

PAGE 4,5,6

Thermal Sensor

ADM1032

PAGE 5,16

Clock Generator

ICS952623

PAGE15

CPU VID

PAGE 5

FANController
RTC Battery

PAGE 40

FSB

CRT&LVDS

Connector

TV-OU T

3 3

4 Pin-Connector

PAGE 22

NVIDIA-NV34M

PAGE 22

AGP

PAGE 16,17,18,19

AGP 8X

AGP Bus

Intel Springdale

MCH 865PE

FCBGA-932

VRAM

2 Channel and 4 sets

PAGE 20,21

800MHz

PAGE 7,8,9,10,11

HUB

Interface

266/333/400MHz
(2.55V)

Memory Bus

SO-DIMM x 2(DDR)

BANK 0,1,2,3

Bluetooth

PAGE 36

PAGE 12,13,14

DC/DC Interface

PAGE 43

BATTERY

Charger

PAGE 47

Power Interface &
TEMP. sensing circuit

266MHz

Mini PCI

PAGE 29

RJ-45

PAGE 26

LAN

RTL8101L

PAGE 26

PCI BUS

33MHz (3.3V)

IEEE1394(BTO )

2 2

TSB43AB21A

PAGE 30

(1.8V)

ICH5

mBGA-460

480MHz

PAGE 23,24,25

Primary

Secondary

USB 2.0 Port *3

IDE HDD

CD-ROM/DVD

PAGE 35

PAGE 33

PAGE 33

LID/Kill Switch
Power Buttom

PAGE 46-54

PAGE 39

1 1

Slot 0

PAGE 28

SD Conn

PAGE 28

A

CARDBAY

T7L65XB

PAGE 27,28

FIR(BTO)

PAGE 35

Super I/O

LPC47N227

REV B

PAGE 34

Parallel

PAGE 36

B

LPC BUS 33MHz (3.3V)

Scan KB

Embedded
Controller

NS PC 87591L

PAGE 37

PAGE 37

BIOS(1M)

& I/O PORT

PAGE 38

C

A C-LINK

AC97 CODEC

ALC 202

MDC

Connector

CIR

Controller

PAGE 31

PAGE 36

PAGE 41

Audio Amplifier

TPA6011A4

RJ-11

PAGE 26

CIR

D

PAGE 32

DIRECT BOARD

PAGE 38

VR/CIR BOARD

PAGE 38

SW BOARD

PAGE 38

Compal Electronics, Inc.

Title

Block Digram

Size Document Number Rev
Custom

Date: Sheet of

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2 57Friday, August 08, 2003

0.2

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Voltage Rails

STATE

Power Plane Description

1 1

2 2

VIN
B+
+CPU_CORE
+CPU_VID
+VTT_GMCH +1.225V (Prescott) / +1.45V (Northwood)
+VGA_CORE ON OFF OFF1.2V/1.5V switched power rail for VGA chip
+1.25VS 1.25V switched power rail
+1.5VS
+2.5V
+2.5VS 2.5V switched power rail
+3VALW
+3V
+3VS
+5VALW ON
+5V
+5VS
+12VALW
+RT CVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus

AGP 4X/8X

2.5V power rail

3.3V always on power rail

3.3V power rail

3.3V switched power rail
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail
RTC power

S1 S3 S5

N/A N/A N/A

N/AN/AN/A
ON OFF
ON OFF
ON OFF OFF

ON OFF OFF
ON OFF OFF

ON
ON
ON
ON

ON
ON
ON
ON

OFF

OFF

OFFON

ON

OFF

OFF
ON ON*

OFF

ON
OFF

OFF

ON

ON*

OFF

ON
OFF

OFF

ON

ON*

ON

ON

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

100K +/- 5%Ra

Rb V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

LOW

AD_BID

0 V

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

AD_BID

V typ

ON

ON

ON

ON

ON

0 V 0 V

ON

ON

ON

OFF

OFF

AD_BID

V

ON ON

ON

OFF

OFF

OFF

max

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

LOW

OFF

OFF

OFF

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

VGA

CardBus

LAN

Mini-PCI

1394

3 3

SD

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

AD16
AD20

AD17

AD18
AD16 0
AD22

2

3 PIRQF

1/4

PIRQA
PIRQA/PIRQB/PIRQC/PIRQD

PIRQG/PIRQH
PIRQE
PIRQA/PIRQB/PIRQC/PIRQD

EC SM Bus2 address

Address Address

1010 000X b
1011 000Xb

Device

ADM1032

1001 110X b0001 011X b

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

ICH5 SM Bus address

Device

4 4

Clock Generator
( ICS 952623)

DDR DIMM0

DDR DIMM2

A

Address

1101 001Xb

1010 000Xb
1010 010Xb

Compal Electronics, Inc.

Title

Size Document Number Rev

B

B

C

D

Date: Sheet of

LA-1911

Notes

3 57Friday, August 08, 2003

E

0.2

5

[e-mail]

4

+CPU_CORE

3

2

1

D D

H_A#[3..31]7

C C

H_REQ#[0..4]7

H_ADS#7

R25 62_0402_5%

+CPU_CORE
+CPU_CORE

B B

1 2
1 2

R35 200_0402_5%

H_BR0#7
H_BPRI#7
H_BNR#7
H_LOCK#7

CLK_BCLK15

CLK_BCLK#15

H_HIT#7
H_HITM#7

H_DEFER#7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#

CLK_BCLK
CLK_BCLK#

AMP_3-1565030-1_Prescott

AC1

AC3

AF22
AF23

A10

A12

A14

A16

A18

A20A8AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19B7B9

C10

C12

C14

C16

C18

C20C8D11

D13

D15

D17

D19D7D9

VCC_66

VCC_85

F9

VCC_67

VCC_68

VCC_79

VCC_80

E20E8F11

VCC_69

VCC_70

VCC_77

VCC_78

E16

E18

E10

VCC_71

VCC_72

VCC_75

VCC_76

E12

E14

VCC_73

VCC_74

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] 7

JCPU1A

VCC_0

VCC_1

VCC_2

VCC_3

VCC_4

VCC_5

VCC_6

VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_61

VCC_62

VCC_63

VCC_64

VCC_81

BOOTSELECT

AD1

F13

F15

VCC_82

VCC_83

F17

F19

VCC_65

VCC_84

K2

A#3

K4

A#4

L6

A#5

K1

A#6

L3

A#7

M6

A#8

L2

A#9

M3

A#10

M4

A#11

N1

A#12

M1

A#13

N2

A#14

N4

A#15

N5

A#16

T1

A#17

R2

A#18

P3

A#19

P4

A#20

R3

A#21

T2

A#22

U1

A#23

P6

A#24

U3

A#25

T4

A#26

V2

A#27

R6

A#28

W1

A#29

T5

A#30

U4

A#31

V3

A#32

W2

A#33

Y1

A#34

AB1

A#35

J1

REQ#0

K5

REQ#1

J4

REQ#2

J3

REQ#3

H3

REQ#4

G1

ADS#

AP#0

V5

AP#1

AA3

BINIT#
IERR#

H6

BR0#

D2

BPRI#

G2

BNR#

G4

LOCK#

BCLK0
BCLK1

F3

HIT#

E3

HITM#

E2

DEFER#

VSS_0

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

H1H4H23

H26

A11

A13

A15

A17

A19

A21

A24

A26A3A9

AA1

AA11

AA13

AA15

AA17

AA19

AA23

AA26

AA4

AA7

Prescott

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

AA9

AB10

AB12

AB14

AB16

AB18

AB20

AB21

VSS_31

VSS_32

AB24

AB3

VSS_33

VSS_34

AB6

AB8

VSS_35

VSS_36

AC11

AC13

VSS_37

VSS_38

AC15

AC17

VSS_39

VSS_40

AC19

AC2

VSS_41

VSS_42

AC22

AC25

VSS_43

VSS_44

AC5

AC7

VSS_45

VSS_46

AC9

AD10

VSS_47

VSS_48

AD12

AD14

VSS_49

VSS_50

AD16

AD18

VSS_51

VSS_52

AD21

AD23

VSS_53

VSS_54

AD4

AD8

VSS_55

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

B6 FERR# FERR#/PBE# Pull-up 62ohm

AA20 ITPCLKOUT0 Pull-up56ohm

AB22 ITPCLKOUT1 Pull-up 56ohm

AD2 NC VIDPWRGD Pull-up 8.2Kohm

AD3 NC float VID5 Pull-up1Kohm to

A A

AF3 NC float VCCVIDLB Connect to +VCCVID
AD20 VCCA VCCIOPLLConnect to CPU

AF23 Connect to CPU

VCCIOPLL VCCA

AD1 VSS BOOTSELECTConnect to GND CPU determine
AE26 VSS Connect to GND OPTIMIZED/

Commend Commend

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

to +VCC_CORE
float

Filter

Filter

5

Prescott
Pin name

to +VCC_CORE

TESTHI6 Pull-up 62ohm

TESTHI7 Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCCVID

+3VRUN & connect
to PWRIC

Connect to CPU
Filter
Connect to CPU
Filter

COMPAT#

float

Northwood Prescott

Pop Pop

Pop Pop

Pop Pop

PopDepop

Depop

Depop

Pop

Pop

Pop Depop

Pop Depop

4

+CPU_CORE

H_BOOTSELECT52

3

1 2

R12
0_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BOOTSEL

R_C

1 2

R15
0_0402_5%

Pop: Northwood
Depop: Prescott

Compal Electronics, Inc.

Title

Prescott Processor in uFCPGA478 (1/2)

Size Document Number Rev

C

LA-1911

2

Date: Sheet of

1

4 57Friday, August 08, 2003

0.2

5

[e-mail]

4

3

2

1

Asynch GTL+ PULL HIGH

+CPU_CORE

H_FERR#

1 2

R518 62_0402_5%

H_PROCHOT#

1 2

R27 130_0402_5%

H_PWRGOOD

D D

1 2

R74 300_0402_5%

H_RESET#

1 2

R75 62_0402_5%

JTAG PULL DOWN

RP4

1 8
2 7
3 6
4 5

1K_8P4R_1206_5%

C C

B B

ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI

Close to the CPU

Note: Please change to 10uH, DC current
of 100mA parts and close to cap

+CPU_CORE

Place near ICH

Place near CPU

+CPU_CORE

L5 LQG21F4R7N00_0805

1 2

**

L6 LQG21F4R7N00_0805

1 2

**

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)

H_RS#[0..2]7

H_TRDY#7

H_A20M#23

H_FERR#23
H_IGNNE#23
H_SMI#23
H_PWRGOOD23
H_STPCLK#23

H_INTR23
H_NMI23
H_INIT#23
H_RESET#7

H_DBSY#7

H_DRDY#7
CPU_CLKSEL015
CPU_CLKSEL115

H_THERMTRIP#24

R37 62_0402_5%1 2
R33 62_0402_5%1 2

1 2

R30 62_0402_5%
R36 62_0402_5%1 2
R32 62_0402_5%1 2
R29 62_0402_5%1 2

VCCSENSE52
VSSSENSE52

C80

+

Trace >= 25mils

1 2

33U_D2_8M_R35

Pop: Prescott
Depop: Northwood

+CPUVID

H_VCCA

H_VSSA

1 2

R26

CLK_ITP15
CLK_ITP#15

R65

61.9_0603_1%

H_RS#0
H_RS#1
H_RS#2

H_FERR#

H_PWRGOOD

H_RESET#

H_THERMDA
H_THERMDC

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TCK
ITP_TDI

ITP_TMS
ITP_TRST#

VCCVIDLB

@0_0402_5%

CLK_ITP
CLK_ITP#

COMP0
COMP1

12

12

R14

61.9_0603_1%

AMP_3-1565030-1_Prescott

AB23

AB25

AD6
AD5

AC6
AC4

AD20

AE23

AD22

AC26
AD26

F1

G5

F4

AB2

J6

C6

B6
B2
B5

Y4

D1

E5

W5

H5
H2

B3

C4

A2

AB5

Y6
AA5
AB4

D4
C1
D5

F7

E6

A5

A4
AF3

L24

P1

JCPU1B

RS#0
RS#1
RS#2
RSP#
TRDY#

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCIOPLL
VCCA

VCCSENSE
VSSSENSE
VCCVIDLB

VSSA

ITP_CLK0
ITP_CLK1

COMP0
COMP1

AE11

AE13

VSS_57

VSS_129

F8

G21

AE15

AE17

AE19

AE22

VSS_58

VSS_59

VSS_60

VSS_61

VSS_130

VSS_131

VSS_132

VSS_133

G24G3G6J2J22

AE24

AE7

VSS_62

VSS_63

VSS_65

VSS_134

VSS_135

VSS_136

J25J5K21

AE9

AF1

AF10

VSS_66

VSS_67

VSS_137

VSS_138

K24K3K6L1L23

AF12

AF14

VSS_68

VSS_69

VSS_70

VSS_139

VSS_140

VSS_141

AF16

AF18

VSS_71

VSS_142

AF20

AF6

VSS_72

VSS_73

VSS_75

VSS_143

VSS_144

VSS_145

L26L4M2

AF8

B10

VSS_76

VSS_146

M22

B12

B14

VSS_77

VSS_78

VSS_79

VSS_147

VSS_148

VSS_149

M25M5N21

B16

B18

B20

VSS_80

VSS_81

VSS_82

VSS_150

VSS_151

VSS_152

N24N3N6P2P22

B23

B26B4B8

C11

C13

C15

C17

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

Prescott

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

P25P5R1

R23

R26R4T21

C19C2C22

VSS_90

VSS_91

VSS_92

VSS_160

VSS_161

VSS_162

C25C5C7C9D10

VSS_93

VSS_94

VSS_95

VSS_96

VSS_163

VSS_164

VSS_165

VSS_166

T24T3T6U2U22

D12

VSS_97

VSS_98

VSS_99

VSS_167

VSS_168

VSS_169

U25U5V1

D14

D16

VSS_100

VSS_170

V23

D18

D20

VSS_101

VSS_102

VSS_103

VSS_171

VSS_172

VSS_173

V26V4W21

H_VID052
H_VID152
H_VID252
H_VID352
H_VID452
H_VID552

D21

D24D3D6D8E1

VSS_104

VSS_105

VSS_106

VSS_174

VSS_175

VSS_176

W24W3W6Y2Y22

VSS_107

VSS_108

VSS_109

VSS_177

VSS_178

VSS_179

E11

E13

VSS_110

VSS_180

Y25

Y5

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

E15

E17

VSS_111

VSS_112

VSS_113

VSS_181

E19

E23

VSS_114

AE5

VSS_115

VID0

E26E4E7E9F10

VSS_116

VSS_117

VSS_118

VSS_119

VID1

VID2

VID3

VID4

AE4

AE3

AE2

AE1

F12

VSS_120

VID5

AD3

F14

F16

VSS_121

VSS_122

VSS_123

VIDPWRGD

AD2

F18F2F22

VSS_124

VSS_125

VSS_126

AF26

F25

F5

VSS_127

VSS_128

OPTIMIZED/COMPAT#

VCCVID

AF4

Trace >= 25mils

1

C39

0.1U_0402_10V6K

2

H_VID_PWRGD

SKTOCC#

PROCHOT#

1 2

DP#0
DP#1
DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

TESTHI9
TESTHI10
TESTHI11
TESTHI12

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

MCERR#

SLP#

NC1
NC2
NC3
NC4
NC5

+CPUVID

R84

0_0402_5%

J26
K25
K26
L25

AA21
AA6
F20
F6

AE26

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

E22
K22
R22
W22

F21
J23
P23
W23

L5
R5

E21
G25
P26
V21

AE25

C3
V6
AB26

A22
A7
AF25
AF24
AE21

@2.43K_0603_1%

H_PROCHOT#

R_E

R31

1 2

R83 0_0402_5%

1 2

H_TESTHI0
H_TESTHI1

H_TESTHI2_7

H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_TESTHI12

H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7

H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7

H_ADSTB#0 7
H_ADSTB#1 7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

1 2

R82
62_0402_5%

RE
Pop: Prescott
Depop: Northwood

+CPUVID

+CPU_GTLREF

R_G

R78 62_0402_5%1 2
R20 62_0402_5%1 2

R64 62_0402_5%1 2

R34 62_0402_5%1 2
R28 62_0402_5%1 2
R19 62_0402_5%1 2
R38 62_0402_5%1 2

1 2

R79 62_0402_5%

H_PROCHOT# 7,51
H_CPUSLP# 23

+CPU_CORE

Pop: Northwood
Depop: Prescott

+CPU_CORE

VID PULL HIGH VID PWRGD Circuit Thermal SensorGTL Reference Voltage

H_VID5

R18 1K_0402_5%

H_VID4

R17 1K_0402_5%

H_VID3
H_VID2

A A

H_VID1
H_VID0

1 2
1 2

RP3

45
36
27
18

1K_8P4R_1206_5%

Layout note :

1. +CPU_GTLREF Trace wide

+3VS

+CPU_GMCH_GTLREF

5

+CPU_CORE

R_A

R_B

12

R59
200_0603_1%

12

R60
169_0603_1%

4

2

C68

0.1U_0402_10V6K

1

12mils(min),Space 15mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+CPU_GTLREF

12

R63

0_0603_5%

1

C78
220P_0402_50V8K

2

0.1U_0402_16V4Z

H_VID_PWRGD

SN74LVC125APWLE_TSSOP14

3

1

C780

2

U4A

+3V POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

147

OE#

IO

+3V

12

R70
10K_0402_5%

1 2

R66 0_0402_5%

PG

23

VID_PWRGD 52

VCORE_ENLL 49,52

2

2200P_0402_50V7K

C47

EC_SMB_CK237
EC_SMB_DA237

+3VS

1

H_THERMDA

1

2

H_THERMDC

Title

Size Document Number Rev

C

Date: Sheet of

2
3
8
7

Compal Electronics, Inc.

Prescott Processor in uFCPGA478 (2/2)

LA-1911

C48

0.1U_0402_16V4Z

2

U3

VDD1

D+

ALERT#

D-

THERM#

SCLK

GND

SDATA

ADM1032ARM_RM8

1

1
6
4
5

5 57Friday, August 08, 2003

12

R41
@10K_0402_5%

0.2

5

4

3

2

1

+CPU_CORE

1

C468
22U_1206_6.3V6M

2

D D

+CPU_CORE

1

C514
22U_1206_6.3V6M

2

+CPU_CORE

1

C59
22U_1206_6.3V6M

2

C C

+CPU_CORE

1

C491
22U_1206_6.3V6M

2

1

C536
22U_1206_6.3V6M

2

1

C70
22U_1206_6.3V6M

2

1

C508
22U_1206_6.3V6M

2

1

C558
22U_1206_6.3V6M

2

Place 11 North of Socket(Stuff 8)

1

C523
22U_1206_6.3V6M

2

1

C545
22U_1206_6.3V6M

2

1

2

Place 12 Inside Socket(Stuff all)

1

C571
22U_1206_6.3V6M

2

1

C518
22U_1206_6.3V6M

2

1

2

Place 9 South of Socket(Unstuff all)

C560
22U_1206_6.3V6M

C535
22U_1206_6.3V6M

1

C16
22U_1206_6.3V6M

2

1

C557
22U_1206_6.3V6M

2

1

C408
22U_1206_6.3V6M

2

1

C570
22U_1206_6.3V6M

2

1

C421
22U_1206_6.3V6M

2

22uF depop reference
Springdale Customer Schematic R1.2 page82

1

C60
22U_1206_6.3V6M

2

1

C440
22U_1206_6.3V6M

2

1

C52
22U_1206_6.3V6M

2

1

C455
22U_1206_6.3V6M

2

**

1

C15
22U_1206_6.3V6M

2

1

C14
22U_1206_6.3V6M

2

1

C13
22U_1206_6.3V6M

2

1

C12
22U_1206_6.3V6M

2

1

C19
22U_1206_6.3V6M

2

1

C18
22U_1206_6.3V6M

2

1

C17
22U_1206_6.3V6M

2

B B

+CPU_CORE

1

+

2

+CPU_CORE

C119
470U_D4_2.5VM

1

+

C95
470U_D4_2.5VM

2

470uF _ERS10m ohm* 15, ESR=0.5m ohm

1

+

C85
470U_D4_2.5VM

2

1

+

C75
@470U_D4_2.5VM

2

1

+

C67
470U_D4_2.5VM

2

1

+

C61
470U_D4_2.5VM

2

**

1

+

C51
470U_D4_2.5VM

2

+CPU_CORE

A A

1

+

C63
470U_D4_2.5VM

2

1

+

C8
470U_D4_2.5VM

2

1

+

C33
470U_D4_2.5VM

2

5

1

+

C29
470U_D4_2.5VM

2

1

+

C28
@470U_D4_2.5VM

2

1

+

C44
470U_D4_2.5VM

2

1

+

C53
470U_D4_2.5VM

2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239

Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

CPU Decoupling

Size Document Number Rev

C

LA-1911

Date: Sheet of

1

6 57Friday, August 08, 2003

0.2

5

4

3

2

1

+VTT_GMCH

12

D D

C C

+CPU_GMCH_GTLREF

12

12

GTL Reference Voltage

B B

A A

Layout note :

1. +GMCH_GTLREF Trace wide
12mils(min),Space 15mils.

2. Place decoupling cap 220PF near GMCH.

Trace width 10mils,Space
7mils

R531
301_0603_1%

HD_SWING

12

R511
200_0603_1%

1

C301

0.01U_0402_16V7K

2

1 2

R522 0_0603_5%

R535
102_0603_1%

HDRCOMP

R525

24.9_0603_1%

+VTT_GMCH

+GMCH_GTLREF

1

C286
220P_0402_50V8K

2

H_RS#[0..2]5

+GMCH_GTLREF

H_A#[3..31]4

H_REQ#[0..4]4

H_ADSTB#05
H_ADSTB#15

CLK_HCLK15
CLK_HCLK#15

H_DSTBP#05
H_DSTBN#05
H_DINV#05
H_DSTBP#15
H_DSTBN#15
H_DINV#15
H_DSTBP#25
H_DSTBN#25
H_DINV#25
H_DSTBP#35
H_DSTBN#35
H_DINV#35

H_ADS#4

H_TRDY#5

H_DRDY#5

H_DEFER#4
H_HITM#4
H_HIT#4
H_LOCK#4
H_BR0#4
H_BNR#4

H_BPRI#4

H_DBSY#5

H_RESET#5 MCH_CLKSEL0 15

SYS_PWROK24,27,40

H_RS#0
H_RS#1
H_RS#2

HDRCOMP
HD_SWING

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

U43A

D26

HA3#

D30

HA4#

L23

HA5#

E29

HA6#

B32

HA7#

K23

HA8#

C30

HA9#

C31

HA10#

J25

HA11#

B31

HA12#

E30

HA13#

B33

HA14#

J24

HA15#

F25

HA16#

D34

HA17#

C32

HA18#

F28

HA19#

C34

HA20#

J27

HA21#

G27

HA22#

F29

HA23#

E28

HA24#

H27

HA25#

K24

HA26#

E32

HA27#

F31

HA28#

G30

HA29#

J26

HA30#

G26

HA31#

B29

HREQ0#

J23

HREQ1#

L22

HREQ2#

C29

HREQ3#

J21

HREQ4#

B30

HADSTB0#

D28

HADSTB1#

B7

HCLKP

C7

HCLKN

B19

HDSTBP0#

C19

HDSTBN0#

C17

DINV0#

L19

HDSTBP1#

K19

HDSTBN1#

L17

DINV1#

G9

HDSTBP2#

F9

HDSTBN2#

L14

DINV2#

D12

HDSTBP3#

E12

HDSTBN3#

C15

DINV3#

F27

ADS#

D24

HTRDY#

G24

DRDY#

L21

DEFER#

E23

HITM#

K21

HIT#

E25

HLOCK#

B24

BREQ0#

B28

BNR#

B26

BPRI#

E27

DBSY#

G22

RS0#

C27

RS1#

B27

RS2#

E8

CPURST#

AE14

PWROK#

E24

HDRCOMP

C25

HDSWING

F23

HDVREF

SPRINGDALE_UFCBGA932

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#

FSB

HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

PROCHOT#

BSEL0
BSEL1

B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8

H_PROCHOT#

L20

L13
L12

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] 4

H_PROCHOT# 5,51

MCH_CLKSEL1 15

U43F

AR32

VSS

AR29

VSS

AR27

VSS

AR25

VSS

AR23

VSS

AR20

VSS

AR16

VSS

AR13

VSS

AR11

VSS

AR9

VSS

AN32

VSS

AN30

VSS

AN28

VSS

AN26

VSS

AN24

VSS

AN22

VSS

AN20

VSS

AN18

VSS

AN16

VSS

AN14

VSS

AN12

VSS

AN10

VSS

AM35

VSS

AM29

VSS

AM27

VSS

AM25

VSS

AM23

VSS

AM21

VSS

AM19

VSS

AM17

VSS

AM15

VSS

AM13

VSS

AM11

VSS

AM9

VSS

AL32

VSS

AL1

VSS

AK28

VSS

AK26

VSS

AK24

VSS

AK22

VSS

AK20

VSS

AK18

VSS

AK16

VSS

AK14

VSS

AK12

VSS

AK10

VSS

AK8

VSS

AK3

VSS

AJ35

VSS

AJ32

VSS

AJ9

VSS

AJ4

VSS

AJ1

VSS

AH33

VSS

AH30

VSS

AH24

VSS

AH22

VSS

AH20

VSS

AH18

VSS

AH16

VSS

AH14

VSS

AH12

VSS

AH10

VSS

AH6

VSS

AH3

VSS

AG35

VSS

AG32

VSS

AG28

VSS

AG26

VSS

AG24

VSS

AG22

VSS

AG20

VSS

AG18

VSS

AG16

VSS

AG14

VSS

AG8

VSS

AG4

VSS

AF33

VSS

AF30

VSS

AF25

VSS

AF24

VSS

AF22

VSS

AF20

VSS

AF18

VSS

AF16

VSS

AF14

VSS

AF11

VSS

AF9

VSS

AF6

VSS

AF3

VSS

AE35

VSS

AE32

VSS

AE26

VSS

AE25

VSS

AE13

VSS

AE12

VSS

SPRINGDALE_UFCBGA932

AE11

VSS

AE10

VSS

AE4

VSS

AE1

VSS

AD33

VSS

AD30

VSS

AD28

VSS

AD10

VSS

AD9

VSS

AD8

VSS

AD6

VSS

AD3

VSS

AC35

VSS

AC32

VSS

AC4

VSS

AC1

VSS

AB33

VSS

AB30

VSS

AB28

VSS

AB27

VSS

AB26

VSS

AB10

VSS

AB9

VSS

AB8

VSS

AB6

VSS

AB3

VSS

AA32

VSS

AA4

VSS

AA1

VSS

Y35

VSS

Y33

VSS

Y30

VSS

Y28

VSS

Y27

VSS

Y26

VSS

Y10

VSS

Y9

VSS

Y8

VSS

Y6

VSS

Y3

VSS

W32

VSS

W18

VSS

W17

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

W4
V33
V30
V28
V27
V26
V19
V17
V10
V9
V8
V6
V3
U32
U19
U18
U4
T35
T33
T30
T28
T27
T26
T10
T9
T8
T6
T3
T1
R32
R4
R1
P33
P30
P28
P27
P26
P9
P8
P6
P3
N35
N32
N4
N1
M33
M30
M28
M27
M26
M6
M3
L35

GND

U43G

L31

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L26
L25

L24
K33
K29
K27
K25
K22
K20
K18
K16
K14
K12
K11

J35

J32

J28

J22

J20

J18

J16

J14

J12

J10
H33
H30
H26
H24
H22
H20
H18
H16
H14
H12

H9
H8
H5

H2
G35
G31
G28

F26
F24
F22
F20
F18

SPRINGDALE_UFCBGA932

F16
F14
F12
F10
F8
F5
F3
F1
E3
E1
D35
D33
D31
D29
D27
D25
D23
D21
D19
D17
D15
D13
D11
D9
D1
C28
C26
C24
C22
C20
C18
C16
C14
C12
C10
C8
C4
A32
A29
A27
A25
A23
A20
A16
A13
A11
A9
A7

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Springdale-Host/GND (1/4)

B

LA-1911

0.2

7 57Friday, August 08, 2003

1

5

DDRA_SMA[0..12]12,14

D D

C C

+SM_VREF_A

+SM_VREF_A trace width of 12mils and space
12mils(min)

2

C730

2.2U_0805_16V4Z

1

2

1

C731

0.1U_0402_16V4Z

DDRA_SMA[0..12]

DDRA_SWE#12,14
DDRA_SCAS#12,14
DDRA_SRAS#12,14

DDRA_SBS012,14
DDRA_SBS112,14

DDRA_SCS#012,14
DDRA_SCS#112,14

DDRA_CKE012,14
DDRA_CKE112,14

DDRA_CLK112
DDRA_CLK1#12
DDRA_CLK212
DDRA_CLK2#12

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12

DDRA_SCS#0
DDRA_SCS#1 DDRA_SDQ18

DDRA_CKE0
DDRA_CKE1

SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL

Close to GMCH(E34)

B B

A A

4

U43B

AJ34

SMAA_A0

AL33

SMAA_A1

AK29

SMAA_A2

AN31

SMAA_A3

AL30

SMAA_A4

AL26

SMAA_A5

AL28

SMAA_A6

AN25

SMAA_A7

AP26

SMAA_A8

AP24

SMAA_A9

AJ33

SMAA_A10

AN23

SMAA_A11

AN21

SMAA_A12

AL34

SMAB_A1

AM34

SMAB_A2

AP32

SMAB_A3

AP31

SMAB_A4

AM26

SMAB_A5

AB34

SWE_A#

Y34

SCAS_A#

AC33

SRAS_A#

AE33

SBA_A0

AH34

SBA_A1

AA34

SCS_A0#

Y31

SCS_A1#

Y32

SCS_A2#

W34

SCS_A3#

AL20

SCKE_A0

AN19

SCKE_A1

AM20

SCKE_A2

AP20

SCKE_A3

AK32

SCMDCLK_A0

AK31

SCMDCLK_A0#

AP17

SCMDCLK_A1

AN17

SCMDCLK_A1#

N33

SCMDCLK_A2

N34

SCMDCLK_A2#

AK33

SCMDCLK_A3

AK34

SCMDCLK_A3#

AM16

SCMDCLK_A4

AL16

SCMDCLK_A4#

P31

SCMDCLK_A5

P32

SCMDCLK_A5#

E34

SMVREF_A

AK9

SMXRCOMP

AN9

SMXRCOMPVOH

AL9

SMXRCOMPVOL

SPRINGDALE_UFCBGA932

SDQS_A0

SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7

SDQS_A1

SDM_A1
SDQ_A8

SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15

SDQS_A2

SDM_A2
SDQ_A16

SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21

DDR Channel A

SDQ_A22
SDQ_A23

SDQS_A3

SDM_A3
SDQ_A24

SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31

SDQS_A4

SDM_A4
SDQ_A32

SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39

SDQS_A5

SDM_A5
SDQ_A40

SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47

SDQS_A6

SDM_A6
SDQ_A48

SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55

SDQS_A7

SDM_A7
SDQ_A56

SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63

AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13

AP15
AP16

AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18

AP23
AM24

AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27

AM30
AP30

AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34

AF34
AF31

AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34

V34
W33

AC34
AB31
V32
V31
AD31
AB32
U34
U33

M32
M34

T34
T32
K34
K32
T31
P34
L34
L33

H31
H32

J33
H34
E33
F33
K31
J34
G34
F34

DDRA_SDQ[0..63]

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

3

DDRA_SDQS0 12,14
DDRA_SDM0 12,14

DDRA_SDQS1 12,14
DDRA_SDM1 12,14

DDRA_SDQS2 12,14
DDRA_SDM2 12,14

DDRA_SDQS3 12,14
DDRA_SDM3 12,14

DDRA_SDQS4 12,14
DDRA_SDM4 12,14

DDRA_SDQS5 12,14
DDRA_SDM5 12,14

DDRA_SDQS6 12,14
DDRA_SDM6 12,14

DDRA_SDQS7 12,14
DDRA_SDM7 12,14

DDRA_SDQ[0..63] 12,14

2

DDR Resistive Compensation

+2.5V

12

R94

42.2_0603_1%

2

C92

2.2U_0805_16V4Z

1

12

R98

42.2_0603_1%

DDR RCOMP VOH Circuitry

+2.5V

2

C590

2.2U_0805_16V4Z

1

1

C595
1U_0603_10V6K

2

12

R434
10K_0603_1%

SMXRCOMPVOH

12

R436

30.9K_0603_1%

*

Follow Intel design guide
R1.11(12474) page124,125

DDR RCOMP VOL Circuitry

+2.5V

2

C110

2.2U_0805_16V4Z

1

1

C146
1U_0603_10V6K

2

12

R106

30.9K_0603_1%

*

12

R110
10K_0603_1%

1

Trace width of 12mils and space
10mils(min)

SMXRCOMP

Place resistors within

1.0 inch of GMCH (AK9)

*

R391 Change to 31.12K is real

Trace width of 12mils and space
10mils(min)

1

C777

0.01U_0402_16V7K

2

1

C152

0.01U_0402_16V7K

2

Close to Pin AN9

Close to GMCH <1"

*

R153 Change to 31.12K is real

Trace width of 12mils and space
10mils(min)

SMXRCOMPVOL

1

C167

0.01U_0402_16V7K

2

Close to Pin AL9

Close to GMCH <1"

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Springdale-DDR Interface-A(2/5)

Size Document Number Rev

B

LA-1911

Date: Sheet of

8 57Friday, August 08, 2003

1

0.2

5

DDRB_SMA[0..12]13,14

D D

C C

SM_VREF_B and SM_VREF_A
are connected inside GMCH.

+2.5V

2

12

R442
150_0603_1%

12

B B

R444
150_0603_1%

1

2

1

C598

2.2U_0805_16V4Z

C612

2.2U_0805_16V4Z

+SM_VREF_B

DDRB_SMA[0..12]

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDRB_SWE#13,14
DDRB_SCAS#13,14
DDRB_SRAS#13,14

DDRB_SBS013,14
DDRB_SBS113,14

DDRB_SCS#013,14
DDRB_SCS#113,14

DDRB_CKE013,14
DDRB_CKE113,14

DDRB_CLK113
DDRB_CLK1#13
DDRB_CLK213
DDRB_CLK2#13

+SM_VREF_B trace width of
12mils and space
12mils(min)

2

C138

0.1U_0402_16V4Z

1

DDRB_SCS#0
DDRB_SCS#1

DDRB_CKE0
DDRB_CKE1

SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL

Close to GMCH(AP9)

A A

4

U43C

AG31

SMAA_B0

AJ31

SMAA_B1

AD27

SMAA_B2

AE24

SMAA_B3

AK27

SMAA_B4

AG25

SMAA_B5

AL25

SMAA_B6

AF21

SMAA_B7

AL23

SMAA_B8

AJ22

SMAA_B9

AF29

SMAA_B10

AL21

SMAA_B11

AJ20

SMAA_B12

AE27

SMAB_B1

AD26

SMAB_B2

AL29

SMAB_B3

AL27

SMAB_B4

AE23

SMAB_B5

W27

SWE_B#

W31

SCAS_B#

W26

SRAS_B#

Y25

SBA_B0

AA25

SBA_B1

U26

SCS_B0#

T29

SCS_B1#

V25

SCS_B2#

W25

SCS_B3#

AK19

SCKE_B0

AF19

SCKE_B1

AG19

SCKE_B2

AE18

SCKE_B3

AG29

SCMDCLK_B0

AG30

SCMDCLK_B0#

AF17

SCMDCLK_B1

AG17

SCMDCLK_B1#

N27

SCMDCLK_B2

N26

SCMDCLK_B2#

AJ30

SCMDCLK_B3

AH29

SCMDCLK_B3#

AK15

SCMDCLK_B4

AL15

SCMDCLK_B4#

N31

SCMDCLK_B5

N30

SCMDCLK_B5#

AP9

SMVREF_B

AA33

SMYRCOMP

R34

SMYRCOMPVOH

R33

SMYRCOMPVOL

SPRINGDALE_UFCBGA932

SDQS_B0

SDM_B0

SDQ_B0

SDQ_B1

SDQ_B2

SDQ_B3

SDQ_B4

SDQ_B5

SDQ_B6

SDQ_B7

SDQS_B1

SDM_B1

SDQ_B8

SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15

SDQS_B2

SDM_B2
SDQ_B16

SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20

DDR Channel B

SDQ_B21
SDQ_B22
SDQ_B23

SDQS_B3

SDM_B3
SDQ_B24

SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31

SDQS_B4

SDM_B4
SDQ_B32

SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39

SDQS_B5

SDM_B5
SDQ_B40

SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47

SDQS_B6

SDM_B6
SDQ_B48

SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55

SDQS_B7

SDM_B7
SDQ_B56

SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63

AF15
AG11
AJ10
AE15
AL11
AE16
AL8
AF12
AK11
AG12

AG13
AG15

AE17
AL13
AK17
AL17
AK13
AJ14
AJ16
AJ18

AG21
AE21

AE19
AE20
AG23
AK23
AL19
AK21
AJ24
AE22

AH27
AJ28

AK25
AH26
AG27
AF27
AJ26
AJ27
AD25
AF28

AD29
AC31

AE30
AC27
AC30
Y29
AE31
AB29
AA26
AA27

U30
U31

AA30
W30
U27
T25
AA31
V29
U25
R27

L27
M29

P29
R30
K28
L30
R31
R26
P25
L32

J30
J31

K30
H29
F32
G33
N25
M25
J29
G32

DDRB_SDQ[0..63]

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

3

DDRB_SDQS0 13,14
DDRB_SDM0 13,14

DDRB_SDQS1 13,14
DDRB_SDM1 13,14

DDRB_SDQS2 13,14
DDRB_SDM2 13,14

DDRB_SDQS3 13,14
DDRB_SDM3 13,14

DDRB_SDQS4 13,14
DDRB_SDM4 13,14

DDRB_SDQS5 13,14
DDRB_SDM5 13,14

DDRB_SDQS6 13,14
DDRB_SDM6 13,14

DDRB_SDQS7 13,14
DDRB_SDM7 13,14

DDRB_SDQ[0..63] 13,14

2

DDR Resistive Compensation

DDR RCOMP VOH Circuitry

2

C709

2.2U_0805_16V4Z

1

1

C691
1U_0603_10V6K

2

DDR RCOMP VOL Circuitry

2

C316

2.2U_0805_16V4Z

1

1

C300
1U_0603_10V6K

2

1

+2.5V

2

12

R494

42.2_0603_1%

SMYRCOMP

12

R496

42.2_0603_1%

R398 Change to 31.12K is real

*

C685

2.2U_0805_16V4Z

1

Trace width of 12mils
and space 10mils(min)

Place resistors within

1.0 inch of GMCH (AA33)

Trace width of 12mils and space
10mils(min)

+2.5V

12

R510
10K_0603_1%

SMYRCOMPVOH

12

R506

30.9K_0603_1%

R163 Change to 31.12K is real

*

+2.5V

1

C778

0.01U_0402_16V7K

2

1

C296

0.01U_0402_16V7K

2

Close to Pin R14

Close to GMCH <1"

Trace width of 12mils and space
10mils(min)

12

R224

30.9K_0603_1%

SMYRCOMPVOL

12

R223
10K_0603_1%

1

C292

0.01U_0402_16V7K

2

Close to Pin R33

Close to GMCH <1"

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Springdale-DDR Interface-B(3/5)

Size Document Number Rev

B

LA-1911

Date: Sheet of

9 57Friday, August 08, 2003

1

0.2

5

+1.5VS

12

R112

43.2_0402_1%

D D

+1.5VS

C C

B B

GRCOMP

12

R163
226_0603_1%

HI_SWING_MCH

12

R439
147_0603_1%

HI_VREF_MCH

12

R437
113_0603_1%

1

C151

0.1U_0402_16V4Z

2

1

C149

0.1U_0402_16V4Z

2

1

C164

2

0.1U_0402_16V4Z

1

C605

0.1U_0402_16V4Z

2

+1.5VS

12

R100
226_0603_1%

CI_SWING_GMCH

12

R99
147_0603_1%

CI_VREF_GMCH

12

R108
113_0603_1%

+1.5VS

12

R103

52.3_0603_1%

HI_RCOMP_MCH

GMCH-HUB Reference Circuit

Close to GMCH(AE3)

1

C170

0.01U_0402_16V7K

2

Close to GMCH ball <250mils

Close to GMCH(AE2)

1

C603

0.01U_0402_16V7K

2

Close to GMCH ball <250mils

GMCH-CSA Reference Circuit

Close to GMCH(AF2)

1

C137

0.01U_0402_16V7K

2

Close to GMCH ball <250mils

0.35V

Close to GMCH(AF4)

1

C158

0.01U_0402_16V7K

2

CLK_MCH_66M

Note:
HI_SWING_MCH, HI_VREF_MCH
trace width of 10mils and
space 7mils

Note:
CI_SWING_MCH, CI_VREF_MCH
trace width of 10mils and
space 20mils

Close to GMCH ball <250mils

+1.5VS

12

R150

60.4_0603_1%

AGP_SWING

12

R143

39.2_0603_1%

+AGP_VREF = 0.3535

1 2

A A

R144

44.2_0603_1%

12

R151

100_0603_1%

GMCH-AGP Reference Circuit

Close GMCH ball (AC3) less than 250mils

1

C175

0.1U_0402_16V4Z

2

+AGP_VREF

1

C160

0.01U_0402_16V7K

2

1

C171

0.01U_0402_16V7K

2

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

Note:
Springdale Customer Schematic R1.2 page18
AGP_SWING only had 0.1u cap ; But Springdale
Chipset Platform Design guide Rev1.11(12474)
page138 had a 0.01uf cap. need confirm with
Intel.

Close GMCH ball (AD2)
less than 250mils

5

12

R453
@10_0402_5%

1

C624
@10P_0402_50V8K

2

4

R590

+3VS

R596

4

@1K_0402_5%1 2
@0_0402_5%

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AGP_C/BE#[0..3]16

AGP_FRAME#16
CLK_MCH_66M15
AGP_DEVSEL#16

AGP_IRDY#16

AGP_TRDY#16

AGP_STOP#16

AGP_PAR16

AGP_REQ#16
AGP_GNT#16

+AGP_VREF

AGP_RBF#16
AGP_WBF#16

AGP_DBIHI16
AGP_DBILO16

AGP_ST[0..2]16

HUB_HL[0..10]23

HUB_HLSTRF23

HUB_HLSTRS23

R435 52.3_0603_1%

+1.5VS

PCIRST#16,22,23,26,27,29,30,33,34,37

3

1 2

R166 0_0402_5%

R128 0_0402_5%

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

CLK_MCH_66M AGP_AD3

AGP_PAR

GRCOMP
AGP_SWING
+AGP_VREF

AGP_ST0
AGP_ST1
AGP_ST2

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

HI_RCOMP_MCH
HI_SWING_MCH
HI_VREF_MCH

CI_SWING_GMCH
CI_VREF_GMCH

12

12

2

U43D

Y7

GCBE0

W5

GCBE1

AA3

GCBE2

U2

GCBE3

U6

GFRAME

H4

GCLKIN

AB4

GDEVSEL

V11

GIRDY

AB5

GTRDY

W11

GSTOP

AB2

GPAR/ADD_DETECT

N6

GREQ

M7

GGNT

AC2

GRCOMP/DVOBCGCOMP

AC3

GVSWING

AD2

GVREF

R10

GRBF

R9

GWBF

M4

DBI_HI

M5

DBI_LO

N3

GST0

N5

GST1

N2

GST2

AF5

HI0

AG3

HI1

AK2

HI2

AG5
AK5

AL3
AL2
AL4
AJ2

AH2

AJ3
AH5
AH4

AD4
AE3
AE2

AK7
AH7

AD11

AF7
AD7

AC10

AF8
AG7
AE9
AH9
AG6

AJ6

AJ5
AG2

AF2

AF4

AP8

AJ8
AK4

AG10

AG9

AN35
AP34

AR1

G4

HUB

HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HISTRF
HISTRS

HI_RCOMP
HI_SWING
HI_VREF

CI0
CI1
CI2
CI3
CI4

CSA

CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS

CI_RCOMP
CI_SWING
CI_VREF

DREFCLK
EXTTS#
ICH_SYNC#
RSTIN#

RESERVED_1
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5

SPRINGDALE_UFCBGA932

2

AGP

1

AGP_AD[0..31] 16

GADSTBF0

GADSTBS0#

GADSTBF1

GADSTBS1#

GSBSTBF

GSBSTBS#

DDCA_DATA

DDCA_CLK

VGA

AC6
AC5

AGP_AD0

AE6

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8

GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15

GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#

RED

RED#

GREEN

GREEN#

BLUE
BLUE#

HSYNC
VSYNC

REFSET

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20

Title

Size Document Number Rev

B

Date: Sheet of

AGP_AD1

AC11

AGP_AD2

AD5
AE5

AGP_AD4

AA10

AGP_AD5

AC9

AGP_AD6

AB11

AGP_AD7

AB7

AGP_AD8

AA9

AGP_AD9

AA6

AGP_AD10

AA5

AGP_AD11

W10

AGP_AD12

AA11

AGP_AD13

W6

AGP_AD14

W9

AGP_AD15

V7
V4

V5

AGP_AD16

AA2

AGP_AD17

Y4

AGP_AD18

Y2

AGP_AD19

W2

AGP_AD20

Y5

AGP_AD21

V2

AGP_AD22

W3

AGP_AD23

U3

AGP_AD24

T2

AGP_AD25

T4

AGP_AD26

T5

AGP_AD27

R2

AGP_AD28

P2

AGP_AD29

P5

AGP_AD30

P4

AGP_AD31

M2
U11

T11

AGP_SBA0

R6

AGP_SBA1

P7

AGP_SBA2

R3

AGP_SBA3

R5

AGP_SBA4

U9

AGP_SBA5

U10

AGP_SBA6

U5

AGP_SBA7

T7

R149 0_0402_5%

H3

R165 0_0402_5%12

F2

R170 0_0402_5%12

F4
E4

R169 0_0402_5%12

H6
G5

R172 0_0402_5%12

H7
G6

G3
E2

R460 0_0402_5%12

D2
A3

A33
A35

Analog RGB/CRT guidelines

AF13

for Springdale-P

AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25

Springdale-AGP/HUB/VGA/CSA (4/5)

LA-1911

AGP_AD_STBF0 16
AGP_AD_STBS0 16

AGP_AD_STBF1 16
AGP_AD_STBS1 16

12

1

AGP_SB_STBF 16
AGP_SB_STBS 16
AGP_SBA[0..7] 16

10 57Friday, August 08, 2003

0.2

5

4

+2.5V

3

2

1

1

Note:
Placed less than 100 mils from ball

Route to GMCH ball without via

D D

1

C681

0.47U_0603_16V7K

2

2

C713

0.1U_0402_10V6K

1

C C

C618

0.1U_0402_10V6K

12

C620 0.22U_0603_10V7K

C736

0.47U_0603_16V7K

12

C719 0.22U_0603_10V7K

C128

Trace 14mils

R467

B B

Note:
Placed less than 100 mils from ball

Route to GMCH ball without via

A A

0.1U_0402_10V6K

12

12

C329 0.1U_0402_10V6K

R462 0_0402_5%

0_0402_5%12

12

1 2

C248 0.1U_0402_10V6K

VTT_DCAP1
VTT_DCAP2

1

C699

0.47U_0603_16V7K

2

+VTT_GMCH

+2.5V

VCC_DDR_DCAP5

12

VCC_DDR_DCAP4

VCC_DDR_DCAP1

12

VCC_AGP_DCAP2

+1.5VS

VTT_DCAP3
VCCA_FSB
VCCA_DPLL
VCCA_DAC

VCC_DDR_DCAP2 VCCA_FSB1 VCCA_FSB

VCCA1P5_DDR_SM

(1A)

*

+3VS

U43E

A15

VTT

A21

VTT

A4

VTT

A5

VTT

A6

VTT

B5

VTT

B6

VTT

C5

VTT

C6

VTT

D5

VTT

D6

VTT

D7

VTT

E6

VTT

E7

VTT

F7

VTT

AA35

VCC_DDR

AL6

VCC_DDR

AL7

VCC_DDR

AM1

VCC_DDR

AM2

VCC_DDR

AM3

VCC_DDR

AM5

VCC_DDR

AM6

VCC_DDR

AM7

VCC_DDR

AM8

VCC_DDR

AN2

VCC_DDR

AN4

VCC_DDR

AN5

VCC_DDR

AN6

VCC_DDR

AN7

VCC_DDR

AN8

VCC_DDR

AP3

VCC_DDR

AP4

VCC_DDR

AP5

VCC_DDR

AP6

VCC_DDR

AP7

VCC_DDR

AR15

VCC_DDR

AR21

VCC_DDR

AR31

VCC_DDR

AR4

VCC_DDR

AR5

VCC_DDR

AR7

VCC_DDR

E35

VCC_DDR

R35

VCC_DDR

G1

VCC_DAC

G2

VCC_DAC

AG1

VCCA_AGP

Y11

VCCA_AGP

A31

VCCA_FSB

B4

VCCA_FSB

B3

VCCA_DPLL

C2

VCCA_DAC

AL35

VCCA_DDR

AB25

VCCA_DDR

AC25

VCCA_DDR

AC26

VCCA_DDR

SPRINGDALE_UFCBGA932

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page84

POWER

VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP

VSSA_DAC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

J6
J7
J8
J9
K6
K7
K8
K9
L6
L7
L9
L10
L11
M8
M9
M10
M11
N9
N10
N11
P10
P11
R11
T16
T17
T18
T19
T20
U16
U17
U20
V16
V18
V20
W16
W19
W20
Y16
Y17
Y18
Y19
Y20

J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5
Y1

D3

+1.5VS

VCC_AGP_DCAP1

C90
22U_1206_10V4Z

2

+2.5V

1

C150

0.1U_0402_10V6K

2

+1.5VS

1

C231

0.1U_0402_10V6K

2

+1.5VS

1

+

C198
470U_D4_2.5VM

2

Place at the output of the 1.5V VR

+VTT_GMCH +2.5V

1 2

C166

0.1U_0402_10V6K

2

C91

4.7U_0805_6.3V6K

1

1

C98

0.1U_0402_10V6K

2

1

C229

0.1U_0402_10V6K

2

2

C224

4.7U_0805_6.3V6K

1

1

C242

0.1U_0402_10V6K

2

Place near GMCH

+1.5VS

1

C105

0.1U_0402_10V6K

2

1

C283

0.1U_0402_10V6K

2

1

C217

0.1U_0402_10V6K

2

C243
10U_1206_10V4Z

+1.5VS

1

C233

0.1U_0402_10V6K

2

Place near ball
Y11,routing trace
from cap to ball

1

C208

0.1U_0402_10V6K

2

+1.5VS

1

C246

0.1U_0402_10V6K

2

1

C213

0.1U_0402_10V6K

2

+VTT_GMCH

1

+

C266
470U_D4_2.5VM

2

Note: Please change to 0.82uH, DC current
of 30mA parts and close to cap

+1.5VS

R141
0_0603_5%

12

1 2

LQG21F4R7N00_0805

Note: Please change to 1uH(0.54uH-D-IN), DC current
of 1000mA parts and close to cap
Trace 50mils
Trace 35mils (under GMCH ball field)

R183
0_0603_5%

VCCA_DDR VCCA1P5_DDR_SM

12

1 2

0_0805_5%

1

2

1

2

Place near GMCH

L15

**

**

L18

1

C103

0.1U_0402_10V6K

2

1

C201

0.1U_0402_10V6K

2

C207

0.1U_0402_10V6K

2

C240

0.1U_0402_16V4Z

1

C148

0.1U_0402_10V6K

Trace 14milsTrace 14mils

12

C214

+

150U_D2_6.3VM

1

C222
22U_1206_6.3V6M

2

1

C114

0.1U_0402_10V6K

2

1

C220

0.1U_0402_10V6K

2

2

C253

4.7U_0805_6.3V6K

1

Trace 35mils

(1A)(1A)

1

C117

0.1U_0402_10V6K

2

1

C197

0.1U_0402_10V6K

2

2

1

2

C235

0.1U_0402_16V4Z

1

Close to GMCH

2

C241

0.1U_0402_16V4Z

1

Close to GMCH

1

C109

0.1U_0402_10V6K

2

1

C216

0.1U_0402_10V6K

2

C258

4.7U_0805_6.3V6K

1

C249
1U_0603_10V6K

2

1

C123

0.1U_0402_10V6K

2

1

C234

0.1U_0402_10V6K

2

1

2

C244

0.47U_0603_16V7K

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Springdale-Decoupling (5/5)

B

LA-1911

0.2

11 57Friday, August 08, 2003

1

5

+2.5V

JP22

1

VREF

3

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0
DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ2

D D

DDRA_CLK18
DDRA_CLK1#8

C C

DDRA_CKE18,14

DDRA_SBS08,14
DDRA_SWE#8,14
DDRA_SCS#08,14

B B

A A

ICH_SMB_DATA13,15,23
ICH_SMB_CLK13,15,23

5

DDRA_SDQ12
DDRA_SDQ8

DDRA_SDQS1
DDRA_SDQ10

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ19
DDRA_SDQ28

DDRA_SDQ29
DDRA_SDQS3

DDRA_SDQ30
DDRA_SDQ27

DDRA_CKE1
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ44

DDRA_SDQ41 DDRA_SDQ45
DDRA_SDQS5

DDRA_SDQ43
DDRA_SDQ46

DDRA_SDQ48
DDRA_SDQ53

DDRA_SDQS6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7

DDRA_SDQ62
DDRA_SDQ59

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

KEYLINK_5762-3-111

4

DU/RESET#

4

2

VREF

4

VSS

6

DQ4

8

DQ5

10

VDD

12

DM0

14

DQ6

16

VSS

18

DQ7

20

DQ12

22

VDD

24

DQ13

26

DM1

28

VSS

30

DQ14

32

DQ15

34

VDD

36

VDD

38

VSS

40

VSS

42

DQ20

44

DQ21

46

VDD

48

DM2

50

DQ22

52

VSS

54

DQ23

56

DQ28

58

VDD

60

DQ29

62

DM3

64

VSS

66

DQ30

68

DQ31

70

VDD

72

CB4

74

CB5

76

VSS

78

DM8

80

CB6

82

VDD

84

CB7

86
88

VSS

90

VSS

92

VDD

94

VDD

96

CKE0

98

DU/BA2

100

A11

102

A8

104

VSS

106

A6

108

A4

110

A2

112

A0

114

VDD

116

BA1

118

RAS#

120

CAS#

122

S1#

124

DU

126

VSS

128

DQ36

130

DQ37

132

VDD

134

DM4

136

DQ38

138

VSS

140

DQ39

142

DQ44

144

VDD

146

DQ45

148

DM5

150

VSS

152

DQ46

154

DQ47

156

VDD

158

CK1#

160

CK1

162

VSS

164

DQ52

166

DQ53

168

VDD

170

DM6

172

DQ54

174

VSS

176

DQ55

178

DQ60

180

VDD

182

DQ61

184

DM7

186

VSS

188

DQ62

190

DQ63

192

VDD

194

SA0

196

SA1

198

SA2

200

DU

H = 5.2mm

+2.5V

DDRA_SDQ5
DDRA_SDQ4

DDRA_SDM0

DDRA_SDQ3
DDRA_SDQ9

DDRA_SDQ13
DDRA_SDM1

DDRA_SDQ14
DDRA_SDQ11

DDRA_SDQ21
DDRA_SDQ17

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ24

DDRA_SDQ25
DDRA_SDM3

DDRA_SDQ26
DDRA_SDQ31

DDRA_CKE0
DDRA_SMA11

DDRA_SMA8
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SDQ32
DDRA_SDQ33

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ47

DDRA_SDQ49
DDRA_SDQ52

DDRA_SDM6
DDRA_SDQ51

DDRA_SDQ50
DDRA_SDQ56

DDRA_SDQ57
DDRA_SDM7

DDRA_SDQ63
DDRA_SDQ58

SO-DIMM 0
REVERSE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

3

DDRA_VREF trace width of
12mils and space 12mils(min)

DDRA_VREF

1

C100

0.1U_0402_16V4Z

2

Close to SO-DIMM

+2.5V

1

C255

0.1U_0402_10V6K

2

DDRA_CKE0 8,14

DDRA_SBS1 8,14
DDRA_SRAS# 8,14
DDRA_SCAS# 8,14
DDRA_SCS#1 8,14

DDRA_CLK2# 8
DDRA_CLK2 8

3

+2.5V

1

C116
22U_1206_10V4Z

2

1

C276

0.1U_0402_10V6K

2

2

+2.5V

12

R87
75_0603_1%

12

R92
75_0603_1%

DDRA_SDQ[0..63]8,14
DDRA_SDQS[0..7]8,14
DDRA_SMA[0..12]8,14
DDRA_SDM[0..7]8,14

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]

System Memory Decoupling caps

1

C134

0.1U_0402_10V6K

2

1

C302

0.1U_0402_10V6K

2

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*14

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42

1

C161

0.1U_0402_10V6K

2

1

C319

0.1U_0402_10V6K

2

2

1

C192

0.1U_0402_10V6K

2

1

C330

0.1U_0402_10V6K

2

Title

Size Document Number Rev

Date: Sheet of

1

C204

0.1U_0402_10V6K

2

1

C341

0.1U_0402_10V6K

2

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-1911

1

1

C227

0.1U_0402_10V6K

2

1

C347

0.1U_0402_10V6K

2

1

1

C247

0.1U_0402_10V6K

2

1

C354

0.1U_0402_10V6K

2

12 57Friday, August 08, 2003

0.2

5

4

3

2

1

+2.5V

JP23

1

VREF

3

DDRB_SDQ4
DDRB_SDQ0

DDRB_SDQS0
DDRB_SDQ7

D D

DDRB_CLK19
DDRB_CLK1#9

C C

DDRB_CKE19,14

DDRB_SBS09,14
DDRB_SWE#9,14
DDRB_SCS#09,14

B B

A A

ICH_SMB_DATA12,15,23
ICH_SMB_CLK12,15,23

DDRB_SDQ5
DDRB_SDQ9

DDRB_SDQ12
DDRB_SDQS1

DDRB_SDQ10
DDRB_SDQ14

DDRB_SDQ20
DDRB_SDQ21

DDRB_SDQS2
DDRB_SDQ22

DDRB_SDQ17
DDRB_SDQ24

DDRB_SDQ25
DDRB_SDQS3

DDRB_SDQ26
DDRB_SDQ30

DDRB_CKE1
DDRB_SMA12

DDRB_SMA9
DDRB_SMA7

DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0

DDRB_SDQ33
DDRB_SDQ34

DDRB_SDQS4
DDRB_SDQ37

DDRB_SDQ38
DDRB_SDQ40

DDRB_SDQ44
DDRB_SDQS5

DDRB_SDQ43 DDRB_SDQ41
DDRB_SDQ42

DDRB_SDQ52
DDRB_SDQ49

DDRB_SDQS6
DDRB_SDQ55

DDRB_SDQ60
DDRB_SDQ56

DDRB_SDQS7
DDRB_SDQ58

DDRB_SDQ57

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

KLINK_5746-3-111

DU/RESET#

VREF

VSS

DQ4
DQ5

VDD

DM0
DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2

DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4
CB5

VSS

DM8
CB6

VDD

CB7

VSS

VSS

VDD

VDD

CKE0

DU/BA2

A11

VSS

VDD

BA1
RAS#
CAS#

S1#

DU

VSS
DQ36
DQ37

VDD

DM4

DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6

DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0
SA1
SA2

DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

H= 9.2mm

5

4

DDRB_VREF trace width of
12mils and space 12mils(min)

DDRB_SDQ2
DDRB_SDQ6

DDRB_SDM0
DDRB_SDQ1

DDRB_SDQ3
DDRB_SDQ13

DDRB_SDQ11
DDRB_SDM1

DDRB_SDQ15
DDRB_SDQ8

DDRB_SDQ19
DDRB_SDQ16

DDRB_SDM2
DDRB_SDQ18

DDRB_SDQ23
DDRB_SDQ28

DDRB_SDQ29
DDRB_SDM3

DDRB_SDQ27
DDRB_SDQ31

DDRB_CKE0
DDRB_SMA11

DDRB_SMA8
DDRB_SMA6

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

DDRB_SDQ32
DDRB_SDQ36

DDRB_SDM4
DDRB_SDQ39

DDRB_SDQ35
DDRB_SDQ46

DDRB_SDQ45
DDRB_SDM5

DDRB_SDQ47

DDRB_SDQ48
DDRB_SDQ53

DDRB_SDM6
DDRB_SDQ51

DDRB_SDQ54DDRB_SDQ50
DDRB_SDQ62

DDRB_SDQ61
DDRB_SDM7

DDRB_SDQ59
DDRB_SDQ63

+3VS

DDRB_VREF

2

C101

0.1U_0402_16V4Z

1

DDRB_CKE0 9,14

DDRB_SBS1 9,14
DDRB_SRAS# 9,14
DDRB_SCAS# 9,14
DDRB_SCS#1 9,14

DDRB_CLK2# 9
DDRB_CLK2 9

+2.5V

REVERSESO-DIMM 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+2.5V+2.5V

+2.5V

1

C118

0.1U_0402_10V6K

2

+2.5V

1

C281

0.1U_0402_10V6K

2

1

C189

0.1U_0402_10V6K

2

DDRB_SDQ[0..63]9,14

12

R86
75_0603_1%

12

R90
75_0603_1%

DDRB_SDQS[0..7]9,14
DDRB_SMA[0..12]9,14
DDRB_SDM[0..7]9,14

System Memory Decoupling caps

1

C139

0.1U_0402_10V6K

2

1

C318

0.1U_0402_10V6K

2

1

C165

0.1U_0402_10V6K

2

1

C162

0.1U_0402_10V6K

2

1

C312

0.1U_0402_10V6K

2

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 0.1uF*24

1

C254

0.1U_0402_10V6K

2

1

2

1

2

1

C289

0.1U_0402_10V6K

2

2

C168

0.1U_0402_10V6K

C333

0.1U_0402_10V6K

1

C190

0.1U_0402_10V6K

2

1

C331

0.1U_0402_10V6K

2

1

C113

0.1U_0402_10V6K

2

Title

Size Document Number Rev

Date: Sheet of

DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]

1

C223

0.1U_0402_10V6K

2

1

C346

0.1U_0402_10V6K

2

1

C309

0.1U_0402_10V6K

2

1

C225

0.1U_0402_10V6K

2

1

C353

0.1U_0402_10V6K

2

1

C305

0.1U_0402_10V6K

2

Compal Electronics, Inc.
DDR-SODIMM SLOT2

LA-1911

1

1

C256

0.1U_0402_10V6K

2

1

C355

0.1U_0402_10V6K

2

1

C193

0.1U_0402_10V6K

2

13 57Friday, August 08, 2003

0.2

5

Channel A(DIMM0) Termination resistors & Decoupling caps

+1.25VS +1.25VS

DDRA_SDQ1
DDRA_SDQ0

DDRA_SDQ6
DDRA_SDQS0

D D

DDRA_SDQ12
DDRA_SDQ2

DDRA_SDQS1
DDRA_SDQ8

DDRA_SDQ15
DDRA_SDQ10

DDRA_SDQ16
DDRA_SDQ20

DDRA_SDQ18
DDRA_SDQS2

C C

DDRA_SDQ28
DDRA_SDQ19

DDRA_SDQS3
DDRA_SDQ29

DDRA_SDQ27
DDRA_SDQ30

DDRA_SDQ37
DDRA_SDQ36

DDRA_SDQ34
DDRA_SDQS4

DDRA_SDQ44
DDRA_SDQ35

B B

DDRA_SDQS5
DDRA_SDQ41

DDRA_SDQ46
DDRA_SDQ43

DDRA_SDQ53
DDRA_SDQ48

DDRA_SDQ54
DDRA_SDQS6

DDRA_SDQ60
DDRA_SDQ55

DDRA_SDQS7
DDRA_SDQ61

A A

DDRA_SDQ59
DDRA_SDQ62

RP72

1 4
2 3

56_0404_4P2R_5%

RP74

1 4
2 3

56_0404_4P2R_5%

RP76

1 4
2 3

56_0404_4P2R_5%

RP77

1 4
2 3

56_0404_4P2R_5%

RP79

1 4
2 3

56_0404_4P2R_5%

RP85

1 4
2 3

56_0404_4P2R_5%

RP87

1 4
2 3

56_0404_4P2R_5%

RP89

1 4
2 3

56_0404_4P2R_5%

RP91

1 4
2 3

56_0404_4P2R_5%

RP97

1 4
2 3

56_0404_4P2R_5%

RP109

1 4
2 3

56_0404_4P2R_5%

RP112

1 4
2 3

56_0404_4P2R_5%

RP114

1 4
2 3

56_0404_4P2R_5%

RP116

1 4
2 3

56_0404_4P2R_5%

RP118

1 4
2 3

56_0404_4P2R_5%

RP120

1 4
2 3

56_0404_4P2R_5%

RP121

1 4
2 3

56_0404_4P2R_5%

RP123

1 4
2 3

56_0404_4P2R_5%

RP127

1 4
2 3

56_0404_4P2R_5%

RP129

1 4
2 3

56_0404_4P2R_5%

RP6

DDRA_SDQ5

14

DDRA_SDQ4

23

56_0404_4P2R_5%

RP8

DDRA_SDM0

14

DDRA_SDQ7

23

56_0404_4P2R_5%

RP10

DDRA_SDQ3

14

DDRA_SDQ9

23

56_0404_4P2R_5%

RP12

DDRA_SDQ13

14

DDRA_SDM1

23

56_0404_4P2R_5%

RP15

DDRA_SDQ14

14

DDRA_SDQ11

23

56_0404_4P2R_5%

RP17

DDRA_SDQ21

14

DDRA_SDQ17

23

56_0404_4P2R_5%

RP19

DDRA_SDM2

14

DDRA_SDQ22

23

56_0404_4P2R_5%

RP21

DDRA_SDQ23

14

DDRA_SDQ24

23

56_0404_4P2R_5%

RP23

DDRA_SDQ25

14

DDRA_SDM3

23

56_0404_4P2R_5%

RP26

DDRA_SDQ26

14

DDRA_SDQ31

23

56_0404_4P2R_5%

RP43

DDRA_SDQ32

14

DDRA_SDQ33

23

56_0404_4P2R_5%

RP45

DDRA_SDM4

14

DDRA_SDQ38

23

56_0404_4P2R_5%

RP49

DDRA_SDQ39

14

DDRA_SDQ40

23

56_0404_4P2R_5%

RP51

DDRA_SDQ45

14

DDRA_SDM5

23

56_0404_4P2R_5%

RP53

DDRA_SDQ42

14

DDRA_SDQ47

23

56_0404_4P2R_5%

RP55

DDRA_SDQ49

14

DDRA_SDQ52

23

56_0404_4P2R_5%

RP57

DDRA_SDM6

14

DDRA_SDQ51

23

56_0404_4P2R_5%

RP59

DDRA_SDQ50

14

DDRA_SDQ56

23

56_0404_4P2R_5%

RP61

DDRA_SDQ57

14

DDRA_SDM7

23

56_0404_4P2R_5%

RP63

DDRA_SDQ63

14

DDRA_SDQ58

23

56_0404_4P2R_5%

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*28

5

RP29

56_0404_4P2R_5%

RP98

56_0404_4P2R_5%

RP100

56_0404_4P2R_5%

RP102

56_0404_4P2R_5%

RP104

56_0404_4P2R_5%

RP106

56_0404_4P2R_5%

RP31

56_0404_4P2R_5%

RP34

56_0404_4P2R_5%

RP39

56_0404_4P2R_5%

RP41

56_0404_4P2R_5%

RP36

56_0404_4P2R_5%

+1.25VS

1

C593

2

0.1U_0402_10V6K

+1.25VS

1

C669

2

0.1U_0402_10V6K

+1.25VS

1

C734

2

0.1U_0402_10V6K

+1.25VS

1

C107

2

0.1U_0402_10V6K

+1.25VS

1

C218

2

0.1U_0402_10V6K

DDRA_CKE1

14

DDRA_CKE0

23

DDRA_SMA9

14

DDRA_SMA12

23

DDRA_SMA5

14

DDRA_SMA7

23

DDRA_SMA1

14

DDRA_SMA3

23

DDRA_SBS0

14

DDRA_SMA10

23

DDRA_SCS#0

14

DDRA_SWE#

23

DDRA_SMA11

14

DDRA_SMA8

23

DDRA_SMA6

14

DDRA_SMA4

23

DDRA_SBS1

14

DDRA_SRAS#

23

DDRA_SCAS#

14

DDRA_SCS#1

23

DDRA_SMA2

14

DDRA_SMA0

23

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C606

2

1

C673

2

1

C742

2

1

C129

2

1

C260

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

4

DDRA_CKE1 8,12
DDRA_CKE0 8,12

DDRA_SBS0 8,12

DDRA_SCS#0 8,12

DDRA_SWE# 8,12

DDRA_SBS1 8,12
DDRA_SRAS# 8,12

DDRA_SCAS# 8,12

DDRA_SCS#1 8,12

0.1U_0402_10V6K

1

C627

2

0.1U_0402_10V6K

1

C324

2

0.1U_0402_10V6K

1

C614

2

0.1U_0402_10V6K

1

C185

2

0.1U_0402_10V6K

1

C298

2

4

1

2

1

2

1

2

1

2

1

C338

2

C749

C271

C349

C200

3

Channel B(DIMM2) Termination resistors & Decoupling caps

DDRB_SDQ0
DDRB_SDQ4

DDRB_SDQ7
DDRB_SDQS0

0.1U_0402_10V6K

1

C638

2

0.1U_0402_10V6K

1

C706

2

0.1U_0402_10V6K

1

C720

2

4.7U_1206_16V6K

1

C172

2

0.1U_0402_10V6K

1

C344

2

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]

DDRA_SMA[0..12]

DDRA_SDM[0..7]

DDRB_SDQ9
DDRB_SDQ5

DDRB_SDQS1
DDRB_SDQ12

DDRB_SDQ14
DDRB_SDQ10

DDRB_SDQ21
DDRB_SDQ20

DDRB_SDQ22
DDRB_SDQS2

DDRB_SDQ24
DDRB_SDQ17

DDRB_SDQS3
DDRB_SDQ25

DDRB_SDQ30
DDRB_SDQ26

DDRB_SDQ34
DDRB_SDQ33

DDRB_SDQ37
DDRB_SDQS4

DDRB_SDQ40
DDRB_SDQ38

DDRB_SDQS5
DDRB_SDQ44

DDRB_SDQ42
DDRB_SDQ43

DDRB_SDQ49
DDRB_SDQ52

DDRB_SDQ55
DDRB_SDQS6

DDRB_SDQ60
DDRB_SDQ50

DDRB_SDQS7
DDRB_SDQ56

DDRB_SDQ57
DDRB_SDQ58

3

DDRA_SDQ[0..63]8,12
DDRA_SDQS[0..7]8,12
DDRA_SMA[0..12]8,12
DDRA_SDM[0..7]8,12

1

C631

2

0.1U_0402_10V6K

1

C690

2

0.1U_0402_10V6K

1

C156

2

0.1U_0402_10V6K

12

C649

4.7U_0805_10V4Z

1

C315

2

0.1U_0402_10V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RP7

1 4
2 3

56_0404_4P2R_5%

RP9

1 4
2 3

56_0404_4P2R_5%

RP11

1 4
2 3

56_0404_4P2R_5%

RP13

1 4
2 3

56_0404_4P2R_5%

RP16

1 4
2 3

56_0404_4P2R_5%

RP18

1 4
2 3

56_0404_4P2R_5%

RP20

1 4
2 3

56_0404_4P2R_5%

RP22

1 4
2 3

56_0404_4P2R_5%

RP24

1 4
2 3

56_0404_4P2R_5%

RP27

1 4
2 3

56_0404_4P2R_5%

RP44

1 4
2 3

56_0404_4P2R_5%

RP47

1 4
2 3

56_0404_4P2R_5%

RP50

1 4
2 3

56_0404_4P2R_5%

RP52

1 4
2 3

56_0404_4P2R_5%

RP54

1 4
2 3

56_0404_4P2R_5%

RP56

1 4
2 3

56_0404_4P2R_5%

RP58

1 4
2 3

56_0404_4P2R_5%

RP60

1 4
2 3

56_0404_4P2R_5%

RP62

1 4
2 3

56_0404_4P2R_5%

RP64

1 4
2 3

56_0404_4P2R_5%

RP71

14
23

56_0404_4P2R_5%

RP73

14
23

56_0404_4P2R_5%

RP75

14
23

56_0404_4P2R_5%

RP78

14
23

56_0404_4P2R_5%

RP80

14
23

56_0404_4P2R_5%

RP84

14
23

56_0404_4P2R_5%

RP86

14
23

56_0404_4P2R_5%

RP88

14
23

56_0404_4P2R_5%

RP90

14
23

56_0404_4P2R_5%

RP96

14
23

56_0404_4P2R_5%

RP108

14
23

56_0404_4P2R_5%

RP111

14
23

56_0404_4P2R_5%

RP113

14
23

56_0404_4P2R_5%

RP115

14
23

56_0404_4P2R_5%

RP117

14
23

56_0404_4P2R_5%

RP119

14
23

56_0404_4P2R_5%

RP122

14
23

56_0404_4P2R_5%

RP124

DDRB_SDQ54

14
23

56_0404_4P2R_5%

RP128

14

DDRB_SDM7

23

56_0404_4P2R_5%

RP130

14
23

56_0404_4P2R_5%

DDRB_SDQ2
DDRB_SDQ6

DDRB_SDM0
DDRB_SDQ1

DDRB_SDQ3
DDRB_SDQ13

DDRB_SDQ11
DDRB_SDM1

DDRB_SDQ15
DDRB_SDQ8

DDRB_SDQ19
DDRB_SDQ16

DDRB_SDM2
DDRB_SDQ18

DDRB_SDQ23
DDRB_SDQ28

DDRB_SDQ29
DDRB_SDM3

DDRB_SDQ27
DDRB_SDQ31

DDRB_SDQ32
DDRB_SDQ36

DDRB_SDM4
DDRB_SDQ39

DDRB_SDQ35
DDRB_SDQ46

DDRB_SDQ45
DDRB_SDM5

DDRB_SDQ41
DDRB_SDQ47

DDRB_SDQ48
DDRB_SDQ53

DDRB_SDM6
DDRB_SDQ51

DDRB_SDQ62

DDRB_SDQ61

DDRB_SDQ59
DDRB_SDQ63

2

+1.25VS+1.25VS

RP32

DDRB_CKE1

14

DDRB_CKE0

23

56_0404_4P2R_5%

RP33

DDRB_SMA9

14

DDRB_SMA12

23

56_0404_4P2R_5%

RP35

DDRB_SMA5

14

DDRB_SMA7

23

56_0404_4P2R_5%

RP38

DDRB_SMA1

14

DDRB_SMA3

23

56_0404_4P2R_5%

RP40

DDRB_SBS0

14

DDRB_SMA10

23

56_0404_4P2R_5%

RP42

DDRB_SCS#0

14

DDRB_SWE#

23

56_0404_4P2R_5%

RP99

DDRB_SMA11

14

DDRB_SMA8

23

56_0404_4P2R_5%

RP101

DDRB_SMA6

14

DDRB_SMA4

23

56_0404_4P2R_5%

RP105

DDRB_SBS1

14

DDRB_SRAS#

23

56_0404_4P2R_5%

RP107

DDRB_SCAS#

14

DDRB_SCS#1

23

56_0404_4P2R_5%

RP103

DDRB_SMA2

14

DDRB_SMA0

56_0404_4P2R_5%

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

2

23

+1.25VS

0.1U_0402_10V6K

C594

C263

C616

4.7U_1206_16V6K

C704

1

C163

2

0.1U_0402_10V6K

1

C279

2

0.1U_0402_10V6K

1

C746

2

0.1U_0402_10V6K

1

C622

2

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_1206_16V6K

1

2

+1.25VS

1

2

+1.25VS

1

2

+1.25VS

1

2

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*26

DDRB_CKE1 9,13
DDRB_CKE0 9,13

DDRB_SBS0 9,13

DDRB_SCS#0 9,13

DDRB_SWE# 9,13

DDRB_SBS1 9,13

DDRB_SRAS# 9,13

DDRB_SCAS# 9,13

DDRB_SCS#1 9,13

1

C111

2

0.1U_0402_10V6K

1

C294

2

0.1U_0402_10V6K

1

C628

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C655

2

Title

Size Document Number Rev

Custom

Date: Sheet of

1

DDRB_SDQ[0..63]9,13
DDRB_SDQS[0..7]9,13
DDRB_SMA[0..12]9,13
DDRB_SDM[0..7]9,13

1

C187

2

1

C313

2

1

C632

2

1

C716

2

0.1U_0402_10V6K

1

C202

2

0.1U_0402_10V6K

1

C322

2

0.1U_0402_10V6K

1

C671

2

1

C740

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C221

2

0.1U_0402_10V6K

1

C343

2

0.1U_0402_10V6K

1

C677

2

1

C348

2

1

C639

2

1

C608

2

1

C682

2

DDR Termination Resistors

LA-1911

1

DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]

0.2

14 57Friday, August 08, 2003

5

4

3

2

1

SEL0 SEL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot

0 0 100 66 14.3 14.3 100/200

0 MID REF REF REF REF REF

D D

0 1 200

66 14.3 100/200 48

1 0 133 66 14.3

1 1 166

66 14.3

14.3

14.3

14.3

100/200

100/2004848

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

CLK_ICH_14M24
CLK_14M_SIO34

C C

+3VS

12

R153
1K_0603_1%

B B

12

R145
2K_0603_1%

12

R152

2.49K_0603_1%

A A

12

R181
1K_0603_1%

CLKSEL0
CLKSEL1

12

R180
2K_0603_1%

12

R179

2.49K_0603_1%

R137 @0_0402_5%
R138 0_0402_5%12
R182 0_0402_5%12
R175 @0_0402_5%

12

12

MCH_CLKSEL0 7
MCH_CLKSEL1 7

Check SPEC (250mA,300 ohm)

CPU_CLKSEL0 5
CPU_CLKSEL1 5

+3VS

48

REF

R196 33_0402_5%
R197 33_0402_5%

+3VS

CLK_ICH_48M24

L16
BLM11A601S_0603

1 2

12

C277

@10P_0402_50V8K

C278

@10P_0402_50V8K

12

Place crystal within
500 mils of CK409

R214 1K_0402_5%
R139 1K_0402_5%1 2
R148 1K_0402_5%

12
12

12

X2

14.31818MHz_20P_1BX14318CC1A~L

1 2
1 2

CK409_PWRGD#40

ICH_SMB_CLK12,13,23
ICH_SMB_DATA12,13,23

R161 33_0402_5%

CLK_VDD_PLL

1

C230
10U_1206_6.3V7K

2

L19

1 2

BLM21A601SPT_0805

L17

1 2

BLM21A601SPT_0805

CLKREF1
CLKREF0

CLK_XTAL_IN

CLK_XTAL_OUT

SLP_S1#
STPPCI#
STPCPU#

CLK_VTT_PG#

CK_SCLK
CK_SDATA

CLK48M_OUT0

12

1 2

R164 475_0603_1%

1

C239

0.1U_0402_16V4Z

2

1

2

CLKSEL0
CLKSEL1

C232
10U_1206_6.3V7K

CLK_VDD_PLL

1
2

4

5

51
56

49
50

35

28
30

37

38

31

32

52

55

54

+3VS_CLK+3VS

U11

3

REF_0
REF_1

XTAL_IN

XTAL_OUT

SEL0
SEL1

PWRDWN#
PCI_STP#
CPU_STP#

VTT_PWRGD#

SCLK
SDATA

SRCLKN_100MHZ

SRCLKP_100MHZ

USB_48MHZ

DOT_48MHZ

IREF

VDD_PLL

VSS_PLL

101624

VDD_PCI

VDD_PCI

VDD_REF

VDD_3V66

CK409

VSS_REF

VSS_PCI

VSS_PCI

6

11

172125

34

36

VDD_48

VDD_SRC

48/66MHZ_OUT/3V66_4

66MHZ_OUT3/3V66_3
66MHZ_OUT2/3V66_2
66MHZ_OUT1/3V66_1
66MHZ_OUT0/3V66_0

VSS_3V66

VSS_48

VSS_SRC

33

39

Place near each pin
W>40 mil

1

C272

0.1U_0402_10V6K

2

424548

VSS_CPU

VDD_CPU

VDD_CPU

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1
CPUCLKT0

CPUCLKC0

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

VSS_IREF

ICS952623BG_TSSOP56

53

1

C273

0.1U_0402_10V6K

2

1

C210

0.1U_0402_10V6K

2

CLK_CPU2

47

CLK_CPU2#

46

CLK_CPU1

44

CLK_CPU1#

43

CLK_CPU0

41

CLK_CPU0#

40
29

CLK66M_OUT3

27
26

CLK66M_OUT1

23

CLK66M_OUT0

22

PCICLK_F2

9
8
7

PCICLK6

20

PCICLK5

19

PCICLK4

18

PCICLK3

15

PCICLK2

14

PCICLK1

13
12

1

C274

0.1U_0402_10V6K

2

1

C261

0.1U_0402_16V4Z

2

1 2

R155 33_0402_5%

1 2

R156 33_0402_5%

1 2

R157 33_0402_5%

1 2

R158 33_0402_5%

1 2

R159 33_0402_5%

1 2

R160 33_0402_5%

1 2

R191 33_0402_5%

1 2

R208 33_0402_5%

1 2

R202 33_0402_5%

1 2

R198 33_0402_5%

1 2

R207 33_0402_5%

1 2

R201 33_0402_5%

1 2

R206 33_0402_5%

1 2

R200 33_0402_5%

1 2

R205 33_0402_5%

1 2

R199 33_0402_5%

1 2

1 2

1 2

1 2

1 2

Trace wide=40 mils

1

C275

0.1U_0402_10V6K

2

R13049.9_0402_1%

R13149.9_0402_1%

R13249.9_0402_1%

R13349.9_0402_1%

R13449.9_0402_1%

1 2

R13549.9_0402_1%

1

C212

0.1U_0402_10V6K

2

1

C211

0.1U_0402_10V6K

2

The host clocks to
the Processor must be
165 mil longer than the
host clocks to the GMCH

CLK_HCLK

CLK_HCLK#
CLK_IT P

CLK_ITP#
CLK_BCLK

CLK_HCLK 7

CLK_HCLK# 7
CLK_IT P 5

CLK_ITP# 5
CLK_BCLK 4

Place near CK409

CLK_BCLK#

CLK_AGP_66M 16

CLK_MCH_66M 10
CLK_ICH_66M 23
CLK_PCI_ICH 23

CLK_PCI_MINI 29
CLK_PCI_CB 27
CLK_PCI_LPC 37
CLK_PCI_1394 30
CLK_PCI_LAN 26
CLK_PCI_SIO 34

CLK_BCLK# 4

1

C215

0.1U_0402_10V6K

2

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Clock Generator

LA-1911

0.2

15 57Friday, August 08, 2003

1

5

+3VS+3VS

Place close
to pin
D+ & D-

@2200P_0402_50V7K

1

C419

+3VS

D D

R591 @10K_0402_5%
R592 @10K_0402_5%

AGP_AD[0..31]10

AGP_SBA[0..7]10

AGP_C/BE#[0..3]10

AGP_ST[0..2]10

+3VS

C C

B B

R354
10K_0402_5%

1 2
1 2

R361 10K_0402_5%

0.1U_0402_10V6K

12

C434

Selection Table For W180

Modulation
Setting

NV_THERMDA

2

NV_THERMDC

I2CC_SCL

12

I2CC_SDA

12

12

C451

4.7U_0805_10V4Z

R405 220K_0402_5%
R387 220K_0402_5%

SST
Ratio

AGP_AD[0..31]

AGP_SBA[0..7]

AGP_C/BE#[0..3]

AGP_ST[0..2]

STP_AGP#
AGP_BUSY#

4.7U_0805_10V4Z

1 2
1 2

SS%

1

8

1.25%

3.75%

+SVDD

U27

X1/CLK

FS2

5

0
1

XTALOUTBUFF

+3VS

R319
1K_0402_5%

1 2
1 2

A A

R315
1K_0402_5%

U28

2

D+

3

D-

8

SCLK

7

SDATA

@ADM1032ARM_RM8

PCIRST#10,22,23,26,27,29,30,33,34,37

+SVDD

12

C461

PLACE COLSE TO VGA

6

Pin AJ5, AJ7,

VDD

5

CLKOUT

GND

3

R11

27

X2FS1

SPREAD_RATE

4

SS%

W180-01GT_SO8

VDD1

ALERT#

THERM#

GND

L30

1 2

FCM2012C-800_0805

12

C441

0.1U_0402_10V6K

AGP_AD_STBS0
AGP_AD_STBS1

Close VGA ball (AK29)
less than 250mils-->350mV

+AGP_VREF

1 2

22_0402_5%

R346
10K_0402_5%

1 2

1

NV_THERCT L#

6
4
5

PCIRST#

R601 10_0402_5%

+3VS

XTALSSIN

1 2

R350
@1K_0402_5%

@2.2K_0402_5%

@10P_0402_50V8K

1 2

1

2

12

R362

@0.1U_0402_16V4Z

C479

1 2

CLK_AGP_66M15

C569

0.1U_0402_10V6K

+3VS

+SVDD

4

12

R310
@2.2K_0402_5%

+3VS

1

C462

2

R369

1 2

@10_0402_5%

AGP_REQ#10
AGP_GNT#10

AGP_PAR10

AGP_STOP#10

AGP_DEVSEL#10

AGP_TRDY#10

AGP_IRDY#10

AGP_FRAME#10

PCI_PIRQA#23,27

AGP_WBF#10

AGP_RBF#10
AGP_DBIHI10
AGP_DBILO10

AGP_SB_STBF10

AGP_SB_STBS10
AGP_AD_STBF010
AGP_AD_STBS010
AGP_AD_STBF110
AGP_AD_STBS110

R377 10K_0402_5%

CRMA22

LUMA22

COMPS22

1 2

R299 63.4_0603_1%

R318 10K_0402_5%

12

4

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

CLK_AGP_66M
AGP_REQ#

AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
PCI_PIRQA#

AGP_WBF#
AGP_RBF#

AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF0
AGP_AD_STBS0
AGP_AD_STBF1
AGP_AD_STBS1

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2

+AGP_REF

12

AGP_BUSY#
STP_AGP#

CRMA
LUMA

COMPS
DACB_HSYNC
DACB_VSYNC
DACB_RSET

XTALIN
XTALOUT

XTALSSIN
XTALOUTBUFF
NV_THERMDA
NV_THERMDC

PROPRIETARY NOTE

DAC2

SSC

CLK

3

3

FPBCLKOUT#

FPBCLKOUT

DVOHSYNC
DVOVSYNC

DVOCLKOUT

DVOCLKOUT#

ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDS

IFPATXDO#

IFPATXD1#
IFPATXD2#
IFPATXD3#

IFPBTXD4#
IFPBTXD5#
IFPBTXD6#
IFPBTXD7#

DACA_RED

DACA_GREEN

DACA_BLUE
DACA_HSYNC
DACA_VSYNC

DACA_RSET

DAC1

SWAPRDY_A
DACA_IDUMP

IFPCTXD0#
IFPCTXD1#
IFPCTXD2#

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

ROMA14
ROMA15

ROMCS#

VIPPCLK
VIPHCTL
VIPHCLK

VIPHAD0
VIPHAD1

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8

DVOD9
DVOD10
DVOD11

DVODE

I2CC_SCL

I2CC_SDA

BUFRST#

DVOCLKIN

STRAP0
STRAP1
STRAP2
STRAP3

IFPATXDO

IFPATXD1
IFPATXD2
IFPATXD3

IFPATXC#

IFPATXC
IFPBTXD4
IFPBTXD5
IFPBTXD6
IFPBTXD7

IFPBTXC#

IFPBTXC

I2CA_SCL

I2CA_SDA

IFPCTXD0
IFPCTXD1
IFPCTXD2

IFPCTXC#

IFPCTXC

VGA_GPIO0 SPREAD_RATE

G5
F4
G4
H5
H4
J4
J5
J6
K4
K6

M2
M3

R2
R1
AF2

L4
M4
M5

P3
P2

J3
J2
K2
K1
L3
L2
N2
N1

AG2
AH1
AG3
AJ1
AH2
AK1
AJ3
AK3
AH4
AK4
AJ4
AH5

AD5
AD6
AE4
AJ2
AK2
AG6
AG7
B1
AG1

G1
G2
F2
F3

T4
U4
AA1
Y2
W3
V3
V4
U5
V1
W2
V5
W4
AB2
AB3
W6
Y6
AC2
AC3
Y3
AA2

AK10
AJ10
AJ9

DACA_HSYNC

AH9

DACA_VSYNC

AJ8
AG8
AG5

AF7
AF9
AG10

T2
R3
T3
U2
V2
U3
P4
P5

ENBKL
ENVDD

VAG_GPIO6
POWER_SEL
NV_THERCT L#

TXOUT 0­TXOUT0+
TXOUT 1­TXOUT1+
TXOUT 2­TXOUT2+

TXCLK­TXCLK+
TZOUT0­TZOUT0+
TZOUT1­TZOUT1+
TZOUT2­TZOUT2+

TZCLK­TZCLK+

DACA_RSET

DDC_CLK
DDC_DATA

ROMA14
ROMA15

VIPHCT L

VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

DVOD2
DVOD3

DVOD8
DVOD9

DVO_HSYNC

I2CC_SCL
I2CC_SDA

STRAP0
STRAP1
STRAP2
STRAP3

TXOUT 3­TXOUT3+

TZOUT3­TZOUT3+

R
G
B

R351 10K_0402_5%

SWAPRDY_A
NV31,NV34 use.
NV18 not use.

12

R363 0_0402_5%

ENVDD 22

R326 10K_0402_5%

TXOUT 0- 22
TXOUT0+ 22
TXOUT 1- 22
TXOUT1+ 22
TXOUT 2- 22
TXOUT2+ 22
TXOUT 3- 22
TXOUT3+ 22
TXCLK- 22
TXCLK+ 22
TZOUT0- 22
TZOUT0+ 22
TZOUT1- 22
TZOUT1+ 22
TZOUT2- 22
TZOUT2+ 22
TZOUT3- 22
TZOUT3+ 22
TZCLK- 22
TZCLK+ 22

R 22
G 22
B 22
DACA_HSYNC 22
DACA_VSYNC 22

1 2

R370 130_0603_1%

DDC_CLK 22
DDC_DATA 22

12

U1A

AJ28

AD0

AK28

AD1

AH27

AD2

AK27

AD3

AJ27

AD4

AH26

AD5

AJ26

AD6

AH25

AD7

AH23

AD8

AJ23

AD9

AH22

AD10

AJ22

AD11

AJ21

AD12

AK21

AD13

AH20

AD14

AJ20

AD15

AG26

AD16

AE24

AD17

AG25

AD18

AG24

AD19

AF24

AD20

AG23

AD21

AE22

AD22

AF22

AD23

AE21

AD24

AG20

AD25

AG19

AD26

AF19

AD27

AE19

AD28

AF18

AD29

AG18

AD30

AE18

AD31

AJ24

C/BE#0

AH19

C/BE#1

AF25

C/BE#2

AG22

C/BE#3

AG12

PCICLK

AF15

PCIRST#

AF13

PCIREQ#

AE15

PCIGNT#

AK18

PCIPAR

AH17

PCISTOP#

AJ16

PCIDEVSEL#

AJ17

PCITRDY#

AG16

PCIIRDY#

AK16

PCIFRAME#

AG15

PCIINTA#

AE10

NC

AG17

AGPWBF#

AG14

AGPRBF#

AJ18

AGPPIPE/ DBI_HI

AJ19

NC/ DBI_LO

AK13

AGPSB_STB/ ADSTBF

AJ13

AGPSB_STB#/ ADSTBS

AK24

AGPADSTB0/ ADSTBF0

AJ25

AGPADSTB0#/ADSTBS0

AG21

AGPADSTB1/ ADSTBF1

AF21

AGPADSTB1#/ADSTBS1

AJ11

AGPSBA0

AH11

AGPSBA1

AJ12

AGPSBA2

AH12

AGPSBA3

AJ14

AGPSBA4

AH14

AGPSBA5

AJ15

AGPSBA6

AH15

AGPSBA7

AG13

AGPST0

AE16

AGPST1

AE13

AGPST2

AK29

AGPVREF

AF16

NC/AGPMBDET#

AF12

AGP_BUSY#

AG11

STP_AGP#

AE2

DACB_RED/CHROMA

AD2

DACB_GREEN/LUMA

AD1

DACB_BLUE/COMPOSITE

AF3

DACB_HSYNC

AE3

DACB_VSYNC

AD3

DACB_RSET

AE7

I2CB_SCL

AF6

I2CB_SDA

AD4

SWAPRDY_B

Y5

STEREO

AC4

DACB_IDUMP

AJ6

XTALIN

AH6

XTALOUT

AJ7

XTALSSIN

AJ5

XTALOUTBUFF

H2

THERMDA

H3

THERMDC

C2

JTAG[0]

C1

JTAG[1]

D1

JTAG[2]

E2

JTAG[3]

D2

JTAG[4]

NV34M_EPBGA701

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

nVIDIA
NV31/34

PCI/AGP

AGP4X/8X

2

12

R339 10K_0402_5%

1 2

R331 10K_0402_5%

12

R308

10K_0402_5%

+3VS

(SUS_STAT#)

12

PCI_AD_SWAP: 0-RVSERSED 1-NORMAL

1

SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS

2

R311 10K_0402_5%12

RAM_CFG[3:0]

3

Low

High

Low

High

Low

High

Low

High

Low

High

2

(1101 = 4Mx32 DDR, DQS per byte)

R301 @10K_0402_5%12

NV18M

0

R300 @10K_0402_5%12

NV31M:NV34M

4

R323 @10K_0402_5%12

NV18M

1

R306 10K_0402_5%12

NV31M:NV34M

5

R353 @10K_0402_5%

2

R371 @10K_0402_5%

3

CRYSTAL: (10)-27MHz

6

R302 10K_0402_5%

0
1

TVMODE: (01)-NTSC

7

0

R305 10K_0402_5%

1

AGP8X/4X: (0)-8X / (1)-4X

8

R317 10K_0402_5%

AGP_SIDEBAND: (0)-ENABLE

9

R314 10K_0402_5%

AGP_FASTWRITE: (0)-ENABLE

10

R321 10K_0402_5%

PCI_DEVID[3:0]

11

R313 10K_0402_5%

0

R312 10K_0402_5%

1

R303 @10K_0402_5%

2

R333 10K_0402_5%

3

BUS_TYPE: (1)-AGP

12

ROM TYPE: (00)-PARALLEL

R309 10K_0402_5%

0

R304 10K_0402_5%

1

1

ENBKL 37

POWER_SEL 50

12
12

12

12

12

12

12

+3VS

12
12

12

12

12

12

12

1 2

R356 10K_0402_5%

+3VS

STRAP0

STRAP1

STRAP2
DVOD2

STRAP3
DVOD3

DACA_VSYNC
DACA_HSYNC

VIPD2
VIPD6

DACB_VSYNC
DACB_HSYNC

DVOD9

VIPD7

DVOD8

1010-NV31M

R292 10K_0402_5%12

R291 @10K_0402_5%12
R285 10K_0402_5%12

R290 @10K_0402_5%12
R286 @10K_0402_5%12

R360 10K_0402_5%
R367 10K_0402_5%

R297 10K_0402_5%

R284 10K_0402_5%

R322 @10K_0402_5%

R296 @10K_0402_5%

R330 @10K_0402_5%

0100-NV34M

1101-NV33M 0101-NV34M-U

12
12
12
12

12
12

XTALIN

1

C27
22P_0402_50V8J

2

Title

Size Document Number Rev

VIPD4
VIPD5
VIPD3

DVO_HSYNC

VIPHCT L

ROMA14
ROMA15

Y1

**

4

GNDINOUT

1

27MHz_16PF_6P27000019

1 2

R8 @2M_0402_5%

Compal Electronics, Inc.
nVIDIA NV34M (AGP BUS)

R295 @10K_0402_5%
R294 @10K_0402_5%
R293 10K_0402_5%
R341 @10K_0402_5%

R352 10K_0402_5%12

R283 @10K_0402_5%
R282 @10K_0402_5%

XTALOUT

3
2

GND

C9

22P_0402_50V8J

12
12
12
12

12
12

1

2

LA-1911

Date: Sheet of

16 57Friday, August 08, 2003

1

+3VS

0.2

5

4

3

2

1

NDQMA[0..7]20

NDQSA[0..7]20

D D

C C

B B

NMAA[0..11]20
NMDA[0..63]20

NDQMA[0..7]
NDQSA[0..7]
NMAA[0..11]
NMDA[0..63]

NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63

U1B

N25

FBAD0

N27

FBAD1

N26

FBAD2

M25

FBAD3

K26

FBAD4

K27

FBAD5

J27

FBAD6

H27

FBAD7

N29

FBAD8

M29

FBAD9

M28

FBAD10

L29

FBAD11

J29

FBAD12

J28

FBAD13

H29

FBAD14

G30

FBAD15

K25

FBAD16

J26

FBAD17

J25

FBAD18

G26

FBAD19

F28

FBAD20

F26

FBAD21

E27

FBAD22

D27

FBAD23

H28

FBAD24

G29

FBAD25

F29

FBAD26

E29

FBAD27

C30

FBAD28

C29

FBAD29

B30

FBAD30

A30

FBAD31

AJ29

FBAD32

AJ30

FBAD33

AH29

FBAD34

AH30

FBAD35

AF29

FBAD36

AE29

FBAD37

AD29

FBAD38

AC28

FBAD39

AG28

FBAD40

AF27

FBAD41

AE26

FBAD42

AE28

FBAD43

AD25

FBAD44

AB25

FBAD45

AB26

FBAD46

AA25

FBAD47

AD30

FBAD48

AC29

FBAD49

AB28

FBAD50

AB29

FBAD51

Y29

FBAD52

W28

FBAD53

W29

FBAD54

V29

FBAD55

AC27

FBAD56

AB27

FBAD57

AA27

FBAD58

AA26

FBAD59

W25

FBAD60

V26

FBAD61

V27

FBAD62

V25

FBAD63

NV34M_EPBGA701

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8

FBAA9
FBAA10
FBAA11
FBAA12

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

FBARAS#

MEMORY

INTERFACE A

FBACAS#

FBAWE#
FBACS0#
FBACS1#

FBACKE

FBACLK0

FBACLK0#

FBACLK1

FBACLK1#

FBABA0
FBABA1

FB_VREF

NDQMB[0..7]21

NDQSB[0..7]21

NMAB[0..11]21

NMDB[0..63]21

NMAA0

V30

NMAA1

U28

NMAA2

U29

NMAA3

T28

NMAA4

T29

NMAA5

T27

NMAA6

T30

NMAA7

T26

NMAA8

T25

NMAA9

R27

NMAA10

R25

NMAA11

R30
U24

L27
K29
G25
E28
AF28
AD27
AA30
Y27

M27
K30
G27
D30
AG30
AD26
AA29
W27

P28
P29
R28
U27
P27
N30
U21

V21
N21

P21

R26
R29

C28

NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7

NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

NMCKEA
NMCLKA0

NMCLKA0#
NMCLKA1 NMCLKB1#

NMCLKA1#

NMA_BA0
NMA_BA1

A_REF

(10 mil)

NMRASA# 20
NMCASA# 20
NMWEA# 20
NMCSA0# 20

NMCKEA 20

NMA_BA0 20
NMA_BA1 20

1

C563

0.1U_0402_10V6K

2

+2.5VS

12

12

12

R390
@120_0402_5%

12

R389
@120_0402_5%

R396
1K_0402_1%

R388
1K_0402_1%

NDQMB[0..7]
NDQSB[0..7]
NMAB[0..11]
NMDB[0..63]

NMCLKA0 20

NMCLKA0# 20
NMCLKA1 20

NMCLKA1# 20

NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28NDQSA0
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63

U1C

F13

FBCD0

D13

FBCD1

E13

FBCD2

F12

FBCD3

E10

FBCD4

D10

FBCD5

D9

FBCD6

D8

FBCD7

B13

FBCD8

B12

FBCD9

C12

FBCD10

B11

FBCD11

B9

FBCD12

C9

FBCD13

B8

FBCD14

A7

FBCD15

F10

FBCD16

E9

FBCD17

F9

FBCD18

F7

FBCD19

C6

FBCD20

E6

FBCD21

D5

FBCD22

C4

FBCD23

C8

FBCD24

B7

FBCD25

B6

FBCD26

B5

FBCD27

A3

FBCD28

B3

FBCD29

A2

FBCD30

B2

FBCD31

B29

FBCD32

A29

FBCD33

B28

FBCD34

A28

FBCD35

B26

FBCD36

B25

FBCD37

B24

FBCD38

C23

FBCD39

E26

FBCD40

D26

FBCD41

E25

FBCD42

C25

FBCD43

E24

FBCD44

F22

FBCD45

E22

FBCD46

F21

FBCD47

A24

FBCD48

B23

FBCD49

C22

FBCD50

B22

FBCD51

B20

FBCD52

C19

FBCD53

B19

FBCD54

B18

FBCD55

D23

FBCD56

D22

FBCD57

D21

FBCD58

E21

FBCD59

F19

FBCD60

E18

FBCD61

D18

FBCD62

F18

FBCD63

NV34M_EPBGA701

FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8

FBCA9
FBCA10
FBCA11
FBCA12

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

FBCRAS#
FBCCAS#

MEMORY INTERFACE

B

FBCWE#
FBCCS0#
FBCCS1#

FBCCKE

FBCCLK0

FBCCLK0#

FBCCLK1

FBCCLK1#

FBCBA0
FBCBA1

C17
B17
C16
B16
D16
A16
E16
F16
D15
F15
A15
G17

D11
B10
D7
C5
C26
F24
B21
D20

D12
A10
E7
A4
A27
D24
A21
D19

C14
B14
C15
D17
D14
A13
K18

K17

K13
K14

E15
B15

NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11

NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7

NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

NMCKEB
NMCLKB0

NMCLKB0#

NMCLKB1

NMB_BA0
NMB_BA1

NMAB0

A18

NMRASB# 21
NMCASB# 21
NMWEB# 21
NMCSB0# 21

NMCKEB 21

NMB_BA0 21
NMB_BA1 21

12

R381
@120_0402_5%

12

R372
@120_0402_5%

NMCLKB0 21

NMCLKB0# 21

NMCLKB1 21

NMCLKB1# 21

1 2

R417 10K_0402_5%

1 2

A A

R368 10K_0402_5%

NMCKEA

NMCKEB

32M VRAM-->Channel A only-->2 sets
64M VRAM-->Channel A and B-->4 sets

5

4

Title

Size Document Number Rev

3

2

Date: Sheet of

Compal Electronics, Inc.

nVIDIA NV34M (DDR)

LA-1911

17 57Friday, August 08, 2003

1

0.2

5

4

3

2

1

U1D

AA4
V6

U10
V10

T5
T6

Y4
W5

AA3
R4

P10
N10

R5
R6

L6
L7
M7

P6
P7

AD8
AD9
AE8

AB6
AB7
AF4

AE5
G24

AB4
AB5

AG9
AH8

F5
E4
D3
E3

C27
AK7

B4
B27
C11
C20
D6
D25
D29
E12
E19
F27
L28
M26
N5
W7
W26
Y7

IFPABVPROB E
IFPABRSET

+IFPABPLLVDD

+IFPABIOVDD

IFPCVPROBE

+IFPCPLLVDD

+IFPCIOVDD

VIPCAL_1
VIPCAL_2

DVOCAL_1
DVOCAL_2

+FB_DLLVDD
+PLLVDD

NV31 use only.
NV18,NV33,NV34 not use.

R335 10K_0402_5%1 2
R404 10K_0402_5%1 2

+DACA/BVDD
DACAVREF

DACBVREF

12

12

AD11

AGPVDDQ

AD14

AGPVDDQ

AD17

AGPVDDQ

AD20

AGPVDDQ

AD23

AGPVDDQ

AE11

AGPVDDQ

AE14

AGPVDDQ

AE17

AGPVDDQ

AE20

AGPVDDQ

AE23

AGPVDDQ

L11

VDD

L13

VDD

L14

VDD

L17

VDD

L18

VDD

L20

VDD

N6

VDD

N11

VDD

N20

VDD

P11

VDD

P20

VDD

U11

VDD

U20

VDD

V11

VDD

V20

VDD

Y11

VDD

Y13

VDD

Y14

VDD

Y17

VDD

Y18

VDD

Y20

VDD

AA17

VDD

AA18

VDD

G14

VDD33

H6

VDD33

H7

VDD33

M6

VDD33

P24

VDD33

U6

VDD33

U7

VDD33

AC6

VDD33

AC7

VDD33

AD12

VDD33

AD15

VDD33

AD19

VDD33

AD22

VDD33

AD16

VDD33

N4

VD50CLAMP0

AE9

VD50CLAMP1

AA13

AGPCALPD_VDDQ

AA14

AGPCALPU_GND

AE12

AGP_PLLVDD

F8

FBVDDQ

F11

FBVDDQ

F14

FBVDDQ

F17

FBVDDQ

F20

FBVDDQ

F23

FBVDDQ

G8

FBVDDQ

G11

FBVDDQ

G20

FBVDDQ

G23

FBVDDQ

H24

FBVDDQ

H25

FBVDDQ

L24

FBVDDQ

L25

FBVDDQ

P25

FBVDDQ

U25

FBVDDQ

Y24

FBVDDQ

Y25

FBVDDQ

AC24

FBVDDQ

AC25

FBVDDQ

AA6

NC

AC5

NC

AF10

NC

AG29

NC

AE27

NC

G9

NC

Y28

NC

NV34M_EPBGA701

IFPABVPROBE

IFPABRSET

IFPABPLLVDD
IFPABPLLGND

IFPAIOVDD
IFPAIOGND

IFPBIOVDD
IFPBIOGND

IFPCVPROBE

IFPCRSET

IFPCPLLVDD
IFPCPLLGND

IFPCIOVDD
IFPCIOGND

VIPVDDQ
VIPVDDQ
VIPVDDQ

VIPCAL_PD_VDDQ

VIPCAL_PU_GND

DVOVDDQ
DVOVDDQ
DVOVDDQ

DVOCAL_PD_VDDQ

DVOCAL_PU_GND

DVO_VREF

TESTMODE

TESTMECLK

I/O

POWER

DACB_VDD

DACB_VREF

DACA_VDD

DACA_VREF

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

FBCAL_CLK_GND

FB_DLLVDD

PLLVDD

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+1.5VS

D D

+VGA_CORE

R614

0_0402_5%

C C

+3VS

R615

0_0402_5%

+1.5VS

R373 49.9_0402_1%

R378 49.9_0402_1%

B B

FBCAL_PD_VDDQ
NV31,NV33,NV34 use.
NV18 not use.

FBCAL_PUK_GND
NV31,NV33,NV34 use.
NV18 not use.

FBCAL_TERM_GND
NV31 use (tie to GND).
NV18,NV33,NV34 not use.

FBCAL_CLK_GND
NV31 use.
NV18,NV33,NV34 not use.

A A

12
12

+5VS

AGPCALPD_VDDQ
AGPCALPU_GND
+AGP_PLLVDD

+2.5VS

C424 0.1U_0402_10V6K

1 2

1 2

R324 1K_0402_5%

C423 0.1U_0402_10V6K

1 2

1 2

R320 1K_0402_5%

1 2

R364 10K_0402_5%

1 2

R332 10K_0402_5%

+VIP/DVOVDDQ

NV31 use only.

R347 @49.9_0402_1%12
R334 @49.9_0402_1%

1 2

R349 @49.9_0402_1%1 2
R348 @49.9_0402_1%

1 2

TESTMECLK
NV31,NV33,NV34 use.
NV18 not use.

1 2

C443 0.01U_0402_16V7K

1 2

C36 0.01U_0402_16V7K

FBCAL_TERM_GND & FBCAL_CLK_GND
NV31 use.
NV18,NV33,NV34 not use.

NV18,NV33,NV34 not use.

+DVO_VREF

+2.5VS

R28949.9_0402_1% 12
R28849.9_0402_1%

12

R287@0_0402_5% 12
R325@549_0402_1%

12

1

C556
4700P_0402_25V7K

2

+1.5VS

1

C476

4.7U_0805_10V4Z

2

1

C429

0.1U_0402_10V6K

2

1

C427
470P_0402_50V7K

2

L40

1 2

KC FBM-L11-201209-221LMAT_0805

1

C555
470P_0402_50V7K

2

+FB_DLLVDD
NV31,NV33,NV34 use.
NV18 not use.

1

C482

0.1U_0402_16V4Z

2

+VIP/DVOVDDQ

12

12

1

C422
4700P_0402_25V7K

2

+3VS

1

C460

0.022U_0402_16V7K

2

R340
1K_0402_1%

R316
1K_0402_1%

L31

KC FBM-L11-201209-221LMAT_0805

1

C449

4.7U_0805_10V4Z

2

12

1

C541

0.022U_0402_16V7K

2

+3VS

+AGP_PLLVDD+FB_DLLVDD

C41

4.7U_0805_10V4Z

+DACA/BVDD

1

C32

4.7U_0805_10V4Z

2

+PLLVDD

C7

1

4.7U_0805_10V4Z

2

+IFPABPLLVDD

1

C465
470P_0402_50V7K

2

+VIP/DVOVDDQ+IFPABIOVDD

1

C454
470P_0402_50V7K

2

1

C485
4700P_0402_25V7K

2

1

C507

0.022U_0402_16V7K

2

1

C428
4700P_0402_25V7K

2

1

C450

4700P_0402_25V7K

2

1

C464
4700P_0402_25V7K

2

1

C430
4700P_0402_25V7K

2

+5VS

1

C452

0.1U_0402_10V6K

2

KC FBM-L11-201209-221LMAT_0805

1

C457
470P_0402_50V7K

2

1

C448

470P_0402_50V7K

2

1

C490

4.7U_0805_10V4Z

2

1

2

L34

1 2

KC FBM-L11-201209-221LMAT_0805

1

C467
470P_0402_50V7K

2

+AGP_PLLVDD
NV31,NV33,NV34 use.
NV18 not use.

1

2

L4

1 2

L24KC FBM-L11-201209-221LMAT_0805

1 2

L37

KC FBM-L11-201209-221LMAT_0805

L25

1 2

KC FBM-L11-201209-221LMAT_0805

C493

4.7U_0805_10V4Z

+3VS

C436

0.1U_0402_10V6K

+3VS

+3VS

C414

1

4.7U_0805_10V4Z

2

+3VS

12

+3VS

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

nVIDIA NV34M POWER)

LA-1911

18 57Friday, August 08, 2003

1

0.2