Compal LA-1861, TravelMate 540 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Intel portability uFCBGA/uFCPGA
with ATI-RC300M+SB200 core logic

3 3

4 4

A

B

2003-07-10

REV:0.4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Docu ment Number Re v

D

Date: Sheet

Compal E l e c t r onics, Inc.
SCHEMATIC, M/B LA-1861

401257

星期三 七月

30, 2003

0E

of

161,

E

A

B

C

D

E

Compal confidential

File Name : LA-1861

1 1

W/EXT VGA CHIP

W/EXT VGA CHIP

VGA DDR x2 CHB

2 2

IEEE 1394
VIA -VT6301

3 3

page 33

IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)

RTC CKT.

page 25

Mini PCI
socket

IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)

CRT & TV -O UT Conn.

LCD C onn

ATI-M9+X/M10C

page 16,17,18,19,20

VGA DDR x2 CHA

page 22

IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)

RTL 8100C/8110S

page 34

page 24

page 24

page 21

3.3V 33 MHz

LAN

page 32

RJ45 CONN

page 32

Power OK CKT.

page 42

Power On/Off CKT.

page 39

DC/DC Interface CKT.

4 4

page 44

Power Circuit DC/DC

page 45,46,47,48,49,50,51,52,53,54

A

Fan Cont rol

page 7

W/O EXT VGA CHIP
W/O EXT VGA CHIP

AGP BUS

USB conn x4

page 37

VIA_ VT 6202
USB2.0

IDSEL:AD27
(PIRQA/B/C#,GNT#4,REQ#4)

page 44

PCI BUS

IDSEL:AD20
(PIRQC/D#,GNT#2,REQ#2)

CardBus Controller

ENE C B1420

Slot 1

page 31

page 30

Slot 0

page 31

EC NS8 7 591L

page 39

EC I/O Buffer

page 41

B

Intel Northwood

uFCBGA-479/uFC PGA-478 CP U

page 4,5,6

PSB

533MHz

ATI-RC300M

VGA M9 Embeded

718 pin u-BGA

page 8,9,10,11,12,13

A-Link

ATI-SB200

BGA 457 pin

page 25,26,27,28

LPC BUS

page 40

Int.KBDTouch Pad

BIOS

page 39

page 41

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PARALLEL

page 43

Serial

page 38

C

Therm al Sensor
ADM1 032AR

H_D#(0..63)H_A#( 3..31)

Memory BUS(DDR)

2.5V DDR- 200/266

USB Interface

AC-LINK

Primary IDE

ATA-100

Secondary IDE

ATA-100 page 29

SMsC L PC 47N227

Super I/O

page 38

FDD

page 38

Clock Generator

page 7

DDR-SO-DIMM X2

BANK 0 , 1, 2, 3

Blu etooth

Card Reader

USB conn x4

Audio Codec
ALC202A

MDC CONN

Mini-PCI solt

HDD
Connector

CDROM
Connector

D

ICS 951402

page 23

page 14

page 37

page 37

page 37

page 35

page 37

page 34

page 29

SPR USB X 2

page 43

AMP

page 36

RJ11 CONN

page 37

SPR CONN.

*RJ45 CONN
*PS2 x2 CONN
*CRT CONN
*LINE IN JACK
*LINE OUT JACK
*DC JACK
*TVOUT CONN
*PRINTER PORT
*COM PORT
*USB CONN x1

page 43

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

of

261,

E

0E

A

Symbol Note :

Voltage Rails

Power Plane

VIN
B+
+CPU_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3VS OFF
+3V 3.3V system power rail for SB,LAN,CardReader and HUB. ON ON OFF

+5VS
+12VALW
+12VS
RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit.

The voltage for Processor VID select

1.25V switched power rail for DDR Vtt

1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.

1.8V switched power rail for ATI-RS300M/RC300M NB.

2.5V always on power rail

2.5V system power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V switched power rail OFF
12V always on power rail
12Vswitched power rail on power rail
RTC power

S0-S1

N/A
N/A
ON
ON

ON
ON

ON

ON
ON
ON
ON

ON
ON
ON
ON
ON

S3

N/AONN/A
N/A
OFF
OFF
OFF

OFF
OFF

OFF
ONON
ON
OFF
ON

ON
OFF
ON
OFF
ON

S5

N/A
OFF
OFF
OFF

OFF
OFF
ON*
OFF
OFF
ON*
OFF

ON*+5VALW 5V always on power rail

ON*
OFF
ON

@ : means just reserve , no build
M9@ : means just build when no exter nal AG P VGA chip build in .
M9+/M10@ : mean s j ust b u i l d when M9+XC or M10 build in
M9+@ : mean s j ust build wh e n M9+X C chip build in .
M10@ : means just build when M 1 0 c h i p build in .
NSPR@ : m e a ns jus t build when n o SPR build in .
SPR@ : mea ns ju st b u ild when SP R build in .
8100S@ : means just build when 8100S build in .
1394@ : means just build when 1394 b uild in .
MDC@ : me a n s just build when MDC build in .

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

Exter n al PCI Devices

1 1

NB Internal VGA
AGP BUS
SOUTHBRI DGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN
VIA 6202 USB20 AD27 4 A/ B/ C

IDSEL # PIRQ

N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24 (INT.)
AD16
AD19
AD20
AD18

REQ/GNT #DEVICE

N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3

A
A

N/A

D
B
A
C
A
D
A/B
C

I2C / SMBUS ADDRESSING

: me a ns Digi t a l Ground

: me a ns Ana l og Ground

100K +/- 5%Ra

Rb V min
0
1
2
3
4
5
6

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7NC

Board ID

0
1
2
3
4
5
6
7

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

PCB Revision

0.1

0.2

0.3

0.4

max

DEVICE HEX ADDRESS

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERA TOR (EXT.)

A2
D2

1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

of

361,

0E

5

4

+CPU_CORE

3

2

1

D D

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

C C

H_REQ#[0..4]<8>

H_ADS#<8>

R110
@62_0402_5%

+CPU_CORE
+CPU_CORE

B B

R416

1 2

1 2

H_BR0#<8>
H_BPRI#<8>
H_BNR#<8>

H_LOCK#<8>

CK_BCLK<23>

CK_BCLK#<23>

H_HIT#<8>

H_HITM#<8>

H_DEFER#<8>

200_0402_5%

CK_BCLK#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#

CK_BCLK

AF22
AF23

A10

A12

A14

A16

A18

A20

AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19

C10

C12

C14

C16

C18

C20

D11

D13

D15

D17

D19

D9

VCC_65C8VCC_66

VCC_84

VCC_85

F9

F11

VCC_67

VCC_68

VCC_79E8VCC_80

E20

VCC_69

VCC_78

E18

VCC_70

VCC_77

E16

E10

VCC_71D7VCC_72

VCC_75

VCC_76

E12

E14

VCC_73

VCC_74

D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

H_D#0H_A#3

B21

D#0

H_D#1

B22

D#1

H_D#2

A23

D#2

H_D#3

A25

D#3

H_D#4

C21

D#4

H_D#5

D22

D#5

H_D#6

B24

D#6

H_D#7

C23

D#7

H_D#8

C24

D#8

H_D#9

B25

D#9

H_D#10

G22

H_D#11

H21

H_D#12

C26

H_D#13

D23

H_D#14

J21

H_D#15

D25

H_D#16

H22

H_D#17

E24

H_D#18

G23

H_D#19

F23

H_D#20

F24

H_D#21

E25

H_D#22

F26

H_D#23

D26

H_D#24

L21

H_D#25

G26

H_D#26

H24

H_D#27

M21

H_D#28

L22

H_D#29

J24

H_D#30

K23

H_D#31

H25

H_D#32

M23

H_D#33

N22

H_D#34

P21

H_D#35

M24

H_D#36

N23

H_D#37

M26

H_D#38

N26

H_D#39

N25

H_D#40

R21

H_D#41

P24

H_D#42

R25

H_D#43

R24

H_D#44

T26

H_D#45

T25

H_D#46

T22

H_D#47

T23

H_D#48

U26

H_D#49

U24

H_D#50

U23

H_D#51

V25

H_D#52

U21

H_D#53

V22

H_D#54

V24

H_D#55

W26

H_D#56

Y26

H_D#57

W25

H_D#58

Y23

H_D#59

Y24

H_D#60

Y21

H_D#61

AA25

H_D#62

AA22

H_D#63

AA24

H_D#[0..63] <8>H_A#[3..31]<8>

JP25A

VCC_0

VCC_1

VCC_2

VCC_3

VCC_4

VCC_5

VCC_6A8VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56B7VCC_57B9VCC_58

VCC_59

VCC_61

VCC_62

VCC_63

K2

A#3

K4

A#4

L6

A#5

K1

A#6

L3

A#7

M6

A#8

L2

A#9

M3

A#10

M4

A#11

N1

A#12

M1

A#13

N2

A#14

N4

A#15

N5

A#16

T1

A#17

R2

A#18

P3

A#19

P4

A#20

R3

A#21

T2

A#22

U1

A#23

P6

A#24

U3

A#25

T4

A#26

V2

A#27

R6

A#28

W1

A#29

T5

A#30

U4

A#31

V3

A#32

W2

A#33

Y1

A#34

AB1

A#35

J1

REQ#0

K5

REQ#1

J4

REQ#2

J3

REQ#3

H3

REQ#4

G1

ADS#

AC1

AP#0

V5

AP#1

AA3

BINIT#

AC3

IERR#

H6

BR0#

D2

BPRI#

G2

BNR#

G4

LOCK#

BCLK0
BCLK1

F3

HIT#

E3

HITM#

E2

DEFER#

VSS_0H1VSS_1H4VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12A3VSS_13A9VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

A11

A13

A15

A17

A19

A21

A24

H23

H26

A26

AA1

AA4

AA11

AA13

AA15

AA17

AA19

AA23

AA26

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

AA7

AA9

AB10

AB12

AB14

AB16

Prescott

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

AB3

AB6

AB8

AB18

AB20

AB21

AB24

AC11

AC13

AC15

AC17

AC19

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

AC2

AC5

AC7

AC9

AC22

AC25

AD10

AD12

AD14

AD16

AD18

AD21

AD23

VCC_64

BOOTSELECT

VSS_54

VSS_55

VCC_81

VCC_82

VCC_83

F13

F15

F17

F19

AD1

AD4

AD8

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

A6 TESTHI11 GHIPull-up 200ohm

TESTHI11

B6 FERR# FERR#/PBE# Pull-up 62ohm

AA20 ITPCLKOUT0 Pull-up56ohm

AB22 ITPCLKOUT1 Pull-up 56ohm

AD2 NC VIDPWRGD Pull-up 2.43K ohm

AD3 NC float VID5 Pull-up1Kohm to

A A

AF3 NC float VCCVIDLB Connect to +VCCVID
AD20 VCCA VCCIOPLLConnect to CPU

AE23

VCCIOPLL VCCA

AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/

TESTHI12 TESTHI12AD25 DPSLP

Commend Commend

to +VCC_CORE
Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCC_CORE
float

Filter
Connect to CPU

Filter
Connect to GND CPU determine

Pull-up 200ohm
to +VCC_CORE

5

Prescott
Pin name

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

TESTHI6 Pull-up 62ohm

TESTHI7 Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCCVID

+3VRUN & connect
to PWRIC

Connect to CPU

Filter

Connect to CPU

Filter

COMPAT#

float

Pull-up 62ohm
to +VCC_CORE

Northwood MT
Pin name

FERR#

ITPCLKOUT0

ITPCLKOUT1

NC

NC

NC
VCCA

VCCIOPLL

VSS
VSS

Commend

Connect to PLD
CPUPREF through
0ohm

Pull-up 62ohm
to +VCC_CORE

Pull-up56ohm
to +VCC_CORE

Pull-up 56ohm
to +VCC_CORE

float

float

float

Connect to CPU
Filter

Connect to CPU
Filter

Connect to GND
Connect to GND

Connect to PLD
through 0ohm

4

Northwood

Pop

Pop

Pop

Depop

Depop

Pop

Pop Pop

Prescott

PopPop Pop

Pop

Pop

Pop

PopDepop

Pop

Pop

Depop

DepopPop

Pop

Northwood
MT

H_BOOTSELECT<53>

Pop

Pop

Pop

Depop

Depop

Depop

Pop

Pop

3

H_BO OTSELEC T

Note: pop in page53

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R_C

+CPU_CORE

1 2

R141
@0_0402_5%

Pop: No rt hwood
Depop: Pr es cott

Title

Size Document Number Re v

2

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

461星期T, 30, 2003

5

4

3

2

1

+CPU_CORE

AE11

AE13

AE15

AE17

AE19

AE22

AE24

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B10

B12

B14

B16

B18

B20

B23

B26

C11

C13

C15

C17

C19

C22

C25

D10

D12

D14

D16

D18

D20

D21

D24

E11

E13

E15

E17

E19

E23

E26

F10

F12

F14

F16

F18

F22

F25

VSS_121

VSS_122

VSS_123

VIDPWRGD

VID5

AD2

H_VID_PWRGD

11

F5

VSS_124

VSS_125F2VSS_126

VSS_127

OPTIMIZED/COMPAT#

AF4

2

JP25B

VSS_57

F1

G5

F4

AB2

J6

C6

B6
B2
B5

AB23

Y4

D1

E5

W5

AB25

H5

H2
AD6
AD5

B3

C4

A2

AC6
AB5
AC4

Y6
AA5
AB4

D4
C1
D5

F7

E6

AD20
AE23

A5

A4
AF3

AD22

ITP

AC26

ITP#

AD26

COMP0

L24

COMP1

P1

2

C447

0.1U_0402_16V4Z

1

R_A

200_0402_1%

49.9_0402_1%

4

VSS_58

RS#0
RS#1
RS#2
RSP#
TRDY#

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCIOPLL
VCCA

VCCSENSE
VSSSENSE
VCCVIDLB

VSSA

ITP_CLK0
ITP_CLK1

COMP0
COMP1

VSS_129F8VSS_130

G21

G24

1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+CPU_GTLREF

R_B

169_0402_1%

100_0402_1%

VSS_59

VSS_60

VSS_131

VSS_132G3VSS_133G6VSS_134J2VSS_135

VSS_61

VSS_62

VSS_63

VSS_65

VSS_66

VSS_67

VSS_136

VSS_137J5VSS_138

J22

J25

K21

K24

1

C446
220P_0402_50V8J~D

2

VSS_68

VSS_69

VSS_139

VSS_140K3VSS_141K6VSS_142L1VSS_143

VSS_70

VSS_71

VSS_72

VSS_73

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85B4VSS_86B8VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92C2VSS_93

VSS_94

VSS_95C5VSS_96C7VSS_97C9VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117E4VSS_118E7VSS_119E9VSS_120

Prescott

VID0

VID1

VID2

VID3

AE5

AE4

AE3

AE2

VID0
VID1
VID2
VID3
VID4
VID5

+3VS

12

R179
10K_0402_5%

13

U44D

OE#

I12O

SN74LVC125APWLE_TSSOP14

VID4

AE1

AD3

VSS_144

VSS_145L4VSS_146M2VSS_147

VSS_148

VSS_149M5VSS_150

VSS_151

VSS_152N3VSS_153N6VSS_154P2VSS_155

VSS_156

VSS_157P5VSS_158R1VSS_159

VSS_160

VSS_161R4VSS_162

VSS_163

VSS_164T3VSS_165T6VSS_166U2VSS_167

VSS_168

VSS_169U5VSS_170V1VSS_171

VSS_172

VSS_173V4VSS_174

VSS_175

VSS_176W3VSS_177W6VSS_178Y2VSS_179

VSS_180

VSS_181

L23

L26

N21

N24

M22

M25

T21

P22

T24

P25

R23

R26

VID_PWRGD<53>

VCORE_ENLL<53>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

V23

V26

U22

U25

Y5

Y22

Y25

W21

W24

12

R1770 _ 0 402_5%

+CPU_CORE

C115

Pop: Prescott
Depop: Northwood

ITP_DBRESET#
ITP_TDO

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near CPU

1

1

+

+

2

2

H_RS#[0..2]<8>

H_TRDY#<8>

H_A20M#<25>

H_FERR#<25>

H_IGNNE#<25>

H_SMI#<25>

H_PWR GOOD<25>

H_STPCLK#<25>

H_INTR<25>

H_NMI<25>

H_INIT#<25>

H_RESET#<8,25>

H_DBSY#<8>

H_DRDY#<8>
CPU_CLKSEL0<13,23>
CPU_CLKSEL1<13,23>

H_THERMDA<7>
H_THERMDC<7>

H_THERMTRIP#<7>

R86 62_0402_5%

1 2

R96 62_0402_5%

1 2

R105 62_0402_5%

1 2

R82 62_0402_5%

1 2

R90 62_0402_5%

1 2

R100 62_0402_5%

1 2

H_VCCIOPLL

H_VCCA

C76
33U_D2_8M_R35

VCCSENSE<53>

VSSSENSE<53>

+VCCVID

H_VSSA

CK_ITP<23>

CK_ITP#<23>

CK_ITP
CK_ITP#

R23

51.1_ 0603_1%

+CPU_CORE

R_A

R_B

H_P WRGOOD

H_RESET#

1 2

R144

R370

0_0402_5%
1 2
1 2

R371

0_0402_5%

Prescott
Northwood

R388

49.9_0402_1%

R387
100_0402_1%

Prescott

Northwood

H_RS#0
H_RS#1
H_RS#2

H_FERR#

H_THERMDA
H_THERMDC

H_THERMTRIP#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

0_0402_5%

12

12

R139

51.1_ 0603_1%

COMP0 & COMP1

61.9_0603_1%

51.1_0603_1%

GTL Reference Voltage

Layout note :

R415 130_0402_5%

H_PROCHOT#

1 2

R54 300_0402_5%

D D

R38 62_0402_5%

C C

Note: Please change to 10uH, DC current
of 100mA parts and close to cap

B B

+CPU_CORE

+CPU_CORE

A A

H_PWRGOOD

1 2

H_RESET#

1 2

Note:H_FERR#,H_THERMTRIP#
pull-high in page25,page7

+CPU_CORE

L13 LQG21F4 R 7 N00_0805

1 2

33U_D2_8M_R35

1 2

L10 LQG21F4 R 7 N00_0805

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mils(min)

R390

54.9_ 0603_1%

1 2

R404

54.9_ 0603_1%

1 2

Between the CPU

R1024 47_0402_5%

1 2

R1025 150_0402_5%

1 2

R1026 680_0402_5%

1 2

R1027 47_0402_5%

1 2

Close to the CPU

5

R25

1 2

@0_0402_5%

AF26

VSS_128

SKTOCC#

DP#0
DP#1
DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

TESTHI9
TESTHI10
TESTHI11
TESTHI12

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

PROCHOT#

MCERR#

SLP#

NC1
NC2
NC3
NC4
NC5

VCCVID

AMP_3 - 1 565030-1_Pres cot t

+VCCVID

R_F

H_VID_PWRGD

J26
K25
K26
L25

AA21
AA6
F20
F6

AE26

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

E22
K22
R22
W22

F21
J23
P23
W23

L5
R5

E21
G25
P26
V21

AE25

C3
V6
AB26

A22
A7
AF25
AF24
AE21

R_E

R145

2.43K _0603_1%
1 2

CPUCLK_STP#<11,25,28,53>

R26 0_0402_5%

1 2

H_TEST HI 0
H_TEST HI 1

H_TEST HI 2_7

H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#

H_TESTHI12

ITP_DBRESET#

H_PROCHOT#

RE,RF
Pop: Pr es cott
Depop: No rt hwood

+VCCVID

+CPU_GTLREF

Pop: No rt hwood

R_G

R960 62_ 0402_5%
R53 62_0402_5%

R58 62_ 0402_5%

R417 62_ 0402_5%
R107 62_ 0402_5%
R114 62_ 0402_5%
R413 62_ 0402_5%
R51 62_ 0402_5%

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_ADSTB#0 <8>
H_ADSTB#1 <8>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_PROCHOT# <52>
H_C PUSLP# <25>

R194 200_0402_5%

1 2

Depop: Pr es cott

1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2

R_H

R414 0_0402_5%

1 2

+CPU_CORE

RH
Pop: Pr es cott
Depop: No rt hwood

+CPU_CORE

CP U_GHI# <26>

BOM update 7/10

+3VS

VID5

R113 1K _ 0 402_5%

VID5<53>
VID4<53>
VID3<53>

VID2<53>
VID1<53>
VID0<53>

R1008

1 2

4.7K_0402_5%

Level shift

1 2

VID4

R119 1K _ 0 402_5%

1 2

VID3
VID2
VID1
VID0

RP2 1K_1206_8P4R_5%

+3VS

2

4.7K_0402_5%
R109

2

Q5
MMBT3904_SOT23

3 1

45
36
27
18

CPU_STP#

Q6
MMBT3904_SOT23

3 1

Populate for Northwood

R37

1 2

0_0402_5%

1

H_DPSLP#

of

561星期T, 30, 2003

CPU_STP#

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

0E

5

4

3

2

1

+CPU_CORE

1

C113
22U_1 2 06_10V4Z

2

D D

+CPU_CORE

1

C65
22U_1 2 06_10V4Z

2

+CPU_CORE

1

C121
22U_1 2 06_10V4Z

2

C C

+CPU_CORE

1

C465
22U_1 2 06_10V4Z

2

1

C61
22U_1206_10V4Z

2

1

C70
22U_1206_10V4Z

2

1

C110
22U_1206_10V4Z

2

1

C460
22U_1206_10V4Z

2

1

C60
22U_1206_10V4Z

2

1

C82
22U_1206_10V4Z

2

1

C453
22U_1206_10V4Z

2

Place 11 North of Socket(Stuff 6)

1

C114
22U_1206_10V4Z

2

1

C491
22U_1206_10V4Z

2

1

2

Place 12 Inside Socket(Stuff all)

1

C93
22U_1206_10V4Z

2

1

C62
22U_1206_10V4Z

2

1

2

Place 9 South of Socket(Unstuff all)

1

C448
22U_1206_10V4Z

2

1

C445
22U_1206_10V4Z

2

1

2

C463
22U_1 2 06_10V4Z

C69
22U_1 2 06_10V4Z

C500
22U_1 2 06_10V4Z

1

C475
22U_1206_10V4Z

2

1

C81
22U_1206_10V4Z

2

1

C450
22U_1206_10V4Z

2

1

C474
22U_1206_10V4Z

2

22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)

1

C94
22U_1206_10V4Z

2

1

C441
22U_1206_10V4Z

2

1

C455
22U_1206_10V4Z

2

1

C111
22U_1206_10V4Z

2

1

C442
22U_1206_10V4Z

2

1

C43
22U_1206_10V4Z

2

1

C124
22U_1206_10V4Z

2

1

C462
22U_1 2 06_10V4Z

2

B B

+CPU_CORE

1

C39

+

@470U_D2_2.5VM

2

+CPU_CORE

1

C136

+

@470U_D2_2.5VM

2

+CPU_CORE

A A

1

C467

+

470U_D2_2.5VM

2

470uF _ERS10m ohm* 15

1

C90

+

@470U_D2_2.5VM

2

1

C495

+

@470U_D2_2.5VM

2

1

C466

+

470U_D2_2.5VM

2

5

1

C134

+

@470U_D2_2.5VM

2

1

C518

+

470U_D2_2.5VM

2

1

C516

+

470U_D2_2.5VM

2

1

C38

+

@470U_D2_2.5VM

2

1

C504

+

470U_D2_2.5VM

2

1

C519

+

@470U_D2_2.5VM

2

1

C91

+

@470U_D2_2.5VM

2

1

C443

+

470U_D2_2.5VM

2

1

C444

+

470U_D2_2.5VM

2

4

3

+CPU_CORE

0.1U_ 0 402_16V4Z

1

2

+CPU_CORE

0.1U_ 0 402_16V4Z

1

2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239

Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C106

C67

1

C123

2

0.1U_ 0 402_16V4Z

1

C45

2

0.1U_ 0 402_16V4Z

0.1U_0402_16V4Z

0.1U_ 0 402_16V4Z

1

2

1

2

C66

C48

@0.1U _0402_16V4Z

@0.1U _0402_16V4Z

1

C46

2

1

C122

2

2

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

661星期T, 30, 2003

5

4

3

2

1

Thermal Sensor ADM1032AR

+3VS

W=15mil

12

R501

D D

@10K_0402_5%

C590

2200P_0402_25V7K

1

2

H_THERMDA
H_THERMDC

THERM#

2

C580

1

0.1U_0402_16V4Z

1
2
3

U32

VDD

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ADM1032AR_SOP8

Address:1001_100X

R492

300_0402_5%

H_THERMTRIP#

+CPU_CORE

+CPU_CORE

R488 56_0402_5%

8
7
6
5

Q52

CBE

2SC2411K_SC59

123

H_THERMDA
H_THERMDC

C591 1U_0603_10V4Z

H_T HER MDA <5>
H_T HER MDC <5>

EC_SM C _2 <40>
EC_SM D _2 <40>

MAI N PWON <46,47,49>H_THERMTRIP#<5>

Fan Control circuitFan Control circuit

3

1

G

+5VS

6

2

D

S

4 5

FAN2_VOUT

1

C642

10U_0805_10V4Z

2

Q56

SI3456DV-T1_TSOP6

0.001U_0402_50V7M

0.001U_0402_50V7M

1

2

C640

C641

+5VS

1

2

12

R568
10K_0402_5%

JP27

1
2
3

53398-0390

0.1U_0402_16V4Z

EN_FAN1<40>EN_FAN2<40>

R542

13K_0603_1%

1 2

2

C635

1

1
3

1 2

R592 7.32K_0603_1%

RB751V_SOD323

+12VS

5

U39

P

+

FAN2_ON

4

O

-

G

LM321MF_SOT23-5

2

C653

1 2

@2200P_0603_16V7K

D20

2 1

C C

0.1U_0402_16V4Z

R583

13K_0603_1%

1 2

2

C613

1

1

+

3

-

1 2

R543 7.32K_0603_1%

RB751V_SOD323

+12VS

5

U36

P

FAN1_ON

4

O

G

LM321MF_SOT23-5

2

C614

1 2

@2200P_0603_16V7K

D19

2 1

3

1

G

+5VS

6

2

D

S

4 5

FAN1_VOUT

1

C637
10U_0805_10V4Z

2

Q55

SI3456DV-T1_TSOP6

0.001U_0402_50V7M

FANSPEED1<40>FANSPEED2< 40>

0.001U_0402_50V7M

1

2

C623

C633

+5VS

1

2

12

R541

10K_0402_5%

JP28

1
2
3

53398-0390

B B

A A

C

2222

1

3EB

2

SYMBOL(SOT23-NEW)

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

761星期T, 30, 2003

5

4

3

2

1

H_A#[3..31]
H_REQ# [0 ..4 ]

H_D#[0..63]

D D

H_ADSTB#0<5>

C C

H_ADSTB#1<5>

H_ADS#<4>

H_BNR#<4>

H_BPRI#<4>

H_DEFER#<4>

H_DRDY#<5>

H_DBSY#<5>

H_BR0#<4>

+1.8VS+1.8VS

R173

@1K_0402_5%

1 2
2

SUS_STAT#<16,26>

B B

3 1

Q12 @MMBT3904_SOT23

R1023

1 2

0_0402_5%

49.9_0402_1%

100_0402_1%

12

Layout & BOM update 7/10

R479
@1K_0402_5%

C823 0.1U_0402_16V4Z

R80 330_0805_1%

+CPU_CORE

+CPU_CORE

R136

R135

PLACE CLOSE TO U5 Ball
W28, USE 10/10
WIDTH/SPACE

C157
1U_0603_10V4Z

1 2

1 2

NB_RST#<11,16,25,38>

NB_PWRGD<42>

1 2

+1.8VS

L45

HB-1M2012-121JT03_0805

C164
220P_0402_50V9J

C587 CLOSE
TO Ball W28

H_LOCK#<4>

H_RESET#<5,25>

H_RS#2<5>
H_RS#1<5>
H_RS#0<5>

H_TRDY#<5>

H_HIT#<4>

H_HITM#<4>

SUS_STAT_R#

R132 24.9_0402_1%

1 2

R134 49.9_0402_1%

1 2

1

+

2

BOM update 7/10

NB_GTLREF

CPVDD

C822

C97
@1U_0603_10V4Z

@470U_D2_2.5VM

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#

H_RESET#
H_RS#2
H_RS#1
H_RS#0

H_TRDY#
H_HIT#
H_HITM#

COMP_N
COMP_P

M28

P25
M25
N29
N30
M26
N28

P29

P26
R29

P30

P28
N26
N27
M29
N25
R26

L28

L29
R27

U30

T30
R28
R25
U25

T28

V29

T26
U29
U26

V26

T25

V25
U27
U28

T29

L27

K25
H26

J27

L26
G27

F25

K26

A17
G25
G26

J25

F26

J26

H25

A9
AH5
AG5

C7

V28
W29
H23

J23

W28

Y29

Y28

B17

12

R76

4.7K_0402_5%

U11A

216RC300M_BGA_718

PART 1 OF 6

CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#

CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#

CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#

CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#

CPU_TRDY#
CPU_HIT#
CPU_HITM#

CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD

CPU_COMP_N
CPU_COMP_P
CPVDD
CPVSS
CPU_VREF

THERMALDIODE_N
THERMALDIODE_P

TESTMODE

ADDR. GROUP 1 ADDR. GROUP 0CONTROL

MISC.

DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3

CPU_DSTBN0#

CPU_DSTBP0#

CPU_DSTBN1#

AGTL+ I/F

CPU_DSTBP1#

PENTIUM

IV

CPU_DSTBN2#

CPU_DSTBP2#

CPU_DSTBN3#

CPU_DSTBP3#

H_A#[3..31] <4>
H_REQ#[0..4 ] <4>
H_D#[0..6 3 ] <4>

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#

CPU_DBI0#

CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#

CPU_DBI1#

CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#

CPU_DBI2#

CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_DBI3#

L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29

B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27

F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22

B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3

H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>

H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>

H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>

H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>

TESTMODE RS200 MODE
LOW

A A

5

4

HIGH

NORMAL MODE
TEST MODE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

of

861,

1

0E

5

4

3

2

1

As close as to DIMM

U11B

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4

D D

DDRA_SRAS#<14,15>
DDRA_SCAS#<14,15>

DDRA_SWE#<14,15>

C C

DDRA_CLK0<14>

DDRA_CLK0#<14>

DDRA_CLK1<14>

DDRA_CLK1#<14>

DDRA_CLK2<14>

DDRA_CLK2#<14>

DDRA_CLK3<14>

DDRA_CLK3#<14>

DDRA_CLK4<14>

DDRA_CLK4#<14>

DDRA_CLK5<14>

DDRA_CLK5#<14>

L47

B B

+1.8VS

1 2

HB-1M2012-121JT03_0805

DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_SRAS#
DDRA_SCAS#

DDRA_SWE#
DDRA_DQS0

DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7

DDRA_CLK0
DDRA_CLK0#

DDRA_CLK1
DDRA_CLK1#

DDRA_CLK2
DDRA_CLK2#

DDRA_CLK3
DDRA_CLK3#

DDRA_CLK4

DDRA_CLK4#

DDRA_CLK5
DDRA_CLK5#

DDRA_CKE0
DDRA_CKE1
DDRA_CKE2
DDRA_CKE3

DDRA_SCS#0
DDRA_SCS#1
DDRA_SCS#2
DDRA_SCS#3

C206
1U_0603_10V4Z

MPVDD

0.1U_0402_16V4Z

DDR_VREF

0.1U_0402_16V4Z

AH19

AJ17
AK17

AH16

AK16
AF17
AE18
AF16
AE17
AE16
AJ20

AG15

AF15
AE23

AH20

AE25

AH7
AF10
AJ14
AF21

AH23

AK28

AD29

AB26
AF24

AF25
AE24

AH13

AE21
AJ23
AJ27

AC28

AA25

AK10

AH10
AH18

AJ19

AG30
AG29

AK11
AJ11

AH17

AJ18
AF28

AG28

AF13
AE13

AG14

AF14

AH26
AH27

AF26

AG27
AC18

AD18

AJ8

AF9

PART 2 OF 6

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15

MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7

MEM_RAS#
MEM_CAS#

MEM_WE#
MEM_DQS0

MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7

MEM_CK0
MEM_CK0#

MEM_CK1
MEM_CK1#

MEM_CK2
MEM_CK2#

MEM_CK3
MEM_CK3#

MEM_CK4
MEM_CK4#

MEM_CK5
MEM_CK5#

MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3

MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3

MPVDD

MPVSS

216RC300M_BGA_718

2

C203

1

DDR_VREF

2

C202

1

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38

MEM I/F

MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

MEM_CAP1
MEM_CAP2

MEM_COMP

MEM_DDRVREF

+2.5V+2.5V

12

R176
1K_0603_1%

12

R175
1K_0603_1%

DDRA_DQ0

AG6

DDRA_DQ1

AJ7

DDRA_DQ2

AJ9

DDRA_DQ3

AJ10

DDRA_DQ4

AJ6

DDRA_DQ5

AH6

DDRA_DQ6

AH8

DDRA_DQ7

AH9

DDRA_DQ8

AE7

DDRA_DQ9

AE8

DDRA_DQ10

AE12

DDRA_DQ11

AF12

DDRA_DQ12

AF7

DDRA_DQ13

AF8

DDRA_DQ14

AE11

DDRA_DQ15

AF11

DDRA_DQ16

AJ12

DDRA_DQ17

AH12

DDRA_DQ18

AH14

DDRA_DQ19

AH15

DDRA_DQ20

AH11

DDRA_DQ21

AJ13

DDRA_DQ22

AJ15

DDRA_DQ23

AJ16

DDRA_DQ24

AF18

DDRA_DQ25

AG20

DDRA_DQ26

AG21

DDRA_DQ27

AF22

DDRA_DQ28

AF19

DDRA_DQ29

AF20

DDRA_DQ30

AE22

DDRA_DQ31

AF23

DDRA_DQ32

AJ21

DDRA_DQ33

AJ22

DDRA_DQ34

AJ24

DDRA_DQ35

AK25

DDRA_DQ36

AH21

DDRA_DQ37

AH22

DDRA_DQ38

AH24

DDRA_DQ39

AJ25

DDRA_DQ40

AK26

DDRA_DQ41

AK27

DDRA_DQ42

AJ28

DDRA_DQ43

AH29

DDRA_DQ44

AH25

DDRA_DQ45

AJ26

DDRA_DQ46

AJ29

DDRA_DQ47

AH30

DDRA_DQ48

AF29

DDRA_DQ49

AE29

DDRA_DQ50

AB28

DDRA_DQ51

AA28

DDRA_DQ52

AE28

DDRA_DQ53

AD28

DDRA_DQ54

AC29

DDRA_DQ55

AB29

DDRA_DQ56

AC26

DDRA_DQ57

AB25

DDRA_DQ58

Y26

DDRA_DQ59

W26

DDRA_DQ60

AE26

DDRA_DQ61

AD26

DDRA_DQ62

AA26

DDRA_DQ63

Y27

C205 0.47U_0603_16V7K

AF6

1 2

C167 0.47U_0603_16V7K

AA29

1 2

R174 49.9_0402_1%

AK19

1 2

AK20

DDRA_SDM[0..7]

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_SMA[0..15]

DDRA_CKE[0..3]

DDRA_SCS#[0..3]

DDRA_SDM[0..7] <14,15>

DDRA_SDQ[0..63] <14,15>

DDRA_SDQS[0..7] <14,15>

DDRA_SMA[0..15] <14,15>

DDRA_CKE[0..3] <14,15>

DDRA_SCS#[0..3] <14,15>

DDRA_DQ7
DDRA_DQ0
DDRA_DM0
DDRA_DQ5

DDRA_DQ4
DDRA_DQ6
DDRA_DQ1
DDRA_DQ2

DDRA_DQ3
DDRA_DQS0

DDRA_DQ9
DDRA_DQ8
DDRA_DQ14
DDRA_DM1

DDRA_DQ12
DDRA_DQ13
DDRA_DQ10
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ20
DDRA_DQS2 DDRA_SDQS2
DDRA_DQ17
DDRA_DQ16

DDRA_DQ21 DDRA_SDQ21
DDRA_DQ18
DDRA_DM2
DDRA_DQ22

DDRA_DQ23 DDRA_SDQ23

DDRA_DQ30
DDRA_DQ27
DDRA_DQ28

DDRA_DQ24
DDRA_DQ25
DDRA_DQ29

DDRA_DQ26
DDRA_DQ31

RP70

0_0804_8P4R_5%
RP69

0_0804_8P4R_5%

RP68

0_0804_8P4R_5%
RP67

0_0804_8P4R_5%

RP80

0_0804_8P4R_5%

RP79

0_0804_8P4R_5%

RP82

0_0804_8P4R_5%

RP81

0_0804_8P4R_5%

DDRA_SDQ7
DDRA_SDQ0
DDRA_SDM0
DDRA_SDQ5

DDRA_SDQ4
DDRA_SDQ6
DDRA_SDQ1
DDRA_SDQ2

DDRA_SDQ3
DDRA_SDQS0

DDRA_SDQ9
DDRA_SDQ8
DDRA_SDQ14
DDRA_SDM1

DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQS1

DDRA_SDQ15
DDRA_SDQ11

DDRA_SDQ20
DDRA_SDQ17

DDRA_SDQ16

DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ19DDRA_DQ19

DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQS3DDRA_DQS3

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDM3DDRA_DM3

DDRA_SDQ26
DDRA_SDQ31

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R621 0_0402_5%
R620 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R619 0_0402_5%
R618 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R630 0_0402_5%
R633 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R632 0_0402_5%
R631 0_0402_5%

DDRA_DQ33
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37

DDRA_DQS4
DDRA_DQ34
DDRA_DM4
DDRA_DQ38

DDRA_DQ39
DDRA_DQ35

DDRA_DQ40
DDRA_DQ45
DDRA_DQ44
DDRA_DQS5

DDRA_DQ41
DDRA_DQ42
DDRA_DQ46
DDRA_DM5

DDRA_DQ47
DDRA_DQ43

DDRA_DQ53
DDRA_DQ52
DDRA_DM6 DDRA_SDM6
DDRA_DQS6

DDRA_DQ54
DDRA_DQ49
DDRA_DQ48
DDRA_DQ50

DDRA_DQ55
DDRA_DQ51

DDRA_DQ60
DDRA_DQ61

DDRA_DQ56

DDRA_DQS7
DDRA_DQ62
DDRA_DM7
DDRA_DQ63

DDRA_DQ59

RP78

0_0804_8P4R_5%
RP77

0_0804_8P4R_5%

RP76

0_0804_8P4R_5%
RP75

0_0804_8P4R_5%

RP74

0_0804_8P4R_5%

RP73

0_0804_8P4R_5%

RP72

0_0804_8P4R_5%

RP71

0_0804_8P4R_5%

DDRA_SDQ33
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ35

DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ44
DDRA_SDQS5

DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ46
DDRA_SDM5

DDRA_SDQ47
DDRA_SDQ43

DDRA_SDQ53
DDRA_SDQ52

DDRA_SDQS6

DDRA_SDQ54
DDRA_SDQ49
DDRA_SDQ48
DDRA_SDQ50

DDRA_SDQ55
DDRA_SDQ51

DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ57DDRA_DQ57
DDRA_SDQ56

DDRA_SDQS7
DDRA_SDQ62
DDRA_SDM7
DDRA_SDQ63

DDRA_SDQ58DDRA_DQ58
DDRA_SDQ59

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R629 0_0402_5%
R628 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R627 0_0402_5%
R626 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R625 0_0402_5%
R624 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R623 0_0402_5%
R622 0_0402_5%

DDR_VREF trace width of
12mils and space

A A

5

12mils(min)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

961,

1

5

A_PAR<13,25>

A_ACAT#<25>

A_END#<25>

A_OFF#<25>

RA

1 2

R122
169_0402_1%

1 2

R947
M9@71.5_0402_1%

A_AD[0..31]
A_CBE#[0..3]

A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31

A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3

A_PAR
A_STROBE#
A_ACAT#
A_END#

R969 0_0402_5%

1 2

A_DEVSEL#
A_OFF#

A_SBREQ#
A_SBGNT#

A_REQ#0

New add

AGP_GNT#
AGP_REQ#

C149

1 2

0.1U_0402_16V4Z
AGP_COMP

8X

169_0402_1%

324_0603_1%1K_0603_1%
100_0603_1%

U11C

AK5

ALINK_AD0

AJ5

ALINK_AD1

AJ4

ALINK_AD2

AH4

ALINK_AD3

AJ3

ALINK_AD4

AJ2

ALINK_AD5

AH2

ALINK_AD6

AH1

ALINK_AD7

AG2

ALINK_AD8

AG1

ALINK_AD9

AG3

ALINK_AD10

AF3

ALINK_AD11

AF1

ALINK_AD12

AF2

ALINK_AD13

AF4

ALINK_AD14

AE3

ALINK_AD15

AE4

ALINK_AD16

AE5

ALINK_AD17

AE6

ALINK_AD18

AC2

ALINK_AD19

AC4

ALINK_AD20

AB3

ALINK_AD21

AB2

ALINK_AD22

AB5

ALINK_AD23

AB6

ALINK_AD24

AA2

ALINK_AD25

AA4

ALINK_AD26

AA5

ALINK_AD27

AA6

ALINK_AD28

Y3

ALINK_AD29

Y5

ALINK_AD30

Y6

ALINK_AD31

AG4

ALINK_CBE#0

AE2

ALINK_CBE#1

AC3

ALINK_CBE#2

AA3

ALINK_CBE#3

AD5

PCI_PAR/ALINK_NC

AC6

PCI_FRAME#/ALINK_STROBE#

AC5

PCI_IRDY#/ALINK_ACAT#

AD2

PCI_TRDY#/ALINK_END#

W4

INTA#

AD3

ALINK_DEVSEL#

AD6

PCI_STOP#/ALINK_OFF#

W5

ALINK_SBREQ#

W6

ALINK_SBGNT#

V5

PCI_REQ#0/ALINK_NC

V6

PCI_GNT#0/ALINK_NC

K5

AGP2_GNT#/AGP3_GNT

K6

AGP2_REQ#/AGP3_REQ

M5

AGP8X_DET#

J6

AGP_VREF/TMDS_VREF

J5

AGP_COMP

216RC300M_BGA_718

A_AD[0..31]<13,25>

A_CBE#[0..3]<25>

D D

C C

PCI_PIRQA#<16,25,30,33,44>

+1.5VS

+1.8VS

R1005
@4.7K_0402_5%

RB

?

B B

A A

RC

1 2

R125
100_0603_1%

1 2

RA

RB
RC

R121

324_0603_1%

4X

169_0402_1% //

71.5_0402_1%

1K_0603_1%

A_STROBE#<25>

A_DEVSEL#<25>

1 2

+3VS

R131

8.2K_0402_5%

AGP_REQ#<16>

AGP8X_DET#<16>

AGPREF_8X

PLACE CLOSE TO
CONNECTOR

+1.5VS

A_SBREQ#<25>
A_SBGNT#<25>

AGP_GNT#<16>

4

PART 3 OF 6

PCI Bus 0 / A-Link I/F

AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC

AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC

AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON

AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK

AGP2_CBE#0/AGP3_CBE0/TMD2_D7

AGP2_CBE#1/AGP3_CBE1/TMD2_DE

AGP2_CBE#2/AGP3_CBE2

AGP2_CBE#3/AGP3_CBE3/TMD1_D5

AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK

AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK

AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA

AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA

AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA

PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)

AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#

AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON

AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#

AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#

AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT

AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN

AGP2_PIPE#/AGP3_DBI_HI

AGP2_NC/AGP3_DBI_LO
AGP2_WBF#/AGP3_WBF

AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9

AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10

AGP_AD13
AGP_AD14
AGP_AD15

AGP_AD18/TMD1_DE

AGP_AD19/TMD1_D0

AGP_AD20/TMD1_D1

AGP_AD21/TMD1_D2

AGP_AD22/TMD1_D3

AGP_AD23/TMD1_D4

AGP_AD24/TMD1_D7

AGP_AD25/TMD1_D6

AGP_AD26/TMD1_D9

AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10

AGP_AD30/TMDS_HPD

AGP_AD31

AGP_PAR

AGP2_RBF#/AGP3_RBF

AGP_ST0
AGP_ST1
AGP_ST2

3

Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1

E5
E6
T3
U2
G3
H2

R3
M1
L3
H1

P5
R6
T6
T5
P6
R5
C1
D3
N6
N5

C3
C2
D4
E4
F6
F5
G6
G5

L6
M6
L5

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_SBSTBF
AGP_SBSTBS
AGP_ADSTBF_0
AGP_ADSTBS_0
AGP_ADSTBF_1
AGP_ADSTBS_1

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI
AGP_DBI_LO
AGP_RBF#
AGP_WBF#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

BOM update 7/18 for EMI

AGP_SBSTBF <16>
AGP_SBSTBS <16>
AGP_ADSTBF_0 <16>
AGP_ADSTBS_0 <16>
AGP_ADSTBF_1 <16>
AGP_ADSTBS_1 <16>

AGP_IRDY# <16>
AGP_TRDY# <16>
AGP_STOP# <16>
AGP_PAR <16>
AGP_FRAME# <16>
AGP_DEVSEL# <16>
AGP_DBI_HI <16>
AGP_DBI_LO <16>
AGP_RBF# <16>
AGP_WBF# <16>

BOM update 7/18 for EMI

@10U_0805_6.3V6M

C133

@10K_0402_5%

@10K_0402_5%

2

AGPAND LVDS MUXED SIGNALS

AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5

AGP_SBA7 LVDS_SSIN

R103 M9@0_0402_5%

1 2

R106 M9@0_0402_5%

1 2

R382 M9@0_0402_5%

1 2

R381 M9@0_0402_5%

1 2

R118 @0_0402_5%

1 2

R112 @0_0402_5%

1 2

For integrated graphics

AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]

M9@2.2K_0402_5%

AGP_SBA0

R958 M9@0_0402_5%

AGP_SBA1

@0.1U_0402_16V4Z

C137

12

R116

12

R120

12

12

Note: P L AC E CLOSE TO (NB RC30 0M)

1 2

R959 M9@0_0402_5%

1 2

SST Ratio Selection Table For SM560

Input Freq.
Range

60~70MHz
70~80MHz
80~100MHz

S1=1
S0=M S0=1

2.5%

2.4%

2.3%

2.0%

1.8%100~108MHz

"1"= Pull-Up ; "0"= Pull-Down ;
"M"= Pull-up & Pull-Down

2

R111
@10K_0402_5%

R108
@10K_0402_5%

U9

1

X1/CLK

S0

7

S0

6

S1

S1

@SM560BS_SOIC8

LVDS SPREAD SPECTRUM

VDD
SSCLK

GND

3

Xout

SSCC

ENABLT# <16,24,40>
ENAVDD <16,24>
AGP_STP# <16,26>
AGP_BUSY# <16,26>

LVDS_SSOUTAGP_SBA6

AGP_AD[0..31] <16>
AGP_SBA[0..7] <16>
AGP_CBE#[0..3] <16>
AGP_ST[0..2] <16>

R963

S1=0 S1=1
S0=1

1.8%

1.6%

1.4%

1.3%

L16
@BLM21P300S_0805

1 2

12

R124
@0_0402_5%

4

8
5

12

R129
@0_0402_5%

1

+3VS

R964
M9@2.2K_0402_5%

NB_I2CCLK <24>
NB_I2CDATA <24>

S1=M

S0=1

1.2%

1.1%

1.1%

1.0%

0.8%

1.0%1.9%

0.9%

0.9%

0.8%

0.6%

BOM up date 7/18 for EMI

+3VS

1 2

1

2

R117

@22_0402_5%
C148
@10P_0402_50V8K

LVDS_SSIN

LVDS_SSOUTSSOUT_IN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

1

星期三 七月

0E

of

10 61,

5

4

3

2

1

D D

L59

1 2

FBM-11-160808-121-T_0603

1

C525

0.1U_0402_16V4Z

+2.5VS

L60

1 2

KC FBM-L11-201209-221LMAT_0805

Note: P L AC E CLOS E TO (NB CHI P)

CRT_R

R71 M9@0_0402_5%

CRT_R<16,24,43>
CRT_G<16,24,43>

CRT_B<16,24,43>

CRT_HSYNC<16,24>
CRT_VSYNC<16,24>

C C

CRMA_R
LUMA_R TV_LUMA

DDCCLK_R
DDCDATA_R

1 2

R67 M9@0_0402_5%

1 2

CRT_B BLUE_R

R63 M9@0_0402_5%

1 2

CRT_HSYNC

R363 M9@0_0402_5%

CRT_VSYNC

1 2

R361 M9@0_0402_5%

1 2

R72 M9@0_0402_5%

1 2

R62 M9@0_0402_5%

1 2

R68 M9@0_0402_5%

1 2

R365 M9@0_0402_5%

1 2

R368 M9@0_0402_5%

1 2

RED_R
GREEN_RCRT_G

TV_CRMA
TV_COMPSCOMPS_R

3VDDCCL
3VDDCDA

HSYNC_R
VSYNC_R

+1.8VS

KC FBM-L11-201209-221LMAT_0805

TV_CRMA <16,24,43>
TV_LUMA <16,24,43>
TV_COMPS <16,24>

3VDDCCL <16,24>
3VDDCDA <16,24>

REFCLK1_NB<23>

Note: PLACE CLOSE TO (NB CHIP)

RC300M_X1

R91

RC300M_X2

B B

@1M_0402_1%

@18P_0402_50V8K

12

C95
Y2
@14.31818MHZ_20P_6X1430004201

C119

@18P_0402_50V8K

CLK_AGP_66M CLK_MEM_66M

12

R395
10_0402_5%

C464
15P_0402_50V8D

12

R101
10_0402_5%

C127
15P_0402_50V8D

L61

1 2

+1.8VS

1 2

KC FBM-L11-201209-221LMAT_0805

0.1U_0402_16V4Z

+1.8VS

KC FBM-L11-201209-221LMAT_0805

R84 0_0402_5%

R88
68_0603_1%

+3VS

1

C75
@0.1U_0402_16V4Z

2

1

2

L62

1 2

10U_0805_10V4Z

X2

4

VDD

1

OE

@27MHZ_15P

C86

0.1U_0402_16V4Z

1

1

L63

OUT
GND

2

C92

R75

3
2

C481

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C482

+3VS

Layout & BOM update 7/10

1

2

1

1

C102

2

2

1 2
715_0402_1%

CLK_NB_BCLK<23>

CLK_NB_BCLK#<23>

CLK_AGP_66M<23>

CLK_MEM_66M<23>

R1055

4.7K_0402_5%

R73 @22_0402_5%

C104

0.1U_0402_16V4Z

C103 0.1U_0402_16V4Z

RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R

NB_RSET

RC300M_X1
RC300M_X2

CLK_NB_BCLK
CLK_NB_BCLK#

CLK_AGP_66M
CLK_MEM_66M

27M_TV_R27M_TV

2

U11D

G9

VDDR3

H9

VDDR3

A14

AVDD_25

B13

AVSSN

B14

AVDDDI_18

C13

AVSSDI

A15

AVDDQ

B15

AVSSQ

H11

PLLVDD_18

G11

PLLVSS

F14

RED

F15

GREEN

E14

BLUE

C8

DACHSYNC

D9

DACVSYNC

C14

RSET

A4

XTALIN

B4

XTALOUT

A5

HCLKIN

B5

HCLKIN#

B6

SYS_FBCLKOUT

A6

SYS_FBCLKOUT#

D8

ALINK_CLK

B2

AGPCLKOUT

B3

AGPCLKIN

A3

EXT_MEM_CLK

D7

USBCLK

B7

REF27

C5

OSC

216RC300M_BGA_718

+3VS

PART 4 OF 6

LVDS

CRT

CLK. GEN.

TXOUT_U0N

TXOUT_U0P

TXOUT_U1N

TXOUT_U1P

TXOUT_U2N

TXOUT_U2P

TXCLK_UN
TXCLK_UP

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P

TXCLK_LN
TXCLK_LP

LPVDD_18

LPVSS

LVDDR_18
LVDDR_18

LVSSR
LVSSR

COMP_B

SVID

DACSCL
DACSDA

CPUSTOP#

SYSCLK

SYSCLK#

C_R
Y_G

D12
E12
F11
F12
D13
D14
E13
F13

E10
D10
B9
C9
D11
E11
B10
C10

A12
A11

B12
C12

B11
C11

CRMA_R

E15

LUMA_R

C15

COMPS_R

D15

DDCCLK_R

D6

DDCDATA_R

C6

D5

R401 @0_0402_5%
A8
B8

BOM update 6/16

TXB0-_NB <24>
TXB0+_NB <24>
TXB1-_NB <24>
TXB1+_NB <24>
TXB2-_NB <24>
TXB2+_NB <24>
TXBCLK-_NB <24>
TXBCLK+_NB <24>

TXA0-_NB <24>
TXA0+_NB <24>
TXA1-_NB <24>
TXA1+_NB <24>
TXA2-_NB <24>
TXA2+_NB <24>
TXACLK-_NB <24>
TXACLK+_NB <24>

+1.8VS_LPVDD

+1.8VS_LVDDR

@2N7002_SOT23

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

S

Q47

D

1 3

0.1U_0402_16V4Z

1

C73

C74

2

1

C484

C483

2

G

2

R402

4.7K_0402_5%

+1.8VS

R70

1 2

KC FBM-L11-201209-221LMAT_0805

C68
10U_0805_10V4Z

+1.8VS

R399

1 2

KC FBM-L11-201209-221LMAT_0805

C468
10U_0805_10V4Z

CPUCLK_STP# <5,25,28,53>

NB_RST# <8,16,25,38>

+3VS

CPUSTOP# <23>

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

11 61,

1

5

4

3

2

1

+1.5VS +2.5V

D D

C C

+CPU_CORE

+3VS

B B

U11E

F10

VDD_CORE

F9

VDD_CORE

G12

VDD_CORE

H12

VDD_CORE

H13

VDD_CORE

M12

VDD_CORE

M13

VDD_CORE

M14

VDD_CORE

M17

VDD_CORE

M18

VDD_CORE

M19

VDD_CORE

N12

VDD_CORE

N13

VDD_CORE

N14

VDD_CORE

N17

VDD_CORE

N18

VDD_CORE

N19

VDD_CORE

P12

VDD_CORE

P13

VDD_CORE

P14

VDD_CORE

P17

VDD_CORE

P18

VDD_CORE

P19

VDD_CORE

U12

VDD_CORE

U13

VDD_CORE

U14

VDD_CORE

U17

VDD_CORE

U18

VDD_CORE

U19

VDD_CORE

V12

VDD_CORE

V13

VDD_CORE

V14

VDD_CORE

V17

VDD_CORE

V18

VDD_CORE

V19

VDD_CORE

W12

VDD_CORE

W13

VDD_CORE

W14

VDD_CORE

W17

VDD_CORE

W18

VDD_CORE

W19

VDD_CORE

C16

VDDR2_CPU

D16

VDDR2_CPU

D17

VDDR2_CPU

E16

VDDR2_CPU

E17

VDDR2_CPU

F16

VDDR2_CPU

F17

VDDR2_CPU

G17

VDDR2_CPU

G21

VDDR2_CPU

G23

VDDR2_CPU

G24

VDDR2_CPU

H16

VDDR2_CPU

H17

VDDR2_CPU

H19

VDDR2_CPU

H21

VDDR2_CPU

H24

VDDR2_CPU

K23

VDDR2_CPU

K24

VDDR2_CPU

M23

VDDR2_CPU

P23

VDDR2_CPU

P24

VDDR2_CPU

T23

VDDR2_CPU

T24

VDDR2_CPU

U23

VDDR2_CPU

U24

VDDR2_CPU

W30

VDDR2_CPU

AA1

VDDL_ALINK

AA7

VDDL_ALINK

AA8

VDDL_ALINK

AC7

VDDL_ALINK

AC8

VDDL_ALINK

AD1

VDDL_ALINK

AD7

VDDL_ALINK

AD8

VDDL_ALINK

AK3

VDDL_ALINK

W8

VDDL_ALINK

216RC300M_BGA_718

PART 5 OF 6

CORE PWR

CPU I/F PWRALINK PWR

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

MEM I/F PWR

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

POWER

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP

AGP PWR

VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP

VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33

VDD_18
VDD_18
VDD_18
VDD_18

AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25

A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6

E7
F7
G8

AC22
AC9
H10
H22

+1.5VS

+1.8VS

R104
M9+/M10@0_0805_5%

1 2

1 2

R102
M9@0_0805_5%

+1.5VS

+3VS

U11F

PART 6 OF 6

A29

VSS

AB23

VSS

AB24

VSS

AB27

VSS

AB4

VSS

AB8

VSS

AC1

VSS

AC11

VSS

AC14

VSS

AC16

VSS

AC20

VSS

AC30

VSS

AD11

VSS

AD14

VSS

AD16

VSS

AD20

VSS

AD4

VSS

AE27

VSS

AF30

VSS

AF5

VSS

AG10

VSS

AG13

VSS

AG16

VSS

AG19

VSS

AG22

VSS

AG25

VSS

AG7

VSS

AH28

VSS

AH3

VSS

AJ1

VSS

AK13

VSS

AK2

VSS

AK22

VSS

AK29

VSS

AK4

VSS

AK7

VSS

B1

VSS

B16

VSS

B30

VSS

C19

VSS

C23

VSS

C27

VSS

C4

VSS

D21

VSS

D25

VSS

E3

VSS

E8

VSS

E9

VSS

F27

VSS

F4

VSS

F8

VSS

G14

VSS

G15

VSS

G18

VSS

G20

VSS

H14

VSS

H15

VSS

H18

VSS

H20

VSS

H27

VSS

H4

VSS

H8

VSS

J7

VSS

216RC300M_BGA_718

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

For external AGP/1.5V GPIO

For 3.3V GPIO

R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8

C531

47U_B_6.3VM

C176

47U_B_6.3VM

@0.1U_0402_16V4Z

C89

47U_B_6.3VM

C161

47U_B_6.3VM

C150

47U_B_6.3VM

+CPU_CORE

1

+

2

+2.5V

1

+

2

+2.5V

1

2

+1.8VS

1

+

2

+3VS

1

+

2

+1.5VS

22U_1206_10V4Z

1

+

2

0.1U_0402_16V4Z

1

C539

2

0.1U_0402_16V4Z

47U_B_6.3VM

1

+

C181

2

0.1U_0402_16V4Z

@0.1U_0402_16V4Z

1

C587

C576

2

@0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C98

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C183

2

0.1U_0402_16V4Z

1

C135

2

0.1U_0402_16V4Z

1

C151

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C200

2

@0.1U_0402_16V4Z

1

C198

2

0.1U_0402_16V4Z

1

C99

2

0.1U_0402_16V4Z

1

C524

2

0.1U_0402_16V4Z

1

C566

2

0.1U_0402_16V4Z

1

C544

2

1

C169

2

0.1U_0402_16V4Z

1

C201

2

1

C582

2

0.1U_0402_16V4Z

1

C564

2

0.1U_0402_16V4Z

1

C546

2

0.1U_0402_16V4Z

1

C555

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C180

2

1

C521

2

0.1U_0402_16V4Z

1

C568

2

0.1U_0402_16V4Z

1

C561

2

0.1U_0402_16V4Z

1

C559

2

1

C182

2

0.1U_0402_16V4Z

1

C589

2

0.1U_0402_16V4Z

1

C567

2

0.1U_0402_16V4Z

1

C523

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C588

2

0.1U_0402_16V4Z

1

C177

2

0.1U_0402_16V4Z

1

C545

2

0.1U_0402_16V4Z

1

C31

2

1

C581

2

0.1U_0402_16V4Z

1

C577

2

0.1U_0402_16V4Z

1

C560

2

0.1U_0402_16V4Z

1

C522

2

@0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C585

2

0.1U_0402_16V4Z

1

C173

2

0.1U_0402_16V4Z

1

C549

2

1

C532

2

1

2

1

2

1

2

0.1U_0402_16V4Z

1

C583

C570

2

0.1U_0402_16V4Z

1

C562

C558

2

0.1U_0402_16V4Z

1

C538

C557

2

0.1U_0402_16V4Z

1

C586

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C810

2

0.1U_0402_16V4Z

1

C584

2

0.1U_0402_16V4Z

1

C811

2

0.1U_0402_16V4Z

1

C575

2

0.1U_0402_16V4Z

1

C812

2

1

C563

2

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

12 61,

1

5

4

3

2

1

A_AD[0..31]<10,25>

A_AD31

R473 4.7K_0402_5%

D D

C C

A_AD30

R502 4.7K_0402_5%

A_AD29

A_AD28

A_AD27

A_AD26

A_AD17

R147 10K_0402_5%

R489 10K_0402_5%

R475 4.7K_0402_5%
R476 @4.7K_0402_5%

R481 @4.7K_0402_5%
R148 4.7K_0402_5%

R503 4.7K_0402_5%
R161 @4.7K_0402_5%

R149 4.7K_0402_5%
R482 @4.7K_0402_5%

R151 4.7K_0402_5%
R150 @4.7K_0402_5%

2 1
D32
RB751V_SOD323

2 1
D33
RB751V_SOD323

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

CPU_CLKSEL1 <5,23>

+3VS

CPU_CLKSEL0 <5,23>

A_AD[31..30] : FSB CLK SPEED

DEFAULT: 01
00: 100 MHZ

01: 133 MHZ
10: 200MHZ
11: 166 MHZ

A_AD2 9: STRAP CONFIGURATION

DEFAULT:1
0: REDUCEDE SET

1: FULL SET

A_AD28: SPREAD SPECTRUM ENABLE

DEFAULT:0
0: DISABLE

1: ENABLE

A_AD27 : Fr cShortReset#

DEFAULT: 1
0: TEST MODE

1: NORMAL MODE

A_AD26 : ENABLE IOQ

DEFAULT: 1
0: IOQ=1

1: IOQ=12

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

A_CBE#[0..3]<10,25>

A_AD[0..31]
A_CBE#[0..3]

A_AD18

A_PAR<10,25>

R487 @4.7K_0402_5%
R478 4.7K_0402_5%

R953 4.7K_0402_5%

A_PAR

R480 @4.7K_0402_5%

+3VS

+3VS

A_AD1 8 : ENABLE PHASE CAL IBRATION

DEFAULT: 0
0: ENABLE

1: DISABLE

PAR: EXTENDED DEBUG MODE

DEFAULT : 1
0: DEBUG MODE

1: NORMAL

DEFAULT: 00
00: 1.05V

01: 1.35V
11: 1.75V
10: 1.45V

A_AD25

R510 @4.7K_0402_5%
R163 4.7K_0402_5%

+3VS

A_AD24

B B

A_AD23

A_AD22

R512 4.7K_0402_5%

R490 4.7K_0402_5%
R153 @4.7K_0402_5%

R166 4.7K_0402_5%

+3VS

+3VS

A_AD2 4 : M OBILE CPU SELECT

DEFAULT: 1
0: BANIAS CPU

1: OTH ER CPU

A_AD2 3 : C L OCK BYPASS DISABLE

DEFAULT: 1
0: TEST MODE

1: NORMAL

A_AD22 : OSC PAD OUTPUT PCICLK

DEFAULT : 1
0: OSC CLK OUT

1: PCICLK OUT

A_AD21

A A

A_AD20

R158 4.7K_0402_5%
R160 @4.7K_0402_5%

R494 @4.7K_0402_5%
R157 4.7K_0402_5%

5

+3VS

+3VS

A_AD2 1 : A UTO_CAL ENABLE

DEFAULT : 1
0: DISABLE

1: ENABLE

A_AD20 : INTERNAL CLK GEN ENABLE

DEFAULT : 0
0: DISABLE

1: ENABLE

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

of

13 61,

1

0E

5

4

3

2

1

R673
1K_0603_1%

R672
1K_0603_1%

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..15]
DDRA_SDM[0..7]

DDRA_SCS#2 <9,15>
DDRA_SCS#3 <9,15>

DDRA_CKE2 <9,15>
DDRA_CKE3 <9,15>

+2.5V

JP10

1

VREF

3
DDRA_SDQ7
DDRA_SDQ5 DDRA_SDQ4

DDRA_SDQS0
DDRA_SDQ6

DDRA_SDQ2 DDRA_SDQ3

DDRA_SDQ14
DDRA_SDQS1

DDRA_SDQ13

DDRA_CLK0<9>

DDRA_CLK0#<9>

DDRA_CLK2<9>

DDRA_CLK2#<9>

DDRA_CKE1<9,15> DDRA_CKE0 <9,15>

DDRA_SWE#<9,15>

DDRA_SCS#0<9,15>

SMB_CK_DAT1<23,26>

SMB_CK_CLK1<23,26>

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ19 DDRA_SDQ23
DDRA_SDQ30

DDRA_SDQ28
DDRA_SDQS3

DDRA_SDQ25
DDRA_SDQ26

DDRA_CKE1 D DRA_CKE0
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1 DDRA_SMA0

DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#0
DDRA_SMA15

DDRA_SDQ33
DDRA_SDQ32

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDQ44
DDRA_SDQS5

DDRA_SDQ42
DDRA_SDQ47

DDRA_SDQ53 DDRA_SDQ52
DDRA_SDQ54

DDRA_SDQS6
DDRA_SDQ48

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ57
DDRA_SDQS7

DDRA_SDQ62 DDRA_SDQ63
DDRA_SDQ58

SMB_CK_DAT1
SMB_CK_CLK1

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP1565711-1_STANDARD 4.0

DIMM0

STANDARD

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

A11

A8

VSS

A6
A4
A2

A0
VDD
BA1

S1#

DU

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD
CK1

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD
SA0
SA1
SA2

DU

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ0

DDRA_SDM0
DDRA_SDQ1

DDRA_SDQ8DDRA_SDQ9
DDRA_SDQ12

DDRA_SDM1
DDRA_SDQ10

DDRA_SDQ11

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ27
DDRA_SDQ24

DDRA_SDM3
DDRA_SDQ29

DDRA_SDQ31

DDRA_SMA11
DDRA_SMA8

DDRA_SMA6
DDRA_SMA4
DDRA_SMA2

DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ45

DDRA_SDQ41
DDRA_SDM5

DDRA_SDQ46
DDRA_SDQ43

DDRA_SDQ49
DDRA_SDM6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ61
DDRA_SDQ56

DDRA_SDM7

DDRA_SDQ59

0.1U_ 0 402_16V4Z

C831

0.1U_ 0 402_16V4Z

DDRA_SRAS# <9,15>
DDRA_SCAS# <9,15>
DDRA_SCS#1 <9,15>

DDRA_CLK1# <9>
DDRA_CLK1 <9>

+2.5V

2

C235

1

2

2

C233

1

1

0.1U_ 0 402_16V4Z

DDRA_VREF trace width of
20mils and space
20mils(min)

DDRA_SDQ[0..63]<9,15>
DDRA_SDQS[0..7]<9,15>
DDRA_SMA[0..15]<9,15>

DDRA_SDM[0..7]<9,15>

D D

DDRA_CLK3<9>

DDRA_CLK3#<9>

C C

DDRA_CLK5<9>

DDRA_CLK5#<9>

B B

A A

+2.5V

JP29

1

VREF

3
DDRA_SDQ0
DDRA_SDQ4

DDRA_SDQS0
DDRA_SDQ1

DDRA_SDQ3
DDRA_SDQ8

DDRA_SDQ12
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDQS2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ27

DDRA_SDQ24
DDRA_SDQS3

DDRA_SDQ29
DDRA_SDQ31

DDRA1_CKE3
DDRA1_SMA12

DDRA1_SMA9
DDRA1_SMA7

DDRA1_SMA5
DDRA1_SMA3
DDRA1_SMA1

DDRA1_SMA10
DDRA1_SMA13
DDRA1_SWE#
DDRA1_SCS#2
DDRA1_SMA15

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ45

DDRA_SDQ41
DDRA_SDQS5

DDRA_SDQ46
DDRA_SDQ43

DDRA_SDQ52
DDRA_SDQ49

DDRA_SDQS6 DDRA_SDM6
DDRA_SDQ50

DDRA_SDQ51
DDRA_SDQ61

DDRA_SDQ56
DDRA_SDQS7

DDRA_SDQ63
DDRA_SDQ59

SMB_CK_DAT1
SMB_CK_CLK1

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP1565619_REVERSE 5.2

DIMM1

REVERSE

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

2
4

VSS

6

DQ4

8

DQ5

10

VDD

12

DM0

14

DQ6

16

VSS

18

DQ7

20
22

VDD

24
26

DM1

28

VSS

30
32
34

VDD

36

VDD

38

VSS

40

VSS

42
44
46

VDD

48

DM2

50
52

VSS

54
56
58

VDD

60
62

DM3

64

VSS

66
68
70

VDD

72

CB4

74

CB5

76

VSS

78

DM8

80

CB6

82

VDD

84

CB7

86
88

VSS

90

VSS

92

VDD

94

VDD

96
98
100

A11

102

A8

104

VSS

106

A6

108

A4

110

A2

112

A0

114

VDD

116

BA1

118
120
122

S1#

124

DU

126

VSS

128
130
132

VDD

134

DM4

136
138

VSS

140
142
144

VDD

146
148

DM5

150

VSS

152
154
156

VDD

158
160

CK1

162

VSS

164
166
168

VDD

170

DM6

172
174

VSS

176
178
180

VDD

182
184

DM7

186

VSS

188
190
192

VDD

194

SA0

196

SA1

198

SA2

200

DU

Layout & BOM update 7/10 Layout & BOM update 7/10

+2.5V

DDRA_SDQ7
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ2
DDRA_SDQ9

DDRA_SDQ14
DDRA_SDM1

DDRA_SDQ13
DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDM2
DDRA_SDQ18

DDRA_SDQ19
DDRA_SDQ30

DDRA_SDQ28
DDRA_SDM3

DDRA_SDQ25
DDRA_SDQ26

DDRA1_CKE2
DDRA1_SMA11

DDRA1_SMA8
DDRA1_SMA6

DDRA1_SMA4
DDRA1_SMA2
DDRA1_SMA0

DDRA1_SMA14
DDRA1_SRAS#
DDRA1_SCAS#
DDRA1_SCS#3

DDRA_SDQ33
DDRA_SDQ32

DDRA_SDM4
DDRA_SDQ34

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDQ44
DDRA_SDM5

DDRA_SDQ42
DDRA_SDQ47

DDRA_SDQ53
DDRA_SDQ54

DDRA_SDQ48
DDRA_SDQ55

DDRA_SDQ60
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ62

DDRA_SDQ58

+3VS

0.1U_0402_16V4Z

C830

0.1U_0402_16V4Z

DDRA_CLK4# <9>
DDRA_CLK4 <9>

2

C701

1

2

2

C700

1

1

DDRA_VREF trace width of
20mils and space
20mils(min)

DDRA1_SMA9
DDRA1_SMA12

DDRA1_SMA5
DDRA1_SMA7

DDRA1_SMA1
DDRA1_SMA3

DDRA1_SMA13
DDRA1_SMA10

DDRA1_SMA8
DDRA1_SMA11

DDRA1_SMA4
DDRA1_SMA6

DDRA1_SMA0
DDRA1_SMA2

DDRA1_SMA14
DDRA1_SMA15
DDRA1_SWE#

DDRA1_SCS#2
DDRA1_SCS#3
DDRA1_SRAS#
DDRA1_SCAS#
DDRA1_CKE2
DDRA1_CKE3

+2.5V+2.5V

12

DDR A_VREF DDR A_VREF

0.1U_ 0 402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 2

R1045 10_0402_5%

1 2

R1046 10_0402_5%

1 2

R1047 10_0402_5%

1 2

R1048 10_0402_5%

1 2

R1049 10_0402_5%

1 2

R1050 10_0402_5%

1 2

R1051 10_0402_5%

1 2

R1052 10_0402_5%

1 2

R1053 10_0402_5%

RP114

10_0404_4P2R_5%

RP115

10_0404_4P2R_5%

RP116

10_0404_4P2R_5%

RP117

10_0404_4P2R_5%

RP118

10_0404_4P2R_5%

RP119

10_0404_4P2R_5%

RP120

10_0404_4P2R_5%

12

DDRA_SMA9
DDRA_SMA12

DDRA_SMA5
DDRA_SMA7

DDRA_SMA1
DDRA_SMA3

DDRA_SMA13
DDRA_SMA10

DDRA_SMA8
DDRA_SMA11

DDRA_SMA4
DDRA_SMA6

DDRA_SMA0
DDRA_SMA2

DDRA_SMA14
DDRA_SMA15
DDRA_SWE#

DDRA_SCS#2
DDRA_SCS#3
DDRA_SRAS#
DDRA_SCAS#
DDRA_CKE2
DDRA_CKE3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Re v

Date: Sheet

Compal Ele c t ronics, Inc.

SCHEMATIC, M/B LA-1861

401257

七月

1

14 61星期T, 30, 2003

0E

of

5

DDR Termination resistors & Decoupling caps

4

3

2

1

+1.25VS

DDRA_SMA15
DDRA_SMA13

DDRA_SDQ[0..63]<9,14>

D D

C C

B B

DDRA_SDQS[0..7]<9,14>

DDRA_SMA[0..15]<9,14>

DDRA_SDM[0..7]<9,14>

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..15]
DDRA_SDM[0..7]

DDRA_SCAS#<9,14>

DDRA_SCS#0<9, 14>

DDRA_SRAS#<9,14>

DDRA_CKE3<9,14>

DDRA_CKE1<9,14>

DDRA_CKE2<9,14>

DDRA_CKE0<9,14>

DDRA_SWE#<9,14>

DDRA_SCS#1<9, 14>

DDRA_SCS#2<9, 14>

DDRA_SCS#3<9, 14>

DDRA_SMA14
DDRA_SMA10

DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7

DDRA_SMA8
DDRA_SMA9
DDRA_SMA11
DDRA_SMA12

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3

DDRA_SCAS#

DDRA_SCS#0

DDRA_SRAS#

DDRA_CKE3

DDRA_CKE1

DDRA_CKE2

DDRA_CKE0

DDRA_SWE#

DDRA_SCS#1

DDRA_SCS#2

DDRA_SCS#3

RP92

33_0804_8P4R_5%

RP94

33_0804_8P4R_5%

33_0804_8P4R_5%

33_0804_8P4R_5%

1 2

R236 33_0402_5%

1 2

R237 33_0402_5%

1 2

R234 33_0402_5%

1 2

R232 33_0402_5%

1 2

R230 33_0402_5%

1 2

R233 33_0402_5%

1 2

R231 33_0402_5%

1 2

R235 33_0402_5%

1 2

R238 33_0402_5%

1 2

R239 33_0402_5%

1 2

R240 33_0402_5%

RP95

RP93

18
27
36
45

18
27
36
45

+1.25VS

18
27
36
45

18
27
36
45

C743 0.1U_04 02_16V4Z

1 2

+2.5V

1 2

C76 5 0.1U _ 0 4 02_16V4Z

C739 0.1U_04 02_16V4Z

1 2

+2.5V

1 2

C73 8 0.1U _ 0 4 02_16V4Z

C741 0.1U_0402_16V4Z

1 2
1 2

C740 0.1U_0402_16V4Z

C745 0.1U_0402_16V4Z

1 2
1 2

C744 0.1U_0402_16V4Z

+1.25VS

C298 0.1U_04 02_16V4Z

1 2

1 2

C28 5 0.1U _ 0 4 02_16V4Z

C284 0.1U_04 02_16V4Z

1 2

1 2

C28 6 0.1U _ 0 4 02_16V4Z

C297 0.1U_04 02_16V4Z

1 2

1 2

C28 3 0.1U _ 0 4 02_16V4Z

+2.5V

+2.5V

1

C813

22U_1206_10V4Z

2

+2.5V

+2.5V

+2.5V

+1.25VS

1

2

C814
22U_1206_10V4Z

DDRA_SDQS0
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQ6

DDRA_SDQ0
DDRA_SDQ7
DDRA_SDQ4
DDRA_SDQ5

DDRA_SDQ3
DDRA_SDQ2
DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQ10
DDRA_SDQ13
DDRA_SDQ11
DDRA_SDQ15

DDRA_SDQ12
DDRA_SDQ14
DDRA_SDQS1
DDRA_SDM1

DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ20
DDRA_SDQ17

DDRA_SDQ18
DDRA_SDQ22
DDRA_SDM2
DDRA_SDQS2

DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ19
DDRA_SDQ23

DDRA_SDM3
DDRA_SDQS3
DDRA_SDQ28
DDRA_SDQ24

DDRA_SDQ26
DDRA_SDQ31
DDRA_SDQ25
DDRA_SDQ29

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

+1.25VS +1.25VS

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

C762 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C763 0.1U_0402_16V4Z

C764 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C759 0.1U_0402_16V4Z

C758 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C757 0.1U_0402_16V4Z

C754 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C751 0.1U_0402_16V4Z

C750 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C749 0.1U_0402_16V4Z

C769 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C767 0.1U_0402_16V4Z

C287 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C770 0.1U_0402_16V4Z

C291 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C296 0.1U_0402_16V4Z

C775 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C290 0.1U_0402_16V4Z

C771 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C774 0.1U_0402_16V4Z

DDRA_SDQ34
DDRA_SDQ38
DDRA_SDM4
DDRA_SDQS4

DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ36

DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ39
DDRA_SDQ35

DDRA_SDM5
DDRA_SDQS5
DDRA_SDQ44
DDRA_SDQ41

DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ42
DDRA_SDQ46

DDRA_SDQ54
DDRA_SDQ49
DDRA_SDQ53
DDRA_SDQ52

DDRA_SDQ48
DDRA_SDQ50
DDRA_SDM6
DDRA_SDQS6

DDRA_SDQ61
DDRA_SDQ60
DDRA_SDQS7
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ55

DDRA_SDQ59
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM7

RP15

RP13

RP14

RP17

RP16

RP100

RP99

RP98

RP97

RP96

RP109

18
27
36
45

56_0804_8P4R_5%

RP110

18
27
36
45

56_0804_8P4R_5%

RP108

18
27
36
45

56_0804_8P4R_5%

RP107

18
27
36
45

56_0804_8P4R_5%

RP106

18
27
36
45

56_0804_8P4R_5%

RP104

18
27
36
45

56_0804_8P4R_5%

RP105

18
27
36
45

56_0804_8P4R_5%

RP102

18
27
36
45

56_0804_8P4R_5%

RP103

18
27
36
45

56_0804_8P4R_5%

RP101

18
27
36
45

56_0804_8P4R_5%

C76 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C742 0.1U _ 0 4 02_16V4Z

C76 0 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C761 0.1U _ 0 4 02_16V4Z

C75 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C755 0.1U _ 0 4 02_16V4Z

C75 2 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C753 0.1U _ 0 4 02_16V4Z

C74 8 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C747 0.1U _ 0 4 02_16V4Z

C74 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C768 0.1U _ 0 4 02_16V4Z

C28 9 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C772 0.1U _ 0 4 02_16V4Z

C29 5 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C294 0.1U _ 0 4 02_16V4Z

C77 3 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C292 0.1U _ 0 4 02_16V4Z

C29 3 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C288 0.1U _ 0 4 02_16V4Z

System Memory Decoupling caps

+2.5V

1

C236

0.1U_ 0 402_16V4Z

2

+2.5V

1

C249

0.1U_ 0 402_16V4Z

2

+2.5V

A A

1

2

+2.5V

1

2

C276
22U_1206_10V4Z

C267

0.1U_ 0 402_16V4Z

5

1

C234

0.1U_ 0 402_16V4Z

2

1

C250

0.1U_ 0 402_16V4Z

2

1

C261

0.1U_ 0 402_16V4Z

2

1

C268

0.1U_ 0 402_16V4Z

2

1

C237

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C262

0.1U_0402_16V4Z

2

1

C238

0.1U_0402_16V4Z

2

1

C240

0.1U_ 0 402_16V4Z

2

1

C252

0.1U_ 0 402_16V4Z

2

1

C263

0.1U_ 0 402_16V4Z

2

1

C239

0.1U_ 0 402_16V4Z

2

1

C241

0.1U_0402_16V4Z

2

1

C253

0.1U_0402_16V4Z

2

1

C264

0.1U_0402_16V4Z

2

1

C269

0.1U_0402_16V4Z

2

1

C242

0.1U_ 0 402_16V4Z

2

1

C254

0.1U_ 0 402_16V4Z

2

1

C265

0.1U_ 0 402_16V4Z

2

1

C270

0.1U_ 0 402_16V4Z

2

4

1

C243

0.1U_ 0 402_16V4Z

2

1

C255

0.1U_ 0 402_16V4Z

2

1

C266

0.1U_ 0 402_16V4Z

2

1

C271

0.1U_ 0 402_16V4Z

2

1

C244

0.1U_0402_16V4Z

2

1

C256

0.1U_0402_16V4Z

2

1

C277
10U_0805_10V4Z

2

1

C272

0.1U_0402_16V4Z

2

1

C245

0.1U_ 0 402_16V4Z

2

1

C257

0.1U_ 0 402_16V4Z

2

1

C275
22U_1206_10V4Z

2

1

C246

0.1U_0402_16V4Z

2

1

C258

0.1U_0402_16V4Z

2

3

1

C247

0.1U_ 0 402_16V4Z

2

1

C259

0.1U_ 0 402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C248

0.1U_ 0 402_16V4Z

2

1

C260

0.1U_ 0 402_16V4Z

2

1

+

C280
@100U_D2_10VM

2

1

+

C282
@100U_D2_10VM

2

2

Title

Size Document Number Re v

Date: Sheet

Compal Ele c t ronics, Inc.

SCHEMATIC, M/B LA-1861

401257

七月

1

15 61星期T, 30, 2003

of

0E

5

1 2

1 2

C461

M9+/M10@0.1U_0402_16V4Z

Q72

2SC2411K_SC59

+3VS

AGP_AD[0..31]

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_ST[0..2]

R389
10_0402_5%

1 2

AGP_REQ#<10>
AGP_GNT#<10>

AGP_PAR<10>

AGP_STOP#<10>

AGP_DEVSEL#<10>

AGP_TRDY#<10>

AGP_IRDY#<10>
PCI_PIRQA#<10,25,30,33,44>
AGP_WBF#<10>
AGP_STP#<10,26>

AGP_BUSY#<10,26>

AGP_RBF#<10>
AGP_ADSTBF_0<10>
AGP_ADSTBF_1<10>
AGP_ADSTBS_0<10>
AGP_ADSTBS_1<10>

8X4X

AGP_SBSTBF<10>
AGP_SBSTBS<10>

EXTAGPREF_8X

R400 M9+/M10@137_0402_1%

+1.5VS

1 2

AGP_DBI_HI<10>
AGP_DBI_LO<10>

R403 M9+/M10@715_0603_1%

+1.8VS

R1030
470_0402_5%

1 2

CBE

123

5

1 2

AGP8X_DET#<10>

1 2

TV_CRMA<11,24,43>
TV_LUMA<11,24,43>

TV_COMPS<11,24>

R77

@10K_0402_5%

SSIN
SSOUT

R391 M9+/M10@1K_0603_5%

1 2

SUSSTAT#

R1031

10K_0402_5%

1 2

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

CLK_AGP_EXT_66M

RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#

AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTBF_0
AGP_ADSTBF_1
AGP_ADSTBS_0
AGP_ADSTBS_1

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

AGP_SBSTBF
AGP_SBSTBS

AGP_DBI_HI
AGP_DBI_LO

R393M9+/M10@1K_0402_5%

TV_CRMA
TV_LUMA
TV_COMPS

12

XTALIN

AGP_AD[0..31]<10>

AGP_SBA[0..7]<10>

AGP_CBE#[0..3]<10>

AGP_ST[0..2]<10>

D D

C451 15P_0402_50V8D

CLK_AGP_EXT_66M<23>

+3VS

C C

R1041
M9@8.2K_0402_5%

AGP_FRAME#<10>

1K_0603_1%RA324_0603_1%
1K_0603_1% 100_0603_1%

RB

+1.5VS

RA

R46
M9+/M10@324_0603_1%

1 2

B B

RB

Leave These Pin No Connecting, When
Using M10-P Int ernal Sp r ead Spe ctrum

2

1

R45

1 2

M9+/M10@100_0603_1%

If M10+P PO P 4 7_0402_1%
If M9+X POP 13 7_0402_1%

Layout & BOM update 7/10

A A

SUS_STAT#<8,26>

U7A

H29

AD0

H28

AD1

J29

AD2

J28

AD3

K29

AD4

K28

AD5

L29

AD6

L28

AD7

N28

AD8

P29

AD9

P28

AD10

R29

AD11

R28

AD12

T29

AD13

T28

AD14

U29

AD15

N25

AD16

R26

AD17

P25

AD18

R27

AD19

R25

AD20

T25

AD21

T26

AD22

U25

AD23

V27

AD24

W26

AD25

W25

AD26

Y26

AD27

Y25

AD28

AA26

AD29

AA25

AD30

AA27

AD31

N29

C/BE#0

U28

C/BE#1

P26

C/BE#2

U26

C/BE#3

AG30

PCICLK

AG28

RST#

AF28

REQ#

AD26

GNT#

M25

PAR

N26

STOP#

V29

DEVSEL#

V28

TRDY#

W29

IRDY#

W28

FRAME#

AE26

INTA#

AC26

WBF#

AH30

STP_AGP#

AH29

AGP_BUSY#

AE29

RBF#

M28

AD_STBF_0

V25

AD_STBF_1

M29

AD_STBS_0

V26

AD_STBS_1

AD28

SBA0

AD29

SBA1

AC28

SBA2

AC29

SBA3

AA28

SBA4

AA29

SBA5

Y28

SBA6

Y29

SBA7

AF29

ST0

AD27

ST1

AE28

ST2

AB29

SB_STBF

AB28

SB_STBS

M26

AGPREF

M27

AGPTEST

AB25

DBI_HI

AB26

DBI_LO

AC25

AGP8X_DET#

AE11

DMINUS

AF11

DPLUS

AK21

R2SET

AJ23

C_R

AJ22

Y_G

AK22

COMP_B

AJ24

H2SYNC

AK24

V2SYNC

AG23

DDC3CLK

AG24

DDC3DATA

AK25

SSIN

AJ25

SSOUT

AH28

XTALIN

AJ29

XTALOUT

AH27

TESTEN

AG26

SUS_STAT#

M9+/M10@SA002160E00(0301021300)

4

M10-P/(M9+X)
(1/6)

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8

ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15

ZV PORT / EX T TM DS / GPIO / ROMLVDSTMDSDAC1

ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23

ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3

PCI/AGPAGP8XCLK

TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

BLON/(BLON#)

THRM

SSC DAC2

TEST_MCLK/(NC)

TEST_YCLK/(NC)

PLLTEST/(NC)

RSTB_MSK/(NC)

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

VREFG/(NC)

ROMCS#

DVOMODE

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P

TXCLK_LN
TXCLK_LP

TXCLK_UN
TXCLK_UP

DIGON

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TXCM

TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC

VSYNC

RSET

DDC1DATA

DDC1CLK

AUXWIN

STRAP_G

AJ5

STRAP_H

AH5

STRAP_J

AJ4

STRAP_K

AK4

STRAP_D

AH4

STRAP_E

AF4

STRAP_F

AJ3

STRAP_B

AK3

STRAP_A

AH3

STRAP_O

AJ2
AH2

STRAP_L

AH1

STRAP_M

AG3

STRAP_N

AG1
AG2
AF3

XTALINSS_R

AF2

VREFG

AG4
AF5

R1002 128M@0_0402_5%

AH6

1 2
1 2

AJ6

R1003 @0_0402_5%

AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7

STRAP_R

AF7

STRAP_S

AE8
AG8
AF8

STRAP_T

AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

DVOMODE

AE10

AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19

AE12
AG12

AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13

AE13
AE14

AF12

AK27

R

AJ27

G

AJ26

B

AG25
AH25

AH26
AF25

AF24
AF26

B6
E8
AE25
AG29

R428

TXA0­TXA0+
TXA1­TXA1+
TXA2­TXA2+

TXACLK­TXACLK+
TXB0­TXB0+
TXB1­TXB1+
TXB2­TXB2+

TXBCLK­TXBCLK+

ENAVDD

1 2

R426 M9+@0_0402_5%

ENABLT

R424 M9+/M10@100K_0402_5%

CRTR_R
CRTG_R
CRTB_R
CRTHSYNC_R
CRTVSYNC_R

AGP_RSET
3VDDCDA

3VDDCCL

1 2

R380 M9+/M10@10K_0402_5%

1 2
R378
M9+/M10@1K_0603_5%

3

2

AGP, DAC & LVDS INTERFACE

+3VS

12

PWR_SEL <52>

R460 M9+/M10@0_0402_5%

1 2

+3VS

+3VS

RST#

R429

R433

R397 M9+/M10@499_0402_1%

M9+/M10@2.2K_0402_5%

M9+/M10@2.2K_0402_5%

I2C_DATA <24>
I2C_CLK <24>

@10U_0805_6.3V6M

M9+/M10@0_0402_5%

1 2

TXA0- <24>
TXA0+ <24>
TXA1- <24>
TXA1+ <24>
TXA2- <24>
TXA2+ <24>

TXACLK- <24>
TXACLK+ <24>
TXB0- <24>
TXB0+ <24>
TXB1- <24>
TXB1+ <24>
TXB2- <24>
TXB2+ <24>

TXBCLK- <24>
TXBCLK+ <24>

ENAVDD <10,24>

R369 M9+/M10@0_0402_5%

1 2

R16 M9+/M10@0_0402_5%

1 2

R14 M9+/M10@0_0402_5%

1 2

R364 M9+/M10@0_0402_5%

1 2

R362 M9+/M10@0_0402_5%

1 2

1 2

(15mil)

3VDDCDA <11,24>
3VDDCCL <11,24>

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(25 mil)

C47

ENABLT#

3

XTALIN_SS

R1028 @0_0402_5%

12

R1029

@0.1U_0402_16V4Z

@10K_0402_5%

@10K_0402_5%

12

M9+/M10@0_0402_5%

C64

12

12

R34

@10K_0402_5%

12

12

R33

R31

R32
@10K_0402_5%

Note: PLACE CLOSE TO VGA CHIP

+3VS

12

R468
M10@10K_0402_5%

ENABLT#

13

D

Q51

2

G

M10@2N7002_SOT23

S

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

PCI_RST# <25,29,30,32,33,34,38,44>

NB_RST# <8,11,25,38>

S0

S1

ENABLT# <10,24,40>

CRT_R <11,24,43>
CRT_G <11,24,43>
CRT_B <11,24,43>
CRT_HSYNC <11,24>
CRT_VSYNC <11,24>

R427
M10@1K_0603_1%

12

R425
M10@1K_0603_1%

2

U5

VDD

1

X1/CLK

7

S0

6

S1

LVDS SPREAD SPECTRUM

4

SSCLK

8

Xout

5

SSCC

GND

@SM560BS_SOIC8

3

Selection Table For W180

SS%

0
1

L9
@BLM21P300S_0805

1 2

12

R35
@0_0402_5%

1 2

R65
@22_0402_5%

12

R36
@0_0402_5%

Spread % Setting for
Freq. Range

Fin>Fout>Fin-1.25%
Fin>Fout>Fin-3.75%

2

+3VS

SSOUT

1 2

R27

1

@22_0402_5%
C30
@10P_0402_25V8K

2

SSIN

1

C63
@10P_0402_25V8K

2

Ra 180_0603_5%
Rb

+3VS

Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out

12

R24
M9+/M10@10K_0402_5%

C20

M9+/M10@0.1U_0402_16V4Z

+3VS

FREQOUT XTALIN_SS

12

R142 M9+/M10@10K_0402_5%

12

R143 M9+/M10@10K_0402_5%

1

ID_Disable

GPIO8

GPIO7

GPIO4

GPIO5

GPIO6

GPIO0

GPIO1

GPIO2

GPIO3

GPIO9

GPIO11

GPIO12

GPIO13

STRAP_A

VGA_Disable

STRAP_B

STRAP_D

STRAP_E

STRAP_F

STRAP_G

STRAP_H

STRAP_J

STRAP_K

STRAP_O

STRAP_L

STRAP_M

STRAP_N

STRAP_R

STRAP_S

STRAP_T

R451 @10K_0402_5%

R456 @10K_0402_5%

R450 @10K_0402_5%

R446 @10K_0402_5%

R457 @10K_0402_5%

R440 @10K_0402_5%
R449 @10K_0402_5%

R441 @10K_0402_5%
R442 @10K_0402_5%

R439 @10K_0402_5%
R438 @10K_0402_5%

R448 @10K_0402_5%
R447 @10K_0402_5%

R458 @10K_0402_5%

R462 @10K_0402_5%

R459 @10K_0402_5%

R463 @10K_0402_5%

R434 @10K_0402_5%

For M10-P

R435 @10K_0402_5%

R454 @10K_0402_5%
R452 @10K_0402_5%

12

12

12

12

12

12
12

12
12

12
12

12
12

12

12

12

12

12

12

12
12

M9+X M10-P

261_0603_1%

150_0402_5%

X1

4

OUT

VDD

1

GND

OE

M9+/M10@27MHZ_15P

M9+/M10@W180-01GT_SO8

3
2

U10

1

X1/CLK

7

FS1

8

FS2

150_0402_5%

FREQOUT

M9+/M10@180_0603_5%

1.5V OSC out for M9+X

1.2V OSC out for M10-P

Ra

1 2

R377

6

M9+/M10@0.1U_0402_16V4Z

VDD

CLKOUT

X2

SS%

GND

3

12

R379
M9+/M10@150_0402_5%

Rb

L17
M9+/M10@FCM2012C-800_0805

1

C165

2

5

2
4

SS%

1 2

XTALIN

1 2

C166
M9+/M10@4.7U_0805_10V4Z

R115
M9+/M10@10K_0402_5%

Note: PLACE CLOSE TO U10 (VGA M9+X/M10-P)

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

of

16 61,

1

+3VS

+3VS

0E

5

4

3

2

1

D D

R_NMDA0
R_NMDA1
R_NMDA2
R_NMDA3
R_NMDA4
R_NMDA5
R_NMDA6
R_NMDA7
R_NMDA8
R_NMDA9

C C

B B

R_NMDA10
R_NMDA11
R_NMDA12
R_NMDA13
R_NMDA14
R_NMDA15
R_NMDA16
R_NMDA17
R_NMDA18
R_NMDA19
R_NMDA20
R_NMDA21
R_NMDA22
R_NMDA23
R_NMDA24
R_NMDA25
R_NMDA26
R_NMDA27
R_NMDA28
R_NMDA29
R_NMDA30
R_NMDA31
R_NMDA32
R_NMDA33
R_NMDA34
R_NMDA35
R_NMDA36
R_NMDA37
R_NMDA38
R_NMDA39
R_NMDA40
R_NMDA41
R_NMDA42
R_NMDA43
R_NMDA44
R_NMDA45
R_NMDA46
R_NMDA47
R_NMDA48
R_NMDA49
R_NMDA50
R_NMDA51
R_NMDA52
R_NMDA53
R_NMDA54
R_NMDA55
R_NMDA56
R_NMDA57
R_NMDA58
R_NMDA59
R_NMDA60
R_NMDA61
R_NMDA62
R_NMDA63

R_NMDA[0..63]<21>

NMAA[0..13]<21>

NDQMA[0..7]<21>

NDQSA[0..7]<21>

U7B

L25

DQA0

L26

DQA1

K25

DQA2

K26

DQA3

J26

DQA4

H25

DQA5

H26

DQA6

G26

DQA7

G30

DQA8

D29

DQA9

D28

DQA10

E28

DQA11

E29

DQA12

G29

DQA13

G28

DQA14

F28

DQA15

G25

DQA16

F26

DQA17

E26

DQA18

F25

DQA19

E24

DQA20

F23

DQA21

E23

DQA22

D22

DQA23

B29

DQA24

C29

DQA25

C25

DQA26

C27

DQA27

B28

DQA28

B25

DQA29

C26

DQA30

B26

DQA31

F17

DQA32

E17

DQA33

D16

DQA34

F16

DQA35

E15

DQA36

F14

DQA37

E14

DQA38

F13

DQA39

C17

DQA40

B18

DQA41

B17

DQA42

B15

DQA43

C13

DQA44

B14

DQA45

C14

DQA46

C16

DQA47

A13

DQA48

A12

DQA49

C12

DQA50

B12

DQA51

C10

DQA52

C9

DQA53

B9

DQA54

B10

DQA55

E13

DQA56

E12

DQA57

E10

DQA58

F12

DQA59

F11

DQA60

E9

DQA61

F9

DQA62

F8

DQA63

M9+/M10@SA002160E00(0301021300)

R_NMDA[0..63]

NMAA[0..13]

NDQMA[0..7]

NDQSA[0..7]

M10-P/(M9+X)
(2/6)

AA12/(AA13)
AA13/(AA12)

AA14/(NC)

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MEMORY INTERFACE

A

CLKA0#

CLKA1#

MVREFD

MVREFS/(NC)

AA10
AA11

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA1

DIMA0

DIMA1

AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9

NMAA1

B22

NMAA2

B23

NMAA3

B24

NMAA4

C23

NMAA5

C22

NMAA6

F22

NMAA7

F21

NMAA8

C21

NMAA9

A24

NMAA10

C24

NMAA11

A25

NMAA12

E21

NMAA13

B20
C19

NDQMA0

J25

NDQMA1

F29

NDQMA2

E25

NDQMA3

A27

NDQMA4

F15

NDQMA5

C15

NDQMA6

C11

NDQMA7

E11

NDQSA0

J27

NDQSA1

F30

NDQSA2

F24

NDQSA3

B27

NDQSA4

E16

NDQSA5

B16

NDQSA6

B11

NDQSA7

F10

NMRASA#

A19

NMCASA#

E18

NMWEA#

E19

NMCSA0#

E20

NMCSA1#

F20

NMCKEA

B19

NMCLKA0

B21

NMCLKA0#

C20

NMCLKA1

C18

NMCLKA1#

A18
D30

B13

MVREFD

B7

MVREFS

B8

NMRASA# <21>
NMCASA# <21>

NMWEA# <21>
NMCSA0# <21>
NMCSA1# <21>

NMCKEA <21>

NMCLKA0 <21>
NMCLKA0# <21>

NMCLKA1 <21>
NMCLKA1# <21>

NMAA0

E22

MEMORY INTERFACE A

+2.5VS

12

R431
M9+/M10@1K_0402_1%

MVREFD

M9+/M10@0.1U_0402_16V4Z

MVREFS

M10@0.1U_0402_16V4Z

Poped for M10-P
Depoped for
M9+X

C542

C543

1

2

1

2

(25 mil)

(25 mil)

12

R430
M9+/M10@1K_0402_1%

+2.5VS

12

R437
M10@1K_0402_1%

12

R436
M10@1K_0402_1%

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

0E

of

17 61,

1

5

D D

4

3

2

1

MEMORY INTERFACE B

R_NMDB[0..63]<22>

NMAB[0..13]<22>

NDQMB[0..7]<22>

NDQSB[0..7]<22>

C C

B B

R_NMDB[0..63]

NMAB[0..13]

NDQMB[0..7]

NDQSB[0..7]

R_NMDB0
R_NMDB1
R_NMDB2
R_NMDB3
R_NMDB4
R_NMDB5
R_NMDB6
R_NMDB7
R_NMDB8
R_NMDB9
R_NMDB10
R_NMDB11
R_NMDB12
R_NMDB13
R_NMDB14
R_NMDB15
R_NMDB16
R_NMDB17
R_NMDB18
R_NMDB19
R_NMDB20
R_NMDB21
R_NMDB22
R_NMDB23
R_NMDB24
R_NMDB25
R_NMDB26
R_NMDB27
R_NMDB28
R_NMDB29
R_NMDB30
R_NMDB31
R_NMDB32
R_NMDB33
R_NMDB34
R_NMDB35
R_NMDB36
R_NMDB37
R_NMDB38
R_NMDB39
R_NMDB40
R_NMDB41
R_NMDB42
R_NMDB43
R_NMDB44
R_NMDB45
R_NMDB46
R_NMDB47
R_NMDB48
R_NMDB49
R_NMDB50
R_NMDB51
R_NMDB52
R_NMDB53
R_NMDB54
R_NMDB55
R_NMDB56
R_NMDB57
R_NMDB58
R_NMDB59
R_NMDB60
R_NMDB61
R_NMDB62
R_NMDB63

U7C

M10-P/(M9+X)

D7

DQB0

F7

(3/6)

DQB1

E7

DQB2

G6

DQB3

G5

DQB4

F5

DQB5

E5

DQB6

C4

DQB7

B5

DQB8

C5

DQB9

A4

DQB10

B4

DQB11

C2

DQB12

D3

DQB13

D1

DQB14

D2

DQB15

G4

DQB16

H6

DQB17

H5

DQB18

J6

DQB19

K5

DQB20

K4

DQB21

L6

DQB22

L5

DQB23

G2

DQB24

F3

DQB25

H2

DQB26

E2

DQB27

F2

DQB28

J3

DQB29

F1

DQB30

H3

DQB31

U6

DQB32

U5

DQB33

U3

DQB34

V6

DQB35

W5

DQB36

W4

DQB37

Y6

DQB38

Y5

DQB39

U2

DQB40

V2

DQB41

V1

DQB42

V3

DQB43

W3

DQB44

Y2

DQB45

Y3

DQB46

AA2

DQB47

AA6

DQB48

AA5

DQB49

AB6

DQB50

AB5

DQB51

AD6

DQB52

AD5

DQB53

AE5

DQB54

AE4

DQB55

AB2

DQB56

AB3

DQB57

AC2

DQB58

AC3

DQB59

AD3

DQB60

AE1

DQB61

AE2

DQB62

AE3

DQB63

M9+/M10@SA002160E00(0301021300)

MEMORY INTERFACE B

MEMVMODE0
MEMVMODE1

AB10

AB11
AB12/(AB13)
AB13/(AB12)

AB14/(NC)

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB0
DIMB1

MEMTEST

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9

NMAB1

M1

NMAB2

M3

NMAB3

L3

NMAB4

L2

NMAB5

M2

NMAB6

M5

NMAB7

P6

NMAB8

N3

NMAB9

K2

NMAB10

K3

NMAB11

J2

NMAB12

P5

NMAB13

P3
P2

NDQMB0

E6

NDQMB1

B2

NDQMB2

J5

NDQMB3

G3

NDQMB4

W6

NDQMB5

W2

NDQMB6

AC6

NDQMB7

AD2

NDQSB0

F6

NDQSB1

B3

NDQSB2

K6

NDQSB3

G1

NDQSB4

V5

NDQSB5

W1

NDQSB6

AC5

NDQSB7

AD1

NMRASB#

R2

NMCASB#

T5

NMWEB#

T6

NMCSB0#

R5

NMCSB1#

R6

NMCKEB

R3

NMCLKB0

N1

NMCLKB0#

N2

NMCLKB1

T2

NMCLKB1#

T3

R444 M9+/M10@4.7K_0402_5%

C6

1 2

R445 M9+/M10@4.7K_0402_5%

1 2

C7
E3

AA3

R432 M9+/M10@47_0603_1%

1 2

C8

NMAB0

N5

NMRASB# <22>
NMCASB# <22>
NMWEB# <22>
NMCSB0# <22>
NMCSB1# <22>
NMCKEB <22>
NMCLKB0 <22>

NMCLKB0# <22>
NMCLKB1 <22>

NMCLKB1# <22>

+1.8VS

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF

R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

0E

of

18 61,

1

5

4

3

2

1

+3VS

1

U7D

M10-P/(M9+X)

VDDR1

(4/6)

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)

VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)

TPVDD
TPVSS

AVDD
A2VDD
A2VDD
A2VDDQ

A2VSSN
A2VSSN
A2VSSQ

AVSSN
AVSSQ

M9+/M10@SA002160E00(0301021300)

I/O POWER

LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)

VDDRH0
VDDRH1

VSSRH0
VSSRH1

MPVDD

MPVSS

PVDD
PVSS

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3

VDDR4
VDDR4
VDDR4
VDDR4
VDDR4

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

LVDDR_18
LVDDR_18

LPVDD

LVSSR
LVSSR
LVSSR
LVSSR
LPVSS

VDD1DI
VDD2DI

VSS1DI
VSS2DI

TXVDDR
TXVDDR

TXVSSR
TXVSSR
TXVSSR

+VDDC15

AD4

AC11
AC20

AK12

AJ12

AH24

AG21

AH21
AF22

AH22

AJ21

AF23

AH23
AD24

B1
B30
A15
A21
A28

A3

A9
AA1
AA4
AA7
AA8

D5

D8
D11
D13
D14
D17
D20
D23
D26
E27

F4

G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22

J1
J23
J24

J4

J7

J8

L27

L8
M4
N4
N7
N8
R1

T4

T7

T8

V4

V7

V8

D19

R4

H11
H20
L23

P8

Y23

Y8

D D

C C

+2.5VS

+1.5VS

Poped for M10-P

+2.5VS

Poped for
M10-P

R412 M10@0_0402_5%

1 2

R422 M10@0_0402_5%

1 2

1 2
R411
M10@0_0805_5%

Poped for M9+X

B B

A A

+1.8VS

1 2
R406
M9+@0_0805_5%

+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_DAC2.5

+VDD_DAC1.8

F18
N6

F19
M6

A7
A6

AK28
AJ28

AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7

AC10
AC9
AD10
AD9
AG7

AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27

AE20
AE17
AF21
AE15
AJ20

AF20
AF15
AE19
AE16
AJ19

AE24
AE22

AE23
AE21

AF13
AF14

AG13
AG14
AH12

+2.5VDDRH

1 2
1 2

+VDD_MEMPLL1.8

+VDD_PLL1.8

+3VS

+1.5VS

Poped for M10-P

R419

M10@0_0805_5%

R423

M9+@0_0805_5%

Poped for M9+X

+VDD_PNLIO1.8
+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_PNLIO1.8

M9+/M10@22U_1206_10V4Z

M9+/M10@22U_1206_10V4Z

M9+/M10@10U_0805_6.3V6M

M9+/M10@10U_0805_6.3V6M

+VDD_PNLIO2.5

+VDD_PNLIO1.8

M9+/M10@10U_0805_6.3V6M

M9+/M10@10U_0805_6.3V6M

C175

2

M9+/M10@0.1U_0402_16V4Z

+1.5VS

1

C24

2

M9+/M10@0.1U_0402_16V4Z

+VDD_DAC2.5

(20 mil)

1

C105

2

+VDD_PNLPLL1.8

(20 mil)

1

C145

2

M9+/M10@10U_0805_6.3V6M

+VDD_PNLIO1.8

(20 mil)

1

C530

2

+VDD_PNLIO2.5

(20 mil)

1

C496

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

1

C449

C472

C140

M9+/M10@0.1U_0402_16V4Z

+VDD_DAC1.8

C96

C510

M9+/M10@0.1U_0402_16V4Z

C501

C454

2

M9+/M10@0.1U_0402_16V4Z

1

C471

2

L14
M9+/M10@CHB1608U301_0603

1 2

1

C488
M9+/M10@0.1U_0402_16V4Z

2

1

2

(20 mil)

1

2

M9+/M10@0.1U_0402_16V4Z

1

C506

2

1

2

1

2

1

2

1

C143
M9+/M10@0.1U_0402_16V4Z

2

1

C493
M9+/M10@0.1U_0402_16V4Z

2

1

2

1

C502
M9+/M10@0.1U_0402_16V4Z

2

1

C458

2

M9+/M10@0.01U_0402_16V7K

1

C470

2

M9+/M10@0.01U_0402_16V7K

+2.5VS

L15
M9+/M10@CHB1608U301_0603

1 2

L11
M9+/M10@CHB1608U301_0603

1 2

1

C490
M9+/M10@0.1U_0402_16V4Z

2

L43
M9+/M10@CHB1608U301_0603

1 2

1

C477
M9+/M10@0.01U_0402_16V7K

2

M9+/M10@0.01U_0402_16V7K

1

C469

2

M9+/M10@1U_0603_10V4Z

+1.8VS

M9+/M10@10U_0805_6.3V6M

+1.8VS

L41
M9+/M10@CHB1608U301_0603

1 2

+2.5VS

POWER
INTERFACE

M9+/M10@0.1U_0402_16V4Z

1

C824

M9+/M10@0.1U_0402_16V4Z

+VDD_MEMPLL1.8

+1.8VS

M9+/M10@0.1U_0402_16V4Z

2

+2.5VDDRH

(20 mil)

1

C513

2

+VDD_PLL1.8

(20 mil)

1

C78

2

(20 mil)

1

C540
M9+/M10@0.1U_0402_16V4Z

2

C825

1

2

L42
M9+/M10@CHB1608U301_0603

1 2

1

C541
M9+/M10@0.1U_0402_16V4Z

2

L12
M9+/M10@CHB1608U301_0603

1 2

1

C77
M9+/M10@0.1U_0402_16V4Z

2

L46
M9+/M10@CHB1608U301_0603

1 2

+VDDC15

M9+/M10@0.1U_0402_16V4Z

1

1

C816

C815

2

2

1

C826
M9+/M10@0.1U_0402_16V4Z

2

+2.5VS

+1.8VS

+1.8VS

1

1

C828

C827

M9+/M10@0.1U_0402_16V4Z

2

2

M9+/M10@0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

0E

of

19 61,

1

5

U7E

M10-P/(M9+X)
(5/6)

A10

VSS

A16

D D

C C

+VGA_CORE

1

B B

A A

M9+/M10@22U_1206_10V4Z

M9+/M10@22U_1206_10V4Z

M9+/M10@22U_1206_10V4Z

C526

2

M9+/M10@22U_1206_10V4Z

+2.5VS

1

C528

2

+2.5VS

M9+/M10@0.1U_0402_16V4Z

1

C505

2

M9+/M10@0.1U_0402_16V4Z

VSS

A2

VSS

A22

VSS

A29

VSS

AA30

VSS

AB1

VSS

AB23

VSS

AB24

VSS

AB27

VSS

AB4

VSS

AB7

VSS

AB8

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC4

VSS

AD12

VSS

AD16

VSS

AD18

VSS

AD25

VSS

AD30

VSS

AE27

VSS

AG11

VSS

AG15

VSS

AG18

VSS

AG22

VSS

AG27

VSS

AG5

VSS

AG9

VSS

AJ1

VSS

AJ30

VSS

AK2

VSS

AK29

VSS

C1

VSS

C28

VSS

C3

VSS

C30

VSS

D10

VSS

D12

VSS

D15

VSS

D18

VSS

D21

VSS

D24

VSS

D25

VSS

D27

VSS

D4

VSS

D6

VSS

D9

VSS

E4

VSS

F27

VSS

M9+/M10@SA002160E00(0301021300)

M9+/M10@0.1U_0402_16V4Z

1

2

1

2

1

2

1

C527

2

1

C512

2

M9+/M10@0.1U_0402_16V4Z

1

C485

2

M9+/M10@0.1U_0402_16V4Z

CORE POWER

M9+/M10@0.1U_0402_16V4Z

1

C503

M9+/M10@0.1U_0402_16V4Z

C509

M9+/M10@0.1U_0402_16V4Z

C473

C511

2

M9+/M10@0.1U_0402_16V4Z

1

C554

2

M9+/M10@0.1U_0402_16V4Z

1

C459

2

4

H4

VSS

H8

VSS

H9

VSS

H12

VSS

H14

VSS

H18

VSS

H21

VSS

H23

VSS

H27

VSS

K1

VSS

K23

VSS

K24

VSS

K27

VSS

K30

VSS

K7

VSS

K8

VSS

L4

VSS

M30

VSS

M7

VSS

M8

VSS

N23

VSS

N24

VSS

N27

VSS

P4

VSS

R23

VSS

R24

VSS

R30

VSS

R7

VSS

R8

VSS

T1

VSS

T27

VSS

U23

VSS

U4

VSS

U8

VSS

V30

VSS

W23

VSS

W24

VSS

W27

VSS

W7

VSS

W8

VSS

Y4

VSS

G9

VSS

G12

VSS

G16

VSS

G18

VSS

G21

VSS

G24

VSS

1

C498

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

1

C553

2

M9+/M10@0.1U_0402_16V4Z

1

C457

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.01U_0402_16V7K

1

2

1

2

1

2

1

C487

2

1

C552

2

M9+/M10@0.01U_0402_16V7K

1

C533

2

M9+/M10@0.01U_0402_16V7K

POWER
INTERFACE

M9+/M10@0.01U_0402_16V7K

1

C480

M9+/M10@0.01U_0402_16V7K

C551

C534

C479

2

1

C550
M9+M10@0.01U_0402_16V7K

2

1

C535
M9+/M10@0.01U_0402_16V7K

2

3

1

2

1

C514

M9+/M10@0.01U_0402_16V7K

M9+/M10@22U_1206_10V4Z

C520

2

+VGA_CORE_CI

1

C497

2

2

+VGA_CORE

(20 mil)

M9+/M10@10U_0805_6.3V6M

U7F

M10-P/(M9+X)

M12

(6/6)

VDDC

M13

VDDC

M14

VDDC

M17

VDDC

M18

VDDC

M19

VDDC

N12

VDDC

N13

VDDC

N14

VDDC

N17

VDDC

N18

VDDC

N19

VDDC

P12

VDDC

P13

VDDC

P14

VDDC

P17

VDDC

P18

VDDC

P19

VDDC

U12

VDDC

U13

VDDC

U14

VDDC

U17

VDDC

U18

VDDC

U19

VDDC

V12

VDDC

V13

VDDC

V14

VDDC

V17

VDDC

V18

VDDC

V19

VDDC

W12

VDDC

W13

VDDC

W14

VDDC

W17

VDDC

W18

VDDC

W19

VDDC

AB22

VDDC

AB9

VDDC

J10

VDDC

J12

VDDC

J14

VDDC

J15

VDDC

J16

VDDC

J17

VDDC

J19

VDDC

J21

VDDC

K22

VDDC

K9

VDDC

M22

VDDC

M9

VDDC

P22

VDDC

P9

VDDC

R22

VDDC

R9

VDDC

T22

VDDC

T9

VDDC

U22

VDDC

U9

VDDC

V22

VDDC

V9

VDDC

Y22

VDDC

Y9

VDDC

M9+/M10@SA002160E00(0301021300)

M9+/M10@0.1U_0402_16V4Z

1

2

C517

1

2

C515

M10-P&M9+X
COMMON

CORE POWER

M10-P
ONLY

M9+X
ONLY

1

2

As close as possible to related pin

AD15

VDDC

AD13

VDDC

AC17

VDDC

AC15

VDDC

AC13

VDDC

T12

VDDCI

M15

VDDCI

W16

VDDCI

R19

VDDCI

R12

VSS

R13

VSS

T13

VSS

R14

VSS

T14

VSS

N15

VSS

P15

VSS

R15

VSS

T15

VSS

U15

VSS

V15

VSS

W15

VSS

H16

VSS

M16

VSS

N16

VSS

P16

VSS

R16

VSS

T16

VSS

U16

VSS

V16

VSS

R17

VSS

T17

VSS

R18

VSS

T18

VSS

T19

VSS

AA22

VSS

AA9

VSS

J11

VSS

J13

VSS

J18

VSS

J20

VSS

J22

VSS

J9

VSS

L22

VSS

L9

VSS

N22

VSS

N9

VSS

W22

VSS

W9

VSS

L44
M9+/M10@CHB1608U301_0603

1 2

C508
M9+/M10@0.1U_0402_16V4Z

+VGA_CORE

480MIL

+VGA_CORE_CI

+VGA_CORE

VGA_CORE for M10P

1.2

1.0

1

VGA_CORE for M9+

1.5V

1.25V

As close as possible to related pin

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

0E

of

20 61,

1

5

+2.5VS +2.5VS

M9+/M10@22U_1206_10V4Z

1

M9+/M10@22U_1206_10V4Z

D D

NMAA[0..13]<17>

R_NMDA[0..63]<17>

2

NMAA[0..13] NDQMA[0..7]

R_NMDA[0..63]

1

C129

C109

2

M9+/M10@0.1U_0402_16V4Z

As close as ppossible to related pin

M9+/M10@0.1U_0402_16V4Z

C100

1

2

NDQMA[0..7]<17>

NDQSA[0..7]<17>

1

2

C117

M9+/M10@0.1U_0402_16V4Z

4

M9+/M10@0.1U_0402_16V4Z

1

2

NDQSA[0..7]

1

C87

2

M9+/M10@0.01U_0402_16V7K

C108

C116

M9+/M10@0.01U_0402_16V7K

VGA DDR FOR
CHANNEL A

C101

C88

M9+/M10@0.01U_0402_16V7K

3

M9+/M10@22U_1206_10V4Z

1

M9+/M10@22U_1206_10V4Z

C156

2

2

1

2

1

C171

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

1

C153

C154

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

C158

1

2

1

2

1

M9+/M10@0.01U_0402_16V7K

C163

C155

M9+/M10@0.01U_0402_16V7K

C159

C152

M9+/M10@0.01U_0402_16V7K

As close as ppossible to related pin

NMAA13
NMAA12
NMAA11
NMAA10
NMAA9
NMAA8
NMAA7
NMAA6
NMAA5
NMAA4
NMAA3
NMAA2
NMAA1

C C

+2.5VS

R98
M9+/M10@1K_0402_1%

1 2

R99

1 2

M9+/M10@1K_0402_1%

B B

NMCLKA0<17>

NMCLKA0#<17> NMCLKA1#<17>

A A

NMCSA1#<17>

M9+/M10@0.1U_0402_16V4Z

C130

NMCLKA0

R93
M9+/M10@56.2_0402_1%

C125M9+/M10@470P_0402_50V7K

R92

NMCLKA0#

M9+/M10@56.2_0402_1%

R1006 128M@0_0402_5%

NMRASA#<17>
NMCASA#<17>
NMWEA#<17>
NMCSA0#<17>

NMCKEA<17>

NMAA0
NDQMA1

NDQMA2
NDQMA0
NDQMA3

NDQSA1
NDQSA2
NDQSA0
NDQSA3

NMCSA1M# NMCSA1M#

1 2

VREF_1

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

NMCKEA

U29

N4

BA0

M5

BA1

M7

A11

L6

A10

M8

A9

N11

A8

N10

A7

N9

A6

M9

A5

N8

A4

N7

A3

M6

A2

N6

A1

N5

A0

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

C4

NC1

C11

NC2

H4

NC3

H11

NC4

L12

NC5

L13

NC6

M3

NC7

M4

NC8

N3

NC9

L9

NC10/A12

M10

NC11/BA2

N13

VREF

M13

MCL

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#

N12

CKE

M11

CK

M12

CK#

E5

VSS

E7

VSS

E8

VSS

E10

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G6

VSS

G7

VSS

G8

VSS

G9

VSS

H6

VSS

H7

VSS

H8

VSS

H9

VSS

J6

VSS

J7

VSS

J8

VSS

J9

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

R_NMDA11

B7

R_NMDA9

C6

R_NMDA10

B6

R_NMDA8 R_NMDA52

B5

R_NMDA15

C2

R_NMDA14

D3

R_NMDA13

D2

R_NMDA12

E2

R_NMDA23

K13

R_NMDA22

K12

R_NMDA21

J13

R_NMDA20

J12

R_NMDA19

G13

R_NMDA18

G12

R_NMDA17

F13

R_NMDA16

F12

R_NMDA6

F3

R_NMDA7

F2

R_NMDA4

G3

R_NMDA5

G2

R_NMDA2

J3

R_NMDA3

J2

R_NMDA1

K2

R_NMDA0

K3

R_NMDA31

E13

R_NMDA30

D13

R_NMDA28

D12

R_NMDA29

C13

R_NMDA27

B10

R_NMDA25

B9

R_NMDA26

C9

R_NMDA24

B8
C3

C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

+2.5VS

R123
M9+/M10@1K_0402_1%

1 2

(25mil)(25mil)

R128
M9+/M10@1K_0402_1%

1 2

NMCLKA1<17>

M9+/M10@470P_0402_50V7K

NMCLKA1

C146

NMCLKA1#

M9+/M10@0.1U_0402_16V4Z

C147

R126
M9+/M10@56.2_0402_1%

R127
M9+/M10@56.2_0402_1%

NMAA13
NMAA12
NMAA11
NMAA10
NMAA9
NMAA8
NMAA7
NMAA6
NMAA5
NMAA4
NMAA3
NMAA2
NMAA1
NMAA0

NDQMA6
NDQMA4
NDQMA5
NDQMA7

NDQSA6
NDQSA4
NDQSA5
NDQSA7

VREF_2

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

NMCKEA

U30

N4

BA0

M5

BA1

M7

A11

L6

A10

M8

A9

N11

A8

N10

A7

N9

A6

M9

A5

N8

A4

N7

A3

M6

A2

N6

A1

N5

A0

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

C4

NC1

C11

NC2

H4

NC3

H11

NC4

L12

NC5

L13

NC6

M3

NC7

M4

NC8

N3

NC9

L9

NC10/A12

M10

NC11/BA2

N13

VREF

M13

MCL

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#

N12

CKE

M11

CK

M12

CK#

E5

VSS

E7

VSS

E8

VSS

E10

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G6

VSS

G7

VSS

G8

VSS

G9

VSS

H6

VSS

H7

VSS

H8

VSS

H9

VSS

J6

VSS

J7

VSS

J8

VSS

J9

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

R_NMDA55

B7

R_NMDA53

C6

R_NMDA54

B6
B5

R_NMDA50

C2

R_NMDA51

D3

R_NMDA49

D2

R_NMDA48

E2

R_NMDA34

K13

R_NMDA35

K12

R_NMDA32

J13

R_NMDA33

J12

R_NMDA39

G13

R_NMDA38

G12

R_NMDA36

F13

R_NMDA37

F12

R_NMDA47

F3

R_NMDA46

F2

R_NMDA45

G3

R_NMDA44

G2

R_NMDA43

J3

R_NMDA42

J2

R_NMDA40

K2

R_NMDA41

K3

R_NMDA63

E13

R_NMDA62

D13

R_NMDA60

D12

R_NMDA61

C13

R_NMDA59

B10

R_NMDA57

B9

R_NMDA58

C9

R_NMDA56

B8
C3

C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

+2.5VS+2.5VS

M9+/M10@K4D263238A_FBGA144

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M9+/M10@K4D263238A_FBGA144

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

of

21 61,

1

0E

5

+2.5VS

1

M9+/M10@22U_1206_10V4Z

D D

2

M9+/M10@22U_1206_10V4Z

C207

M9+/M10@0.1U_0402_16V4Z

C215

1

C212

2

M9+/M10@0.1U_0402_16V4Z

1

2

M9+/M10@0.1U_0402_16V4Z

1

2

C199

1

2

C192

M9+/M10@0.1U_0402_16V4Z

As close as ppossible to related pin As close as ppossible to related pin

4

M9+/M10@0.01U_0402_16V7K

C191

1

C209

2

M9+/M10@0.01U_0402_16V7K

1

2

M9+/M10@0.01U_0402_16V7K

1

C213

2

3

1

C197

2

M9+/M10@22U_1206_10V4Z

+2.5VS

1

C204

2

M9+/M10@22U_1206_10V4Z

1

2

2

M9+/M10@0.1U_0402_16V4Z

1

C186

C194

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

C211

1

2

1

2

M9+/M10@0.01U_0402_16V7K

1

C208

M9+/M10@0.1U_0402_16V4Z

C196

2

1

1

2

1

C195

2

M9+/M10@0.01U_0402_16V7K

M9+/M10@0.01U_0402_16V7K

1

C193

C210

2

VGA DDR FOR
CHANNEL B

NMAB[0..13]<18>

R_NMDB[0..63]<18>

R_NMDB[0..63]

NDQMB[0..7]<18>

NDQSB[0..7]<18>

NDQMB[0..7]NMAB[0..13]

NDQSB[0..7]

NMAB13
NMAB12
NMAB11
NMAB10
NMAB9
NMAB8
NMAB7
NMAB6
NMAB5
NMAB4
NMAB3
NMAB2
NMAB1

C C

+2.5VS

R181
M9+/M10@1K_0402_1%

1 2

(25mil)

R182

1 2

M9+/M10@1K_0402_1%

B B

A A

C216

NMCLKB0<18>

C214
M9+/M10@470P_0402_50V7K

NMCLKB0#<18>

NMCSB1#<18>

M9+/M10@0.1U_0402_16V4Z

NMCLKB0 NMCLKB1

NMCLKB0#

5

R1007 128M@0_0402_5%

NMRASB#<18>
NMCASB#<18>
NMWEB#<18>
NMCSB0#<18>

NMCKEB<18>

R178
M9+/M10@56.2_0402_1%

R180
M9+/M10@56.2_0402_1%

NMAB0
NDQMB0

NDQMB3
NDQMB2
NDQMB1

NDQSB0
NDQSB3
NDQSB2
NDQSB1

NMCSB1M# NMCSB1M#

1 2

VREF_3

NMRASB#
NMCASB#
NMWEB#

NMCKEB

U35

N4

BA0

M5

BA1

M7

A11

L6

A10

M8

A9

N11

A8

N10

A7

N9

A6

M9

A5

N8

A4

N7

A3

M6

A2

N6

A1

N5

A0

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

C4

NC1

C11

NC2

H4

NC3

H11

NC4

L12

NC5

L13

NC6

M3

NC7

M4

NC8

N3

NC9

L9

NC10/A12

M10

NC11/BA2

N13

VREF

M13

MCL

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#

N12

CKE

M11

CK

M12

CK#

E5

VSS

E7

VSS

E8

VSS

E10

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G6

VSS

G7

VSS

G8

VSS

G9

VSS

H6

VSS

H7

VSS

H8

VSS

H9

VSS

J6

VSS

J7

VSS

J8

VSS

J9

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

M9+/M10@K4D263238A_FBGA144

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

R_NMDB7

B7

R_NMDB5

C6

R_NMDB6

B6

R_NMDB4

B5

R_NMDB2

C2

R_NMDB3

D3

R_NMDB1

D2

R_NMDB0

E2

R_NMDB30

K13

R_NMDB31

K12

R_NMDB28

J13

R_NMDB29

J12

R_NMDB27

G13

R_NMDB26

G12

R_NMDB25

F13

R_NMDB24

F12

R_NMDB19

F3

R_NMDB18

F2

R_NMDB17

G3

R_NMDB16

G2

R_NMDB22

J3

R_NMDB23

J2

R_NMDB21

K2

R_NMDB20

K3

R_NMDB15

E13

R_NMDB14

D13

R_NMDB12

D12

R_NMDB13

C13

R_NMDB11

B10

R_NMDB10

B9

R_NMDB9

C9

R_NMDB8

B8
C3

C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

4

+2.5VS +2.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+2.5VS

R170
M9+/M10@1K_0402_1%

1 2

(25mil)

R169

1 2

M9+/M10@1K_0402_1%

NMCLKB1<18>

M9+/M10@470P_0402_50V7K

NMCLKB1#<18>

3

M9+/M10@0.1U_0402_16V4Z

C187

C190

NMCLKB1#

R172
M9+/M10@56.2_0402_1%

R171
M9+/M10@56.2_0402_1%

VREF_4

NMAB13
NMAB12
NMAB11
NMAB10
NMAB9
NMAB8
NMAB7
NMAB6
NMAB5
NMAB4
NMAB3
NMAB2
NMAB1
NMAB0

NDQMB7
NDQMB4
NDQMB5
NDQMB6

NDQSB7
NDQSB4
NDQSB5
NDQSB6

NMRASB#
NMCASB#
NMWEB#
NMCSB0#NMCSB0#

NMCKEB

U34

N4

BA0

M5

BA1

M7

A11

L6

A10

M8

A9

N11

A8

N10

A7

N9

A6

M9

A5

N8

A4

N7

A3

M6

A2

N6

A1

N5

A0

B3

DM0

H12

DM1

H3

DM2

B12

DM3

B2

DQS0

H13

DQS1

H2

DQS2

B13

DQS3

C4

NC1

C11

NC2

H4

NC3

H11

NC4

L12

NC5

L13

NC6

M3

NC7

M4

NC8

N3

NC9

L9

NC10/A12

M10

NC11/BA2

N13

VREF

M13

MCL

M2

RAS#

L2

CAS#

L3

WE#

N2

CS#

N12

CKE

M11

CK

M12

CK#

E5

VSS

E7

VSS

E8

VSS

E10

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G6

VSS

G7

VSS

G8

VSS

G9

VSS

H6

VSS

H7

VSS

H8

VSS

H9

VSS

J6

VSS

J7

VSS

J8

VSS

J9

VSS

K6

VSS

K7

VSS

K8

VSS

K9

VSS

L5

VSS

L10

VSS

M9+/M10@K4D263238A_FBGA144

2

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

R_NMDB63

B7

R_NMDB61

C6

R_NMDB62

B6

R_NMDB60

B5

R_NMDB58

C2

R_NMDB59

D3

R_NMDB57

D2

R_NMDB56

E2

R_NMDB34

K13

R_NMDB35

K12

R_NMDB32

J13

R_NMDB33

J12

R_NMDB39

G13

R_NMDB38

G12

R_NMDB37

F13

R_NMDB36

F12

R_NMDB47

F3

R_NMDB46

F2

R_NMDB45

G3

R_NMDB44

G2

R_NMDB42

J3

R_NMDB43

J2

R_NMDB41

K2

R_NMDB40

K3

R_NMDB55

E13

R_NMDB54

D13

R_NMDB52

D12

R_NMDB53

C13

R_NMDB51

B10

R_NMDB49

B9

R_NMDB50

C9

R_NMDB48

B8
C3

C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

D7
D8
E4
E11
L4
L7
L8
L11

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

of

22 61,

1

0E

A

1 1

+3VS +3VS

12

R644
1K_0402_5%

PCICLK_RSTP# CPUCLK_RSTP#

2 2

B

12

R694
1K_0402_5%

VTT_PWRGD<26,42>

CPUSTOP#<11>

PCICLK_STP#<25>

PCICLK_STP#

CLK_SB_48M<26>

REFCLK1_NB<11>
CLK_14M_SIO<38>

CLK_14M_CODEC<35>

CLK_SB_14M<26>

CLK_14M_APIC<25>

C

C707
10P_0402_50V8K

C703
10P_0402_50V8K

SMB_CK_CLK1<14,26>
SMB_CK_DAT1<14,26>

R688 @0_0402_5%
R649 @0_0402_5%
R596 10K_0402_5%

R595 33_0402_5%

R666 68_0402_5%
R676 33_0402_5%
R681 33_0402_5%
R701 33_0402_5%
R663 33_0402_5%

12

14.31818MHZ_20P_6X1430004201

1 2
1 2
1 2

XTALIN_CLK

Y6

XTALOUT_CLK

R643
475_0402_1%

+3VS

HB-1M2012-121JT03_0805

SMB_CK_CLK1
SMB_CK_DAT1

CPUCLK_RSTP#
PCICLK_RSTP#

24/48#

PCI33/66#

CLK_48M

FS2
FS1

FS0

CLK_IREF

L49

1 2

U40

6

XIN

7

XOUT

35

SCLK

34

SDATA

10

VTTPWRGD/PD#

45

CPU_STP#

12

PCI_STOP#

26

24/48#SEL

11

PCI33/66#SEL

27

48MHz_1

28

48MHz_0

4

FS2/REF2

3

FS1/REF1

2

FS0/REF0

38

IREF

D

+3V_CLK

Width=40 mils

C718

10U_0805_10V4Z

42

13

19

30

48

29

VDDSD

VDDPCI

VDDPCI

VDD48M

VDDAGP

VDDCPU

9

1

VDDREF

VDDXTAL

SDRAMOUT

AGPCLK0
AGPCLK1

FS3/PCICLK_F0
FS4/PCICLK_F1

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

0.1U_0402_16V4Z

VDDA

VSSA

CPUT0

CPUC0
CPUT1

CPUC1

1

2

36

37
40

39
44

43
47
32

31
14

15

16
17
20
21
22
23

E

CLK_BCLK
CLK_BCLK#

0.1U_0402_16V4Z

1

C665

2

+3V_VDD

1

C678

0.1U_0402_16V4Z

2

CLK_BCLK

CLK_BCLK#
CLK_NB

CLK_NB#
MEM_66M
AGP_66M

AGP_EXT_66M
FS3

FS4

R665 @0_0402_5%
R656 @0_0402_5%

0.1U_0402_16V4Z

C658

C664

0.1U_0402_16V4Z

L48
BLM21A601SPT_0805

1 2

C677
10U_0805_10V4Z

R662 33_0402_5%

R646
R680 33_0402_5%

R675
R695 33_0402_5%
R616 33_0402_5%

R607 33_0402_5%
R635 33_0402_5%

33_0402_5%

33_0402_5%

F

CK_ITP <5>
CK_ITP# <5>

0.1U_0402_16V4Z

1

1

2

C716

C717

2

0.1U_0402_16V4Z

+3VS

CK_BCLK

R661 49.9_0402_1%
R655 49.9_0402_1%

CK_BCLK#

R679 49.9_0402_1%

R674 49.9_0402_1%

1

C657

2

0.1U_0402_16V4Z

CK_BCLK <4>

CK_BCLK# <4>
CLK_NB_BCLK <11>

CLK_NB_BCLK# <11>
CLK_MEM_66M <11>
CLK_AGP_66M <11>

CLK_AGP_EXT_66M <16>
CLK_ALINK_SB <25>

1

C675

2

0.1U_0402_16V4Z

1

2

C668

G

+3V_CLK

12

R617
@10K_0402_5%

12

R608

10K_0402_5%

H

GNDREF5GNDXTAL

GNDPCI

GNDPCI

GNDSD

GNDCPU

GND48M

GNDAGP

18

24

25

33

D34
D35

ICS951402AGT_TSSOP48

46

41

10K_0402_5%

RB751V_SOD323

21
21

RB751V_SOD323

R699

+3V_CLK

1 2

E

R703
10K_0402_5%

1 2

4.7K_0402_5%

1 2
1 2

4.7K_0402_5%

R700

R689

12

R966

@10K_0402_5%

12

R967

@10K_0402_5%

F

+3V_CLK

12

R664

@10K_0402_5%

FS0
FS1

FS2
FS3
PCI33/66#

12

R667

10K_0402_5%

Title

Size Docu ment Number Re v

Date: Sheet

星期三 七月

G

12

R645

@10K_0402_5%

12

R636

10K_0402_5%

12

R657

10K_0402_5%

12

R650

@10K_0402_5%

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1861

401257

30, 2003

23 61,

H

0E

of

8

3 3

CLOCK FREQUENCY SELECT TABLE

FS2 MEMFS1

FS3

FS4

0 0 0 1 0
0 0 0 0 1
0 0 0 0 0

Note: 0 = P ULL LOW

4 4

1 = PULL HIGH

A-LINK FREQ

PCI33/66# = HIGH

PCI33/66# = LOW

A

66MHZ

33MHZ

FS0

CPU

200
133
100

With Spread Enabled…

200

*

Spreaf OFF OR

133
100

Center spread +/-0.3%

CPU_CLKSEL0<5,13>
CPU_CLKSEL1<5,13>

A_AD[31..30] : FSB CLK SPEED

DEFAULT: 01

00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

5

LCD CONN

TXA1+<16>
TXA1-<16>

TXB2+<16>
TXB2-<16>

TXA0+<16>

D D

C C

TXA0-<16>

TXACLK+<16>
TXACLK-<16>

TXB1+<16>
TXB1-<16>

TXB0+<16>
TXB0-<16>

TXBCLK+<16>
TXBCLK-<16>

TXA1+_NB<11>
TXA1-_NB<11>

TXB2+_NB<11>
TXB2-_NB<11>

TXA0+_NB<11>
TXA0-_NB<11>

TXACLK+_NB<11>
TXACLK-_NB<11>

TXB1+_NB<11>
TXB1-_NB<11>

TXB0+_NB<11>
TXB0-_NB<11>

TXBCLK+_NB<11>
TXBCLK-_NB<11>

TXA1+
TXA1-

TXB2+
TXB2-

TXA0+
TXA0-

TXACLK+
TXACLK-

TXB1+
TXB1-

TXB0+
TXB0-

TXBCLK+

TXBCLK-

TXA1+_NB
TXA1-_NB

TXB2+_NB
TXB2-_NB

TXA0+_NB
TXA0-_NB

TXACLK+_NB
TXACLK-_NB

TXB1+_NB
TXB1-_NB

TXB0+_NB
TXB0-_NB

TXBCLK+_NB

TXBCLK-_NB

JP5

20

40

19

39

18

38

17

37
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

M9+/M10@JST_SM40B-SRDS-G

JP6

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

M9@JST BM40B-SRDS

PID0

36

PID1

35

PID2

34

PID3

33

PID4

32

I2C_CLK

31

I2C_DATA

30

29

28

27

26

25

24

23

22

21

1
2
3
4

PID0

5

PID1

6

PID2

7

PID3

8

PID4

9
10
11
12
13
14
15
16
17
18
19
20

LCDVDD_C

TV_OUT CONNECTOR

12

75_0402_5%

5

TV_LUMA
TV_CRMA
TV_COMPS

1

1

C17

2

2

270P_0402_50V7K

TV_LUMA<11,16,43>
TV_CRMA<11,16,43>

TV_COMPS<11,16>

TV_LUMA

B B

TV_CRMA

TV_COMPS

12

12

R367

R22

75_0402_5%

A A

R18

270P_0402_50V7K

75_0402_5%

@SFI0603-120E100MP_0603

1

C428

C16

2

270P_0402_50V7K

L7
CHB1608B121_0603

1 2

L36
CHB1608B121_0603

1 2

L3
CHB1608B121_0603

1 2

@10U_0805_10V4Z

TXA2+
TXA2-

+3VS

TXA2+_NB
TXA2-_NB

+3VS

@SFI0603-120E100MP_0603

D3

1

C12

C424

2

330P_0402_50V7K

330P_0402_50V7K

CRT_HSYNC<11,16>

CRT_VSYNC<11,16>

PID0 <38>
PID1 <38>
PID2 <38>
PID3 <38>
PID4 <38>
I2C_CLK <16>
I2C_DATA <16>

The cap.'s colsely to LCD CONN.

21

C817

TXA2+ <16>
TXA2- <16>

NB_I2CCLK <10>
NB_I2CDATA <10>

TXA2+_NB <11>
TXA2-_NB <11>

D14

1

1

2

2

330P_0402_50V7K

4

1

2

21

TV_LUMAL
TV_CRMAL

TV_COMPSL

C11

CRT_HSYNC

CRT_VSYNC

4

1 2

KC FBM-L11-201209-221LMAT_0805

1

C37
68P_0402_50V8J

2

B+

1

C806

0.001U_0402_50V7M

21

2

D1
@SFI0603-120E100MP_0603

JP19

SUYIN_33007SR-07T1-C

+5VS

SN74AHCT126PWR_TSSOP14

LCDVDDLCDVDD_C

L8

1

C807

2

0.1U_0402_16V4Z

M_SEN#<40,43>

CRT_R<11,16,43>

CRT_G<11,16,43>

CRT_B<11,16,43>

1
2
3
4
5
6
7

14

1

U1A

P

OE

3

A2Y

G

7

R5

1 2

1K_0402_5%

14

4

U1B

P

OE

6

A5Y

G

SN74AHCT126PWR_TSSOP14

7

INVT_PWM<40>
DAC_BRIG<40>

3

+3VS

12

R8

4.7K_0402_5%

R1056

2

G

DISPOFF#

13

D

Q1
2N7002_SOT23

S

1K_0402_1%

2N7002_SOT23

12

@SFI0603-120E100MP_0603

D15

21

CRTL_R

CRTL_G

CRTL_B

1

C6
22P_0402_25V8K

2

R66

Q4

Q43

2

I

3

G

DTC124EK_SC59

22P_0402_25V8K

L2

1 2

CHB1608B121_0603
L1

1 2

CHB1608B121_0603

14

13

U1D

P

OE

A12Y

G

SN74AHCT126PWR_TSSOP14

7

BKOFF#<40>

ENABLT#<10,16,40>

INVT_PWM
DISPOFF#
DAC_BRIG

D2 RB751V_SOD323

ENABLT#

JP2
1
2
3
4
5
6
7

ACES_87212-0700

Layout & BOM update 7/10

21

1
2
3
4
5
6
7

ENAVDD<10,16>

ENAVDD

2.7K_0402_5%

@SFI0603-120E100MP_0603

CRT CONNECTOR

M_SEN#
CRT_R

CRT_G

CRT_B

R17

75_0402_5%

1 2

10P_0402_50V8K

+5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10P_0402_50V8K

1

C15

R15

2

1 2

75_0402_5%

CRT_HSYNCRFL<43>
CRT_VSYNCRFL<43>

+5VS +5VS

14

P

A9Y

G

7

3

L5

1 2

FCM2012C-800_0805

L4

1 2

FCM2012C-800_0805
L6

1 2

FCM2012C-800_0805

1

2

10

1

C14

OE

C13

R13

10P_0402_50V8K

2

1 2

75_0402_5%

CRT_HSYNCRFL
CRT_VSYNCRFL

U1C

8

SN74AHCT126PWR_TSSOP14

CRT_HSYNCRFL

CRT_VSYNCRFL

LCDVDD

12

13

D

2

G

S

O

D17

@SFI0603-120E100MP_0603

21

1

C8

2

22P_0402_25V8K

11

2

+12VALW

1

2

1

C1

2

R30
100K_0402_5%

D16

21

CRTL_HSYNCRFL

CRTL_VSYNCRFL

22P_0402_25V8K

2

G

Q42

2N7002_SOT23

+5VS

RB411D_SOT23

C9

1

+12VALW

R29
100K_0402_5%

1

C32

R28

13

D

150K_0402_5%

S

SI2 30 1D S: P CHANNEL
VGS: -4 . 5V , RD S : 130 mOHM
VGS: -2 . 5V , RD S : 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

R_CRT_VCC

D4

2 1

FUSE_1A

0.1U_0402_16V4Z

220P_0402_50V8K

1

1

1

2

22P_0402_25V8K

2

2

C2

220P_0402_50V8K

Title

SCHEMATIC, M/B LA-1861

Size Docu ment Number Re v
Custom

Date: Sheet

0.047U_0402_16V4Z

2

0.1U_0402_16V4Z

CRT_VCC

F1

21

1

C3

2

C5

1

1

2

2

C7

C4

220P_0402_50V8K

Compal Electronics, Inc.

星期三 七月

30, 2003

+3VS

2

G

C44

SI2302DS: N CHANNEL
VGS: 4. 5 V , RDS : 85 mOHM
VGS: 2. 5 V , RDS : 1 15mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V

6.8K_0402_5%

R4

R3

6.8K_0402_5%

1 2

1 2

CRT_VCC

Q37

D

S

1 3

2N7002_SOT23

G

2

D

1 3

DOCK_DDCDA
DOCK_DDCCL

3VDDCDA<11,16>

3VDDCCL<11,16>

401257

1

1

2

13

D

Q2

S

SI2302DS 1N_SOT23

1

1

C41

4.7U_0805_10V4Z

2

2

DOCK_DDCDA
DOCK_DDCCL

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

Q36

S

2N7002_SOT23

R21

G

2

4.7K_0402_5%

3VDDCDA
3VDDCCL

24 61,

C42

4.7U_0805_10V4Z

LCDVDD

JP20
CRT-15P

3VDDCDA

3VDDCCL

R366

4.7K_0402_5%

+3VS
DOCK_DDCDA <43>
DOCK_DDCCL <43>

of

0E

5

A_AD[0..31]<10,13>

A_CBE#[0..3]<10>

A_AD[0..31]
A_CBE#[0..3]

R207 8.2K_0402_5%

PULL DOWN FOR S3

D D

+CPU_CORE

12

R537
56_0402_5%

R538

1 2

H_FERR#<5>

Near SB

C C

H_INIT#
H_A20M#
H_INTR
H_NMI
H_SMI#
H_STPCLK#

B B

H_IGNNE#

H_INIT#
H_INTR
H_NMI

R191 200_0402_5%
R193 200_0402_5%
R192 200_0402_5%
R189 200_0402_5%
R188 200_0402_5%
R195 200_0402_5%
R190 200_0402_5%

2

330_0402_5%

MMBT3904_SOT23

1 2
1 2
1 2
1 2
1 2
1 2
1 2

C818 180P_0603_50V8J
C819 180P_0603_50V8J
C621 180P_0603_50V8J
C622 180P_0603_50V8J

PLACE CLOSE TO CPU SOCKET

A A

H_RESET#<5,8>

H_RESET#

5

R185

1 2

@330_0402_5%

12

R536

1K_0402_5%

2

Q53

3 1

+3VS

@1K_0402_5%

2

@MMBT3904_SOT23

+3VS

12

330_0402_5%

Q54
MMBT3904_SOT23

3 1

+CPU_CORE

12

R186

Q14

3 1

R540

H_CPUFERR#

R206

8.2K_0402_5%

1 2

PAD

PM_DPRSLPVR<53>

CLK_14M_APIC<23>

2

T1

R204 10K_0402_5%

@

R205 10K_0402_5%

+3VS

12

R187

4.7K_0402_5%

CPURSTIN#

Q15
@MMBT3904_SOT23

3 1

4

CLK_ALINK_SB<23>

CLK_ALINK_SB

12

R200
10_0402_5%

C228
15P_0402_50V8D

A_STROBE#<10>

A_DEVSEL#<10>

A_ACAT#<10>

A_END#<10>

A_PAR<10,13>

A_OFF#<10>

A_SBREQ#<10>
A_SBGNT#<10>

CPUCLK_STP#<5,11,28,53>

PCICLK_STP#<23>

PCI_PIRQA#<10,16,30,33,44>
PCI_PIRQB#<30,44>
PCI_PIRQC#<34,44>
PCI_PIRQD#<32,34>

H_PWRGOOD<5>

H_INTR<5>

H_NMI<5>

H_INIT#<5>

H_SMI#<5>

H_CPUSLP#<5>

H_IGNNE#<5>

H_A20M#<5>

H_STPCLK#<5>

1 2
1 2

R202 @300_0402_1%

4

SB_APIC_D0
SB_APIC_D1

1K_0402_1%

CLK_ALINK_SB

NBRST#
A_AD0

A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#

CPUCLK_STP#
PCICLK_STP#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

RTCX1

RTCX2

CPURSTIN#

R954

1 2

0_0402_5%

H_CPUFERR#
GPIO0

R203

U15A

B22

PCICLKF

R22

A_RST#

H22

A_AD0

P23

A_AD1

L23

A_AD2

N23

A_AD3

N22

A_AD4

M23

A_AD5

M22

A_AD6

K22

A_AD7

M21

A_AD8

M20

A_AD9

L21

A_AD10

K21

A_AD11

L20

A_AD12

N21

A_AD13

K23

A_AD14

K20

A_AD15

F23

A_AD16

G21

A_AD17

F20

A_AD18

H21

A_AD19

F22

A_AD20

F21

A_AD21

G20

A_AD22

E21

A_AD23

E20

A_AD24

D23

A_AD25

D22

A_AD26

E22

A_AD27

D20

A_AD28

C23

A_AD29

D21

A_AD30

C22

A_AD31

L22

A_CBE#0

J23

A_CBE#1

G22

A_CBE#2

E23

A_CBE#3

H20

A_STROBE#

J21

A_DEVSEL#

G23

A_ACAT#

H23

A_END#

J20

A_PAR

J22

A_OFF#

P22

A_SERR#

B21

A_SBREQ#

B20

A_SBGNT#

N20

CPU_STP#/DPSLP#

R23

PCI_STP#

C20

A_INTA#

P20

INTB#

B23

INTC#

P21

INTD#

AC12

X1

AC11

X2

B18

CPURSTIN#

E4

CPU_PWRGD

B17

INTR/LINT0

B16

NMI/LINT1

C17

INIT

C16

SMI#

F19

SLP#

D17

IGNNE#

D18

A20M#

E19

FERR#

E16

STPCLK#

E17

SSMUXSEL/GPIO0

E18

DPRSLPVR

C19

APIC_D0

C18

APIC_D1

B19

APIC_CLK

South bridge SB200

12P_0402_50V8K

3

Layout note:

Trace length of PCI_CLK_R + PCI_CLK_FB should
be less than 200 mils.

PCI_1394

SB200 SB

Part 1 of 3

PCI CLKS

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6

AD23/ROMD7
AD24/RTC_AD7
AD25/RTC_AD6
AD26/RTC_AD5
AD27/RTC_AD4
AD28/RTC_AD3
AD29/RTC_AD2
AD30/RTC_AD1
AD31/RTC_AD0

CBE#0/ROMA10

CBE#1/ROMA1

A-LINK INTERFACE

XTAL

CPU

RTC

Y3 32.768KHZ_12.5P_MC-206

1 4

RTCX2

2 3

R223

C273

1 2

20M_0603_5%

12P_0402_50V8K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CBE#2/ROMWE#

PCI INTERFACE

CBE#3/RTC_RD#

DEVSEL#/ROMA0

TRDY#/ROMOE#

REQ#3/PDMAREQ0#

REQ#4/PLLBP33/PDMAREQ1#

GNT#3/PDMAGNT0#

GNT#4/PLLBP50/PDMAGNT1#

GPIO1/ROMCS#

LPC

USBOC5#/GPM1

RTC_ALE/USBOC4#/GPIO3

RTC_WR#/RTC_CLKOUT

RTC_CS#/USBOC3#/GPIO2

RTCX1

C274

3

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7

PCICLK_FB

PCIRST#

AD8/ROMA9
AD9/ROMA8

FRAME#

IRDY#

PAR
STOP#
PERR#
SERR#
REQ#0
REQ#1
REQ#2

GNT#0
GNT#1
GNT#2

CLKRUN#

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ#0
LDRQ#1

SERIRQ

VBAT

RTC_GND

12

R222
20M_0603_5%

B15
D16
A14
A15
A16
A17
D15
A18
A19

C15
B1
C1
A1
D2
B2
C2
A2
D3
C3
A3
D4
B4
C4
A4
D5
B5
C8
D8
B8
A8
C9
D9
B9
A9
C10
B10
D11
A10
C11
B11
D12
A11
B3
C5
A7
D10
B7
A6
C7
D7
A5
B6
C6
D6
B12
C12
D13
A12
C13
A13
B13
C14
D14
B14
A20

AB5

Y14
AA14
AB14
AA13
AB13
AC14
Y13

AC13

AA2
AB7
AB8
AC8
AC10
AB11

PCI_LAN
PCI_PCM
PCI_MINI
PCI_EC
PCI_SIO
PCI_USB
PCI_CLK_R
PCI_CLK_FB

PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#

SIDEPWR

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1

SIRQ

OVCUR#5
OVCUR#4

INT_OVCUR#3

+RTCVCC

R561 33_0402_5%
R563 33_0402_5%
R562 33_0402_5%
R560 33_0402_5%
R566 33_0402_5%
R549 33_0402_5%
R970 33_0402_5%
R559 33_0402_5%

PCI_A D[0..31]

12

10K_0402_5%

NBRST# NB_RST#

PCI_CBE#[0..3]

PCI_FRAME# <30,32,33,34,44>
PCI_DEVSEL# <30,32,33,34,44>
PCI_IRDY# <30,32,33,34,44>
PCI_TRDY# <30,32,33,34,44>
PCI_PAR <30,32,33,34,44>
PCI_STOP# <30,32,33,34,44>
PCI_PERR# <30,32,33,34>
PCI_SERR# <30,32,34>
PCI_REQ#0 <33>
PCI_REQ#1 <32>
PCI_REQ#2 <30>
PCI_REQ#3 <34>
PCI_REQ#4 <34,44>
PCI_GNT#0 <33>
PCI_GNT#1 <32>
PCI_GNT#2 <30>
PCI_GNT#3 <34>
PCI_GNT#4 <34,44>
PCI_CLKRUN# <30,32,34,38,40>

SIDEPWR <29>

LPC_AD0 <38,40>
LPC_AD1 <38,40>
LPC_AD2 <38,40>
LPC_AD3 <38,40>
LPC_FRAME# <38,40>

LPC_DRQ#1 <38>
SIRQ <30,38,40>

R998 NUSB20@0_0402_5%

1 2

PCIRST#

R736

2

CLK_PCI_1394 <33>
CLK_PCI_LAN <32>
CLK_PCI_PCM <30>
CLK_PCI_MINI <34>
CLK_PCI_EC <40>
CLK_PCI_SIO <38>
CLK_PCI_USB20 <44>

C619 @22P_0402_50V8J

PCI_AD[0..31] <28,30,32,33,34,44>

+3VALW

14

1

U44A

P

OE#

I2O
G

SN74LVC125APWLE_TSSOP14

7

4

U44B

OE#

I5O

SN74LVC125APWLE_TSSOP14

PCI_CBE#[0..3] <30,32,33,34,44>

W=20mils

JOPEN1

No short

1 2

2

PCI_RST#

3

6

PCI_RST# <16,29,30,32,33,34,38,44>

NB_RST# <8,11,16,38>

R569

@4.7K_0402_5%

Layout update 7/16

OVCUR#3 <37,44>

+RTCVCC

1 2

R353 1K_0603_1%
C419
1U_0603_10V4Z

Layout & BOM update 7/10

Title

Size Docu ment Number Re v

Date: Sheet

PCI_CLKRUN#

12

SIDEPWRH_A20M#
INT_OVCUR#3
OVCUR#5

OVCUR#4

2 1

RB751V_SOD323

R578 10K_0402_5%

SIRQ

R716 8.2K_0402_5%

D13

W=15mils

R711 10K_0402_5%
R718 10K_0402_5%
R709 10K_0402_5%

R1060 @10K_0402_5%
R719 10K_0402_5%

BATT1.1

W=20mils

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

1

PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

PCI_REQ#4

PCI_GNT#4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
GPIO0

1 2
1 2
1 2

1 2
1 2

+

CHGRTC

1

RP62
4 5
3 6
2 7
1 8

8.2K_0804_8P4R_5%
RP59

4 5
3 6
2 7
1 8

8.2K_0804_8P4R_5%
RP60

4 5
3 6
2 7
1 8

8.2K_0804_8P4R_5%
RP61

4 5
3 6
2 7
1 8

8.2K_0804_8P4R_5%
RP58

4 5
3 6
2 7
1 8

8.2K_0804_8P4R_5%
R546

8.2K_0402_5%
R545

8.2K_0402_5%
RP10

4 5
3 6
2 7
1 8

100K_0804_8P4R_5%

RP84

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

12

BATT1

1 2

ML1220T13RE

of

25 61,

+3VS

+3VS

+3V

-

0E

5

4

3

2

1

SB_EC_THERM#
SB_PM_BATLOW#

CLK_SB_48M

12

R659

D D

C C

B B

A A

+3V

10_0402_5%

C695
15P_0402_50V8D

AC97_BITCLK

12

R584
@10_0402_5%

C639
@15P_0402_50V8D

CLK_SB_14M

12

R198
@10_0402_5%

C227
@15P_0402_50V8D

R639 15K_0402_5%

1 2

R648 15K_0402_5%

1 2

R614 15K_0402_5%

1 2

R641 15K_0402_5%

1 2

R602 15K_0402_5%

1 2

R612 15K_0402_5%

1 2

R594 15K_0402_5%

1 2

R604 15K_0402_5%

1 2

R554 15K_0402_5%

1 2

R552 15K_0402_5%

1 2

R556 15K_0402_5%

1 2

R557 15K_0402_5%

1 2

R65310K_0402_5%

12

R71410K_0402_5%

12

R71010K_0402_5%

12

INT_OVCUR#1

OVCUR#2<37,44>
OVCUR#1<37,44>

INT_OVCUR#0
INT_OVCUR#1
INT_OVCUR#2

5

INT_OVCUR#1<43>

VTT_PWRGD<23,42>

CLK_SB_48M<23>

INT_OVCUR#0<43>

OVCUR#0<37,44>

USB20P5+<37>
USB20P5-<37>

USB20P4+<37>
USB20P4-<37>

USB20P3+<37>
USB20P3-<37>

USB20P2+<37>
USB20P2-<37>

USB20P1+<37,43>
USB20P1-<37,43>

USB20P0+<37,43>
USB20P0-<37,43>

USB20P5+
USB20P5­USB20P4+
USB20P4­USB20P3+
USB20P3­USB20P2+
USB20P2­USB20P1+
USB20P1­USB20P0+
USB20P0-

Note:EC_FLASH# pull-high in page 41

EC_FLASH#<41>

32KHZ_S5_OUT<28>

SB_SPKR<35>

AGP_STP#<10,16>

CPU_GHI#<5>

IDERST_HD#<29>
IDERST_CD#<29>

R999 NUSB20@0_0402_5%

1 2

R638 @40.2_0402_1%
R647 @40.2_0402_1%

R613 @40.2_0402_1%
R640 @40.2_0402_1%

R601 @40.2_0402_1%
R611 @40.2_0402_1%

R593 @40.2_0402_1%
R603 @40.2_0402_1%

R553 @40.2_0402_1%
R551 @40.2_0402_1%

R555 @40.2_0402_1%
R550 @40.2_0402_1%

MII_TXD3<28>
MII_TXD2<28>
MII_TXD1<28>
MII_TXD0<28>

MII_TXEN<28>

+3V

R1033 @10K_0402_5%

1 2

SB_EEDO<28>

SB_EECLK<28>

R713100K_0402_5%

R1000 NUSB20@0_0402_5%

1 2

R1001 NUSB20@0_0402_5%

1 2

AGP_BUSY#<10,16>

EC_RSMRST#<30,31,40>

CLK_SB_14M<23>

EC_FLASH#
32KHZ_S5_OUT
SB_SPKR

R723 0_0402_5%

R957 10K_0402_5%

2 1

D30 RB751V_SOD323

1 2

R225

1K_0402_5%

AGP_BUSY# AGP_BUSY#_R

3 1
Q65
MMBT3904_SOT23

+3VS

CLK_SB_48M
USB_RCOMP

R654

12.4K_0603_1%
INT_OVCUR#0

USB20P5+
USBP5_R
USB20P5­USBN5_R

USB20P4+
USBP4_R
USB20P4­USBN4_R

USB20P3+
USBP3_R
USB20P3­USBN3_R

USB20P2+
USBP2_R
USB20P2­USBN2_R

USB20P1+
USBP1_R
USB20P1­USBN1_R

USB20P0+
USBP0_R
USB20P0­USBN0_R

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

MII_TXEN

R706 100K_0402_5%

SB_EEDI
SB_EEDO
SB_EECLK

EC_RSMRST#
CLK_SB_14M

INT_OVCUR#2
INT_OVCUR#1

1 2

AGP_STP#_RAGP_STP#

AGP_BUSY#_R

VGATE

1 2
2

4

U15B

P3

USBCLK/CLK48

R1

USB_RCOMP

P1

USB_VREFOUT

N4

USB_ATEST1

N3

USB_ATEST0

P4

USBOC0#/GPM7

M2

USB_HSDP5+

M1

USB_FLDP5+

N2

USB_HSDM5-

N1

USB_FLDM5-

L4

USB_HSDP4+

L3

USB_FLDP4+

M4

USB_HSDM4-

M3

USB_FLDM4-

K2

USB_HSDP3+

K1

USB_FLDP3+

L2

USB_HSDM3-

L1

USB_FLDM3-

H2

USB_HSDP2+

H1

USB_FLDP2+

J2

USB_HSDM2-

J1

USB_FLDM2-

G3

USB_HSDP1+

J3

USB_FLDP1+

H3

USB_HSDM1-

K3

USB_FLDM1-

F1

USB_HSDP0+

F2

USB_FLDP0+

G1

USB_HSDM0-

G2

USB_FLDM0-

R5

MCOL

W1

MCRS

V4

MDCK

V2

MDIO

T1

RX_CLK

T3

RXD3

U2

RXD2

T5

RXD1

W4

RXD0

T2

RX_DV

U1

RX_ERR

T4

TX_CLK

U4

TXD3

V1

TXD2

U3

TXD1

V3

TXD0

W2

TX_EN

W3

PHY_PD

U5

PHY_RST#

Y7

CLK_25M

P2

EE_CS

R3

EE_DI

R2

EE_DO

R4

EE_CK

AB9

RSMRST#

A23

OSC_IN

W6

SIO_CLK

AB2

BLINK/GPM0

AA3

FANOUT1/USBOC2#/GPM2

W11

32KHZ_IN/GPM3

AB1

USBOC1#/GPM4

Y4

SPEAKER/GPM5

AA1

FANOUT0/GPM6

AC1

GPIO_X0/AGP_STP#

AC6

GPIO_X1/AGP_BUSY#

AC2

GPIO_X2/GHI#

AC3

GPIO_X3/VGATE

AC4

GPIO_X4

AC5

GPIO_X5

South bridge SB200

SB200 SB

TALERT#/ETH_TALERT#

Part 2 of 3

USB INTERFACE

ETHERNET MIIEEPROMCL K / RST

PME#/EXT_EVNT0#

RI#/EXT_EVNT1#

SLP_S3#
SLP_S5#

PWR_BTN#

PWR_GOOD

PCI_REQACT#

SUS_STAT#

TEST1
TEST0

GA20_IN/GEVNT0#

KB_RST#/GEVNT1#

SMB_ALERT#/GEVNT2#

LPC_PME#/GEVNT3#

LPC_SMI#/GEVNT4#
GEVENT5#/ETH_VALERT#
GEVENT6#/ETH_FALERT#

ACPI / WAKE UP EVENTS

GEVENT7#/ETH_CALERT#

GPOC0#/SCL0
GPOC1#/SDA0
GPOC2#/SCL1
GPOC3#/SDA1

RTC_IRQ#/PWR_STRP

PIDE_IORDY

PIDE_IRQ

PIDE_A0
PIDE_A1
PIDE_A2

PIDE_DACK#

PIDE_DRQ

PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8

PIDE_D9
PIDE_D10
PIDE_D11

PRIMARY ATA 66/100

SECONDARY ATA 66/100

GPIOGPIO_XTRA

AC97

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

SIDE_IORDY

SIDE_IRQ

SIDE_A0

SIDE_A1

SIDE_A2

SIDE_DACK#

SIDE_DRQ

SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#

SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8

SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15

AC_BITCLK
AC_SDOUT

AC_SDIN0
AC_SDIN1
AC_SDIN2

AC_SYNC

AC_RST#

SPDIF_OUT

3

AB4
AC9

AC7
AA11
AB10
AA10
Y11
C21
Y10
AA5
AA6

Y5
AA4
AB3
Y6
W5
Y8
AA7
AB6

AA12
W12
Y12
AB12
AA8

AB17
AC16
AB15
AB16
AC15
Y16
AA17
AA16
AC17
Y15
AA15

AC18
AA18
AC19
AA19
AC20
AA20
AC21
AB21
AA21
Y20
AB20
Y19
AB19
Y18
AB18
Y17

AA23
AA22
AC23
Y21
AB23
Y22
W21
Y23
W20
AC22
AB22

W23
V21
V23
U21
U23
T21
T23
R21
R20
T22
T20
U22
U20
V22
V20
W22

E1
E2
Y1
Y2
Y3
E3
V5
E5

SB_EC_THERM#
SB_PM_BATLOW#

SB_EC_SWI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
PCI_ACT_REQ#
SUS_STAT#
SB_TEST1
SB_TEST0

SB_GA20

SB_KBRST#
SB_AC_IN
LPC_PME#
LPC_SMI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#

SMB_CK_CLK1
SMB_CK_DAT1
SMB_CK_CLK2
SMB_CK_DAT2
PWR_STRP

IDEIORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3

IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15

IDEIORDYB
IDEIRQB
IDESAB0
IDESAB1
IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B
IDECS#B1
IDECS#B3

IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15

AC97_SDOUT_R

AC97_SYNC_R
SPDIF_OUT

SLP_S3# <40>
SLP_S5# <40>
PWRBTN_OUT# <40>
SB_PWRGD <42>

SUS_STAT# <8,16>

LPC_SMI# <44>

SMB_CK_CLK1 <14,23>
SMB_CK_DAT1 <14,23>

PWR_STRP <28>
IDEIORDYA <29>

IDEIRQA <29>
IDESAA0 <29>
IDESAA1 <29>
IDESAA2 <29>
IDEDACK#A <29>
IDEREQA <29>
IDEIOR#A <29>
IDEIOW #A <29>
IDECS#A1 <29>
IDECS#A3 <29>

IDEDA[0..15] <29>

IDEIORDYB <29>
IDEIRQB <29>
IDESAB0 <29>
IDESAB1 <29>
IDESAB2 <29>
IDEDACK#B <29>
IDEREQB <29>
IDEIOR#B <29>
IDEIOW #B <29>
IDECS#B1 <29>
IDECS#B3 <29>

IDEDB[0..15] <29>

R590 33_0402_5%

R574 33_0402_5%

SPDIF_OUT <28>

AC97_BITCLK
AC97_SDOUT
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
AC97_SYNC
AC97_RST#

SB_EC_SWI#
SB_GA20 GA20
SB_KBRST#

SB_EC_SMI#
SB_SCI# SCI#

AC97_BITCLK <34,35,37>
AC97_SDOUT <28,34,35,37>
AC97_SDIN0 <35>
AC97_SDIN1 <34,37>

AC97_SYNC <28,34,35,37>
AC97_RST# <34,35,37>

2

D28 RB751V_SOD323

2 1

D22 RB751V_SOD323

2 1

D25 RB751V_SOD323

2 1

D27 RB751V_SOD323

2 1

D29 RB751V_SOD323

2 1

D21 RB751V_SOD323

2 1

D23 RB751V_SOD323

2 1

D24 RB751V_SOD323

2 1

D26 RB751V_SOD323

2 1

SB_AC_IN
AGP_STP#_R

AGP_BUSY#_R
SB_GA20
SB_KBRST#
SB_EC_SWI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
LPC_PME#
LPC_SMI#
PCI_ACT_REQ#

PWRBTN_OUT#
SLP_S3#
SLP_S5#

BOM update 7/24 for ATI recommend

SMB_CK_CLK1
SMB_CK_DAT1
SMB_CK_CLK2
SMB_CK_DAT2

AGP_STP#
AGP_BUSY#

SB_TEST0
SB_TEST1

AC97_RST#

AC97_BITCLK
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2

Title

Size Docu ment Number Re v

Date: Sheet

星期三 七月

EC_THERM#
PM_BATLOW#
EC_SWI#

KBRST#
ACINSB_AC_IN
EC_SMI#

LID_OUT#SB_LID_OUT#

R955 10K_0402_5%
R210 10K_0402_5%

R216 10K_0402_5%
R213 10K_0402_5%
R211 10K_0402_5%
R217 10K_0402_5%
R220 10K_0402_5%
R218 10K_0402_5%
R214 10K_0402_5%
R212 10K_0402_5%
R221 10K_0402_5%
R704 10K_0402_5%
R693 10K_0402_5%
R642 10K_0402_5%

R1032 10K_0402_5%
R961 10K_0402_5%
R962 10K_0402_5%

R956

SUS_STAT#

1 2

10K_0402_5%

RP12 2.2K_0804_8P4R_5%

R224 8.2K_0402_5%
R219 8.2K_0402_5%

R707 8.2K_0402_5%
R708 8.2K_0402_5%

R682 8.2K_0402_5%

RP83

8.2K_0804_8P4R_5%

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 8
2 7
3 6
4 5

1 2
1 2

1 2
1 2

1 8
2 7
3 6
4 5

R1022

1 2

4.7K_0402_5%

EC_THERM# <40>
PM_BATLOW# <40>
EC_SWI# <40>
GA20 <40>
KBRST# <40>
ACIN <40,46>
EC_SMI# <40>
SCI# <40>
LID_OUT# <40>

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

26 61,

1

+3V

+3VALW

+2.5V

+3VS

+3V

0E

of

5

+3VS

47U_B_6.3VM

1

22U_1206_10V4Z

D D

22U_1206_10V4Z

22U_1206_10V4Z

C C

22U_1206_10V4Z

+3V

B B

+3V

+2.5VS

A A

C219

2

+2.5VS

0.1U_0402_16V4Z

1

C223

2

+2.5V

0.1U_0402_16V4Z

C222

+3V

0.1U_0402_16V4Z

C699

1 2

R652 0_0805_5%

+3V_AVDDUSB

1 2

R634 0_1206_5%

C221

22U_1206_10V4Z

+2.5V_AVDDCK

1 2

R558 0_0805_5%

+3V_AVDDC

1

+

C220

2

0.1U_0402_16V4Z

C636

0.1U_0402_16V4Z

C659

0.1U_0402_16V4Z

C694

0.1U_0402_16V4Z

C690
1U_0603_10V4Z

0.1U_0402_16V4Z

C628
1U_0603_10V4Z

0.1U_0402_16V4Z

C708

C702

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C666

C682

0.1U_0402_16V4Z

C671

C688

0.1U_0402_16V4Z

C706

C705

C651

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C709

0.1U_0402_16V4Z

C667

0.1U_0402_16V4Z

C704

0.1U_0402_16V4Z

C714

0.1U_0402_16V4Z

C689

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C645

C629

0.1U_0402_16V4Z

C673

0.1U_0402_16V4Z

C643

0.1U_0402_16V4Z

C670

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C672

0.1U_0402_16V4Z

C650

C649

0.1U_0402_16V4Z

C693

C684

C680

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C644

0.1U_0402_16V4Z

C692

0.1U_0402_16V4Z

C681

4

C646

@0.1U_0402_16V4Z

0.1U_0402_16V4Z

C696

0.1U_0402_16V4Z

@0.01U_0402_16V7K

@0.01U_0402_16V7K

C698

C616

@22U_1206_10V4Z

C687

0.1U_0402_16V4Z

+3VS

C499

+2.5VS

C492

+3V

0.1U_0402_16V4Z

C683

@0.01U_0402_16V7K

1

1

C556

2

2

@0.01U_0402_16V7K

1

1

2

2

C697

@0.1U_0402_16V4Z

@47U_B_6.3VM

0.1U_0402_16V4Z

C647

C656

C662

0.1U_0402_16V4Z

ATI request

@0.01U_0402_16V7K

1

1

C529

C536

2

2

@0.01U_0402_16V7K

C476

@0.01U_0402_16V7K

@0.1U_0402_16V4Z

@0.01U_0402_16V7K

@0.01U_0402_16V7K

1

1

C569

2

2

+2.5V

C679

ATI request CLOSE
TO L6,H6,J6

+3V_AVDDUSB +3V_AVDDC+2.5V_AVDDCK

1

+

C652

@10U_1206_10V6K

2

+3VS

3

C648

0.1U_0402_16V4Z

1

C486

2

C537

C686

2 1

RB751V_SOD323

C661
@0.1U_0402_16V4Z

D37

+5VS

12

R1034
1K_0402_5%

C638

0.1U_0402_16V4Z

+2.5V

+3V_AVDDC

+3V

+3V_AVDDUSB

+2.5VS

+2.5V_AVDDCK

+2.5VALW

+3VALW

0.1U_0402_16V4Z

+2.5VS

C715

+3VS

2

E11
E12
E15

F11
F12
F15
F16
F17

G18
G19
H18

H19
M18
M19

N18

N19

T18

T19

U18

U19

V17

V18
W17
W18

J10
J11
J13
J14

K15

L15

N15

P15

R10

R11

R13

R14

V13
W13

V12

V10

V11

W9

W10

D19

A21

AA9

C719

0.1U_0402_16V4Z

U15C

VDDQ
VDDQ
VDDQ

E7

VDDQ

E8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

F7

VDDQ

F8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE

K9

VDD_CORE
VDD_CORE

L9

VDD_CORE
VDD_CORE

N9

VDD_CORE
VDD_CORE

P9

VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE

P6

STB_2.5V

R6

STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V

L6

VDD_USB

H6

VDD_USB

J6

VDD_USB

P5

AVDDC

T6

STB_3.3V

U6

STB_3.3V

V9

STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V

F4

AVDDTX0

J4

AVDDTX1

K5

AVDDTX2

F3

AVDDRX0

K4

AVDDRX1

L5

AVDDRX2
VREF_CPU

D1

5V_VREF
AVDD_CK

Y9

S5_2.5V
S5_3.3V

South bridge SB200

SB200 SB

Part 3 of 3

POWER

VSS_USB
VSS_USB

AVSSC

AVSSRX2
AVSSRX1
AVSSRX0

AVSSTX2
AVSSTX1
AVSSTX0

AVSSCK

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E10
E13
E14
E6
E9
F10
F13
F14
F18
F6
F9
G6
J12
J15
J18
J19
J9
K10
K11
K12
K13
K14
K18
K19
L10
L11
L12
L13
L14
L18
L19
M10
M11
M12
M13
M14
M15
M6
M9
N10
N11
N12
N13
N14
N6
P10
P11
P12
P13
P14
P18
P19
R12
R15
R18
R19
R9
V14
V15
V16
V19
V6
V7
V8
W14
W15
W16
W19
W7
W8
H5
G5

N5
M5

J5
G4
K6
H4
F5

A22

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

0E

of

27 61,

1

5

D D

4

3

2

1

+3V +3V

12

R705
10K_0402_5%

PWR_STRP<26>

SB_EEDO<26>

SB_EECLK<26>

AC97_SYNC<26,34,35,37>

AC97_SDOUT<26,34,35,37>

SPDIF_OUT<26>

CPUCLK_STP#<5,11,25,53>

C C

MII_TXEN<26>
MII_TXD3<26>
MII_TXD2<26>
MII_TXD1<26>
MII_TXD0<26>

32KHZ_S5_OUT<26>

R696

@10K_0402_5%

REQUIRED SYSTEM STRAPS

STRAP
HIGH

STRAP

B B

LOW

MANUAL
PWR ON

DEFAULT

PWR
ON

R684
@10K_0402_5%

12

R658
10K_0402_5%

IGN DEBUG SPEEDSTEP FREQLTCH

EEDO

DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

+3VS

12

R579
@10K_0402_5%

EECK

ROM ON
PCI BUS

DEFAULT

ROM ON
LPC
BUS

R660
@10K_0402_5%

12

R651
10K_0402_5%

+3VS

1 2

AC_SYNC

INIT ACTIVE
HIGH

INIT ACTIVE
LOW (PIII)

DEFAULT

R587
@10K_0402_5%

R575
10K_0402_5%

+3VS +3VS +3VS

SIO 24MHzUSE

SIO 48MHzAUTO

DEFAULT

R589
@10K_0402_5%

12

R582
10K_0402_5%

12

33MHz NB
BUS

DEFAULT

HI SPEED
A-LINK

R588
@10K_0402_5%

R581
10K_0402_5%

12

CPU_STP#

ENABLE
SPEED
STEP

DISABLE
SPEED
STEP

DEFAULT

R597
@10K_0402_5%

R598
@10K_0402_5%

TX_EN

DISABLE
CPU FREQ
SETTING

DEFAULT

ENABLE CPU
FREQSETTING

+3V +3V +3V +3V +3V

12

R685
10K_0402_5%

R698

@10K_0402_5%

R669
10K_0402_5%

R668

@10K_0402_5%

R697
10K_0402_5%

R686

@10K_0402_5%

R670
10K_0402_5%

R671

@10K_0402_5%

ETHERN ET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP

PROCESSOR FREQ MULTIPLIER

R677
10K_0402_5%

R678

@10K_0402_5%

32KHZ_S5

32KHZ
OUTPUT
FROM SB200
(INT RTC)

DEFAULT

32KHZ INPUT
TO SB200
(EXT RTC)

+3VALW+3VALW

12

R692
10K_0402_5%

R691

@10K_0402_5%

PCI_AD26<25,30,32,33,34,44>

R580

A A

10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

1

0E

of

28 61,

5

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

1 2

R730

5.6K_0402_5%

1 2

R154 5.6K_0402_5%

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

IDEDA[0..15]

IDEDB[0..15]

SD_D0
SD_D1
SD_D2
SD_D3

SD_D4
SD_D5
SD_D6
SD_D7

SD_D8
SD_D9
SD_D10
SD_D11

SD_D12
SD_D13
SD_D14
SD_D15

SD_SBA0
SD_SBA1
SD_SBA2
SD_SCS3#

SD_SCS1#
SD_SIOW#
SD_SIOR#
SD_DACK#

PD_D0
PD_D1
PD_D2
PD_D3

PD_D4
PD_D5
PD_D6
PD_D7

PD_D8
PD_D9
PD_D10
PD_D11

PD_D12
PD_D13
PD_D14
PD_D15

PD_A0
PD_A1
PD_A2
PD_CS#3

PD_IOW#
PD_IOR#
PD_DACK#

R733

4.7K_0402_5%

1 2

1 2

R748

8.2K_0402_5%

R168 4.7K_0402_5%

1 2

SD_SIORDY

SD_DREQ

SD_IRQB

1 2

R162 8.2K_0402_5%

PD_IORDY
PD_DREQ
PD_IRQA

IDEDA[0..15]<26>

IDEDA0
IDEDA1
IDEDA2
IDEDA3

RP90 33_0804_8P4R_5%

IDEDA4
IDEDA5
IDEDA6

D D

IDESAA0<26>
IDESAA1<26>
IDESAA2<26>

IDECS#A3<26>

IDECS#A1<26>
IDEIOW#A<26>
IDEIOR#A<26>

IDEDACK#A<26>

IDEIORDYA<26>

C C

IDEREQA<26>
IDEIRQA<26>

IDEIORDYB<26>

IDEREQB<26>

IDEIRQB<26>

B B

IDESAB0<26>
IDESAB1<26>

A A

IDESAB2<26>

IDECS#B3<26>

IDECS#B1<26>

IDEIOW#B<26>

IDEIOR#B<26>
IDEDACK#B<26>

IDEDA7

RP88 33_0804_8P4R_5%

IDEDA8
IDEDA9
IDEDA10
IDEDA11

RP89 33_0804_8P4R_5%

IDEDA12
IDEDA13
IDEDA14
IDEDA15

RP87 33_0804_8P4R_5%

IDESAA0
IDESAA1
IDESAA2
IDECS#A3

RP85 33_0804_8P4R_5%

IDECS#A1 PD_CS#1

RP86 33_0804_8P4R_5%

R732 33_0402_5%

1 2

R734 33_0402_5%

1 2

R747 33_0402_5%

1 2

R165 33_0402_5%

1 2

R159 33_0402_5%

1 2

R164 33_0402_5%

1 2

IDEDB[0..15]<26>

IDEDB0
IDEDB1
IDEDB2
IDEDB3

RP8 33_0804_8P4R_5%

IDEDB4
IDEDB5
IDEDB6
IDEDB7

RP7 33_0804_8P4R_5%

IDEDB8
IDEDB9
IDEDB10
IDEDB11

RP9 33_0804_8P4R_5%

IDEDB12
IDEDB13
IDEDB14
IDEDB15

RP6 33_0804_8P4R_5%

IDESAB0
IDESAB1
IDESAB2
IDECS#B3

RP3 33_0804_8P4R_5%

IDECS#B1

RP5 33_0804_8P4R_5%

5

+5VS

1

C731
1000P_0402_50V7K

2

HD_IDERST#

R729
33_0402_5%

1 2

+5VS

R749
100K_0402_5%

+3VS

+3VS

INT_CD_L<35> INT_CD_R <35>
CD_AGND<35>

SD_D7

R133
100K_0402_5%

4

Placea caps . ne ar HDD CONN.

R728
10K_0402_5%

1 2

1 2

1

2

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_DREQ
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#

+5VS

10U_0805_10V4Z

C730
10U_0805_10V4Z

+5VSCD

1

C780
10U_0805_10V4Z

2

JP30

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

HDD CONN

1

C565

2

1

C172

2

1U_0603_10V4Z

Placea caps. nea r CDRO M CONN.

+5VSCD trace to CONN W=100mils

BOM update 7/15

C609 0.1U_0402_16V4Z

1 2

C606 10U_0805_10V4Z

12

INT_CD_L INT_CD_R

SD_IDERST# SD_D8

SD_D6
SD_D5

SD_D4 SD_D12
R1054
10K_0402_5%

1 2

1 2

R130 470_0402_5%

EXTID1<41>

SD_D3

SD_D2

SD_D1

SD_D0

SD_SIOW#
SD_SIORDY
SD_IRQB
SD_SBA1
SD_SBA0
SD_SCS1#
CDLED#

+5VSCD
+5VSCD

SD_CSEL

12

CD-ROM
2'nd HDD
NONE

4

JP26

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

FOX_QL11253-A606

EXIT0 EXIT1

00
01
11

1

C779
1U_0603_10V4Z

2

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PCSEL

R731 470_0402_5%

R735 @100K_0402_5%
PD_A2
PD_CS#3

+5VS

W=100mils

1

C178

2

0.1U_0402_16V4Z

C174

0.1U_0402_16V4Z

1 2

SD_D9
SD_D10
SD_D11

SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#

SD_DACK#

SD_SBA2
SD_SCS3#

R152 100K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C720

0.1U_0402_16V4Z

2

1 2

1 2

C179

1 2

3

1

1000P_0402_50V7K

2

EXTID0 <41>

+5VSCD+5VSCD
+5VSCD
+5VSCD

3

+5VSCD

+5VSCD

+5VS

R155
100K_0402_5%

1 2

Layout & BOM update 7/11

SIDEPWR<25>

CD_PLAY<35,40>

HDD_LED#

12

CDLED#

I0

13

I1

U41D
74HCT08PW_TSSOP14

CR_LED#<37>

R1058
0_0402_5%
1 2

D36

2 1

@RB751V_SOD323

@1K_0402_5%

11

O

1 2

+3VS

2

R396

10K_0402_5%

2N7002_SOT23

R392

10

R687
10K_0402_5%

10K_0402_5%

IDERST_CD#<26>

2

Q45

2

G

9

+5VALW

I0
I1

13

D

S

U41C

8

O

74HCT08PW_TSSOP14

+3VS

12

R715

PCI_RST#

SW_CDP<40>

1

SI3 4 56DV : N CHA NNEL
VGS: 4. 5 V , RDS : 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

+5VALW

SI3456DV-T1_TSOP6

+12VALW

100K_0402_5%

DTC124EK_SC59

+3VS

IDERST_HD#<26>

PCI_RST#<16,25,30,32,33,34,38,44>

6
2

1

R408

Q50

ACT_LED# <39>

R720
10K_0402_5%

1 2

Q48

D

G

12

1

O

PCI_RST#

+5VSCD

S

45

3

G

3I2

0.01U_0402_16V7K

1
2

WITH: 100 mils

1

C507

4.7U_0805_10V4Z

2

1

2

C478

SIDE_PWR#

+5VS

14

U41A

P

I0

3

O

I1

G

74HCT08PW_TSSOP14

7

D

S

HD_IDERST#

Layout & BOM update 7/11

R1057
0_0402_5%

U41B

4

I0

6

O

5

I1

74HCT08PW_TSSOP14

R702

NSW@10K_0402_5%

Title

Size Docu ment Number Re v

Date: Sheet

星期三 七月

1 2

D

S

SD_IDERST#SD_IDERST#_Q

13

Q64
NSW@2N7002_SOT23

G

12

1

O

G

3

2

Q61
NSW@DTC124EK_SC59

+5VALW

I

2

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

30, 2003

1

7/7 Alex C

12

R409
1K_0402_5%

13

2

G

+5VSCD

1 2

29 61,

Q49
2N7002_SOT23

R726
100K_0402_5%

of

0E

A

B

C

D

E

ENE_RTCCLK<31>

1 2

W10

U10
P10

H2

K1

K3
V10
R10

W11

H1

K2

K5

R8

W7

V7

W6

V6

U6

V5

U5
N1
M3

L1

M1

T1

N3

P1

P5

P6

M6
N2
N6
N5
R1
R2
R3

W4

R6

V9

W9

H3
R9

V8

W8

U9
R7

K6

L2

P3

L5

M2

L6

U8

P7

P8

W5

CLK_PCI_PCM<25>

PCI_DEVSEL#<25,32,33,34,44>

J1
J3

J2
J6

SLDATA<31>

PCI_CBE#3<25,32,33,34,44>
PCI_CBE#2<25,32,33,34,44>
PCI_CBE#1<25,32,33,34,44>
PCI_CBE#0<25,32,33,34,44>

PCI_FRAME#<25,32,33,34,44>

PCI_RST#<16,25,29,32,33,34,38,44>
PCI_TRDY#<25,32,33,34,44>
PCI_IRDY#<25,32,33,34,44>
PCI_STOP#<25,32,33,34,44>
PCI_PERR#<25,32,33,34>

PCI_SERR#<25,32,34>

PCI_PAR<25,32,33,34,44>

B_D0/CAD27
B_D1/CAD29
B_D2/RSVD
B_D3/CAD0
B_D4/CAD1
B_D5/CAD3
B_D6/CAD5
B_D7/CAD7
B_D8/CAD28
B_D9/CAD30
B_D10/CAD31
B_D11/CAD2
B_D12/CAD4
B_D13/CAD6
B_D14/RSVD
B_D15/CAD8

B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A7/CAD18
B_A8/CC/BE1#
B_A9/CAD14
B_A10/CAD9
B_A11/CAD12
B_A12/CC/BE2#
B_A13/CPAR
B_A14/CPERR#
B_A15/CIRDY#
B_A16/CCLK
B_A17/CAD16
B_A18/RSVD
B_A19/CBLOCK#
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A23/CFRAME#
B_A24/CAD17
B_A25/CAD19

B_BVD1/CSTSCHG
B_BVD2/CAUDIO
B_CD1#/CCD1#
B_CD2#/CCD2#
B_READY/CINT#
B_WAIT#/CSERR#
B_WP/CCLKRUN#
B_INPACK/CREQ#

B_CE1#/CC/BE0#
B_CE2#/CAD10
B_WE#/CGNT#
B_IORD#/CAD13
B_IOWR#/CAD15
B_OE#/CAD11
B_VS1#/CVS1
B_VS2#/CVS2
B_REG#/CC/BE3#
B_RESET/CRST#

R305

C6

PAR

SERR#B6PERR#

10_0402_5%

1 2

A6

F7

B7

A7

IRDY#

STOP#

TRDY#

F8

A14

C7

RSTIN#

FRAME#

DEVSEL#

Slot

B

C13

F14

A10

B13

A15

PCLK

C/BE0#E2C/BE1#A5C/BE2#C8C/BE3#

GNT#

DATA

REQ#

PCI

Interface

D

S

PCI_REQ#2<25>

+12VS

1 1

S1_D[0..15]<31>

S1_A[0..25]<31>

S2_D[0..15]<31>

S2_A[0..25]<31>

PCI_AD [0 ..3 1 ]<25,28,32,33,34,44>

PCI_CBE # [0 ..3 ]<25,32,33,34,44>

2 2

C335 10P_0402_50V8K

S2_CD1#

1 2

3 3

C350 10P_0402_50V8K

S2_CD2# S2_WAIT#

1 2

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]
PCI_A D[0..31]
PCI_CBE#[0 ..3 ]

Placement near
to PCMCIA
controller

S2_A16

S2_INPACK#<31>

S2_BVD1<31>
S2_BVD2<31>
S2_CD1#<31>
S2_CD2#<31>
S2_RDY#<31>
S2_WAIT#<31>

S2_WP<31>

S2_CE1#<31>
S2_CE2#<31>
S2_WE#<31>

S2_IORD#<31>

S2_IOWR#<31>

S2_OE#<31>
S2_VS1<31>

S2_VS2<31>
S2_REG#<31>
S2_RST<31>

2N7002_SOT23

1 2

R314
100K_0402_5%

R290
47_0402_5%

1 2

Q28

13

G

2

C353 15P_0402_50V8D

S2_D0
S2_D1
S2_D2
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15

S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8

S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
SB_A16
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25

S2_BVD1
S2_BVD2
S2_CD1#
S2_CD2#
S2_RDY#

S2_WP
S2_INPACK#

S2_OE#
S2_VS1
S2_VS2

S2_RST

E19

CLOCK

F17

G15

LATCH

SPKOUT

SLATCH <31>
PCM_SPK# <35>PCI_GNT#2<25>

+3VALW

CB_+3VALW

0.1U_0402_16V4Z

F18

E11

D1

VCCI

VCCP

VCCP

IRQ/DMA

1

1

0.1U_0402_16V4Z

C331
2

2

+3VALW

W12

L3

U7

F3

VCC

VCC

VCC

VCC

Power

Slot

A

1 2

R287
0_0805_5%

C330

N15

G19

B14

VCC

VCC

VCC

E7

VCCC9VCC

+3VALW

S2_VCC

M5

VCCB

S1_VCC

M17

A11

VCCA

GRST#

A_A12/CC/BE2#
A_A14/CPERR#

A_A19/CBLOCK#

A_A20/CSTOP#

A_A21/CDEVSEL#

A_A23/CFRAME#

A_BVD1/CSTSCHG

A_BVD2/CAUDIO

A_CD1#/CCD1#
A_CD2#/CCD2#

A_READY/CINT#

A_WAIT#/CSERR#

A_WP/CCLKRUN#

A_INPACK/CREQ#

A_CE1#/CC/BE0#

A_IORD#/CAD13

A_IOWR#/CAD15

A_REG#/CC/BE3#

A_RESET/CRST#

C332 0.1U_0402_16V4Z

1 2

C374 0.1U_0402_16V4Z

1 2

A_D0/CAD27
A_D1/CAD29

A_D2/RSVD
A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5

A_D7/CAD7
A_D8/CAD28
A_D9/CAD30

A_D10/CAD31

A_D11/CAD2
A_D12/CAD4
A_D13/CAD6
A_D14/RSVD
A_D15/CAD8

A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18

A_A8/CC/BE1#

A_A9/CAD14
A_A10/CAD9

A_A11/CAD12

A_A13/CPAR

A_A15/CIRDY#

A_A16/CCLK

A_A17/CAD16

A_A18/RSVD

A_A22/TRDY#
A_A24/CAD17

A_A25/CAD19

A_CE2#/CAD10
A_WE#/CGNT#

A_OE#/CAD11
A_VS1#/CVS1
A_VS2#/CVS2

W=10mils

U24

H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13

J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18

H19
J15
V11
H17
J17
J14
H18
L14

P13
R13
R19
W15
V15
U14
J18
M19
K17
L18

W=10mils

S1_BVD1
S1_BVD2
S1_CD1#
S1_CD2#
S1_RDY#
S1_WAIT#
S1_WP
S1_INPACK#

S1_OE#
S1_VS1
S1_VS2

S1_RST

S2_VCC
S1_VCC

EC_RSMRST# <26,31,40>

S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9S2_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
SA_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25

R326
47_0402_5%

1 2

Placement near
to PCMCIA
controller

GND

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD4

AD10E3AD9F5AD8G6AD7E1AD6

AD5G5AD3H6AD2G3AD1

AD0

F1

F2

H5

G1

PCI_AD0

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD1

4 4

C12

PCI_AD15

PCI_AD13

PCI_AD10

PCI_AD7

PCI_AD5

PCI_AD6

PCI_AD14

PCI_AD11

PCI_AD12

PCI_AD9

PCI_AD8

AD21A9AD20B9AD19F9AD17

AD15F6AD14B5AD13E6AD12A4AD11

AD18

AD16

A8

E9

B8

PCI_AD16

PCI_AD17

F11

F10

E10

PCI_AD24

PCI_AD21

PCI_AD22

PCI_AD19

PCI_AD23

PCI_AD18

PCI_AD25

PCI_AD20

AD31

AD30

INTA#/MFUNC0

IDSEL

INTB#/MFUNC1

SUSPEND#

E12

PCI_AD30

A13

PCI_AD31

F15

E17

C10

PCM_INTA#

12

PCI_AD20

R292100_0402_5%

D19

PCM_INTB#

B12

A12

B11

E13

C11

PCI_AD27

PCI_AD26

PCI_AD28

PCI_AD29

A16

DMAREQ#/MFUNC2

C15

IRQSER/MFUNC3

DMAGNT#/MFUNC5

LOCK#/MFUNC4

CLKRUN#/MFUNC6

F13

E14

B15

PCM_RI#

R315

1 2

10_0402_5%

RIOUT#/PME#

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

J5

P2

P9

G2

C14

E8

F12

V14

K18

E18

B10

PCM_PME# <32,34,40,41,44>

PCM_RI# <41>
SIRQ <25,38,40>

PCM_SUSP# <40>

PCI1420-GHK

C5

PCI_CLKRUN# <25,32,34,38,40>

12

+3VS

R311@10K_0402_5%

CARDBUS

+3VALW

+3VALW

1

C376
1000P_0402_50V7K

2

S1_A16

S1_BVD1 <31>
S1_BVD2 <31>
S1_CD1# <31>
S1_CD2# <31>
S1_RDY# <31>
S1_WAIT# <31>
S1_WP <31>
S1_INPACK# <31>

S1_CE1# <31>
S1_CE2# <31>
S1_WE# <31>
S1_IORD# <31>
S1_IOWR# <31>
S1_OE# <31>
S1_VS1 <31>
S1_VS2 <31>
S1_REG# <31>
S1_RST <31>

1

C329

4.7U_0805_10V4Z

2

1

2

PCM_INTA#

PCM_INTB#

C346
1000P_0402_50V7K

S1_A23

S1_RST

S1_OE#

S1_CE1#

S1_CE2#

S2_A23

S2_RST

S2_OE#

S2_CE1#

S2_CE2#

S1_CD1#

S1_CD2#

R317
22K_0402_5%

1 2

R322
22K_0402_5%

1 2

CB1420

+3VALW

1

C336

0.1U_0402_16V4Z

2

+3VALW

1

C361

0.1U_0402_16V4Z

2

+3VALW

1

C377
1000P_0402_50V7K

2

R323
22K_0402_5%

1 2

R325
47K_0402_5%

1 2

R324
47K_0402_5%

1 2

R948
43K_0402_5%

1 2

R949
43K_0402_5%

1 2

R289
47K_0402_5%

1 2

R288
22K_0402_5%

1 2

R291
47K_0402_5%

1 2

R950
43K_0402_5%

1 2

R951
43K_0402_5%

1 2

C355 10P_0402_50V8K

1 2

C373 10P_0402_50V8K

1 2

+3VALW

D11

21

RB751V_SOD323

+3VALW

D12

21

RB751V_SOD323

1

C334

0.1U_0402_16V4Z

2

1

C345

0.1U_0402_16V4Z

2

1

C375
1000P_0402_50V7K

2

S1_VCC

S1_VCC

S1_VCC

S1_VCC

S1_VCC

S2_VCC

S2_VCC

S2_VCC

S2_VCC

S2_VCC

PCI_PIRQA# <10,16,25,33,44>

PCI_PIRQB# <25,44>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

0E

of

30 61,

E

5

4

3

2

1

S1_D[0..15]<30>
S1_A[0..25]<30>

S2_D[0..15]<30>

S2_A[0..25]<30>

S2_CD2# <30>
S2_WP <30>

S2_BVD1 <30>
S2_BVD2 <30>
S2_REG# <30>
S2_INPACK# <30>
S2_WAIT# <30>
S2_RST <30>
S2_VS2 <30>

S2_VPP
S2_VCC

S2_RDY# <30>
S2_WE# <30>

S2_IOWR# <30>
S2_IORD# <30>
S2_VS1 <30>

S2_OE# <30>
S2_CE2# <30>

S2_CE1# <30>

S2_CD1# <30>

144G143G142G141G140G139G138G137

G

A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

SOCKET

FOX_1CA94505-T1-VM_144P

136

B68

135

B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10

B9
B8
B7
B6
B5
B4
B3
B2
B1

JP15

S2_CD2#

134

S2_WP

133

S2_D10

132

S2_D2

131

S2_D9

130

S2_D1

129

S2_D8

128

S2_D0

127

S2_BVD1

126

S2_A0

125

S2_BVD2

124

S2_A1

123

S2_REG#

122

S2_A2

121

S2_INPACK#

120

S2_A3

119

S2_WAIT#

118

S2_A4

117

S2_RST

116

S2_A5

115

S2_VS2

114

S2_A6

113

S2_A25

112

S2_A7

111

S2_A24

110

S2_A12

109

S2_A23

108

S2_A15

107

S2_A22

106

S2_A16

105
104
103
102
101

S2_A21

100

S2_RDY#

99

S2_A20

98

S2_WE#

97

S2_A19

96

S2_A14

95

S2_A18

94

S2_A13

93

S2_A17

92

S2_A8

91

S2_IOWR#

90

S2_A9

89

S2_IORD#

88

S2_A11

87

S2_VS1

86

S2_OE#

85

S2_CE2#

84

S2_A10

83

S2_D15

82

S2_CE1#

81

S2_D14

80

S2_D7

79

S2_D13

78

S2_D6

77

S2_D12

76

S2_D5

75

S2_D11

74

S2_D4

73

S2_CD1#

72

S2_D3

71
70
69

CARDBUS

D D

68

S1_CD2#<30>

S1_WP<30>

C C

B B

A A

S1_BVD1<30>
S1_BVD2<30>

S1_REG#<30>

S1_INPACK#<30>

S1_WAIT#<30>

S1_RST<30>
S1_VS2<30>

S1_VPP

S1_VCC

S1_RDY#<30>

S1_WE#<30>

S1_IOWR#<30>

S1_IORD#<30>

S1_VS1<30>
S1_OE#<30>

S1_CE2#<30>

S1_CE1#<30>

S1_CD1#<30>

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22
S1_A16

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13

S1_D6
S1_D12
S1_D5
S1_D11

S1_D4

S1_CD1#

S1_D3

67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]

C320 2.2U_0805_16V4Z

1 2

C308 4.7U_0805_10V4Z

1 2

C312 4.7U_0805_10V4Z

1 2

C313 4.7U_0805_10V4Z

1 2

C333 4.7U_0805_10V4Z

1 2

C328 4.7U_0805_10V4Z

1 2

C327 4.7U_0805_10V4Z

1 2

S1_VCC

1

0.1U_0402_16V4Z

2

S2_VCC

1

0.1U_0402_16V4Z

2

C344

C359

1

C347

2

1

C363

2

PCMCIA POWER CTRL.

+12VALW

4.7U_0805_10V4Z

4.7U_0805_10V4Z

ENE_RTCCLK<30>

+3VALW

SLDATA<30>

SLATCH<30>

8.2K_0402_5%

+5VALW

R279

12

25

7

24

1
2

30
15

16
17

3
5
4

13
19
18

S1_VPP

S2_VPP

1

2

1

2

U23

NC
12V

12V
5V

5V
5V

3.3V

3.3V

3.3V
DATA

LATCH
CLOCK

NC
STBY#
OC#

TPS2216AI

C352

4.7U_0805_10V4Z

C366

4.7U_0805_10V4Z

AVPP
AVCC
AVCC
AVCC

BVPP
BVCC
BVCC
BVCC

RESET

RESET#

MODE

GND

NC
NC
NC

8
9
10
11

23
20
21
22

6
14

26
27
28
29

12

7/7 Alex C

S1_VPP

S1_VPP
S1_VCC

1

C337

4.7U_0805_10V4Z

2

S2_VPP

1

C326

4.7U_0805_10V4Z

2

RSMRST#

SN74LVC32APWLE_TSSOP14

S2_VPP
S2_VCC

+3VALW

14

U16D

12

P

A

11

O

B

G

7

13

EC_RSMRST# <26,30,40>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

1

星期三 七月

0E

of

31 61,

A

Q3
SI2301DS_SOT23

1

C72

1U_0603_10V4Z

1 1

2 2

3 3

4 4

EN_WOLL#<40>

PCI_AD[0..3 1 ]<25,28,30,33,34,44>

PCI_CBE#[0 ..3 ]<25,30,33,34,44>

PCI_FRAME#<25,30,33,34,44>

PCI_DEVSEL#<25,30,33,34,44>

ONBD_LAN_PME#<30,34,40,41,44>

CLK_PCI_LAN<25>
PCI_CLKRUN#<25,30,34,38,40>

15P_0402_50V8D

A

PCI_IRDY#<25,30,33,34,44>

PCI_TRDY#<25,30,33,34,44>
PCI_STOP#<25,30,33,34,44>
PCI_PERR#<25,30,33,34>

PCI_SERR#<25,30,34>
PCI_REQ#1<25>

PCI_GNT#1<25>

PCI_PIRQD#<25,34>

PCI_RST#<16,25,29,30,33,34,38,44>

2

PCI_AD19

PCI_PAR<25,30,33,34,44>

10_0402_5%

C40

2

EN_WOLL#

PCI_A D[0..31]

PCI_CBE#[0 ..3 ]

R78 100_0402_5%

1 2

R61

1 2
1

2

13

B

LANVDD+3VALW

1

2

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

B

C71

0.1U_0402_16V4Z

U6

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100C_QFP128

LANVDD

R87 for AT93C56

AUX/EEDI

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/SMBDATA

NC/M66EN

NC/AVDDH

PCI I/F

NC/HV

NC/HSDAC+

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

NC/GND
NC/GND

CTRL25

RTT3/CRTL18

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

8100C@0.1U_0402_16V4Z

C

108

EEDO

109
111

EESK

106

EECS

117

LED0

115

LED1

114

LED2

113
1

2
5
6

14
15
18
19

121

X1

122

X2

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

8110S@0.1U_0402_16V4Z

12

C

LANVDD

3

CTRL25

1

2

C456

4.7U_0805_10V4Z

R94 5.6K_0402_5%

R87@10K_0402_5%

12

EEDO
EEDI
EESK
EECS

ACTIVITY#

LINK_10_100_1000#

TXD+/MDI0+
TXD-/MDI0­RXIN+/MDI1+
RXIN-/MDI1-

NC/MDI2+
NC/MDI2­NC/MDI3+
NC/MDI3-

X1
X2

R64 5.9K_0603_1%

@0_0402_5%

R60

CTRL25
CTRL18

1

C55

2

ACTIVITY# <43>
LINK_10_100_1000# <43>

+5VS

12

12

R64 5.9K for 8100C

2.49K for 8110S

8110S@0.1U_0402_16V4Z

12

1 2

1

R69
8110S@0_0805_5%

2

C79
8110S@0.1U_0402_16V4Z

1

C144
10U_0805_10V4Z

2

1

C50

0.1U_0402_16V4Z

2

2

C58

0.1U_0402_16V4Z

1

2

C57

1

8110S@0.1U_0402_16V4Z

R49 @0_0805_5%

1

R50 8100C@0_0805_5%

C52

2

8100C@0.1U_0402_16V4Z

D

Layout update 7/10

Q44
2SB1188_SOT89

V2.5_LAN

1

1

C452

0.1U_0402_16V4Z

2

2

12

R95
1K_0402_5%

R59 15K_0402_5%

1

C49

2

27P_0402_50V8J

1

C139

0.1U_0402_16V4Z

2

1

C53

0.1U_0402_16V4Z

2

2

C118

0.1U_0402_16V4Z
1

2

C85

1

1 2

1 2

LANVDD

U8

4

DO

GND

3

DI

2

SK

1

CS

VCC

AT93C46-10SI-2.7_SO8

12

R79 8110S@0_0805_5%

1 2

1

C83
8110S@0.1U_0402_16V4Z

2

V1.8_LAN

1

C112

2

1

C56

0.1U_0402_16V4Z

2

1

C51

0.1U_0402_16V4Z

2

2

C141

0.1U_0402_16V4Z

1

2

C132

1

8110S@0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

5
6

NC

7

NC

8

AT93C56 for 8110S

Y1

X2X1

12

25MHZ_20P

0.1U_0402_16V4Z

LANVDD

V2.5_LAN

E

CTRL18

1

8110S@2SB1188_SOT89

2

1

1

C126

0.1U_0402_16V4Z

2

2

C54

1

2

C138

0.1U_0402_16V4Z

1

2

C120

1

8110S@0.1U_0402_16V4Z

Q46

8110S@4.7U_0805_10V4Z

2

C128 0.1U_0402_16V4Z

LANVDD

1

C35 0.1U for 8100C

0.01U for 8110S

8100C@0.1U_0402_16V4Z
C35

12

C36 8110S@0.01U_0402_16V7K

12

C34 8110S@0.01U_0402_16V7K

12

C33 8110S@0.01U_0402_16V7K

12

LANVDD

C59
27P_0402_50V8J

1

C80

0.1U_0402_16V4Z

2

2

C107
8110S@0.1U_0402_16V4Z

1

E

LANVDD

6/12 Modify Alex C

3

V1.8_LAN

2

1

1

C494

C489

8110S@0.1U_0402_16V4Z

2

2

4@

R6,R7 for 8110S,default stuff on R6

R6 8110S@0_0402_5%

V2.5_LAN

R7 @0_0402_5%

V1.8_LAN

TXD+/MDI0+
TXD-/MDI0-

1

2

1 2

1 2
1 2

1 2

R1010

12

0_0402_5%

C142

0.1U_0402_16V4Z

V1.8_LAN

V_DAC_R

RXIN+/MDI1+

RXIN-/MDI1­V_DAC

NC/MDI2+
NC/MDI2­V_DAC

NC/MDI3+
NC/MDI3- MDO3­V_DAC

LANVDD

2

1

V_DAC

R55 8100C@0_0805_5%

R56 8110S@0_0805_5%
R83 8110S@0_0805_5%

R57 8100C@0_0805_5%

F

12

12

C131

0.1U_0402_16V4Z

LANVDD

V2.5_LAN
V1.8_LAN

V2.5_LAN

F

R12 300_0402_5%

+3VS

R11 300_0402_5%

+3VS

V_DAC

U28

12

TD4-

MX4-

11

TD4+

MX4+

10

TCT4

MCT4

9

TD3-

MX3-

8

TD3+

MX3+

7

TCT3

MCT3

TD2-6MX2-

5

TD2+

MX2+

4

TCT2

MCT2

3

TD1-

MX1-

2

TD1+

MX1+

1

TCT1

MCT1

PULSE_H1285

G

ACTIVITY#

12

MDO3­MDO3+
MDO1­MDO2­MDO2+
MDO1+
MDO0­MDO0+

LINK_10_100_1000#

12

JP21

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

AMP_0-0440470-4

SHLD4
SHLD3

SHLD2
SHLD1

H

16
15

14
13

6/12 Modify Alex C

13
14
15

16
17
18

19
20
21

22
23
24

MDO0+
MDO0-

MDO1+
MDO1-

MDO2+
MDO2-

MDO3+

8110S@49.9_0402_1%

NC/MDI3+

NC/MDI3-

8110S@49.9_0402_1%

8110S@49.9_0402_1%

NC/MDI2+

NC/MDI2-

8110S@49.9_0402_1%

49.9_0402_1%

TXD+/MDI0+

TXD-/MDI0-

49.9_0402_1%

49.9_0402_1%

RXIN+/MDI1+

RXIN-/MDI1-

49.9_0402_1%

MDO0+ <43>
MDO0- <43>

MDO1+ <43>
MDO1- <43>

R41

R42

R43

R44

R47

R48

R40

R39

75_0402_5%

75_0402_5%

C26

12

12

12

8110S@0.01U_0402_16V7K

C27

12

12

12

8110S@0.01U_0402_16V7K

C29

12

12

12

0.01U_0402_16V7K

C28

12

12

12

0.01U_0402_16V7K

R2

12

R1

12

R108110S@75_0402_5%

12

R98110S@75_0402_5%

12

C10

1000P_1206_2KV7K

near U6

@49.9_0402_1%

RXIN-/MDI1­RXIN+/MDI1+

@49.9_0402_1%

R1019

R1020

12
12

C809

12

@0.01U_0402_16V7K

near U28

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1861

30, 2003

401257

G

星期三 七月

of

32 61,

H

12

0E

A

B

C

D

E

0.1U_0402_16V4Z

1

1

C598

1 1

110

VDD199VDD2

VSSC2

22

112

PCI_AD[0..3 1 ]<25,28,30,32,34,44>

2 2

PCI_CBE#[0 ..3 ]<25,30,32,34,44>

PCI_FRAME#<25,30,32,34,44>

PCI_IRDY#<25,30,32,34,44>

PCI_TRDY#<25,30,32,34,44>

PCI_DEVSEL#<25,30,32,34,44>

PCI_STOP#<25,30,32,34,44>
PCI_PERR#<25,30,32,34>

PCI_PAR<25,30,32,34,44>
PCI_REQ#0<25>
PCI_GNT#0<25>

PCI_PIRQA#<10,16,25,30,44>

PCI_RST#<16,25,29,30,32,34,38,44>

3 3

CLK_PCI_1394<25>

PCI_A D[0..31]

PCI_CBE#[0 ..3 ]

PCI_AD16

CLK_PCI_1394

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

R528

1 2

100_0402_5%

12

1

2

25
24
20
19
18
16
15
14
11
10

9
8
7
4
3

2
117
116
115
114
113
109
107
106
103
102
101

98
97
96
95
94

12

1
119
104

105
120
121
123
124
125
127
128

93
92
88
89
90

R520
10_0402_5%

C608
15P_0402_50V8D

U33

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
PAR
REQ#
GNT#
INTA#
PCIRST#
PCICLK

+3VS +3VS

122

32

VDD3

VDD45VDD517VDD6

111

30

VDDC221VDDC1

RAMVDD

46

PVDD136PVDD2

38

PGND247PGND1

IEEE 1394

VT6307S

VSS191VSS2

VSS3

VSS4

VSS5

VSS66VSS713VSS823VSS933VSSC1

RAMVSS

64

31

100

108

118

126

4.7K_0402_5%

R471

56

59

VDDATX0

GNDATX0

NC835NC937NC1041NC1142I2CEEENA

NC1244NC1345NC1448NC1549NC1650NC1751NC1852NC1953NC2054NC21

43

XI

57

XI

12

+3VS

66

73

VDDATX1

GNDATX1

VDDATX2

GNDATX2
VDDARX0

GNDARX0

VDDARX1

GNDARX1

VDDARX2

GNDARX2

SDA/EEDI

SCL/EECK

XTPBIAS0

XTPBIAS1

PHYRESET

XO

58

VT6301-CD_LQFP128

XO

10P_0402_50V8K

EECS

EEDO

PME#

NC1
NC2

XCPS

XREXT

XTPB0M

XTPB0P

XTPA0M

XTPA0P

XTPB1M

XTPB1P

XTPA1M

XTPA1P

NC3
NC4
NC5
NC6
NC7

C548

+3VS

87

80
62

61
72

65
86

79

26
27

EEDI_1394

28

EECK_1394

29
34

39
40

60

1394_XREXT

63

XTPB0-

67

XTPB0+

68

XTPA0-

69

XTPA0+

70

XTPBIAS0

71
74

75
76
77
78

81
82
83
84
85
55

24.576MHz_16P_3XG-24576-43E1

XI

1 2

2

1M_0402_1%

1

6.34K_0603_1%

X3

XO

12

R443

R470

2

1

1 2

C571

0.1U_0402_16V4Z
12

C547
10P_0402_50V8K

C602

0.1U_0402_16V4Z

1K_0402_5%

1K_0402_5%

2

1

C573
47P_0402_50V8J

2

2

+3VS

R472

1 2

R469

1 2

1

C572

2

0.1U_0402_16V4Z

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

54.9_0402_1%

270P_0402_25V8K

0.1U_0402_16V4Z

1

C610

2

U31
1
2
3
4

AT24C02N-10SC-2.7_SO8

1

C611

2

0.1U_0402_16V4Z

A0

VCC

A1

WC

SCL

A2

SDA

GND

0.1U_0402_16V4Z

8
7
6
5

Place close to 1394 chip

54.9_0402_1%

12

12

R495

1

C579

2

R507

54.9_0402_1%

12

12

12

1

C612

2

0.1U_0402_16V4Z

+3VS

EECK_1394
EEDI_1394

R504

0.33U_0805_16V7K

R491

54.9_0402_1%

R477

5.1K_0603_1%

C597

0.1U_0402_16V4Z

1

C593

2

12

R500
510_0402_5%

1

C594

2

+3VS

1

1

C578

2

2

0.1U_0402_16V4Z

JP23

345
2
1

FOXCONN_UV31413

6

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

E

星期三 七月

0E

of

33 61,

A

B

C

D

E

1 1

WL_ON<39,40>

R513 0_1206_5%

+3VS

C607

0.1U_0402_16V4Z

12

1

C605

2

1

1

C603

2

2

1000P_0402_50V7K

0.1U_0402_16V4Z

CLK_PCI_MINI

12

2 2

R519
10_0402_5%

1

C601
15P_0402_50V8D

2

AC97_BITCLK

12

R586
@10_0402_5%

1

C655
@15P_0402_50V8D

2

PCI_PIRQD#<25,32>

CLK_PCI_MINI<25>

PCI_REQ#3<25>

PCI_CBE#3<25,30,32,33,44>

PCI_CBE#2<25,30,32,33,44>

PCI_IRDY#<25,30,32,33,44>

PCI_CLKRUN#<25,30,32,38,40>

PCI_SERR#<25,30,32>

PCI_PERR#<25,30,32,33>

PCI_CBE#1<25,30,32,33,44>

PCI_AD14<25,30,32,33,44>
PCI_AD12<25,30,32,33,44>

PCI_AD10<25,30,32,33,44>

AC97_SYNC<26,28,35,37>

AC97_SDIN1<26,37>

AC97_BITCLK<26,35,37>

PCI_AD31<25,30,32,33,44>
PCI_AD29<25,30,32,33,44>

PCI_AD27<25,30,32,33,44>
PCI_AD25<25,30,32,33,44>

IDSEL : AD22

PCI_AD23<25,30,32,33,44>
PCI_AD21<25,30,32,33,44>

PCI_AD19<25,30,32,33,44>
PCI_AD17<25,30,32,33,44>

PCI_AD8<25,30,32,33,44>
PCI_AD7<25,30,32,33,44>

PCI_AD5<25,30,32,33,44>
PCI_AD3<25,30,32,33,44>

+5VS

PCI_AD1<25,30,32,33,44>

MD_MON<35>

LAN RESERVED LAN RESERVED

TIP

WL_ON

R511 0_0402_5%

1 2

W=40mils

+3VS_MINI_L

CLK_PCI_MINI

PCI_AD22

R521

1 2

100_0402_5%

W=30mils

AC97_BITCLK
MD_MON

MD_MIC<35,37>

MODEM_RI#<41>

3 3

+5VS

C660

@1000P_0402_50V7K

W=30mils

2

1

101
103
105
107
109
111
113
115
117
119
121
123

127

JP8

112

KEY KEY

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

127

129

Mini-PCI SLOT

RING

2
4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

W=30mils

R514 0_0402_5%

1 2

W=40mils

W=40mils

1 2

R525 100_0402_5%

R591 10K_0402_5%

1 2

W=40mils

129

+3VS_MINI_R

MDM_PME#
WLAN_PME#

PCI_AD18
PCI_AD22

PCI_AD18

MD_SPK

2

C663
1000P_0402_50V7K

1

+5VS
PCI_PIRQC# <25,44>
PCI_GNT#4 <25,44>PCI_REQ#4<25,44>
+3VALW
PCI_RST# <16,25,29,30,32,33,38,44>

PCI_GNT#3 <25>
MDM_PME# <30,32,40,41,44>

WLAN_PME# <30,32,40,41,44>
PCI_AD30 <25,30,32,33,44>

PCI_AD28 <25,30,32,33,44>
PCI_AD26 <25,28,30,32,33,44>
PCI_AD24 <25,30,32,33,44>

IDSEL : AD18

PCI_AD22 <25,30,32,33,44>
PCI_AD20 <25,30,32,33,44>
PCI_PAR <25,30,32,33,44>
PCI_AD18 <25,30,32,33,44>
PCI_AD16 <25,30,32,33,44>

PCI_FRAME# <25,30,32,33,44>
PCI_TRDY# <25,30,32,33,44>
PCI_STOP# <25,30,32,33,44>

PCI_DEVSEL# <25,30,32,33,44>
PCI_AD15 <25,30,32,33,44>

PCI_AD13 <25,30,32,33,44>
PCI_AD11 <25,30,32,33,44>

PCI_AD9 <25,30,32,33,44>
PCI_CBE#0 <25,30,32,33,44>

PCI_AD6 <25,30,32,33,44>
PCI_AD4 <25,30,32,33,44>
PCI_AD2 <25,30,32,33,44>
PCI_AD0 <25,30,32,33,44>

AC97_SDOUT <26,28,35,37>
AC97_RST# <26,35,37>

MD_SPK <35,37>

+3VAUX

1

C674
1U_0603_10V4Z

2

1

C625

2

0.1U_0402_16V4Z

R571 0_1206_5%

1 2

1

C618

2

1000P_0402_50V7K

+5VS

C631

4.7U_0805_10V4Z

+3VS_MINI_L

+3VAUX

C600

4.7U_0805_10V4Z

1

C654

0.1U_0402_16V4Z

2

1

C676

2

0.1U_0402_16V4Z

+3VS_MINI_R

1

C596

4.7U_0805_10V4Z

2

1

C599

2

+3VS

1

1

C592

2

2

1000P_0402_50V7K

1

1

C595

2

2

1000P_0402_50V7K

1

C604

4.7U_0805_10V4Z

2

0.1U_0402_16V4Z

+3VALW

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Title

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

E

0E

of

34 61,

A

B

C

D

E

F

G

H

+5VALW

12

R296

6.8K_0402_5%

1
4

ADJ

3

12

R327

10K_0402_5%

LEFT <36>
RIGHT <36>
MD_MIC <34,37>

L_HP <36>
R_HP <36>

Title

Size Docu ment Number Re v

Date: Sheet

Q34

R332

1 2

30K_0402_5%

C396

12

68P_0402_50V8K

1

C395

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

星期三 七月

G

R741

R258

R260

R257

R259

@10K_0402_5%

R349

10U_0805_10V4Z

XTL-IN
XTL-OUT

12

12

MONO_IN

MICIN

MD_MONRC
LINEL_IN_C
LINER_IN_C

+5VS

12

12

0_0805_5%

2
3

11

6

10

5
8

12
13
14
15
16
17
18
20
21
22
23
24

VDDA

C

2

B

E

12

D6
1SS355_SOD323

12

1

C416

2

U27

XTL-IN
XTL-OUT

RESET#
BIT-CLK
SYNC
SDATA-OUT
SDATA-IN

PC-BEEP
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
CD-L
CD-R
MIC1
MIC2
LINE-L
LINE-R

CD_AGNDRC

12

R357
10K_0402_5%

12

R358
10K_0402_5%

1

Q35
2SC2411K_SC59

3

1

C420
10U_0805_10V4Z

2

R354 0_0402_5%

1

0.1U_0402_16V4Z
2

VSS4VSS7AVSS26AVSS

D

12

VDDC

AVDD_AC97

C418

0.1U_0402_16V4Z

9

VDD1VDD

CD-GND

42

19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C413

MONO_IN_R MONO_IN

1 2

1U_0603_10V4Z

12

Close to AC97 CODEC

R355

2.4K_0402_5%

HB-1M2012-121JT03_0805

1

1

2

LINE-OUTL

VREF

VREFOUT

AFILT1
AFILT2

VRAD
VRDA
CAP1

JD/SDIN1

TEST1

ID0#
ID1#

EAPD

SPDIFO

HP-OUT-L

HP-OUT-R

2

35
36
37

27
28

29
30

31
32
33
34

NC

43
44
45
46
47
48
39
40

NC

41

C406

10U_0805_10V4Z

C394

38

AVDD25AVDD

ALC202A F_LQFP48

LINE-OUTR

MONO-OUT

@1000P_0402_50V7K

+5VALW

12

C392

LINEL

LINER

+AUD_REF

C390 1000P_0402_50V7K

1 2

1 2
C389 1000P_0402_50V7K
C383 1U_0603_10V4Z

1 2
C382 1U_0603_10V4Z

1 2
C381 1U_0603_10V4Z

1 2
R965 0_0402_5%

1 2

R345 @0_0402_5%

1 2

LINEL_HP
LINER_HP

E

0.1U_0402_16V4Z

L27

VDDA+3VS

2

1

MDMIC

+AUD_VREF

EAPD <36>

22U_1206_10V4Z

1

1

C411

C403

2

2

1U_0603_10V4Z

2

C388
@1000P_0402_50V7K

1

C380 4.7U_0805_10V4Z
C378 4.7U_0805_10V4Z
C379 1U_0603_10V4Z
C386 1000P_0402_50V7K

1U_0603_10V4Z

VDDA

C399 4.7U_0805_10V4Z
C402 4.7U_0805_10V4Z

C391

0.1U_0402_16V4Z

1

C408

2

1 2
1 2
1 2
1 2

Layout & BOM update 7/15

1

1

C385

C384

0.1U_0402_16V4Z

2

2

1 2
1 2

+AUD_VREF

1

2

F

U26

VIN2SD

GND5VOUT

LP3965EMP-ADJ_SOT223-5

+AUD_REF

1

C387
@10U_0805_10V4Z

2

BEEP#<40>

1 1

+3VALW

1

C737

0.1U_0402_16V4Z

2 2

3 3

2

CLK_14M_CODEC<23>

I9O

DLINE_IN_L<43>

DLINE_IN _R<43>

INT_CD_L<29>

INT_CD_R<29>

Layout & BOM update 7/21

MD_SPK<34,37>

+AUD_REF

4 4

1 2

2.2K_0402_5%

MICIN_IN<39>

C832

1U_0603_10V4Z

Layout & BOM update 7/15

R1061

A

1

2

2

C410

0.1U_0402_16V4Z

1

MD_MON<34>

+3VALW

12

R742

10

U44C

OE#

SN74LVC125APWLE_TSSOP14

100K_0402_5%

R254

8

1 2

10K_0402_5%

0.22U_0603_16V7K

DLINE_IN_L

R331 6.8K_0402_5%

R328 6.8K_0402_5%

R347 6.8K_0402_5%
R344 6.8K_0402_5%
R341 6.8K_0402_5%
R340 6.8K_0402_5%

@0_0402_5%

R356

C417

22P_0402_25V8K

R346 20K_0402_5%
R348 33K_0402_5%

12
12

BOM update 7/15

R336
R337

CD_AGND<29>

+3VALW

14

0.1U_0402_16V4Z

P

3

O4I

G

1

C305

2

R330

6.8K_0402_5%

12
12

R329

6.8K_0402_5%

12
12

12
12
12
12

12

1 2

24.576MHZ_16P_1BX24576EE1B

1

2

10K_0402_5%

12
12

1K_0402_5%

R342 6.8K_0402_5%
R343 6.8K_0402_5%

B

U45B

SN74LVC14APWLE_TSSOP14

7

PCM_SPK#<30>

SB_SPKR<26>

R352 1M_0402_5%

Y5

1 2

AC97_RST#<26,34,37>

AC97_BITCLK<26,34,37>

AC97_SYNC<26,28,34,37>
AC97_SDOUT<26,28,34,37>

AC97_SDIN0<26>

MD_SPKR

C412 0.1U_0402_16V4Z

CDL
CDR

MD_MONR

LINEINL_R
LINEINR_R

12
12

C734

1 2

C306

1 2

1U_0603_10V4Z

C310

1 2

1U_0603_10V4Z

C311

1 2

1U_0603_10V4Z

LINEINL_R

LINEINR_RDLINE_ IN _ R

CDL
CDR

1

C414

22P_0402_25V8K

2

1 2

C407 1U_0603_10V4Z
C400 1U_0603_10V4Z
C401 1U_0603_10V4Z
C398 1U_0603_10V4Z
C397 1U_0603_10V4Z
C393 1U_0603_10V4Z

1

C415
15P_0402_50V8D

2

R350 22_0402_5%

R351 22_0402_5%

C409

0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2

CD_AGNDR

C405 0.1U_0402_16V4Z

@100K_0402_5%

1 2

560_0402_5%

1 2

560_0402_5%

1 2

560_0402_5%

MD_SPKRC

12

1 2

C

+3VALW

12

R295
@4.7K_0402_5%

2

G

1 3

D

S

@2N7002_SOT23

CD_PLAY <29,40>

BOM update 7/11

VDDA

R345 Pin45 FREQ. SEL

X

X

ON

X

SCHEM AT IC , M/ B LA- 1861

401257

30, 2003

24.576MHZ

X

14.318MHZ

ON

48MHZ

L26

1 2

L22

1 2

L24

1 2

L28

1 2

L25

1 2

DGND AGND

35 61,

H

@0_0805_5%

@0_0805_5%

@0_0805_5%

@0_0805_5%

GNDA

0_0805_5%

of

0E

A

1 1

B

0.1U_0402_16V4Z

C356

C

1

2

4.7U_0805_10V4Z

1

C354

2

22U_1206_10V4Z

D

VDDA

12

R318

+5V_AMP

L23 0_1206_5%

1

C348

2

1 2

VDDA

SHUTDOWN#

2N7002_SOT23

100K_0402_5%

13

D

R320 @0_0402_5%

2

1 2

G

Q29

R321 0_0402_5%

S

1 2

E

EAPD <35>
EC_MUTEO <41>

U25

3

PVDD

SHUTDOWN#

11

C3670.1U_0402_16V4Z

R308

1.3K_0402_5%

1 2

1 2

LEFT_R
RIGHT_R

R319

1.3K_0402_5%

1 2

HPS<40>

1 2
1 2

LHP_R

1 2

RHP_R

1 2

0.47U_0603_16V7K

C3600.47U_0603_16V7K
C3700.47U_0603_16V7K
C3580.47U_0603_16V7K
C371

LEFT_C
RIGHT_C
LHP_C

RHP_C

VOLUME

1 2

R312

1.3K_0402_5%

1 2

R307

1.3K_0402_5%

VDDA

2

C404

BOM update 7/15

R1059

1 2

1.6K_0402_5%

2 2

R339
@1K_0402_1%

12

12

1

R338
1K_0402_5%

0.1U_0402_16V4Z

R334
@2K_0402_1%

12

R335
@4.3K_0402_5%

INTSPK_L+<39,43>
INTSPK_R+<39,43>

LEFT<35>

RIGHT<35>

L_HP<35>
R_HP<35>

12

INTSPK_L+
INTSPK_R+

R333
@8K_0402_5%

C3620.47U_0603_16V7K

1 2

C3690.47U_0603_16V7K

1 2

C3570.47U_0603_16V7K

1 2

C3720.47U_0603_16V7K

1 2

VOLUME

12

HPS

PVDD

7

VDD

22

HP/LINE#

21

VOLUME

14

LOUT+

24

ROUT+

9

LLINEIN
RLINEIN5SEDIFF

10

LHPIN

4

RHPIN

16

FADE#

TPA6011A4_TSSOP24

SE/BTL#
BYPASS

LOUT-

ROUT-

SEMAX

PGND
PGND
AGND

15

HPS

23
17
12
2
8

LIN

6

RIN

19
20

1
13
18

1U_0603_10V4Z

R286 100K_0402_5%

1 2

INTSPK_L­INTSPK_R-

1

C365

2

0.47U_0603_16V7K

1

C368

2

1

C364

2

0.47U_0603_16V7K

INTSPK_L- <39>
INTSPK_R- <39>

+5VS

R310

10K_0402_5%

R309

@10K_0402_5%

VDDA VDDA

12

12

12

R313
@0_0402_5%

12

R316
0_0402_5%

7/7 Alex C

1

O

Q33
@DTC124EK_SC59

G

I

3

2

MSB3<40>

MSB2<40>

MSB1<40>

MSB0<40>

3 3

00 0

MSB1MSB2

0
0001
0010
0011
0100
0101
011
0111

1

O

Q31
@DTC124EK_SC59

G

I

3

2

MSB0MSB3

0

4.7225

4.47

4.34

4.0485

3.86

0

3.56
1000
1001
1010
1011
1100
1101

4 4

1110
1111

2.84

2.76

2.67

1

I

2

BTL SEVo (dB)

20
20
20
20
20
20

14
12
10
8
6

O

G

3

Q32
@DTC124EK_SC59

(dB)

14
14
14
14
14

143.719

83.4

63.272

43.1659

23.05

02.938

1

O

Q30
@DTC124EK_SC59

G

I

3

2

Layout & BOM update 7/15

D

S

DOCK_MIC

INT_MIC<37,39>

INTMICOFF#<43>

LINE_OUT_PLUG<39,43>

DOCK_OUT_PLUG<43>

1 2

R615 SPR@39K_0402_5%

+5VS

MICOFF#

R280 100K_0402_5%

1 2

1 2

R281 SPR@100K_0402_5%

13

Q58
2N7002_SOT23

G

2

1 2

R637 470K_0402_5%

1

C685
@10U_0805_10V4Z

2

+5VS

5

2

I0

1

I1

3

R968

1 2

NSPR@0_0402_5%

DOCK_MIC <43>

+12VS

SPR@0.1U_0402_16V4Z

1 2

C321

U22

P

4

O

G

SPR@TC7SH32FU_SSOP5

HPS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

E

星期三 七月

0E

of

36 61,

MDC Note
Pin 1 is NC for Pctel and connexant MDC modem
Pin 2 is NC for Pctel and connexant MDC modem

+3VALW

1

C351

4.7U_0805_10V4Z
2

BlueTooth Interface

Bluetooth Connector

JP16

1

USB20P5+

L29 0_0603_5%

USB20P5-

L30 0_0603_5%

BT_ON#<39,41>

12
12

+3VALW

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

ACES_87213-1000

SWITCH BOARD CONN.

+5VS

NUMLED#<40>

CAPSLED#<40>

INT_MIC<36,39>

GNDA

JP3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

SW BD CONN

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

1000P_0402_50V7K

2

C349

0.1U_0402_16V4Z

1

C341

+3VALW

AC97_SDOUT<26,28,34,35>

1

2

MD_MIC<34,35>

R303

1 2

0_0603_5%

AC97_RST#<26,34,35>

USER_BTN0# <41>
USER_BTN1# <41>
BT/WL_ON/OFF# <39,41>SCROLLED#<40>

R302 0_0603_5%

1 2

1

C342

0.1U_0402_16V4Z

2

+3VALW

MDC Conn.

JP14

1

MONO_OUT/PC_BEEP

3

AGND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

QTC_C104A-030F030P28

1

C339

2

@1000P_0402_50V7K

AC97_SDATA_IN1
AC97_SDATA_IN0

+5VALW

C23

1 2

0.1U_0402_16V4Z
SYSON#

+5VALW

C25

1 2

0.1U_0402_16V4Z
SYSON#

+5VALW

C727

1 2

0.1U_0402_16V4Z
SYSON#

@0.1U_0402_16V4Z

1

C340

2

AUDIO_PWDN

MONO_PHONE

RESERVED

GND

+5V
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
AC97_SYNC

GND

AC97_BITCLK

U2

1

GND

2

IN

3

EN1#

4

EN2#

TPS2042ADR_SO8

U3

1

GND

2

IN

3

IN

4

EN#

TPS2041ADR_SO8

U43

1

GND

2

IN

3

IN

4

EN#

TPS2041ADR_SO8

+5VMDC

1 2

R304 @0_0805_5%

@1000P_0402_50V7K

C338

12

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

BT_DETACH

BT_ON#

USBBlue+

R301 0_0603_5%

USBBlue-

R294 10K_0402_5%

R299 22_0402_5%
R298 @22_0402_5%

8

OC1#

7

OUT1

6

OUT2

5

OC2#

8

OUT

7

OUT

6

OUT

5

OC#

8

OUT

7

OUT

6

OUT

5

OC#

1 2

R300 0_0603_5%

1 2

1 2

12
12

1 2
1

2

USB_VCCC

USB_VCCD

+5VALW

BT_DETACH <41>
MD_SPK <34,35>

BT_WAKE_UP

R297
10_0402_5%

C343
22P_0402_25V8K

OVCUR#0 <26,44>
USB_VCCA
USB_VCCB

OVCUR#1 <26,44>SYSON#<43,45>

OVCUR#2 <26,44>

OVCUR#3 <25,44>

+3VS

R293
100K_0402_5%

1 2

MDC_DET# <38>

BT_WAKE_UP <41>
AC97_SYNC <26,28,34,35>

AC97_SDIN1 <26,34>

AC97_BITCLK <26,34,35>

USB20P5+ <26>
USB20P5- <26>
+3VALW

USB_VCCA
USBP1­USBP1+

@SF10402ML080C

USB20EP1-<44>

USB20EP1+<44>

USB20P0-<26,43>
USB20P0+<26,43>

USB_VCCB
USBP2­USBP2+

@SF10402ML080C

USB20EP2-<44>

USB20EP2+<44>

USB20P1-<26,43>

USB20P1+<26,43>

DSSA-P3100SB

220P_1808_3KV8K

@SF10402ML080C

1

TVS7

TVS9

1

TVS6

2

2

@SF10402ML080C

R1011 USB20@0_0402_5%

1 2

R1012 USB20@0_0402_5%

1 2

L32 NUSB20@0_0402_5%
L33 NUSB20@0_0402_5%

@SF10402ML080C

1

1

TVS8

2

2
@SF10402ML080C

R1013 USB20@0_0402_5%

1 2

R1014 USB20@0_0402_5%

1 2

L34 NUSB20@0_0402_5%
L35 NUSB20@0_0402_5%

RJ11 CONN.

MOD_TIP

MOD_RING

C19

1

1
2

2

1

2

1

2

VH1

MOD_RING
MOD_TIP

USB CONNECTOR 1

1

TVS5

2

12
12

150U_D2_6.3VM

USB20@15K_0402_5%

C435

+

R971

USB CONNECTOR 2

1

TVS4

2

12
12

150U_D2_6.3VM

USB20@15K_0402_5%

C430

1

+

2

R973

JP22

1

TIP

2

RING

5

GND

6

GND

RJ11-ALLT_C10121-10204

C18
220P_1808_3KV8K

W=40mils

1

1

C425

2

2

0.1U_0402_16V4Z

12

12

R972
USB20@15K_0402_5%

W=40mils

1

C421

2

0.1U_0402_16V4Z

12

12

R974
USB20@15K_0402_5%

JP4

1
2

HEADER 2

USB_VCCA

1

C429
1000P_0402_50V7K

2

USBP1­USBP1+

USB_VCCB

1

C423
1000P_0402_50V7K

2

USBP2­USBP2+

JP18

1
2
3
4

2551A-04G5T

JP17

1

VCC

2

D-

3

D+

4

GND

2551A-04G5T

VCC
D­D+
GND

USB_VCCD
USBP4-

5 IN 1 CONN

+5VS

JP32

1

0_0603_5%

USB20P4+<26>
USB20P4-<26>
CR_LED#<29>

L18
L21 0_0603_5%

L_USB4_D+

12
12

CR_LED# CR_LED#

1

2

2

3

3

4

4

5

5

6

6

4 in1 CONN

+5VS

7

7

8

8

L_USB4_D+

9

9

L_USB4_D-L_USB4_D-

10

10

11

11

12

12

USBP4+

TVS10

@SF10402ML080C

USB20EP4-<44>

USB20P3-<26>
USB20P3+<26>

@SF10402ML080C

1

1

1

TVS11

TVS3

2

2

@SF10402ML080C

2

R1015 USB20@0_0402_5%

1 2

R1016 USB20@0_0402_5%

1 2

L52 NUSB20@0_0402_5%
L50 NUSB20@0_0402_5%

150U_D2_6.3VM

12
12

USB20@15K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB CONNECTOR 4(RIGHT)

C230

W=40mils

1

+

C232

2

0.1U_0402_16V4Z

R975

12

USB_VCCD

1

1

C231
1000P_0402_50V7K

2

2

USBP4­USBP4+

12

R976
USB20@15K_0402_5%

JP11

1

VCC

2

D-

3

D+

4

GND

2569AR_04G3T

USB_VCCC
USBP3­USBP3+

@SF10402ML080C

USB CONNECTOR 3(LEFT)

@SF10402ML080C

1

1

1

TVS14

2
@SF10402ML080C

USB20EP3-<44>USB20EP4+<44>

USB20EP3+<44>

USB20P2-<26>
USB20P2+<26>

L53 @0_0402_5%
L55 @0_0402_5%

TVS12

TVS13

2

2

R1017 @0_0402_5%

1 2

R1018 @0_0402_5%

1 2

12
12

1

1

2

2

12

R978
@15K_0402_5%

USB_VCCC

C778
@1000P_0402_50V7K

1

USBP3-

2

USBP3+

3
4

@2569AR_04G3T

37 61,

JP13

of

VCC
D­D+
GND

W=40mils

1

+

C781

@150U_D2_6.3VM

@15K_0402_5%

Title

Size Docu ment Number Re v

Date: Sheet

星期三 七月

C777

2

@0.1U_0402_16V4Z

12

R977

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

30, 2003

0E

10

CLK_PCI_SIO

1 2
2

1

1 2
2

1

RP51

1 8
2 7
3 6
4 5

100K_0804_8P4R_5%

1 2

1 2

R576
10_0402_5%

C632
15P_0402_50V8D

R609
@10_0402_5%

C669
@15P_0402_50V8D

PID0
PID1
PID2
PID3

PID4

FDD_DET#

H H

CLK_14M_SIO

G G

+3VS

F F

R531 100K_0402_5%

R530 100K_0402_5%

E E

D D

C C

B B

9

LPC_AD[0..3]<25,40>

LPC_FRAME#<25,40>

LPC_DRQ#1<25>

R585 10K_0603_5%

1 2

R539 10K_0603_5%

+3VS

R526 10K_0402_5%

1 2

R529 10K_0402_5%

1 2

+3VS

C626

4.7U_0805_10V4Z

NB_RST#<8,11,16,25>

PCI_RST#<16,25,29,30,32,33,34,44>

1 2

R610 10K_0603_5%

1 2

PCI_CLKRUN#<25,30,32,34,40>

CLK_PCI_SIO<25>

CLK_14M_SIO<23>

MDC_DET#<37>

1

C634

2

0.1U_0402_16V4Z

LPC_AD[0..3]

SIRQ<25,30,40>

PID0<24>
PID1<24>
PID2<24>
PID3<24>
PID4<24>

0.1U_0402_16V4Z

1

C630

2

R599

1 2

R600

1 2

8

7

SUPER I/O S MsC FDC47N227

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_RST#

CLK_PCI_SIO
CLK_14M_SIO
PID0

PID1
PID2
PID3
PID4

FDD_DET#

1

C617

2

0.1U_0402_16V4Z

0_0402_5%

@0_0402_5%

1

2

U38

20

LAD0

21

LAD1

22

LAD2

23

LAD3

24

LFRAME#

25

LDRQ#

26

PCIRST#

27

LPCPD#

50

GPIO12/IO_SMI#

17

IO_PME#

30

SIRQ

28

CLKRUN#

29

PCICLK

19

CLK14

48

GPIO10

54

GPIO15

55

GPIO16

56

GPIO17

57

GPIO20

58

GPIO21

59

GPIO22

6

GPIO24

32

GPIO30

33

GPIO31

34

GPIO32

35

GPIO33

36

GPIO34

37

GPIO35

38

GPIO36

39

GPIO37

40

GPIO40

41

GPIO41

42

GPIO42

43

GPIO43

44

GPIO44

45

GPIO45

46

GPIO46

47

GPIO47

51

GPIO13/IRQIN1

52

GPIO14/IRQIN2

64

GPIO23/FDC_PP

18

VTR

53

VCC

65

VCC

93

VCC

7

VSS

31

VSS

60

VSS

76

VSS

LPC47N227 B_TQFP100

LPC_RST#

PD2/WRTPRT#
PD4/DSKCHG#

BUSY/MTR1#

SLCT/WGATE#

ERROR#/HDSEL#

AUTOFD#/DRVDEN0#

STROBE#/DS0#

SLCTIN#/STEP#

IRMODE/IRRX3

GPIO11/SYSOPT

LPC_RST# <40>

PD0/INDEX#

PD1/TRK0

PD3/RDATA#

PD6/MTR0#

PE/WDATA#

ACK#/DS1#

INIT#/DIR#

DTR2#
CTS2#
RTS2#

DSR2#

TXD2
RXD2

DCD2#

RI2#

DTR1#
CTS1#
RTS1#

DSR1#

TXD1
RXD1

DCD1#

RI1#

IRRX2

IRTX2

RDATA#

WDATA#

WGATE#

HDSEL#

DIR#

STEP#

DS0#

INDEX#

DSKCHG#

WRTPRT#

TRK0#

MTR0#

DRVDEN0
DRVDEN1

PD5
PD7

6

LPD[0..7]
LPD0

68

LPD1

69

LPD2

70

LPD3

71

LPD4

72

LPD5

73

LPD6

74

LPD7

75

LPTBUSY

79

LPTPE

78

LPTSLCT

77

LPTERR#

81

LPTACK#

80

LPTINIT#

66

LPTAFD#

82

LPTSTB#

83

LPTSLCTIN#

67
100

CTS#2

99
98

DSR#2

97
96
95
94
92

89
88
87
86
85
84
91
90

63
61
62

16
10
11
12
8
9
5
13
4
15
14
3
1

2
49

R577 1K_0402_5%
DCD#2
RI#2

DTRA#
CTSA#
RTSA#
DSRA#
TXDA
RXDA
DCDA#
RIA#

IRMODE
IRRX
IRTXOUT

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV05V#
INDEX#
DISKCHG#
WP#
TRACK0#
MTR0#
3MODE#

R606 10K_0402_5%

R544 @10K_0402_5%

1 2

R548 10K_0402_5%

1 2

Base I/O Address

0 = 02Eh
1 = 04Eh

*

1 2

5

LPD[0..7] <43>

LPTBUSY <43>
LPTPE <43>
LPTSLCT <43>
LPTERR# <43>
LPTACK# <43>
LPTINIT# <43>
LPTAFD# <43>
LPTSTB# <43>
LPTSLCTIN# <43>

IRMODE <39>
IRRX <39>
IRTXOUT <39>

12

+3VS

+5VS

CTSA#
DCDA#

RIA#

TRACK0#
WP#
INDEX#
DISKCHG#

HDSEL#
WGATE#
WDATA#
FDDIR#

4

C439

0.1U_0402_16V4Z

RIA0<41>

SUSP#<40,45,49>

RP63
1 8
2 7
3 6
4 5

NSPR@4.7K_0804_8P4R_5%

RP66
1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

STEP#
MTR0#
RDATA#

+5VS

DRV05V#

1

C168

2

10U_0805_10V4Z

Placea caps. n ear FDD CONN.

3

+5VALW

1

2

1 2

C440 0.1U_0402_16V4Z

1 2

C436 0.1U_0402_16V4Z

DTRA#
RTSA#
TXDA
CTSA#
RIA# RI1#
RXDA
DCDA#
DSRA#
RIA0

SUSP#

+3VS

+5VS

CTS#2
DSR#2DSRA#
DCD#2
RI#2

HDSEL#
WGATE#
WDATA#
FDDIR#

STEP#
MTR0#
RDATA#
DRV05V#

28

24

1

2
14
13
12
19
18
17
16
15
20

23
22

RP64
1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%

RP121
1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

RP122
1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

26

U4

C1+

VCC

C1­C2+

C2­TIN1
TIN2
TIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUTB2

FORCEON
FORCEOFF#

SPR@MAX3243CAI_SSOP28

+3VS

+5VS

TOUT1
TOUT2
TOUT3

RIN1
RIN2
RIN3
RIN4
RIN5

INVLD#

GND

2

27

V+

3

V-

9
10
11
4
5
6
7
8

21
25

RXDA

+5VS trace to CONN W=100mils

1

C574

2

1U_0603_10V4Z

C736

0.1U_0402_16V4Z

1

C160

2

0.1U_0402_16V4Z

+5VS

12

INDEX#
DRV05V#
DISKCHG#

MTR0#
FDDIR#

3MODE#
FDD_DET#

WDATA#
WGATE#
TRACK0#
WP#
RDATA#
HDSEL#

C162

JP31

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES 85203-2602

1

1000P_0402_50V7K

2

52

52

51

51

50

50

49

49

48

48

47

47

46

46

45

45

44

44

43

43

42

42

41

41

40

40

39

39

38

38

37

37

36

36

35

35

34

34

33

33

32

32

31

31

30

30

29

29

28

28

27

27

1

Serial Port

C438

0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

1 2

C437

DTR1#
RTS1#
TXD1
CTS1#

RXD1
DCD1#
DSR1#

R547 1K_0402_5%

1 2

DTR1# <43>
RTS1# <43>
TXD1 <43>
CTS1# <43>
RI1# <43>
RXD1 <43>
DCD1# <43>
DSR1# <43>

FDD CONN.

C735

+5VS

0.1U_0402_16V4Z

1 2

INDEX#

DRV05V#

DISKCHG#

MTR0#

FDDIR#

3MODE#

STEP#STEP#

FDD_DET#

WDATA#
WGATE#

TRACK0#

WP#
RDATA#
HDSEL#

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10

9

8

7

6

5

4

3

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1861

30, 2003

2

401257

星期三 七月

0E

of

38 61,

1

5

4

3

2

1

INT_KBD CONN.

KSI[0 ..7 ]
KSO[0..15]

D D

MAIL_LED#<40>

BT/WL_ON/OFF#<37,41>

+3VALW
+3VALW

C C

2

I

+3VALW

R247

10K_0402_5%

R242 100K_0402_5%

1 2

R241 100K_0402_5%

1 2

NEED CLOSEST JP18 ADD BY EMI REQUEST

+3VALW

3

G

O

DTA114YKA_SC59

1

12

R244
330_0402_5%

1 2

BT/WL_ON/OFF#

R243 0_0402_5%

KB_ID2<40>
KB_ID1<40>

KSI[0..7] <40>
KSO[0..15] <40>

Q27

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

LED+

12

JP12

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

ACES_85201-3005

+3VALW

12

R278
100K_0402_5%

EC_ON

EC_ON<40>

1 2

R276 0_0402_5%

Power BTN

ON/OFFBTN#

Q26

DTC124EK_SC59

D9

1

DAN202U_SC70

SW1

3

4

MCH_MPU-101

R274 100K_0402_5%

1 2

ON/OFF#

3
2

1

O

G

I

3

2

1

2

1000P_0402_50V7K

1

2

ON/OFF# <40>

EC_PWR_ON# <46>

12

1

C319

D8
RLZ20A_LL34

2

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

LID_SW# <40>

TVS1
@SF10402ML080C_0402

+3VALW

@SF10402ML080C_0402

TVS2

ON/OFFBTN#

1

2

SW2

3

4

HCH SMT1-02

1

2

Touch P a d & Stat us LED Conn.

CP1
KSO3
KSO2
KSO1
KSO0

100P_1206_8P4C_50V8

KSO7
KSO6
KSO5
KSO4

100P_1206_8P4C_50V8

KSI7
KSI6
KSI5

B B

A A

KSI4

100P_1206_8P4C_50V8

KSI3
KSI2
KSI1
KSI0

100P_1206_8P4C_50V8

KSO11
KSO10
KSO9
KSO8

100P_1206_8P4C_50V8

KSO15
KSO14
KSO13
KSO12

100P_1206_8P4C_50V8

2
3
4 5

CP2

2
3
4 5

CP6

2
3
4 5

CP5

2
3
4 5

CP3

2
3
4 5

CP4

2
3
4 5

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

JP9

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

ACES_85202-3802

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

T = 12mil
T = 12mil
T = 12mil

+5VS

22P_0402_25V8K

TP_DATA
TP_CLK

IRTXOUT
IRMODE
IRRX

layout update 7/21

2

C710

1

IRTXOUT <38>
IRMODE <38>
IRRX <38>

PMLED_0# <41>
PMLED_1# <41>
BATLED_0# <41>
BATLED_1# <41>
ACT_LED# <29>

BT_ON# <37,41>

LINE_OUT_PLUG <36,43>

INT_MIC <36,37>
MICIN_IN <35>

2

C711
22P_0402_25V8K

1

+3VS

+5VALW

TP_DATA <40>
TP_CLK <40>

1

C833

220P_0402_50V8K

2

+5VS

1

C713

0.1U_0402_16V4Z

2

WL_ON <34,40>

layout & BOM update 7/18 for EMI

1

C836

33P_0402_50V8J

1

2

C837

33P_0402_50V8J

1

2

C838

33P_0402_50V8J

1

2

C839

33P_0402_50V8J

2

layout & BOM update 7/18 for EMI

INTSPK_L+ <36,43>
INTSPK_L- <36>
INTSPK_R+ <36,43>
INTSPK_R- <36>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

1

星期三 七月

0E

of

39 61,

A

B

C

D

E

Layout update 7/10

+3VALW

4.7U_0805_10V4Z

1 1

2 2

3 3

4 4

+3VALW

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK

PS2_DATA
PS2_CLK

FSEL#
SELIO#
FRD#

EC_SMI#

EC_SMD_2 ADB3
EC_SMC_2
EC_SMD_1
EC_SMC_1

+3VALW

1 2

R271 20K_0402_5%

M_SEN#

0.1U_0402_16V4Z

1

C303

C314

2

L19

1 2

MURATA BLM11A20PT_0603

12

1

2

1 2

R256 10K_0402_5%

C304

0.1U_0402_16V4Z
L20

1 2

MURATA BLM11A20PT_0603

CLK_PCI_EC

R270
@10_0402_5%

C315
@15P_0402_50V8D

RP123
1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP124
1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP20
1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP21
1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

LID_SW#

A

1

1

1

C318

2

2

2

0.1U_0402_16V4Z

2

1

1

2

ECAGND

BOM update 7/10

+5VS

+3VALW

+5VALW

10P_0402_50V8K

+3VS

C322

0.01U_0402_16V7K

EC_AVCC

C302
1000P_0402_50V7K

+3VALW

C325

32.768KHZ_12.5P_MC-206

R269

1 2

10K_0402_5%

R284 20M_0603_5%
Y4

1 4

1

2 3

2

1 2

1

2

J1 JOPEN

KBRST#<26>

KSI[0..7 ]<39>

KSO[0..15]<39>

R283

C324

10P_0402_50V8K

+3VS

4.7U_0805_10V4Z

LPC_FRAME#<25,38>

LPC_AD0<25,38>
LPC_AD1<25,38>
LPC_AD2<25,38>
LPC_AD3<25,38>

CLK_PCI_EC<25>

12

SCI#<26>

GA20<26>

KBD_CLK<43>

KBD_DATA<43>

PS2_CLK<43>

PS2_DATA<43>

TP_CLK<39>
TP_DATA<39>
LID_SW#<39>

12

120K_0402_5%

EC_SMI#<26>

EC_SWI#<26>

SYSON<45>

SW_CDP<29>

EC_RSMRST#<26,30,31>

PCM_SUSP#<30>

ENABLT#<10,16,24>

BKOFF#<24>

SUSP#<38,45,49>
VR_ON<45,53>

FSEL#<41>

SIRQ<25,30,38>

MSB0<36>
MSB1<36>

MSB2<36>
MSB3<36>

C317

KSI[0 ..7 ]
KSO[0..15]

B

C316

1

1

0.1U_0402_16V4Z

2

2

7
8

9
15
14
13

CLK_PCI_EC
EC_RST#

SCI#

GA20
KBRST#

10
18
19
22
23

31

5

6

KSI0

71

KSI1

72

KSI2

73

KSI3

74

KSI4

77

KSI5

78

KSI6

79

KSI7

80

KSO0

49

KSO1

50

KSO2

51

KSO3

52

KSO4

53

KSO5

56

KSO6

57

KSO7

58

KSO8

59

KSO9

60

KSO10

61

KSO11

64

KSO12

65

KSO13

66

KSO14

67

KSO15

68

EC_TINIT#

105

EC_TCK

106

EC_TDO

107

EC_TDI

108

EC_TMS

109

KBD_CLK

110

KBD_DATA

111

PS2_CLK

114

PS2_DATA

115

TP_CLK

116

TP_DATA

117

LID_SW#

118
119

CRY1

158

CRY2

160

EC_SMI#

62
63
69
70
75
76

148
149
155
156

3

4
27
28

FSEL#

173
174

47

PC87591L-VPCN01 A2_LQFP176

16

U21

SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#

IOPD3/ECSCI#

GA20/IOPB5
KBRST/IOPB6

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

TINT#
TCK
TDO
TDI
TMS

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

32KX1/32KCLKIN
32KX2

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

SEL0#
SEL1#
CLK

EC_AVCC

123

136

157

166

95

VDD

VCC134VCC245VCC3

VCC4

VCC5

VCC6

Host interface

AD Input

DA output

PWM
or PORTA

Key matrix scan

PORTB

IOPB7/RING/PFAIL/RESET2

PORTC

PORTD-1

PORTE

JTAG debug port

PS2 interface

PORTJ-2

PORTM

GND117GND235GND346GND4

122

159

IOPE7/CLKRUN/EXWINT46

PORTH

PORTI

PORTJ-1

PORTD-2

PORTK

PORTL

AGND

GND5

GND6

GND7

96

167

137

ECAGND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

161

AVCC

IOPD2/EXWINT24/RESET2

VBAT

AD0
AD1
AD2
AD3

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7

DP/AD8
DN/AD9

DA0
DA1
DA2
DA3

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

IOPB0/URXD
IOPB1/UTXD

IOPB2/USCLK

IOPB3/SCL1
IOPB4/SDA1

IOPC0
IOPC1/SCL2
IOPC2/SDA2

IOPC3/TA1

IOPC4/TB1/EXWINT22

IOPC5/TA2

IOPC6/TB2/EXWINT23

IOPC7/CLKOUT

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21

IOPE4/SWIN

IOPE5/EXWINT40

IOPE6/LPCPD/EXWIN45

IOPH0/A0/ENV0

IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1

IOPH4/A4/TRIS

IOPH5/A5/SHBM

IOPH6/A6
IOPH7/A7

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

IOPJ0/RD

IOPJ1/WR0

SELIO#

IOPD4
IOPD5
IOPD6
IOPD7

IOPK0/A8

IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12

IOPK5/A13_BE0
IOPK6/A14_BE1

IOPK7/A15_CBRD

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19

IOPL4/WR1#

NC212NC320NC421NC585NC686NC791NC892NC997NC10

NC1

11

C820 @1U_0603_10V4Z

1 2

C

98

2

C323
1U_0603_10V4Z

1

81
82
83

ADP_IR

84
87
88
89
90

AD_BID0

93
94

99
100
101
102

32
33
36
37
38
39
40

EN_WOLL#

43

KSO16

153

KSO17

154

MAIL_LED#

162

EC_SMC_1

163

EC_SMD_1

164

LPC_RST#

165
168

EC_SMC_2

169

EC_SMD_2

170
171

PME_EC#

172

EC_THERM#

175
176
1

26
29
30

2
44
24
25

1 2

R268 @0_0402_5%

KBA0

124

KBA1

125

KBA2

126

KBA3

127

KBA4

128

KBA5

131

KBA6

132

KBA7

133

ADB0

138

ADB1

139

ADB2

140
141

ADB4

144

ADB5

145

ADB6

146

ADB7

147

FRD#

150

FWR#

151

SELIO#

152
41

42
54
55

KBA8

143

KBA9

142

KBA10

135

KBA11

134

KBA12

130

KBA13

129

KBA14

121

KBA15

120

KBA16

113

KBA17

112

KBA18

104

KBA19

103
48

BATT1.1+3VALW

BATT_TEMPA <47>

KB_ID1 <39>
KB_ID2 <39>

ALI/MH# <47>
M_SEN# <24,43>

BATT_OVP <48>

DAC_BRIG <24>
EN_FAN1 <7>
EN_FAN2 <7>
IREF <48>

INVT_PWM <24>
HPS <36>

ACOFF <48>
PM_BATLOW# <26>
EC_ON <39>
LID_OUT# <26>
EN_WOLL# <32>

MAIL_LED# <39>
EC_SMC_1 <41,47>
EC_SMD_1 <41,47>
LPC_RST# <38>

PWRBTN_OUT# <26>
EC_SMC_2 <7>
EC_SMD_2 <7>
FANSPEED1 <7>
PME_EC# <30,32,34,41,44>
EC_THERM# <26>
FANSPEED2 <7>
WL_ON <34,39>

ACIN <26,46>
RING# <41>
SLP_S3# <26>

ON/OFF# <39>
SLP_S5# <26>

PCI_CLKRUN# <25,30,32,34,38>

FRD# <41>
FWR# <41>

SELIO# <41>
SCROLLED# <37>

NUMLED# <37>
CAPSLED# <37>
CD_PLAY <29,35>

FSTCHG <48>

C301

1 2

0.01U_0402_16V7K

EEPROM/BATTERY

THERMAL/DOCKING

ADB[0..7]
KBA[0..19]

D

ECAGND

R250

1 2

1

10K_0402_5%
C300

0.22U_0603_16V7K

2

BEEP# <35>

ADB[0..7] <41>
KBA[0..19] <41>

BADDR1-0

*

Title

Size Docu ment Number Re v

Date: Sheet

Index
0 0
0 1
1 0

(HCFGBAH, HCFGBAL)

1 1

ADP_I <48,52>

SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the
signals for clip-on ISE use

Analog Board ID definition,
Please see page 3.

星期三 七月

2E
4E

Ra

Rb

KBA1

KBA2

KBA3

KBA5

I/O Address

*

(ENV1)

(BADDR0)

(BADDR1)

(SHBM)

+3VALW

R261
100K_0402_5%

1 2

R266

8.2K_0402_5%

1 2

Reserved

IRE
OBD
DEV
PROG

Data

2F
4F

(HCFGBAH, HCFGBAL)+1

ENV1

ENV0

0

0

1

0
1

0

1

1

+3VALW

R272

1 2

10K_0402_5%

R273

1 2

@10K_0402_5%

R275

1 2

10K_0402_5%

1 2

R277 10K_0402_5%

AD_BID0

1

C309

0.1U_0402_16V4Z

2

EC DEBUG port

JP7

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

KSO16
KSO17

MAIL_LED#

+5VALW

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

40 61,

E

TRIS

0
0
0
0

0E

of

12

R306
10K_0402_5%

13

D

S

+3VALW

2

G

Q25
2N7002_SOT23

RIA0 <38>

KBA2
SELIO#

+3VALW

+3VALW

1

A

2

B

1 2

20K_0402_5%

14

P

G

7

R739

OUTPUT

+5VALW

C782 0.1U_0402_16V4Z

1 2

20

3

11

1

D0
D14Q1

VCC
D27Q2
D38Q3
D413Q4
D514Q5
D617Q6
D718Q7

CP
MR

GND

10

U46

2

Q0

5
6
9
12
15
16
19

SN74HCT273PW_TSSOP20

EC_MUTEO <36>
BT_DETACH <37>
BT_ON# <37,39>
PMLED_0# <39>
PMLED_1# <39>
BATLED_0# <39>
BATLED_1# <39>

ADB0
ADB1
ADB2
ADB3
ADB4

ADB6
ADB7

3

O

LARST#

U16ASN74LVC32APWLE_TSSOP14

C733

1 2

1U_0603_10V4Z

ADB[0..7]<40>

KBA[0..19]<40>

ADB[0 ..7 ]
KBA[0..19]

100K_0804_8P4R_5%

USER_BTN0#<37>
USER_BTN1#<37>

EXTID0<29>
EXTID1<29>

BT/WL_ON/OFF#<37,39>

CONA#<43>
BT_WAKE_UP<37>

SELIO#<40>

RP113

KBA1
SELIO#

+3VALW

12

R262
100K_0402_5%

1 8

2 7

3 6

4 5

BT/WL_ON/OFF#
CONA#

BT_WAKE_UP

1 2

R249 100K_0402_5%

+3VALW

14

U16B

4

P

A

6

O

5

B

G

SN74LVC32APWLE_TSSOP14

7

1A121Y1
1A241Y2
1A361Y3
1A481Y4
2A1112Y1
2A2132Y2
2A3152Y3
2A4172Y4

1

1G

19

2G

INPUT

+3VALW

1 2

20

U20

18
16

VCC

14
12
9
7
5
3

GND

SN74LVC244APWLE_TSSOP20

10

C279

0.1U_0402_16V4Z

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6 ADB5
ADB7

CONA#
MDM_PME#
WLAN_PME#
BT/WL_ON/OFF#

PCM_RI#<30>

MODEM_RI#<34>

D31

RING#<40>

D5

RP18
1 8
2 7
3 6
4 5

100K_0804_8P4R_5%

12

R263
10K_0402_5%

RB751V_SOD323

RB751V_SOD323

+3VALW+3VALW

21

21

VCC_FLASH

U18

KBA18

1

A18

KBA16

2

A16

KBA15

3

A15

KBA12

4

A12

KBA7

5

A7

KBA6

6

A6

KBA5

7

A5

KBA4

8

A4

KBA3

9

A3

KBA2

10

A2

KBA1

11

A1

KBA0

12

A0

ADB0

13

DQ0

ADB1

14

DQ1

ADB2

15

DQ2

16

VSS

512K8-90_PLCC32

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#<40>

FRD#<40>

FSEL#
FRD#
FWE#

U17

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

@SST39VF080-70_TSOP40

VDD
WE#

VCC0
VCC1

GND0
GND1

A17
A14
A13

A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

RP#

NC0
NC1

32

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

RESET#

C724

4.7U_0805_10V4Z

1 2
R725
@100K_0402_5%

31
30
29
28
27

A8

26

A9

25
24
23
22
21
20
19
18
17

31
30

25

D0

26

D1

27

D2

28

D3

32

D4

33

D5

34

D6

35

D7

10
11

NC

12
29
38

23
39

1

2

+3VALW

R724

1 2

2

C725

0.1U_0402_16V4Z

1

1

C776
@0.1U_0402_16V4Z

2

+3VALW

0_0603_5%

+3VALW

FWE#

SN74LVC32APWLE_TSSOP14

U16C

8

+3VALW

O

R228

100K_0402_5%

14

9

P

A

10

B

G

7

+3VALW +5VS

12

1 3

D

Q19 2N7002_SOT23

12

R227
100K_0402_5%

2

G

S

+3V

12

R1021
10K_0402_5%

FWR# <40>

EC_FLASH# <26>

ONBD_LAN_PME#<30,32,34,40,44>

USB20_PME#<30,32,34,40,44>

WLAN_PME#<30,32,34,40,44>

C278

0.1U_0402_16V4Z

EC_SMC_1<40,47>
EC_SMD_1<40,47>

PCM_PME#<30,32,34,40,44>
MINI_PME#<30,32,34,40,44>

LAN_PME#<30,32,34,40,44>

MDM_PME#<30,32,34,40,44>

+3VALW

1

2

12

U19

8

VCC

7

WC

6

SCL

5

SDA

AT24C164-10SC_SO8
R226
100K_0402_5%

+3VALW

GND

12

R248

4.7K_0402_5%

1

A0

2

A1

3

A2

4

+3VALW

12

R264
100K_0402_5%

12

R265
100K_0402_5%

PME_EC# <30,32,34,40,44>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

of

41 61,

0E

+CPU_CORE

VCORE_PWRGD<53>

R745

+2.5VS

@0.047U_0603_16V7K

R229

1 2

@10K_0402_5%

@0.047U_0603_16V7K

1 2

@10K_0402_5%

C281

R253 0_0402_5%

1 2

@4.7K_0603_5%

1

C299

2

1

C

2

B

E

1

2

3

R255

+5VS

12

R746

1

C

Q20

2

B

@HMBT2222A_SOT23

E

3

Q24
@HMBT2222A_SOT23

+3VS

12

2

G

47K_0603_5%

R1036

1 2

10K_0402_5%

0.1U_0402_16V4Z

13

D

Q67
@2N7002_SOT23

S

C821

+3VALW

14

P

1

O2I

G

1

SN74LVC14APWLE_TSSOP14

7

2

U45A

R1035

2

G

+3VALW

12

13

D

S

1K_0402_5%

Q68
2N7002_SOT23

R252

1 2

330K_0402_5%

VTT_PWRGD <23,26>

+3VALW +3VALW +3VALW

5

1

C307

2

0.1U_0402_16V4Z

14

P

O6I

G

U45C

SN74LVC14APWLE_TSSOP14

7

2N7002_SOT23

14

P

9

O8I

G

SN74LVC14APWLE_TSSOP14

7

+2.5VS

12

13

D

2

G

Q66

S

U45D

R744
1K_0402_5%

R738

1 2

300K_0603_5%

0.47U_0603_16V7K

12

R743
47K_0402_5%

C732

14

P

11

O10I

G

1

SN74LVC14APWLE_TSSOP14

7

2

NB_PWRGD <8>

U45E

+3VALW

14

P

13

O12I

G

SN74LVC14APWLE_TSSOP14

7

U45F

R737

1 2

47_0603_5%

12

SB_PWRGD <26>

R740
10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

of

42 61,

0E

A

D

S

LINE_OUT_PLUG#

D

S

Q38
SPR@2N7002_SOT23

13

D

DOCK_MIC_PLUG

2

G

S

VIN

1 3

Q41
SPR@2N7002_SOT23

G

2

R376 SPR@100K_0402_5%

2

G

DQLINE_OUT_L

1 3

D

S

Q40
SPR@2N7002_SOT23

12

L31
SPR@KC FBM-L18-453215-900LMA90T_1812

1

C426
SPR@1000P_0402_50V7K

2

INTSPK_R+<36,39>

13

LINE_OUT_PLUG<36,39>

1 1

2 2

SPR@0.1U_0402_16V4Z

C432

SPR@2N7002_SOT23

INTSPK_L+<36,39>

INTMICOFF#<36>

+5VS

1

2

2

G

Q39

1

C431
SPR@0.1U_0402_16V4Z

2

B

+

1 2

C21 SPR@150U_D2_6.3VM

12

+

1 2

C22 SPR@150U_D2_6.3VM

R375
SPR@1M_0402_5%

1 2

DLINE_OUT_RDQLINE_OUT_R

+12VALW

DLINE_OUT_L

DOCKVIN

1

C433
SPR@1000P_0402_50V7K

2

C

KBD_CLK<40>

KBD_DATA<40>

PS2_CLK<40>

RI1#<38>

LPTSTB#<38>

DOCK_OUT_PLUG<36>

CRT_VSYNCRFL<24>

DOCK_DDCCL<24>
DOCK_DDCDA<24>

1 2
1 2

PS2_DATA<40>

DSR1#<38>

RTS1#<38>
CTS1#<38>

LPTSTB#
LPD0

LPD1
LPD2
LPD3
LPD4

LPD5
LPD6
LPD7

DLINE_IN_L<35>

DLINE_IN_R<35>

USB_SPR1­USB_SPR1+

M_SEN#<24,40>

TV_LUMA<11,16,24>

DKMOD_TIP DKMOD_RING

+5VS

USB20P1-<26,37> USB20P0+ <26,37>

USB20P1+<26,37>

LINK_10_100_1000#<32>

1

+

C808
SPR@100U_D2_10VM

2

L37 SPR@0_0402_5%
L38 SPR@0_0402_5%

ACTIVITY#<32>

GNDA

12
12

SPR_UVCCB

R20 SPR@330_0402_5%

+3VALW

R19 SPR@220_0402_5%

+3VALW

D

JP24

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56

52 2

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6

CONA# <41>
DCD1# <38>
RXD1 <38>
TXD1 <38>

LPTAFD#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTACK#
LPTBUSY
LPTSLCT
LPTPE

DLINE_OUT_L
DLINE_OUT_R

DOCK_MIC_PLUG

USB_SPR0-

R979 SPR@0_0402_5%

USB_SPR0+

1 2

R980 SPR@0_0402_5%

1 2

CRT_HSYNCRFL <24>
CRT_B <11,16,24>

CRT_G <11,16,24>
CRT_R <11,16,24>
TV_CRMA <11,16,24>

E

SPR 204 PIN

DOCKVIN

DTR1# <38>
LPTAFD# <38>
LPTERR# <38>
LPTINIT# <38>
LPTSLCTIN# <38>

LPTACK# <38>
LPTBUSY <38>
LPTSLCT <38>
LPTPE <38>

GNDA

DOCK_MIC <36>

12
12
12
12

USB20P0- <26,37>

SPR_UVCCA

R1037 SPR@0_0402_5%
R1038 SPR@0_0402_5%
R1039 SPR@0_0402_5%
R1040 SPR@0_0402_5%

MDO1+ <32>
MDO1- <32>
MDO0+ <32>
MDO0- <32>

+5VALW

C829

1 2

SPR@0.1U_0402_16V4Z

1

1

1

H5
HOLEC

1

H34
HOLEE

1

CF3

CF11

CF19

1

H3
HOLEB

H37
HOLEL

1

1

A

1

1

1

FM6

H9
HOLEC

H16
HOLEE

1

1

CF4

CF12

CF20

H28
HOLEB

H38
HOLEL

SYSON#

1

1

1

1

1

H14
HOLEC

H27
HOLEE

1

SYSON#<37,45> INT_OVCUR#1 <26>

CF1

1

1

1

1

H30
HOLEA

1

H12
HOLEC

1

H36
HOLEE

1

H22
HOLEJ

1

CF9

CF17

FM2

1

1

1

1

H32
HOLEA

1

H4
HOLEC

1

H35
HOLEE

1

H31
HOLEK

CF2

CF10

CF18

FM5

1

3 3

4 4

FM1

1

1

CF5

CF13

CF21

H19
HOLEM

U50

1

GND

2

IN

3

EN1#

4

EN2#

SPR@TPS2042ADR_SO8

CF6

1

1

CF14

1

1

CF22

1

1

FM3

1

1

H1

H2

HOLED

HOLED

1

1

H15

H8

HOLEC

HOLEC

1

1

H26

H23

HOLEE

HOLEE

1

1

1

CF7

CF15

CF23

FM4

OC1#
OUT1
OUT2
OC2#

1

1

1

H20
HOLEE

CF8

CF16

CF24

H21
HOLEF

1

1

8
7
6
5

H17
HOLEC

H13
HOLEE

1

1

INT_OVCUR#0

INT_OVCUR#1

H29
HOLEG

1

H6
HOLEC

1

H10
HOLEE

1

H33
HOLEH

1

H7
HOLEC

1

INT_OVCUR#0 <26>
SPR_UVCCA
SPR_UVCCB

H24
HOLEI

1

H11
HOLEC

1

+5V_PRN

1

1

C434

4.7U_0805_10V4Z

B

C427

0.1U_0402_16V4Z

2

2

LPTAFD#

LPTINIT#
LPTSLCTIN#

LPD[0..7]<38>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VS

1SS355_SOD323

LPTSTB#

R360 33_0402_5%

1 2

R374 33_0402_5%

1 2

R373 33_0402_5%

1 2

R372 33_0402_5%

1 2

LPD[0..7]

C

+5V_PRN

D18

w=10mils

12

AFD/3M#
FD0
LPTERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

12

Parallel Port

R359

2.7K_0402_5%
C422

PWRPRN

1 2

47P_0402_50V8J

1

w=10mils

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

JP1

SUYIN_070536FR025S204AU

101

SPR@FCI_10007221-001

FD3
FD1

FD0

+5V_PRN

SLCTIN#
PRNINIT#
LPTERR#
AFD/3M#

+5V_PRN

D

LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4

RP23
1
2
3
4
5

2.7K_1206_10P8R_5%

RP22
1
2
3
4
5

2.7K_1206_10P8R_5%
RP24

1
2
3
4
5
6
7
8 9

68_1206_16P8R_5%

Title

Size Docu ment Number Re v

Date: Sheet

+5V_PRN

10

FD7FD2

9

FD6

8

FD5

7

FD4

6

+5V_PRN

10

LPTSLCT

9

LPTPE

8

LPTBUSY

7

LPTACK#

6

FD3

16

FD2

15

FD1

14

FD0

13

FD7

12

FD6

11

FD5

10

FD4

220P_1206_8P4C_50V8K

220P_1206_8P4C_50V8K

220P_1206_8P4C_50V8K

220P_1206_8P4C_50V8K

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

AFD/3M#
LPTERR#
PRNINIT#
SLCTIN#

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

FD0
FD1
FD2
FD3

FD4
FD5
FD6
FD7

CP10

2
3
4 5

CP7

2
3
4 5

CP9

2
3
4 5

CP8

2
3
4 5

E

81
7
6

81
7
6

81
7
6

81
7
6

43 61,

0E

of

10

9

8

7

6

5

4

3

2

1

+3VS +2.5VS

H H

10

U47

PCI_AD [0 ..3 1 ]<25,28,30,32,33,34>

G G

CLK_PCI_USB20

12

F F

E E

PCI_AD27

D D

R981
10_0402_5%

1

C784
15P_0402_50V8D

2

PCI_CBE#3<25,30,32,33,34>
PCI_CBE#2<25,30,32,33,34>
PCI_CBE#1<25,30,32,33,34>
PCI_CBE#0<25,30,32,33,34>

CLK_PCI_USB20<25>

PCI_GNT#4<25,34>
PCI_REQ#4<25,34>

PCI_FRAME#<25,30,32,33,34>

PCI_IRDY#<25,30,32,33,34>

PCI_TRDY#<25,30,32,33,34>

PCI_DEVSEL#<25,30,32,33,34>

PCI_STOP#<25,30,32,33,34>

PCI_PIRQA#<10,16,25,30,33>
PCI_PIRQB#<25,30>
PCI_PIRQC#<25,34>

PCI_RST#<16,25,29,30,32,33,34,38>

USB20_PME#<30,32,34,40,41>

LPC_SMI#<26>

CLK_PCI_USB20

R991 USB20@100_0402_5%

PCI_PAR<25,30,32,33,34>

1 2

R994

1 2

USB20@0_0402_5%

R997

1 2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

0_0402_5%

USB20@VT6202

VCC33

116

AD31

117

AD30

118

AD29

121

AD28

122

AD27

123

AD26

124

AD25

125

AD24

126

AD23

1

AD22

2

AD21

7

AD20

8

AD19

11

AD18

12

AD17

13

AD16

14

AD15

15

AD14

16

AD13

29

AD12

30

AD11

31

AD10

32

AD9

37

AD8

38

AD7

39

AD6

40

AD5

42

AD4

45

AD3

46

AD2

47

AD1

48

AD0

3

-CBE3

19

-CBE2

28

-CBE1

41

-CBE0

109

PCICLK

112

-GNT

113

-REQ

6

IDSEL

20

-FRAME

21

-IRDY

22

-TRDY

23

-DEVSEL

24

-STOP

27

PAR

105

-INTA

106

-INTB

107

-INTC

111

PCIRST

67

-PME

64

-SMI
GND

5

VCC3318VCC3326VCC3334VCC3344VCC3352VCC3362VCC33

GND

GND17GND25GND33GND43GND51GND61GND

GND36GND54GND

9

101

110

120

VCC33

C C

+3V_USB20

1

C783
USB20@0.1U_0402_16V4Z

2

128

115

70

GND

108

VCC254VCC2535VCC2553VCC25

GND

119

114

-USBOC0

-USBOC1
VCCUSB

VCCUSB
VCCUSB
VCCUSB

GNDUSB
GNDUSB
GNDUSB
GNDUSB

VCCPLLA

VCCOSC

GNDPLLA

GNDOSC

GNDPLL

WAKEUP_EN

ATPGEN

TESTMODE

GND

GNDSUS

69

127

VSUS

USBP1-

USBP1+

USBP2-

USBP2+

USBP3-

USBP3+

USBP4-

USBP4+

REXT

VCCPLL

EECS
EESK

EEDO

EEDI

TEST1
TEST2
TEST3
TEST4

XOUT

NC
NC
NC
NC
NC
NC

XIN

USB20EP1-

85

USB20EP1+

86

USB20EP2-

81

USB20EP2+

82

USB20EP3-

77

USB20EP3+

78

USB20EP4-

73

USB20EP4+

74

USBOC#0

71

USBOC#1

68
84

80
76
72

R982

1 2

88

USB20@2.2K_0603_1%
87
83
79
75

89
96
91

90
93
92

R984 USB20@4.7K_0402_5%

60
63
97
103
104
102

98
49

50
55
56

65
66
57
58
59
99

94
95

USB20@20P_0603_50V8J

1 2

R985 USB20@4.7K_0402_5%

1 2

R986 USB20@4.7K_0402_5%

1 2

R987 USB20@4.7K_0402_5%

1 2

R988 USB20@4.7K_0402_5%

1 2

R990 USB20@4.7K_0402_5%

1 2

USB20ATPGEN
USB20TESTMODE
USB20TEST1
USB20TEST2

USB20XIN
USB20XOUT

USB20@24MHz

2

C785

1

R983
USB20@3.92K_0603_0.5%

+2.5VS_USB20

R995 USB20@4.7K_0402_5%

1 2

R996 USB20@4.7K_0402_5%

1 2

X4

USB20@20P_0603_50V8J

USB20EP1- <37>
USB20EP1+ <37>

USB20EP2- <37>
USB20EP2+ <37>

USB20EP3- <37>
USB20EP3+ <37>

USB20EP4- <37>
USB20EP4+ <37>

1 2

1 2

L58
USB20@BLM21A601SPT_0805

+3VS

2

C786

1

VCC33

VCC33

100

+3V_USB20

RP111

1 8
2 7
3 6
4 5

USB20@100K_0804_8P4R_5%

+3V_USB20

+2.5VS

R992 @4.7K_0402_5%

R993 USB20@4.7K_0402_5%

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3

L56

USB20@BLM21A601SPT_0805

1 2
1 2

L57 @BLM21A601SPT_0805

R989
USB20@4.7K_0402_5%

1 2

1 2

1 2

USB20TEST1
USB20TEST2
USB20ATPGENUSB20ATPGEN
USB20TESTMODE

+3V
+3VS

+3V_USB20

RP112
4 5
3 6
2 7
1 8

USB20@4.7K_0804_8P4R_5%

USBOC#0

USB20@SN74AHCT1G08DCKR_SC70

USBOC#1

USB20@SN74AHCT1G08DCKR_SC70

+3V

5

U48

4

U49

4

1

P

A

O

B

G

3

+3V

5

P

A

O

B

G

3

2

1
2

OVCUR#0 <26,37>
OVCUR#1 <26,37>

OVCUR#2 <26,37>
OVCUR#3 <25,37>

+3VS +2.5VS

B B

USB20@0.1U_0402_16V4Z

1

C787

2

USB20@0.01U_0402_16V7K

1

C788

2

USB20@0.01U_0402_16V7K

USB20@0.1U_0402_16V4Z

1

C789

2

1

2

1

C790

2

USB20@0.01U_0402_16V7K

USB20@0.1U_0402_16V4Z

1

C791

C792

2

USB20@0.01U_0402_16V7K

USB20@0.1U_0402_16V4Z

1

C793

2

1

C794

2

USB20@0.01U_0402_16V7K

USB20@0.1U_0402_16V4Z

1

2

C795

1

2

USB20@0.1U_0402_16V4Z

1

C796

C797

2

USB20@0.01U_0402_16V7K

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10

9

8

7

6

1

C798

2

+3V_USB20

USB20@0.1U_0402_16V4Z

1

C799

2

USB20@0.1U_0402_16V4Z

5

1

C800

2

USB20@0.1U_0402_16V4Z

USB20@0.1U_0402_16V4Z

1

C801

2

4

1

C802

2

+2.5VS_USB20

USB20@0.1U_0402_16V4Z

1

C803

2

USB20@0.1U_0402_16V4Z

3

1

2

1

C804

C805
USB20@0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Title

SCHEM AT IC , M/ B LA- 1861

Size Docu ment Number Re v

401257

Custom

星期三 七月

Date: Sheet

30, 2003

2

0E

of

44 61,

1

A

B

C

D

E

+12VALW TO +12VS Transfer

+3VALW to +3VS Transfer+2.5VALW t o + 2.5V Transfer

1

2

SYSON<40>

RUNON

SYSON#<37,43>

+12VALW

2

G

12

R722
100K_0402_5%

12

R721
51K_0402_5%

13

D

Q63
2N7002_SOT23

S

SYSON#

SYSON

2

G

+2.5VALW

+12VALW

12

2

G

R201
100K_0402_5%

13

D

Q17
2N7002_SOT23

S

5VON

1 1

SYSON#

1

2

R199 47K_0402_5%

1 2

8
7
6

C229

5

10U_0805_10V4Z

U14

D
D
D
D

SI4800DY_SO8

1

2

+3VALW to +3V Transfer

U42

8

D

7

D

6

1

2 2

5VON

2

R727 47_0402_5%

1 2

C728

5

10U_0805_10V4Z

D
D

SI4800DY_SO8

1

2

+2.5V

1

S

2

S

3

S

4

G

0.1U_0402_16V4Z

C226

0.1U_0402_16V4Z

+3V+3VALW

1

S

2

S

3

S

4

G

0.1U_0402_16V4Z

C729

0.01U_0402_16V7K

+12VALW

2

R570

G

12

13

D

S

RUNON

C225

1

C224

2

10U_0805_10V4Z

100K_0402_5%

SUSP

1

2

+5VALW to +5VS Transfer

C726

1

C723

2

10U_0805_10V4Z

1

2

+2.5V to +2 . 5V S Tran sfer

RUNON

+3VALW

U37

8

D

7

D

6

1

2

R567 300K_0402_5%

1 2

Q57
2N7002_SOT23

+5VALW

1

C189

2

10U_0805_10V4Z

RUNON

+2.5VALW

1

C170

2

10U_0805_10V4Z
R167 150K_0402_5%

1 2

5

C620
10U_0805_10V4Z

U13

8

D

7

D

6

D

5

D

SI4800DY_SO8

U12

8

D

7

D

6

D

5

D

SI4800DY_SO8

D
D

SI4800DY_SO8

1

2

S
S
S
G

S
S
S
G

1

2

1

S

2

S

3

S

4

G

C627

0.01U_0402_16V7K

+5VS

1
2
3
4

1

C218

0.1U_0402_16V4Z

2

+2.5VS

1
2
3
4

1

2

0.1U_0402_16V4Z

C185

0.1U_0402_16V4Z

+3VS

1

C624

2

0.1U_0402_16V4Z

1

2

C188

1

C615
10U_0805_10V4Z

2

C217
10U_0805_10V4Z

1

C184
10U_0805_10V4Z

2

C721

0.1U_0402_16V4Z

+5VALW

2

G

12

R251
100K_0402_5%

13

D

Q23
2N7002_SOT23

S

+12VALW

3

S

D

1

1

C722
1U_0805_16V7K

2

1

C712
1U_0805_16V7K

2

Q62
NDS352P_SOT23

+12VS

Discharge circuit

3 3

+2.5V

12

R196
470_0402_5%

13

D

Q16

2

2N7002_SOT23

G

S

+1.25VS

12

R246
470_0402_5%

13

D

4 4

SUSP

Q21

2

G

2N7002_SOT23

S

A

+3VS +5VS

12

R197
470_0402_5%

13

SUSP

SUSP

D

Q18

2

2N7002_SOT23

G

S

+1.8VS

12

R156
470_0402_5%

13

D

Q8

2

G

2N7002_SOT23

S

SUSP

12

R184
470_0402_5%

13

D

Q13

2

2N7002_SOT23

G

S

+2.5VS

12

R140
470_0402_5%

13

D

Q7

2

2N7002_SOT23

G

S

B

+12VS

12

R683
470_0805_5%

13

D

SUSPSYSON# SUSP

2

G

SYSON#

S

2

Q60
2N7002_SOT23

+3V

12

13

D

G

S

R1042
470_0402_5%

Q69
2N7002_SOT23

VR_ON<40,53>

SUSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R137

100K_0402_5%

+1.5VS

2

G

C

2

G

12

13

D

S

+5VALW

1 2

13

R1043
470_0402_5%

Q70
2N7002_SOT23

D

S

+CPU_CORE

2

G

Q9
2N7002_SOT23

SUSP

12

R138
470_0402_5%

13

D

S

+VGA_CORE

2

G

Q10
2N7002_SOT23

12

R1044
470_0402_5%

13

D

S

Q71
2N7002_SOT23

+5VALW

12

R245
100K_0402_5%

SUSP

13

D

Q22

SUSP#<38,40,49>

D

12

Title

Size Docu ment Number Re v

Date: Sheet

2

G

2N7002_SOT23

R1009
10K_0402_5%

S

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

E

0E

of

45 61,

A

PCN1

1

4

1 1

3

SINGA_2DC-S107B200

1

23

2

PD1

12

EC10QS04

12

PC1

1000P_0402_50V7K

PL1

1 2

C8B BPH 853025_2P

12

PC2

100P_0402_50V8J

B

12

PC3
1000P_0402_50V7K

VIN

12

PC4
100P_0402_50V8J

PC5

1000P_0402_50V7K

C

PD2

VS

12

12

PR2

5.6K_0402_5%

12

PR7
10K_0402_5%

PR4

1 2

1K_0402_5%

PACIN

VIN

12

PR3

84.5K_0402_1%
PR5

1 2

160K_0402_5%

PR6
24K_0402_1%

12

PC6

0.1U_0402_16V4Z

12

12

PR1

1 2

1M_0402_1%

VS

8

3

+

2

-

4

PR8

10K_0402_5%

PU1A

P

1

O

G

LM393M_SO8

12

RTCVREF

3.3V

RLZ4.3B_LL34

D

ACIN <26,40>

PACIN <48,49>

Vin Detector

VIN

PD3

PD4
RB751V

CHGRTCP

EC_PWR_ON#<39>

PR178

1 2

200_0402_5%

PAD-OPEN 4x4m

1 2

PAD-OPEN 4x4m

1 2

PJP4

1 2

PAD-OPEN 3x3m

2 1

PAD-OPEN 2x2m

PJP7

2 1

PAD-OPEN 3x3m

2 1

PAD-OPEN 2x2m
PJP10

1 2

PAD-OPEN 3x3m

BATT+

PJP1

PJP2

PJP6

PJP9

2 2

CHGRTC

3 3

+2.5VALWP

+1.25VSP

+VCCVIDP

4 4

+1.5VSP

+12VALWP

+1.8VSP

PR177

1 2

100_0805_5%

2 1

PR12

100K_0402_5%

PR14

1 2

22K_0402_5%

PR19

1 2

200_0402_5%

+2.5VALW

+1.25VS

+VCCVID

+1.5VS

+12VALW

+1.8VS

A

N1

12

12

PC7

0.22U_1206_25V7M

RTCVREF

12

3.3V

3

PC11

10U_0805_10V4Z

PU2
S-81233SGUP-T1_SOT89

3

1

1

(12A,480mils ,Via NO.=24)

(2A,80mils ,Via NO.= 4)

(150mA,40mils ,Via NO.= 2)

(6A,240mils ,Via NO.= 12)

(120mA,20mils ,Via NO.= 1)

(3A,120mils ,Via NO.= 6)

2

2

1 2
12

13

PQ1
TP0610T_SOT23

12

12

2

12

1N4148_SOD80

PR10
33_1206_5%

PC8

0.1U_0805_25V7K

PR18
200_0805_5%

N2
PC9
1U_0805_25V4Z

VGA_CORE_PWR

VS

MAINPWON<7,47,49>

PJP3

1 2

PAD-OPEN 4x4m

ACON<48>

2 1

+5VALWP

PD8
RLZ16B_LL34

(6A,240mils ,Via NO.= 12)

PJP5

+3VALWP

(6A,240mils ,Via NO.= 12)

1 2

PAD-OPEN 4x4m

PJP8

1 2

PAD-OPEN 4x4m

(6A,240mils ,Via NO.= 12)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VALW

+3VALW

+VGA_CORE

VS

PD7

2
3

RB715F_SOT323

PD5

12

1N4148_SOD80

PR15

VL

1

1 2

PON

PD9

2 1

10K_0402_5%

RLZ6.2C_LL34@

Precharge detector

15.34 15.90 16.48

13.13 13.71 14.20

N3

PR9

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

6.0V

1000P_0402_50V7K

C

PR11

PR13

7

12

PC12

O

8

LM393M_SO8

5

P

+

6

-

G

PU1B

4

0.1U_0402_16V4Z

PR16

12

1M_0402_1%

12

PC13

PR21

10K_0402_5%

1 2

RTCVREF

3.3V

PQ2

2N7002_SOT23

12

13

D

S

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

PR22
215K_0402_1%

2

G

期三 七月

High 17.58
Low 14.11

B+

12

PR17
499K_0402_1%

12

PR20
499K_0402_1%

47K_0402_5%

13

100K

100K

PR23

PQ3
DTC115EKA_SOT23

2

12

12

PC10

1000P_0402_50V7K

PACIN

+5VALWP

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

D

0E

of

46 61¬P , 30, 2003

A

CHANGE CONNECTER

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1 1

2 2

PCN2

1
2
3
4
5
6
7
8
9

SUYIN_250145MR009GX14ZR

ALI/NIMH#

AB/I

TS_A
EC_SMDA
EC_SMCA

PR28

100_0402_5%

12

PR29
100_0402_5%

VMB

PL2

PR25

12

1K_0402_5%

12

12

PR31

1K_0402_5%

1 2

12

PR36
1K_0402_5%

25.5K_0402_1%

1 2

PR34

PD12

3

1

PD10

BAS40-04_SOT23@

PR26
47K_0402_5%

3

2

+3VALWP

+3VALWP

1 2

C8B BPH 853025_2P

12

PC15
1000P_0402_50V7K

ALI/MH# <40>

12

PC16

0.01U_0402_50V7K

BATT+

0.22U_0805_16V7K

PC17

12

VL VS

12

PH1

10KB_0603_1%_TH11-3H103FT

PR30

1 2

16.9K_0402_1%

12

PR32

3.32K_0402_1%

1000P_0402_50V7K

TM_REF1

12

PC18

12

PC14

0.1U_0603_25V4Z

1 2

8

PU4A

47K_0402_1%

3

P

+

2

-

G

LM393M_SO8

4

PR33

100K_0402_1%

12

PR35

100K_0402_1%

O

12

PR27

VL

PR24
47K_0402_1%

1 2

1

VL

PD11

12

1SS355_SOD323

100K

2

100K

13

PQ4

DTC115EKA_SOT23

MAINPWON <7,46,49>

1

2

BAS40-04_SOT23@

1

PD13

BAS40-04_SOT23@

3

3 3

+5VALWP

1

PD14

2

2

BAS40-04_SOT23@

3

BATT_TEMPA <40>

EC_SMD_1 <40,41>
EC_SMC_1 <40,41>

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 45 degree C

12

PH2
10KB_0603_1%_TH11-3H103FT

PC19

0.22U_0805_16V7K

12

3.48K_0402_1%

PR41

PR39

1 2

14.7K_0603_1%

12

TM_REF2

12

PC20

1000P_0402_50V7K

12

PR42
100K_0402_1%

5

+

6

-

1 2

47K_0402_1%

PR38

8

PU4B

P

7

O

G

LM393M_SO8

4

PR40

100K_0402_1%

VLVL

12

PR37
47K_0402_1%

1 2

VL

PD15

12

1SS355_SOD323

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

D

0E

of

47 61¬P , 30, 2003

A

B

C

D

1 2

4700P_0402_25V8K

1 2

1000P_0402_50V7K

Iadp=0~4.2A

PR43

12

0.015_2512_1%

PR50

12

100K_0402_5%

PC27

PR54

1 2

10K_0402_5%

PC30

PR55

1 2

1K_0402_5%

PR59

12

10K_0402_5%

1

2

3

4

5

6

7

8

9

10

11

12

PR63

150K_0603_0.1%

PU5

-INC2

+INC2

OUTC2

GND

+INE2

CS

-INE2

VCC(o)

FB2

OUT

VREF

VH

FB1

VCC

-INE1

RT

+INE1

-INE3

OUTC1

FB3

OUTD

CTL

-INC1

+INC1

MB3887_SSOP24

12

PL3

1 2

HCB4532K-800T90_1812

24

23

CS

22

21

20

PC28

19

1 2

0.1U_0603_25V4Z

PR56

1 2

68K_0402_5%

PR60

1 2

47K_0402_5%

ACON

1500P_0402_50V7K

18

17

16

15

14

13

12

PC21

4.7U_1210_25V6K

12

PR49
0_0402_5%

PC24 0.022U_0402_16V7K

1 2

PC25

1 2

0.1U_0805_25V7K

PC31

1 2

0.1U_0805_25V7K

PC32

1 2

4.2V

12

PC22

4.7U_1210_25V6K

PR64

300K_0603_0.1%

12

PC23

4.7U_1210_25V6K

N18

12

B++

36

241

578

LXCHRG

1 2

12

PD17

RB051L-40_SOD106

ACOFF#

PQ8
SI4835DY_SO8

13

100K

CC=0.5~2.7A
CV=12.6V(9 CELLS LI-ION)

PL4

22UH_SPC-1204P-220_2.9A_20%

PR58

1 2

0.02_2512_1%

PQ7

1

S

2

S

3

S

4

G

SI4825DY_SO8

PR46

1 2

10K_0402_5%

PQ9
DTC115EKA_SOT23

100K

2

PC34

4.7U_1210_25V6K

D
D
D
D

12

4.7U_1210_25V6K

8
7
6
5

PR47

1 2

47K_0402_5%

PC35

ACOFF <40>

12

PC36

VIN

12

4.7U_1210_25V6K

BATT+

P2

PQ5

S

D

S

D

S

D

G

D

SI4825DY_SO8

1
2
3
4

12

VIN

PR44

10K_0402_5%

12

1 1

8
7
6
5

12

PD16

ACOFF#

1 2

1SS355_SOD323

PR51

PACIN

PACIN<46,49>

ACON<46>

2 2

1 2

3K_0402_5%

ACON

IREF=1.31*Icharge

13

D

2

G

S

PQ6

1
2
3
4

PR45

SI4825DY_SO8

200K_0402_1%

PR48

150K_0402_1%

PQ10
2N7002_SOT23

PC26

0.1U_0402_16V4Z

8

S

D

7

S

D

6

S

D

5

G

D

ADP_I<40,52>

12

12

PR53
10K_0402_1%

12

IREF=0.73~3.3V

PR57

IREF<40>

+3VALWP

12

PR62
47K_0402_5%

13

100K

FSTCHG<40>

3 3

2

100K

PQ12

DTC115EKA_SOT23

1 2

205K_0603_1%

CS

13

PQ11
DTC115EKA_SOT23

100K

2

100K

PR61

100K_0402_1%

P3 B+

12

PR52

29.4K_0402_1%

PC29

0.1U_0402_16V4Z

12

12

PC33

0.1U_0402_16V4Z

VMB

12

PR65

PR68

340K_0603_1%

12

PR66
499K_0402_1%

12

12

PC38

0.01U_0402_50V7K

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

D

0E

of

48 61¬P , 30, 2003

OVP voltage : LI

4S3P : 18V--> BATT_OVP= 2.0V
3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V

+5VALWP

(BAT_OVP=0.1111 *VMB)

8

PU6A

3

P

+

1

BATT_OVP<40>

4 4

12

@

A

12

PC37

0.1U_0402_16V4Z

PR67

2.2K_0402_5%

0

2

-

G

LM358A_SO8

4

105K_0603_0.5%

5

B+++

PL5

1 2

B+

HCB4532K-800T90_1812

D D

C C

PC52

150U_D2E_6.3VM_R18@

PC42

4.7U_1210_25V6K

10U_SPC-1204P-100_4.5A_20%

+3VALWP

1

1

+

2

2

150U_D2E_6.3VM_R18

12

0.012_2512_1%

+

PC53

12

PC43

4.7U_1210_25V6K

PL6

12

PR73

2 1

10K_0402_1%

12

PD21

EP10QY03

PR79

12

PC50

47P_0402_50V8J

PR72
1M_0402_1%

1 2

PR77

3.57K_0402_1%

1 2

PQ13

1

D1

2

D1

S1/D2

3

G2

S1/D2

4

S1/D2

S2

SI4814DY_SO8

12

PC54
100P_0402_50V8J

1 2

G1

PACIN<46,48>
SUSP#<38,40,45>

1 2

PDH31

8
7
6
5

PC52 and PC53 LOCATION
need change from BOM

B B

+3.3V Ipeak = 6.66A ~ 10A +5V Ipeak = 6.66A ~ 10A

VS

PR80

1 2

47K_0402_5%

4

PC41

0.1U_0805_25V7K

PR70

1 2

0_0402_5%

PLX3

PDL3

CSH3

PD33

2
3

RB715F_SOT323

PR76

270K_0402_5%

12

PC60

0.047U_0603_25V7M

BST31

1

3

BST51

3

VS

BST3
DH3
LX3

DL3

CSH3
CSL3
FB3
SKIP#
SHDN#

TIME/ON5
RUN/ON3

VL

1 2

22

V+

8

12

VL

PDH3

PD20

1SS355_SOD323

12

PC48

0.1U_0805_25V7K

PU7

25
27
26

24

1
2

3
10
23

7
28

12

PC56
680P_0402_50V7K

1 2

PR83

47K_0402_1%

12

PC61

0.047U_0603_25V7M

2

PD19
DAP202U_SOT323

1

12

PC47

4.7U_1206_16V4Z

21

4

12OUT

VL

5

VDD

18

BST5

16

DH5

17

LX5

19

DL5

20

PGND

14

CSH5

13

CSL5

12

FB5

15

SEQ

9

REF

6

SYNC

11

RST#

GND

MAX1632_SSOP28

MAINPWON <7,46,47>

+12VALWP

12

PR81

0_0402_5%

PC49

4.7U_1206_16V4Z

12

PC55

4.7U_1206_16V4Z

12

2.5VREF

POK <50>

PC44

1 2

0.1U_0805_25V7K

PDH5

PLX5

10.5K_0402_1%

4.7U_1210_25V6K

PR78

2

12

PC45

PR71

1 2

0_0402_5%

PDL5

12

12

PR82
10K_0402_1%

N4

B+++

12

PC46

4.7U_1210_25V6K

12

PC59
100P_0402_50V8J

PDH51

PC40
470P_0805_100V7K

1 2

PR69
22_1206_5%

PQ14

1

D1

2

D1

S1/D2

3

G2

S1/D2

4

S1/D2

S2

SI4814DY_SO8

1

+

3 2

PC58

CSH5

PC39

4.7U_1210_25V6K

12

PR75

0.012_2512_1%

PD22

EP10QY03

2 1

+5VALWP

1 2

12

PD18

EC11FS2_SOD106

FLYBACKSNB

12

1 4

PT1

SPC_SDT-1405P-100

8

G1

7
6
5

12

PC51
47P_0402_50V8J

12

PR74
2M_0402_5%

1

1

+

PC57

150U_D2E_6.3VM_R18@

2

2

150U_D2E_6.3VM_R18

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

1

0E

of

49 61¬P , 30, 2003

A

1 1

12

PC63

4.7U_1210_25V6K

PD23

PQ15

G1

D1
D1

S1/D2

G2

S1/D2
S1/D2

S2

SI4814DY_SO8

8
7
6
5

LX1.5

PC73 ESR=18m

2 2

+1.5VSP +2.5VALWP

2.0U_SPC-07040-2R0_6A_30%

1

+

PD24

EP10QY03

PC73

2

2 1

150U_D2E_6.3VM_R18

12

PR179

5.1K_0603_1%

PL8

1
2
3
4

12

+1.5VS_EN<52>

12

3 3

PR181

10K_0402_1%

0.1U_0603_25V4Z

DL1.5

DAP202U_SOT323

PC70

PR90

0_0402_5%

12

12

1

2

1 2

3

PR86

0_0402_5%

DH1.5

B

1U_0805_25V4Z

PC65

BST1.5A

12

PR84

0_0402_5%

1 2

25
26
27

24
28

11

PC69

1U_0805_25V4Z

BST1
DH1
LX1

DL1

MAX1845EEI_QSOP28

CS1

1

OUT1

2

FB1

ON1

OVP

8

0.22U_0402_10V4Z

4

V+

GND

23

1845-1_VCC

12

22

VCC

PU8

SKIP

6

PC78

PR85

20_0402_5%

1 2

9

VDD

UVP

BST2

DH2

LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR92

10

90.9K_0402_1%

PR93

12

16.2K_0603_1%

100K_0402_1%

21
19

18
17
20
16

15
14
12

7
5

13
3

12
12

+5VALWP

BST2.5A

DH2.5

PR94

C

BST2.5B

PR87

0_0402_5%

1 2

12

12

PC64

4.7U_1206_16V4Z

12

PR95

PC72

0.1U_0603_25V4Z
LX2.5

12

DL2.5

150K_0402_1%

PR91

0_0402_5%@

PR183

0_0402_5%

PR184

0_0402_5% @

D

PL7

1 2

HCB4532K-800T90_1812

12

12

PC68

5

PQ16

D8D7D6D

S1S3G

S

IRF7811A_SO8

4

2

4.4U_SPC-1405P-4R4_+40-20%

578

3 6

241

12

12

12

1 2

PQ17
FDS7764S_SO8

POK <49>

+3VALWP

+5VALWP

PC67

4.7U_1210_25V6K

4.7U_1210_25V6K

PL9

12

PR180

15K_0603_1%

12

PR182

9.53K_0402_1%

B+

1

1

+

+

PC75

2

2

220U_D2_4VM

PC76

220U_D2_4VM

PD25

EP10QY03

2 1

+1.5V Ipeak =

+2.5V Ipeak = 12.06A ~ 22.41A

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

D

0E

of

50 61¬P , 30, 2003

A

B

C

D

+3VALWP

PR96
0_1206_5%

1 1

13

D

PQ19

+1.8VS_EN<52>

2 2

2

G

2N7002_SOT23

S

PR99
332K_0603_1%

PC86

470P_0402_50V8J

1 2

21

10

8

9

6

7

3

PD26

EP10QY03

PC82

12

0.1U_0402_16V4Z

PQ18

1
2
3
4

SI4814DY_SO8

5

PU9

IN

1

HSD

BST

DH

LX

2

PC85

COMP

4

GND

MAX1954EUB_10UMAX

DL

PGND

FB

12

12

12

33P_0402_50V8J

22U_1210_6.3V6M

G1

D1
D1

S1/D2

G2

S1/D2
S1/D2

S2

12

PC80

8
7
6
5

12

22U_1210_6.3V6M

PL10

2.2UH_PLFC1235P-2R2A_6A_30%

1 2

PR98

11.5K_0603_1%

PR100

9.09K_0603_1%

PC81

12

220U_D2_4VM

12

PC83

1

+

2

+1.8VSP

1

+

2

PC84

220U_D2_4VM @

PU10

3 3

+1.8VSP

PC89

22U_1210_6.3V6M@

(1.25V)

+SDREF

+1.25VS_EN<52>

12

PC79

22U_1210_6.3V6M

PR101

1 2

12

0.1U_0402_10V6K

12

PC91

7

STANDBY/

4

VD
RefOut8VttSense

1

VSS

NE57814

VDD

ExtRefIn

VTT

5
6
2
3

PC92

1

+

2

150U_D2_6.3VM

12

PC93

0.1U_0402_10V6K

+1.25VSP

PC87

0.1U_0402_10V6K

12

12

PC90

0.1U_0402_10V6K

+2.5VS

12

PC88
1U_0603_10V6K

0_0402_5%@

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Title

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

D

0E

of

51 61¬P , 30, 2003

5

4

3

2

1

VS

12

Sequ en ce_ref

12

Sequ en ce_ref

12

8

PU19A

3

P

+

2

-

G

LM393M_SO8

4

8

5

P

+

6

-

G

4

PC147

0.1U_0603_25V4Z

D D

+2.5VS

C C

+1.8VS

10K_0402_5%

PR187

1 2

PC148

0.1U_0402_16V4Z

10K_0402_5%

PR190

1 2

PC149

0.1U_0402_16V4Z

+3VALWP +3VALWP

PR185
10K_0402_5%

1 2

1

O

+1.25VS_EN<51>

+3VALWP +3VALWP

PR188
10K_0402_5%

1 2

PU19B

7

O

LM393M_SO8

+1.5VS_EN<50>

+5VALWP

PR186
10K_0402_5%

1 2

+1.8VS_EN <51>

13

D

PQ47

2

G

2N7002_SOT23

S

2N7002_SOT231@

13

D

PQ22

2

G

S

PR189
10K_0402_5%

1 2

13

D

PQ48

2

G

2N7002_SOT23

S

1@

470P_0402_50V8J

1@

332K_0603_1%

12

PR105

12

PC101

PWR_SEL<16>

PR102

0_1206_5%1@

1 2

12

PC100

33P_0402_50V8J1@

+3VALWP

13

2

G

PQ21

G1

D1
D1

S1/D2

G2

S1/D2
S1/D2

S2

SI4814DY_SO8

PQ24

2N7002_SOT231@

12

PC95

22U_1210_6.3V6M1@

8
7
6
5

21

10

8

9

6

7

3

PR104

100K_0402_5%1@

PD27

EP10QY031@

PC97

12

0.1U_0402_16V4Z

1
2
3
4

1@

13

D

2

G

S

5

PU11

IN

1

HSD

2

COMP

4

GND

MAX1954EUB_10UMAX 1@

D

PQ23

2N7002_SOT231@

S

BST

DH

LX

DL

PGND

FB

12

PL11

2.2UH_PLFC1235P-2R2A_6A_30%1@

1 2

8.06K_0603_1%1@

5.23K_0603_1%1@

12

PR103

PR107

PC96

22U_1210_6.3V6M1@

VGA_CORE_PWR

1

12

12

PR106

9.09K_0603_1%1@

12

PC98

220U_D2_4VM1@

1

+

+

PC99
220U_D2_4VM@

2

2

PR108

3
2

5
6

1 2

1M_0402_1%

VS

8

PU3A

P

+

-

G

LM393M_SO8

4

8

+

-

4

12

1

O

PU3B

P

7

O

G

LM393M_SO8

PC102

0.1U_0603_25V4Z

4

VL

12

PR109
47K_0402_1%

12

PC104
1000P_0402_50V7K

POWER_SEL

H_PROCHOT# <5>

13

D

2

G

PQ25
2N7002_SOT23

S

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

POWER_SEL

2

VGA_CORE for M9+

L

H

1.5V

1.25V

VGA_CORE for M10P

L

H

1.2V

1.0V

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

PR103 = 8.06K_0603_1%

PR107 = 5.23K_0603_1%

PR103 = 4.64K_0603_1%

PR107 = 4.87K_0603_1%

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

1

0E

of

52 61¬P , 30, 2003

B B

ADP_I<40,48>

PR110

1 2

PR111

VL

A A

1 2

100K_0402_1%

200K_0402_1%

PR112

5

12

84.5K_0402_1%

12

Sequ en ce_ref

PC103
1000P_0402_50V7K

A

5

1 1

PR116

0_0402_5%@

1 2

PR118

PM_DPRSLPVR

5>

CPUCLK_STP#

,28>

2 2

1 2

0_0402_5%

PR119

0_0402_5%

0_0402_5%@

DSEN#:C3(Deep Sleep)

DRSEN:C4(Deeper Sleep)

3 3

+3VALWP

VID_PWRGD<5>

PR145

0_0402_5%

1.2VDD

12

12

VR_ON<40,45>

PR114

1 2

VCORE_ENLL<5>

12

PR120

1 2

0_0402_5%@

PC108

100P_0402_50V8J

PC114

4.7U_1206_16V4Z

PR149

0_0402_5%

0_0402_5% @

12

PR117

+5VALWP

12

0_0402_5%@

12

PR123

12

VID4<5>
VID3<5>
VID2<5>
VID1<5>
VID0<5>
VID5<5>

1 2

12

PR124

301_0402_1%

12

PR126

17.4K_0603_1%

PR139

4.22K_0603_1%

1 2

PU14

1

VIN

4

PG

3

EN

LMS5258_SOT23-5

PR151
100K_0402_5%

PR125

12

PR130

1K_0402_1%

0_0402_5%@

7

1 2

12

PR136

3.24K_0603_1%

VOUT

GND

Frequency Select

PU6B

5

+

0

6

-

LM358A_SO8

PR133

100K_0402_5%

VCORE_VTT

5

2

12

+3VALWP

PR135

1 2

+VCCVIDP

12

PC115

4.7U_1206_16V4Z

1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line
(Northwood="0",Prescott="1")

2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.

B

+5VALWP

12

PC105
1U_0603_10V6K

32

1
2
3
4
5

6
34
33

35

12

PC106

12

0.033U_0402_16V8K

1K_0402_1%@

PR121

10

11

9

36

37

PR128

1 2

0_0402_5%@

PC111

12

220P_0402_50V9J@

1 2

10K_0402_5%@

Panasonic ERTJ0EV334J (0402)
Locate this NTC resistor on
PCB between phase 2 and 3
for thermal compensation.

PR132
330K_0402_5%@

38
40
12
19

D

S

H_BOOTSELECT<4>

PU13

VCC
VID4

VID3
VID2
VID1
VID0
VID12.5

ENLL
DRSEN

DSEN#

OCSET

SOFT

DSV

FS

DRSV

VR-TT#
NTC
GND
GND

ISL6247_MLFP40

13

PQ28

2

G

2N7002_SOT23

PR113

80.6K_0603_1%

RAMPS

PGOOD

PWM1

ISEN1+

ISEN1-

PWM2

ISEN2+

ISEN2-

PWM3

ISEN3+

ISEN3-

PWM4

ISEN4+

ISEN4-

COMP

NC

VDIFF

VSEN
VRTN

OFS

PR137

1.2M_0402_5%

PQ27

13

2

TP0610T_SOT23

PR148
22K_0402_5%

12

PR150

100K_0402_5%

7
39

25
24

23

26
27

28

20
21

22

31
30

29

15

13

FB

14
16

17
18

8

PR140

340K_0603_1%

12

B+

1 2

PR115

0_0402_5%

+5VALWP

12

1 2

2

Battery Feed
Forward

12

10K_0402_5%

PR122
0_0402_5% @

PR129

12

0.1U_0402_16V4Z
PC112

PR142

PR141

5.1K_0603_1%

1 2

27K_0402_5%

1 2

13

D

2

G

S

PQ30
MMBT3904_SOT23

3 1

C

12

+5VALWP

PC107

1000P_0402_50V7K

12

PC110

12

1000P_0402_50V7K @

Place close to IC

1 2

12

PC113

1U_0603_10V6K

PR146

PQ29
2N7002_SOT23

0_0402_5%

PR147
0_0402_5% @

PR127

20K_0402_1%

1 2

PC109

12

1000P_0402_50V7K

@

PR131
0_0402_5%@

1.91K_0603_1%

PQ26

2N7002_SOT23

PR143

0_0402_5%

12

12

VCORE_PWRGD <42>

PWM1 <54>
ISEN1+ <54>

ISEN1- <54>

PWM2 <54>
ISEN2+ <54>

ISEN2- <54>

PWM3 <55>
ISEN3+ <55>

ISEN3- <55>

PWM4 <55>
ISEN4+ <55>

ISEN4- <55>

12

PR134

1 2

PR138

D

S

13

G

2

12

PR144

12

0_0402_5% @

Place near +VCC_CORE
output capacitor

VSSSENSE <5>

16.2K_0603_1%

+CPU_CORE

VCCSENSE <5>

12

Remote
Sensing

D

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期三 七月

D

0E

of

53 61¬P , 30, 2003

A

B

C

D

+5VALWP

PR152

2.2_0402_5%

1 1

PWM1 <53>

PR155

499K_0402_1%

2 2

1 2

PWM2 <53>

PR154

0_0402_5%

0.1U_0402_16V4Z

CPU_DRIVE_EN

ISEN1-<53>
ISEN1+<53>

12

PC122

1 2

1 2

PC123

1 2

1U_0603_10V6K

1 2

6
3
7
4

PR159

2.2_0402_5%

6
3
7

PR161
499K_0402_1%

1 2

3 3

ISEN2-<53>
ISEN2+<53>

PC131

1U_0603_10V6K

4

1 2

PC116

0.22U_0805_16V

PU15

BOOT

VCC
PWM

UGATE

EN

PHASE

LGATE

GND

ISL6207CB-T_SO8

PC126

1 2

0.22U_0805_16V

PU16

BOOT

VCC
PWM

UGATE

EN

PHASE

LGATE

GND

ISL6207CB-T_SO8

12

2
1
8
5

2
1
8
5

N5

PHASE1

PQ33

SI4362DY_SO8

N6

PQ35

IRF7811A_SO8

N7

PHASE2

PQ37

SI4362DY_SO8

N8

5

4

2

5

4

2

5

4

2

5

4

2

PQ31

D8D7D6D

S1S3G

S

IRF7811A_SO8

D8D7D6D

S1S3G

S

D8D7D6D

S1S3G

S

D8D7D6D

S1S3G

S

5

4

5

4

5

4

5

4

PQ32

D8D7D6D

4.7U_1210_25V6K

S1S3G

S

IRF7811A_SO8

2

PQ34

D8D7D6D

SI4362DY_SO8

S1S3G

S

2

D8D7D6D

PQ36

S1S3G

S

IRF7811A_SO8

2

PQ38

D8D7D6D

SI4362DY_SO8

S1S3G

S

2

4.7U_1210_25V6K
PC127

CPU_B+

PC117

4.7U_1210_25V6K

1 2

220P_0402_50V9J

12

PD28

EC31QS04

@

CPU_B+

12

4.7U_1210_25V6K

12

PD29

EC31QS04

@

PC118

12

68_0805_5%

12

PC128

220P_0402_50V9J

PC119

12

PC124

PR156

12

PC129

PC130

PR162

68_0805_5%

4.7U_1210_25V6K

12

Snubber

12

4.7U_1210_25V6K

12

12

1

+

PC120
100U_25V_M

2

1 2

0.56UH_ETQP4LR56WFC_21A_20%

PR157

32.4K_0603_1%

1 2

0.56UH_ETQP4LR56WFC_21A_20%

PR163

12

32.4K_0603_1%

Local Transistor
Swtich Decoupling

PL12

1 2

HCB4532K-800T90_1812

1000P_0402_50V7K

Panasonic ETQ-P4LR56WFC

PL13

12

Local Transistor
Swtich Decoupling

Panasonic ETQ-P4LR56WFC

PL14

12

PC151

PC125

12

0.01U_0402_50V7K

PR158

12

820B_0603_5%_ERAV33J821V

PC132

12

0.01U_0402_50V7K

PR164

12

820B_0603_5%_ERAV33J821V

12

PC150

0.1U_0603_25V4Z

12

PD30

EC31QS04

B+

5/5 BOM update

+CPU_CORE

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期四 七月

D

0E

of

54 61¬P , 31, 2003

A

PC133

1 2

+5VALWP

1 1

PWM3 <53>

PR167

499K_0402_1%

1 2

PC137

1U_0603_10V6K

PR165

2.2_0402_5%

1 2

1 2

6
3
7
4

0.22U_0805_16V

PU17

BOOT

VCC
PWM

UGATE

EN

PHASE
LGATE

GND

ISL6207CB-T_SO8

2
1
8

N9

PHASE3

5

5

4

5

4

B

D8D7D6D

S1S3G

S

2

D8D7D6D

S1S3G

S

2

PQ39
IRF7811A_SO8

PQ41
SI4362DY_SO8

5

4

5

4

D8D7D6D

S1S3G

S

2

D8D7D6D

S1S3G

S

2

PC134

PQ40

4.7U_1210_25V6K

IRF7811A_SO8

PQ42
SI4362DY_SO8

@

CPU_B+

12

PD31

EC31QS04

12

PC135

4.7U_1210_25V6K

220P_0402_50V9J

12

12

PC138

PR168

68_0805_5%

PC136

4.7U_1210_25V6K

12

12

C

Panasonic ETQ-P4LR56WFC

PL15

1 2

0.56UH_ETQP4LR56WFC_21A_20%

PR169

12

32.4K_0603_1%

PC139

12

0.01U_0402_50V7K

D

N10

ISEN3-<53>

CPU_DRIVE_EN

2 2

PWM4 <53>

PR173
499K_0402_1%

1 2

ISEN3+<53>

PC144

1U_0603_10V6K

PR171

2.2_0402_5%

1 2

1 2

1 2

PU18

6

VCC

3

PWM

UGATE

7

EN

PHASE

4

LGATE

GND

ISL6207CB-T_SO8

PC140

0.22U_0805_16V

2

BOOT

1
8
5

PHASE4

N11

5

4

5

4

D8D7D6D

S1S3G

S

2

D8D7D6D

S1S3G

S

2

PQ43
IRF7811A_SO8

PQ45
SI4362DY_SO8

5

4

5

4

D8D7D6D

S1S3G

S

2

D8D7D6D

S1S3G

S

2

PQ44
IRF7811A_SO8

PQ46
SI4362DY_SO8

CPU_B+

12

PC142

PC141

4.7U_1210_25V6K

4.7U_1210_25V6K

12

PD32

EC31QS04

@

12

PC145

220P_0402_50V9J

PR174

68_0805_5%

12

PC143

4.7U_1210_25V6K

12

12

Local Transistor
Swtich Decoupling

Panasonic ETQ-P4LR56WFC

PL16

1 2

0.56UH_ETQP4LR56WFC_21A_20%

PR175

12

32.4K_0603_1%

PR170

12

820B_0603_5%_ERAV33J821V

PC146

12

0.01U_0402_50V7K

+CPU_CORE

N12

3 3

ISEN4-<53>
ISEN4+<53>

PR176

1 2

820B_0603_5%_ERAV33J821V

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Title

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Size Doc u men t Numbe r R e v

Dat e : Sheet

Compal El e ct r o nics, Inc.

SCHEMATIC, M/B LA-1861

401257

期四 七月

D

0E

of

55 61¬P , 31, 2003

5

MODIFY PIR LIST

1. Mod ify the Block Diagram for sc he m atic page swap . ( Page 2)

2. Mod ify ATI chip re l ated schematic for recomend demo schem atic an d layou t action . ( Page 8~23)

2. Mod ify LAN chip related schematic for Model SPEC change d . (Page 33,34)

For B test

2003/4/10

D D

1.Modify Q48 join to C507 (Page 29)
2003/4/15

1.SGA19471D00 470u 2.5V D4 change to SGA20471D00 470u 2.5V D2

2003/4/22

1.Page5 change R23/R139 footprint and form 51.1_0402 to

51.1_0603(BOM&layout update)

2.Page7 net name FANSPEED1 and FANSPEED2 swap(layout update)

3.Page8 change R132 from 49.9_0402 to 24.9_0402(BOM update)

4.Page8 change R134 from 24.9K_0402 to 49.9_0402(BOM update)

5.Page10 change R958.1 contact to AGP_SBA0(BOM&layout update)

6.Page10 change R959.1 contact to AGP_SBA1(BOM&layout update)

7.Page10 new add R963/R964 2.2K_0402(BOM&layout update)

8.Page10 new add R969 0_0402 for ATI INTA# issue(BOM&layout update)

9.Page10 new add R1005 4.7K_0402 pull-high +1.8VS for internal VGA
Vref power(BOM&layout update)

C C

10.Page11 change R84 to 0_0402 and R88 to 68_0603(BOM update)

11.Page12 R104 for external VGA,R102 for internal VGA(BOM control)

12.Page13 New add D32/D33 RB751V,Add R147(BOM update)

13.Page13 del R146/R493(layout update)

14.Page13 R476/R150 change to @(BOM update)

15.Page13 R475/R151 change to Pop(BOM update)

16.Page16 new add R1002/R1003 for VGA 128M DRAM(BOM&layout update)

17.Page17 U7.F20 new add trace NMCSA1#

18.Page18 U7.R6 new add trace NMCSB1#

19.Page23 change R666 from 33_0402 to 68_0402,change R699/R703 from 1K_0402
to 10K_0402,change R689/R700 from 10K_0402 to 4.7K_0402(BOM update)

20.Page23 new add D34/D35 RB751V(BOM&layout update)

21.Page24 chnage U1.14 from CRT_VCC to +5VS(layout update)

22.Page24 chnage R5.2 from GND to +5VS(layout update)

23.Page25 del R717 and RP84.1 contact to GPIO0(layout update)

B B

24.Page25 chnage R718.1 contact to INT_OVCUR#3(layout update)

25.Page25 add R998 0_0402(BOM&layout update)

4

3

2

1

40.Page22 U34/U35 pin M4 add NMCSB1# and add R1007 0_0402 for external
VGA 128M RAM option(BOM&layout update)

41.Page17/18 del R85,R81,R89,R97,R484,R483,R485,R486(BOM&layout update)

42.Page32 JP21 Footprint update for CIS(layout update)

43.Page25 remove R711 from page26 to page25

44.Page41 add RP113 100K_8P4R_0804 100K_0402(BOM&layout update)

45.Page44 all new add for external USB2.0(BOM&layout update)

46.Y3,Y4 footprint update(layout update)

47.D9 footprint update(layout update)

48.page32 R69.2 contact to V1.8_LAN for LAN vender updater(layout update)

49.page32 R94.1 contact to LANVDD(layout update)

50.page32 R60/R49/C55/C52 BOM option(BOM update)

2003/4/24

1.page5 Add R1008 for speedstep issue(BOM&layout update)

2.page25/40 Y3/Y4 pin define update(layout update)

2003/4/25

1.page31 add resume for carbus issue(layout update)

2.page26 del R215 for R216 only(BOM&layout update)

2003/4/30

1.page45 add R1009 for SUSP#(BOM&layout update)

2.page32 add R1010 for LAN transformer issue(BOM&layout update)

2003/5/02

1.page40 change HPS from U21 88pin to 36pin(layout update)

2.page43 change JP24 pin7/8/9/10 to MDI0-/MDI0+/MDI1-/MDI1+
(layout update)

3.page43 USB20P2+ and USB20P2- swap(layout update)

4.page38 del RP1/RP91(BOM&layout update)

5.page23 del R605(BOM&layout update)

6.page28 change R598 to @ and del @ for R597(BOM update)

7.page37 add R1011~R1018 for USB2.0 option(BOM&layout update)

2003/5/05

1.page11 del R74,C84(layout update)

2.page25/30/32/33/34/38/40/44 add AC termination
R305,C353,R61,C40,R520,C608,R519,C601,R576,C632,R270,
C315,R981,C784,R200,C228 for EMI request(BOM update)

26.Page25 add R970 22_0402 for add external USB2.0 PCI clock (BOM&layout update)

27.Page26 add R1004 10K_0402 for VCORE _PWRGD pull-high +3V(BOM&layout update)

28.Page26 del RP11 and add R961/R962 10K_0402(BOM&layout update)

29.Page26 add R999/R1000/R1001 0_0402 for extrenal ovcur
option(BOM&layout update)

30.Page29 Q48 pin1.2.5.6/R396.2/R702.1 contact to +5VALW for sw_cdplay
power(layout update)

31.Page32 change R95.2 contact to R59.2(layout update)

32.Page35 del C415(BOM update)

33.Page35 U27 pin34 pull-high R965 0_0402 to VDDA for codec by pass
mode(BOM&layout update)

34.Page37 del L39/L40/L54/L51 and add R971~R978 for external USB2.0
option(BOM&layout update)

A A

35.Page36 add R968 for CY30/BY31 BOM option(BOM&layout update)

36.Page39 JP9 Footprint update for factory request(layout update)

3.page25 change damping resistor
R561,R563,R562,R560,R566,R549,R970,R559 to 33 ohm(BOM update)

4.page11/16 add AC termination R395,C464,R101,C127,R389,C451 for
EMI request(BOM update)

5.page11/16 add AC termination R395,C464,R101,C127,R389,C451 for
EMI request(BOM update)

6.page35 add AC termination C415 for EMI request(BOM update)

7.page7 add FAN Cap C641,C640,C633,C623 for EMI request(BOM update)

8.page24 new add Cap C806,C807 for EMI request(BOM&layout update)

9.page43 new add Cap C808 for SPR PS2 issue(BOM&layout update)

10.page27 change cap R634 footprint to 0_1206(BOM&layout update)

2003/5/14

1.R702 from 100K change to 10K (BOM update)

37.Page40 U21 pin3,4 swap(layout update)

38.Page40 AD_BID0 for Board ID update(BOM update)

39.Page21 U29/U30 pin M4 add NMCSA1# and add R1006 0_0402 for external
VGA 128M RAM option(BOM&layout update)

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Docu ment Number Re v

3

2

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

1

星期三 七月

0E

of

56 61,

5

4

3

2

1

For B2 test

2003/5/22

1.Page13 R147.1 connect to R473.2,R489.1 connect to R502.2(layout update)
2003/6/09

1.Page7 C623/C633 update footprint 0402 type(layout update)

2.Page45 R199,R567,R167 update value for power sequence delay(BOM update)

D D

3.Page25 del R569 for PCI_CLKRUN# pull_high(Layout & BOM update)

4.Page25 Add R578 for PCI_CLKRUN# pull_high(Layout & BOM update)

5.Page30 Del R311 for PCI_CLKRUN# pull_high(BOM update)

6.Page40 Del R268 for EC591 not need (BOM update)

7.Page29 add D36 for SIDEPWR leakage current(layout & BOM update)

8.Page10 Del R1005 it's not need(BOM update)

9.Page41 Add R1021 for EC_FLASH# pull_high(Layout & BOM update)

10.Page26 Add R1022 pull_high(Layout & BOM update)

11.Page26 R956 pin1 contact to GND(Layout update)

12.Page8 add R1023(BOM update)

13.Page8 Del R173,R479,Q12 for change to @(BOM update)

31.Page26 Del R208,R209 8.2K_0402(Layout & BOM update)

32.Page26 Change R224,R219,R707,R708 to 8.2K_0402(BOM update)

33.Page26 Del R1004 10K_0402(Layout & BOM update)

34.Page44 Add R997 0_0402( BOM update)

35.Page44 R997 pin1 contact to LPC_SMI# for DOS mode USB
support (Layout update)

36.Page27 Add D37 RB751V,R1034 1K_0402(Layout & BOM update)

37.Page27 Change C219,C223,C222,C699 to
22U_1206(Layout & BOM update)

38.Page28 Add R685,R669,R697,R670,R677 10K_0402(BOM update)

39.Page28 Del R698 10K_0402(BOM update)

40.Page40 Add C820 for EC97591 option(Layout update)

41.Page42 Add R253 0_0402(BOM update)

42.Page42 Del R229,R745,R746,Q67,C299,C281,Q20,Q24,(BOM
update)

43.Page42 Change R252 to 330K_0402(BOM update)

44.Page42 Change C307 to 0.1U_0402(BOM update)

45.Page42 Add R1035 1K_0402,R1036 10K_0402,C821

2003/6/11

1.Page5 R1008 change to 4.7K_0402 for follow HR60(BOM update)

2.Page5 Q5,Q6 change to MMBT3904 for follow HR60(BOM update)

C C

3.Page5 del RP4 for ITP update (BOM update)

4.Page5 add R1024 47_0402,R1027 47_0402 ,R1025 150_0402 ,R1026 680_0402,R390

54.9_0603_1%,R404 54.9_0603_1% for ITP update(Layout & BOM update)

5.Page6 del C122,C46 for cost down (BOM update)

6.Page12 del C576,C588,C201,C198 for cost down (BOM update)

7.Page12 Change C150 to 47U_B(Layout & BOM update)

8.Page12 add C810,C811,C812 0.1U_0402 for +1.5VS(BOM update)

9.Page15 add C813,C814 22U_1206 for +1.25VS(Layout & BOM update)

10.Page15 del C280,C282 for cost dowN(BOM update)

11.Page16 add @ R1028 contact to PCI_RST# for RST# option(Layout update)

12.Page16 add R1029 0_0402 contact to NB_RST# for RST# option(Layout & BOM update)

13.Page16 add @ R1030 for M9+ SUS_STAT# option(Layout update)

14.Page16 add R1031 10K_0402 for M9+ SUS_STAT# pull-high +3VS(Layout & BOM update)

15.Page17,18 del R405,R407,R420,R421,R466,R467,R465,R464(BOM update)

16.Page19 Add C815,C816 for +VDDC15(Layout & BOM update)

17.Page20 Del C497 for cost down(BOM update)

B B

18.Page21 Del RP25,RP26,RP27,RP28,RP29,RP30,RP31,RP32,RP33,RP34,RP35 for
cost down(Layout & BOM update)

19.Page21,22 Del RP36,RP37,RP38,RP39,RP40 for cost down(Layout & BOM update)

20.Page21,22 Del RP41,RP42,RP43,RP44,RP45,RP46,RP47,RP48,RP49,RP50 for cost
down(Layout & BOM update)

21.Page22 Del RP52,RP53,RP54,RP55,RP56,RP57 for cost
down(Layout & BOM update)

22.Page21 Del R384,R394,R418,R385,R383,R398,R410,R386 for cost down(Layout & BOM
update)

23.Page21 Del R505,R453,R474,R509,R506,R455,R461,R508 for cost down(Layout & BOM
update)

24.Page22 Del R516,R534,R497,R524,R518,R535,R496,R522 for cost down(Layout & BOM
update)

25.Page22 Del R523,R498,R533,R515,R527,R499,R532,R517 for cost down(Layout & BOM

A A

update)

26.Page23 Change U40 pin10 contact to VTT_PWRGD (Layout update)

0.1U_0603,Q68 2N7002(Layout & BOM update)

46.Page43 Add R1037,R1038,R1039,R1040 0_0402 for
SPR LAN option(Layout & BOM update)

2003/6/12

1.Page43 Change R979,R980 contact to JP24
pin21,20 for USB trace option (Layout update)

2.Page43 Change R979,R980,L37,L38 to 0_0402 for SPR USB
option(Layout & BOM update)

3.Page37 Change L32,L33,L34,L35,L53,L55,L50,L52 to
0_0402 for SPR USB option(Layout & BOM update)

4.Page26 Del
R638,R647,R613,R640,R601,R611,R593,R603,R553,R551,R555,R550
for ATI DOC_PA_218IXP0T1 request(BOM update)

5.Page24 JP5,JP6 reverse for ME update(Layout update)
2003/6/12

1.Page32 Del U6 Pin114,113(schematic update)

2.Page32 Q44,Q46 from 2SB1197 change to 2SB1188(Layout & BOM update)

3.Page32 U28 from 24ST0023P change to H5007(H1285)

4.Page32 C10 1000P_0402_50V7K change to 1000P_1206_2KV7K
(Layout & BOM update)

2003/6/16

1.page11 Add L59,L60,L61,L62,L63 0805 type NB power
bed (Layout & BOM update)

2.page11 Change R399,R70 type to 0805 for NB power
bed (Layout & BOM update)

3.page11 Del Q47 for change to @(BOM update)
2003/6/17

1.Page24 JP5,JP6 reverse again for ME update(Layout update)

2.page40 Change C820 to 0603 type(Layout update)

27.Page24 Add C817 10U_0805 for LCDVDD_C power (Layout & BOM update)

28.Page25 Add C818,C819 180P_0603 (Layout & BOM update)

29.Page25 Add C621,C622 180P_0603 (BOM update)

30.Page26 Add R1032,R1033 10K_0402 for PWRBTN_OUT
pull-high and SB_EEDI pull-down (Layout & BOM update)

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

1

星期三 七月

0E

of

57 61,

5

For B2 test

4

3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

2003/6/18

1.Page8 Add C822 D2 type for CPVDD power(Layout update)

2.Page16 Add R1041 8.2K_0402 AGP_FRAME# pull-high to +3VS(Layout & BOM update)

3.Page45 Add R1042,Q69 / R1043,Q70 / R1044,Q7 ,for +3V,+1.5VS,+VGA_CORE discharge circuit(Layout & BOM update)

4.Page8 add C823 0.1u_0402 for ATI recommand

D D

5.Page19 add C824,C825,C826 0.1U for 1.5VS
C828,C827 0.1U for +VDDC15

2003/6/19

1.Page32 U28 +-pair reverse(Layout update)

2.Page14 add RP114,RP115,RP116,RP117,RP118,RP119,RP120,R1045,R1046,R1047,R1048,R1049,R1050,R1051,R1052,R1053 for ATI DDR
recommand(Layout & BOM update)

3.Page23 R688 pin1 contact to U40 pinD5(Layout update)

4.Page42 C821 change to 0402 type(Layout & BOM update)

5.Page8 Update C822(Layout update)

6.Page43 Update L34,L38 to JP24 NET name.
2003/6/20

1.Page34 add C663 for audio noise(BOM update)
2003/6/22

1.Page25 R187 change to 4.7K for 4/22 ATI review update(BOM update)

2.Page25 GPIO0,OVCUR#4 pull-down for 4/22 ATI review update(Layout update)

3.Page26 del R1033 for 4/22 ATI review update(BOM update)

C C

4.Page26 R706 pull-high to +3V for 4/22 ATI review update(BOM update)

5.Page28 R579 pull-high to +3VS for 4/22 ATI review update(Layout update)

6.Page28 del R597(CPU_STP# strap not need) for 4/22 ATI review update(BOM update)

7.Page29 Change R732,R734,R747,R165,R159,R164 to 33_0402 for 4/22 ATI review update(BOM update)

8.Page29 SD_D7 Add R1054 10k_0402 Pull-down for 6/22 ATI review update(Layout & BOM update)
2003/6/24

1.Page38 Del RP65 for cost down(Layout & BOM update)

2.Page38 Add RP0121,RP122 for cost down(Layout & BOM update)

3.Page40 Add RP0123,RP124 for cost down(Layout & BOM update)

4.Page40 Del RP19 for cost down(Layout & BOM update)
2003/6/25

1.Page43 change SPR USB power source(Layout update)
2003/6/26

1.Page43 add U50,C829 for SPR USB power switch(Layout & BOM update)

2.Page26 add R659,C659 for EMI request(BOM update)
2003/7/01

B B

1.Page16 add R1030 0_0402 for S3 SUS_STAT# issue(BOM update)

2.Page16 del R1031 for S3 SUS_STAT# issue(BOM update)

For C test

2003/7/07

1.Page36 C364 from 1U_0402 change to 1U_0603 (Layout & BOM update)

2.Page31 C366,C352 from 4.7U_1206 change to 4.7U_0805 (Layout & BOM update)

3.Page29 C507 from TAN4.7U_0805 change to 4.7U_0805 (Layout & BOM update)

4.C170,C184,C189,C217,C224,C229,C277,C615,C620,C677,C718,C723,C728 from 10U_1206 change to 10U_0805 (Layout & BOM update)

5.C68,C92,C168,C406,C416,C420,C468,C565,C606,C730,C780,C637,C642 from 10U_1206 change to 10U_0805 (Layout & BOM update)
2003/7/10

1.Page5 change R194 from 62_0402 to 200_0402 for ATI recommend(BOM update)

2.Page8 change R80 from 412_0402 to 330_0805_1% for ATI recommend(BOM update)

3.Page11 del M9@ C75/X2/R73 ATI recommend(BOM update)

4.Page11 add R1055 4.7K_0402 for ATI recommend(Layout & BOM update)

5.Page16 add Q72 for SUSSTAT# level shift and ATI recommend(Layout & BOM update)

6.Page16 add R1031 10K_0402 for SUSSTAT# level shift and ATI recommend(BOM update)

A A

7.Page16 change R1030 to 470_0402 for SUSSTAT# level shift and ATI recommend(BOM update)

8.Page24 add R1056 2.7K_0402 for ENAVDD pull-down and ATI recommend(Layout & BOM update)

9.Page25 change D13 to RB751V for ATI recommend(Layout & BOM update)

10.Page40 change +RTCVCC to BATT1.1 for ATI recommend(Layout update)

11.Page8 del C97 for CEL CPU can't BOOT issue(BOM update)

12.Page40 del R270/C315 for can't BOOT issue(BOM update)

13.Page32 update Q44/46 footprint(Layout update)

14.Page14 add C830/C831 for ATI recommend(Layout & BOM update)

5

4

3

2

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1861

Size Docu ment Number Re v
Custom

401257

Date: Sheet

星期三 七月

30, 2003

1

of

58 61,

0E

5

4

3

2

1

For C test

2003/7/11

1.Page29 add R1057 0_0402 for cost down(Layout & BOM update)

2.Page29 del Q64/R702/Q61 for cost down(BOM update)

3.Page29 del D36 for cost down(BOM update)

4.Page29 add R1058 for cost down(BOM update)

5.Page35 del R295/Q34 for cost down(BOM update)

D D

2003/7/15

1.Page35 add C832_1U_0603 for MIC noise issue(Layout & BOM update)

2.Page35 Change C379 form 0805 to 0603(Layout & BOM update)

3.Page35 add C410 form audio noise(BOM update)

4.Page29 add C609/C174 form audio noise(BOM update)

5.Page36 add R1059 form audio AMP(Layout & BOM update)

6.Page36 del R339/R334/R335/R333/Q30/Q31/Q32/Q33 form audio AMP(BOM update)

7.Page36 R338 change to 1K_0402( BOM update)
2003/7/18

1.Page39 add C833/C836/C837/C838/C839 for EMI request(Layout & BOM update)

2.Page10 DEL R118/R112/U9/L16/R117/C148/R111/R108/R116/C137/C133 for EMI request(BOM update)

3.Page35 add R1061 2.2K_0402(Layout & BOM update)

4.Page35 change JP9 pin34/35 to (Layout update)

5.Page26 RP12 from 10k change to 2.2K (BOM update)

C C

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

SCHEMATIC, M/B LA-1861

Size Docu ment Number Re v
Custom

401257

Date: Sheet

星期三 七月

30, 2003

1

of

59 61,

0E

10

9

8

7

6

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

H H

Reason for change PAGE Modify List M.B Ver.Fixed IssueItem

1

2

modify for RTC battery

For ME change battery connecter

46 Del PD6(RLZ3.6B) and add PR177(100_0805_5%)

Add PR178(200_0603_5%)

47 change P/N: from DC040012310 to DC040012330

EVT

EVT

3

G G

4

F F

E E

5

6

D D

7

8

Modify +1.5VSP ripple and OCP
+2.5ALWP output voltage

add po wer sequence circuit
for HW requirement

add VGA_CORE power select
for HW requirement

change CPU CORE boost resister value
for EMI requirement

Add by pass cap. for EMI requirement

For BOM error

50 change PL8 from 5U_SPC-06704-5R0_2.9A

52 add PU19 LM393M_SO8

50

52

54
55

54 Add PC150 0.1U_0603_50V

51

to 2U_SPC-SPC-07040-2R0_6A
change PC73 from 150U/4V( ESR=45 )
to 150U/6.3V( ESR=18 )
change PR93 from 102K_0402_1% to 16.2K_0402_1%
add PR179(5.1K_0402_1%)
add PR181(10K_0402_1%)
add PR180(15K_0402_1%
add PR182(9.53K_0402_1%)

add PC147 0.1U_0603_50V
add PC148 0.1U_0603_50V
add PC149 0.1U_0603_50V
add PR187 10K_0603_5%
add PR185 10K_0603_5%
add PR186 10K_0603_5%
add PR183 0_0402_5%
add PR184 0_0402_5%
add PR188 10K_0603_5%
add PR189 10K_0603_5%
add PR190 10K_0603_5%
add PQ47 2N7002_SOT23
add PQ48 2N7002_SOT23

add PQ23 2N7002_SOT23(for DBY31)

change PR152 , PR159 , PR165 , PR171
from 0_0603_5% to 2.2_0603_5%

Add PC151 1000P_0603_50V

Change PR98 vaule from 4.87K_0603_1% to

11.5K_0603_1%

EVT

EVT

EVT

EVT

EVT

EVT

C C

9

Change Battery side OTP point to 79C for thermal requirement

47 Change PR39 from 16.9K_0603_1% to 14.7K_0603_1%

DVT

Change PR41 from 3.32K_0603_1% to 3.48K_0603_1%

10

11

B B

12

A A

10

Delete CPU_CORE IC's OTP function

Add snubber for EMI requirement

Change Material

9

8

7

53 Delete PR132,PC111

54,55 Add 68_0805_5% at PR156,PR162,PR168,PR174

Add 220P_0603_50V at PC124,PC130,PC138,PC145

49,50 Change PC53,PC58,PC73 from SGA19151330(H2.8)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6

to SGA20151320(H1.9)

5

4

DVT

DVT

DVT

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1861

Size Docu ment Number Re v
Custom

401257

星期三 七月

3

Date: Sheet

30, 2003

2

60 61,

0E

of

1

10

9

8

7

6

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 2

H H

Reason for change PAGE Modify List M.B Ver.Fixed IssueItem

14

G G

F F

E E

To prevent surge current at CPU_CORE

54,55 Add 499K_0603_5% at PR155,PR161,PR167,PR173

PVT

D D

C C

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10

9

8

7

6

5

4

3

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1861

Size Docu ment Number Re v
Custom

401257

星期三 七月

Date: Sheet

30, 2003

2

of

61 61,

1

0E