Compal LA-1861, TravelMate 540 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Intel portability uFCBGA/uFCPGA
with ATI-RC300M+SB200 core logic

3 3

4 4

A

B

2003-07-10

REV:0.4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Docu ment Number Re v

D

Date: Sheet

Compal E l e c t r onics, Inc.
SCHEMATIC, M/B LA-1861

401257

星期三 七月

30, 2003

0E

of

161,

E

A

B

C

D

E

Compal confidential

File Name : LA-1861

1 1

W/EXT VGA CHIP

W/EXT VGA CHIP

VGA DDR x2 CHB

2 2

IEEE 1394
VIA -VT6301

3 3

page 33

IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)

RTC CKT.

page 25

Mini PCI
socket

IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)

CRT & TV -O UT Conn.

LCD C onn

ATI-M9+X/M10C

page 16,17,18,19,20

VGA DDR x2 CHA

page 22

IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)

RTL 8100C/8110S

page 34

page 24

page 24

page 21

3.3V 33 MHz

LAN

page 32

RJ45 CONN

page 32

Power OK CKT.

page 42

Power On/Off CKT.

page 39

DC/DC Interface CKT.

4 4

page 44

Power Circuit DC/DC

page 45,46,47,48,49,50,51,52,53,54

A

Fan Cont rol

page 7

W/O EXT VGA CHIP
W/O EXT VGA CHIP

AGP BUS

USB conn x4

page 37

VIA_ VT 6202
USB2.0

IDSEL:AD27
(PIRQA/B/C#,GNT#4,REQ#4)

page 44

PCI BUS

IDSEL:AD20
(PIRQC/D#,GNT#2,REQ#2)

CardBus Controller

ENE C B1420

Slot 1

page 31

page 30

Slot 0

page 31

EC NS8 7 591L

page 39

EC I/O Buffer

page 41

B

Intel Northwood

uFCBGA-479/uFC PGA-478 CP U

page 4,5,6

PSB

533MHz

ATI-RC300M

VGA M9 Embeded

718 pin u-BGA

page 8,9,10,11,12,13

A-Link

ATI-SB200

BGA 457 pin

page 25,26,27,28

LPC BUS

page 40

Int.KBDTouch Pad

BIOS

page 39

page 41

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PARALLEL

page 43

Serial

page 38

C

Therm al Sensor
ADM1 032AR

H_D#(0..63)H_A#( 3..31)

Memory BUS(DDR)

2.5V DDR- 200/266

USB Interface

AC-LINK

Primary IDE

ATA-100

Secondary IDE

ATA-100 page 29

SMsC L PC 47N227

Super I/O

page 38

FDD

page 38

Clock Generator

page 7

DDR-SO-DIMM X2

BANK 0 , 1, 2, 3

Blu etooth

Card Reader

USB conn x4

Audio Codec
ALC202A

MDC CONN

Mini-PCI solt

HDD
Connector

CDROM
Connector

D

ICS 951402

page 23

page 14

page 37

page 37

page 37

page 35

page 37

page 34

page 29

SPR USB X 2

page 43

AMP

page 36

RJ11 CONN

page 37

SPR CONN.

*RJ45 CONN
*PS2 x2 CONN
*CRT CONN
*LINE IN JACK
*LINE OUT JACK
*DC JACK
*TVOUT CONN
*PRINTER PORT
*COM PORT
*USB CONN x1

page 43

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

of

261,

E

0E

A

Symbol Note :

Voltage Rails

Power Plane

VIN
B+
+CPU_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3VS OFF
+3V 3.3V system power rail for SB,LAN,CardReader and HUB. ON ON OFF

+5VS
+12VALW
+12VS
RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit.

The voltage for Processor VID select

1.25V switched power rail for DDR Vtt

1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.

1.8V switched power rail for ATI-RS300M/RC300M NB.

2.5V always on power rail

2.5V system power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V switched power rail OFF
12V always on power rail
12Vswitched power rail on power rail
RTC power

S0-S1

N/A
N/A
ON
ON

ON
ON

ON

ON
ON
ON
ON

ON
ON
ON
ON
ON

S3

N/AONN/A
N/A
OFF
OFF
OFF

OFF
OFF

OFF
ONON
ON
OFF
ON

ON
OFF
ON
OFF
ON

S5

N/A
OFF
OFF
OFF

OFF
OFF
ON*
OFF
OFF
ON*
OFF

ON*+5VALW 5V always on power rail

ON*
OFF
ON

@ : means just reserve , no build
M9@ : means just build when no exter nal AG P VGA chip build in .
M9+/M10@ : mean s j ust b u i l d when M9+XC or M10 build in
M9+@ : mean s j ust build wh e n M9+X C chip build in .
M10@ : means just build when M 1 0 c h i p build in .
NSPR@ : m e a ns jus t build when n o SPR build in .
SPR@ : mea ns ju st b u ild when SP R build in .
8100S@ : means just build when 8100S build in .
1394@ : means just build when 1394 b uild in .
MDC@ : me a n s just build when MDC build in .

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

Exter n al PCI Devices

1 1

NB Internal VGA
AGP BUS
SOUTHBRI DGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN
VIA 6202 USB20 AD27 4 A/ B/ C

IDSEL # PIRQ

N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24 (INT.)
AD16
AD19
AD20
AD18

REQ/GNT #DEVICE

N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3

A
A

N/A

D
B
A
C
A
D
A/B
C

I2C / SMBUS ADDRESSING

: me a ns Digi t a l Ground

: me a ns Ana l og Ground

100K +/- 5%Ra

Rb V min
0
1
2
3
4
5
6

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

7NC

Board ID

0
1
2
3
4
5
6
7

AD_BID

0 V

V typ

AD_BID

0 V 0 V

V

AD_BID

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

PCB Revision

0.1

0.2

0.3

0.4

max

DEVICE HEX ADDRESS

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERA TOR (EXT.)

A2
D2

1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

401257

星期三 七月

30, 2003

of

361,

0E

5

4

+CPU_CORE

3

2

1

D D

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

C C

H_REQ#[0..4]<8>

H_ADS#<8>

R110
@62_0402_5%

+CPU_CORE
+CPU_CORE

B B

R416

1 2

1 2

H_BR0#<8>
H_BPRI#<8>
H_BNR#<8>

H_LOCK#<8>

CK_BCLK<23>

CK_BCLK#<23>

H_HIT#<8>

H_HITM#<8>

H_DEFER#<8>

200_0402_5%

CK_BCLK#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#

CK_BCLK

AF22
AF23

A10

A12

A14

A16

A18

A20

AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19

C10

C12

C14

C16

C18

C20

D11

D13

D15

D17

D19

D9

VCC_65C8VCC_66

VCC_84

VCC_85

F9

F11

VCC_67

VCC_68

VCC_79E8VCC_80

E20

VCC_69

VCC_78

E18

VCC_70

VCC_77

E16

E10

VCC_71D7VCC_72

VCC_75

VCC_76

E12

E14

VCC_73

VCC_74

D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

H_D#0H_A#3

B21

D#0

H_D#1

B22

D#1

H_D#2

A23

D#2

H_D#3

A25

D#3

H_D#4

C21

D#4

H_D#5

D22

D#5

H_D#6

B24

D#6

H_D#7

C23

D#7

H_D#8

C24

D#8

H_D#9

B25

D#9

H_D#10

G22

H_D#11

H21

H_D#12

C26

H_D#13

D23

H_D#14

J21

H_D#15

D25

H_D#16

H22

H_D#17

E24

H_D#18

G23

H_D#19

F23

H_D#20

F24

H_D#21

E25

H_D#22

F26

H_D#23

D26

H_D#24

L21

H_D#25

G26

H_D#26

H24

H_D#27

M21

H_D#28

L22

H_D#29

J24

H_D#30

K23

H_D#31

H25

H_D#32

M23

H_D#33

N22

H_D#34

P21

H_D#35

M24

H_D#36

N23

H_D#37

M26

H_D#38

N26

H_D#39

N25

H_D#40

R21

H_D#41

P24

H_D#42

R25

H_D#43

R24

H_D#44

T26

H_D#45

T25

H_D#46

T22

H_D#47

T23

H_D#48

U26

H_D#49

U24

H_D#50

U23

H_D#51

V25

H_D#52

U21

H_D#53

V22

H_D#54

V24

H_D#55

W26

H_D#56

Y26

H_D#57

W25

H_D#58

Y23

H_D#59

Y24

H_D#60

Y21

H_D#61

AA25

H_D#62

AA22

H_D#63

AA24

H_D#[0..63] <8>H_A#[3..31]<8>

JP25A

VCC_0

VCC_1

VCC_2

VCC_3

VCC_4

VCC_5

VCC_6A8VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56B7VCC_57B9VCC_58

VCC_59

VCC_61

VCC_62

VCC_63

K2

A#3

K4

A#4

L6

A#5

K1

A#6

L3

A#7

M6

A#8

L2

A#9

M3

A#10

M4

A#11

N1

A#12

M1

A#13

N2

A#14

N4

A#15

N5

A#16

T1

A#17

R2

A#18

P3

A#19

P4

A#20

R3

A#21

T2

A#22

U1

A#23

P6

A#24

U3

A#25

T4

A#26

V2

A#27

R6

A#28

W1

A#29

T5

A#30

U4

A#31

V3

A#32

W2

A#33

Y1

A#34

AB1

A#35

J1

REQ#0

K5

REQ#1

J4

REQ#2

J3

REQ#3

H3

REQ#4

G1

ADS#

AC1

AP#0

V5

AP#1

AA3

BINIT#

AC3

IERR#

H6

BR0#

D2

BPRI#

G2

BNR#

G4

LOCK#

BCLK0
BCLK1

F3

HIT#

E3

HITM#

E2

DEFER#

VSS_0H1VSS_1H4VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12A3VSS_13A9VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

A11

A13

A15

A17

A19

A21

A24

H23

H26

A26

AA1

AA4

AA11

AA13

AA15

AA17

AA19

AA23

AA26

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

AA7

AA9

AB10

AB12

AB14

AB16

Prescott

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

AB3

AB6

AB8

AB18

AB20

AB21

AB24

AC11

AC13

AC15

AC17

AC19

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

AC2

AC5

AC7

AC9

AC22

AC25

AD10

AD12

AD14

AD16

AD18

AD21

AD23

VCC_64

BOOTSELECT

VSS_54

VSS_55

VCC_81

VCC_82

VCC_83

F13

F15

F17

F19

AD1

AD4

AD8

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

A6 TESTHI11 GHIPull-up 200ohm

TESTHI11

B6 FERR# FERR#/PBE# Pull-up 62ohm

AA20 ITPCLKOUT0 Pull-up56ohm

AB22 ITPCLKOUT1 Pull-up 56ohm

AD2 NC VIDPWRGD Pull-up 2.43K ohm

AD3 NC float VID5 Pull-up1Kohm to

A A

AF3 NC float VCCVIDLB Connect to +VCCVID
AD20 VCCA VCCIOPLLConnect to CPU

AE23

VCCIOPLL VCCA

AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/

TESTHI12 TESTHI12AD25 DPSLP

Commend Commend

to +VCC_CORE
Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCC_CORE
float

Filter
Connect to CPU

Filter
Connect to GND CPU determine

Pull-up 200ohm
to +VCC_CORE

5

Prescott
Pin name

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

TESTHI6 Pull-up 62ohm

TESTHI7 Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCCVID

+3VRUN & connect
to PWRIC

Connect to CPU

Filter

Connect to CPU

Filter

COMPAT#

float

Pull-up 62ohm
to +VCC_CORE

Northwood MT
Pin name

FERR#

ITPCLKOUT0

ITPCLKOUT1

NC

NC

NC
VCCA

VCCIOPLL

VSS
VSS

Commend

Connect to PLD
CPUPREF through
0ohm

Pull-up 62ohm
to +VCC_CORE

Pull-up56ohm
to +VCC_CORE

Pull-up 56ohm
to +VCC_CORE

float

float

float

Connect to CPU
Filter

Connect to CPU
Filter

Connect to GND
Connect to GND

Connect to PLD
through 0ohm

4

Northwood

Pop

Pop

Pop

Depop

Depop

Pop

Pop Pop

Prescott

PopPop Pop

Pop

Pop

Pop

PopDepop

Pop

Pop

Depop

DepopPop

Pop

Northwood
MT

H_BOOTSELECT<53>

Pop

Pop

Pop

Depop

Depop

Depop

Pop

Pop

3

H_BO OTSELEC T

Note: pop in page53

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R_C

+CPU_CORE

1 2

R141
@0_0402_5%

Pop: No rt hwood
Depop: Pr es cott

Title

Size Document Number Re v

2

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

461星期T, 30, 2003

5

4

3

2

1

+CPU_CORE

AE11

AE13

AE15

AE17

AE19

AE22

AE24

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B10

B12

B14

B16

B18

B20

B23

B26

C11

C13

C15

C17

C19

C22

C25

D10

D12

D14

D16

D18

D20

D21

D24

E11

E13

E15

E17

E19

E23

E26

F10

F12

F14

F16

F18

F22

F25

VSS_121

VSS_122

VSS_123

VIDPWRGD

VID5

AD2

H_VID_PWRGD

11

F5

VSS_124

VSS_125F2VSS_126

VSS_127

OPTIMIZED/COMPAT#

AF4

2

JP25B

VSS_57

F1

G5

F4

AB2

J6

C6

B6
B2
B5

AB23

Y4

D1

E5

W5

AB25

H5

H2
AD6
AD5

B3

C4

A2

AC6
AB5
AC4

Y6
AA5
AB4

D4
C1
D5

F7

E6

AD20
AE23

A5

A4
AF3

AD22

ITP

AC26

ITP#

AD26

COMP0

L24

COMP1

P1

2

C447

0.1U_0402_16V4Z

1

R_A

200_0402_1%

49.9_0402_1%

4

VSS_58

RS#0
RS#1
RS#2
RSP#
TRDY#

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCIOPLL
VCCA

VCCSENSE
VSSSENSE
VCCVIDLB

VSSA

ITP_CLK0
ITP_CLK1

COMP0
COMP1

VSS_129F8VSS_130

G21

G24

1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+CPU_GTLREF

R_B

169_0402_1%

100_0402_1%

VSS_59

VSS_60

VSS_131

VSS_132G3VSS_133G6VSS_134J2VSS_135

VSS_61

VSS_62

VSS_63

VSS_65

VSS_66

VSS_67

VSS_136

VSS_137J5VSS_138

J22

J25

K21

K24

1

C446
220P_0402_50V8J~D

2

VSS_68

VSS_69

VSS_139

VSS_140K3VSS_141K6VSS_142L1VSS_143

VSS_70

VSS_71

VSS_72

VSS_73

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85B4VSS_86B8VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92C2VSS_93

VSS_94

VSS_95C5VSS_96C7VSS_97C9VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117E4VSS_118E7VSS_119E9VSS_120

Prescott

VID0

VID1

VID2

VID3

AE5

AE4

AE3

AE2

VID0
VID1
VID2
VID3
VID4
VID5

+3VS

12

R179
10K_0402_5%

13

U44D

OE#

I12O

SN74LVC125APWLE_TSSOP14

VID4

AE1

AD3

VSS_144

VSS_145L4VSS_146M2VSS_147

VSS_148

VSS_149M5VSS_150

VSS_151

VSS_152N3VSS_153N6VSS_154P2VSS_155

VSS_156

VSS_157P5VSS_158R1VSS_159

VSS_160

VSS_161R4VSS_162

VSS_163

VSS_164T3VSS_165T6VSS_166U2VSS_167

VSS_168

VSS_169U5VSS_170V1VSS_171

VSS_172

VSS_173V4VSS_174

VSS_175

VSS_176W3VSS_177W6VSS_178Y2VSS_179

VSS_180

VSS_181

L23

L26

N21

N24

M22

M25

T21

P22

T24

P25

R23

R26

VID_PWRGD<53>

VCORE_ENLL<53>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

V23

V26

U22

U25

Y5

Y22

Y25

W21

W24

12

R1770 _ 0 402_5%

+CPU_CORE

C115

Pop: Prescott
Depop: Northwood

ITP_DBRESET#
ITP_TDO

ITP_TMS

ITP_TDI

ITP_TRST#

ITP_TCK

Place near CPU

1

1

+

+

2

2

H_RS#[0..2]<8>

H_TRDY#<8>

H_A20M#<25>

H_FERR#<25>

H_IGNNE#<25>

H_SMI#<25>

H_PWR GOOD<25>

H_STPCLK#<25>

H_INTR<25>

H_NMI<25>

H_INIT#<25>

H_RESET#<8,25>

H_DBSY#<8>

H_DRDY#<8>
CPU_CLKSEL0<13,23>
CPU_CLKSEL1<13,23>

H_THERMDA<7>
H_THERMDC<7>

H_THERMTRIP#<7>

R86 62_0402_5%

1 2

R96 62_0402_5%

1 2

R105 62_0402_5%

1 2

R82 62_0402_5%

1 2

R90 62_0402_5%

1 2

R100 62_0402_5%

1 2

H_VCCIOPLL

H_VCCA

C76
33U_D2_8M_R35

VCCSENSE<53>

VSSSENSE<53>

+VCCVID

H_VSSA

CK_ITP<23>

CK_ITP#<23>

CK_ITP
CK_ITP#

R23

51.1_ 0603_1%

+CPU_CORE

R_A

R_B

H_P WRGOOD

H_RESET#

1 2

R144

R370

0_0402_5%
1 2
1 2

R371

0_0402_5%

Prescott
Northwood

R388

49.9_0402_1%

R387
100_0402_1%

Prescott

Northwood

H_RS#0
H_RS#1
H_RS#2

H_FERR#

H_THERMDA
H_THERMDC

H_THERMTRIP#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

0_0402_5%

12

12

R139

51.1_ 0603_1%

COMP0 & COMP1

61.9_0603_1%

51.1_0603_1%

GTL Reference Voltage

Layout note :

R415 130_0402_5%

H_PROCHOT#

1 2

R54 300_0402_5%

D D

R38 62_0402_5%

C C

Note: Please change to 10uH, DC current
of 100mA parts and close to cap

B B

+CPU_CORE

+CPU_CORE

A A

H_PWRGOOD

1 2

H_RESET#

1 2

Note:H_FERR#,H_THERMTRIP#
pull-high in page25,page7

+CPU_CORE

L13 LQG21F4 R 7 N00_0805

1 2

33U_D2_8M_R35

1 2

L10 LQG21F4 R 7 N00_0805

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mils(min)

R390

54.9_ 0603_1%

1 2

R404

54.9_ 0603_1%

1 2

Between the CPU

R1024 47_0402_5%

1 2

R1025 150_0402_5%

1 2

R1026 680_0402_5%

1 2

R1027 47_0402_5%

1 2

Close to the CPU

5

R25

1 2

@0_0402_5%

AF26

VSS_128

SKTOCC#

DP#0
DP#1
DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

TESTHI9
TESTHI10
TESTHI11
TESTHI12

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

PROCHOT#

MCERR#

SLP#

NC1
NC2
NC3
NC4
NC5

VCCVID

AMP_3 - 1 565030-1_Pres cot t

+VCCVID

R_F

H_VID_PWRGD

J26
K25
K26
L25

AA21
AA6
F20
F6

AE26

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

E22
K22
R22
W22

F21
J23
P23
W23

L5
R5

E21
G25
P26
V21

AE25

C3
V6
AB26

A22
A7
AF25
AF24
AE21

R_E

R145

2.43K _0603_1%
1 2

CPUCLK_STP#<11,25,28,53>

R26 0_0402_5%

1 2

H_TEST HI 0
H_TEST HI 1

H_TEST HI 2_7

H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#

H_TESTHI12

ITP_DBRESET#

H_PROCHOT#

RE,RF
Pop: Pr es cott
Depop: No rt hwood

+VCCVID

+CPU_GTLREF

Pop: No rt hwood

R_G

R960 62_ 0402_5%
R53 62_0402_5%

R58 62_ 0402_5%

R417 62_ 0402_5%
R107 62_ 0402_5%
R114 62_ 0402_5%
R413 62_ 0402_5%
R51 62_ 0402_5%

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_ADSTB#0 <8>
H_ADSTB#1 <8>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_PROCHOT# <52>
H_C PUSLP# <25>

R194 200_0402_5%

1 2

Depop: Pr es cott

1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2

R_H

R414 0_0402_5%

1 2

+CPU_CORE

RH
Pop: Pr es cott
Depop: No rt hwood

+CPU_CORE

CP U_GHI# <26>

BOM update 7/10

+3VS

VID5

R113 1K _ 0 402_5%

VID5<53>
VID4<53>
VID3<53>

VID2<53>
VID1<53>
VID0<53>

R1008

1 2

4.7K_0402_5%

Level shift

1 2

VID4

R119 1K _ 0 402_5%

1 2

VID3
VID2
VID1
VID0

RP2 1K_1206_8P4R_5%

+3VS

2

4.7K_0402_5%
R109

2

Q5
MMBT3904_SOT23

3 1

45
36
27
18

CPU_STP#

Q6
MMBT3904_SOT23

3 1

Populate for Northwood

R37

1 2

0_0402_5%

1

H_DPSLP#

of

561星期T, 30, 2003

CPU_STP#

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

0E

5

4

3

2

1

+CPU_CORE

1

C113
22U_1 2 06_10V4Z

2

D D

+CPU_CORE

1

C65
22U_1 2 06_10V4Z

2

+CPU_CORE

1

C121
22U_1 2 06_10V4Z

2

C C

+CPU_CORE

1

C465
22U_1 2 06_10V4Z

2

1

C61
22U_1206_10V4Z

2

1

C70
22U_1206_10V4Z

2

1

C110
22U_1206_10V4Z

2

1

C460
22U_1206_10V4Z

2

1

C60
22U_1206_10V4Z

2

1

C82
22U_1206_10V4Z

2

1

C453
22U_1206_10V4Z

2

Place 11 North of Socket(Stuff 6)

1

C114
22U_1206_10V4Z

2

1

C491
22U_1206_10V4Z

2

1

2

Place 12 Inside Socket(Stuff all)

1

C93
22U_1206_10V4Z

2

1

C62
22U_1206_10V4Z

2

1

2

Place 9 South of Socket(Unstuff all)

1

C448
22U_1206_10V4Z

2

1

C445
22U_1206_10V4Z

2

1

2

C463
22U_1 2 06_10V4Z

C69
22U_1 2 06_10V4Z

C500
22U_1 2 06_10V4Z

1

C475
22U_1206_10V4Z

2

1

C81
22U_1206_10V4Z

2

1

C450
22U_1206_10V4Z

2

1

C474
22U_1206_10V4Z

2

22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)

1

C94
22U_1206_10V4Z

2

1

C441
22U_1206_10V4Z

2

1

C455
22U_1206_10V4Z

2

1

C111
22U_1206_10V4Z

2

1

C442
22U_1206_10V4Z

2

1

C43
22U_1206_10V4Z

2

1

C124
22U_1206_10V4Z

2

1

C462
22U_1 2 06_10V4Z

2

B B

+CPU_CORE

1

C39

+

@470U_D2_2.5VM

2

+CPU_CORE

1

C136

+

@470U_D2_2.5VM

2

+CPU_CORE

A A

1

C467

+

470U_D2_2.5VM

2

470uF _ERS10m ohm* 15

1

C90

+

@470U_D2_2.5VM

2

1

C495

+

@470U_D2_2.5VM

2

1

C466

+

470U_D2_2.5VM

2

5

1

C134

+

@470U_D2_2.5VM

2

1

C518

+

470U_D2_2.5VM

2

1

C516

+

470U_D2_2.5VM

2

1

C38

+

@470U_D2_2.5VM

2

1

C504

+

470U_D2_2.5VM

2

1

C519

+

@470U_D2_2.5VM

2

1

C91

+

@470U_D2_2.5VM

2

1

C443

+

470U_D2_2.5VM

2

1

C444

+

470U_D2_2.5VM

2

4

3

+CPU_CORE

0.1U_ 0 402_16V4Z

1

2

+CPU_CORE

0.1U_ 0 402_16V4Z

1

2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239

Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C106

C67

1

C123

2

0.1U_ 0 402_16V4Z

1

C45

2

0.1U_ 0 402_16V4Z

0.1U_0402_16V4Z

0.1U_ 0 402_16V4Z

1

2

1

2

C66

C48

@0.1U _0402_16V4Z

@0.1U _0402_16V4Z

1

C46

2

1

C122

2

2

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

661星期T, 30, 2003

5

4

3

2

1

Thermal Sensor ADM1032AR

+3VS

W=15mil

12

R501

D D

@10K_0402_5%

C590

2200P_0402_25V7K

1

2

H_THERMDA
H_THERMDC

THERM#

2

C580

1

0.1U_0402_16V4Z

1
2
3

U32

VDD

SCLK

D+

SDATA

ALERT#

D­THERM#4GND

ADM1032AR_SOP8

Address:1001_100X

R492

300_0402_5%

H_THERMTRIP#

+CPU_CORE

+CPU_CORE

R488 56_0402_5%

8
7
6
5

Q52

CBE

2SC2411K_SC59

123

H_THERMDA
H_THERMDC

C591 1U_0603_10V4Z

H_T HER MDA <5>
H_T HER MDC <5>

EC_SM C _2 <40>
EC_SM D _2 <40>

MAI N PWON <46,47,49>H_THERMTRIP#<5>

Fan Control circuitFan Control circuit

3

1

G

+5VS

6

2

D

S

4 5

FAN2_VOUT

1

C642

10U_0805_10V4Z

2

Q56

SI3456DV-T1_TSOP6

0.001U_0402_50V7M

0.001U_0402_50V7M

1

2

C640

C641

+5VS

1

2

12

R568
10K_0402_5%

JP27

1
2
3

53398-0390

0.1U_0402_16V4Z

EN_FAN1<40>EN_FAN2<40>

R542

13K_0603_1%

1 2

2

C635

1

1
3

1 2

R592 7.32K_0603_1%

RB751V_SOD323

+12VS

5

U39

P

+

FAN2_ON

4

O

-

G

LM321MF_SOT23-5

2

C653

1 2

@2200P_0603_16V7K

D20

2 1

C C

0.1U_0402_16V4Z

R583

13K_0603_1%

1 2

2

C613

1

1

+

3

-

1 2

R543 7.32K_0603_1%

RB751V_SOD323

+12VS

5

U36

P

FAN1_ON

4

O

G

LM321MF_SOT23-5

2

C614

1 2

@2200P_0603_16V7K

D19

2 1

3

1

G

+5VS

6

2

D

S

4 5

FAN1_VOUT

1

C637
10U_0805_10V4Z

2

Q55

SI3456DV-T1_TSOP6

0.001U_0402_50V7M

FANSPEED1<40>FANSPEED2< 40>

0.001U_0402_50V7M

1

2

C623

C633

+5VS

1

2

12

R541

10K_0402_5%

JP28

1
2
3

53398-0390

B B

A A

C

2222

1

3EB

2

SYMBOL(SOT23-NEW)

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Re v

Date: Sheet

Compal El e c t ronics, Inc.

SCHEMATIC , M/B LA-1861

401257

七月

1

0E

of

761星期T, 30, 2003

5

4

3

2

1

H_A#[3..31]
H_REQ# [0 ..4 ]

H_D#[0..63]

D D

H_ADSTB#0<5>

C C

H_ADSTB#1<5>

H_ADS#<4>

H_BNR#<4>

H_BPRI#<4>

H_DEFER#<4>

H_DRDY#<5>

H_DBSY#<5>

H_BR0#<4>

+1.8VS+1.8VS

R173

@1K_0402_5%

1 2
2

SUS_STAT#<16,26>

B B

3 1

Q12 @MMBT3904_SOT23

R1023

1 2

0_0402_5%

49.9_0402_1%

100_0402_1%

12

Layout & BOM update 7/10

R479
@1K_0402_5%

C823 0.1U_0402_16V4Z

R80 330_0805_1%

+CPU_CORE

+CPU_CORE

R136

R135

PLACE CLOSE TO U5 Ball
W28, USE 10/10
WIDTH/SPACE

C157
1U_0603_10V4Z

1 2

1 2

NB_RST#<11,16,25,38>

NB_PWRGD<42>

1 2

+1.8VS

L45

HB-1M2012-121JT03_0805

C164
220P_0402_50V9J

C587 CLOSE
TO Ball W28

H_LOCK#<4>

H_RESET#<5,25>

H_RS#2<5>
H_RS#1<5>
H_RS#0<5>

H_TRDY#<5>

H_HIT#<4>

H_HITM#<4>

SUS_STAT_R#

R132 24.9_0402_1%

1 2

R134 49.9_0402_1%

1 2

1

+

2

BOM update 7/10

NB_GTLREF

CPVDD

C822

C97
@1U_0603_10V4Z

@470U_D2_2.5VM

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#

H_RESET#
H_RS#2
H_RS#1
H_RS#0

H_TRDY#
H_HIT#
H_HITM#

COMP_N
COMP_P

M28

P25
M25
N29
N30
M26
N28

P29

P26
R29

P30

P28
N26
N27
M29
N25
R26

L28

L29
R27

U30

T30
R28
R25
U25

T28

V29

T26
U29
U26

V26

T25

V25
U27
U28

T29

L27

K25
H26

J27

L26
G27

F25

K26

A17
G25
G26

J25

F26

J26

H25

A9
AH5
AG5

C7

V28
W29
H23

J23

W28

Y29

Y28

B17

12

R76

4.7K_0402_5%

U11A

216RC300M_BGA_718

PART 1 OF 6

CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#

CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#

CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#

CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#

CPU_TRDY#
CPU_HIT#
CPU_HITM#

CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD

CPU_COMP_N
CPU_COMP_P
CPVDD
CPVSS
CPU_VREF

THERMALDIODE_N
THERMALDIODE_P

TESTMODE

ADDR. GROUP 1 ADDR. GROUP 0CONTROL

MISC.

DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3

CPU_DSTBN0#

CPU_DSTBP0#

CPU_DSTBN1#

AGTL+ I/F

CPU_DSTBP1#

PENTIUM

IV

CPU_DSTBN2#

CPU_DSTBP2#

CPU_DSTBN3#

CPU_DSTBP3#

H_A#[3..31] <4>
H_REQ#[0..4 ] <4>
H_D#[0..6 3 ] <4>

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#

CPU_DBI0#

CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#

CPU_DBI1#

CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#

CPU_DBI2#

CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_DBI3#

L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29

B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27

F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22

B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3

H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>

H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>

H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>

H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>

TESTMODE RS200 MODE
LOW

A A

5

4

HIGH

NORMAL MODE
TEST MODE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

of

861,

1

0E

5

4

3

2

1

As close as to DIMM

U11B

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4

D D

DDRA_SRAS#<14,15>
DDRA_SCAS#<14,15>

DDRA_SWE#<14,15>

C C

DDRA_CLK0<14>

DDRA_CLK0#<14>

DDRA_CLK1<14>

DDRA_CLK1#<14>

DDRA_CLK2<14>

DDRA_CLK2#<14>

DDRA_CLK3<14>

DDRA_CLK3#<14>

DDRA_CLK4<14>

DDRA_CLK4#<14>

DDRA_CLK5<14>

DDRA_CLK5#<14>

L47

B B

+1.8VS

1 2

HB-1M2012-121JT03_0805

DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_SRAS#
DDRA_SCAS#

DDRA_SWE#
DDRA_DQS0

DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7

DDRA_CLK0
DDRA_CLK0#

DDRA_CLK1
DDRA_CLK1#

DDRA_CLK2
DDRA_CLK2#

DDRA_CLK3
DDRA_CLK3#

DDRA_CLK4

DDRA_CLK4#

DDRA_CLK5
DDRA_CLK5#

DDRA_CKE0
DDRA_CKE1
DDRA_CKE2
DDRA_CKE3

DDRA_SCS#0
DDRA_SCS#1
DDRA_SCS#2
DDRA_SCS#3

C206
1U_0603_10V4Z

MPVDD

0.1U_0402_16V4Z

DDR_VREF

0.1U_0402_16V4Z

AH19

AJ17
AK17

AH16

AK16
AF17
AE18
AF16
AE17
AE16
AJ20

AG15

AF15
AE23

AH20

AE25

AH7
AF10
AJ14
AF21

AH23

AK28

AD29

AB26
AF24

AF25
AE24

AH13

AE21
AJ23
AJ27

AC28

AA25

AK10

AH10
AH18

AJ19

AG30
AG29

AK11
AJ11

AH17

AJ18
AF28

AG28

AF13
AE13

AG14

AF14

AH26
AH27

AF26

AG27
AC18

AD18

AJ8

AF9

PART 2 OF 6

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15

MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7

MEM_RAS#
MEM_CAS#

MEM_WE#
MEM_DQS0

MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7

MEM_CK0
MEM_CK0#

MEM_CK1
MEM_CK1#

MEM_CK2
MEM_CK2#

MEM_CK3
MEM_CK3#

MEM_CK4
MEM_CK4#

MEM_CK5
MEM_CK5#

MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3

MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3

MPVDD

MPVSS

216RC300M_BGA_718

2

C203

1

DDR_VREF

2

C202

1

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38

MEM I/F

MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

MEM_CAP1
MEM_CAP2

MEM_COMP

MEM_DDRVREF

+2.5V+2.5V

12

R176
1K_0603_1%

12

R175
1K_0603_1%

DDRA_DQ0

AG6

DDRA_DQ1

AJ7

DDRA_DQ2

AJ9

DDRA_DQ3

AJ10

DDRA_DQ4

AJ6

DDRA_DQ5

AH6

DDRA_DQ6

AH8

DDRA_DQ7

AH9

DDRA_DQ8

AE7

DDRA_DQ9

AE8

DDRA_DQ10

AE12

DDRA_DQ11

AF12

DDRA_DQ12

AF7

DDRA_DQ13

AF8

DDRA_DQ14

AE11

DDRA_DQ15

AF11

DDRA_DQ16

AJ12

DDRA_DQ17

AH12

DDRA_DQ18

AH14

DDRA_DQ19

AH15

DDRA_DQ20

AH11

DDRA_DQ21

AJ13

DDRA_DQ22

AJ15

DDRA_DQ23

AJ16

DDRA_DQ24

AF18

DDRA_DQ25

AG20

DDRA_DQ26

AG21

DDRA_DQ27

AF22

DDRA_DQ28

AF19

DDRA_DQ29

AF20

DDRA_DQ30

AE22

DDRA_DQ31

AF23

DDRA_DQ32

AJ21

DDRA_DQ33

AJ22

DDRA_DQ34

AJ24

DDRA_DQ35

AK25

DDRA_DQ36

AH21

DDRA_DQ37

AH22

DDRA_DQ38

AH24

DDRA_DQ39

AJ25

DDRA_DQ40

AK26

DDRA_DQ41

AK27

DDRA_DQ42

AJ28

DDRA_DQ43

AH29

DDRA_DQ44

AH25

DDRA_DQ45

AJ26

DDRA_DQ46

AJ29

DDRA_DQ47

AH30

DDRA_DQ48

AF29

DDRA_DQ49

AE29

DDRA_DQ50

AB28

DDRA_DQ51

AA28

DDRA_DQ52

AE28

DDRA_DQ53

AD28

DDRA_DQ54

AC29

DDRA_DQ55

AB29

DDRA_DQ56

AC26

DDRA_DQ57

AB25

DDRA_DQ58

Y26

DDRA_DQ59

W26

DDRA_DQ60

AE26

DDRA_DQ61

AD26

DDRA_DQ62

AA26

DDRA_DQ63

Y27

C205 0.47U_0603_16V7K

AF6

1 2

C167 0.47U_0603_16V7K

AA29

1 2

R174 49.9_0402_1%

AK19

1 2

AK20

DDRA_SDM[0..7]

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_SMA[0..15]

DDRA_CKE[0..3]

DDRA_SCS#[0..3]

DDRA_SDM[0..7] <14,15>

DDRA_SDQ[0..63] <14,15>

DDRA_SDQS[0..7] <14,15>

DDRA_SMA[0..15] <14,15>

DDRA_CKE[0..3] <14,15>

DDRA_SCS#[0..3] <14,15>

DDRA_DQ7
DDRA_DQ0
DDRA_DM0
DDRA_DQ5

DDRA_DQ4
DDRA_DQ6
DDRA_DQ1
DDRA_DQ2

DDRA_DQ3
DDRA_DQS0

DDRA_DQ9
DDRA_DQ8
DDRA_DQ14
DDRA_DM1

DDRA_DQ12
DDRA_DQ13
DDRA_DQ10
DDRA_DQS1

DDRA_DQ15
DDRA_DQ11

DDRA_DQ20
DDRA_DQS2 DDRA_SDQS2
DDRA_DQ17
DDRA_DQ16

DDRA_DQ21 DDRA_SDQ21
DDRA_DQ18
DDRA_DM2
DDRA_DQ22

DDRA_DQ23 DDRA_SDQ23

DDRA_DQ30
DDRA_DQ27
DDRA_DQ28

DDRA_DQ24
DDRA_DQ25
DDRA_DQ29

DDRA_DQ26
DDRA_DQ31

RP70

0_0804_8P4R_5%
RP69

0_0804_8P4R_5%

RP68

0_0804_8P4R_5%
RP67

0_0804_8P4R_5%

RP80

0_0804_8P4R_5%

RP79

0_0804_8P4R_5%

RP82

0_0804_8P4R_5%

RP81

0_0804_8P4R_5%

DDRA_SDQ7
DDRA_SDQ0
DDRA_SDM0
DDRA_SDQ5

DDRA_SDQ4
DDRA_SDQ6
DDRA_SDQ1
DDRA_SDQ2

DDRA_SDQ3
DDRA_SDQS0

DDRA_SDQ9
DDRA_SDQ8
DDRA_SDQ14
DDRA_SDM1

DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQS1

DDRA_SDQ15
DDRA_SDQ11

DDRA_SDQ20
DDRA_SDQ17

DDRA_SDQ16

DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ19DDRA_DQ19

DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQS3DDRA_DQS3

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDM3DDRA_DM3

DDRA_SDQ26
DDRA_SDQ31

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R621 0_0402_5%
R620 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R619 0_0402_5%
R618 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R630 0_0402_5%
R633 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R632 0_0402_5%
R631 0_0402_5%

DDRA_DQ33
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37

DDRA_DQS4
DDRA_DQ34
DDRA_DM4
DDRA_DQ38

DDRA_DQ39
DDRA_DQ35

DDRA_DQ40
DDRA_DQ45
DDRA_DQ44
DDRA_DQS5

DDRA_DQ41
DDRA_DQ42
DDRA_DQ46
DDRA_DM5

DDRA_DQ47
DDRA_DQ43

DDRA_DQ53
DDRA_DQ52
DDRA_DM6 DDRA_SDM6
DDRA_DQS6

DDRA_DQ54
DDRA_DQ49
DDRA_DQ48
DDRA_DQ50

DDRA_DQ55
DDRA_DQ51

DDRA_DQ60
DDRA_DQ61

DDRA_DQ56

DDRA_DQS7
DDRA_DQ62
DDRA_DM7
DDRA_DQ63

DDRA_DQ59

RP78

0_0804_8P4R_5%
RP77

0_0804_8P4R_5%

RP76

0_0804_8P4R_5%
RP75

0_0804_8P4R_5%

RP74

0_0804_8P4R_5%

RP73

0_0804_8P4R_5%

RP72

0_0804_8P4R_5%

RP71

0_0804_8P4R_5%

DDRA_SDQ33
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ35

DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ44
DDRA_SDQS5

DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ46
DDRA_SDM5

DDRA_SDQ47
DDRA_SDQ43

DDRA_SDQ53
DDRA_SDQ52

DDRA_SDQS6

DDRA_SDQ54
DDRA_SDQ49
DDRA_SDQ48
DDRA_SDQ50

DDRA_SDQ55
DDRA_SDQ51

DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ57DDRA_DQ57
DDRA_SDQ56

DDRA_SDQS7
DDRA_SDQ62
DDRA_SDM7
DDRA_SDQ63

DDRA_SDQ58DDRA_DQ58
DDRA_SDQ59

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R629 0_0402_5%
R628 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R627 0_0402_5%
R626 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R625 0_0402_5%
R624 0_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R623 0_0402_5%
R622 0_0402_5%

DDR_VREF trace width of
12mils and space

A A

5

12mils(min)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

961,

1

5

A_PAR<13,25>

A_ACAT#<25>

A_END#<25>

A_OFF#<25>

RA

1 2

R122
169_0402_1%

1 2

R947
M9@71.5_0402_1%

A_AD[0..31]
A_CBE#[0..3]

A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31

A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3

A_PAR
A_STROBE#
A_ACAT#
A_END#

R969 0_0402_5%

1 2

A_DEVSEL#
A_OFF#

A_SBREQ#
A_SBGNT#

A_REQ#0

New add

AGP_GNT#
AGP_REQ#

C149

1 2

0.1U_0402_16V4Z
AGP_COMP

8X

169_0402_1%

324_0603_1%1K_0603_1%
100_0603_1%

U11C

AK5

ALINK_AD0

AJ5

ALINK_AD1

AJ4

ALINK_AD2

AH4

ALINK_AD3

AJ3

ALINK_AD4

AJ2

ALINK_AD5

AH2

ALINK_AD6

AH1

ALINK_AD7

AG2

ALINK_AD8

AG1

ALINK_AD9

AG3

ALINK_AD10

AF3

ALINK_AD11

AF1

ALINK_AD12

AF2

ALINK_AD13

AF4

ALINK_AD14

AE3

ALINK_AD15

AE4

ALINK_AD16

AE5

ALINK_AD17

AE6

ALINK_AD18

AC2

ALINK_AD19

AC4

ALINK_AD20

AB3

ALINK_AD21

AB2

ALINK_AD22

AB5

ALINK_AD23

AB6

ALINK_AD24

AA2

ALINK_AD25

AA4

ALINK_AD26

AA5

ALINK_AD27

AA6

ALINK_AD28

Y3

ALINK_AD29

Y5

ALINK_AD30

Y6

ALINK_AD31

AG4

ALINK_CBE#0

AE2

ALINK_CBE#1

AC3

ALINK_CBE#2

AA3

ALINK_CBE#3

AD5

PCI_PAR/ALINK_NC

AC6

PCI_FRAME#/ALINK_STROBE#

AC5

PCI_IRDY#/ALINK_ACAT#

AD2

PCI_TRDY#/ALINK_END#

W4

INTA#

AD3

ALINK_DEVSEL#

AD6

PCI_STOP#/ALINK_OFF#

W5

ALINK_SBREQ#

W6

ALINK_SBGNT#

V5

PCI_REQ#0/ALINK_NC

V6

PCI_GNT#0/ALINK_NC

K5

AGP2_GNT#/AGP3_GNT

K6

AGP2_REQ#/AGP3_REQ

M5

AGP8X_DET#

J6

AGP_VREF/TMDS_VREF

J5

AGP_COMP

216RC300M_BGA_718

A_AD[0..31]<13,25>

A_CBE#[0..3]<25>

D D

C C

PCI_PIRQA#<16,25,30,33,44>

+1.5VS

+1.8VS

R1005
@4.7K_0402_5%

RB

?

B B

A A

RC

1 2

R125
100_0603_1%

1 2

RA

RB
RC

R121

324_0603_1%

4X

169_0402_1% //

71.5_0402_1%

1K_0603_1%

A_STROBE#<25>

A_DEVSEL#<25>

1 2

+3VS

R131

8.2K_0402_5%

AGP_REQ#<16>

AGP8X_DET#<16>

AGPREF_8X

PLACE CLOSE TO
CONNECTOR

+1.5VS

A_SBREQ#<25>
A_SBGNT#<25>

AGP_GNT#<16>

4

PART 3 OF 6

PCI Bus 0 / A-Link I/F

AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC

AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC

AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON

AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK

AGP2_CBE#0/AGP3_CBE0/TMD2_D7

AGP2_CBE#1/AGP3_CBE1/TMD2_DE

AGP2_CBE#2/AGP3_CBE2

AGP2_CBE#3/AGP3_CBE3/TMD1_D5

AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK

AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK

AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA

AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA

AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA

PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)

AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#

AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON

AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#

AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#

AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT

AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN

AGP2_PIPE#/AGP3_DBI_HI

AGP2_NC/AGP3_DBI_LO
AGP2_WBF#/AGP3_WBF

AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9

AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10

AGP_AD13
AGP_AD14
AGP_AD15

AGP_AD18/TMD1_DE

AGP_AD19/TMD1_D0

AGP_AD20/TMD1_D1

AGP_AD21/TMD1_D2

AGP_AD22/TMD1_D3

AGP_AD23/TMD1_D4

AGP_AD24/TMD1_D7

AGP_AD25/TMD1_D6

AGP_AD26/TMD1_D9

AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10

AGP_AD30/TMDS_HPD

AGP_AD31

AGP_PAR

AGP2_RBF#/AGP3_RBF

AGP_ST0
AGP_ST1
AGP_ST2

3

Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1

E5
E6
T3
U2
G3
H2

R3
M1
L3
H1

P5
R6
T6
T5
P6
R5
C1
D3
N6
N5

C3
C2
D4
E4
F6
F5
G6
G5

L6
M6
L5

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_SBSTBF
AGP_SBSTBS
AGP_ADSTBF_0
AGP_ADSTBS_0
AGP_ADSTBF_1
AGP_ADSTBS_1

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI
AGP_DBI_LO
AGP_RBF#
AGP_WBF#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

BOM update 7/18 for EMI

AGP_SBSTBF <16>
AGP_SBSTBS <16>
AGP_ADSTBF_0 <16>
AGP_ADSTBS_0 <16>
AGP_ADSTBF_1 <16>
AGP_ADSTBS_1 <16>

AGP_IRDY# <16>
AGP_TRDY# <16>
AGP_STOP# <16>
AGP_PAR <16>
AGP_FRAME# <16>
AGP_DEVSEL# <16>
AGP_DBI_HI <16>
AGP_DBI_LO <16>
AGP_RBF# <16>
AGP_WBF# <16>

BOM update 7/18 for EMI

@10U_0805_6.3V6M

C133

@10K_0402_5%

@10K_0402_5%

2

AGPAND LVDS MUXED SIGNALS

AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5

AGP_SBA7 LVDS_SSIN

R103 M9@0_0402_5%

1 2

R106 M9@0_0402_5%

1 2

R382 M9@0_0402_5%

1 2

R381 M9@0_0402_5%

1 2

R118 @0_0402_5%

1 2

R112 @0_0402_5%

1 2

For integrated graphics

AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]

M9@2.2K_0402_5%

AGP_SBA0

R958 M9@0_0402_5%

AGP_SBA1

@0.1U_0402_16V4Z

C137

12

R116

12

R120

12

12

Note: P L AC E CLOSE TO (NB RC30 0M)

1 2

R959 M9@0_0402_5%

1 2

SST Ratio Selection Table For SM560

Input Freq.
Range

60~70MHz
70~80MHz
80~100MHz

S1=1
S0=M S0=1

2.5%

2.4%

2.3%

2.0%

1.8%100~108MHz

"1"= Pull-Up ; "0"= Pull-Down ;
"M"= Pull-up & Pull-Down

2

R111
@10K_0402_5%

R108
@10K_0402_5%

U9

1

X1/CLK

S0

7

S0

6

S1

S1

@SM560BS_SOIC8

LVDS SPREAD SPECTRUM

VDD
SSCLK

GND

3

Xout

SSCC

ENABLT# <16,24,40>
ENAVDD <16,24>
AGP_STP# <16,26>
AGP_BUSY# <16,26>

LVDS_SSOUTAGP_SBA6

AGP_AD[0..31] <16>
AGP_SBA[0..7] <16>
AGP_CBE#[0..3] <16>
AGP_ST[0..2] <16>

R963

S1=0 S1=1
S0=1

1.8%

1.6%

1.4%

1.3%

L16
@BLM21P300S_0805

1 2

12

R124
@0_0402_5%

4

8
5

12

R129
@0_0402_5%

1

+3VS

R964
M9@2.2K_0402_5%

NB_I2CCLK <24>
NB_I2CDATA <24>

S1=M

S0=1

1.2%

1.1%

1.1%

1.0%

0.8%

1.0%1.9%

0.9%

0.9%

0.8%

0.6%

BOM up date 7/18 for EMI

+3VS

1 2

1

2

R117

@22_0402_5%
C148
@10P_0402_50V8K

LVDS_SSIN

LVDS_SSOUTSSOUT_IN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

1

星期三 七月

0E

of

10 61,

5

4

3

2

1

D D

L59

1 2

FBM-11-160808-121-T_0603

1

C525

0.1U_0402_16V4Z

+2.5VS

L60

1 2

KC FBM-L11-201209-221LMAT_0805

Note: P L AC E CLOS E TO (NB CHI P)

CRT_R

R71 M9@0_0402_5%

CRT_R<16,24,43>
CRT_G<16,24,43>

CRT_B<16,24,43>

CRT_HSYNC<16,24>
CRT_VSYNC<16,24>

C C

CRMA_R
LUMA_R TV_LUMA

DDCCLK_R
DDCDATA_R

1 2

R67 M9@0_0402_5%

1 2

CRT_B BLUE_R

R63 M9@0_0402_5%

1 2

CRT_HSYNC

R363 M9@0_0402_5%

CRT_VSYNC

1 2

R361 M9@0_0402_5%

1 2

R72 M9@0_0402_5%

1 2

R62 M9@0_0402_5%

1 2

R68 M9@0_0402_5%

1 2

R365 M9@0_0402_5%

1 2

R368 M9@0_0402_5%

1 2

RED_R
GREEN_RCRT_G

TV_CRMA
TV_COMPSCOMPS_R

3VDDCCL
3VDDCDA

HSYNC_R
VSYNC_R

+1.8VS

KC FBM-L11-201209-221LMAT_0805

TV_CRMA <16,24,43>
TV_LUMA <16,24,43>
TV_COMPS <16,24>

3VDDCCL <16,24>
3VDDCDA <16,24>

REFCLK1_NB<23>

Note: PLACE CLOSE TO (NB CHIP)

RC300M_X1

R91

RC300M_X2

B B

@1M_0402_1%

@18P_0402_50V8K

12

C95
Y2
@14.31818MHZ_20P_6X1430004201

C119

@18P_0402_50V8K

CLK_AGP_66M CLK_MEM_66M

12

R395
10_0402_5%

C464
15P_0402_50V8D

12

R101
10_0402_5%

C127
15P_0402_50V8D

L61

1 2

+1.8VS

1 2

KC FBM-L11-201209-221LMAT_0805

0.1U_0402_16V4Z

+1.8VS

KC FBM-L11-201209-221LMAT_0805

R84 0_0402_5%

R88
68_0603_1%

+3VS

1

C75
@0.1U_0402_16V4Z

2

1

2

L62

1 2

10U_0805_10V4Z

X2

4

VDD

1

OE

@27MHZ_15P

C86

0.1U_0402_16V4Z

1

1

L63

OUT
GND

2

C92

R75

3
2

C481

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C482

+3VS

Layout & BOM update 7/10

1

2

1

1

C102

2

2

1 2
715_0402_1%

CLK_NB_BCLK<23>

CLK_NB_BCLK#<23>

CLK_AGP_66M<23>

CLK_MEM_66M<23>

R1055

4.7K_0402_5%

R73 @22_0402_5%

C104

0.1U_0402_16V4Z

C103 0.1U_0402_16V4Z

RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R

NB_RSET

RC300M_X1
RC300M_X2

CLK_NB_BCLK
CLK_NB_BCLK#

CLK_AGP_66M
CLK_MEM_66M

27M_TV_R27M_TV

2

U11D

G9

VDDR3

H9

VDDR3

A14

AVDD_25

B13

AVSSN

B14

AVDDDI_18

C13

AVSSDI

A15

AVDDQ

B15

AVSSQ

H11

PLLVDD_18

G11

PLLVSS

F14

RED

F15

GREEN

E14

BLUE

C8

DACHSYNC

D9

DACVSYNC

C14

RSET

A4

XTALIN

B4

XTALOUT

A5

HCLKIN

B5

HCLKIN#

B6

SYS_FBCLKOUT

A6

SYS_FBCLKOUT#

D8

ALINK_CLK

B2

AGPCLKOUT

B3

AGPCLKIN

A3

EXT_MEM_CLK

D7

USBCLK

B7

REF27

C5

OSC

216RC300M_BGA_718

+3VS

PART 4 OF 6

LVDS

CRT

CLK. GEN.

TXOUT_U0N

TXOUT_U0P

TXOUT_U1N

TXOUT_U1P

TXOUT_U2N

TXOUT_U2P

TXCLK_UN
TXCLK_UP

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P

TXCLK_LN
TXCLK_LP

LPVDD_18

LPVSS

LVDDR_18
LVDDR_18

LVSSR
LVSSR

COMP_B

SVID

DACSCL
DACSDA

CPUSTOP#

SYSCLK

SYSCLK#

C_R
Y_G

D12
E12
F11
F12
D13
D14
E13
F13

E10
D10
B9
C9
D11
E11
B10
C10

A12
A11

B12
C12

B11
C11

CRMA_R

E15

LUMA_R

C15

COMPS_R

D15

DDCCLK_R

D6

DDCDATA_R

C6

D5

R401 @0_0402_5%
A8
B8

BOM update 6/16

TXB0-_NB <24>
TXB0+_NB <24>
TXB1-_NB <24>
TXB1+_NB <24>
TXB2-_NB <24>
TXB2+_NB <24>
TXBCLK-_NB <24>
TXBCLK+_NB <24>

TXA0-_NB <24>
TXA0+_NB <24>
TXA1-_NB <24>
TXA1+_NB <24>
TXA2-_NB <24>
TXA2+_NB <24>
TXACLK-_NB <24>
TXACLK+_NB <24>

+1.8VS_LPVDD

+1.8VS_LVDDR

@2N7002_SOT23

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

S

Q47

D

1 3

0.1U_0402_16V4Z

1

C73

C74

2

1

C484

C483

2

G

2

R402

4.7K_0402_5%

+1.8VS

R70

1 2

KC FBM-L11-201209-221LMAT_0805

C68
10U_0805_10V4Z

+1.8VS

R399

1 2

KC FBM-L11-201209-221LMAT_0805

C468
10U_0805_10V4Z

CPUCLK_STP# <5,25,28,53>

NB_RST# <8,16,25,38>

+3VS

CPUSTOP# <23>

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

11 61,

1

5

4

3

2

1

+1.5VS +2.5V

D D

C C

+CPU_CORE

+3VS

B B

U11E

F10

VDD_CORE

F9

VDD_CORE

G12

VDD_CORE

H12

VDD_CORE

H13

VDD_CORE

M12

VDD_CORE

M13

VDD_CORE

M14

VDD_CORE

M17

VDD_CORE

M18

VDD_CORE

M19

VDD_CORE

N12

VDD_CORE

N13

VDD_CORE

N14

VDD_CORE

N17

VDD_CORE

N18

VDD_CORE

N19

VDD_CORE

P12

VDD_CORE

P13

VDD_CORE

P14

VDD_CORE

P17

VDD_CORE

P18

VDD_CORE

P19

VDD_CORE

U12

VDD_CORE

U13

VDD_CORE

U14

VDD_CORE

U17

VDD_CORE

U18

VDD_CORE

U19

VDD_CORE

V12

VDD_CORE

V13

VDD_CORE

V14

VDD_CORE

V17

VDD_CORE

V18

VDD_CORE

V19

VDD_CORE

W12

VDD_CORE

W13

VDD_CORE

W14

VDD_CORE

W17

VDD_CORE

W18

VDD_CORE

W19

VDD_CORE

C16

VDDR2_CPU

D16

VDDR2_CPU

D17

VDDR2_CPU

E16

VDDR2_CPU

E17

VDDR2_CPU

F16

VDDR2_CPU

F17

VDDR2_CPU

G17

VDDR2_CPU

G21

VDDR2_CPU

G23

VDDR2_CPU

G24

VDDR2_CPU

H16

VDDR2_CPU

H17

VDDR2_CPU

H19

VDDR2_CPU

H21

VDDR2_CPU

H24

VDDR2_CPU

K23

VDDR2_CPU

K24

VDDR2_CPU

M23

VDDR2_CPU

P23

VDDR2_CPU

P24

VDDR2_CPU

T23

VDDR2_CPU

T24

VDDR2_CPU

U23

VDDR2_CPU

U24

VDDR2_CPU

W30

VDDR2_CPU

AA1

VDDL_ALINK

AA7

VDDL_ALINK

AA8

VDDL_ALINK

AC7

VDDL_ALINK

AC8

VDDL_ALINK

AD1

VDDL_ALINK

AD7

VDDL_ALINK

AD8

VDDL_ALINK

AK3

VDDL_ALINK

W8

VDDL_ALINK

216RC300M_BGA_718

PART 5 OF 6

CORE PWR

CPU I/F PWRALINK PWR

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

MEM I/F PWR

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

POWER

VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM

VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP

AGP PWR

VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP

VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33

VDD_18
VDD_18
VDD_18
VDD_18

AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25

A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6

E7
F7
G8

AC22
AC9
H10
H22

+1.5VS

+1.8VS

R104
M9+/M10@0_0805_5%

1 2

1 2

R102
M9@0_0805_5%

+1.5VS

+3VS

U11F

PART 6 OF 6

A29

VSS

AB23

VSS

AB24

VSS

AB27

VSS

AB4

VSS

AB8

VSS

AC1

VSS

AC11

VSS

AC14

VSS

AC16

VSS

AC20

VSS

AC30

VSS

AD11

VSS

AD14

VSS

AD16

VSS

AD20

VSS

AD4

VSS

AE27

VSS

AF30

VSS

AF5

VSS

AG10

VSS

AG13

VSS

AG16

VSS

AG19

VSS

AG22

VSS

AG25

VSS

AG7

VSS

AH28

VSS

AH3

VSS

AJ1

VSS

AK13

VSS

AK2

VSS

AK22

VSS

AK29

VSS

AK4

VSS

AK7

VSS

B1

VSS

B16

VSS

B30

VSS

C19

VSS

C23

VSS

C27

VSS

C4

VSS

D21

VSS

D25

VSS

E3

VSS

E8

VSS

E9

VSS

F27

VSS

F4

VSS

F8

VSS

G14

VSS

G15

VSS

G18

VSS

G20

VSS

H14

VSS

H15

VSS

H18

VSS

H20

VSS

H27

VSS

H4

VSS

H8

VSS

J7

VSS

216RC300M_BGA_718

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

For external AGP/1.5V GPIO

For 3.3V GPIO

R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8

C531

47U_B_6.3VM

C176

47U_B_6.3VM

@0.1U_0402_16V4Z

C89

47U_B_6.3VM

C161

47U_B_6.3VM

C150

47U_B_6.3VM

+CPU_CORE

1

+

2

+2.5V

1

+

2

+2.5V

1

2

+1.8VS

1

+

2

+3VS

1

+

2

+1.5VS

22U_1206_10V4Z

1

+

2

0.1U_0402_16V4Z

1

C539

2

0.1U_0402_16V4Z

47U_B_6.3VM

1

+

C181

2

0.1U_0402_16V4Z

@0.1U_0402_16V4Z

1

C587

C576

2

@0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C98

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C183

2

0.1U_0402_16V4Z

1

C135

2

0.1U_0402_16V4Z

1

C151

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C200

2

@0.1U_0402_16V4Z

1

C198

2

0.1U_0402_16V4Z

1

C99

2

0.1U_0402_16V4Z

1

C524

2

0.1U_0402_16V4Z

1

C566

2

0.1U_0402_16V4Z

1

C544

2

1

C169

2

0.1U_0402_16V4Z

1

C201

2

1

C582

2

0.1U_0402_16V4Z

1

C564

2

0.1U_0402_16V4Z

1

C546

2

0.1U_0402_16V4Z

1

C555

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C180

2

1

C521

2

0.1U_0402_16V4Z

1

C568

2

0.1U_0402_16V4Z

1

C561

2

0.1U_0402_16V4Z

1

C559

2

1

C182

2

0.1U_0402_16V4Z

1

C589

2

0.1U_0402_16V4Z

1

C567

2

0.1U_0402_16V4Z

1

C523

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C588

2

0.1U_0402_16V4Z

1

C177

2

0.1U_0402_16V4Z

1

C545

2

0.1U_0402_16V4Z

1

C31

2

1

C581

2

0.1U_0402_16V4Z

1

C577

2

0.1U_0402_16V4Z

1

C560

2

0.1U_0402_16V4Z

1

C522

2

@0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C585

2

0.1U_0402_16V4Z

1

C173

2

0.1U_0402_16V4Z

1

C549

2

1

C532

2

1

2

1

2

1

2

0.1U_0402_16V4Z

1

C583

C570

2

0.1U_0402_16V4Z

1

C562

C558

2

0.1U_0402_16V4Z

1

C538

C557

2

0.1U_0402_16V4Z

1

C586

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C810

2

0.1U_0402_16V4Z

1

C584

2

0.1U_0402_16V4Z

1

C811

2

0.1U_0402_16V4Z

1

C575

2

0.1U_0402_16V4Z

1

C812

2

1

C563

2

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1861

30, 2003

401257

星期三 七月

0E

of

12 61,

1

5

4

3

2

1

A_AD[0..31]<10,25>

A_AD31

R473 4.7K_0402_5%

D D

C C

A_AD30

R502 4.7K_0402_5%

A_AD29

A_AD28

A_AD27

A_AD26

A_AD17

R147 10K_0402_5%

R489 10K_0402_5%

R475 4.7K_0402_5%
R476 @4.7K_0402_5%

R481 @4.7K_0402_5%
R148 4.7K_0402_5%

R503 4.7K_0402_5%
R161 @4.7K_0402_5%

R149 4.7K_0402_5%
R482 @4.7K_0402_5%

R151 4.7K_0402_5%
R150 @4.7K_0402_5%

2 1
D32
RB751V_SOD323

2 1
D33
RB751V_SOD323

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

CPU_CLKSEL1 <5,23>

+3VS

CPU_CLKSEL0 <5,23>

A_AD[31..30] : FSB CLK SPEED

DEFAULT: 01
00: 100 MHZ

01: 133 MHZ
10: 200MHZ
11: 166 MHZ

A_AD2 9: STRAP CONFIGURATION

DEFAULT:1
0: REDUCEDE SET

1: FULL SET

A_AD28: SPREAD SPECTRUM ENABLE

DEFAULT:0
0: DISABLE

1: ENABLE

A_AD27 : Fr cShortReset#

DEFAULT: 1
0: TEST MODE

1: NORMAL MODE

A_AD26 : ENABLE IOQ

DEFAULT: 1
0: IOQ=1

1: IOQ=12

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

A_CBE#[0..3]<10,25>

A_AD[0..31]
A_CBE#[0..3]

A_AD18

A_PAR<10,25>

R487 @4.7K_0402_5%
R478 4.7K_0402_5%

R953 4.7K_0402_5%

A_PAR

R480 @4.7K_0402_5%

+3VS

+3VS

A_AD1 8 : ENABLE PHASE CAL IBRATION

DEFAULT: 0
0: ENABLE

1: DISABLE

PAR: EXTENDED DEBUG MODE

DEFAULT : 1
0: DEBUG MODE

1: NORMAL

DEFAULT: 00
00: 1.05V

01: 1.35V
11: 1.75V
10: 1.45V

A_AD25

R510 @4.7K_0402_5%
R163 4.7K_0402_5%

+3VS

A_AD24

B B

A_AD23

A_AD22

R512 4.7K_0402_5%

R490 4.7K_0402_5%
R153 @4.7K_0402_5%

R166 4.7K_0402_5%

+3VS

+3VS

A_AD2 4 : M OBILE CPU SELECT

DEFAULT: 1
0: BANIAS CPU

1: OTH ER CPU

A_AD2 3 : C L OCK BYPASS DISABLE

DEFAULT: 1
0: TEST MODE

1: NORMAL

A_AD22 : OSC PAD OUTPUT PCICLK

DEFAULT : 1
0: OSC CLK OUT

1: PCICLK OUT

A_AD21

A A

A_AD20

R158 4.7K_0402_5%
R160 @4.7K_0402_5%

R494 @4.7K_0402_5%
R157 4.7K_0402_5%

5

+3VS

+3VS

A_AD2 1 : A UTO_CAL ENABLE

DEFAULT : 1
0: DISABLE

1: ENABLE

A_AD20 : INTERNAL CLK GEN ENABLE

DEFAULT : 0
0: DISABLE

1: ENABLE

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

of

13 61,

1

0E

5

4

3

2

1

R673
1K_0603_1%

R672
1K_0603_1%

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..15]
DDRA_SDM[0..7]

DDRA_SCS#2 <9,15>
DDRA_SCS#3 <9,15>

DDRA_CKE2 <9,15>
DDRA_CKE3 <9,15>

+2.5V

JP10

1

VREF

3
DDRA_SDQ7
DDRA_SDQ5 DDRA_SDQ4

DDRA_SDQS0
DDRA_SDQ6

DDRA_SDQ2 DDRA_SDQ3

DDRA_SDQ14
DDRA_SDQS1

DDRA_SDQ13

DDRA_CLK0<9>

DDRA_CLK0#<9>

DDRA_CLK2<9>

DDRA_CLK2#<9>

DDRA_CKE1<9,15> DDRA_CKE0 <9,15>

DDRA_SWE#<9,15>

DDRA_SCS#0<9,15>

SMB_CK_DAT1<23,26>

SMB_CK_CLK1<23,26>

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ19 DDRA_SDQ23
DDRA_SDQ30

DDRA_SDQ28
DDRA_SDQS3

DDRA_SDQ25
DDRA_SDQ26

DDRA_CKE1 D DRA_CKE0
DDRA_SMA12

DDRA_SMA9
DDRA_SMA7

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1 DDRA_SMA0

DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#0
DDRA_SMA15

DDRA_SDQ33
DDRA_SDQ32

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDQ44
DDRA_SDQS5

DDRA_SDQ42
DDRA_SDQ47

DDRA_SDQ53 DDRA_SDQ52
DDRA_SDQ54

DDRA_SDQS6
DDRA_SDQ48

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ57
DDRA_SDQS7

DDRA_SDQ62 DDRA_SDQ63
DDRA_SDQ58

SMB_CK_DAT1
SMB_CK_CLK1

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP1565711-1_STANDARD 4.0

DIMM0

STANDARD

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

A11

A8

VSS

A6
A4
A2

A0
VDD
BA1

S1#

DU

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD
CK1

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD
SA0
SA1
SA2

DU

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ0

DDRA_SDM0
DDRA_SDQ1

DDRA_SDQ8DDRA_SDQ9
DDRA_SDQ12

DDRA_SDM1
DDRA_SDQ10

DDRA_SDQ11

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ27
DDRA_SDQ24

DDRA_SDM3
DDRA_SDQ29

DDRA_SDQ31

DDRA_SMA11
DDRA_SMA8

DDRA_SMA6
DDRA_SMA4
DDRA_SMA2

DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ45

DDRA_SDQ41
DDRA_SDM5

DDRA_SDQ46
DDRA_SDQ43

DDRA_SDQ49
DDRA_SDM6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ61
DDRA_SDQ56

DDRA_SDM7

DDRA_SDQ59

0.1U_ 0 402_16V4Z

C831

0.1U_ 0 402_16V4Z

DDRA_SRAS# <9,15>
DDRA_SCAS# <9,15>
DDRA_SCS#1 <9,15>

DDRA_CLK1# <9>
DDRA_CLK1 <9>

+2.5V

2

C235

1

2

2

C233

1

1

0.1U_ 0 402_16V4Z

DDRA_VREF trace width of
20mils and space
20mils(min)

DDRA_SDQ[0..63]<9,15>
DDRA_SDQS[0..7]<9,15>
DDRA_SMA[0..15]<9,15>

DDRA_SDM[0..7]<9,15>

D D

DDRA_CLK3<9>

DDRA_CLK3#<9>

C C

DDRA_CLK5<9>

DDRA_CLK5#<9>

B B

A A

+2.5V

JP29

1

VREF

3
DDRA_SDQ0
DDRA_SDQ4

DDRA_SDQS0
DDRA_SDQ1

DDRA_SDQ3
DDRA_SDQ8

DDRA_SDQ12
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ17
DDRA_SDQ21

DDRA_SDQS2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ27

DDRA_SDQ24
DDRA_SDQS3

DDRA_SDQ29
DDRA_SDQ31

DDRA1_CKE3
DDRA1_SMA12

DDRA1_SMA9
DDRA1_SMA7

DDRA1_SMA5
DDRA1_SMA3
DDRA1_SMA1

DDRA1_SMA10
DDRA1_SMA13
DDRA1_SWE#
DDRA1_SCS#2
DDRA1_SMA15

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ45

DDRA_SDQ41
DDRA_SDQS5

DDRA_SDQ46
DDRA_SDQ43

DDRA_SDQ52
DDRA_SDQ49

DDRA_SDQS6 DDRA_SDM6
DDRA_SDQ50

DDRA_SDQ51
DDRA_SDQ61

DDRA_SDQ56
DDRA_SDQS7

DDRA_SDQ63
DDRA_SDQ59

SMB_CK_DAT1
SMB_CK_CLK1

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP1565619_REVERSE 5.2

DIMM1

REVERSE

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

2
4

VSS

6

DQ4

8

DQ5

10

VDD

12

DM0

14

DQ6

16

VSS

18

DQ7

20
22

VDD

24
26

DM1

28

VSS

30
32
34

VDD

36

VDD

38

VSS

40

VSS

42
44
46

VDD

48

DM2

50
52

VSS

54
56
58

VDD

60
62

DM3

64

VSS

66
68
70

VDD

72

CB4

74

CB5

76

VSS

78

DM8

80

CB6

82

VDD

84

CB7

86
88

VSS

90

VSS

92

VDD

94

VDD

96
98
100

A11

102

A8

104

VSS

106

A6

108

A4

110

A2

112

A0

114

VDD

116

BA1

118
120
122

S1#

124

DU

126

VSS

128
130
132

VDD

134

DM4

136
138

VSS

140
142
144

VDD

146
148

DM5

150

VSS

152
154
156

VDD

158
160

CK1

162

VSS

164
166
168

VDD

170

DM6

172
174

VSS

176
178
180

VDD

182
184

DM7

186

VSS

188
190
192

VDD

194

SA0

196

SA1

198

SA2

200

DU

Layout & BOM update 7/10 Layout & BOM update 7/10

+2.5V

DDRA_SDQ7
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ2
DDRA_SDQ9

DDRA_SDQ14
DDRA_SDM1

DDRA_SDQ13
DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDM2
DDRA_SDQ18

DDRA_SDQ19
DDRA_SDQ30

DDRA_SDQ28
DDRA_SDM3

DDRA_SDQ25
DDRA_SDQ26

DDRA1_CKE2
DDRA1_SMA11

DDRA1_SMA8
DDRA1_SMA6

DDRA1_SMA4
DDRA1_SMA2
DDRA1_SMA0

DDRA1_SMA14
DDRA1_SRAS#
DDRA1_SCAS#
DDRA1_SCS#3

DDRA_SDQ33
DDRA_SDQ32

DDRA_SDM4
DDRA_SDQ34

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDQ44
DDRA_SDM5

DDRA_SDQ42
DDRA_SDQ47

DDRA_SDQ53
DDRA_SDQ54

DDRA_SDQ48
DDRA_SDQ55

DDRA_SDQ60
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ62

DDRA_SDQ58

+3VS

0.1U_0402_16V4Z

C830

0.1U_0402_16V4Z

DDRA_CLK4# <9>
DDRA_CLK4 <9>

2

C701

1

2

2

C700

1

1

DDRA_VREF trace width of
20mils and space
20mils(min)

DDRA1_SMA9
DDRA1_SMA12

DDRA1_SMA5
DDRA1_SMA7

DDRA1_SMA1
DDRA1_SMA3

DDRA1_SMA13
DDRA1_SMA10

DDRA1_SMA8
DDRA1_SMA11

DDRA1_SMA4
DDRA1_SMA6

DDRA1_SMA0
DDRA1_SMA2

DDRA1_SMA14
DDRA1_SMA15
DDRA1_SWE#

DDRA1_SCS#2
DDRA1_SCS#3
DDRA1_SRAS#
DDRA1_SCAS#
DDRA1_CKE2
DDRA1_CKE3

+2.5V+2.5V

12

DDR A_VREF DDR A_VREF

0.1U_ 0 402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 2

R1045 10_0402_5%

1 2

R1046 10_0402_5%

1 2

R1047 10_0402_5%

1 2

R1048 10_0402_5%

1 2

R1049 10_0402_5%

1 2

R1050 10_0402_5%

1 2

R1051 10_0402_5%

1 2

R1052 10_0402_5%

1 2

R1053 10_0402_5%

RP114

10_0404_4P2R_5%

RP115

10_0404_4P2R_5%

RP116

10_0404_4P2R_5%

RP117

10_0404_4P2R_5%

RP118

10_0404_4P2R_5%

RP119

10_0404_4P2R_5%

RP120

10_0404_4P2R_5%

12

DDRA_SMA9
DDRA_SMA12

DDRA_SMA5
DDRA_SMA7

DDRA_SMA1
DDRA_SMA3

DDRA_SMA13
DDRA_SMA10

DDRA_SMA8
DDRA_SMA11

DDRA_SMA4
DDRA_SMA6

DDRA_SMA0
DDRA_SMA2

DDRA_SMA14
DDRA_SMA15
DDRA_SWE#

DDRA_SCS#2
DDRA_SCS#3
DDRA_SRAS#
DDRA_SCAS#
DDRA_CKE2
DDRA_CKE3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Re v

Date: Sheet

Compal Ele c t ronics, Inc.

SCHEMATIC, M/B LA-1861

401257

七月

1

14 61星期T, 30, 2003

0E

of

5

DDR Termination resistors & Decoupling caps

4

3

2

1

+1.25VS

DDRA_SMA15
DDRA_SMA13

DDRA_SDQ[0..63]<9,14>

D D

C C

B B

DDRA_SDQS[0..7]<9,14>

DDRA_SMA[0..15]<9,14>

DDRA_SDM[0..7]<9,14>

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..15]
DDRA_SDM[0..7]

DDRA_SCAS#<9,14>

DDRA_SCS#0<9, 14>

DDRA_SRAS#<9,14>

DDRA_CKE3<9,14>

DDRA_CKE1<9,14>

DDRA_CKE2<9,14>

DDRA_CKE0<9,14>

DDRA_SWE#<9,14>

DDRA_SCS#1<9, 14>

DDRA_SCS#2<9, 14>

DDRA_SCS#3<9, 14>

DDRA_SMA14
DDRA_SMA10

DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7

DDRA_SMA8
DDRA_SMA9
DDRA_SMA11
DDRA_SMA12

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3

DDRA_SCAS#

DDRA_SCS#0

DDRA_SRAS#

DDRA_CKE3

DDRA_CKE1

DDRA_CKE2

DDRA_CKE0

DDRA_SWE#

DDRA_SCS#1

DDRA_SCS#2

DDRA_SCS#3

RP92

33_0804_8P4R_5%

RP94

33_0804_8P4R_5%

33_0804_8P4R_5%

33_0804_8P4R_5%

1 2

R236 33_0402_5%

1 2

R237 33_0402_5%

1 2

R234 33_0402_5%

1 2

R232 33_0402_5%

1 2

R230 33_0402_5%

1 2

R233 33_0402_5%

1 2

R231 33_0402_5%

1 2

R235 33_0402_5%

1 2

R238 33_0402_5%

1 2

R239 33_0402_5%

1 2

R240 33_0402_5%

RP95

RP93

18
27
36
45

18
27
36
45

+1.25VS

18
27
36
45

18
27
36
45

C743 0.1U_04 02_16V4Z

1 2

+2.5V

1 2

C76 5 0.1U _ 0 4 02_16V4Z

C739 0.1U_04 02_16V4Z

1 2

+2.5V

1 2

C73 8 0.1U _ 0 4 02_16V4Z

C741 0.1U_0402_16V4Z

1 2
1 2

C740 0.1U_0402_16V4Z

C745 0.1U_0402_16V4Z

1 2
1 2

C744 0.1U_0402_16V4Z

+1.25VS

C298 0.1U_04 02_16V4Z

1 2

1 2

C28 5 0.1U _ 0 4 02_16V4Z

C284 0.1U_04 02_16V4Z

1 2

1 2

C28 6 0.1U _ 0 4 02_16V4Z

C297 0.1U_04 02_16V4Z

1 2

1 2

C28 3 0.1U _ 0 4 02_16V4Z

+2.5V

+2.5V

1

C813

22U_1206_10V4Z

2

+2.5V

+2.5V

+2.5V

+1.25VS

1

2

C814
22U_1206_10V4Z

DDRA_SDQS0
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQ6

DDRA_SDQ0
DDRA_SDQ7
DDRA_SDQ4
DDRA_SDQ5

DDRA_SDQ3
DDRA_SDQ2
DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQ10
DDRA_SDQ13
DDRA_SDQ11
DDRA_SDQ15

DDRA_SDQ12
DDRA_SDQ14
DDRA_SDQS1
DDRA_SDM1

DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ20
DDRA_SDQ17

DDRA_SDQ18
DDRA_SDQ22
DDRA_SDM2
DDRA_SDQS2

DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ19
DDRA_SDQ23

DDRA_SDM3
DDRA_SDQS3
DDRA_SDQ28
DDRA_SDQ24

DDRA_SDQ26
DDRA_SDQ31
DDRA_SDQ25
DDRA_SDQ29

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

56_0804_8P4R_5%

+1.25VS +1.25VS

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

C762 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C763 0.1U_0402_16V4Z

C764 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C759 0.1U_0402_16V4Z

C758 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C757 0.1U_0402_16V4Z

C754 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C751 0.1U_0402_16V4Z

C750 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C749 0.1U_0402_16V4Z

C769 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C767 0.1U_0402_16V4Z

C287 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C770 0.1U_0402_16V4Z

C291 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C296 0.1U_0402_16V4Z

C775 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C290 0.1U_0402_16V4Z

C771 0.1U_0402_16V4Z

1 2

+2.5V

1 2

C774 0.1U_0402_16V4Z

DDRA_SDQ34
DDRA_SDQ38
DDRA_SDM4
DDRA_SDQS4

DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ36

DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ39
DDRA_SDQ35

DDRA_SDM5
DDRA_SDQS5
DDRA_SDQ44
DDRA_SDQ41

DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ42
DDRA_SDQ46

DDRA_SDQ54
DDRA_SDQ49
DDRA_SDQ53
DDRA_SDQ52

DDRA_SDQ48
DDRA_SDQ50
DDRA_SDM6
DDRA_SDQS6

DDRA_SDQ61
DDRA_SDQ60
DDRA_SDQS7
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ55

DDRA_SDQ59
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM7

RP15

RP13

RP14

RP17

RP16

RP100

RP99

RP98

RP97

RP96

RP109

18
27
36
45

56_0804_8P4R_5%

RP110

18
27
36
45

56_0804_8P4R_5%

RP108

18
27
36
45

56_0804_8P4R_5%

RP107

18
27
36
45

56_0804_8P4R_5%

RP106

18
27
36
45

56_0804_8P4R_5%

RP104

18
27
36
45

56_0804_8P4R_5%

RP105

18
27
36
45

56_0804_8P4R_5%

RP102

18
27
36
45

56_0804_8P4R_5%

RP103

18
27
36
45

56_0804_8P4R_5%

RP101

18
27
36
45

56_0804_8P4R_5%

C76 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C742 0.1U _ 0 4 02_16V4Z

C76 0 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C761 0.1U _ 0 4 02_16V4Z

C75 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C755 0.1U _ 0 4 02_16V4Z

C75 2 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C753 0.1U _ 0 4 02_16V4Z

C74 8 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C747 0.1U _ 0 4 02_16V4Z

C74 6 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C768 0.1U _ 0 4 02_16V4Z

C28 9 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C772 0.1U _ 0 4 02_16V4Z

C29 5 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C294 0.1U _ 0 4 02_16V4Z

C77 3 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C292 0.1U _ 0 4 02_16V4Z

C29 3 0.1U_ 0 4 02_16V4Z

1 2

+2.5V

1 2

C288 0.1U _ 0 4 02_16V4Z

System Memory Decoupling caps

+2.5V

1

C236

0.1U_ 0 402_16V4Z

2

+2.5V

1

C249

0.1U_ 0 402_16V4Z

2

+2.5V

A A

1

2

+2.5V

1

2

C276
22U_1206_10V4Z

C267

0.1U_ 0 402_16V4Z

5

1

C234

0.1U_ 0 402_16V4Z

2

1

C250

0.1U_ 0 402_16V4Z

2

1

C261

0.1U_ 0 402_16V4Z

2

1

C268

0.1U_ 0 402_16V4Z

2

1

C237

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C262

0.1U_0402_16V4Z

2

1

C238

0.1U_0402_16V4Z

2

1

C240

0.1U_ 0 402_16V4Z

2

1

C252

0.1U_ 0 402_16V4Z

2

1

C263

0.1U_ 0 402_16V4Z

2

1

C239

0.1U_ 0 402_16V4Z

2

1

C241

0.1U_0402_16V4Z

2

1

C253

0.1U_0402_16V4Z

2

1

C264

0.1U_0402_16V4Z

2

1

C269

0.1U_0402_16V4Z

2

1

C242

0.1U_ 0 402_16V4Z

2

1

C254

0.1U_ 0 402_16V4Z

2

1

C265

0.1U_ 0 402_16V4Z

2

1

C270

0.1U_ 0 402_16V4Z

2

4

1

C243

0.1U_ 0 402_16V4Z

2

1

C255

0.1U_ 0 402_16V4Z

2

1

C266

0.1U_ 0 402_16V4Z

2

1

C271

0.1U_ 0 402_16V4Z

2

1

C244

0.1U_0402_16V4Z

2

1

C256

0.1U_0402_16V4Z

2

1

C277
10U_0805_10V4Z

2

1

C272

0.1U_0402_16V4Z

2

1

C245

0.1U_ 0 402_16V4Z

2

1

C257

0.1U_ 0 402_16V4Z

2

1

C275
22U_1206_10V4Z

2

1

C246

0.1U_0402_16V4Z

2

1

C258

0.1U_0402_16V4Z

2

3

1

C247

0.1U_ 0 402_16V4Z

2

1

C259

0.1U_ 0 402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C248

0.1U_ 0 402_16V4Z

2

1

C260

0.1U_ 0 402_16V4Z

2

1

+

C280
@100U_D2_10VM

2

1

+

C282
@100U_D2_10VM

2

2

Title

Size Document Number Re v

Date: Sheet

Compal Ele c t ronics, Inc.

SCHEMATIC, M/B LA-1861

401257

七月

1

15 61星期T, 30, 2003

of

0E

5

1 2

1 2

C461

M9+/M10@0.1U_0402_16V4Z

Q72

2SC2411K_SC59

+3VS

AGP_AD[0..31]

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_ST[0..2]

R389
10_0402_5%

1 2

AGP_REQ#<10>
AGP_GNT#<10>

AGP_PAR<10>

AGP_STOP#<10>

AGP_DEVSEL#<10>

AGP_TRDY#<10>

AGP_IRDY#<10>
PCI_PIRQA#<10,25,30,33,44>
AGP_WBF#<10>
AGP_STP#<10,26>

AGP_BUSY#<10,26>

AGP_RBF#<10>
AGP_ADSTBF_0<10>
AGP_ADSTBF_1<10>
AGP_ADSTBS_0<10>
AGP_ADSTBS_1<10>

8X4X

AGP_SBSTBF<10>
AGP_SBSTBS<10>

EXTAGPREF_8X

R400 M9+/M10@137_0402_1%

+1.5VS

1 2

AGP_DBI_HI<10>
AGP_DBI_LO<10>

R403 M9+/M10@715_0603_1%

+1.8VS

R1030
470_0402_5%

1 2

CBE

123

5

1 2

AGP8X_DET#<10>

1 2

TV_CRMA<11,24,43>
TV_LUMA<11,24,43>

TV_COMPS<11,24>

R77

@10K_0402_5%

SSIN
SSOUT

R391 M9+/M10@1K_0603_5%

1 2

SUSSTAT#

R1031

10K_0402_5%

1 2

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

CLK_AGP_EXT_66M

RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#

AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTBF_0
AGP_ADSTBF_1
AGP_ADSTBS_0
AGP_ADSTBS_1

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

AGP_SBSTBF
AGP_SBSTBS

AGP_DBI_HI
AGP_DBI_LO

R393M9+/M10@1K_0402_5%

TV_CRMA
TV_LUMA
TV_COMPS

12

XTALIN

AGP_AD[0..31]<10>

AGP_SBA[0..7]<10>

AGP_CBE#[0..3]<10>

AGP_ST[0..2]<10>

D D

C451 15P_0402_50V8D

CLK_AGP_EXT_66M<23>

+3VS

C C

R1041
M9@8.2K_0402_5%

AGP_FRAME#<10>

1K_0603_1%RA324_0603_1%
1K_0603_1% 100_0603_1%

RB

+1.5VS

RA

R46
M9+/M10@324_0603_1%

1 2

B B

RB

Leave These Pin No Connecting, When
Using M10-P Int ernal Sp r ead Spe ctrum

2

1

R45

1 2

M9+/M10@100_0603_1%

If M10+P PO P 4 7_0402_1%
If M9+X POP 13 7_0402_1%

Layout & BOM update 7/10

A A

SUS_STAT#<8,26>

U7A

H29

AD0

H28

AD1

J29

AD2

J28

AD3

K29

AD4

K28

AD5

L29

AD6

L28

AD7

N28

AD8

P29

AD9

P28

AD10

R29

AD11

R28

AD12

T29

AD13

T28

AD14

U29

AD15

N25

AD16

R26

AD17

P25

AD18

R27

AD19

R25

AD20

T25

AD21

T26

AD22

U25

AD23

V27

AD24

W26

AD25

W25

AD26

Y26

AD27

Y25

AD28

AA26

AD29

AA25

AD30

AA27

AD31

N29

C/BE#0

U28

C/BE#1

P26

C/BE#2

U26

C/BE#3

AG30

PCICLK

AG28

RST#

AF28

REQ#

AD26

GNT#

M25

PAR

N26

STOP#

V29

DEVSEL#

V28

TRDY#

W29

IRDY#

W28

FRAME#

AE26

INTA#

AC26

WBF#

AH30

STP_AGP#

AH29

AGP_BUSY#

AE29

RBF#

M28

AD_STBF_0

V25

AD_STBF_1

M29

AD_STBS_0

V26

AD_STBS_1

AD28

SBA0

AD29

SBA1

AC28

SBA2

AC29

SBA3

AA28

SBA4

AA29

SBA5

Y28

SBA6

Y29

SBA7

AF29

ST0

AD27

ST1

AE28

ST2

AB29

SB_STBF

AB28

SB_STBS

M26

AGPREF

M27

AGPTEST

AB25

DBI_HI

AB26

DBI_LO

AC25

AGP8X_DET#

AE11

DMINUS

AF11

DPLUS

AK21

R2SET

AJ23

C_R

AJ22

Y_G

AK22

COMP_B

AJ24

H2SYNC

AK24

V2SYNC

AG23

DDC3CLK

AG24

DDC3DATA

AK25

SSIN

AJ25

SSOUT

AH28

XTALIN

AJ29

XTALOUT

AH27

TESTEN

AG26

SUS_STAT#

M9+/M10@SA002160E00(0301021300)

4

M10-P/(M9+X)
(1/6)

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8

ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15

ZV PORT / EX T TM DS / GPIO / ROMLVDSTMDSDAC1

ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23

ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3

PCI/AGPAGP8XCLK

TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

BLON/(BLON#)

THRM

SSC DAC2

TEST_MCLK/(NC)

TEST_YCLK/(NC)

PLLTEST/(NC)

RSTB_MSK/(NC)

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

VREFG/(NC)

ROMCS#

DVOMODE

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P

TXCLK_LN
TXCLK_LP

TXCLK_UN
TXCLK_UP

DIGON

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TXCM

TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC

VSYNC

RSET

DDC1DATA

DDC1CLK

AUXWIN

STRAP_G

AJ5

STRAP_H

AH5

STRAP_J

AJ4

STRAP_K

AK4

STRAP_D

AH4

STRAP_E

AF4

STRAP_F

AJ3

STRAP_B

AK3

STRAP_A

AH3

STRAP_O

AJ2
AH2

STRAP_L

AH1

STRAP_M

AG3

STRAP_N

AG1
AG2
AF3

XTALINSS_R

AF2

VREFG

AG4
AF5

R1002 128M@0_0402_5%

AH6

1 2
1 2

AJ6

R1003 @0_0402_5%

AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7

STRAP_R

AF7

STRAP_S

AE8
AG8
AF8

STRAP_T

AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

DVOMODE

AE10

AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19

AE12
AG12

AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13

AE13
AE14

AF12

AK27

R

AJ27

G

AJ26

B

AG25
AH25

AH26
AF25

AF24
AF26

B6
E8
AE25
AG29

R428

TXA0­TXA0+
TXA1­TXA1+
TXA2­TXA2+

TXACLK­TXACLK+
TXB0­TXB0+
TXB1­TXB1+
TXB2­TXB2+

TXBCLK­TXBCLK+

ENAVDD

1 2

R426 M9+@0_0402_5%

ENABLT

R424 M9+/M10@100K_0402_5%

CRTR_R
CRTG_R
CRTB_R
CRTHSYNC_R
CRTVSYNC_R

AGP_RSET
3VDDCDA

3VDDCCL

1 2

R380 M9+/M10@10K_0402_5%

1 2
R378
M9+/M10@1K_0603_5%

3

2

AGP, DAC & LVDS INTERFACE

+3VS

12

PWR_SEL <52>

R460 M9+/M10@0_0402_5%

1 2

+3VS

+3VS

RST#

R429

R433

R397 M9+/M10@499_0402_1%

M9+/M10@2.2K_0402_5%

M9+/M10@2.2K_0402_5%

I2C_DATA <24>
I2C_CLK <24>

@10U_0805_6.3V6M

M9+/M10@0_0402_5%

1 2

TXA0- <24>
TXA0+ <24>
TXA1- <24>
TXA1+ <24>
TXA2- <24>
TXA2+ <24>

TXACLK- <24>
TXACLK+ <24>
TXB0- <24>
TXB0+ <24>
TXB1- <24>
TXB1+ <24>
TXB2- <24>
TXB2+ <24>

TXBCLK- <24>
TXBCLK+ <24>

ENAVDD <10,24>

R369 M9+/M10@0_0402_5%

1 2

R16 M9+/M10@0_0402_5%

1 2

R14 M9+/M10@0_0402_5%

1 2

R364 M9+/M10@0_0402_5%

1 2

R362 M9+/M10@0_0402_5%

1 2

1 2

(15mil)

3VDDCDA <11,24>
3VDDCCL <11,24>

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(25 mil)

C47

ENABLT#

3

XTALIN_SS

R1028 @0_0402_5%

12

R1029

@0.1U_0402_16V4Z

@10K_0402_5%

@10K_0402_5%

12

M9+/M10@0_0402_5%

C64

12

12

R34

@10K_0402_5%

12

12

R33

R31

R32
@10K_0402_5%

Note: PLACE CLOSE TO VGA CHIP

+3VS

12

R468
M10@10K_0402_5%

ENABLT#

13

D

Q51

2

G

M10@2N7002_SOT23

S

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

PCI_RST# <25,29,30,32,33,34,38,44>

NB_RST# <8,11,25,38>

S0

S1

ENABLT# <10,24,40>

CRT_R <11,24,43>
CRT_G <11,24,43>
CRT_B <11,24,43>
CRT_HSYNC <11,24>
CRT_VSYNC <11,24>

R427
M10@1K_0603_1%

12

R425
M10@1K_0603_1%

2

U5

VDD

1

X1/CLK

7

S0

6

S1

LVDS SPREAD SPECTRUM

4

SSCLK

8

Xout

5

SSCC

GND

@SM560BS_SOIC8

3

Selection Table For W180

SS%

0
1

L9
@BLM21P300S_0805

1 2

12

R35
@0_0402_5%

1 2

R65
@22_0402_5%

12

R36
@0_0402_5%

Spread % Setting for
Freq. Range

Fin>Fout>Fin-1.25%
Fin>Fout>Fin-3.75%

2

+3VS

SSOUT

1 2

R27

1

@22_0402_5%
C30
@10P_0402_25V8K

2

SSIN

1

C63
@10P_0402_25V8K

2

Ra 180_0603_5%
Rb

+3VS

Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out

12

R24
M9+/M10@10K_0402_5%

C20

M9+/M10@0.1U_0402_16V4Z

+3VS

FREQOUT XTALIN_SS

12

R142 M9+/M10@10K_0402_5%

12

R143 M9+/M10@10K_0402_5%

1

ID_Disable

GPIO8

GPIO7

GPIO4

GPIO5

GPIO6

GPIO0

GPIO1

GPIO2

GPIO3

GPIO9

GPIO11

GPIO12

GPIO13

STRAP_A

VGA_Disable

STRAP_B

STRAP_D

STRAP_E

STRAP_F

STRAP_G

STRAP_H

STRAP_J

STRAP_K

STRAP_O

STRAP_L

STRAP_M

STRAP_N

STRAP_R

STRAP_S

STRAP_T

R451 @10K_0402_5%

R456 @10K_0402_5%

R450 @10K_0402_5%

R446 @10K_0402_5%

R457 @10K_0402_5%

R440 @10K_0402_5%
R449 @10K_0402_5%

R441 @10K_0402_5%
R442 @10K_0402_5%

R439 @10K_0402_5%
R438 @10K_0402_5%

R448 @10K_0402_5%
R447 @10K_0402_5%

R458 @10K_0402_5%

R462 @10K_0402_5%

R459 @10K_0402_5%

R463 @10K_0402_5%

R434 @10K_0402_5%

For M10-P

R435 @10K_0402_5%

R454 @10K_0402_5%
R452 @10K_0402_5%

12

12

12

12

12

12
12

12
12

12
12

12
12

12

12

12

12

12

12

12
12

M9+X M10-P

261_0603_1%

150_0402_5%

X1

4

OUT

VDD

1

GND

OE

M9+/M10@27MHZ_15P

M9+/M10@W180-01GT_SO8

3
2

U10

1

X1/CLK

7

FS1

8

FS2

150_0402_5%

FREQOUT

M9+/M10@180_0603_5%

1.5V OSC out for M9+X

1.2V OSC out for M10-P

Ra

1 2

R377

6

M9+/M10@0.1U_0402_16V4Z

VDD

CLKOUT

X2

SS%

GND

3

12

R379
M9+/M10@150_0402_5%

Rb

L17
M9+/M10@FCM2012C-800_0805

1

C165

2

5

2
4

SS%

1 2

XTALIN

1 2

C166
M9+/M10@4.7U_0805_10V4Z

R115
M9+/M10@10K_0402_5%

Note: PLACE CLOSE TO U10 (VGA M9+X/M10-P)

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

of

16 61,

1

+3VS

+3VS

0E

5

4

3

2

1

D D

R_NMDA0
R_NMDA1
R_NMDA2
R_NMDA3
R_NMDA4
R_NMDA5
R_NMDA6
R_NMDA7
R_NMDA8
R_NMDA9

C C

B B

R_NMDA10
R_NMDA11
R_NMDA12
R_NMDA13
R_NMDA14
R_NMDA15
R_NMDA16
R_NMDA17
R_NMDA18
R_NMDA19
R_NMDA20
R_NMDA21
R_NMDA22
R_NMDA23
R_NMDA24
R_NMDA25
R_NMDA26
R_NMDA27
R_NMDA28
R_NMDA29
R_NMDA30
R_NMDA31
R_NMDA32
R_NMDA33
R_NMDA34
R_NMDA35
R_NMDA36
R_NMDA37
R_NMDA38
R_NMDA39
R_NMDA40
R_NMDA41
R_NMDA42
R_NMDA43
R_NMDA44
R_NMDA45
R_NMDA46
R_NMDA47
R_NMDA48
R_NMDA49
R_NMDA50
R_NMDA51
R_NMDA52
R_NMDA53
R_NMDA54
R_NMDA55
R_NMDA56
R_NMDA57
R_NMDA58
R_NMDA59
R_NMDA60
R_NMDA61
R_NMDA62
R_NMDA63

R_NMDA[0..63]<21>

NMAA[0..13]<21>

NDQMA[0..7]<21>

NDQSA[0..7]<21>

U7B

L25

DQA0

L26

DQA1

K25

DQA2

K26

DQA3

J26

DQA4

H25

DQA5

H26

DQA6

G26

DQA7

G30

DQA8

D29

DQA9

D28

DQA10

E28

DQA11

E29

DQA12

G29

DQA13

G28

DQA14

F28

DQA15

G25

DQA16

F26

DQA17

E26

DQA18

F25

DQA19

E24

DQA20

F23

DQA21

E23

DQA22

D22

DQA23

B29

DQA24

C29

DQA25

C25

DQA26

C27

DQA27

B28

DQA28

B25

DQA29

C26

DQA30

B26

DQA31

F17

DQA32

E17

DQA33

D16

DQA34

F16

DQA35

E15

DQA36

F14

DQA37

E14

DQA38

F13

DQA39

C17

DQA40

B18

DQA41

B17

DQA42

B15

DQA43

C13

DQA44

B14

DQA45

C14

DQA46

C16

DQA47

A13

DQA48

A12

DQA49

C12

DQA50

B12

DQA51

C10

DQA52

C9

DQA53

B9

DQA54

B10

DQA55

E13

DQA56

E12

DQA57

E10

DQA58

F12

DQA59

F11

DQA60

E9

DQA61

F9

DQA62

F8

DQA63

M9+/M10@SA002160E00(0301021300)

R_NMDA[0..63]

NMAA[0..13]

NDQMA[0..7]

NDQSA[0..7]

M10-P/(M9+X)
(2/6)

AA12/(AA13)
AA13/(AA12)

AA14/(NC)

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MEMORY INTERFACE

A

CLKA0#

CLKA1#

MVREFD

MVREFS/(NC)

AA10
AA11

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA1

DIMA0

DIMA1

AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9

NMAA1

B22

NMAA2

B23

NMAA3

B24

NMAA4

C23

NMAA5

C22

NMAA6

F22

NMAA7

F21

NMAA8

C21

NMAA9

A24

NMAA10

C24

NMAA11

A25

NMAA12

E21

NMAA13

B20
C19

NDQMA0

J25

NDQMA1

F29

NDQMA2

E25

NDQMA3

A27

NDQMA4

F15

NDQMA5

C15

NDQMA6

C11

NDQMA7

E11

NDQSA0

J27

NDQSA1

F30

NDQSA2

F24

NDQSA3

B27

NDQSA4

E16

NDQSA5

B16

NDQSA6

B11

NDQSA7

F10

NMRASA#

A19

NMCASA#

E18

NMWEA#

E19

NMCSA0#

E20

NMCSA1#

F20

NMCKEA

B19

NMCLKA0

B21

NMCLKA0#

C20

NMCLKA1

C18

NMCLKA1#

A18
D30

B13

MVREFD

B7

MVREFS

B8

NMRASA# <21>
NMCASA# <21>

NMWEA# <21>
NMCSA0# <21>
NMCSA1# <21>

NMCKEA <21>

NMCLKA0 <21>
NMCLKA0# <21>

NMCLKA1 <21>
NMCLKA1# <21>

NMAA0

E22

MEMORY INTERFACE A

+2.5VS

12

R431
M9+/M10@1K_0402_1%

MVREFD

M9+/M10@0.1U_0402_16V4Z

MVREFS

M10@0.1U_0402_16V4Z

Poped for M10-P
Depoped for
M9+X

C542

C543

1

2

1

2

(25 mil)

(25 mil)

12

R430
M9+/M10@1K_0402_1%

+2.5VS

12

R437
M10@1K_0402_1%

12

R436
M10@1K_0402_1%

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

30, 2003

401257

星期三 七月

0E

of

17 61,

1

5

D D

4

3

2

1

MEMORY INTERFACE B

R_NMDB[0..63]<22>

NMAB[0..13]<22>

NDQMB[0..7]<22>

NDQSB[0..7]<22>

C C

B B

R_NMDB[0..63]

NMAB[0..13]

NDQMB[0..7]

NDQSB[0..7]

R_NMDB0
R_NMDB1
R_NMDB2
R_NMDB3
R_NMDB4
R_NMDB5
R_NMDB6
R_NMDB7
R_NMDB8
R_NMDB9
R_NMDB10
R_NMDB11
R_NMDB12
R_NMDB13
R_NMDB14
R_NMDB15
R_NMDB16
R_NMDB17
R_NMDB18
R_NMDB19
R_NMDB20
R_NMDB21
R_NMDB22
R_NMDB23
R_NMDB24
R_NMDB25
R_NMDB26
R_NMDB27
R_NMDB28
R_NMDB29
R_NMDB30
R_NMDB31
R_NMDB32
R_NMDB33
R_NMDB34
R_NMDB35
R_NMDB36
R_NMDB37
R_NMDB38
R_NMDB39
R_NMDB40
R_NMDB41
R_NMDB42
R_NMDB43
R_NMDB44
R_NMDB45
R_NMDB46
R_NMDB47
R_NMDB48
R_NMDB49
R_NMDB50
R_NMDB51
R_NMDB52
R_NMDB53
R_NMDB54
R_NMDB55
R_NMDB56
R_NMDB57
R_NMDB58
R_NMDB59
R_NMDB60
R_NMDB61
R_NMDB62
R_NMDB63

U7C

M10-P/(M9+X)

D7

DQB0

F7

(3/6)

DQB1

E7

DQB2

G6

DQB3

G5

DQB4

F5

DQB5

E5

DQB6

C4

DQB7

B5

DQB8

C5

DQB9

A4

DQB10

B4

DQB11

C2

DQB12

D3

DQB13

D1

DQB14

D2

DQB15

G4

DQB16

H6

DQB17

H5

DQB18

J6

DQB19

K5

DQB20

K4

DQB21

L6

DQB22

L5

DQB23

G2

DQB24

F3

DQB25

H2

DQB26

E2

DQB27

F2

DQB28

J3

DQB29

F1

DQB30

H3

DQB31

U6

DQB32

U5

DQB33

U3

DQB34

V6

DQB35

W5

DQB36

W4

DQB37

Y6

DQB38

Y5

DQB39

U2

DQB40

V2

DQB41

V1

DQB42

V3

DQB43

W3

DQB44

Y2

DQB45

Y3

DQB46

AA2

DQB47

AA6

DQB48

AA5

DQB49

AB6

DQB50

AB5

DQB51

AD6

DQB52

AD5

DQB53

AE5

DQB54

AE4

DQB55

AB2

DQB56

AB3

DQB57

AC2

DQB58

AC3

DQB59

AD3

DQB60

AE1

DQB61

AE2

DQB62

AE3

DQB63

M9+/M10@SA002160E00(0301021300)

MEMORY INTERFACE B

MEMVMODE0
MEMVMODE1

AB10

AB11
AB12/(AB13)
AB13/(AB12)

AB14/(NC)

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB0
DIMB1

MEMTEST

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9

NMAB1

M1

NMAB2

M3

NMAB3

L3

NMAB4

L2

NMAB5

M2

NMAB6

M5

NMAB7

P6

NMAB8

N3

NMAB9

K2

NMAB10

K3

NMAB11

J2

NMAB12

P5

NMAB13

P3
P2

NDQMB0

E6

NDQMB1

B2

NDQMB2

J5

NDQMB3

G3

NDQMB4

W6

NDQMB5

W2

NDQMB6

AC6

NDQMB7

AD2

NDQSB0

F6

NDQSB1

B3

NDQSB2

K6

NDQSB3

G1

NDQSB4

V5

NDQSB5

W1

NDQSB6

AC5

NDQSB7

AD1

NMRASB#

R2

NMCASB#

T5

NMWEB#

T6

NMCSB0#

R5

NMCSB1#

R6

NMCKEB

R3

NMCLKB0

N1

NMCLKB0#

N2

NMCLKB1

T2

NMCLKB1#

T3

R444 M9+/M10@4.7K_0402_5%

C6

1 2

R445 M9+/M10@4.7K_0402_5%

1 2

C7
E3

AA3

R432 M9+/M10@47_0603_1%

1 2

C8

NMAB0

N5

NMRASB# <22>
NMCASB# <22>
NMWEB# <22>
NMCSB0# <22>
NMCSB1# <22>
NMCKEB <22>
NMCLKB0 <22>

NMCLKB0# <22>
NMCLKB1 <22>

NMCLKB1# <22>

+1.8VS

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF

R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

0E

of

18 61,

1

5

4

3

2

1

+3VS

1

U7D

M10-P/(M9+X)

VDDR1

(4/6)

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)

VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)

TPVDD
TPVSS

AVDD
A2VDD
A2VDD
A2VDDQ

A2VSSN
A2VSSN
A2VSSQ

AVSSN
AVSSQ

M9+/M10@SA002160E00(0301021300)

I/O POWER

LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)

VDDRH0
VDDRH1

VSSRH0
VSSRH1

MPVDD

MPVSS

PVDD
PVSS

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3

VDDR4
VDDR4
VDDR4
VDDR4
VDDR4

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

LVDDR_18
LVDDR_18

LPVDD

LVSSR
LVSSR
LVSSR
LVSSR
LPVSS

VDD1DI
VDD2DI

VSS1DI
VSS2DI

TXVDDR
TXVDDR

TXVSSR
TXVSSR
TXVSSR

+VDDC15

AD4

AC11
AC20

AK12

AJ12

AH24

AG21

AH21
AF22

AH22

AJ21

AF23

AH23
AD24

B1
B30
A15
A21
A28

A3

A9
AA1
AA4
AA7
AA8

D5

D8
D11
D13
D14
D17
D20
D23
D26
E27

F4

G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22

J1
J23
J24

J4

J7

J8

L27

L8
M4
N4
N7
N8
R1

T4

T7

T8

V4

V7

V8

D19

R4

H11
H20
L23

P8

Y23

Y8

D D

C C

+2.5VS

+1.5VS

Poped for M10-P

+2.5VS

Poped for
M10-P

R412 M10@0_0402_5%

1 2

R422 M10@0_0402_5%

1 2

1 2
R411
M10@0_0805_5%

Poped for M9+X

B B

A A

+1.8VS

1 2
R406
M9+@0_0805_5%

+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_DAC2.5

+VDD_DAC1.8

F18
N6

F19
M6

A7
A6

AK28
AJ28

AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7

AC10
AC9
AD10
AD9
AG7

AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27

AE20
AE17
AF21
AE15
AJ20

AF20
AF15
AE19
AE16
AJ19

AE24
AE22

AE23
AE21

AF13
AF14

AG13
AG14
AH12

+2.5VDDRH

1 2
1 2

+VDD_MEMPLL1.8

+VDD_PLL1.8

+3VS

+1.5VS

Poped for M10-P

R419

M10@0_0805_5%

R423

M9+@0_0805_5%

Poped for M9+X

+VDD_PNLIO1.8
+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_PNLIO1.8

M9+/M10@22U_1206_10V4Z

M9+/M10@22U_1206_10V4Z

M9+/M10@10U_0805_6.3V6M

M9+/M10@10U_0805_6.3V6M

+VDD_PNLIO2.5

+VDD_PNLIO1.8

M9+/M10@10U_0805_6.3V6M

M9+/M10@10U_0805_6.3V6M

C175

2

M9+/M10@0.1U_0402_16V4Z

+1.5VS

1

C24

2

M9+/M10@0.1U_0402_16V4Z

+VDD_DAC2.5

(20 mil)

1

C105

2

+VDD_PNLPLL1.8

(20 mil)

1

C145

2

M9+/M10@10U_0805_6.3V6M

+VDD_PNLIO1.8

(20 mil)

1

C530

2

+VDD_PNLIO2.5

(20 mil)

1

C496

2

M9+/M10@0.1U_0402_16V4Z

M9+/M10@0.1U_0402_16V4Z

1

C449

C472

C140

M9+/M10@0.1U_0402_16V4Z

+VDD_DAC1.8

C96

C510

M9+/M10@0.1U_0402_16V4Z

C501

C454

2

M9+/M10@0.1U_0402_16V4Z

1

C471

2

L14
M9+/M10@CHB1608U301_0603

1 2

1

C488
M9+/M10@0.1U_0402_16V4Z

2

1

2

(20 mil)

1

2

M9+/M10@0.1U_0402_16V4Z

1

C506

2

1

2

1

2

1

2

1

C143
M9+/M10@0.1U_0402_16V4Z

2

1

C493
M9+/M10@0.1U_0402_16V4Z

2

1

2

1

C502
M9+/M10@0.1U_0402_16V4Z

2

1

C458

2

M9+/M10@0.01U_0402_16V7K

1

C470

2

M9+/M10@0.01U_0402_16V7K

+2.5VS

L15
M9+/M10@CHB1608U301_0603

1 2

L11
M9+/M10@CHB1608U301_0603

1 2

1

C490
M9+/M10@0.1U_0402_16V4Z

2

L43
M9+/M10@CHB1608U301_0603

1 2

1

C477
M9+/M10@0.01U_0402_16V7K

2

M9+/M10@0.01U_0402_16V7K

1

C469

2

M9+/M10@1U_0603_10V4Z

+1.8VS

M9+/M10@10U_0805_6.3V6M

+1.8VS

L41
M9+/M10@CHB1608U301_0603

1 2

+2.5VS

POWER
INTERFACE

M9+/M10@0.1U_0402_16V4Z

1

C824

M9+/M10@0.1U_0402_16V4Z

+VDD_MEMPLL1.8

+1.8VS

M9+/M10@0.1U_0402_16V4Z

2

+2.5VDDRH

(20 mil)

1

C513

2

+VDD_PLL1.8

(20 mil)

1

C78

2

(20 mil)

1

C540
M9+/M10@0.1U_0402_16V4Z

2

C825

1

2

L42
M9+/M10@CHB1608U301_0603

1 2

1

C541
M9+/M10@0.1U_0402_16V4Z

2

L12
M9+/M10@CHB1608U301_0603

1 2

1

C77
M9+/M10@0.1U_0402_16V4Z

2

L46
M9+/M10@CHB1608U301_0603

1 2

+VDDC15

M9+/M10@0.1U_0402_16V4Z

1

1

C816

C815

2

2

1

C826
M9+/M10@0.1U_0402_16V4Z

2

+2.5VS

+1.8VS

+1.8VS

1

1

C828

C827

M9+/M10@0.1U_0402_16V4Z

2

2

M9+/M10@0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Docu ment Number Re v

Date: Sheet

Compal E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA-1861

401257

星期三 七月

30, 2003

0E

of

19 61,

1