Compal LA-1811, TravelMate 290 Schematic
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LA-1811
1 1
2 2
Compal confidential
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic
3 3
4 4
A
B
2003-07-30(Under review)
REV:0.7
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
星期四 八月
LA-1811
0.7
of
166, 07, 2003
E
A
B
C
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Compal confidential
File Name :LA1811
1 1
CRT & TV-OUT Conn.
LCD Conn
W/EXT VGA CHIP
W/EXT VGA CHIP
VGA DDR x2 CHB
2 2
page 23
ATI-M9+X/M10C
page 17,18,19,20,21
VGA DDR x2 CHA
page 25
page 25
page 22
Fan Control
page 7
W/O EXT VGA CHIP
W/O EXT VGA CHIP
AGP BUS
Intel Northwood/Prescott Processor
uFCBGA-479/uFCPGA-478 CPU
page 4,5,6
H_A#(3..31)
PSB
800MHz
H_D#(0..63)
ATI-RC300M
VGA M9 Embeded
868 pin u-BGA
page 8,9,10,11,12,13
A-Link
Thermal Sensor
ADM1032AR
page 7
Memory BUS(DDR)
2.5V DDR- 200/266
USB1.1
USB2.0
CLOCK GENERATOR
ICS951402AGT
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
page 14,15,16
BT/USB KEY
USB conn x3
page 44
Audio Codec
ADI 1981B
page 37
page 24
page 44
AMP & Audio Jack
page 38
MDC & BT Conn
3.3V 33 MHz
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
USB2.0 Ctrl.
NEC uPD720101
page 36
IDSEL:AD23
(PIRQA/C/D#,GNT#4,REQ#4)
3 3
IEEE 1394
TI-TSB43AB22
page 35
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
Mini PCI
socket
page 43
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)
RTL 8101BL
RJ45 CONN
LAN
page 34
page 34
CardBus Controller
RTC CKT.
page 26
Power OK CKT.
page 48
NS 87591
page 46
PCI BUS
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
TI PCI1520/1620
Slot 0,1
page 32
page 31
Card slot
page 33
ATI-SB200
BGA 457 pin
page 26,27,28,29
LPC BUS
AC-LINK
Primary IDE
ATA-100
Secondary IDE
ATA-100
Mini-PCI solt
VIA VT1211
page 44
page 43
HDD
Connector
page 30
CDROM
Connector
Super I/O
page 30
page 39
RJ11 CONN
page 44
CABLE CONN.
*RJ45 CONN
*LINE IN JACK
*DC JACK
*COM PORT
page 41
*USB CONN x1
Power On/Off CKT.
page 45
4 4
DC/DC Int erface CKT.
page 49
Touch Pad
page 44,45
EC I/O Bu ffer
page 47
Int.KBD
BIOS
page 45
page 47
PARALLEL
page 40
FIR
page 45
FDD
page 40
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT
Power Circuit DC/DC
page 50,51,52,53,54,55,56,57
A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
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Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LA-1811
星期四 八月
Block Diagram
E
0.7
of
266, 07, 2003
Voltage Rails
A
Power Plane
VIN
B+
+VCC_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
The voltage for Processor VID select
1.25V switched power rail for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V switched power rail for ATI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
S3
S0-S1
N/AONN/A
N/A
N/A
N/A
ON
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ONON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
OFF
ON
ON
ON
ON
ON
S5
N/A
OFF
OFF
OFF
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*+5VALW 5V always on power rail
ON*
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means bui ld ATI SB USB2.0 related to turn on the function .
NEC@ : means bu ild NEC USB2.0 related to turn on the function .
External PCI Devices
1 1
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
IDSEL # PIRQ
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
REQ/GNT #DEVICE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
A
A
N/A
D
B
A
C
A
D
A.B
C
EXT USB AD23(EXT.) 4 A,C,D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
A2
D2
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
星期四 八月
LA-1811
Notes List
of
366, 07, 2003
0.7
5
4
+VCC_CORE
3
2
1
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C C
H_REQ#[0..4]<8>
H_ADS#<8>
R230
@62_0402_5%
+VCC_CORE
+VCC_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
VCCA VCCIOPLLConnect to CPU
AE23
VCCIOPLL VCCA
AD20
AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/
TESTHI12 TESTHI12AD25 DPSLP
Commend Commend
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Connect to CPU
Filter
Connect to GND CPU determine
Pull-up 200ohm
to +VCC_CORE
5
1 2
R231
1 2
H_BR0#<8>
H_BPRI#<8>
H_BNR#<8>
H_LOCK#<8>
CK_BCLK<24>
CK_BCLK#<24>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
COMPAT#
float
Pull-up 62ohm
to +VCC_CORE
51_0402_5%
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
CK_BCLK
CK_BCLK#
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VCCIOPLL
VSS
VSS
AF22
AF23
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
J1
K5
J4
J3
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
F3
E3
E2
A10
JP8A
VCC_0
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to GND
Connect to PLD
through 0ohm
4
A12
A14
VCC_1
Commend
A16
VCC_2
VSS_0H1VSS_1H4VSS_2
float
float
float
VCC_3
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
VCC_65C8VCC_66
VCC_84
VCC_85
F9
F11
VCC_67
VCC_68
VCC_69
VCC_70
VCC_77
VCC_78
VCC_79E8VCC_80
E18
E20
+VCC_CORE
1 2
E10
VCC_71D7VCC_72
VCC_73
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
AMP_3-1565030-1_Prescott
E12
E14
E16
12
R1099
47K_0402_5%
3 1
2
H_D#[0..63] <8>H_A#[3..31]<8>
+5VS+5VS
12
1
C
R1100
47K_0402_5%
Q106
2SC2411K_SC59
E3B
H_BOOTSELECT <56>
H_D#0
B21
D#0
H_D#1
B22
D#1
H_D#2
A23
D#2
H_D#3
A25
D#3
H_D#4
C21
D#4
H_D#5
D22
D#5
H_D#6
B24
D#6
H_D#7
C23
D#7
H_D#8
C24
D#8
H_D#9
B25
D#9
H_D#10
G22
H_D#11
H21
H_D#12
C26
H_D#13
D23
H_D#14
J21
H_D#15
D25
H_D#16
H22
H_D#17
E24
H_D#18
G23
H_D#19
F23
H_D#20
F24
H_D#21
E25
H_D#22
F26
H_D#23
D26
H_D#24
L21
H_D#25
G26
H_D#26
H24
H_D#27
M21
H_D#28
L22
H_D#29
J24
H_D#30
K23
H_D#31
H25
H_D#32
M23
H_D#33
N22
H_D#34
P21
H_D#35
M24
H_D#36
N23
H_D#37
M26
H_D#38
N26
H_D#39
N25
H_D#40
R21
H_D#41
P24
H_D#42
R25
H_D#43
R24
H_D#44
T26
H_D#45
T25
H_D#46
T22
H_D#47
T23
H_D#48
U26
H_D#49
U24
H_D#50
U23
H_D#51
V25
H_D#52
U21
H_D#53
V22
H_D#54
V24
H_D#55
W26
H_D#56
Y26
H_D#57
W25
H_D#58
Y23
H_D#59
Y24
H_D#60
Y21
H_D#61
AA25
H_D#62
AA22
H_D#63
AA24
2
Q107
MMBT3904_SOT23
A18
A20
AA10
AA12
AA14
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
Prescott
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
Northwood
AA4
AA7
AA11
AA13
AA9
AA15
AA17
AA19
AA23
AA26
AB10
Prescott
AB12
AB14
AB16
Northwood
MT
AB3
AB6
AB8
AC2
AC5
AC7
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC9
AC17
AC19
AC22
AC25
AD10
AD12
AD14
BOOTSELECT
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VCC_81
VCC_82
VCC_83
F13
F15
F17
F19
AD1
AD4
AD8
AD16
AD18
AD21
AD23
R899 22K_0402_5%
12
R900
100K_0402_5%
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
Pop
Depop
DepopPop
Pop Pop
Pop
Pop
Pop
Pop
Depop
Depop
Depop
Pop
Pop
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-1811
星期四 八月
, 2003
1
0.7
of
466, 07
5
+VCC_CORE
R513 56_0402_5%
R515 56_0402_5%
D D
R519 56_0402_5%
C C
B B
+VCC_CORE
+VCC_CORE
A A
H_FERR#
1 2
H_THERMTRIP#
1 2
R517 130_0402_5%
H_PROCHOT#
1 2
R518 300_0402_5%
H_PWRGOOD
1 2
H_RESET#
1 2
+VCC_CORE
L36 LQG21F4R7N00_0805
1 2
1 2
L37 LQG21F4R7N00_0805
R546
54.9_0603_1%
1 2
If CPU is P4 , Change the resistor
R546 value to 75_0603_1%
R547
54.9_0603_1%
1 2
Close to the ITP
R550
47_0402_5%
12
If CPU is P4 , Change the resistor
R550 value to 39_0402_5%
R552 150_0402_5%
1 2
If CPU is P4 , Change the resistor
R556 value to 27.4_0402_5%
12
R556 47_0402_5%
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
ITP_TDO
ITP_DBRESET#
ITP_TMS
ITP_TDI
ITP_TCK
Place near SB200 (U6)
Place near CPU
+VCC_CORE
Note: Please change to 10uH, DC current
of 100mA parts and close to cap
33U_D2_8M_R35
C544
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>
H_FERR#<26>
H_IGNNE#<26>
H_PWRGOOD<26>
H_STPCLK#<26>
H_INIT#<26>
H_RESET#<8,26>
H_DBSY#<8>
H_DRDY#<8>
H_THERMDA<7>
H_THERMDC<7>
H_THERMTRIP#<7>
R529 56_0402_5%
1 2
R530 56_0402_5%
1 2
1 8
2 7
3 6
4 5
RP137 56_0804_8P4R_5%
1
1
C854
+
+
2
2
33U_D2_8M_R35
CPUCLK_STP#<11,26,56>
H_SMI#<26>
H_INTR<26>
H_NMI<26>
VCCSENSE<56>
VSSSENSE<56>
BSEL0<13,24>
BSEL1<13,24>
H_VCCA
+VCCVID
H_VSSA
1 2
12K_0402_5%
51.1_0402_1%
If CPU is P4 , Change the
resistor R53 9,R540 value to
51.1_0603_1%,or prescott
61.9_0603_1%
R1125
R1017
CK_ITP<24>
CK_ITP#<24>
R539
Close to the CPU
R559
680_0603_5%
1 2
Between the CPU and ITP
ITP_TRST#
5
H_FERR#
H_PWRGOOD
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
12
+3VS
2
4
H_RS#0
H_RS#1
H_RS#2
1 2
0_0402_5%
CK_ITP
CK_ITP#
COMP0
COMP1
12
R540
51.1_0402_1%
12
R993
4.7K_0402_5%
2
Q96
MMBT3904_SOT23
3 1
4
JP8B
F1
RS#0
G5
RS#1
F4
RS#2
AB2
RSP#
J6
TRDY#
C6
A20M#
B6
FERR#
B2
IGNNE#
B5
SMI#
AB23
PWRGOOD
Y4
STPCLK#
D1
LINT0
E5
LINT1
W5
INIT#
AB25
RESET#
H5
DBSY#
H2
DRDY#
AD6
BSEL0
AD5
BSEL1
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AC6
BPM#0
AB5
BPM#1
AC4
BPM#2
Y6
BPM#3
AA5
BPM#4
AB4
BPM#5
D4
TCK
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
AD20
VCCIOPLL
AE23
VCCA
A5
VCCSENSE
A4
VSSSENSE
AF3
VCCVIDLB
AD22
VSSA
AC26
ITP_CLK0
AD26
ITP_CLK1
L24
COMP0
P1
COMP1
CPU_STP#
Q95
MMBT3904_SOT23
3 1
AE11
AE13
AE15
AE17
AE19
AE22
AE24
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_129F8VSS_130
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
J22
G21
G24
4.7K_0402_5%
VID_PWRGD<55,56>
SN74LVC14APWLE_TSSOP14
AE7
J25
R545
3
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
Prescott
VID0
VID1
VID2
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
L23
L26
K21
K24
+3VS
U32A
1
+3VALW
N21
N24
M22
M25
14
P
O2I
G
7
P22
P25
2
G
R23
R26
H_VID_PWRGD
13
D
Q45
S
2N7002 1N_SOT23
3
T21
T24
V23
V26
Y22
U22
U25
+VCC_CORE
12
R_A
12
R558
R_B
100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
Y25
W21
W24
GTL Reference Voltage
Layout note :
R553
49.9_0402_1%
2
1
VID3
VSS_181
Y5
AE5
AE4
AE3
AE2
AE1
VID0
VID1
VID2
VID3
VID4
VID5
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
C546
0.1U_0402_10V6K
F10
F12
F14
VSS_121
VSS_122
VID4
VID5
AD3
1
C547
220P_0402_25V8K
2
F16
F18
VSS_123
VSS_124
VSS_125F2VSS_126
VIDPWRGD
AD2
2
F22
F25
F5
AF26
VSS_127
VSS_128
SKTOCC#
OPTIMIZED/COMPAT#
VCCVID
AMP_3-1565030-1_Prescott
AF4
+VCCVID
1
C932
0.1U_0402_10V6K
2
H_VID_PWRGD
2
R514
1 2
@0_0402_5%
J26
DP#0
K25
DP#1
K26
DP#2
L25
DP#3
AA21
GTLREF0
AA6
GTLREF1
F20
GTLREF2
F6
GTLREF3
AE26
AD24
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
R541 2.43K_0603_1%
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
1 2
H_TESTHI0_1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
1
+CPU_GTLREF
R520 0_0402_5%
1 2
R521 56_0402_5%
1 2
R522 56_0402_5%
1 2
RP136 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
R990 56_0402_5%
1 2
R527 56_0402_5%
1 2
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_PROCHOT# <26,51>
H_CPUSLP# <26>
+VCCVID
VID5<56>
VID4<56>
VID3<56>
VID2<56>
VID1<56>
VID0<56>
Title
Size Document N u mb er Re v
Date: Sheet
星期四 八月
+VCC_CORE
CPU_STP#
VID5
R542 1K_0402_5%
1 2
VID4
R543 1K_0402_5%
1 2
VID3
VID2
VID1
VID0
RP94 1K_1206_8P4R_5%
45
36
27
18
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-1811
, 2003
1
566, 07
CPU_GHI# <27>
+3VS
of
0.7
5
4
3
2
1
+VCC_CORE
1
C131
22U_1206_16V4Z
2
D D
+VCC_CORE
1
C142
22U_1206_16V4Z
2
+VCC_CORE
1
C152
22U_1206_16V4Z
2
C C
+VCC_CORE
1
C154
22U_1206_16V4Z
2
1
C132
22U_1206_16V4Z
2
1
C143
22U_1206_16V4Z
2
1
C153
22U_1206_16V4Z
2
1
C155
22U_1206_16V4Z
2
1
C133
22U_1206_16V4Z
2
1
C144
22U_1206_16V4Z
2
1
C156
22U_1206_16V4Z
2
Place 11 North of Socket(Stuff 6)
1
C134
22U_1206_16V4Z
2
1
C135
22U_1206_16V4Z
2
1
2
Place 12 Insid e So c ke t( S tu f f all)
1
C145
22U_1206_16V4Z
2
1
C146
22U_1206_16V4Z
2
1
2
Place 9 South o f So c ke t( U ns t uf f all)
1
C157
22U_1206_16V4Z
2
1
C158
22U_1206_16V4Z
2
1
2
C136
22U_1206_16V4Z
C147
22U_1206_16V4Z
C159
22U_1206_16V4Z
1
C137
22U_1206_16V4Z
2
1
C148
22U_1206_16V4Z
2
1
C160
22U_1206_16V4Z
2
1
C138
22U_1206_16V4Z
2
1
C149
22U_1206_16V4Z
2
1
C161
22U_1206_16V4Z
2
1
C139
22U_1206_16V4Z
2
1
C150
22U_1206_16V4Z
2
1
C162
22U_1206_16V4Z
2
1
C140
22U_1206_16V4Z
2
1
C151
22U_1206_16V4Z
2
1
C141
22U_1206_16V4Z
2
B B
+VCC_CORE
1
C163
+
470U_D2_2.5VM
2
+VCC_CORE
1
C174
+
470U_D2_2.5VM
2
+VCC_CORE
A A
1
C179
+
470U_D2_2.5VM
2
1
C164
+
470U_D2_2.5VM
2
1
C175
+
470U_D2_2.5VM
2
1
C180
+
470U_D2_2.5VM
2
5
1
C165
+
470U_D2_2.5VM
2
1
C176
+
@330U_D2E_2.5VM
2
1
C181
+
470U_D2_2.5VM
2
1
C166
+
@330U_D2E_2.5VM
2
1
C177
+
470U_D2_2.5VM
2
1
C182
+
470U_D2_2.5VM
2
4
1
C167
+
470U_D2_2.5VM
2
1
C178
+
470U_D2_2.5VM
2
1
C183
+
@470U_D2_2.5VM
2
3
Place Insi de S oc ket around the edge
+VCC_CORE
1
C168
0.22U_0603_10V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C169
0.22U_0603_10V7K
2
1
C170
0.22U_0603_10V7K
2
1
C171
0.22U_0603_10V7K
2
2
1
C172
0.22U_0603_10V7K
2
1
C173
0.22U_0603_10V7K
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Decoupling
LA-1811
星期四 八月
, 2003
1
0.7
of
666, 07
5
4
3
2
1
Thermal Sensor ADM1032AR
+3VALW
W=15mil
12
R283
D D
@10K_0402_5%
C253
2200P_0402_25V7K
1
2
2
1
H_THERMDA
H_THERMDC
C251
0.1U_0402_10V6K
U8
1
VDD
2
D+
3
DTHERM#4GND
ADM1032AR_SOP8
SCLK
SDATA
ALERT#
Address:1001_100X
H_THERMDA
H_THERMDC
8
7
6
5
H_THER MDA <5>
H_TH ERMDC <5>
EC_SMC_2 <46>
EC_SMD_2 <46>
+VCC_CORE
C C
EN_FAN1<46> EN_FAN2<46>
B B
R286 300_0402_5%12C256 @1U_0603_10V6K
H_THERMTRIP#<5>
R915
10K_0402_5%
H_THERMTRIP#
FAN CONN.1 FAN CONN. 2
+12VALW
8
U10A
3
+IN
2
-IN
1 2
R917
P
OUT
G
LM358A_SO8
4
8.2K_0402_5%
1
R913 100_0402_5%
EN_DFAN2 EN_FAN2
12
2
B
3
E
1 2
12
1
C
Q17
2SC2411K_SC59
2
B
2
C840
0.1U_0402_10V6K
1
D25
1N4148_SOD80
R919 10K_0402_5%
1 2
+3VS
MAINPWON <50,51,53>
+5VS
1SS355_SOD323
1
C
FMMT619_SOT23
Q90
E
3
FAN1 FAN2
12
C265
10U_0805_10V4Z
12
D67
1
1
C855
2
2
@1000P_0402_16V7K
12
C838
10U_0805_16V4Z
JP10
ACES_85205-0300
1
C907
@1000P_0402_16V7K
2
U10B
5
+IN
6
12
R916
10K_0402_5%
1
2
3
-IN
1 2
R918
7
OUT
LM358A_SO8
8.2K_0402_5%
R914 100_0402_5%
1 2
2
C841
0.1U_0402_10V6K
1
+3VS
FANSPEED2<46>FANSPEED1<46>
+5VS
1
C
FMMT619_SOT23
2
B
Q91
E
3
12
D26
1N4148_SOD80
10U_0805_10V4Z
R920 10K_0402_5%
1 2
C266
12
D68
1SS355_SOD323
1
2
@1000P_0402_16V7K
1
C839
10U_0805_16V4Z
2
1
C856
2
1
2
JP11
1
2
3
ACES_85205-0300
C908
@1000P_0402_16V7K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Thermal Sensor&FAN CTRL
LA-1811
星期四 八月
, 2003
1
0.7
of
766, 07
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
U27A
1U_0603_10V6K
1 2
C361
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF
D D
H_ADSTB#0<5>
C C
H_ADSTB#1<5>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<5>
H_DBSY#<5>
H_BR0#<4>
H_LOCK#<4>
H_RESET#<5,26>
H_RS#2<5>
SUS_STAT#<27>
NB_RST#<17,26,39>
NB_PWRGD<48>
1 2
1 2
L34
1 2
H_RS#1<5>
H_RS#0<5>
H_TRDY#<5>
H_HIT#<4>
H_HITM#<4>
0.1U_0402_10V6K
C974
12
--> 412_0402_1%
R380 412_0402_1%
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+VCC_CORE
PLACE CLOSE TO U27 Ball
W28, USE 20/20
1 2
12
WIDTH/SPACE
1
C362
1U_0603_10V6K
2
1
C363
220P_0402_25V8K
2
C363 CLOSE
TO Ball W28
B B
R383
49.9_0402_1%
R384
100_0402_1%
1 2
+VCC_CORE
+1.8VS
R381 24.9_0402_1%
R382 49.9_0402_1%
HB-1M2012-121JT03_0805
12
R385
4.7K_0402_5%
M28
P25
M25
N29
N30
M26
N28
P29
P26
R29
P30
P28
N26
N27
M29
N25
R26
L28
L29
R27
U30
T30
R28
R25
U25
T28
V29
T26
U29
U26
V26
T25
V25
U27
U28
T29
L27
K25
H26
J27
L26
G27
F25
K26
A17
G25
G26
J25
F26
J26
H25
A9
AH5
AG5
C7
V28
W29
H23
J23
W28
Y29
Y28
B17
216RC300M_BGA_718
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD
CPU_COMP_N
CPU_COMP_P
CPVDD
CPVSS
CPU_VREF
THERMALDIODE_N
THERMALDIODE_P
TESTMODE
PART 1 OF 6
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
MISC.
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_DSTBN0#
CPU_DSTBP0#
CPU_DSTBN1#
AGTL+ I/F
CPU_DSTBP1#
PENTIUM
CPU_DSTBN2#
CPU_DSTBP2#
CPU_DSTBN3#
CPU_DSTBP3#
IV
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_D#[0..63] <4>
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
H_D#0
L30
H_D#1
K29
H_D#2
J29
H_D#3
H28
H_D#4
K28
H_D#5
K30
H_D#6
H29
H_D#7
J28
H_D#8
F28
H_D#9
H30
H_D#10
E30
H_D#11
D29
H_D#12
G28
H_D#13
E29
H_D#14
D30
H_D#15
F29
H_DINV#0
E28
H_DSTBN#0
G30
H_DSTBP#0
G29
H_D#16
B26
H_D#17
C30
H_D#18
A27
H_D#19
B29
H_D#20
C28
H_D#21
C29
H_D#22
B28
H_D#23
D28
H_D#24
D26
H_D#25
B27
H_D#26
C26
H_D#27
E25
H_D#28
E26
H_D#29
A26
H_D#30
B25
H_D#31
C25
H_DINV#1
A28
H_DSTBN#1
D27
H_DSTBP#1
E27
H_D#32
F24
H_D#33
D24
H_D#34
E23
H_D#35
E24
H_D#36
F23
H_D#37
C24
H_D#38
B24
H_D#39
A24
H_D#40
F21
H_D#41
A23
H_D#42
B23
H_D#43
C22
H_D#44
B22
H_D#45
C21
H_D#46
E21
H_D#47
D22
H_DINV#2
D23
H_DSTBN#2
E22
H_DSTBP#2
F22
H_D#48
B21
H_D#49
F20
H_D#50
A21
H_D#51
C20
H_D#52
E20
H_D#53
D20
H_D#54
A20
H_D#55
D19
H_D#56
C18
H_D#57
B20
H_D#58
E18
H_D#59
B19
H_D#60
D18
H_D#61
B18
H_D#62
C17
H_D#63
A18
H_DINV#3
F19
H_DSTBN#3
E19
H_DSTBP#3
F18
H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>
H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>
H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
+VCC_CORE
22U_1206_16V4Z_V1
A A
5
4
C364
0.1U_0402_10V6K
1
1
C366
C365
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C367
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C368
2
1
C369
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C370
2
2
1
C371
2
0.1U_0402_10V6K
1
C372
0.1U_0402_10V6K
2
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGTL+
星期四 八月
LA-1811
of
866, 07, 2003
1
0.7
5
U27B
DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4
D D
DDRA_RAS#<14,15,16>
DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
C C
DDRA_CLK0<14>
DDRA_CLK0#<14>
DDRA_CLK1<14>
DDRA_CLK1#<14>
DDRA_CLK3<15>
DDRA_CLK3#<15>
DDRA_CLK4<15>
DDRA_CLK4#<15>
DDRA_CKE_R0<14,16>
DDRA_CKE_R1<14,16>
DDRA_CKE_R2<15,16>
DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>
DDRA_CS#1<14,16>
DDRA_CS#2<15,16>
DDRA_CS#3<15,16>
L35
B B
A A
+1.8VS
C857
0.1U_0402_10V6K
1 2
HB-1M2012-121JT03_0805
+2.5V
1
1
C858
2
2
@0.1U_0402_10V6K
@0.1U_0402_10V6K
C859
5
DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15
DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK3
DDRA_CLK3#
DDRA_CLK4
DDRA_CLK4#
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
C375
1 2
1U_0603_10V6K
1
C860
2
@0.1U_0402_10V6K
MPVDD
MPVSS
1
2
DDR_VREF
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AJ8
AF9
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
0.1U_0402_10V6K
0.1U_0402_10V6K
L
1
C861
@0.1U_0402_10V6K
2
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
216RC300M_BGA_718
2
C376
1
DDR_VREF
2
C377
1
DDR_VREF trace width of
20mils and space
20mils(min)
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM I/F
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
+2.5V+2.5V
12
R408
1K_0603_1%
12
R409
1K_0603_1%
4
DDRA_DQ0
AG6
DDRA_DQ1
AJ7
DDRA_DQ2
AJ9
DDRA_DQ3
AJ10
DDRA_DQ4
AJ6
DDRA_DQ5
AH6
DDRA_DQ6
AH8
DDRA_DQ7
AH9
DDRA_DQ8
AE7
DDRA_DQ9
AE8
DDRA_DQ10
AE12
DDRA_DQ11
AF12
DDRA_DQ12
AF7
DDRA_DQ13
AF8
DDRA_DQ14
AE11
DDRA_DQ15
AF11
DDRA_DQ16
AJ12
DDRA_DQ17
AH12
DDRA_DQ18
AH14
DDRA_DQ19
AH15
DDRA_DQ20
AH11
DDRA_DQ21
AJ13
DDRA_DQ22
AJ15
DDRA_DQ23
AJ16
DDRA_DQ24
AF18
DDRA_DQ25
AG20
DDRA_DQ26
AG21
DDRA_DQ27
AF22
DDRA_DQ28
AF19
DDRA_DQ29
AF20
DDRA_DQ30
AE22
DDRA_DQ31
AF23
DDRA_DQ32
AJ21
DDRA_DQ33
AJ22
DDRA_DQ34
AJ24
DDRA_DQ35
AK25
DDRA_DQ36
AH21
DDRA_DQ37
AH22
DDRA_DQ38
AH24
DDRA_DQ39
AJ25
DDRA_DQ40
AK26
DDRA_DQ41
AK27
DDRA_DQ42
AJ28
DDRA_DQ43
AH29
DDRA_DQ44
AH25
DDRA_DQ45
AJ26
DDRA_DQ46
AJ29
DDRA_DQ47
AH30
DDRA_DQ48
AF29
DDRA_DQ49
AE29
DDRA_DQ50
AB28
DDRA_DQ51
AA28
DDRA_DQ52
AE28
DDRA_DQ53
AD28
DDRA_DQ54
AC29
DDRA_DQ55
AB29
DDRA_DQ56
AC26
DDRA_DQ57
AB25
DDRA_DQ58
Y26
DDRA_DQ59
W26
DDRA_DQ60
AE26
DDRA_DQ61
AD26
DDRA_DQ62
AA26
DDRA_DQ63
Y27
C373 0.47U_0603_16V7K
AF6
1 2
C374 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
C378
100U_D2_10VM
4
Group 6 sweep Group 7
R405 49.9_0402_1%
1 2
+2.5V
1
1
+
C379
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C380
2
0.1U_0402_10V6K
C381
3
DDRA_DQ8
DDRA_DQ12
DDRA_DQ9
DDRA_DQ13
DDRA_DQ10
DDRA_DQ14
DDRA_DQ11
DDRA_DQ15
DDRA_DQS1
DDRA_DM1
DDRA_DQ0
DDRA_DQ4
DDRA_DQ1
DDRA_DQ3
DDRA_DQ7
DDRA_DQ2
DDRA_DQ6
DDRA_DQS0 DDRA_SD QS0
DDRA_DM0
DDRA_DQ20
DDRA_DQ16
DDRA_DQ21
DDRA_DQ17
DDRA_DQ18
DDRA_DQ22
DDRA_DQ19
DDRA_DQ23
DDRA_DM2 DDRA_SDM2
DDRA_DQS2
DDRA_DQ24
DDRA_DQ28
DDRA_DQ25
DDRA_DQ29
DDRA_DQ26
DDRA_DQ30
DDRA_DQ27
DDRA_DQ31
DDRA_DQS3 DDRA_SD QS3
DDRA_DM3 DDRA_SDM3
0.1U_0402_10V6K
1
C382
2
0.1U_0402_10V6K
1
1
C383
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP28
1 4
2 3
0_0404_4P2R_5%
RP31
1 4
2 3
0_0404_4P2R_5%
RP34
1 4
2 3
0_0404_4P2R_5%
RP37
1 4
2 3
0_0404_4P2R_5%
R387 0_0402_5%
R388 0_0402_5%
RP40
1 4
2 3
0_0404_4P2R_5%
RP43
1 4
2 3
0_0404_4P2R_5%
RP45
1 4
2 3
0_0404_4P2R_5%
RP47
1 4
2 3
0_0404_4P2R_5%
R394 0_0402_5%
R397 0_0402_5%
RP49
1 4
2 3
0_0404_4P2R_5%
RP51
1 4
2 3
0_0404_4P2R_5%
RP53
1 4
2 3
0_0404_4P2R_5%
RP55
1 4
2 3
0_0404_4P2R_5%
R403 0_0402_5%
R406 0_0402_5%
RP57
1 4
2 3
0_0404_4P2R_5%
RP59
1 4
2 3
0_0404_4P2R_5%
RP61
1 4
2 3
0_0404_4P2R_5%
RP63
1 4
2 3
0_0404_4P2R_5%
R412 0_0402_5%
R415 0_0402_5%
1
C384
C385
2
0.1U_0402_10V6K
DDRA_SDQ8
DDRA_SDQ12
DDRA_SDQ9
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQS1
12
DDRA_SDM1
12
DDRA_SDQ0
DDRA_SDQ4
DDRA_SDQ1
DDRA_SDQ5DDRA_DQ5
DDRA_SDQ3
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ6
12
DDRA_SDM0
12
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
12
DDRA_SDQS2
12
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQ26
DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ31
12
12
0.1U_0402_10V6K
1
C386
2
1
C387
2
0.1U_0402_10V6K
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37
DDRA_DQ33
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35
DDRA_DQS4
DDRA_DM4
DDRA_DQ40
DDRA_DQ45
DDRA_DQ41
DDRA_DQ46
DDRA_DQ42
DDRA_DQ43
DDRA_DQS5
DDRA_DM5
DDRA_DQ60 DDRA_SDQ60
DDRA_DQ57 DDRA_SDQ57
DDRA_DQ58 DDRA_SDQ58
DDRA_DQ59 DDRA_SDQ59
DDRA_DQS7
DDRA_DM7
DDRA_DQ52 DDRA_SDQ52
DDRA_DQ49 DDRA_SDQ49
DDRA_DQ50
DDRA_DQ54
DDRA_DQ51
DDRA_DQ55
0.1U_0402_10V6K
1
1
C388
2
2
0.1U_0402_10V6K
2
RP27
1 4
2 3
0_0404_4P2R_5%
RP30
1 4
2 3
0_0404_4P2R_5%
RP33
1 4
2 3
0_0404_4P2R_5%
RP36
1 4
2 3
0_0404_4P2R_5%
R386 0_0402_5%
R389 0_0402_5%
RP41
1 4
2 3
0_0404_4P2R_5%
RP44
1 4
2 3
0_0404_4P2R_5%
RP46
1 4
2 3
0_0404_4P2R_5%
RP48
1 4
2 3
0_0404_4P2R_5%
R395 0_0402_5%
R398 0_0402_5%
RP50
1 4
2 3
0_0404_4P2R_5%
RP52
1 4
2 3
0_0404_4P2R_5%
RP54
1 4
2 3
0_0404_4P2R_5%
RP56
1 4
2 3
0_0404_4P2R_5%
R404 0_0402_5%
R407 0_0402_5%
RP58
1 4
2 3
0_0404_4P2R_5%
RP60
1 4
2 3
0_0404_4P2R_5%
RP62
1 4
2 3
0_0404_4P2R_5%
RP64
1 4
2 3
0_0404_4P2R_5%
R413 0_0402_5%
R416 0_0402_5%
0.1U_0402_10V6K
1
C390
C389
2
2
12
12
12
12
12
12
12
12
1
2
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ38
DDRA_SDQ34
DDRA_SDQ39
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ44DDRA_DQ44
DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47DDRA_DQ47
DDRA_SDQ43
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQ56DDRA_DQ56
DDRA_SDQ61DDRA_DQ61
DDRA_SDQ62DDRA_DQ62
DDRA_SDQ63DDRA_DQ63
DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ48DDRA_DQ48
DDRA_SDQ53DDRA_DQ53
DDRA_SDQ50
DDRA_SDQ54
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQS6DDRA_DQS6
DDRA_SDM6DDRA_DM6
1
C391
0.1U_0402_10V6K
2
1
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7] <14,15,16>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-DDR I/F
星期四 八月
LA-1811
of
966, 07, 2003
1
0.7
5
4
3
2
1
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
D D
C C
?
B B
47U_B_6.3VM
A A
47U_B_6.3VM
A_PAR<13,26>
A_STROBE#<26>
A_ACAT#<26>
A_END#<26>
PCI_PIRQA#<17,26,31,35,36>
Rb
Rc
+1.5VS +3VS
C551
+1.5VS
C552
+1.5VS+1.5VS
R576
324_0402_1%
1 2
AGPREF_8X
R577
100_0402_1%
1 2
1
1
+
C553
2
2
0.1U_0402_10V6K
1
1
+
C570
2
2
0.1U_0402_10V6K
A_DEVSEL#<26>
A_SBREQ#<26>
A_SBGNT#<26>
AGP_GNT#<17>
AGP_REQ#<17>
AGP8X_DET#<17>
VREF_8X_IN<17>
R575
PLACE CLOSE TO
CONNECTOR
0.1U_0402_10V6K
C554
0.1U_0402_10V6K
C571
5
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
1 2
1 2
Ra
1 2
169_0402_1%
1
C555
2
0.1U_0402_10V6K
1
C572
2
0.1U_0402_10V6K
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
C550
1 2
0.1U_0402_10V6K
AGP_COMP
+3VS
R945
NAGP@47K_0402
1 2
0.1U_0402_10V6K
1
1
C556
2
2
0.1U_0402_10V6K
1
C573
2
R1005 0_0402_5%
A_OFF#<26>
+3VS
AGP8X_DET#
1
2
U27C
AK5
ALINK_AD0
AJ5
ALINK_AD1
AJ4
ALINK_AD2
AH4
ALINK_AD3
AJ3
ALINK_AD4
AJ2
ALINK_AD5
AH2
ALINK_AD6
AH1
ALINK_AD7
AG2
ALINK_AD8
AG1
ALINK_AD9
AG3
ALINK_AD10
AF3
ALINK_AD11
AF1
ALINK_AD12
AF2
ALINK_AD13
AF4
ALINK_AD14
AE3
ALINK_AD15
AE4
ALINK_AD16
AE5
ALINK_AD17
AE6
ALINK_AD18
AC2
ALINK_AD19
AC4
ALINK_AD20
AB3
ALINK_AD21
AB2
ALINK_AD22
AB5
ALINK_AD23
AB6
ALINK_AD24
AA2
ALINK_AD25
AA4
ALINK_AD26
AA5
ALINK_AD27
AA6
ALINK_AD28
Y3
ALINK_AD29
Y5
ALINK_AD30
Y6
ALINK_AD31
AG4
ALINK_CBE#0
AE2
ALINK_CBE#1
AC3
ALINK_CBE#2
AA3
ALINK_CBE#3
AD5
PCI_PAR/ALINK_NC
AC6
PCI_FRAME#/ALINK_STROBE#
AC5
PCI_IRDY#/ALINK_ACAT#
AD2
PCI_TRDY#/ALINK_END#
W4
INTA#
AD3
ALINK_DEVSEL#
AD6
PCI_STOP#/ALINK_OFF#
W5
ALINK_SBREQ#
W6
ALINK_SBGNT#
R570
V5
PCI_REQ#0/ALINK_NC
V6
PCI_GNT#0/ALINK_NC
K5
AGP2_GNT#/AGP3_GNT
K6
AGP2_REQ#/AGP3_REQ
M5
AGP8X_DET#
J6
AGP_VREF/TMDS_VREF
J5
AGP_COMP
216RC300M_BGA_718
0.1U_0402_10V6K
1
C557
2
0.1U_0402_10V6K
Ra
Rb
Rc
1
C559
C558
2
0.1U_0402_10V6K
0.1U_0402_10V6K
PART 3 OF 6
8X(M9+M10@)
169_0402_1%
324_0402_1%
100_0402_1%
0.1U_0402_10V6K
1
1
C560
2
2
+1.5VS
C574
1
C575
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
4
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
PCI Bus 0 / A-Link I/F
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
4X(NAGP@)
52.1_0402_1%
1K_0402_1%
1K_0402_1%
10U_0805_10V4Z
1
C561
2
0.1U_0402_10V6K
1
C576
2
0.1U_0402_10V6K
C577
C632
0.1U_0402_10V6K
1
C578
2
1
C562
2
0.1U_0402_10V6K
1
C937
2
0.1U_0402_10V6K
Note: PLACE C L OS E TO U 27 (N B R C300M)
L
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP2_CBE#2/AGP3_CBE2
AGP_PAR
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
AGP_ST0
AGP_ST1
AGP_ST2
0.1U_0402_10V6K
1
1
C563
C564
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C938
C939
2
2
0.1U_0402_10V6K
AGP_AD0
Y2
AGP_AD1
W3
AGP_AD2
W2
AGP_AD3
V3
AGP_AD4
V2
AGP_AD5
V1
AGP_AD6
U1
AGP_AD7
U3
AGP_AD8
T2
AGP_AD9
R2
AGP_AD10
P3
AGP_AD11
P2
AGP_AD12
N3
AGP_AD13
N2
AGP_AD14
M3
AGP_AD15
M2
AGP_AD16
L1
AGP_AD17
L2
AGP_AD18
K3
AGP_AD19
K2
AGP_AD20
J3
AGP_AD21
J2
AGP_AD22
J1
AGP_AD23
H3
AGP_AD24
F3
AGP_AD25
G2
AGP_AD26
F2
AGP_AD27
F1
AGP_AD28
E2
AGP_AD29
E1
AGP_AD30
D2
AGP_AD31
D1
AGP_SBSTB
E5
AGP_SBSTB#
E6
AGP_ADSTB0
T3
AGP_ADSTB0#
U2
AGP_ADSTB1
G3
AGP_ADSTB1#
H2
AGP_CBE#0
R3
AGP_CBE#1
M1
AGP_CBE#2
L3
AGP_CBE#3
H1
AGP_IRDY#
P5
AGP_TRDY#
R6
AGP_STOP#
T6
AGP_PAR
T5
AGP_FRAME#
P6
AGP_DEVSEL#
R5
AGP_DBI_HI/PIPE#
C1
AGP_DBI_LO
D3
AGP_RBF#
N6
AGP_WBF#
N5
AGP_SBA0
C3
AGP_SBA1
C2
AGP_SBA2
D4
AGP_SBA3
E4
AGP_SBA4
F6
AGP_SBA5
F5
AGP_SBA6
G6
AGP_SBA7
G5
AGP_ST0
L6
AGP_ST1
M6
AGP_ST2
L5
1
C566
2
0.1U_0402_10V6K
1
C941
2
0.1U_0402_10V6K
3
0.1U_0402_10V6K
1
C567
2
0.1U_0402_10V6K
1
C942
2
0.1U_0402_10V6K
1
C565
2
0.1U_0402_10V6K
1
C940
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>
AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>
1
C568
2
0.1U_0402_10V6K
1
C943
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C944
2
1
C569
2
1
C945
2
0.1U_0402_10V6K
PIR BOM 92.06.23
@0.1U_0402_10V6K
C548
@10U_0805_6.3V6M
@0_0402_5%
+1.5VS
C947
@0.01U_0402_16V7Z
0.1U_0402_10V6K
1
1
C946
2
2
@0_0402_5%
L
@0.01U_0402_16V7Z
1
2
AGPAND LVDS MUXED SIGNALS
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA7 LVDS_SSIN
AGP_SBA1
AGP_SBA0
C549
R568
R560 NAPG@0_0402_5%
R561 NAPG@0_0402_5%
R562 NAPG@0_0402_5%
R563 NAPG@0_0402_5%
R564 @0_0402_5%
R565 @0_0402_5%
R994 NAPG@0_0402_5%
R995 NAPG@0_0402_5%
12
12
R569
@0_0402_5%
S0
S1
12
12
R572
@SM561BS_SO8
R573
@0_0402_5%
Note: PLACE C L OS E TO U 27 (N B R C300M)
ATI request
@0.01U_0402_16V7Z
1
1
C864
C948
2
2
C949
2
@0.01U_0402_16V7Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@0_0402_5%
R1086
2
U33
VDD
1
Xin/CLK
7
S0
6
S1
LVDS SPREAD SPECTRUM
1
C950
2
@0.01U_0402_16V7Z
Title
Size Document Number Rev
Date: Sheet
4
SSCLK
8
Xout
5
SSCC
VSS
3
R1088
@0_0402_5%
@0.01U_0402_16V7Z
1
1
C935
2
2
@0.01U_0402_16V7Z
星期四 八月
ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_STP# <17,27>
AGP_BUSY# <17,27>
LVDS_SSOUTAGP_SBA6
12
12
C936
DDC_DAT
DDC_CLK
L38
12
R567
@0_0402_5%
1
12
2
R574
@0_0402_5%
1
2
@BLM21P300S_0805
R1144 @0_0402_5%
C952
@10P_0402_25V8K
@0.01U_0402_16V7Z
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
1 2
1 2
R1087
1 2
@0_0402_5%
1
C933
2
@0.01U_0402_16V7Z
DDC_DAT <17,25>
DDC_CLK <17,25>
+3VS
LVDS_SSOUT
LVDS_SSIN
SSIN <17>
@0.01U_0402_16V7Z
1
C934
2
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-1811
1
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_CBE#[0..3] <17>
AGP_ST[0..2] <17>
SSOUT <17>
1
C951
2
of
10 66, 07, 2003
0.7
5
4
3
2
1
D D
+2.5VS
12
L59
KC FBM-L11-201209-221LMAT_0805
1
C587
0.1U_0402_10V6K
KC FBM-L11-201209-221LMAT_0805
L60
+1.8VS
C C
REFCLK1_NB<24>
CLK_AGP_66M
12
R588
@10_0402_5%
C601
@15P_0402_50V8J
CLK_MEM_66M
B B
12
R591
@10_0402_5%
C603
@15P_0402_50V8J
L
CRMA_R
LUMA_R TV_LUMA
L
CRT_R<17,25>
CRT_G<17,25>
CRT_B<17,25>
A A
CRT_HSYNC<17,25>
CRT_VSYNC<17,25>
DDCCLK_R
DDCDATA_R
5
1 2
0.1U_0402_10V6K
L61
+1.8VS
KC FBM-L11-201209-221LMAT_0805
+1.8VS
KC FBM-L11-201209-221LMAT_0805
1
C588
2
1 2
0.1U_0402_10V6K
L62
1 2
10U_0805_16V4Z
R585 0_0402_5%
1 2
R587
68_0402_5%
wait 1% new part
+3VS
X2
4
VCC
1
ST
1
NAGP@27MHZ_20P_6N
C602
NAGP@0.1U_0402_16V7K
2
1
1
C590
C589
0.1U_0402_10V6K
2
2
1
C591
2
0.1U_0402_10V6K
R584 715 _0402_1%
1 2
12
3
OUT
2
GND
Note: PLACE CLOSE TO U27 (NB CHIP)
R597 NAPG@0_0402_5%
1 2
R598 NAPG@0_0402_5%
1 2
R599 NAPG@0_0402_5%
1 2
TV_CRMA
TV_COMPSCOMPS_R
Note: PLACE CLOSE TO U6 (VGA CHIP)
CRT_R
R594 NAPG@0_0402_5%
1 2
R595 NAPG@0_0402_5%
1 2
CRT_B BLUE_R
R596 NAPG@0_0402_5%
1 2
CRT_HSYNC
CRT_VSYNC
RP103
1 4
2 3
NAGP@0_4P2R_0402_5%
RP104
14
NAGP@0_4P2R_0402_5%
23
HSYNC_R
VSYNC_R
3VDDCCL
3VDDCDA
RED_R
GREEN_RCRT_G
4
3VDDCCL <17,25>
3VDDCDA <17,25>
2
1
C592
2
CLK_NB_BCLK<24>
CLK_NB_BCLK#<24>
CLK_AGP_66M<24>
CLK_MEM_66M<24>
27M_TV 27M_TV_R
R592 NAGP@22_0402_5%
PLLVDD_18
1
PLLVSS_18
C593
0.1U_0402_10V6K
2
RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_BCLK
CLK_NB_BCLK#
CLK_AGP_66M
CLK_MEM_66M
TV_CRMA <17,41,48>
TV_LUMA <17,41,48>
TV_COMPS <17,41,48>
L58
1 2
FBM-11-160808-121-T_0603
U27D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
D8
ALINK_CLK
B2
AGPCLKOUT
B3
AGPCLKIN
A3
EXT_MEM_CLK
D7
USBCLK
B7
REF27
C5
OSC
216RC300M_BGA_718
L
+3VS
1
C586
0.1U_0402_10V6K
2
PART 4 OF 6
LVDS
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
C_R
Y_G
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
CRMA_R
E15
LUMA_R
C15
COMPS_R
D15
DDCCLK_R
D6
DDCDATA_R
C6
D5
A8
B8
R590 1K_0402_5%
TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
Q97
@2N7002 1N_SOT23
D
1 3
R589 @0_0402_5%
C594
0.1U_0402_10V6K
C598
0.1U_0402_10V6K
S
G
2
1
2
0.1U_0402_10V6K
1
2
CPUCLK_STP#
0.1U_0402_10V6K
1
C596
C595
2
10U_0805_16V4Z
1
C600
C599
2
10U_0805_16V4Z
+3VS
Note: PLACE CLOSE TO U27 (NB CHIP)
RC300M_X1
@1M_0402_1%
RC300M_X2
12
R593
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C604
12
@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201
C605
@18P_0402_50V8K
2
KC FBM-L11-201209-221LMAT_0805
1 2
L63
1
2
KC FBM-L11-201209-221LMAT_0805
1 2
L64
1
2
CPUCLK_STP# <5,26,56>
PCI_RST# <26,30,31,34,35,36,43,46>
Title
Size Document Number Rev
Date: Sheet
星期四 八月
+1.8VS
+1.8VS
Compal Electronics, Inc.
ATI RC300M-VIDEO I/F
LA-1811
1
0.7
of
11 66, 07, 2003
5
4
3
2
1
+1.5VS +2.5V
D D
C C
B B
+VCC_CORE
+3VS
U27E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
216RC300M_BGA_718
PART 5 OF 6
CORE PWR
CPU I/F PWRALINK PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
MEM I/F PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
R418
1 2
R419 NAGP@0_0603_5%
1 2
+1.8VS
M9-M10@0_0603_5%
+1.5VS
+3VS
U27F
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7
VSS
216RC300M_BGA_718
PART 6 OF 6
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8
+1.8VS
C579
10U_0805_10V4Z
A A
5
4
1
C580
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C581
2
1
C582
2
0.1U_0402_10V6K
1
1
C583
0.1U_0402_10V6K
2
2
Compal Electronics, Inc.
ATI RC300M-POWER
星期四 八月
LA-1811
0.7
of
12 66, 07, 2003
1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
5
4
3
2
1
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
R420 10K_0402_5%
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
5
R422 4.7K_0402_5%
R425 4.7K_0402_5%
R427 10K_0402_5%
1 2
R429 @4. 7K_0402_5%
R430 @10K_0402_5%
1 2
R431 4.7K_0402_5%
R434 10K_0402_5%
1 2
R435 @4. 7K_0402_5%
R438 10K_0402_5%
1 2
R440 @4. 7K_0402_5%
R443 10K_0402_5%
1 2
R444 @4. 7K_0402_5%
R448 10K_0402_5%
1 2
R452 10K_0402_5%
1 2
R454 @4. 7K_0402_5%
R457 @4. 7K_0402_5%
R461 10K_0402_5%
1 2
R462 @4. 7K_0402_5%
R464 @4. 7K_0402_5%
R465 4.7K_0402_5%
R466 @4. 7K_0402_5%
R467 @4. 7K_0402_5%
R468 @4. 7K_0402_5%
R469 @4. 7K_0402_5%
1 2
R424 10K_0402_5%
1 2
2 1
D85
RB751V_SOD323
2 1
D86
RB751V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 <5,24>
+3VS
BSEL0 <5,24>
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcS hortReset#
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3: NOT USED
A_CBE#0 :NO USED
4
A_AD[31..30 ] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
A_CBE#[0..3]
A_AD18
A_AD17
A_PAR<10,26>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
R421 @4. 7K_0402_5%
R423 4.7K_0402_5%
R426 @4. 7K_0402_5%
R428 4.7K_0402_5%
A_PAR
R463 @4. 7K_0402_5%
R460 4.7K_0402_5%
+3VS
+3VS
+3VS
2
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
0: DEBUG MODE
1: NORMAL
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-SYSTEM STRAP
星期四 八月
LA-1811
of
13 66, 07, 2003
1
0.7
5
DDRA_SDQ[0..63]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
D D
C C
B B
Group 0 sweep Group 1
Group 6 sweep Group 7
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
3
+2.5V
JP24
1
VREF
3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_CLK0<9>
DDRA_CLK0#<9>
DDRA_CKE_R1<9,16>
DDRA_WE#<9,15,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE_R1 DDRA_CKE_R0
DDRA_ADD12
DDRA_ADD9
DDRA_ADD7
DDRA_ADD5
DDRA_ADD3
DDRA_ADD1
DDRA_ADD10
DDRA_ADD13
DDRA_WE#
DDRA_CS#0 DDRA_CS#1
DDRA_ADD15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<15,24,27>
SMB_CK_CLK2<15,24,27>
+3VS
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
AMP_1565918-1
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
DIMM0
REVERSE
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
S1#
DU
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
DU
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_ADD11
DDRA_ADD8
DDRA_ADD6
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_ADD14
DDRA_RAS#
DDRA_CAS#
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
2
L
DDRA_CKE_R0 <9,16>
DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>
DDRA_CLK1# <9>
DDRA_CLK1 <9>
Group 6 sweep Group 7
+2.5V+2.5V
C411
0.1U_0402_10V6K
C412
0.1U_0402_10V6K
12
12
2
1
DDRA_VREF
2
1
DDRA_VREF trace width of
20mils and space 20mils(min)
R472
1K_0603_1%
R473
1K_0603_1%
1
System Memory Decoupling caps
+2.5V
1
C413
0.1U_0402_10V6K
2
A A
+2.5V
1
2
5
C426
0.1U_0402_10V6K
1
C414
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
C415
0.1U_0402_10V6K
2
1
C428
0.1U_0402_10V6K
2
1
C416
0.1U_0402_10V6K
2
1
C429
0.1U_0402_10V6K
2
1
C417
0.1U_0402_10V6K
2
1
C430
0.1U_0402_10V6K
2
1
C418
0.1U_0402_10V6K
2
1
C431
0.1U_0402_10V6K
2
4
1
C419
0.1U_0402_10V6K
2
1
C432
0.1U_0402_10V6K
2
1
C420
0.1U_0402_10V6K
2
1
C433
0.1U_0402_10V6K
2
1
C421
0.1U_0402_10V6K
2
1
C434
0.1U_0402_10V6K
2
1
C422
0.1U_0402_10V6K
2
1
C435
0.1U_0402_10V6K
2
3
1
C423
0.1U_0402_10V6K
2
1
C436
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C424
0.1U_0402_10V6K
2
1
C437
0.1U_0402_10V6K
2
1
C425
10U_0805_6.3V6M
2
1
C438
10U_0805_6.3V6M
2
Title
Size Document N u mb er Re v
2
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT1
LA-1811
星期四 八月
, 2003
1
0.7
of
14 66, 07
5
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
DDRA_SDM[0..7]<9,14,16>
D D
C C
B B
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
Group 0 sweep Group 1
DDRA_CLK3<9>
DDRA_CLK3#<9>
Group 6 sweep Group 7
+2.5V
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE3
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#2
DDRA_SMA15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<14,24,27>
SMB_CK_CLK2<14,24,27>
+3VS
JP23
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
AMP_1565917-1
4
DIMM1
STANDARD
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
3
C392
0.1U_0402_10V6K
DDRB_VREF
C393
0.1U_0402_10V6K
+2.5V+2.5V
12
12
DDRA_CKE_R3<9,16>
R470
1K_0603_1%
R471
1K_0603_1%
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
DDRA_SMA9
DDRA_SMA12
DDRA_SMA5
DDRA_SMA7
DDRA_SMA1
DDRA_SMA3
DDRA_SMA13
DDRA_SMA10
DDRA_WE# DDRA_SWE#
DDRA_CS#2 DDRA_SCS#2
+2.5V
2
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
22
VDD
24
26
DM1
28
VSS
30
32
34
VDD
36
VDD
38
VSS
40
VSS
42
44
46
VDD
48
DM2
50
52
VSS
54
56
58
VDD
60
62
DM3
64
VSS
66
68
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
88
VSS
90
VSS
92
VDD
94
VDD
96
98
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
120
122
S1#
124
DU
126
VSS
128
130
132
VDD
134
DM4
136
138
VSS
140
142
144
VDD
146
148
DM5
150
VSS
152
154
156
VDD
158
160
CK1
162
VSS
164
166
168
VDD
170
DM6
172
174
VSS
176
178
180
VDD
182
184
DM7
186
VSS
188
190
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE2
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#3
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
+3VS
DDRA_CLK4# <9>
DDRA_CLK4 <9>
2
1
2
1
DDRB_VREF trace width of
L
20mils and space
20mils(min)
2
DDRA_CKE3DDRA_CKE_R3
12
R1122 10_0402_5%
RP26
DDRA_ADD9
1 4
DDRA_ADD12
2 3
10_0404_4P2R_5%
RP32
DDRA_ADD5
1 4
DDRA_ADD7
2 3
10_0404_4P2R_5%
RP38
DDRA_ADD1
1 4
DDRA_ADD3
2 3
10_0404_4P2R_5%
RP42
DDRA_ADD13 DDRA_SMA14DDRA_ADD14
1 4
DDRA_ADD10
2 3
10_0404_4P2R_5%
12
R392 10_0402_5%
12
R401 10_0402_5%
DDRA_ADD15DDRA_SMA15
12
R391 10_0402_5%
DDRA_CKE_R2<9,16>
1
DDRA_CKE2DDRA_CKE_R2
12
R1121 10_0402_5%
RP29
1 4
2 3
10_0404_4P2R_5%
RP35
1 4
2 3
10_0404_4P2R_5%
RP39
1 4
2 3
10_0404_4P2R_5%
12
12
12
12
DDRA_SMA8
DDRA_SMA11
DDRA_SMA4
DDRA_SMA6
DDRA_SMA0
DDRA_SMA2
DDRA_ADD8
DDRA_ADD11
DDRA_ADD4
DDRA_ADD6
DDRA_ADD0
DDRA_ADD2
R390 10_0402_5%
DDRA_RAS#< 9,14,16>
DDRA_CAS#< 9,14,16>
DDRA_CS#3<9,16>
DDRA_RAS# DDRA_S RAS#
R396 10_0402_5%
DDRA_CAS# DDRA_S CAS#
R393 10_0402_5%
DDRA_CS#3 DDRA_SCS#3
R402 10_0402_5%
System Memory Decoupling caps
+2.5V
1
2
+2.5V
1
2
C394
22U_1206_10V4Z
C403
0.1U_0402_10V6K
A A
1
C395
0.1U_0402_10V6K
2
1
C404
0.1U_0402_10V6K
2
5
1
C396
0.1U_0402_10V6K
2
1
C405
0.1U_0402_10V6K
2
1
C397
0.1U_0402_10V6K
2
1
C406
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C407
0.1U_0402_10V6K
2
1
C399
0.1U_0402_10V6K
2
1
C408
0.1U_0402_10V6K
2
1
C400
0.1U_0402_10V6K
2
1
C409
0.1U_0402_10V6K
2
4
1
C401
10U_0805_6.3V6M
2
1
C410
0.1U_0402_10V6K
2
1
C402
10U_0805_6.3V6M
2
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT2
LA-1811
星期四 八月
, 2003
1
0.7
of
15 66, 07
5
4
3
2
1
DDR Termination resistors & Decoupling caps
+1.25VS +1.25VS
DDRA_SDQ[0..63]<9,14,15>
DDRA_SDQS[0..7]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
RP65
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP68
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP71
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP74
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP77
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP80
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP83
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP86
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP90
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ12
DDRA_SDQ13
D D
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQS2
DDRA_SDQ18
C C
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ25
DDRA_SDQS3
R474
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
RP66
DDRA_SDQ30
18
DDRA_SDQ31
27
DDRA_SDQ26
36
DDRA_SDQ27
45
56 _0804_8P4R_5%
RP69
DDRA_CKE_R0
14
DDRA_CKE_R1
23
33_0404_4P2R_5%
RP75
DDRA_ADD9
18
DDRA_ADD3
27
DDRA_ADD7
36
DDRA_ADD5
45
33_0804_8P4R_5%
RP78
DDRA_ADD1
18
DDRA_ADD10
27
DDRA_ADD13
36
DDRA_ADD15
45
33_0804_8P4R_5%
RP81
DDRA_ADD8
18
DDRA_ADD6
27
DDRA_ADD4
36
DDRA_ADD2
45
33_0804_8P4R_5%
RP84
DDRA_ADD0
18
DDRA_ADD14
27
DDRA_RAS#
36
DDRA_CAS#
45
33_0804_8P4R_5%
RP87
DDRA_WE#
14
DDRA_ADD11
23
33_0404_4P2R_5%
RP89
DDRA_CS#0
14
DDRA_CS#3
23
33_0404_4P2R_5%
DDRA_ADD12
12
33_0402_5%
RP72
DDRA_CKE_R3
14
DDRA_CKE_R2
23
33_0404_4P2R_5%
RP92
DDRA_CS#1
14
DDRA_CS#2
23
33_0404_4P2R_5%
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
DDRA_RAS# <9,14,15>
DDRA_CAS# <9,14,15>
DDRA_ WE # <9,14,15>
DDRA_CS#0 <9,14>
DDRA_CS#3 <9,15>
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
DDRA_CS#1 <9,14>
DDRA_CS#2 <9,15>
RP67
DDRA_SDQ32
18
DDRA_SDQ33
27
DDRA_SDQ36
36
DDRA_SDQ37
45
56 _0804_8P4R_5%
RP70
DDRA_SDQS4
18
DDRA_SDQ34
27
DDRA_SDM4
36
DDRA_SDQ38
45
56 _0804_8P4R_5%
RP73
DDRA_SDQ35
18
DDRA_SDQ39
27
DDRA_SDQ44
36
DDRA_SDQ40
45
56 _0804_8P4R_5%
RP76
DDRA_SDQ46
18
DDRA_SDQ47
27
DDRA_SDQ42
36
DDRA_SDQ43
45
56 _0804_8P4R_5%
RP79
DDRA_SDQ45
18
DDRA_SDM5
27
DDRA_SDQ41
36
DDRA_SDQS5
45
56 _0804_8P4R_5%
RP82
DDRA_SDQ60
18
DDRA_SDQ61
27
DDRA_SDQ56
36
DDRA_SDQ57
45
56 _0804_8P4R_5%
RP85
DDRA_SDM7
18
DDRA_SDQ62
27
DDRA_SDQS7
36
DDRA_SDQ58
45
56 _0804_8P4R_5%
RP88
DDRA_SDQ63
18
DDRA_SDQ52
27
DDRA_SDQ59
36
DDRA_SDQ48
45
56 _0804_8P4R_5%
RP91
DDRA_SDQ53
18
DDRA_SDM6
27
DDRA_SDQ49
36
DDRA_SDQS6
45
56 _0804_8P4R_5%
RP93
DDRA_SDQ54
18
DDRA_SDQ55
27
DDRA_SDQ51
36
DDRA_SDQ50
45
56 _0804_8P4R_5%
+2.5V
1
C475
0.1U_0402_10V6K
2
+2.5V
1
C493
0.1U_0402_10V6K
2
1
C476
0.1U_0402_10V6K
2
1
C494
0.1U_0402_10V6K
2
1
C477
0.1U_0402_10V6K
2
1
C495
0.1U_0402_10V6K
2
1
C478
0.1U_0402_10V6K
2
1
C496
0.1U_0402_10V6K
2
1
2
1
2
+1.25VS
C479
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
1
C480
0.1U_0402_10V6K
2
1
C481
0.1U_0402_10V6K
2
1
2
+1.25VS
C482
0.1U_0402_10V6K
B B
+2.5V
1
C451
0.1U_0402_10V6K
2
+1.25VS
1
C459
0.1U_0402_10V6K
2
+1.25VS
1
C467
0.1U_0402_10V6K
2
+1.25VS
1
A A
C483
0.1U_0402_10V6K
2
1
C452
0.1U_0402_10V6K
2
1
C460
0.1U_0402_10V6K
2
1
C468
0.1U_0402_10V6K
2
1
C484
0.1U_0402_10V6K
2
1
C453
0.1U_0402_10V6K
2
1
C461
0.1U_0402_10V6K
2
1
C469
0.1U_0402_10V6K
2
1
C485
0.1U_0402_10V6K
2
5
1
C454
0.1U_0402_10V6K
2
1
C462
0.1U_0402_10V6K
2
1
C470
0.1U_0402_10V6K
2
1
C486
0.1U_0402_10V6K
2
1
C455
0.1U_0402_10V6K
2
1
C463
0.1U_0402_10V6K
2
1
C471
0.1U_0402_10V6K
2
1
C487
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
1
C464
0.1U_0402_10V6K
2
1
C472
0.1U_0402_10V6K
2
1
C488
0.1U_0402_10V6K
2
1
C457
0.1U_0402_10V6K
2
1
C465
0.1U_0402_10V6K
2
1
C473
0.1U_0402_10V6K
2
1
C489
4.7U_0805_16V6K
2
4
1
C458
0.1U_0402_10V6K
2
+1.25VS
1
C466
0.1U_0402_10V6K
2
1
C474
0.1U_0402_10V6K
2
1
C490
4.7U_0805_16V6K
2
1
+
C491
@100U_D2_10M_R45
2
1
+
C492
100U_D2_10M_R45
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR Termination Resistors
LA-1811
星期四 八月
, 2003
1
0.7
of
16 66, 07
5
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
D D
C184 @10P_0402_50V8K
1 2
CLK_AGP_EXT_66M<24>
C C
VREF_8X_IN<10>
B B
+1.5VS
If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%
A A
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R249 @10_0402_5%
1
C185
0.1U_0402_10V6K
2
(Closed to M26)
(15mil)
1 2
R264 137_0603_1%
AGP8X_DET#
Low:
AGP3.0
SSIN<10>
R936
@4.7K_0402_5%
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#0
1 2
M9-M10@1K_5%
AGP8X_DET#<10>
1 2
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
CLK_AGP_EXT_66M
NB_RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
(25mil)
AGP_DBI_HI/PIPE#
AGP_DBI_LO
TV_CRMA
TV_LUMA
TV_COMPS
SSOUT
XTALIN
SUSSTAT#
1 2
NB_RST#<8,26,39>
AGP_REQ#<10>
AGP_GNT#<10>
AGP_PAR<10>
AGP_STOP#<10>
AGP_DEVSEL#<10>
AGP_TRDY#<10>
AGP_IRDY#<10>
AGP_FRAME#<10>
PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
AGP_STP#<10,27>
AGP_BUSY#<10,27>
AGP_RBF#<10>
AGP_ADSTB0<10>
AGP_ADSTB1<10>
AGP_ADSTB0#<10>
AGP_ADSTB1#<10>
AGP_SBSTB<10>
AGP_SBSTB#<10>
AGP_DBI_HI/PIPE#<10>
AGP_DBI_LO<10>
R265
(15mil)
R266 715_0603_1%
TV_CRMA<11,41,48>
TV_LUMA<11,41,48>
TV_COMPS<11,41,48>
SSIN
SSOUT<10>
R275 1K_0603_5%
Leave These Pin No Connecting, When
Using M10-P I nter nal Spread Spectrum
5
U6A
H29
AD0
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AH30
STP_AGP#
AH29
AGP_BUSY#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
M29
AD_STBS_0
V26
AD_STBS_1
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB29
SB_STBF
AB28
SB_STBS
M26
AGPREF
M27
AGPTEST
AB25
DBI_HI
AB26
DBI_LO
AC25
AGP8X_DET#
AE11
DMINUS
AF11
DPLUS
AK21
R2SET
AJ23
C_R
AJ22
Y_G
AK22
COMP_B
AJ24
H2SYNC
AK24
V2SYNC
AG23
DDC3CLK
AG24
DDC3DATA
AK25
SSIN
AJ25
SSOUT
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
AG26
SUS_STAT#
SA002160E00(0301021300)
4
M10-P/(M9+X)
(1/6)
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
PCI/AGPAGP8XCLK
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U3N
BLON/(BLON#)
THRM
SSC DAC2
TEST_MCLK/(NC)
TEST_YCLK/(NC)
PLLTEST/(NC)
RSTB_MSK/(NC)
4
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
VREFG/(NC)
ROMCS#
DVOMODE
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
MCLK_SPREAD
AF2
AG4
AF5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AE10
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
R267 100K_0402_5%
AF12
AK27
R
AJ27
G
AJ26
B
AG25
AH25
AH26
AF25
AF24
AF26
R274 10K_0402_5%
B6
E8
AE25
AG29
R276
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N
STRAP_R
STRAP_S
STRAP_T
DVOMODE
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACLKTXACLK+
TXB0TXB0+
TXB1TXB1+
TXB2TXB2+
TXBCLKTXBCLK+
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
AGP_RSET
3VDDCDA
3VDDCCL
1 2
1 2
+3VS
12
R955
@10K_0402_5%
R235 @1K_0402_5%
R237
1 2
VREFG
ENAVDD
0_0402_5%
DDC_DAT <10,25>
DDC_CLK <10,25>
1 2
R258 0_0402_5%
TXA0- <25>
TXA0+ <25>
TXA1- <25>
TXA1+ <25>
TXA2- <25>
TXA2+ <25>
TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>
TXBCLK- <25>
TXBCLK+ <25>
ENAVDD <10,25,46>
R829
R830 M10@0_0402_5%
ENABLT#
M9@0_0402_5%
(15mil)
1 2
R272 499_0402_1%
3VDDCDA <11,25>
3VDDCCL <11,25>
1K_0603_5%
1 2
XTALIN_SS
3
(25 mil)
DRAM128M
+3VS
12
+3VS
12
12
R1149
@10K_0402_5%
For 8Mx32 VGA DRAM only
R234
M10@1K_0603_1%
R239
M10@1K_0603_1%
2
AGP, DAC & LVDS INTERFACE
GPIO8
GPIO7
GPIO4
GPIO5
GPIO6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO9
GPIO11
GPIO12
GPIO13
+3VS
DATA
CLK
+3VS
12
R253
10K_0402_5%
SUSSTAT#
M10-PM9+X
Ra 261_0603_1%
ENABLT# <10,25>
M10_BKOFF# <25>
Rb
180_0603_5%
150_0402_5%
150_0402_5%
1
2
For VGA DDR spread sprum
CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>
+3VS
Selection Table For W180
SS%
0
1
Spread % Setting for
Freq. Range
Fin>Fout>Fin-1.25%
Fin>Fout>Fin-3.75%
+3VS
R269 10K_0402_5%
R270 10K_0402_5%
12
12
L
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
1
+3VS
ID_Disable
STRAP_A
VGA_Disable
STRAP_B
STRAP_D
STRAP_E
STRAP_F
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_O
STRAP_L
STRAP_M
STRAP_N
STRAP_R
STRAP_S
STRAP_T
R232 @10K_0402_5%
R233 @10K_0402_5%
R236 @10K_0402_5%
R238 @10K_0402_5%
R240 @10K_0402_5%
R241 M10@10K_0402_5%
R242 @10K_0402_5%
R243 M10@10K_0402_5%
R244 @10K_0402_5%
R245 @10K_0402_5%
R246 @10K_0402_5%
R247 @10K_0402_5%
R248 @10K_0402_5%
R250 @10K_0402_5%
R252 @10K_0402_5%
R254 @10K_0402_5%
R255 @10K_0402_5%
R256 @10K_0402_5%
R257 @10K_0402_5%
R259 @10K_0402_5%
R260 @10K_0402_5%
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
12
R261
10K_0402_5%
X1
4
VDD
1
OE
27MHZ_15P
C186
0.1U_0402_10V6K
U7
1
X1/CLK
7
FS1
8
FS2
3.3V OSC out for W18 0
FREQOUT
3
OUT
GND
6
VDD
CLKOUT
GND
W180-01GT_SO8
3
2
0.1U_0402_10V6K
1
1
C188
2
2
0.1U_0402_10V6K
5
2
X2
4
SS%
SS%
R262 180_0603_5%
R268
Ra
1 2
150_0402_5%
1
C189
2
0.1U_0402_10V6K
1 2
R273
10K_0402_5%
1 2
Rb
22_0402_5%
R263
C190
R271 @10K_0402_5%
1.5V OSC out for M9+X
1.2V OSC out for
M10-P
XTALIN
12
C187
@15P_0402_50V8J
L13
1 2
1
2.2U_0603_6.3V4Z
C191
FCM2012C-800_0805
2
XTALIN_SSFREQOUT
+3VS
12
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P & M9+X (AGP BUS)
星期二 九月
LA-1811
17 66, 02, 2003
1
+3VS
0.7
of
5
4
3
2
1
D D
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
C C
B B
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
NMDA[0..63]<22>
NMAA[0..13]<22>
NDQMA[0..7]<22>
NDQSA[0..7]<22>
U6B
L25
DQA0
L26
DQA1
K25
DQA2
K26
DQA3
J26
DQA4
H25
DQA5
H26
DQA6
G26
DQA7
G30
DQA8
D29
DQA9
D28
DQA10
E28
DQA11
E29
DQA12
G29
DQA13
G28
DQA14
F28
DQA15
G25
DQA16
F26
DQA17
E26
DQA18
F25
DQA19
E24
DQA20
F23
DQA21
E23
DQA22
D22
DQA23
B29
DQA24
C29
DQA25
C25
DQA26
C27
DQA27
B28
DQA28
B25
DQA29
C26
DQA30
B26
DQA31
F17
DQA32
E17
DQA33
D16
DQA34
F16
DQA35
E15
DQA36
F14
DQA37
E14
DQA38
F13
DQA39
C17
DQA40
B18
DQA41
B17
DQA42
B15
DQA43
C13
DQA44
B14
DQA45
C14
DQA46
C16
DQA47
A13
DQA48
A12
DQA49
C12
DQA50
B12
DQA51
C10
DQA52
C9
DQA53
B9
DQA54
B10
DQA55
E13
DQA56
E12
DQA57
E10
DQA58
F12
DQA59
F11
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
SA002160E00(0301021300)
NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]
M10-P/(M9+X)
(2/6)
AA12/(AA13)
AA13/(AA12)
AA14/(NC)
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MEMORY INTERFACE
A
MVREFD
MVREFS/(NC)
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
DIMA0
DIMA1
NMAA0
E22
NMAA1
B22
NMAA2
B23
NMAA3
B24
NMAA4
C23
NMAA5
C22
NMAA6
F22
NMAA7
F21
NMAA8
C21
NMAA9
A24
NMAA10
C24
NMAA11
A25
NMAA12
E21
NMAA13
B20
C19
NDQMA0
J25
NDQMA1
F29
NDQMA2
E25
NDQMA3
A27
NDQMA4
F15
NDQMA5
C15
NDQMA6
C11
NDQMA7
E11
NDQSA0
J27
NDQSA1
F30
NDQSA2
F24
NDQSA3
B27
NDQSA4
E16
NDQSA5
B16
NDQSA6
B11
NDQSA7
F10
MVREFD
MVREFS
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA
NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#
NMRASA# <22>
NMCASA# <22>
NMWEA# <22>
NMCSA0# <22>
NMCSA1# <22>
NMCKEA <22>
NMCLKA0 <22>
NMCLKA0# <22>
NMCLKA1 <22>
NMCLKA1# <22>
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
D30
B13
B7
B8
MEMORY
INTERFACE A
MVREFD
0.1U_0402_10V6K
MVREFS
M10@0.1U_0402_16V4Z
Poped for M10-P
Depoped for
M9+X
C498
C503
1
2
1
2
(25 mil)
(25 mil)
+2.5VS
12
R475
1K_0402_1%
12
R478
1K_0402_1%
+2.5VS
12
R486
M10@1K_0402_1%
12
R487
M10@1K_0402_1%
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-A
星期四 八月
LA-1811
0.7
of
18 66, 07, 2003
1
5
D D
4
3
2
1
MEMORY
INTERFACE B
NMDB[0..63]<23>
NMAB[0..13]<23>
NDQMB[0..7]<23>
NDQSB[0..7]<23>
C C
B B
NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
U6C
M10-P/(M9+X)
D7
DQB0
F7
(3/6)
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46
AA2
DQB47
AA6
DQB48
AA5
DQB49
AB6
DQB50
AB5
DQB51
AD6
DQB52
AD5
DQB53
AE5
DQB54
AE4
DQB55
AB2
DQB56
AB3
DQB57
AC2
DQB58
AC3
DQB59
AD3
DQB60
AE1
DQB61
AE2
DQB62
AE3
DQB63
SA002160E00(0301021300)
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12/(AB13)
AB13/(AB12)
AB14/(NC)
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
MEMORY INTERFACE B
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
MEMVMODE0
MEMVMODE1
DIMB0
DIMB1
MEMTEST
NMAB0
N5
NMAB1
M1
NMAB2
M3
NMAB3
L3
NMAB4
L2
NMAB5
M2
NMAB6
M5
NMAB7
P6
NMAB8
N3
NMAB9
K2
NMAB10
K3
NMAB11
J2
NMAB12
P5
NMAB13
P3
P2
NDQMB0
E6
NDQMB1
B2
NDQMB2
J5
NDQMB3
G3
NDQMB4
W6
NDQMB5
W2
NDQMB6
AC6
NDQMB7
AD2
NDQSB0
F6
NDQSB1
B3
NDQSB2
K6
NDQSB3
G1
NDQSB4
V5
NDQSB5
W1
NDQSB6
AC5
NDQSB7
AD1
NMRASB#
R2
NMCASB#
T5
NMWEB#
T6
NMCSB0#
R5
NMCSB1#
R6
NMCKEB
R3
NMCLKB0
N1
NMCLKB0#
N2
NMCLKB1
T2
NMCLKB1#
T3
R509 4.7K_0402_5%
C6
1 2
R510 4.7K_0402_5%
C7
1 2
E3
AA3
R511 47_0603_1%
C8
1 2
(15mil)
NMRASB# <23>
NMCASB# <23>
NMWEB# <23>
NMCSB0# <23>
NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>
NMCLKB0# <23>
NMCLKB1 <23>
NMCLKB1# <23>
+1.8VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-B
星期四 八月
LA-1811
0.7
of
19 66, 07, 2003
1
5
4
3
2
1
U6D
M10-P/(M9+X)
VDDR1
(4/6)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
TPVDD
TPVSS
AVDD
A2VDD
A2VDD
A2VDDQ
A2VSSN
A2VSSN
A2VSSQ
AVSSN
AVSSQ
SA002160E00(0301021300)
VDDRH0
VDDRH1
VSSRH0
VSSRH1
MPVDD
MPVSS
PVDD
PVSS
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
I/O POWER
LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
LVDDR_18
LVDDR_18
LPVDD
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
VDD1DI
VDD2DI
VSS1DI
VSS2DI
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
AC11
AC20
AK12
AJ12
AH24
AG21
AH21
AF22
AH22
AJ21
AF23
AH23
AD24
B1
B30
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
D5
D8
D11
D13
D14
D17
D20
D23
D26
E27
F4
G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
T4
T7
T8
V4
V7
V8
D19
R4
H11
H20
L23
P8
Y23
Y8
D D
C C
+2.5VS
+1.5VS
+2.5VS
Poped for
M10-P
R277 M10@0_0402_5%
1 2
R278 M10@0_0402_5%
1 2
R279 M10@0_0805_5%
1 2
Poped for M10-P
Poped for M9+X
R282 M9@0_0805_5%
B B
A A
+1.8VS
1 2
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
F18
N6
F19
M6
A7
A6
AK28
AJ28
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
AC10
AC9
AD10
AD9
AG7
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
AE20
AE17
AF21
AE15
AJ20
AF20
AF15
AE19
AE16
AJ19
AE24
AE22
AE23
AE21
AF13
AF14
AG13
AG14
AH12
+2.5VDDRH
+1.5VS
+LVDDR+VDDC1.5
R281 M9@0_0603_5%
+VDD_MEMPLL1.8
+VDD_PLL1.8
+3VS
Poped for M10-P
R280 M10@0_0603_5%
1 2
1 2
+VDD_PNLIO2.5
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_PNLIO1.8
+VDD_PNLIO1.8
Poped for M9+X
C192
22U_1206_10V4Z
C197
22U_1206_10V4Z
+VDD_DAC2.5
C202
2.2U_0603_6.3V4Z
+VDD_PNLPLL1.8
C206
10U_0805_6.3V6M
+VDD_DAC1.8
C211
10U_0805_6.3V6M
+VDD_PNLIO1.8
C214
10U_0805_6.3V6M
+VDD_PNLIO2.5
C218
10U_0805_6.3V6M
+3VS
1
2
+1.5VS
1
2
1
2
1
2
1
2
1
2
1
2
C193
0.1U_0402_10V6K
C198
0.1U_0402_10V6K
(20 mil)
(20 mil)
C207
0.1U_0402_10V6K
(20 mil)
(20 mil)
(20 mil)
POWER
INTERFACE
0.1U_0402_10V6K
1
1
C194
C195
2
2
0.01U_0402_16V7K
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
L
0.1U_0402_10V6K
1
1
C199
C92
2
2
0.1U_0402_10V6K
L14
1 2
CHB1608U301_0603
1
C203
0.1U_0402_10V6K
2
1 2
CHB1608U301_0603
1
1
C208
0.1U_0402_10V6K
2
2
L18
1 2
CHB1608U301_0603
1
C212
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C215
0.1U_0402_10V6K
C219
0.1U_0402_10V6K
2
1
2
C216
0.1U_0402_10V6K
C220
0.01U_0402_16V7K
1
1
C196
2
2
0.01U_0402_16V7K
1
1
C200
2
2
+2.5VS
L16
+1.8VS
1
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C201
2
0.01U_0402_16V7K
+1.8VS
10U_0805_6.3V6M
0.1U_0402_10V6K
1
C217
2
L21
1 2
CHB1608U301
1
C863
C862
2
0.1U_0402_10V6K
+2.5VDDRH
C204
1U_0603_10V6K
+VDD_PLL1.8
C209
+VDD_MEMPLL1.8
C213
L20
1 2
CHB1608U301
+2.5VS
1
2
(20 mil)
1
2
(20 mil)
1
2
(20 mil)
1
2
+1.8VS
0.1U_0402_10V6K
1
C865
C866
2
0.1U_0402_10V6K
1
2
1
2
1
2
0.01U_0402_16V7K
1
C867
2
L15
1 2
CHB1608U301_0603
C205
0.1U_0402_10V6K
L17
1 2
CHB1608U301_0603
C210
0.1U_0402_10V6K
L19
1 2
CHB1608U301_0603
2.2U_0603_6.3V4Z
C931
1
C868
2
0.1U_0402_10V6K
+2.5VS
+1.8VS
0.1U_0402_10V6K
1
C869
2
+1.8VS
As close as possible to related pin
+VDDC1.5 +LVDDR
1
1
2
C968
0.1U_0402_10V6K
2
0.1U_0402_10V6K
C967
0.1U_0402_10V6K
1
C870
2
0.1U_0402_10V6K
C969
0.1U_0402_10V6K
1
C871
2
1
1
C970
0.1U_0402_10V6K
2
2
1
2
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-A
星期四 八月
LA-1811
0.7
of
20 66, 07, 2003
1
5
U6E
M10-P/(M9+X)
(5/6)
A10
VSS
A16
D D
C C
+VGA_CORE
1
+
@47U_D2_6.3VM
B B
2
+2.5VS
C221
1
C223
22U_1206_10V4Z
2
1
2
VSS
A2
VSS
A22
VSS
A29
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE27
VSS
AG11
VSS
AG15
VSS
AG18
VSS
AG22
VSS
AG27
VSS
AG5
VSS
AG9
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
C1
VSS
C28
VSS
C3
VSS
C30
VSS
D10
VSS
D12
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D4
VSS
D6
VSS
D9
VSS
E4
VSS
F27
VSS
SA002160E00(0301021300)
C224
22U_1206_10V4Z
1
C225
0.1U_0402_10V6K
2
CORE POWER
1
C226
0.1U_0402_10V6K
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
4
H4
H8
H9
H12
H14
H18
H21
H23
H27
K1
K23
K24
K27
K30
K7
K8
L4
M30
M7
M8
N23
N24
N27
P4
R23
R24
R30
R7
R8
T1
T27
U23
U4
U8
V30
W23
W24
W27
W7
W8
Y4
G9
G12
G16
G18
G21
G24
C227
0.1U_0402_10V6K
1
C228
0.1U_0402_10V6K
2
POWER
INTERFACE
1
2
1
C229
0.01U_0402_16V7K
2
C230
0.01U_0402_16V7K
3
1
C231
0.01U_0402_16V7K
2
1
C222
+
100U_D2_10M_R45
2
+VGA_CORE
U6F
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
P18
VDDC
P19
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U17
VDDC
U18
VDDC
U19
VDDC
V12
VDDC
V13
VDDC
V14
VDDC
V17
VDDC
V18
VDDC
V19
VDDC
W12
VDDC
W13
VDDC
W14
VDDC
W17
VDDC
W18
VDDC
W19
VDDC
AB22
VDDC
AB9
VDDC
J10
VDDC
J12
VDDC
J14
VDDC
J15
VDDC
J16
VDDC
J17
VDDC
J19
VDDC
J21
VDDC
K22
VDDC
K9
VDDC
M22
VDDC
M9
VDDC
P22
VDDC
P9
VDDC
R22
VDDC
R9
VDDC
T22
VDDC
T9
VDDC
U22
VDDC
U9
VDDC
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
VDDC
SA002160E00(0301021300)
2
M10-P/(M9+X)
(6/6)
M10-P&M9+X
COMMON
CORE POWER
M10-P
ONLY
M9+X
ONLY
VDDC
VDDC
VDDC
VDDC
VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD15
AD13
AC17
AC15
AC13
T12
M15
W16
R19
R12
R13
T13
R14
T14
N15
P15
R15
T15
U15
V15
W15
H16
M16
N16
P16
R16
T16
U16
V16
R17
T17
R18
T18
T19
AA22
AA9
J11
J13
J18
J20
J22
J9
L22
L9
N22
N9
W22
W9
1
+VGA_CORE
+VGA_CORE_CI
1
2
+2.5VS
1
2
A A
C232
22U_1206_10V4Z
C243
22U_1206_10V4Z
1
2
1
2
C233
0.1U_0402_10V6K
C244
0.1U_0402_10V6K
1
2
1
2
C234
0.1U_0402_10V6K
C245
0.1U_0402_10V6K
1
2
1
2
C235
0.1U_0402_10V6K
C246
0.1U_0402_10V6K
1
2
1
2
C236
0.1U_0402_10V6K
C247
0.1U_0402_10V6K
1
2
1
2
C237
0.1U_0402_10V6K
C248
0.1U_0402_10V6K
1
2
1
2
1
C238
0.01U_0402_16V7K
2
1
C249
0.01U_0402_16V7K
2
C239
0.01U_0402_16V7K
C250
0.01U_0402_16V7K
+VGA_CORE_CI
(20 mil)
1
C240
2
10U_0805_6.3V6M
1
C241
0.1U_0402_10V6K
2
1
C242
0.1U_0402_10V6K
2
1 2
CHB1608U301
As close as ppossible to related pin
L22
480MIL
+VGA_CORE
(12A,480mils ,Via NO.=24)
JOPEN5
PAD-OPEN 4x4m
1 2
+1.2VS_VGA
As close as ppossible to related pin
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-B
星期四 八月
LA-1811
0.7
of
21 66, 07, 2003
1
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