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LA-1811
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Compal confidential
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic
3 3
4 4
A
B
2003-07-30(Under review)
REV:0.7
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
星期四 八月
LA-1811
0.7
of
166, 07, 2003
E
Page 2
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Compal confidential
File Name :LA1811
1 1
CRT & TV-OUT Conn.
LCD Conn
W/EXT VGA CHIP
W/EXT VGA CHIP
VGA DDR x2 CHB
2 2
page 23
ATI-M9+X/M10C
page 17,18,19,20,21
VGA DDR x2 CHA
page 25
page 25
page 22
Fan Control
page 7
W/O EXT VGA CHIP
W/O EXT VGA CHIP
AGP BUS
Intel Northwood/Prescott Processor
uFCBGA-479/uFCPGA-478 CPU
page 4,5,6
H_A#(3..31)
PSB
800MHz
H_D#(0..63)
ATI-RC300M
VGA M9 Embeded
868 pin u-BGA
page 8,9,10,11,12,13
A-Link
Thermal Sensor
ADM1032AR
page 7
Memory BUS(DDR)
2.5V DDR- 200/266
USB1.1
USB2.0
CLOCK GENERATOR
ICS951402AGT
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
page 14,15,16
BT/USB KEY
USB conn x3
page 44
Audio Codec
ADI 1981B
page 37
page 24
page 44
AMP & Audio Jack
page 38
MDC & BT Conn
3.3V 33 MHz
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
USB2.0 Ctrl.
NEC uPD720101
page 36
IDSEL:AD23
(PIRQA/C/D#,GNT#4,REQ#4)
3 3
IEEE 1394
TI-TSB43AB22
page 35
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
Mini PCI
socket
page 43
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)
RTL 8101BL
RJ45 CONN
LAN
page 34
page 34
CardBus Controller
RTC CKT.
page 26
Power OK CKT.
page 48
NS 87591
page 46
PCI BUS
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
TI PCI1520/1620
Slot 0,1
page 32
page 31
Card slot
page 33
ATI-SB200
BGA 457 pin
page 26,27,28,29
LPC BUS
AC-LINK
Primary IDE
ATA-100
Secondary IDE
ATA-100
Mini-PCI solt
VIA VT1211
page 44
page 43
HDD
Connector
page 30
CDROM
Connector
Super I/O
page 30
page 39
RJ11 CONN
page 44
CABLE CONN.
*RJ45 CONN
*LINE IN JACK
*DC JACK
*COM PORT
page 41
*USB CONN x1
Power On/Off CKT.
page 45
4 4
DC/DC Int erface CKT.
page 49
Touch Pad
page 44,45
EC I/O Bu ffer
page 47
Int.KBD
BIOS
page 45
page 47
PARALLEL
page 40
FIR
page 45
FDD
page 40
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT
Power Circuit DC/DC
page 50,51,52,53,54,55,56,57
A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Date: Sheet
Compal Electronics, Inc.
LA-1811
星期四 八月
Block Diagram
E
0.7
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266, 07, 2003
Page 3
Voltage Rails
A
Power Plane
VIN
B+
+VCC_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
The voltage for Processor VID select
1.25V switched power rail for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V switched power rail for ATI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
S3
S0-S1
N/AONN/A
N/A
N/A
N/A
ON
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ONON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
OFF
ON
ON
ON
ON
ON
S5
N/A
OFF
OFF
OFF
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*+5VALW 5V always on power rail
ON*
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means bui ld ATI SB USB2.0 related to turn on the function .
NEC@ : means bu ild NEC USB2.0 related to turn on the function .
External PCI Devices
1 1
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
IDSEL # PIRQ
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
REQ/GNT #DEVICE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
A
A
N/A
D
B
A
C
A
D
A.B
C
EXT USB AD23(EXT.) 4 A,C,D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
A2
D2
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
星期四 八月
LA-1811
Notes List
of
366, 07, 2003
0.7
Page 4
5
4
+VCC_CORE
3
2
1
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C C
H_REQ#[0..4]<8>
H_ADS#<8>
R230
@62_0402_5%
+VCC_CORE
+VCC_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
VCCA VCCIOPLLConnect to CPU
AE23
VCCIOPLL VCCA
AD20
AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/
TESTHI12 TESTHI12AD25 DPSLP
Commend Commend
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Connect to CPU
Filter
Connect to GND CPU determine
Pull-up 200ohm
to +VCC_CORE
5
1 2
R231
1 2
H_BR0#<8>
H_BPRI#<8>
H_BNR#<8>
H_LOCK#<8>
CK_BCLK<24>
CK_BCLK#<24>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
COMPAT#
float
Pull-up 62ohm
to +VCC_CORE
51_0402_5%
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
CK_BCLK
CK_BCLK#
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VCCIOPLL
VSS
VSS
AF22
AF23
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
J1
K5
J4
J3
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
F3
E3
E2
A10
JP8A
VCC_0
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to GND
Connect to PLD
through 0ohm
4
A12
A14
VCC_1
Commend
A16
VCC_2
VSS_0H1VSS_1H4VSS_2
float
float
float
VCC_3
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
VCC_65C8VCC_66
VCC_84
VCC_85
F9
F11
VCC_67
VCC_68
VCC_69
VCC_70
VCC_77
VCC_78
VCC_79E8VCC_80
E18
E20
+VCC_CORE
1 2
E10
VCC_71D7VCC_72
VCC_73
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
AMP_3-1565030-1_Prescott
E12
E14
E16
12
R1099
47K_0402_5%
3 1
2
H_D#[0..63] <8>H_A#[3..31]<8>
+5VS+5VS
12
1
C
R1100
47K_0402_5%
Q106
2SC2411K_SC59
E3B
H_BOOTSELECT <56>
H_D#0
B21
D#0
H_D#1
B22
D#1
H_D#2
A23
D#2
H_D#3
A25
D#3
H_D#4
C21
D#4
H_D#5
D22
D#5
H_D#6
B24
D#6
H_D#7
C23
D#7
H_D#8
C24
D#8
H_D#9
B25
D#9
H_D#10
G22
H_D#11
H21
H_D#12
C26
H_D#13
D23
H_D#14
J21
H_D#15
D25
H_D#16
H22
H_D#17
E24
H_D#18
G23
H_D#19
F23
H_D#20
F24
H_D#21
E25
H_D#22
F26
H_D#23
D26
H_D#24
L21
H_D#25
G26
H_D#26
H24
H_D#27
M21
H_D#28
L22
H_D#29
J24
H_D#30
K23
H_D#31
H25
H_D#32
M23
H_D#33
N22
H_D#34
P21
H_D#35
M24
H_D#36
N23
H_D#37
M26
H_D#38
N26
H_D#39
N25
H_D#40
R21
H_D#41
P24
H_D#42
R25
H_D#43
R24
H_D#44
T26
H_D#45
T25
H_D#46
T22
H_D#47
T23
H_D#48
U26
H_D#49
U24
H_D#50
U23
H_D#51
V25
H_D#52
U21
H_D#53
V22
H_D#54
V24
H_D#55
W26
H_D#56
Y26
H_D#57
W25
H_D#58
Y23
H_D#59
Y24
H_D#60
Y21
H_D#61
AA25
H_D#62
AA22
H_D#63
AA24
2
Q107
MMBT3904_SOT23
A18
A20
AA10
AA12
AA14
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
Prescott
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
Northwood
AA4
AA7
AA11
AA13
AA9
AA15
AA17
AA19
AA23
AA26
AB10
Prescott
AB12
AB14
AB16
Northwood
MT
AB3
AB6
AB8
AC2
AC5
AC7
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC9
AC17
AC19
AC22
AC25
AD10
AD12
AD14
BOOTSELECT
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VCC_81
VCC_82
VCC_83
F13
F15
F17
F19
AD1
AD4
AD8
AD16
AD18
AD21
AD23
R899 22K_0402_5%
12
R900
100K_0402_5%
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
Pop
Depop
DepopPop
Pop Pop
Pop
Pop
Pop
Pop
Depop
Depop
Depop
Pop
Pop
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-1811
星期四 八月
, 2003
1
0.7
of
466, 07
Page 5
5
+VCC_CORE
R513 56_0402_5%
R515 56_0402_5%
D D
R519 56_0402_5%
C C
B B
+VCC_CORE
+VCC_CORE
A A
H_FERR#
1 2
H_THERMTRIP#
1 2
R517 130_0402_5%
H_PROCHOT#
1 2
R518 300_0402_5%
H_PWRGOOD
1 2
H_RESET#
1 2
+VCC_CORE
L36 LQG21F4R7N00_0805
1 2
1 2
L37 LQG21F4R7N00_0805
R546
54.9_0603_1%
1 2
If CPU is P4 , Change the resistor
R546 value to 75_0603_1%
R547
54.9_0603_1%
1 2
Close to the ITP
R550
47_0402_5%
12
If CPU is P4 , Change the resistor
R550 value to 39_0402_5%
R552 150_0402_5%
1 2
If CPU is P4 , Change the resistor
R556 value to 27.4_0402_5%
12
R556 47_0402_5%
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
ITP_TDO
ITP_DBRESET#
ITP_TMS
ITP_TDI
ITP_TCK
Place near SB200 (U6)
Place near CPU
+VCC_CORE
Note: Please change to 10uH, DC current
of 100mA parts and close to cap
33U_D2_8M_R35
C544
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>
H_FERR#<26>
H_IGNNE#<26>
H_PWRGOOD<26>
H_STPCLK#<26>
H_INIT#<26>
H_RESET#<8,26>
H_DBSY#<8>
H_DRDY#<8>
H_THERMDA<7>
H_THERMDC<7>
H_THERMTRIP#<7>
R529 56_0402_5%
1 2
R530 56_0402_5%
1 2
1 8
2 7
3 6
4 5
RP137 56_0804_8P4R_5%
1
1
C854
+
+
2
2
33U_D2_8M_R35
CPUCLK_STP#<11,26,56>
H_SMI#<26>
H_INTR<26>
H_NMI<26>
VCCSENSE<56>
VSSSENSE<56>
BSEL0<13,24>
BSEL1<13,24>
H_VCCA
+VCCVID
H_VSSA
1 2
12K_0402_5%
51.1_0402_1%
If CPU is P4 , Change the
resistor R53 9,R540 value to
51.1_0603_1%,or prescott
61.9_0603_1%
R1125
R1017
CK_ITP<24>
CK_ITP#<24>
R539
Close to the CPU
R559
680_0603_5%
1 2
Between the CPU and ITP
ITP_TRST#
5
H_FERR#
H_PWRGOOD
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
12
+3VS
2
4
H_RS#0
H_RS#1
H_RS#2
1 2
0_0402_5%
CK_ITP
CK_ITP#
COMP0
COMP1
12
R540
51.1_0402_1%
12
R993
4.7K_0402_5%
2
Q96
MMBT3904_SOT23
3 1
4
JP8B
F1
RS#0
G5
RS#1
F4
RS#2
AB2
RSP#
J6
TRDY#
C6
A20M#
B6
FERR#
B2
IGNNE#
B5
SMI#
AB23
PWRGOOD
Y4
STPCLK#
D1
LINT0
E5
LINT1
W5
INIT#
AB25
RESET#
H5
DBSY#
H2
DRDY#
AD6
BSEL0
AD5
BSEL1
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AC6
BPM#0
AB5
BPM#1
AC4
BPM#2
Y6
BPM#3
AA5
BPM#4
AB4
BPM#5
D4
TCK
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
AD20
VCCIOPLL
AE23
VCCA
A5
VCCSENSE
A4
VSSSENSE
AF3
VCCVIDLB
AD22
VSSA
AC26
ITP_CLK0
AD26
ITP_CLK1
L24
COMP0
P1
COMP1
CPU_STP#
Q95
MMBT3904_SOT23
3 1
AE11
AE13
AE15
AE17
AE19
AE22
AE24
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_129F8VSS_130
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
J22
G21
G24
4.7K_0402_5%
VID_PWRGD<55,56>
SN74LVC14APWLE_TSSOP14
AE7
J25
R545
3
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
Prescott
VID0
VID1
VID2
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
L23
L26
K21
K24
+3VS
U32A
1
+3VALW
N21
N24
M22
M25
14
P
O2I
G
7
P22
P25
2
G
R23
R26
H_VID_PWRGD
13
D
Q45
S
2N7002 1N_SOT23
3
T21
T24
V23
V26
Y22
U22
U25
+VCC_CORE
12
R_A
12
R558
R_B
100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
Y25
W21
W24
GTL Reference Voltage
Layout note :
R553
49.9_0402_1%
2
1
VID3
VSS_181
Y5
AE5
AE4
AE3
AE2
AE1
VID0
VID1
VID2
VID3
VID4
VID5
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
C546
0.1U_0402_10V6K
F10
F12
F14
VSS_121
VSS_122
VID4
VID5
AD3
1
C547
220P_0402_25V8K
2
F16
F18
VSS_123
VSS_124
VSS_125F2VSS_126
VIDPWRGD
AD2
2
F22
F25
F5
AF26
VSS_127
VSS_128
SKTOCC#
OPTIMIZED/COMPAT#
VCCVID
AMP_3-1565030-1_Prescott
AF4
+VCCVID
1
C932
0.1U_0402_10V6K
2
H_VID_PWRGD
2
R514
1 2
@0_0402_5%
J26
DP#0
K25
DP#1
K26
DP#2
L25
DP#3
AA21
GTLREF0
AA6
GTLREF1
F20
GTLREF2
F6
GTLREF3
AE26
AD24
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
R541 2.43K_0603_1%
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
1 2
H_TESTHI0_1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
1
+CPU_GTLREF
R520 0_0402_5%
1 2
R521 56_0402_5%
1 2
R522 56_0402_5%
1 2
RP136 56_0804_8P4R_5%
1 8
2 7
3 6
4 5
R990 56_0402_5%
1 2
R527 56_0402_5%
1 2
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_PROCHOT# <26,51>
H_CPUSLP# <26>
+VCCVID
VID5<56>
VID4<56>
VID3<56>
VID2<56>
VID1<56>
VID0<56>
Title
Size Document N u mb er Re v
Date: Sheet
星期四 八月
+VCC_CORE
CPU_STP#
VID5
R542 1K_0402_5%
1 2
VID4
R543 1K_0402_5%
1 2
VID3
VID2
VID1
VID0
RP94 1K_1206_8P4R_5%
45
36
27
18
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
LA-1811
, 2003
1
566, 07
CPU_GHI# <27>
+3VS
of
0.7
Page 6
5
4
3
2
1
+VCC_CORE
1
C131
22U_1206_16V4Z
2
D D
+VCC_CORE
1
C142
22U_1206_16V4Z
2
+VCC_CORE
1
C152
22U_1206_16V4Z
2
C C
+VCC_CORE
1
C154
22U_1206_16V4Z
2
1
C132
22U_1206_16V4Z
2
1
C143
22U_1206_16V4Z
2
1
C153
22U_1206_16V4Z
2
1
C155
22U_1206_16V4Z
2
1
C133
22U_1206_16V4Z
2
1
C144
22U_1206_16V4Z
2
1
C156
22U_1206_16V4Z
2
Place 11 North of Socket(Stuff 6)
1
C134
22U_1206_16V4Z
2
1
C135
22U_1206_16V4Z
2
1
2
Place 12 Insid e So c ke t( S tu f f all)
1
C145
22U_1206_16V4Z
2
1
C146
22U_1206_16V4Z
2
1
2
Place 9 South o f So c ke t( U ns t uf f all)
1
C157
22U_1206_16V4Z
2
1
C158
22U_1206_16V4Z
2
1
2
C136
22U_1206_16V4Z
C147
22U_1206_16V4Z
C159
22U_1206_16V4Z
1
C137
22U_1206_16V4Z
2
1
C148
22U_1206_16V4Z
2
1
C160
22U_1206_16V4Z
2
1
C138
22U_1206_16V4Z
2
1
C149
22U_1206_16V4Z
2
1
C161
22U_1206_16V4Z
2
1
C139
22U_1206_16V4Z
2
1
C150
22U_1206_16V4Z
2
1
C162
22U_1206_16V4Z
2
1
C140
22U_1206_16V4Z
2
1
C151
22U_1206_16V4Z
2
1
C141
22U_1206_16V4Z
2
B B
+VCC_CORE
1
C163
+
470U_D2_2.5VM
2
+VCC_CORE
1
C174
+
470U_D2_2.5VM
2
+VCC_CORE
A A
1
C179
+
470U_D2_2.5VM
2
1
C164
+
470U_D2_2.5VM
2
1
C175
+
470U_D2_2.5VM
2
1
C180
+
470U_D2_2.5VM
2
5
1
C165
+
470U_D2_2.5VM
2
1
C176
+
@330U_D2E_2.5VM
2
1
C181
+
470U_D2_2.5VM
2
1
C166
+
@330U_D2E_2.5VM
2
1
C177
+
470U_D2_2.5VM
2
1
C182
+
470U_D2_2.5VM
2
4
1
C167
+
470U_D2_2.5VM
2
1
C178
+
470U_D2_2.5VM
2
1
C183
+
@470U_D2_2.5VM
2
3
Place Insi de S oc ket around the edge
+VCC_CORE
1
C168
0.22U_0603_10V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C169
0.22U_0603_10V7K
2
1
C170
0.22U_0603_10V7K
2
1
C171
0.22U_0603_10V7K
2
2
1
C172
0.22U_0603_10V7K
2
1
C173
0.22U_0603_10V7K
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Decoupling
LA-1811
星期四 八月
, 2003
1
0.7
of
666, 07
Page 7
5
4
3
2
1
Thermal Sensor ADM1032AR
+3VALW
W=15mil
12
R283
D D
@10K_0402_5%
C253
2200P_0402_25V7K
1
2
2
1
H_THERMDA
H_THERMDC
C251
0.1U_0402_10V6K
U8
1
VDD
2
D+
3
DTHERM#4GND
ADM1032AR_SOP8
SCLK
SDATA
ALERT#
Address:1001_100X
H_THERMDA
H_THERMDC
8
7
6
5
H_THER MDA <5>
H_TH ERMDC <5>
EC_SMC_2 <46>
EC_SMD_2 <46>
+VCC_CORE
C C
EN_FAN1<46> EN_FAN2<46>
B B
R286 300_0402_5%12C256 @1U_0603_10V6K
H_THERMTRIP#<5>
R915
10K_0402_5%
H_THERMTRIP#
FAN CONN.1 FAN CONN. 2
+12VALW
8
U10A
3
+IN
2
-IN
1 2
R917
P
OUT
G
LM358A_SO8
4
8.2K_0402_5%
1
R913 100_0402_5%
EN_DFAN2 EN_FAN2
12
2
B
3
E
1 2
12
1
C
Q17
2SC2411K_SC59
2
B
2
C840
0.1U_0402_10V6K
1
D25
1N4148_SOD80
R919 10K_0402_5%
1 2
+3VS
MAINPWON <50,51,53>
+5VS
1SS355_SOD323
1
C
FMMT619_SOT23
Q90
E
3
FAN1 FAN2
12
C265
10U_0805_10V4Z
12
D67
1
1
C855
2
2
@1000P_0402_16V7K
12
C838
10U_0805_16V4Z
JP10
ACES_85205-0300
1
C907
@1000P_0402_16V7K
2
U10B
5
+IN
6
12
R916
10K_0402_5%
1
2
3
-IN
1 2
R918
7
OUT
LM358A_SO8
8.2K_0402_5%
R914 100_0402_5%
1 2
2
C841
0.1U_0402_10V6K
1
+3VS
FANSPEED2<46>FANSPEED1<46>
+5VS
1
C
FMMT619_SOT23
2
B
Q91
E
3
12
D26
1N4148_SOD80
10U_0805_10V4Z
R920 10K_0402_5%
1 2
C266
12
D68
1SS355_SOD323
1
2
@1000P_0402_16V7K
1
C839
10U_0805_16V4Z
2
1
C856
2
1
2
JP11
1
2
3
ACES_85205-0300
C908
@1000P_0402_16V7K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
CPU Thermal Sensor&FAN CTRL
LA-1811
星期四 八月
, 2003
1
0.7
of
766, 07
Page 8
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
U27A
1U_0603_10V6K
1 2
C361
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF
D D
H_ADSTB#0<5>
C C
H_ADSTB#1<5>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<5>
H_DBSY#<5>
H_BR0#<4>
H_LOCK#<4>
H_RESET#<5,26>
H_RS#2<5>
SUS_STAT#<27>
NB_RST#<17,26,39>
NB_PWRGD<48>
1 2
1 2
L34
1 2
H_RS#1<5>
H_RS#0<5>
H_TRDY#<5>
H_HIT#<4>
H_HITM#<4>
0.1U_0402_10V6K
C974
12
--> 412_0402_1%
R380 412_0402_1%
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+VCC_CORE
PLACE CLOSE TO U27 Ball
W28, USE 20/20
1 2
12
WIDTH/SPACE
1
C362
1U_0603_10V6K
2
1
C363
220P_0402_25V8K
2
C363 CLOSE
TO Ball W28
B B
R383
49.9_0402_1%
R384
100_0402_1%
1 2
+VCC_CORE
+1.8VS
R381 24.9_0402_1%
R382 49.9_0402_1%
HB-1M2012-121JT03_0805
12
R385
4.7K_0402_5%
M28
P25
M25
N29
N30
M26
N28
P29
P26
R29
P30
P28
N26
N27
M29
N25
R26
L28
L29
R27
U30
T30
R28
R25
U25
T28
V29
T26
U29
U26
V26
T25
V25
U27
U28
T29
L27
K25
H26
J27
L26
G27
F25
K26
A17
G25
G26
J25
F26
J26
H25
A9
AH5
AG5
C7
V28
W29
H23
J23
W28
Y29
Y28
B17
216RC300M_BGA_718
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD
CPU_COMP_N
CPU_COMP_P
CPVDD
CPVSS
CPU_VREF
THERMALDIODE_N
THERMALDIODE_P
TESTMODE
PART 1 OF 6
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
MISC.
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_DSTBN0#
CPU_DSTBP0#
CPU_DSTBN1#
AGTL+ I/F
CPU_DSTBP1#
PENTIUM
CPU_DSTBN2#
CPU_DSTBP2#
CPU_DSTBN3#
CPU_DSTBP3#
IV
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_D#[0..63] <4>
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
H_D#0
L30
H_D#1
K29
H_D#2
J29
H_D#3
H28
H_D#4
K28
H_D#5
K30
H_D#6
H29
H_D#7
J28
H_D#8
F28
H_D#9
H30
H_D#10
E30
H_D#11
D29
H_D#12
G28
H_D#13
E29
H_D#14
D30
H_D#15
F29
H_DINV#0
E28
H_DSTBN#0
G30
H_DSTBP#0
G29
H_D#16
B26
H_D#17
C30
H_D#18
A27
H_D#19
B29
H_D#20
C28
H_D#21
C29
H_D#22
B28
H_D#23
D28
H_D#24
D26
H_D#25
B27
H_D#26
C26
H_D#27
E25
H_D#28
E26
H_D#29
A26
H_D#30
B25
H_D#31
C25
H_DINV#1
A28
H_DSTBN#1
D27
H_DSTBP#1
E27
H_D#32
F24
H_D#33
D24
H_D#34
E23
H_D#35
E24
H_D#36
F23
H_D#37
C24
H_D#38
B24
H_D#39
A24
H_D#40
F21
H_D#41
A23
H_D#42
B23
H_D#43
C22
H_D#44
B22
H_D#45
C21
H_D#46
E21
H_D#47
D22
H_DINV#2
D23
H_DSTBN#2
E22
H_DSTBP#2
F22
H_D#48
B21
H_D#49
F20
H_D#50
A21
H_D#51
C20
H_D#52
E20
H_D#53
D20
H_D#54
A20
H_D#55
D19
H_D#56
C18
H_D#57
B20
H_D#58
E18
H_D#59
B19
H_D#60
D18
H_D#61
B18
H_D#62
C17
H_D#63
A18
H_DINV#3
F19
H_DSTBN#3
E19
H_DSTBP#3
F18
H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>
H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>
H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
+VCC_CORE
22U_1206_16V4Z_V1
A A
5
4
C364
0.1U_0402_10V6K
1
1
C366
C365
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C367
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C368
2
1
C369
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C370
2
2
1
C371
2
0.1U_0402_10V6K
1
C372
0.1U_0402_10V6K
2
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-AGTL+
星期四 八月
LA-1811
of
866, 07, 2003
1
0.7
Page 9
5
U27B
DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4
D D
DDRA_RAS#<14,15,16>
DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
C C
DDRA_CLK0<14>
DDRA_CLK0#<14>
DDRA_CLK1<14>
DDRA_CLK1#<14>
DDRA_CLK3<15>
DDRA_CLK3#<15>
DDRA_CLK4<15>
DDRA_CLK4#<15>
DDRA_CKE_R0<14,16>
DDRA_CKE_R1<14,16>
DDRA_CKE_R2<15,16>
DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>
DDRA_CS#1<14,16>
DDRA_CS#2<15,16>
DDRA_CS#3<15,16>
L35
B B
A A
+1.8VS
C857
0.1U_0402_10V6K
1 2
HB-1M2012-121JT03_0805
+2.5V
1
1
C858
2
2
@0.1U_0402_10V6K
@0.1U_0402_10V6K
C859
5
DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15
DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK3
DDRA_CLK3#
DDRA_CLK4
DDRA_CLK4#
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
C375
1 2
1U_0603_10V6K
1
C860
2
@0.1U_0402_10V6K
MPVDD
MPVSS
1
2
DDR_VREF
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AJ8
AF9
AH13
AE21
AJ23
AJ27
AC28
AA25
AK10
AH10
AH18
AJ19
AG30
AG29
AK11
AJ11
AH17
AJ18
AF28
AG28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
0.1U_0402_10V6K
0.1U_0402_10V6K
L
1
C861
@0.1U_0402_10V6K
2
PART 2 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
MEM_CK0
MEM_CK0#
MEM_CK1
MEM_CK1#
MEM_CK2
MEM_CK2#
MEM_CK3
MEM_CK3#
MEM_CK4
MEM_CK4#
MEM_CK5
MEM_CK5#
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MPVDD
MPVSS
216RC300M_BGA_718
2
C376
1
DDR_VREF
2
C377
1
DDR_VREF trace width of
20mils and space
20mils(min)
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM I/F
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
+2.5V+2.5V
12
R408
1K_0603_1%
12
R409
1K_0603_1%
4
DDRA_DQ0
AG6
DDRA_DQ1
AJ7
DDRA_DQ2
AJ9
DDRA_DQ3
AJ10
DDRA_DQ4
AJ6
DDRA_DQ5
AH6
DDRA_DQ6
AH8
DDRA_DQ7
AH9
DDRA_DQ8
AE7
DDRA_DQ9
AE8
DDRA_DQ10
AE12
DDRA_DQ11
AF12
DDRA_DQ12
AF7
DDRA_DQ13
AF8
DDRA_DQ14
AE11
DDRA_DQ15
AF11
DDRA_DQ16
AJ12
DDRA_DQ17
AH12
DDRA_DQ18
AH14
DDRA_DQ19
AH15
DDRA_DQ20
AH11
DDRA_DQ21
AJ13
DDRA_DQ22
AJ15
DDRA_DQ23
AJ16
DDRA_DQ24
AF18
DDRA_DQ25
AG20
DDRA_DQ26
AG21
DDRA_DQ27
AF22
DDRA_DQ28
AF19
DDRA_DQ29
AF20
DDRA_DQ30
AE22
DDRA_DQ31
AF23
DDRA_DQ32
AJ21
DDRA_DQ33
AJ22
DDRA_DQ34
AJ24
DDRA_DQ35
AK25
DDRA_DQ36
AH21
DDRA_DQ37
AH22
DDRA_DQ38
AH24
DDRA_DQ39
AJ25
DDRA_DQ40
AK26
DDRA_DQ41
AK27
DDRA_DQ42
AJ28
DDRA_DQ43
AH29
DDRA_DQ44
AH25
DDRA_DQ45
AJ26
DDRA_DQ46
AJ29
DDRA_DQ47
AH30
DDRA_DQ48
AF29
DDRA_DQ49
AE29
DDRA_DQ50
AB28
DDRA_DQ51
AA28
DDRA_DQ52
AE28
DDRA_DQ53
AD28
DDRA_DQ54
AC29
DDRA_DQ55
AB29
DDRA_DQ56
AC26
DDRA_DQ57
AB25
DDRA_DQ58
Y26
DDRA_DQ59
W26
DDRA_DQ60
AE26
DDRA_DQ61
AD26
DDRA_DQ62
AA26
DDRA_DQ63
Y27
C373 0.47U_0603_16V7K
AF6
1 2
C374 0.47U_0603_16V7K
AA29
1 2
MEN_COMP
AK19
AK20
C378
100U_D2_10VM
4
Group 6 sweep Group 7
R405 49.9_0402_1%
1 2
+2.5V
1
1
+
C379
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C380
2
0.1U_0402_10V6K
C381
3
DDRA_DQ8
DDRA_DQ12
DDRA_DQ9
DDRA_DQ13
DDRA_DQ10
DDRA_DQ14
DDRA_DQ11
DDRA_DQ15
DDRA_DQS1
DDRA_DM1
DDRA_DQ0
DDRA_DQ4
DDRA_DQ1
DDRA_DQ3
DDRA_DQ7
DDRA_DQ2
DDRA_DQ6
DDRA_DQS0 DDRA_SD QS0
DDRA_DM0
DDRA_DQ20
DDRA_DQ16
DDRA_DQ21
DDRA_DQ17
DDRA_DQ18
DDRA_DQ22
DDRA_DQ19
DDRA_DQ23
DDRA_DM2 DDRA_SDM2
DDRA_DQS2
DDRA_DQ24
DDRA_DQ28
DDRA_DQ25
DDRA_DQ29
DDRA_DQ26
DDRA_DQ30
DDRA_DQ27
DDRA_DQ31
DDRA_DQS3 DDRA_SD QS3
DDRA_DM3 DDRA_SDM3
0.1U_0402_10V6K
1
C382
2
0.1U_0402_10V6K
1
1
C383
2
2
0.1U_0402_10V6K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP28
1 4
2 3
0_0404_4P2R_5%
RP31
1 4
2 3
0_0404_4P2R_5%
RP34
1 4
2 3
0_0404_4P2R_5%
RP37
1 4
2 3
0_0404_4P2R_5%
R387 0_0402_5%
R388 0_0402_5%
RP40
1 4
2 3
0_0404_4P2R_5%
RP43
1 4
2 3
0_0404_4P2R_5%
RP45
1 4
2 3
0_0404_4P2R_5%
RP47
1 4
2 3
0_0404_4P2R_5%
R394 0_0402_5%
R397 0_0402_5%
RP49
1 4
2 3
0_0404_4P2R_5%
RP51
1 4
2 3
0_0404_4P2R_5%
RP53
1 4
2 3
0_0404_4P2R_5%
RP55
1 4
2 3
0_0404_4P2R_5%
R403 0_0402_5%
R406 0_0402_5%
RP57
1 4
2 3
0_0404_4P2R_5%
RP59
1 4
2 3
0_0404_4P2R_5%
RP61
1 4
2 3
0_0404_4P2R_5%
RP63
1 4
2 3
0_0404_4P2R_5%
R412 0_0402_5%
R415 0_0402_5%
1
C384
C385
2
0.1U_0402_10V6K
DDRA_SDQ8
DDRA_SDQ12
DDRA_SDQ9
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQS1
12
DDRA_SDM1
12
DDRA_SDQ0
DDRA_SDQ4
DDRA_SDQ1
DDRA_SDQ5DDRA_DQ5
DDRA_SDQ3
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ6
12
DDRA_SDM0
12
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
12
DDRA_SDQS2
12
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQ26
DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ31
12
12
0.1U_0402_10V6K
1
C386
2
1
C387
2
0.1U_0402_10V6K
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37
DDRA_DQ33
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35
DDRA_DQS4
DDRA_DM4
DDRA_DQ40
DDRA_DQ45
DDRA_DQ41
DDRA_DQ46
DDRA_DQ42
DDRA_DQ43
DDRA_DQS5
DDRA_DM5
DDRA_DQ60 DDRA_SDQ60
DDRA_DQ57 DDRA_SDQ57
DDRA_DQ58 DDRA_SDQ58
DDRA_DQ59 DDRA_SDQ59
DDRA_DQS7
DDRA_DM7
DDRA_DQ52 DDRA_SDQ52
DDRA_DQ49 DDRA_SDQ49
DDRA_DQ50
DDRA_DQ54
DDRA_DQ51
DDRA_DQ55
0.1U_0402_10V6K
1
1
C388
2
2
0.1U_0402_10V6K
2
RP27
1 4
2 3
0_0404_4P2R_5%
RP30
1 4
2 3
0_0404_4P2R_5%
RP33
1 4
2 3
0_0404_4P2R_5%
RP36
1 4
2 3
0_0404_4P2R_5%
R386 0_0402_5%
R389 0_0402_5%
RP41
1 4
2 3
0_0404_4P2R_5%
RP44
1 4
2 3
0_0404_4P2R_5%
RP46
1 4
2 3
0_0404_4P2R_5%
RP48
1 4
2 3
0_0404_4P2R_5%
R395 0_0402_5%
R398 0_0402_5%
RP50
1 4
2 3
0_0404_4P2R_5%
RP52
1 4
2 3
0_0404_4P2R_5%
RP54
1 4
2 3
0_0404_4P2R_5%
RP56
1 4
2 3
0_0404_4P2R_5%
R404 0_0402_5%
R407 0_0402_5%
RP58
1 4
2 3
0_0404_4P2R_5%
RP60
1 4
2 3
0_0404_4P2R_5%
RP62
1 4
2 3
0_0404_4P2R_5%
RP64
1 4
2 3
0_0404_4P2R_5%
R413 0_0402_5%
R416 0_0402_5%
0.1U_0402_10V6K
1
C390
C389
2
2
12
12
12
12
12
12
12
12
1
2
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ38
DDRA_SDQ34
DDRA_SDQ39
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ44DDRA_DQ44
DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47DDRA_DQ47
DDRA_SDQ43
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQ56DDRA_DQ56
DDRA_SDQ61DDRA_DQ61
DDRA_SDQ62DDRA_DQ62
DDRA_SDQ63DDRA_DQ63
DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ48DDRA_DQ48
DDRA_SDQ53DDRA_DQ53
DDRA_SDQ50
DDRA_SDQ54
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQS6DDRA_DQS6
DDRA_SDM6DDRA_DM6
1
C391
0.1U_0402_10V6K
2
1
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7] <14,15,16>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-DDR I/F
星期四 八月
LA-1811
of
966, 07, 2003
1
0.7
Page 10
5
4
3
2
1
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
D D
C C
?
B B
47U_B_6.3VM
A A
47U_B_6.3VM
A_PAR<13,26>
A_STROBE#<26>
A_ACAT#<26>
A_END#<26>
PCI_PIRQA#<17,26,31,35,36>
Rb
Rc
+1.5VS +3VS
C551
+1.5VS
C552
+1.5VS+1.5VS
R576
324_0402_1%
1 2
AGPREF_8X
R577
100_0402_1%
1 2
1
1
+
C553
2
2
0.1U_0402_10V6K
1
1
+
C570
2
2
0.1U_0402_10V6K
A_DEVSEL#<26>
A_SBREQ#<26>
A_SBGNT#<26>
AGP_GNT#<17>
AGP_REQ#<17>
AGP8X_DET#<17>
VREF_8X_IN<17>
R575
PLACE CLOSE TO
CONNECTOR
0.1U_0402_10V6K
C554
0.1U_0402_10V6K
C571
5
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
1 2
1 2
Ra
1 2
169_0402_1%
1
C555
2
0.1U_0402_10V6K
1
C572
2
0.1U_0402_10V6K
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
C550
1 2
0.1U_0402_10V6K
AGP_COMP
+3VS
R945
NAGP@47K_0402
1 2
0.1U_0402_10V6K
1
1
C556
2
2
0.1U_0402_10V6K
1
C573
2
R1005 0_0402_5%
A_OFF#<26>
+3VS
AGP8X_DET#
1
2
U27C
AK5
ALINK_AD0
AJ5
ALINK_AD1
AJ4
ALINK_AD2
AH4
ALINK_AD3
AJ3
ALINK_AD4
AJ2
ALINK_AD5
AH2
ALINK_AD6
AH1
ALINK_AD7
AG2
ALINK_AD8
AG1
ALINK_AD9
AG3
ALINK_AD10
AF3
ALINK_AD11
AF1
ALINK_AD12
AF2
ALINK_AD13
AF4
ALINK_AD14
AE3
ALINK_AD15
AE4
ALINK_AD16
AE5
ALINK_AD17
AE6
ALINK_AD18
AC2
ALINK_AD19
AC4
ALINK_AD20
AB3
ALINK_AD21
AB2
ALINK_AD22
AB5
ALINK_AD23
AB6
ALINK_AD24
AA2
ALINK_AD25
AA4
ALINK_AD26
AA5
ALINK_AD27
AA6
ALINK_AD28
Y3
ALINK_AD29
Y5
ALINK_AD30
Y6
ALINK_AD31
AG4
ALINK_CBE#0
AE2
ALINK_CBE#1
AC3
ALINK_CBE#2
AA3
ALINK_CBE#3
AD5
PCI_PAR/ALINK_NC
AC6
PCI_FRAME#/ALINK_STROBE#
AC5
PCI_IRDY#/ALINK_ACAT#
AD2
PCI_TRDY#/ALINK_END#
W4
INTA#
AD3
ALINK_DEVSEL#
AD6
PCI_STOP#/ALINK_OFF#
W5
ALINK_SBREQ#
W6
ALINK_SBGNT#
R570
V5
PCI_REQ#0/ALINK_NC
V6
PCI_GNT#0/ALINK_NC
K5
AGP2_GNT#/AGP3_GNT
K6
AGP2_REQ#/AGP3_REQ
M5
AGP8X_DET#
J6
AGP_VREF/TMDS_VREF
J5
AGP_COMP
216RC300M_BGA_718
0.1U_0402_10V6K
1
C557
2
0.1U_0402_10V6K
Ra
Rb
Rc
1
C559
C558
2
0.1U_0402_10V6K
0.1U_0402_10V6K
PART 3 OF 6
8X(M9+M10@)
169_0402_1%
324_0402_1%
100_0402_1%
0.1U_0402_10V6K
1
1
C560
2
2
+1.5VS
C574
1
C575
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
4
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
PCI Bus 0 / A-Link I/F
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
4X(NAGP@)
52.1_0402_1%
1K_0402_1%
1K_0402_1%
10U_0805_10V4Z
1
C561
2
0.1U_0402_10V6K
1
C576
2
0.1U_0402_10V6K
C577
C632
0.1U_0402_10V6K
1
C578
2
1
C562
2
0.1U_0402_10V6K
1
C937
2
0.1U_0402_10V6K
Note: PLACE C L OS E TO U 27 (N B R C300M)
L
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
AGP2_CBE#2/AGP3_CBE2
AGP_PAR
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
AGP_ST0
AGP_ST1
AGP_ST2
0.1U_0402_10V6K
1
1
C563
C564
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C938
C939
2
2
0.1U_0402_10V6K
AGP_AD0
Y2
AGP_AD1
W3
AGP_AD2
W2
AGP_AD3
V3
AGP_AD4
V2
AGP_AD5
V1
AGP_AD6
U1
AGP_AD7
U3
AGP_AD8
T2
AGP_AD9
R2
AGP_AD10
P3
AGP_AD11
P2
AGP_AD12
N3
AGP_AD13
N2
AGP_AD14
M3
AGP_AD15
M2
AGP_AD16
L1
AGP_AD17
L2
AGP_AD18
K3
AGP_AD19
K2
AGP_AD20
J3
AGP_AD21
J2
AGP_AD22
J1
AGP_AD23
H3
AGP_AD24
F3
AGP_AD25
G2
AGP_AD26
F2
AGP_AD27
F1
AGP_AD28
E2
AGP_AD29
E1
AGP_AD30
D2
AGP_AD31
D1
AGP_SBSTB
E5
AGP_SBSTB#
E6
AGP_ADSTB0
T3
AGP_ADSTB0#
U2
AGP_ADSTB1
G3
AGP_ADSTB1#
H2
AGP_CBE#0
R3
AGP_CBE#1
M1
AGP_CBE#2
L3
AGP_CBE#3
H1
AGP_IRDY#
P5
AGP_TRDY#
R6
AGP_STOP#
T6
AGP_PAR
T5
AGP_FRAME#
P6
AGP_DEVSEL#
R5
AGP_DBI_HI/PIPE#
C1
AGP_DBI_LO
D3
AGP_RBF#
N6
AGP_WBF#
N5
AGP_SBA0
C3
AGP_SBA1
C2
AGP_SBA2
D4
AGP_SBA3
E4
AGP_SBA4
F6
AGP_SBA5
F5
AGP_SBA6
G6
AGP_SBA7
G5
AGP_ST0
L6
AGP_ST1
M6
AGP_ST2
L5
1
C566
2
0.1U_0402_10V6K
1
C941
2
0.1U_0402_10V6K
3
0.1U_0402_10V6K
1
C567
2
0.1U_0402_10V6K
1
C942
2
0.1U_0402_10V6K
1
C565
2
0.1U_0402_10V6K
1
C940
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>
AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>
1
C568
2
0.1U_0402_10V6K
1
C943
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C944
2
1
C569
2
1
C945
2
0.1U_0402_10V6K
PIR BOM 92.06.23
@0.1U_0402_10V6K
C548
@10U_0805_6.3V6M
@0_0402_5%
+1.5VS
C947
@0.01U_0402_16V7Z
0.1U_0402_10V6K
1
1
C946
2
2
@0_0402_5%
L
@0.01U_0402_16V7Z
1
2
AGPAND LVDS MUXED SIGNALS
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA7 LVDS_SSIN
AGP_SBA1
AGP_SBA0
C549
R568
R560 NAPG@0_0402_5%
R561 NAPG@0_0402_5%
R562 NAPG@0_0402_5%
R563 NAPG@0_0402_5%
R564 @0_0402_5%
R565 @0_0402_5%
R994 NAPG@0_0402_5%
R995 NAPG@0_0402_5%
12
12
R569
@0_0402_5%
S0
S1
12
12
R572
@SM561BS_SO8
R573
@0_0402_5%
Note: PLACE C L OS E TO U 27 (N B R C300M)
ATI request
@0.01U_0402_16V7Z
1
1
C864
C948
2
2
C949
2
@0.01U_0402_16V7Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@0_0402_5%
R1086
2
U33
VDD
1
Xin/CLK
7
S0
6
S1
LVDS SPREAD SPECTRUM
1
C950
2
@0.01U_0402_16V7Z
Title
Size Document Number Rev
Date: Sheet
4
SSCLK
8
Xout
5
SSCC
VSS
3
R1088
@0_0402_5%
@0.01U_0402_16V7Z
1
1
C935
2
2
@0.01U_0402_16V7Z
星期四 八月
ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_STP# <17,27>
AGP_BUSY# <17,27>
LVDS_SSOUTAGP_SBA6
12
12
C936
DDC_DAT
DDC_CLK
L38
12
R567
@0_0402_5%
1
12
2
R574
@0_0402_5%
1
2
@BLM21P300S_0805
R1144 @0_0402_5%
C952
@10P_0402_25V8K
@0.01U_0402_16V7Z
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
1 2
1 2
R1087
1 2
@0_0402_5%
1
C933
2
@0.01U_0402_16V7Z
DDC_DAT <17,25>
DDC_CLK <17,25>
+3VS
LVDS_SSOUT
LVDS_SSIN
SSIN <17>
@0.01U_0402_16V7Z
1
C934
2
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-1811
1
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_CBE#[0..3] <17>
AGP_ST[0..2] <17>
SSOUT <17>
1
C951
2
of
10 66, 07, 2003
0.7
Page 11
5
4
3
2
1
D D
+2.5VS
12
L59
KC FBM-L11-201209-221LMAT_0805
1
C587
0.1U_0402_10V6K
KC FBM-L11-201209-221LMAT_0805
L60
+1.8VS
C C
REFCLK1_NB<24>
CLK_AGP_66M
12
R588
@10_0402_5%
C601
@15P_0402_50V8J
CLK_MEM_66M
B B
12
R591
@10_0402_5%
C603
@15P_0402_50V8J
L
CRMA_R
LUMA_R TV_LUMA
L
CRT_R<17,25>
CRT_G<17,25>
CRT_B<17,25>
A A
CRT_HSYNC<17,25>
CRT_VSYNC<17,25>
DDCCLK_R
DDCDATA_R
5
1 2
0.1U_0402_10V6K
L61
+1.8VS
KC FBM-L11-201209-221LMAT_0805
+1.8VS
KC FBM-L11-201209-221LMAT_0805
1
C588
2
1 2
0.1U_0402_10V6K
L62
1 2
10U_0805_16V4Z
R585 0_0402_5%
1 2
R587
68_0402_5%
wait 1% new part
+3VS
X2
4
VCC
1
ST
1
NAGP@27MHZ_20P_6N
C602
NAGP@0.1U_0402_16V7K
2
1
1
C590
C589
0.1U_0402_10V6K
2
2
1
C591
2
0.1U_0402_10V6K
R584 715 _0402_1%
1 2
12
3
OUT
2
GND
Note: PLACE CLOSE TO U27 (NB CHIP)
R597 NAPG@0_0402_5%
1 2
R598 NAPG@0_0402_5%
1 2
R599 NAPG@0_0402_5%
1 2
TV_CRMA
TV_COMPSCOMPS_R
Note: PLACE CLOSE TO U6 (VGA CHIP)
CRT_R
R594 NAPG@0_0402_5%
1 2
R595 NAPG@0_0402_5%
1 2
CRT_B BLUE_R
R596 NAPG@0_0402_5%
1 2
CRT_HSYNC
CRT_VSYNC
RP103
1 4
2 3
NAGP@0_4P2R_0402_5%
RP104
14
NAGP@0_4P2R_0402_5%
23
HSYNC_R
VSYNC_R
3VDDCCL
3VDDCDA
RED_R
GREEN_RCRT_G
4
3VDDCCL <17,25>
3VDDCDA <17,25>
2
1
C592
2
CLK_NB_BCLK<24>
CLK_NB_BCLK#<24>
CLK_AGP_66M<24>
CLK_MEM_66M<24>
27M_TV 27M_TV_R
R592 NAGP@22_0402_5%
PLLVDD_18
1
PLLVSS_18
C593
0.1U_0402_10V6K
2
RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_BCLK
CLK_NB_BCLK#
CLK_AGP_66M
CLK_MEM_66M
TV_CRMA <17,41,48>
TV_LUMA <17,41,48>
TV_COMPS <17,41,48>
L58
1 2
FBM-11-160808-121-T_0603
U27D
G9
VDDR3
H9
VDDR3
A14
AVDD_25
B13
AVSSN
B14
AVDDDI_18
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
C8
DACHSYNC
D9
DACVSYNC
C14
RSET
A4
XTALIN
B4
XTALOUT
A5
HCLKIN
B5
HCLKIN#
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
D8
ALINK_CLK
B2
AGPCLKOUT
B3
AGPCLKIN
A3
EXT_MEM_CLK
D7
USBCLK
B7
REF27
C5
OSC
216RC300M_BGA_718
L
+3VS
1
C586
0.1U_0402_10V6K
2
PART 4 OF 6
LVDS
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
C_R
Y_G
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
CRMA_R
E15
LUMA_R
C15
COMPS_R
D15
DDCCLK_R
D6
DDCDATA_R
C6
D5
A8
B8
R590 1K_0402_5%
TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
Q97
@2N7002 1N_SOT23
D
1 3
R589 @0_0402_5%
C594
0.1U_0402_10V6K
C598
0.1U_0402_10V6K
S
G
2
1
2
0.1U_0402_10V6K
1
2
CPUCLK_STP#
0.1U_0402_10V6K
1
C596
C595
2
10U_0805_16V4Z
1
C600
C599
2
10U_0805_16V4Z
+3VS
Note: PLACE CLOSE TO U27 (NB CHIP)
RC300M_X1
@1M_0402_1%
RC300M_X2
12
R593
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C604
12
@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201
C605
@18P_0402_50V8K
2
KC FBM-L11-201209-221LMAT_0805
1 2
L63
1
2
KC FBM-L11-201209-221LMAT_0805
1 2
L64
1
2
CPUCLK_STP# <5,26,56>
PCI_RST# <26,30,31,34,35,36,43,46>
Title
Size Document Number Rev
Date: Sheet
星期四 八月
+1.8VS
+1.8VS
Compal Electronics, Inc.
ATI RC300M-VIDEO I/F
LA-1811
1
0.7
of
11 66, 07, 2003
Page 12
5
4
3
2
1
+1.5VS +2.5V
D D
C C
B B
+VCC_CORE
+3VS
U27E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
216RC300M_BGA_718
PART 5 OF 6
CORE PWR
CPU I/F PWRALINK PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
MEM I/F PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
AGP PWR
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
+1.5VS
R418
1 2
R419 NAGP@0_0603_5%
1 2
+1.8VS
M9-M10@0_0603_5%
+1.5VS
+3VS
U27F
A29
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB8
VSS
AC1
VSS
AC11
VSS
AC14
VSS
AC16
VSS
AC20
VSS
AC30
VSS
AD11
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD4
VSS
AE27
VSS
AF30
VSS
AF5
VSS
AG10
VSS
AG13
VSS
AG16
VSS
AG19
VSS
AG22
VSS
AG25
VSS
AG7
VSS
AH28
VSS
AH3
VSS
AJ1
VSS
AK13
VSS
AK2
VSS
AK22
VSS
AK29
VSS
AK4
VSS
AK7
VSS
B1
VSS
B16
VSS
B30
VSS
C19
VSS
C23
VSS
C27
VSS
C4
VSS
D21
VSS
D25
VSS
E3
VSS
E8
VSS
E9
VSS
F27
VSS
F4
VSS
F8
VSS
G14
VSS
G15
VSS
G18
VSS
G20
VSS
H14
VSS
H15
VSS
H18
VSS
H20
VSS
H27
VSS
H4
VSS
H8
VSS
J7
VSS
216RC300M_BGA_718
PART 6 OF 6
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8
+1.8VS
C579
10U_0805_10V4Z
A A
5
4
1
C580
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C581
2
1
C582
2
0.1U_0402_10V6K
1
1
C583
0.1U_0402_10V6K
2
2
Compal Electronics, Inc.
ATI RC300M-POWER
星期四 八月
LA-1811
0.7
of
12 66, 07, 2003
1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Page 13
5
4
3
2
1
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
R420 10K_0402_5%
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
5
R422 4.7K_0402_5%
R425 4.7K_0402_5%
R427 10K_0402_5%
1 2
R429 @4. 7K_0402_5%
R430 @10K_0402_5%
1 2
R431 4.7K_0402_5%
R434 10K_0402_5%
1 2
R435 @4. 7K_0402_5%
R438 10K_0402_5%
1 2
R440 @4. 7K_0402_5%
R443 10K_0402_5%
1 2
R444 @4. 7K_0402_5%
R448 10K_0402_5%
1 2
R452 10K_0402_5%
1 2
R454 @4. 7K_0402_5%
R457 @4. 7K_0402_5%
R461 10K_0402_5%
1 2
R462 @4. 7K_0402_5%
R464 @4. 7K_0402_5%
R465 4.7K_0402_5%
R466 @4. 7K_0402_5%
R467 @4. 7K_0402_5%
R468 @4. 7K_0402_5%
R469 @4. 7K_0402_5%
1 2
R424 10K_0402_5%
1 2
2 1
D85
RB751V_SOD323
2 1
D86
RB751V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
BSEL1 <5,24>
+3VS
BSEL0 <5,24>
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcS hortReset#
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3: NOT USED
A_CBE#0 :NO USED
4
A_AD[31..30 ] : FSB CLK SPEED
DEFAULT: 01
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD[0..31]
A_CBE#[0..3]
A_AD18
A_AD17
A_PAR<10,26>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
R421 @4. 7K_0402_5%
R423 4.7K_0402_5%
R426 @4. 7K_0402_5%
R428 4.7K_0402_5%
A_PAR
R463 @4. 7K_0402_5%
R460 4.7K_0402_5%
+3VS
+3VS
+3VS
2
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
0: DEBUG MODE
1: NORMAL
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI RC300M-SYSTEM STRAP
星期四 八月
LA-1811
of
13 66, 07, 2003
1
0.7
Page 14
5
DDRA_SDQ[0..63]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
D D
C C
B B
Group 0 sweep Group 1
Group 6 sweep Group 7
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
3
+2.5V
JP24
1
VREF
3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_CLK0<9>
DDRA_CLK0#<9>
DDRA_CKE_R1<9,16>
DDRA_WE#<9,15,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE_R1 DDRA_CKE_R0
DDRA_ADD12
DDRA_ADD9
DDRA_ADD7
DDRA_ADD5
DDRA_ADD3
DDRA_ADD1
DDRA_ADD10
DDRA_ADD13
DDRA_WE#
DDRA_CS#0 DDRA_CS#1
DDRA_ADD15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<15,24,27>
SMB_CK_CLK2<15,24,27>
+3VS
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
AMP_1565918-1
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
DIMM0
REVERSE
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
S1#
DU
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
DU
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_ADD11
DDRA_ADD8
DDRA_ADD6
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_ADD14
DDRA_RAS#
DDRA_CAS#
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
2
L
DDRA_CKE_R0 <9,16>
DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>
DDRA_CLK1# <9>
DDRA_CLK1 <9>
Group 6 sweep Group 7
+2.5V+2.5V
C411
0.1U_0402_10V6K
C412
0.1U_0402_10V6K
12
12
2
1
DDRA_VREF
2
1
DDRA_VREF trace width of
20mils and space 20mils(min)
R472
1K_0603_1%
R473
1K_0603_1%
1
System Memory Decoupling caps
+2.5V
1
C413
0.1U_0402_10V6K
2
A A
+2.5V
1
2
5
C426
0.1U_0402_10V6K
1
C414
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
C415
0.1U_0402_10V6K
2
1
C428
0.1U_0402_10V6K
2
1
C416
0.1U_0402_10V6K
2
1
C429
0.1U_0402_10V6K
2
1
C417
0.1U_0402_10V6K
2
1
C430
0.1U_0402_10V6K
2
1
C418
0.1U_0402_10V6K
2
1
C431
0.1U_0402_10V6K
2
4
1
C419
0.1U_0402_10V6K
2
1
C432
0.1U_0402_10V6K
2
1
C420
0.1U_0402_10V6K
2
1
C433
0.1U_0402_10V6K
2
1
C421
0.1U_0402_10V6K
2
1
C434
0.1U_0402_10V6K
2
1
C422
0.1U_0402_10V6K
2
1
C435
0.1U_0402_10V6K
2
3
1
C423
0.1U_0402_10V6K
2
1
C436
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
1
C424
0.1U_0402_10V6K
2
1
C437
0.1U_0402_10V6K
2
1
C425
10U_0805_6.3V6M
2
1
C438
10U_0805_6.3V6M
2
Title
Size Document N u mb er Re v
2
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT1
LA-1811
星期四 八月
, 2003
1
0.7
of
14 66, 07
Page 15
5
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
DDRA_SDM[0..7]<9,14,16>
D D
C C
B B
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
Group 0 sweep Group 1
DDRA_CLK3<9>
DDRA_CLK3#<9>
Group 6 sweep Group 7
+2.5V
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE3
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#2
DDRA_SMA15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_DAT2<14,24,27>
SMB_CK_CLK2<14,24,27>
+3VS
JP23
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
AMP_1565917-1
4
DIMM1
STANDARD
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
3
C392
0.1U_0402_10V6K
DDRB_VREF
C393
0.1U_0402_10V6K
+2.5V+2.5V
12
12
DDRA_CKE_R3<9,16>
R470
1K_0603_1%
R471
1K_0603_1%
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
DDRA_SMA9
DDRA_SMA12
DDRA_SMA5
DDRA_SMA7
DDRA_SMA1
DDRA_SMA3
DDRA_SMA13
DDRA_SMA10
DDRA_WE# DDRA_SWE#
DDRA_CS#2 DDRA_SCS#2
+2.5V
2
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
22
VDD
24
26
DM1
28
VSS
30
32
34
VDD
36
VDD
38
VSS
40
VSS
42
44
46
VDD
48
DM2
50
52
VSS
54
56
58
VDD
60
62
DM3
64
VSS
66
68
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
88
VSS
90
VSS
92
VDD
94
VDD
96
98
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
120
122
S1#
124
DU
126
VSS
128
130
132
VDD
134
DM4
136
138
VSS
140
142
144
VDD
146
148
DM5
150
VSS
152
154
156
VDD
158
160
CK1
162
VSS
164
166
168
VDD
170
DM6
172
174
VSS
176
178
180
VDD
182
184
DM7
186
VSS
188
190
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE2
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#3
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
+3VS
DDRA_CLK4# <9>
DDRA_CLK4 <9>
2
1
2
1
DDRB_VREF trace width of
L
20mils and space
20mils(min)
2
DDRA_CKE3DDRA_CKE_R3
12
R1122 10_0402_5%
RP26
DDRA_ADD9
1 4
DDRA_ADD12
2 3
10_0404_4P2R_5%
RP32
DDRA_ADD5
1 4
DDRA_ADD7
2 3
10_0404_4P2R_5%
RP38
DDRA_ADD1
1 4
DDRA_ADD3
2 3
10_0404_4P2R_5%
RP42
DDRA_ADD13 DDRA_SMA14DDRA_ADD14
1 4
DDRA_ADD10
2 3
10_0404_4P2R_5%
12
R392 10_0402_5%
12
R401 10_0402_5%
DDRA_ADD15DDRA_SMA15
12
R391 10_0402_5%
DDRA_CKE_R2<9,16>
1
DDRA_CKE2DDRA_CKE_R2
12
R1121 10_0402_5%
RP29
1 4
2 3
10_0404_4P2R_5%
RP35
1 4
2 3
10_0404_4P2R_5%
RP39
1 4
2 3
10_0404_4P2R_5%
12
12
12
12
DDRA_SMA8
DDRA_SMA11
DDRA_SMA4
DDRA_SMA6
DDRA_SMA0
DDRA_SMA2
DDRA_ADD8
DDRA_ADD11
DDRA_ADD4
DDRA_ADD6
DDRA_ADD0
DDRA_ADD2
R390 10_0402_5%
DDRA_RAS#< 9,14,16>
DDRA_CAS#< 9,14,16>
DDRA_CS#3<9,16>
DDRA_RAS# DDRA_S RAS#
R396 10_0402_5%
DDRA_CAS# DDRA_S CAS#
R393 10_0402_5%
DDRA_CS#3 DDRA_SCS#3
R402 10_0402_5%
System Memory Decoupling caps
+2.5V
1
2
+2.5V
1
2
C394
22U_1206_10V4Z
C403
0.1U_0402_10V6K
A A
1
C395
0.1U_0402_10V6K
2
1
C404
0.1U_0402_10V6K
2
5
1
C396
0.1U_0402_10V6K
2
1
C405
0.1U_0402_10V6K
2
1
C397
0.1U_0402_10V6K
2
1
C406
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C407
0.1U_0402_10V6K
2
1
C399
0.1U_0402_10V6K
2
1
C408
0.1U_0402_10V6K
2
1
C400
0.1U_0402_10V6K
2
1
C409
0.1U_0402_10V6K
2
4
1
C401
10U_0805_6.3V6M
2
1
C410
0.1U_0402_10V6K
2
1
C402
10U_0805_6.3V6M
2
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR-SODIMM SLOT2
LA-1811
星期四 八月
, 2003
1
0.7
of
15 66, 07
Page 16
5
4
3
2
1
DDR Termination resistors & Decoupling caps
+1.25VS +1.25VS
DDRA_SDQ[0..63]<9,14,15>
DDRA_SDQS[0..7]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
RP65
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP68
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP71
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP74
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP77
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP80
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP83
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP86
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
RP90
1 8
2 7
3 6
4 5
56 _0804_8P4R_5%
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ12
DDRA_SDQ13
D D
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQS2
DDRA_SDQ18
C C
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ25
DDRA_SDQS3
R474
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
RP66
DDRA_SDQ30
18
DDRA_SDQ31
27
DDRA_SDQ26
36
DDRA_SDQ27
45
56 _0804_8P4R_5%
RP69
DDRA_CKE_R0
14
DDRA_CKE_R1
23
33_0404_4P2R_5%
RP75
DDRA_ADD9
18
DDRA_ADD3
27
DDRA_ADD7
36
DDRA_ADD5
45
33_0804_8P4R_5%
RP78
DDRA_ADD1
18
DDRA_ADD10
27
DDRA_ADD13
36
DDRA_ADD15
45
33_0804_8P4R_5%
RP81
DDRA_ADD8
18
DDRA_ADD6
27
DDRA_ADD4
36
DDRA_ADD2
45
33_0804_8P4R_5%
RP84
DDRA_ADD0
18
DDRA_ADD14
27
DDRA_RAS#
36
DDRA_CAS#
45
33_0804_8P4R_5%
RP87
DDRA_WE#
14
DDRA_ADD11
23
33_0404_4P2R_5%
RP89
DDRA_CS#0
14
DDRA_CS#3
23
33_0404_4P2R_5%
DDRA_ADD12
12
33_0402_5%
RP72
DDRA_CKE_R3
14
DDRA_CKE_R2
23
33_0404_4P2R_5%
RP92
DDRA_CS#1
14
DDRA_CS#2
23
33_0404_4P2R_5%
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
DDRA_RAS# <9,14,15>
DDRA_CAS# <9,14,15>
DDRA_ WE # <9,14,15>
DDRA_CS#0 <9,14>
DDRA_CS#3 <9,15>
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
DDRA_CS#1 <9,14>
DDRA_CS#2 <9,15>
RP67
DDRA_SDQ32
18
DDRA_SDQ33
27
DDRA_SDQ36
36
DDRA_SDQ37
45
56 _0804_8P4R_5%
RP70
DDRA_SDQS4
18
DDRA_SDQ34
27
DDRA_SDM4
36
DDRA_SDQ38
45
56 _0804_8P4R_5%
RP73
DDRA_SDQ35
18
DDRA_SDQ39
27
DDRA_SDQ44
36
DDRA_SDQ40
45
56 _0804_8P4R_5%
RP76
DDRA_SDQ46
18
DDRA_SDQ47
27
DDRA_SDQ42
36
DDRA_SDQ43
45
56 _0804_8P4R_5%
RP79
DDRA_SDQ45
18
DDRA_SDM5
27
DDRA_SDQ41
36
DDRA_SDQS5
45
56 _0804_8P4R_5%
RP82
DDRA_SDQ60
18
DDRA_SDQ61
27
DDRA_SDQ56
36
DDRA_SDQ57
45
56 _0804_8P4R_5%
RP85
DDRA_SDM7
18
DDRA_SDQ62
27
DDRA_SDQS7
36
DDRA_SDQ58
45
56 _0804_8P4R_5%
RP88
DDRA_SDQ63
18
DDRA_SDQ52
27
DDRA_SDQ59
36
DDRA_SDQ48
45
56 _0804_8P4R_5%
RP91
DDRA_SDQ53
18
DDRA_SDM6
27
DDRA_SDQ49
36
DDRA_SDQS6
45
56 _0804_8P4R_5%
RP93
DDRA_SDQ54
18
DDRA_SDQ55
27
DDRA_SDQ51
36
DDRA_SDQ50
45
56 _0804_8P4R_5%
+2.5V
1
C475
0.1U_0402_10V6K
2
+2.5V
1
C493
0.1U_0402_10V6K
2
1
C476
0.1U_0402_10V6K
2
1
C494
0.1U_0402_10V6K
2
1
C477
0.1U_0402_10V6K
2
1
C495
0.1U_0402_10V6K
2
1
C478
0.1U_0402_10V6K
2
1
C496
0.1U_0402_10V6K
2
1
2
1
2
+1.25VS
C479
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
1
C480
0.1U_0402_10V6K
2
1
C481
0.1U_0402_10V6K
2
1
2
+1.25VS
C482
0.1U_0402_10V6K
B B
+2.5V
1
C451
0.1U_0402_10V6K
2
+1.25VS
1
C459
0.1U_0402_10V6K
2
+1.25VS
1
C467
0.1U_0402_10V6K
2
+1.25VS
1
A A
C483
0.1U_0402_10V6K
2
1
C452
0.1U_0402_10V6K
2
1
C460
0.1U_0402_10V6K
2
1
C468
0.1U_0402_10V6K
2
1
C484
0.1U_0402_10V6K
2
1
C453
0.1U_0402_10V6K
2
1
C461
0.1U_0402_10V6K
2
1
C469
0.1U_0402_10V6K
2
1
C485
0.1U_0402_10V6K
2
5
1
C454
0.1U_0402_10V6K
2
1
C462
0.1U_0402_10V6K
2
1
C470
0.1U_0402_10V6K
2
1
C486
0.1U_0402_10V6K
2
1
C455
0.1U_0402_10V6K
2
1
C463
0.1U_0402_10V6K
2
1
C471
0.1U_0402_10V6K
2
1
C487
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
1
C464
0.1U_0402_10V6K
2
1
C472
0.1U_0402_10V6K
2
1
C488
0.1U_0402_10V6K
2
1
C457
0.1U_0402_10V6K
2
1
C465
0.1U_0402_10V6K
2
1
C473
0.1U_0402_10V6K
2
1
C489
4.7U_0805_16V6K
2
4
1
C458
0.1U_0402_10V6K
2
+1.25VS
1
C466
0.1U_0402_10V6K
2
1
C474
0.1U_0402_10V6K
2
1
C490
4.7U_0805_16V6K
2
1
+
C491
@100U_D2_10M_R45
2
1
+
C492
100U_D2_10M_R45
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.
2
Title
Size Document N u mb er Re v
Date: Sheet
Compal Electronics, Inc.
DDR Termination Resistors
LA-1811
星期四 八月
, 2003
1
0.7
of
16 66, 07
Page 17
5
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
D D
C184 @10P_0402_50V8K
1 2
CLK_AGP_EXT_66M<24>
C C
VREF_8X_IN<10>
B B
+1.5VS
If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%
A A
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R249 @10_0402_5%
1
C185
0.1U_0402_10V6K
2
(Closed to M26)
(15mil)
1 2
R264 137_0603_1%
AGP8X_DET#
Low:
AGP3.0
SSIN<10>
R936
@4.7K_0402_5%
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#0
1 2
M9-M10@1K_5%
AGP8X_DET#<10>
1 2
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
CLK_AGP_EXT_66M
NB_RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
(25mil)
AGP_DBI_HI/PIPE#
AGP_DBI_LO
TV_CRMA
TV_LUMA
TV_COMPS
SSOUT
XTALIN
SUSSTAT#
1 2
NB_RST#<8,26,39>
AGP_REQ#<10>
AGP_GNT#<10>
AGP_PAR<10>
AGP_STOP#<10>
AGP_DEVSEL#<10>
AGP_TRDY#<10>
AGP_IRDY#<10>
AGP_FRAME#<10>
PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
AGP_STP#<10,27>
AGP_BUSY#<10,27>
AGP_RBF#<10>
AGP_ADSTB0<10>
AGP_ADSTB1<10>
AGP_ADSTB0#<10>
AGP_ADSTB1#<10>
AGP_SBSTB<10>
AGP_SBSTB#<10>
AGP_DBI_HI/PIPE#<10>
AGP_DBI_LO<10>
R265
(15mil)
R266 715_0603_1%
TV_CRMA<11,41,48>
TV_LUMA<11,41,48>
TV_COMPS<11,41,48>
SSIN
SSOUT<10>
R275 1K_0603_5%
Leave These Pin No Connecting, When
Using M10-P I nter nal Spread Spectrum
5
U6A
H29
AD0
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AH30
STP_AGP#
AH29
AGP_BUSY#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
M29
AD_STBS_0
V26
AD_STBS_1
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB29
SB_STBF
AB28
SB_STBS
M26
AGPREF
M27
AGPTEST
AB25
DBI_HI
AB26
DBI_LO
AC25
AGP8X_DET#
AE11
DMINUS
AF11
DPLUS
AK21
R2SET
AJ23
C_R
AJ22
Y_G
AK22
COMP_B
AJ24
H2SYNC
AK24
V2SYNC
AG23
DDC3CLK
AG24
DDC3DATA
AK25
SSIN
AJ25
SSOUT
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
AG26
SUS_STAT#
SA002160E00(0301021300)
4
M10-P/(M9+X)
(1/6)
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
PCI/AGPAGP8XCLK
TXOUT_U0N
TXOUT_U1N
TXOUT_U2N
TXOUT_U3N
BLON/(BLON#)
THRM
SSC DAC2
TEST_MCLK/(NC)
TEST_YCLK/(NC)
PLLTEST/(NC)
RSTB_MSK/(NC)
4
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
VREFG/(NC)
ROMCS#
DVOMODE
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0P
TXOUT_U1P
TXOUT_U2P
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
MCLK_SPREAD
AF2
AG4
AF5
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AE10
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
R267 100K_0402_5%
AF12
AK27
R
AJ27
G
AJ26
B
AG25
AH25
AH26
AF25
AF24
AF26
R274 10K_0402_5%
B6
E8
AE25
AG29
R276
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N
STRAP_R
STRAP_S
STRAP_T
DVOMODE
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACLKTXACLK+
TXB0TXB0+
TXB1TXB1+
TXB2TXB2+
TXBCLKTXBCLK+
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
AGP_RSET
3VDDCDA
3VDDCCL
1 2
1 2
+3VS
12
R955
@10K_0402_5%
R235 @1K_0402_5%
R237
1 2
VREFG
ENAVDD
0_0402_5%
DDC_DAT <10,25>
DDC_CLK <10,25>
1 2
R258 0_0402_5%
TXA0- <25>
TXA0+ <25>
TXA1- <25>
TXA1+ <25>
TXA2- <25>
TXA2+ <25>
TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>
TXBCLK- <25>
TXBCLK+ <25>
ENAVDD <10,25,46>
R829
R830 M10@0_0402_5%
ENABLT#
M9@0_0402_5%
(15mil)
1 2
R272 499_0402_1%
3VDDCDA <11,25>
3VDDCCL <11,25>
1K_0603_5%
1 2
XTALIN_SS
3
(25 mil)
DRAM128M
+3VS
12
+3VS
12
12
R1149
@10K_0402_5%
For 8Mx32 VGA DRAM only
R234
M10@1K_0603_1%
R239
M10@1K_0603_1%
2
AGP, DAC & LVDS INTERFACE
GPIO8
GPIO7
GPIO4
GPIO5
GPIO6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO9
GPIO11
GPIO12
GPIO13
+3VS
DATA
CLK
+3VS
12
R253
10K_0402_5%
SUSSTAT#
M10-PM9+X
Ra 261_0603_1%
ENABLT# <10,25>
M10_BKOFF# <25>
Rb
180_0603_5%
150_0402_5%
150_0402_5%
1
2
For VGA DDR spread sprum
CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>
+3VS
Selection Table For W180
SS%
0
1
Spread % Setting for
Freq. Range
Fin>Fout>Fin-1.25%
Fin>Fout>Fin-3.75%
+3VS
R269 10K_0402_5%
R270 10K_0402_5%
12
12
L
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
1
+3VS
ID_Disable
STRAP_A
VGA_Disable
STRAP_B
STRAP_D
STRAP_E
STRAP_F
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_O
STRAP_L
STRAP_M
STRAP_N
STRAP_R
STRAP_S
STRAP_T
R232 @10K_0402_5%
R233 @10K_0402_5%
R236 @10K_0402_5%
R238 @10K_0402_5%
R240 @10K_0402_5%
R241 M10@10K_0402_5%
R242 @10K_0402_5%
R243 M10@10K_0402_5%
R244 @10K_0402_5%
R245 @10K_0402_5%
R246 @10K_0402_5%
R247 @10K_0402_5%
R248 @10K_0402_5%
R250 @10K_0402_5%
R252 @10K_0402_5%
R254 @10K_0402_5%
R255 @10K_0402_5%
R256 @10K_0402_5%
R257 @10K_0402_5%
R259 @10K_0402_5%
R260 @10K_0402_5%
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
12
R261
10K_0402_5%
X1
4
VDD
1
OE
27MHZ_15P
C186
0.1U_0402_10V6K
U7
1
X1/CLK
7
FS1
8
FS2
3.3V OSC out for W18 0
FREQOUT
3
OUT
GND
6
VDD
CLKOUT
GND
W180-01GT_SO8
3
2
0.1U_0402_10V6K
1
1
C188
2
2
0.1U_0402_10V6K
5
2
X2
4
SS%
SS%
R262 180_0603_5%
R268
Ra
1 2
150_0402_5%
1
C189
2
0.1U_0402_10V6K
1 2
R273
10K_0402_5%
1 2
Rb
22_0402_5%
R263
C190
R271 @10K_0402_5%
1.5V OSC out for M9+X
1.2V OSC out for
M10-P
XTALIN
12
C187
@15P_0402_50V8J
L13
1 2
1
2.2U_0603_6.3V4Z
C191
FCM2012C-800_0805
2
XTALIN_SSFREQOUT
+3VS
12
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P & M9+X (AGP BUS)
星期二 九月
LA-1811
17 66, 02, 2003
1
+3VS
0.7
of
Page 18
5
4
3
2
1
D D
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
C C
B B
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
NMDA[0..63]<22>
NMAA[0..13]<22>
NDQMA[0..7]<22>
NDQSA[0..7]<22>
U6B
L25
DQA0
L26
DQA1
K25
DQA2
K26
DQA3
J26
DQA4
H25
DQA5
H26
DQA6
G26
DQA7
G30
DQA8
D29
DQA9
D28
DQA10
E28
DQA11
E29
DQA12
G29
DQA13
G28
DQA14
F28
DQA15
G25
DQA16
F26
DQA17
E26
DQA18
F25
DQA19
E24
DQA20
F23
DQA21
E23
DQA22
D22
DQA23
B29
DQA24
C29
DQA25
C25
DQA26
C27
DQA27
B28
DQA28
B25
DQA29
C26
DQA30
B26
DQA31
F17
DQA32
E17
DQA33
D16
DQA34
F16
DQA35
E15
DQA36
F14
DQA37
E14
DQA38
F13
DQA39
C17
DQA40
B18
DQA41
B17
DQA42
B15
DQA43
C13
DQA44
B14
DQA45
C14
DQA46
C16
DQA47
A13
DQA48
A12
DQA49
C12
DQA50
B12
DQA51
C10
DQA52
C9
DQA53
B9
DQA54
B10
DQA55
E13
DQA56
E12
DQA57
E10
DQA58
F12
DQA59
F11
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
SA002160E00(0301021300)
NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]
M10-P/(M9+X)
(2/6)
AA12/(AA13)
AA13/(AA12)
AA14/(NC)
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MEMORY INTERFACE
A
MVREFD
MVREFS/(NC)
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
DIMA0
DIMA1
NMAA0
E22
NMAA1
B22
NMAA2
B23
NMAA3
B24
NMAA4
C23
NMAA5
C22
NMAA6
F22
NMAA7
F21
NMAA8
C21
NMAA9
A24
NMAA10
C24
NMAA11
A25
NMAA12
E21
NMAA13
B20
C19
NDQMA0
J25
NDQMA1
F29
NDQMA2
E25
NDQMA3
A27
NDQMA4
F15
NDQMA5
C15
NDQMA6
C11
NDQMA7
E11
NDQSA0
J27
NDQSA1
F30
NDQSA2
F24
NDQSA3
B27
NDQSA4
E16
NDQSA5
B16
NDQSA6
B11
NDQSA7
F10
MVREFD
MVREFS
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA
NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#
NMRASA# <22>
NMCASA# <22>
NMWEA# <22>
NMCSA0# <22>
NMCSA1# <22>
NMCKEA <22>
NMCLKA0 <22>
NMCLKA0# <22>
NMCLKA1 <22>
NMCLKA1# <22>
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
D30
B13
B7
B8
MEMORY
INTERFACE A
MVREFD
0.1U_0402_10V6K
MVREFS
M10@0.1U_0402_16V4Z
Poped for M10-P
Depoped for
M9+X
C498
C503
1
2
1
2
(25 mil)
(25 mil)
+2.5VS
12
R475
1K_0402_1%
12
R478
1K_0402_1%
+2.5VS
12
R486
M10@1K_0402_1%
12
R487
M10@1K_0402_1%
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-A
星期四 八月
LA-1811
0.7
of
18 66, 07, 2003
1
Page 19
5
D D
4
3
2
1
MEMORY
INTERFACE B
NMDB[0..63]<23>
NMAB[0..13]<23>
NDQMB[0..7]<23>
NDQSB[0..7]<23>
C C
B B
NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
U6C
M10-P/(M9+X)
D7
DQB0
F7
(3/6)
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46
AA2
DQB47
AA6
DQB48
AA5
DQB49
AB6
DQB50
AB5
DQB51
AD6
DQB52
AD5
DQB53
AE5
DQB54
AE4
DQB55
AB2
DQB56
AB3
DQB57
AC2
DQB58
AC3
DQB59
AD3
DQB60
AE1
DQB61
AE2
DQB62
AE3
DQB63
SA002160E00(0301021300)
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12/(AB13)
AB13/(AB12)
AB14/(NC)
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
MEMORY INTERFACE B
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
MEMVMODE0
MEMVMODE1
DIMB0
DIMB1
MEMTEST
NMAB0
N5
NMAB1
M1
NMAB2
M3
NMAB3
L3
NMAB4
L2
NMAB5
M2
NMAB6
M5
NMAB7
P6
NMAB8
N3
NMAB9
K2
NMAB10
K3
NMAB11
J2
NMAB12
P5
NMAB13
P3
P2
NDQMB0
E6
NDQMB1
B2
NDQMB2
J5
NDQMB3
G3
NDQMB4
W6
NDQMB5
W2
NDQMB6
AC6
NDQMB7
AD2
NDQSB0
F6
NDQSB1
B3
NDQSB2
K6
NDQSB3
G1
NDQSB4
V5
NDQSB5
W1
NDQSB6
AC5
NDQSB7
AD1
NMRASB#
R2
NMCASB#
T5
NMWEB#
T6
NMCSB0#
R5
NMCSB1#
R6
NMCKEB
R3
NMCLKB0
N1
NMCLKB0#
N2
NMCLKB1
T2
NMCLKB1#
T3
R509 4.7K_0402_5%
C6
1 2
R510 4.7K_0402_5%
C7
1 2
E3
AA3
R511 47_0603_1%
C8
1 2
(15mil)
NMRASB# <23>
NMCASB# <23>
NMWEB# <23>
NMCSB0# <23>
NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>
NMCLKB0# <23>
NMCLKB1 <23>
NMCLKB1# <23>
+1.8VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X DDR-B
星期四 八月
LA-1811
0.7
of
19 66, 07, 2003
1
Page 20
5
4
3
2
1
U6D
M10-P/(M9+X)
VDDR1
(4/6)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
TPVDD
TPVSS
AVDD
A2VDD
A2VDD
A2VDDQ
A2VSSN
A2VSSN
A2VSSQ
AVSSN
AVSSQ
SA002160E00(0301021300)
VDDRH0
VDDRH1
VSSRH0
VSSRH1
MPVDD
MPVSS
PVDD
PVSS
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
I/O POWER
LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
LVDDR_18
LVDDR_18
LPVDD
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
VDD1DI
VDD2DI
VSS1DI
VSS2DI
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
AC11
AC20
AK12
AJ12
AH24
AG21
AH21
AF22
AH22
AJ21
AF23
AH23
AD24
B1
B30
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
D5
D8
D11
D13
D14
D17
D20
D23
D26
E27
F4
G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
T4
T7
T8
V4
V7
V8
D19
R4
H11
H20
L23
P8
Y23
Y8
D D
C C
+2.5VS
+1.5VS
+2.5VS
Poped for
M10-P
R277 M10@0_0402_5%
1 2
R278 M10@0_0402_5%
1 2
R279 M10@0_0805_5%
1 2
Poped for M10-P
Poped for M9+X
R282 M9@0_0805_5%
B B
A A
+1.8VS
1 2
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
F18
N6
F19
M6
A7
A6
AK28
AJ28
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
AC10
AC9
AD10
AD9
AG7
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
AE20
AE17
AF21
AE15
AJ20
AF20
AF15
AE19
AE16
AJ19
AE24
AE22
AE23
AE21
AF13
AF14
AG13
AG14
AH12
+2.5VDDRH
+1.5VS
+LVDDR+VDDC1.5
R281 M9@0_0603_5%
+VDD_MEMPLL1.8
+VDD_PLL1.8
+3VS
Poped for M10-P
R280 M10@0_0603_5%
1 2
1 2
+VDD_PNLIO2.5
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_PNLIO1.8
+VDD_PNLIO1.8
Poped for M9+X
C192
22U_1206_10V4Z
C197
22U_1206_10V4Z
+VDD_DAC2.5
C202
2.2U_0603_6.3V4Z
+VDD_PNLPLL1.8
C206
10U_0805_6.3V6M
+VDD_DAC1.8
C211
10U_0805_6.3V6M
+VDD_PNLIO1.8
C214
10U_0805_6.3V6M
+VDD_PNLIO2.5
C218
10U_0805_6.3V6M
+3VS
1
2
+1.5VS
1
2
1
2
1
2
1
2
1
2
1
2
C193
0.1U_0402_10V6K
C198
0.1U_0402_10V6K
(20 mil)
(20 mil)
C207
0.1U_0402_10V6K
(20 mil)
(20 mil)
(20 mil)
POWER
INTERFACE
0.1U_0402_10V6K
1
1
C194
C195
2
2
0.01U_0402_16V7K
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
L
0.1U_0402_10V6K
1
1
C199
C92
2
2
0.1U_0402_10V6K
L14
1 2
CHB1608U301_0603
1
C203
0.1U_0402_10V6K
2
1 2
CHB1608U301_0603
1
1
C208
0.1U_0402_10V6K
2
2
L18
1 2
CHB1608U301_0603
1
C212
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
C215
0.1U_0402_10V6K
C219
0.1U_0402_10V6K
2
1
2
C216
0.1U_0402_10V6K
C220
0.01U_0402_16V7K
1
1
C196
2
2
0.01U_0402_16V7K
1
1
C200
2
2
+2.5VS
L16
+1.8VS
1
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C201
2
0.01U_0402_16V7K
+1.8VS
10U_0805_6.3V6M
0.1U_0402_10V6K
1
C217
2
L21
1 2
CHB1608U301
1
C863
C862
2
0.1U_0402_10V6K
+2.5VDDRH
C204
1U_0603_10V6K
+VDD_PLL1.8
C209
+VDD_MEMPLL1.8
C213
L20
1 2
CHB1608U301
+2.5VS
1
2
(20 mil)
1
2
(20 mil)
1
2
(20 mil)
1
2
+1.8VS
0.1U_0402_10V6K
1
C865
C866
2
0.1U_0402_10V6K
1
2
1
2
1
2
0.01U_0402_16V7K
1
C867
2
L15
1 2
CHB1608U301_0603
C205
0.1U_0402_10V6K
L17
1 2
CHB1608U301_0603
C210
0.1U_0402_10V6K
L19
1 2
CHB1608U301_0603
2.2U_0603_6.3V4Z
C931
1
C868
2
0.1U_0402_10V6K
+2.5VS
+1.8VS
0.1U_0402_10V6K
1
C869
2
+1.8VS
As close as possible to related pin
+VDDC1.5 +LVDDR
1
1
2
C968
0.1U_0402_10V6K
2
0.1U_0402_10V6K
C967
0.1U_0402_10V6K
1
C870
2
0.1U_0402_10V6K
C969
0.1U_0402_10V6K
1
C871
2
1
1
C970
0.1U_0402_10V6K
2
2
1
2
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-A
星期四 八月
LA-1811
0.7
of
20 66, 07, 2003
1
Page 21
5
U6E
M10-P/(M9+X)
(5/6)
A10
VSS
A16
D D
C C
+VGA_CORE
1
+
@47U_D2_6.3VM
B B
2
+2.5VS
C221
1
C223
22U_1206_10V4Z
2
1
2
VSS
A2
VSS
A22
VSS
A29
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB27
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE27
VSS
AG11
VSS
AG15
VSS
AG18
VSS
AG22
VSS
AG27
VSS
AG5
VSS
AG9
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
C1
VSS
C28
VSS
C3
VSS
C30
VSS
D10
VSS
D12
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D4
VSS
D6
VSS
D9
VSS
E4
VSS
F27
VSS
SA002160E00(0301021300)
C224
22U_1206_10V4Z
1
C225
0.1U_0402_10V6K
2
CORE POWER
1
C226
0.1U_0402_10V6K
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
4
H4
H8
H9
H12
H14
H18
H21
H23
H27
K1
K23
K24
K27
K30
K7
K8
L4
M30
M7
M8
N23
N24
N27
P4
R23
R24
R30
R7
R8
T1
T27
U23
U4
U8
V30
W23
W24
W27
W7
W8
Y4
G9
G12
G16
G18
G21
G24
C227
0.1U_0402_10V6K
1
C228
0.1U_0402_10V6K
2
POWER
INTERFACE
1
2
1
C229
0.01U_0402_16V7K
2
C230
0.01U_0402_16V7K
3
1
C231
0.01U_0402_16V7K
2
1
C222
+
100U_D2_10M_R45
2
+VGA_CORE
U6F
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
P18
VDDC
P19
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U17
VDDC
U18
VDDC
U19
VDDC
V12
VDDC
V13
VDDC
V14
VDDC
V17
VDDC
V18
VDDC
V19
VDDC
W12
VDDC
W13
VDDC
W14
VDDC
W17
VDDC
W18
VDDC
W19
VDDC
AB22
VDDC
AB9
VDDC
J10
VDDC
J12
VDDC
J14
VDDC
J15
VDDC
J16
VDDC
J17
VDDC
J19
VDDC
J21
VDDC
K22
VDDC
K9
VDDC
M22
VDDC
M9
VDDC
P22
VDDC
P9
VDDC
R22
VDDC
R9
VDDC
T22
VDDC
T9
VDDC
U22
VDDC
U9
VDDC
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
VDDC
SA002160E00(0301021300)
2
M10-P/(M9+X)
(6/6)
M10-P&M9+X
COMMON
CORE POWER
M10-P
ONLY
M9+X
ONLY
VDDC
VDDC
VDDC
VDDC
VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD15
AD13
AC17
AC15
AC13
T12
M15
W16
R19
R12
R13
T13
R14
T14
N15
P15
R15
T15
U15
V15
W15
H16
M16
N16
P16
R16
T16
U16
V16
R17
T17
R18
T18
T19
AA22
AA9
J11
J13
J18
J20
J22
J9
L22
L9
N22
N9
W22
W9
1
+VGA_CORE
+VGA_CORE_CI
1
2
+2.5VS
1
2
A A
C232
22U_1206_10V4Z
C243
22U_1206_10V4Z
1
2
1
2
C233
0.1U_0402_10V6K
C244
0.1U_0402_10V6K
1
2
1
2
C234
0.1U_0402_10V6K
C245
0.1U_0402_10V6K
1
2
1
2
C235
0.1U_0402_10V6K
C246
0.1U_0402_10V6K
1
2
1
2
C236
0.1U_0402_10V6K
C247
0.1U_0402_10V6K
1
2
1
2
C237
0.1U_0402_10V6K
C248
0.1U_0402_10V6K
1
2
1
2
1
C238
0.01U_0402_16V7K
2
1
C249
0.01U_0402_16V7K
2
C239
0.01U_0402_16V7K
C250
0.01U_0402_16V7K
+VGA_CORE_CI
(20 mil)
1
C240
2
10U_0805_6.3V6M
1
C241
0.1U_0402_10V6K
2
1
C242
0.1U_0402_10V6K
2
1 2
CHB1608U301
As close as ppossible to related pin
L22
480MIL
+VGA_CORE
(12A,480mils ,Via NO.=24)
JOPEN5
PAD-OPEN 4x4m
1 2
+1.2VS_VGA
As close as ppossible to related pin
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
ATI M10-P/M9+X POWER-B
星期四 八月
LA-1811
0.7
of
21 66, 07, 2003
1
Page 22
5
4
3
2
1
+2.5VS +2.5VS
1
C504
D D
10U_0805_10V3M
2
1
2
1
C505
0.1U_0402_10V6K
2
1
C507
C506
0.1U_0402_10V6K
2
10U_0805_10V3M
1
C508
0.1U_0402_10V6K
2
1
C509
0.1U_0402_10V6K
2
C510
10U_0805_10V3M
1
2
As close as ppossible to related pin
(25mil)
NMCLKA0
C628
NMCLKA0#
NMCSA1#
NMAA[0..13]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
NMRASA#<18>
NMCASA#<18>
NMWEA#<18>
NMCSA0#<18>
NMCKEA<18>
1
2
R625
56.2_0402_1%
R627
56.2_0402_1%
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NDQMA2
NDQMA3
NDQMA0
NDQMA1
NDQSA2
NDQSA3
NDQSA0
NDQSA1
VREF_1
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
K4D263238A-GC
U28
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
D10
D11
VSSQ
F10
VSSQE6VSSQE9VSSQF5VSSQ
G10
VSSQG5VSSQ
H10
VSSQH5VSSQ
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
NMDA23
B7
NMDA22
C6
NMDA21
B6
NMDA20 NMAA3
B5
NMDA19
C2
NMDA18
D3
NMDA17
D2
NMDA16
E2
NMDA31
K13
NMDA30
K12
NMDA29
J13
NMDA28
J12
NMDA27
G13
NMDA26
G12
NMDA25
F13
NMDA24
F12
NMDA7
F3
NMDA6
F2
NMDA5
G3
NMDA4
G2
NMDA3
J3
NMDA2
J2
NMDA1
K2
NMDA0
K3
NMDA15
E13
NMDA14
D13
NMDA13
D12
NMDA12
C13
NMDA11
B10
NMDA10
B9
NMDA9
C9
NMDA8
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS+2.5VS
12
R489
1K_0402_1%
12
R491
1K_0402_1%
NMCLKA1<18>
NMCLKA1#<18>
1
C517
0.1U_0402_10V6K
2
NMCLKA1
10P_0402_50V8K
NMCLKA1#
C629
NMCSA1#
NMAA[0..13]<18>
NMDA[0..63]<18>
NDQMA[0..7]<18>
NDQSA[0..7]<18>
C C
12
R488
1K_0402_1%
12
R490
1K_0402_1%
B B
1
2
NMCLKA0<18>
NMCLKA0#<18>
NMCSA1#<18>
C516
0.1U_0402_10V6K
10P_0402_50V8K
VGA DDR FOR CHANNEL
A
1
2
1
C511
0.1U_0402_10V6K
2
As close as ppossible to related pin
(25mil)
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
R626
56.2_0402_1%
1
R628
56.2_0402_1%
2
C513
C512
0.1U_0402_10V6K
10U_0805_10V3M
NMAA0
NMAA1
NMAA2
NMAA4
NMAA5
NMAA6
NMAA7
N10
NMAA8
N11
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NDQMA6
NDQMA7
H12
NDQMA4
NDQMA5
B12
NDQSA6
NDQSA7
H13
NDQSA4
NDQSA5
B13
VREF_2
N13
M13
M10
N12
M11
M12
C11
H11
L12
L13
E10
L10
K4D263238A-GC
1
2
U29
N5
N6
M6
N7
N8
M9
N9
M8
L6
M7
N4
M5
B3
H3
B2
H2
L9
M2
L2
L3
N2
C4
H4
M3
M4
N3
E7
E8
K6
K7
K8
K9
L5
E5
1
2
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#
CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
C514
0.1U_0402_10V6K
D10
D11
VSSQ
VSSQE6VSSQE9VSSQF5VSSQ
1
C515
0.1U_0402_10V6K
2
F10
G10
VSSQG5VSSQ
VSSQH5VSSQ
H10
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
NMDA55
B7
NMDA54
C6
NMDA53
B6
NMDA52
B5
NMDA51
C2
NMDA50
D3
NMDA49
D2
NMDA48
E2
NMDA63
K13
NMDA62
K12
NMDA61
J13
NMDA60
J12
NMDA59
G13
NMDA58
G12
NMDA57
F13
NMDA56
F12
NMDA39
F3
NMDA38
F2
NMDA37
G3
NMDA36
G2
NMDA35
J3
NMDA34
J2
NMDA33
K2
NMDA32
K3
NMDA47
E13
NMDA46
D13
NMDA45
D12
NMDA44
C13
NMDA43
B10
NMDA42
B9
NMDA41
C9
NMDA40
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS+2.5VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA DDR FOR CHANNEL A
星期四 八月
LA-1811
0.7
of
22 66, 07, 2003
1
Page 23
5
4
3
2
1
+2.5VS
1
2
D D
1
C518
22U_1206_10V4Z
2
1
C519
0.1U_0402_10V6K
2
1
C520
0.1U_0402_10V6K
2
1
C521
0.01U_0402_16V7K
2
1
C522
0.01U_0402_16V7K
2
1
C523
22U_1206_10V4Z
2
1
C524
0.1U_0402_10V6K
2
1
C525
0.1U_0402_10V6K
2
1
C526
0.01U_0402_16V7K
2
C527
0.01U_0402_16V7K
As close as ppossible to related pin
NMAB[0..13]<19>
NMDB[0..63]<19>
NDQMB[0..7]<19>
NDQSB[0..7]<19>
C C
+2.5VS
R495
1K_0603_1%
1 2
(25mil)
1
R496
1K_0603_1%
1 2
B B
C538
0.1U_0402_10V6K
2
NMCLKB0<19> NMCLKB1<19>
10P_0402_50V8K
NMCLKB0#<19>
NMCSB1#<19>
NMAB[0..13]
NMDB[0..63]
NDQMB[0..7]
NDQSB[0..7]
NMRASB#<19>
NMCASB#<19>
NMWEB#<19>
NMCSB0#<19>
NMCKEB<19>
R629
56.2_0402_1%
R631
1
C630
56.2_0402_1%
2
NMCLKB0# NMCLKB1#
NMCSB1# NMCSB1#
U30
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB0
NDQMB2
NDQMB1
NDQMB3
NDQSB0
NDQSB2
NDQSB1
NDQSB3
VREF_3
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
K4D263238A-GC
B11
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
D10
D11
VSSQ
F10
VSSQE6VSSQE9VSSQF5VSSQ
G10
VSSQG5VSSQ
H10
VSSQH5VSSQ
J10
VSSQJ5VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
K10
VSSQK5VSSQ
+2.5VS
1
C528
22U_1206_10V4Z
2
1
C529
0.1U_0402_10V6K
2
1
C530
0.1U_0402_10V6K
2
VGA DDR FOR CHANNEL
B
1
C531
0.01U_0402_16V7K
2
1
C532
0.01U_0402_16V7K
2
1
C533
22U_1206_10V4Z
2
1
2
1
C534
0.1U_0402_10V6K
2
C535
0.1U_0402_10V6K
1
C536
0.01U_0402_16V7K
2
1
C537
0.01U_0402_16V7K
2
As close as ppossible to related pin
U31
B11
D10
D11
F10
G10
H10
J10
K10
VSSQB4VSSQ
VSSQD4VSSQD5VSSQD6VSSQD9VSSQ
VSSQ
VSSQE6VSSQE9VSSQF5VSSQ
VSSQG5VSSQ
VSSQH5VSSQ
VSSQJ5VSSQ
NMDB7
B7
NMDB6
C6
NMDB5
B6
NMDB4
B5
NMDB3
C2
NMDB2
D3
NMDB1
D2
NMDB0
E2
NMDB23
K13
NMDB22NMAB9
K12
NMDB21
J13
NMDB20
J12
NMDB19
G13
NMDB18
G12
NMDB17
F13
NMDB16
F12
NMDB15
F3
NMDB14
F2
NMDB13
G3
NMDB12
G2
NMDB11
J3
NMDB10
J2
NMDB9
K2
NMDB8
K3
NMDB31
E13
NMDB30
D13
NMDB29
D12
NMDB28
C13
NMDB27
B10
B9
NMDB25
C9
NMDB24
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS
+2.5VS
NMCLKB1#<19>
R494
1K_0603_1%
1 2
R497
1K_0603_1%
1 2
NMCLKB1NMCLKB0
10P_0402_50V8K
(25mil)
1
C539
0.1U_0402_10V6K
2
R630
R632
1
C631
2
56.2_0402_1%
56.2_0402_1%
NMAB0
NMAB1
NMAB2
NMAB3
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB5
NDQMB7
NDQMB4
NDQMB6
NDQSB5
NDQSB7
NDQSB4
NDQSB6
VREF_4
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
K4D263238A-GC
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
VSS THF6VSS THF7VSS THF8VSS THF9VSS THG6VSS THG7VSS THG8VSS THG9VSS THH6VSS THH7VSS THH8VSS THH9VSS THJ6VSS THJ7VSS THJ8VSS TH
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
J9
VSSQK5VSSQ
NMDB47
B7
NMDB46
C6
NMDB45
B6
NMDB44
B5
NMDB43NMAB4
C2
NMDB42
D3
NMDB41
D2
NMDB40
E2
NMDB63
K13
NMDB62
K12
NMDB61
J13
NMDB60
J12
NMDB59
G13
NMDB58
G12
NMDB57
F13
NMDB56
F12
NMDB39
F3
NMDB38
F2
NMDB37
G3
NMDB36
G2
NMDB35
J3
NMDB34
J2
NMDB33
K2
NMDB32
K3
NMDB55
E13
NMDB54
D13
NMDB53
D12
NMDB52
C13
NMDB51
B10
NMDB50NMDB26
B9
NMDB49
C9
NMDB48
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS
A A
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA DDR FOR CHANNEL B
星期四 八月
LA-1811
0.7
of
23 66, 07, 2003
1
Page 24
A
B
C
D
E
F
G
H
CLK_BCLK
CLK_BCLK#
+3VS
1 1
C127 10P_0402_50V8K
C130 10P_0402_50V8K
SMB_CK_CLK2<14,15,27>
SMB_CK_DAT2<14,15,27>
+3VS
R1056 10K_0402_5%
1 2
R1111 10K_0402_5%
1 2
R209 33_0402_1%
2 2
CLK_LPC_48M<39>
CLK_SB_48M<27>
CLK_SD_48M<31>
REFCLK1_NB<11>
CLK_14M_CODEC<37>
CLK_SB_14M<27>
CLK_14M_APIC<26>
1 2
R962 10K_0402_5%
1 2
R206 33_0402_1%
1 2
R207 33_0402_1%
1 2
R996 68_0402_5%
1 2
R215 33_0402_1%
1 2
R997 33_0402_1%
1 2
R1068 @33_0402_1%
1 2
1 2
1 2
VTT_PWRGD<27,46,48>
XTALIN_CLK
12
Y2
14.318MHZ
XTALOUT_CLK
L11
1 2
HB-1M2012-121JT03_0805
12
R963
@1M_0402_5%
SMB_CK_CLK2
SMB_CK_DAT2
24/48#
PCI33/66#
CLK_48M
CLK_SD
FS2
FS1
FS0
CLK_IREF
R218
475_0402_1%
1 2
35
34
10
45
12
26
11
27
28
38
U5
6
XIN
7
XOUT
SCLK
SDATA
VTTPWRGD/PD#
CPU_STP#
PCI_STOP#
24/48#SEL
PCI33/66#SEL
48MHz_1
48MHz_0
4
FS2/REF2
3
FS1/REF1
2
FS0/REF0
IREF
+3V_CLK
42
8
Width=40 mils
10U_0805_6.3V6M
29
19
30
48
VDDSD
VDDPCI
VDD48M
VDDCPU
VDDAGP
GNDREF
GNDXTAL
GNDPCI
GNDPCI
GND48M
5
18
24
25
0.1U_0402_10V6K
1
C118
C119
2
13
9
1
VDDPCI
VDDREF
VDDXTAL
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDSD
GNDCPU
GNDAGP
ICS951402AGT_TSSOP48
46
41
33
1
2
VDDA
VSSA
C120
0.1U_0402_10V6K
36
37
40
39
44
43
47
32
31
14
15
16
17
20
21
22
23
0.1U_0402_10V6K
1
C121
2
+3V_VDD
C128
0.1U_0402_10V6K
VSSA
CLK_BCLK
CLK_BCLK#
CLK_NB
CLK_NB#
MEM_66M
AGP_66M
AGP_EXT_66M
FS3
FS4
R193 @0_0402_5%
R194 @0_0402_5%
0.1U_0402_10V6K
1
1
1
C122
2
2
0.1U_0402_10V6K
1
1
2
2
R195 33_0402_1%
1 2
R200 33_0402_1%
1 2
R201 33_0402_1%
1 2
R204 33_0402_1%
1 2
R205 33_0402_1%
1 2
R208 33_0402_1%
1 2
R210 M9_M10@33_0402_1%
1 2
R213 33_0402_1%
1 2
C124
C123
2
0.1U_0402_10V6K
L12
1 2
CHB2012U121_0805
C129
10U_0805_6.3V6M
R196 49.9_0402_1%
R197 49.9_0402_1%
R202 49.9_0402_1%
R203 49.9_0402_1%
CK_ITP <5>
CK_ITP# <5>
0.1U_0402_10V6K
1
C125
2
+3VS
CK_BCLK
1 2
1 2
CK_BCLK#
1 2
1 2
1
1
C126
0.1U_0402_10V6K
2
2
CK_BCLK <4>
CK_BCLK# <4>
CLK_NB_BCLK <11>
CLK_NB_BCLK# <11>
CLK_MEM_66M <11>
CLK_AGP_66M <11>
CLK_AGP_EXT_66M <17>
CLK_ALINK_SB <26>
3 3
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
0 0 0 1 0
0 0 0 0 1
0 0 0 0 0
Note: 0 = PULL LOW
4 4
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
133
*
Spreaf OFF OR
Center spread +/-0.3%
BSEL1<5,13>
BSEL0<5,13>
133
100 100
10K_0402_5%
D83 RB751V_SOD323
D84 RB751V_SOD323
21
21
R219
+3V_CLK
12
12
R998
10K_0402_5%
FS1
FS0
FS2
FS3
FS4
PCI33/66#
12
R999
4.7K_0402_5%
12
R224
4.7K_0402_5%
12
R220
@10K_0402_5%
12
R225
10K_0402_5%
12
R221
@10K_0402_5%
12
R226
10K_0402_5%
12
R222
@10K_0402_5%
12
R227
10K_0402_5%
+3V_CLK
12
12
R223
10K_0402_5%
R228
@10K_0402_5%
A-LINK FREQ
PCI33/66# = HIGH
PCI33/66# = LOW 33MHZ
A
66MHZ
B
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C
D
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-1811
G
星期四 八月
0.7
of
24 66, 07, 2003
H
Page 25
5
LCD CONN
JP27
1
TXA2+<17>
TXA2-<17>
TXA1+<17>
TXA1-<17>
TXB2+<17>
TXB2-<17>
D D
C C
TXA0+<17>
TXA0-<17>
TXACLK+<17>
TXACLK-<17>
TXB1+<17>
TXB1-<17>
TXA2+_NB<11>
TXA2-_NB<11>
TXA1+_NB<11>
TXA1-_NB<11>
TXB2+_NB<11>
TXB2-_NB<11>
TXA0+_NB<11>
TXA0-_NB<11>
TXACLK+_NB<11>
TXACLK-_NB<11>
TXB1+_NB<11>
TXB1-_NB<11>
TXA2+
TXA2-
TXA1+
TXA1-
TXB2+
TXB2-
TXA0+
TXA0-
TXACLK+
TXACLK-
TXB1+
TXB1-
+3VS
TXA2+_NB
TXA2-_NB
TXA1+_NB
TXA1-_NB
TXB2+_NB
TXB2-_NB
TXA0+_NB
TXA0-_NB
TXACLK+_NB
TXACLK-_NB
TXB1+_NB
TXB1-_NB
+3VS
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
M9-M10@JST BM40B-SRDS
JP28
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
NAGP@JST BM40B-SRDS
LCDVDD_A
2
2
4
4
6
6
8
8
TXB0+
10
10
TXB0-
12
12
14
14
TXBCLK+
16
16
TXBCLK-
18
18
20
20
DISPOFF#
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
LCDVDD_A
2
2
4
4
6
6
8
8
TXB0+_NB
10
10
TXB0-_NB
12
12
14
14
TXBCLK+_NB
16
16
TXBCLK-_NB
18
18
20
20
DISPOFF#
22
22
INVT_PWM
24
24
DAC_BRIG
26
26
28
28
DDC_CLK
30
30
DDC_DAT
32
32
34
34
36
36
38
38
40
40
AT LEAST 60 MIL
TXB0+ <17>
TXB0- <17>
TXBCLK+ <17>
TXBCLK- <17>
INVT_PWM <46>
DAC_BRIG <46>
DDC_CLK <10,17>
DDC_DAT <10,17>
INVPWR_B+
TFT LCD CONN.
AT LEAST 60 MIL
TXB0+_NB <11>
TXB0-_NB <11>
TXBCLK+_NB <11>
TXBCLK-_NB <11>
INVPWR_B+
TFT LCD CONN.
4
1
C618
2
10U_0805_10V3M
1000P_0402_50V8J
1
C619
2
DDC_CLK
DDC_DAT
L41
1 2
KC FBM-L11-201209-221LMAT_0805
1
C620
0.01U_0402_50V7K
2
+3VS
R1007
2.2K_0402_5%
1 2
1 2
R1008
2.2K_0402_5%
3
LCDVDD
0.1U_0402_10V6K
2
+3VS
12
R174
4.7K_0402_5%
R180
12
2
G
LCDVDD
12
13
D
S
2
DISPOFF#
13
D
Q8
M9@2N7002 1N_SOT23
S
+12VALW
R182
100K_0402_5%
2
G
13
22K
22K
2
G
Q11
2N7002_SOT23
Q12
DTC124EK_SOT23
B+
+12VALW
L2
1 2
KC FBM-L11-201209-221LMAT_0805
R175
100K_0402_5%
R181
13
D
150K_0402_5%
S
SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V
INVPWR_B+
1
C89
0.047U_0402_16V4Z
2
0.1U_0402_10V6K
BKOFF#<46>
M10_BKOFF#<17>
1
C87
2
D16 RB751V_SOD323
D41 M10@RB751V_SOD323
+12VALW+5VS
1
C88
0.1U_0402_10V6K
2
21
21
R1013
M9@10K_5%
2N7002_SOT23
ENAVDD
2.2K_0402_5%
ENABLT#
12
1K_0402_1%
Q10
R1115
ENABLT#<10,17>
+3VS
ENAVDD<10,17,46>
1
+3VS
1
C86
4.7U_0805_10V4Z
2
13
D
2
G
Q9
S
SI2302DS 1N_SOT23
LCDVDD
1
1
C90
C91
4.7U_0805_10V4Z
2
2
SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V
+3VS
D21
DAN217_SOT23
1
D22
DAN217_SOT23
1
D23
DAN217_SOT23
CRT CONNECTOR
3VDDCDA<11,17>
3VDDCCL<11,17>
B B
M_SEN#<46>
CRT_R<11,17>
CRT_G<11,17>
CRT_B<11,17>
CRT_VCC
135
CRT_HSYNC<11,17>
A A
CRT_VSYNC<11,17>
CRT_HSYNC
CRT_VSYNC
5
2 4
U57 74AHCT1G125GW
135
2 4
74AHCT1G125GW
U58
M_SEN#
CRT_R
CRT_G
CRT_B
R1150
1 2
1K_0402
4
R1153 20_0402_5%
1 2
1 2
R1154 20_0402_5%
75_0402_5%
L9
1 2
FBM-L10-160808-300LM-T
L10
1 2
FBM-L10-160808-300LM-T
PIR BOM 92.07.30
R185
1 2
10P_0402_50V8K
+5VS
DAN217_SOT23
3VDDCDA
3VDDCCL
L3 FCM2012C-800_0805
1 2
10P_0402_50V8K
1
C100
2
D42
1
R186
2
1 2
75_0402_5%
2
3
1
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
L5 FCM2012C-800_0805
1 2
L6 FCM2012C-800_0805
1 2
1
C101
DAN217_SOT23
R187
75_0402_5%
2
1 2
D43
C102
10P_0402_50V8K
2
3
1
2
1
C103
22P_0402_25V8K
2
3
1
C104
2
22P_0402_25V8K
2
3
2
CRTL_R
CRTL_G
CRTL_B
1
C105
2
22P_0402_25V8K
CRT_HSYNCRFL
CRT_VSYNCRFL
2
+5VS CRT_VCC
R_CRT_VCC
C108
D17
2 1
RB411D_SOT23
4.7K_0402_5%
220P_0402_25V8K
1
1
C109
2
2
10P_0402_50V8K
1
3
10P_0402_50V8K
PIR BOM 92.07.30
Title
Size Document Number Rev
Custom
Date: Sheet
F1
21
1
FUSE_1A
C97
0.1U_0402_10V6K
R1117
1
2
220P_0402_25V8K
R1118
4.7K_0402_5%
C107
1
C116
2
220P_0402_25V8K
2
C117
1
2
CRT_VCC
D
1 3
JP6
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
Q13
SUYIN_7849S-15G2T-HC
S
2N7002 1N_SOT23
G
2
Q14
D
S
1 3
2N7002 1N_SOT23
R191
G
2
4.7K_0402_5%
3VDDCDA
Compal Electronics, Inc.
LCD,CRT,TV-OUT & Inverter BD CONN.
星期四 八月
LA-1811
25 66, 07, 2003
1
3VDDCCL
R192
4.7K_0402_5%
+3VS
0.7
of
Page 26
5
A_AD[0..31]<10,13>
A_CBE#[0..3]<10,13>
+VCC_CORE
D D
Q5 MMBT3904_SOT23
H_FERR#<5>
H_RESET#<5,8>
+3VS
CPUCLK_STP#<5,11,56>
C C
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
B B
H_STPCLK#
H_IGNNE#
H_A20M#
H_INIT#
H_INTR
H_NMI
3 1
+VCC_CORE
Q98 @MMBT3904_SOT23
3 1
R946 8.2K_0402_5%
12
R149 200_0402_5%
1 2
R150 200_0402_5%
1 2
R151 200_0402_5%
1 2
R152 200_0402_5%
1 2
R153 200_0402_5%
1 2
R154 200_0402_5%
1 2
R156 200_0402_5%
1 2
R158 200_0402_5%
1 2
C956 180P_0603_50V8J
12
C617 180P_0603_50V8J
12
C78 180P_0603_50V8J
12
C79 180P_0603_50V8J
12
PLACE CLOSE TO CPU SOCKET
PIR LAYOUT 92.07.30
A A
12P_0402_50V8K
5
A_AD[0..31]
A_CBE#[0..3]
12
R132
470_0402_5%
2
12
R1000
470_0402_5%
2
CLK_14M_APIC
R1143
@10_0402_5%
C973
@15P_0402_50V8J
+VCC_CORE
DPRSLPVR<56>
CLK_14M_APIC<24>
RTCX2
32.768KHZ_12.5P_MC-306
R171
1 2
20M_0603_5%
1
C81
12P_0402_50V8K
2
+3VS
Y1
R131
330_0402_5%
H_CPUFERR#
CPURSTIN#
A_SERR#
SBCLK_STP#
PCI_PIRQB#<31>
R1001
47K_0402_5%
1 2
R1002 47K_0402_5%
RTCX1
12
43
12
1
C82
2
R125 8.2K_0402_5%
PULL DOWN FOR S3
CLK_ALINK_SB
12
R134
@10_0402_5%
C77
@15P_0402_50V8J
+3VS
12
R40
1K_0402_5%
+3VS
12
R921
4.7K_0402_5%
1 2
R1064 10K_0402_5%
R1065 10K_0402_5%
R1066 @300_0402_1%
R1067 1K_0402_1%
0.1U_0402_10V6K
R172
20M_0603_5%
4
CLK_ALINK_SB<24>
A_STROBE#<10>
A_DEVSEL#<10>
A_ACAT#<10>
A_END#<10>
A_PAR<10,13>
A_OFF#<10>
A_SBREQ#<10>
A_SBGNT#<10>
PCI_PIRQA#<10,17,31,35,36>
PCI_PIRQC#<36,43>
PCI_PIRQD#<34,36>
R169
330_0402_5%
H_PWRGOOD<5>
H_INTR<5>
H_NMI<5>
H_INIT#<5>
H_SMI#<5>
H_CPUSLP#<5>
H_IGNNE#<5>
H_A20M#<5>
H_STPCLK#<5>
1 2
1 2
1 2
1 2
C872
R966
10K_0402_5%
NBRST# NB_RST#
SN74LVC14APWLE_TSSOP14
4
CLK_ALINK_SB
NBRST#
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
SBCLK_STP#
PCICLK_STP#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
+3VS
RTCX1
RTCX2
CPURSTIN#
H_A20M#
H_CPUFERR#
GPIO0
SB_APIC_D0
SB_APIC_D1
+3VALW
1
2
PCIRST#
3
12
SN74LVC14APWLE_TSSOP14
+3VALW +3VALW
14
U45E
P
11
G
7
B22
R22
H22
P23
L23
N23
N22
M23
M22
K22
M21
M20
L21
K21
L20
N21
K23
K20
F23
G21
F20
H21
F22
F21
G20
E21
E20
D23
D22
E22
D20
C23
D21
C22
L22
J23
G22
E23
H20
J21
G23
H23
J20
J22
P22
B21
B20
N20
R23
C20
P20
B23
P21
AC12
AC11
B18
E4
B17
B16
C17
C16
F19
D17
D18
E19
E16
E17
E18
C19
C18
B19
14
U45B
P
O4I
G
7
14
13
O10I
7
U3A
PCICLKF
A_RST#
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
CPU_STP#/DPSLP#
PCI_STP#
A_INTA#
INTB#
INTC#
INTD#
X1
X2
CPURSTIN#
CPU_PWRGD
INTR/LINT0
NMI/LINT1
INIT
SMI#
SLP#
IGNNE#
A20M#
FERR#
STPCLK#
SSMUXSEL/GPIO0
DPRSLPVR
APIC_D0
APIC_D1
APIC_CLK
South bridge SB200
9
U45F
P
O12I
G
SN74LVC14APWLE_TSSOP14
A-LINK INTERFACE
14
U45D
P
PCI_RST#
O8I
G
SN74LVC14APWLE_TSSOP14
7
3
Layout note:
Trace length of PCI_CLK_R + PCI_CLK_FB should
be less than 200 mils.
PCI_1394
SB200 SB
Part 1 of 3
PCI CLKS
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24/RTC_AD7
AD25/RTC_AD6
AD26/RTC_AD5
AD27/RTC_AD4
AD28/RTC_AD3
AD29/RTC_AD2
AD30/RTC_AD1
AD31/RTC_AD0
CBE#0/ROMA10
CBE#1/ROMA1
CBE#2/ROMWE#
PCI INTERFACE
CBE#3/RTC_RD#
DEVSEL#/ROMA0
TRDY#/ROMOE#
REQ#3/PDMAREQ0#
REQ#4/PLLBP33/PDMAREQ1#
XTAL
CPU
RTC
GNT#3/PDMAGNT0#
GNT#4/PLLBP50/PDMAGNT1#
GPIO1/ROMCS#
LPC
USBOC5#/GPM1
RTC_ALE/USBOC4#/GPIO3
RTC_WR#/RTC_CLKOUT
RTC_CS#/USBOC3#/GPIO2
PCI_RST# <11,30,31,34,35,36,43,46>
NB_RST# <8,17,39>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK_FB
PCIRST#
AD8/ROMA9
AD9/ROMA8
FRAME#
IRDY#
PAR
STOP#
PERR#
SERR#
REQ#0
REQ#1
REQ#2
GNT#0
GNT#1
GNT#2
CLKRUN#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#0
LDRQ#1
SERIRQ
VBAT
RTC_GND
B15
D16
A14
A15
A16
A17
D15
A18
A19
C15
B1
C1
A1
D2
B2
C2
A2
D3
C3
A3
D4
B4
C4
A4
D5
B5
C8
D8
B8
A8
C9
D9
B9
A9
C10
B10
D11
A10
C11
B11
D12
A11
B3
C5
A7
D10
B7
A6
C7
D7
A5
B6
C6
D6
B12
C12
D13
A12
C13
A13
B13
C14
D14
B14
A20
AB5
Y14
AA14
AB14
AA13
AB13
AC14
Y13
AC13
AA2
AB7
AB8
AC8
AC10
AB11
R122 33_0402_5%
PCI_LAN
R123 33_0402_5%
PCI_PCM
R124 33_0402_5%
PCI_MINI
R126 33_0402_5%
PCI_EC
R127 33_0402_5%
PCI_SIO
R128 33_0402_5%
PCI_USB20
R1021 33_0402_5%
PCI_CLK_R
R130 33_0402_5%
PCI_CLK_FB
PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#
GPIO1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
SIRQ
OVCUR#5
OVCUR#4
GPIO2
+RTCVCC
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI_AD[0..31]
PIR BOM 92.06.23
PCI_CBE#[0..3]
PCI_FRAME# <31,34,35,36,43>
PCI_DEVSEL# <31,34,35,36,43>
PCI_IRDY# <31,34,35,36,43>
PCI_TRDY# <31,34,35,36,43>
PCI_PAR <31,34,35,36,43>
PCI_STOP# <31,34,35,36,43>
PCI_PERR# <31,34,35,36,43>
PCI_SERR# <31,34,35,36,43>
PCI_REQ#0 <35>
PCI_REQ#1 <34>
PCI_REQ#2 <31>
PCI_REQ#3 <36,43>
PCI_REQ#4 <36,43>
PCI_GNT#0 <35>
PCI_GNT#1 <34>
PCI_GNT#2 <31>
PCI_GNT#3 <36,43>
PCI_GNT#4 <36,43>
PCI_CLKRUN# <31,34,35,36,43>
LPC_AD0 <39,46>
LPC_AD1 <39,46>
LPC_AD2 <39,46>
LPC_AD3 <39,46>
LPC_FRAME# <39,46>
LPC_DRQ#1 <39>
SIRQ <31,39,46>
2
C76 @22P_0402_50V8J
1 2
PCI_AD[0..31] <29,31,34,35,36,43>
PCI_CBE#[0..3] <31,34,35,36,43>
2
G
R1151
10K_0402_5%
1 2
+RTCVCC
W=20mils
JOPEN1
No short
2
1 2
1
2
CLK_PCI_1394 <35>
CLK_PCI_LAN <34>
CLK_PCI_PCM <31>
CLK_PCI_MINI <43>
CLK_PCI_EC <46>
CLK_PCI_SIO <39>
CLK_PCI_USB20 <36>
C80
1U_0603_10V6K
13
D
Q118
@2N7002_SOT23
S
R168
1K_0402_5%
1
PCI_IRDY#
4 5
PCI_TRDY#
3 6
PCI_DEVSEL#
2 7
PCI_STOP#
1 8
8.2K _8P4R_0804_5%
PCI_PAR
4 5
PCI_PERR#
3 6
PCI_SERR#
2 7
PCI_FRAME#
1 8
8.2K _8P4R_0804_5%
PCI_PIRQA#
4 5
PCI_PIRQB#
3 6
PCI_PIRQC#
2 7
PCI_PIRQD#
1 8
8.2K _8P4R_0804_5%
PCI_REQ#0
4 5
PCI_REQ#1
3 6
PCI_REQ#2
2 7
PCI_REQ#3
1 8
8.2K _8P4R_0804_5%
PCI_GNT#0
4 5
PCI_GNT#1
3 6
PCI_GNT#2
2 7
PCI_GNT#3
1 8
8.2K _8P4R_0804_5%
PCI_REQ#4
PCI_GNT#4
LPC_AD0
4 5
LPC_AD1
3 6
LPC_AD2
2 7
LPC_AD3
1 8
SIRQ
LPC_FRAME#
LPC_DRQ#0
R145
@4.7K_0402_5%
Title
Size Document Number Rev
Date: Sheet
LPC_DRQ#1
PCI_CLKRUN#
12
GPIO0
H_PROCHOT# <5,51>
OVCUR#4
OVCUR#5
GPIO2
D93
RB751V_SOD323
2 1
W=15mils
CHGRTC
Compal Electronics, Inc.
SB200M(1/4)- PCI/CPU/LPC
星期四 八月
LA-1811
RP138
1 8
2 7
3 6
4 5
R146 4.7K_0402_5%
R1059 10K_0402_5%
BATT1.1
W=20mils
12
R1155 10K_0402_5%
12
R1157 10K_0402_5%
12
1 2
R1156 10K_0402_5%
12
+
1 2
1
+3VS
RP14
RP15
RP16
RP17
RP18
R137
8.2K_0402_5%
R138
8.2K_0402_5%
RP21
100K_1206_8P4R_5%
10K_0804_8P4R_5%
+3V
BATT1
-
RTCBATT
of
26 66, 07, 2003
0.7
Page 27
5
Note: Place close
L
to U3 (ATI SB)
For ATI USB2.0 only .
CLK_SB_48M
12
R64
D D
C C
B B
A A
@10_0402_5%
C73
@15P_0402_50V8J
AC97_BITCLK
12
R71
@10_0402_5%
C74
@15P_0402_50V8J
CLK_SB_14M
12
R92
@10_0402_5%
C75
@15P_0402_50V8J
RP111
1 8
2 7
3 6
4 5
RP112
RP113
IDERST_HD#<30>
IDERST_CD#<30>
+5VS
R934 1K_0603_5%
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
15K_1206_8P4R_5%
1 8
2 7
3 6
4 5
15K_1206_8P4R_5%
R120 10K_0402_5%
+3VS
R121 10K_0402_5%
+3VS
1 2
5
R112 100K_0402_5%
R951 10K_0402_5%
AGP_STP#<10,17>
CPU_GHI#<5>
1 2
IDERST_HD#
1 2
IDERST_CD#
D
1 3
Q89 2N7002 1N_SOT23
2
USB20P4+
USB20P4USB20P5USB20P5+
USB20P3USB20P3+
USB20P2USB20P2+
USB20P1+
USB20P1USB20P0+
USB20P0-
2 1
D13 RB751V_SOD323
2 1
D14 RB751V_SOD323
G
S
CLK_SB_48M<24>
OVCUR#0<44>
USB20P5+<44>
USB20P5-<44>
USB20P4+<41>
USB20P4-<41>
USB20P3+<44>
USB20P3-<44>
USB20P2+<44>
USB20P2-<44>
USB20P1+<44>
USB20P1-<44>
USB20P0+<44>
USB20P0-<44>
12
AGP_STP#
D11 RB751V_SOD323
2 1
D77
2 1
RB751V_SOD323
IDERSTHD#
IDERSTCD#
AGP_BUSY#AGP_BUSY#_R
R63
12.4K_0603_1%
PIR BOM & LAYOUT 92.07.30
MII_TXD3<29>
MII_TXD2<29>
MII_TXD1<29>
MII_TXD0<29>
MII_TXEN<29>
R947 10K_0402_5%
R950 10K_0402_5%
SB_EEDO<29>
SB_EECLK<29>
EC_RSMRST#<46>
CLK_SB_14M<24>
R948 10K_0402_5%
+3V
EC_FLASH#<47>
32KHZ_S5_OUT<29>
OVCUR#1<44>
SB_SPKR<37>
@10K_0402_5%
AGP_BUSY# <10,17>
R952
4
CLK_SB_48M
USB_RCOMP
12
12
12
12
R1003
33_0402_5%
1 2
4
USB20P5+
USB20P5-
USB20P4+
USB20P4-
USB20P3+
USB20P3-
USB20P2+
USB20P2-
USB20P1+
USB20P1-
USB20P0+
USB20P0-
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
SB_EEDO
SB_EECLK
EC_RSMRST#
CLK_SB_14M
EC_FLASH#
OVCUR#1
32KHZ_S5_OUT
OVCUR#1
SB_SPKR
AGP_STP#_R
AGP_BUSY#_R
GHI
VGATE
IDERSTHD#
IDERSTCD#
VTT_PWRGD <24,46,48>
U3B
P3
USBCLK/CLK48
R1
USB_RCOMP
P1
USB_VREFOUT
N4
USB_ATEST1
N3
USB_ATEST0
P4
USBOC0#/GPM7
M2
USB_HSDP5+
M1
USB_FLDP5+
N2
USB_HSDM5-
N1
USB_FLDM5-
L4
USB_HSDP4+
L3
USB_FLDP4+
M4
USB_HSDM4-
M3
USB_FLDM4-
K2
USB_HSDP3+
K1
USB_FLDP3+
L2
USB_HSDM3-
L1
USB_FLDM3-
H2
USB_HSDP2+
H1
USB_FLDP2+
J2
USB_HSDM2-
J1
USB_FLDM2-
G3
USB_HSDP1+
J3
USB_FLDP1+
H3
USB_HSDM1-
K3
USB_FLDM1-
F1
USB_HSDP0+
F2
USB_FLDP0+
G1
USB_HSDM0-
G2
USB_FLDM0-
R5
MCOL
W1
MCRS
V4
MDCK
V2
MDIO
T1
RX_CLK
T3
RXD3
U2
RXD2
T5
RXD1
W4
RXD0
T2
RX_DV
U1
RX_ERR
T4
TX_CLK
U4
TXD3
V1
TXD2
U3
TXD1
V3
TXD0
W2
TX_EN
W3
PHY_PD
U5
PHY_RST#
Y7
CLK_25M
P2
EE_CS
R3
EE_DI
R2
EE_DO
R4
EE_CK
AB9
RSMRST#
A23
OSC_IN
W6
SIO_CLK
AB2
BLINK/GPM0
AA3
FANOUT1/USBOC2#/GPM2
W11
32KHZ_IN/GPM3
AB1
USBOC1#/GPM4
Y4
SPEAKER/GPM5
AA1
FANOUT0/GPM6
AC1
GPIO_X0/AGP_STP#
AC6
GPIO_X1/AGP_BUSY#
AC2
GPIO_X2/GHI#
AC3
GPIO_X3/VGATE
AC4
GPIO_X4
AC5
GPIO_X5
South bridge SB200
SB200 SB
Part 2 of 3
ACPI / WAKE UP EVENTS
USB INTERFACE
PRIMARY ATA 66/100
ETHERNET MIIEEPROMCLK / RST
SECONDARY ATA 66/100
GPIOGPIO_XTRA
3
SB_EC_THERM#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST1
TEST0
PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#
SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT
3
AB4
AC9
AC7
AA11
AB10
AA10
Y11
C21
Y10
AA5
AA6
Y5
AA4
AB3
Y6
W5
Y8
AA7
AB6
AA12
W12
Y12
AB12
AA8
AB17
AC16
AB15
AB16
AC15
Y16
AA17
AA16
AC17
Y15
AA15
AC18
AA18
AC19
AA19
AC20
AA20
AC21
AB21
AA21
Y20
AB20
Y19
AB19
Y18
AB18
Y17
AA23
AA22
AC23
Y21
AB23
Y22
W21
Y23
W20
AC22
AB22
W23
V21
V23
U21
U23
T21
T23
R21
R20
T22
T20
U22
U20
V22
V20
W22
E1
E2
Y1
Y2
Y3
E3
V5
E5
SB_PM_BATLOW#
SB_EC_SWI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
PCI_ACT_REQ#
SUS_STAT#
SB_TEST1
SB_TEST0
SB_GA20
SB_KBRST#
SB_AC_IN
LPC_PME#
LPC_SMI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
PWR_STRP
IDEIORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3
IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15
IDEIORDYB
IDEIRQB
IDESAB0
IDESAB1
IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B
IDECS#B1
IDECS#B3
IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15
AC97_SDOUT_R
AC97_SYNC_R
SPDIF_OUT
SLP_S3# <46>
SLP_S5# <46>
PWRBTN_OUT# <46>
SB_PWRGD <48>
SUS_STAT# <8>
SMB_CK_CLK2 <14,15,24>
SMB_CK_DAT2 <14,15,24>
PWR_STRP <29>
IDEIORDYA <30>
IDEIRQA <30>
IDESAA0 <30>
IDESAA1 <30>
IDESAA2 <30>
IDEDACK#A <30>
IDEREQA <30>
IDEIOR#A <30>
IDEIOW#A <30>
IDECS#A1 <30>
IDECS#A3 <30>
IDEDA[0..15] <30>
IDEIORDYB <30>
IDEIRQB <30>
IDESAB0 <30>
IDESAB1 <30>
IDESAB2 <30>
IDEDACK#B <30>
IDEREQB <30>
IDEIOR#B <30>
IDEIOW#B <30>
IDECS#B1 <30>
IDECS#B3 <30>
IDEDB[0..15] <30>
R117 33_0402_5%
R119 33_0402_5%
SPDIF_OUT <29,37>
TALERT#/ETH_TALERT#
PME#/EXT_EVNT0#
RI#/EXT_EVNT1#
PCI_REQACT#
GA20_IN/GEVNT0#
KB_RST#/GEVNT1#
SMB_ALERT#/GEVNT2#
LPC_PME#/GEVNT3#
LPC_SMI#/GEVNT4#
GEVENT5#/ETH_VALERT#
GEVENT6#/ETH_FALERT#
GEVENT7#/ETH_CALERT#
GPOC0#/SCL0
GPOC1#/SDA0
GPOC2#/SCL1
GPOC3#/SDA1
RTC_IRQ#/PWR_STRP
AC97
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AC97_BITCLK
AC97_SDOUT
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
AC97_SYNC
AC97_RST#
2
SB_EC_THERM#
SB_PM_BATLOW#
SB_EC_SWI#
SB_GA20 GA20
SB_KBRST#
SB_EC_SMI#
SB_SCI# SC I#
LPC_SMI# USB_SMI#
AC97_BITCLK <37,44>
AC97_SDOUT <29,37,44>
AC97_SDIN0 <37>
AC97_SDIN1 <44>
AC97_SYNC <29,37,44>
AC97_RST# <37,44>
2
1
D2 RB751V_SOD323
2 1
D3 RB751V_SOD323
2 1
D4 RB751V_SOD323
2 1
D5 RB751V_SOD323
2 1
D6 RB751V_SOD323
2 1
D7 RB751V_SOD323
2 1
D8 RB751V_SOD323
2 1
D9 RB751V_SOD323
2 1
D10 RB751V_SOD323
2 1
R1062 0_0603_5%
1 2
R68 10K_0402_5%
1 2
PIR BOM 92.07.30
Title
Size Document Number Rev
Date: Sheet
星期四 八月
EC_THERM#
PM_BATLOW#
EC_SWI#
KBRST#
ACINSB_AC_IN
EC_SMI#
LID_OUT#SB_LID_OUT#
SUS_STAT#
R69 4.7K_0402_5%
1 2
GHI
AGP_STP#_R
AGP_BUSY#_R
SB_GA20
SB_KBRST#
SB_EC_SWI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
LPC_PME#
LPC_SMI#
SB_AC_IN
PCI_ACT_REQ#
PWRBTN_OUT#
SLP_S3#
SLP_S5#
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
AC97_RST#
AGP_STP#
AGP_BUSY#
SB_TEST0
SB_TEST1
AC97_BITCLK
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
RP11 10K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP12 2.2K_0804_8P4R_5%
R111 8.2K_0402_5%
1 8
2 7
3 6
4 5
RP140 8.2K _8P4R_0804_5%
1 8
2 7
3 6
4 5
RP13 8. 2 K _ 8 P4 R _0804_5%
Compal Electronics, Inc.
SB200M(2/4) - IDE/USB/MII
LA-1811
03
1
EC_THERM# <46>
PM_BATLOW# <46>
EC_SWI# <46>
GA20 <46>
KBRST# <46>
ACIN <46,50,53>
EC_SMI# <46>
SCI# <46>
LID_OUT# <46>
USB_SMI# <36>
+2.5V
+3V
RP107
10K_0804_8P4R_5%
RP108
10K_0804_8P4R_5%
RP109
10K_0804_8P4R_5%
RP110
10K_0804_8P4R_5%
+3VALW
+3VS
+3V
+3VS
of
27 66, 07, 20
0.7
Page 28
5
4
3
2
1
+3VS +3VS
1
C27
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C44
2
2
1
C53
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
2
C45
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C24
D D
C C
22U_1206_16V4Z_V1
22U_1206_16V4Z_V1
C23
22U_1206_16V4Z_V1
C40
C49
22U_1206_16V4Z_V1
2
+2.5VS
1
2
+2.5V
0.1U_0402_10V6K
1
C50
2
C25
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C42
C41
2
0.1U_0402_10V6K
1
1
C51
2
2
0.1U_0402_10V6K
1
C26
2
1
C43
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C52
2
1
C28
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C46
2
0.1U_0402_10V6K
1
C29
2
1
C47
2
0.1U_0402_10V6K
1
C30
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C32
C31
2
1
C48
0.1U_0402_10V6K
2
ATI request
+3V
0.1U_0402_10V6K
1
C55
22U_1206_16V4Z_V1
1 2
+3V
R60 0_0805_5%
B B
1 2
+3V
R61 0_0805_5%
22U_1206_16V4Z_V1
C54
2
+3V_AVDDC
1
C59
1U_0603_10V6K
2
+3V_AVDDUSB
0.1U_0402_10V6K
1
C63
C62
2
0.1U_0402_10V6K
1
1
C56
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C64
2
2
0.1U_0402_10V6K
1
C57
2
1
C60
0.1U_0402_10V6K
2
1
C66
C65
2
0.1U_0402_10V6K
1
C58
0.1U_0402_10V6K
2
0.1U_0402_10V6K
1
1
C67
2
2
@0.1U_0402_16V7K
1
C68
0.1U_0402_10V6K
2
+3V
C882
ATI request
@10U_0805_10V6K
ATI request
+3V_AVDDUSB
@47U_B_6.3VM
ATI request
+2.5V_AVDDCK
1 2
+2.5VS
R62 0_0805_5%
A A
1
C71
1U_0603_10V6K
2
1
C72
0.1U_0402_10V6K
2
@22U_1206_16V4Z_V1
1
C33
2
0.1U_0402_10V6K
C883
@0.1U_0402_16V7K
+3V_AVDDC
C887
1
+
C888
2
+2.5V_AVDDCK
1
C889
2
0.1U_0402_10V6K
1
1
C35
C34
2
2
0.1U_0402_10V6K
C873
@0.01U_0402_16V7Z
C878
@0.01U_0402_16V7Z
@0.1U_0402_16V7K
0.1U_0402_10V6K
1
1
C36
2
2
0.1U_0402_10V6K
+3VS
1
C874
2
@0.01U_0402_16V7Z
+2.5VS
@0.01U_0402_16V7Z
1
C879
2
+2.5V
C885
0.1U_0402_10V6K
1
C37
2
ATI request
@0.01U_0402_16V7Z
1
C875
2
1
1
C38
2
2
1
1
C876
2
2
@0.01U_0402_16V7Z
ATI request
1
1
C880
2
@0.01U_0402_16V7Z
1
2
2
ATI request
CLOSE TO
L6,H6,J6
C886
@0.1U_0402_16V7K
+3VS
D90
2 1
RB751V_SOD323
1U_0603_10V6K
C39
0.1U_0402_10V6K
1
C877
@0.01U_0402_16V7Z
2
C881
@0.01U_0402_16V7Z
C966
0.1U_0402_16V7K
+5VS
12
R1114
1K_0402_5%
1
C843
2
+2.5V
+3V_AVDDC
+3V
+3V_AVDDUSB
+2.5VS
+2.5V_AVDDCK
+2.5VALW
+3VALW
0.1U_0402_10V6K
+2.5VS
1
1
C69
2
2
E11
E12
E15
E7
E8
F11
F12
F15
F16
F17
F7
F8
G18
G19
H18
H19
M18
M19
N18
N19
T18
T19
U18
U19
V17
V18
W17
W18
J10
J11
J13
J14
K15
K9
L15
L9
N15
N9
P15
P9
R10
R11
R13
R14
P6
R6
V13
W13
V12
L6
H6
J6
P5
T6
U6
V9
V10
V11
W9
W10
F4
J4
K5
F3
K4
L5
D19
D1
A21
Y9
AA9
C70
0.1U_0402_10V6K
U3C
SB200 SB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
VDD_USB
VDD_USB
VDD_USB
AVDDC
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
AVDDTX0
AVDDTX1
AVDDTX2
AVDDRX0
AVDDRX1
AVDDRX2
VREF_CPU
5V_VREF
AVDD_CK
S5_2.5V
S5_3.3V
South bridge SB200
Part 3 of 3
POWER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_USB
VSS_USB
AVSSC
AVSSRX2
AVSSRX1
AVSSRX0
AVSSTX2
AVSSTX1
AVSSTX0
AVSSCK
E10
E13
E14
E6
E9
F10
F13
F14
F18
F6
F9
G6
J12
J15
J18
J19
J9
K10
K11
K12
K13
K14
K18
K19
L10
L11
L12
L13
L14
L18
L19
M10
M11
M12
M13
M14
M15
M6
M9
N10
N11
N12
N13
N14
N6
P10
P11
P12
P13
P14
P18
P19
R12
R15
R18
R19
R9
V14
V15
V16
V19
V6
V7
V8
W14
W15
W16
W19
W7
W8
H5
G5
N5
M5
J5
G4
K6
H4
F5
A22
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(3/4) - PWR
LA-1811
星期四 八月
0.7
of
28 66, 07, 2003
1
Page 29
5
D D
4
3
2
1
+3VALW +3V +3V
MANUAL
PWR ON
DEFAULT
PWR
ON
+3VS
12
R953
@10K_0402_5%
12
R34
10K_0402_5%
R47
@10K_0402_5%
R35
@10K_0402_5%
12
R48
10K_0402_5%
IGN DEBUG SPEEDSTEP FREQLTCH
EEDO
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
EECK
ROM ON
PCI BUS
ROM ON
LPC
BUS
DEFAULT
R36
@10K_0402_5%
12
R49
10K_0402_5%
C C
PWR_STRP<27>
SB_EEDO<27>
SB_EECLK<27>
AC97_SYNC<27,37,44>
AC97_SDOUT<27,37,44>
SPDIF_OUT<27,37>
MII_TXEN<27>
MII_TXD3<27>
MII_TXD2<27>
MII_TXD1<27>
MII_TXD0<27>
32KHZ_S5_OUT<27>
B B
REQUIRED SYSTEM STRAPS
STRAP
HIGH
STRAP
LOW
+3VS
1 2
AC_SYNC
INIT ACTIVE
HIGH
INIT ACTIVE
LOW (PIII)
DEFAULT
R37
@10K_0402_5%
R50
10K_0402_5%
+3VS +3VS
R38
@10K_0402_5%
12
R51
10K_0402_5%
33MHz NB
BUS
HI SPEED
A-LINK
DEFAULT
SIO 24MHzUSE
SIO 48MHzAUTO
DEFAULT
R39
@10K_0402_5%
12
R52
10K_0402_5%
CPU_STP#
ENABLE
SPEED
STEP
DISABLE
SPEED
STEP
DEFAULT
+3V +3V +3V +3V +3V
12
R41
10K_0402_5%
R54
@10K_0402_5%
TX_EN
DISABLE
CPU FREQ
SETTING
DEFAULT
ENABLE CPU
FREQSETTING
R42
10K_0402_5%
R55
@10K_0402_5%
R43
10K_0402_5%
R56
@10K_0402_5%
ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP
PROCESSOR FREQ MULTIPLIER
R44
10K_0402_5%
R57
@10K_0402_5%
R45
10K_0402_5%
R58
@10K_0402_5%
32KHZ_S5
32KHZ
OUTPUT
FROM SB200
(INT RTC)
DEFAULT
32KHZ INPUT
TO SB200
(EXT RTC)
+3VALW
12
R46
10K_0402_5%
R59
@10K_0402_5%
A A
5
PCI_AD26<26,31,34,35,36,43>
12
R967
10K_0402_5%
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SB200M(4/4) - STRAPS
LA-1811
星期四 八月
0.7
of
29 66, 07, 2003
1
Page 30
5
U1B
R19
4
I0
5
I1
9
I0
10
I1
12
PD_A0
PD_A1
PD_A2
PD_CS#3
SD_SBA0
SD_SBA1
SD_SBA2
SD_SCS3#
12
R32
5.6K_0402_5%
6
O
74HCT08PW_TSSOP14
U1C
8
O
74HCT08PW_TSSOP14
PD_DREQ#
PD_IOW#
PD_IOR#
PD_CS#1
PD_DACK#
PD_IRQA
R968
8.2K_0402_5%
1 2
SD_DREQ
SD_SIOW#
SD_SIOR#
SD_SCS1#
SD_DACK#
SD_IRQ15
R33
8.2K_0402_5%
1 2
SD_IDERST#
HD_IDERST#
+5VS
IDEIORDYA< 27>
IDEIORDYB< 27>
IDERST_CD#<27>
D D
IDEDA[0..15]<27>
IDEDA14
IDEDA1
IDEDA15
IDEDA0
IDEDA5
IDEDA10
IDEDA11
IDEDA4
IDEDA7
IDEDA8
IDEDA6
IDEDA9
IDEDA3
IDEDA12
IDEDA13
C C
B B
A A
IDEDA2
IDEIOW#A<27>
IDECS#A1<27>
IDEDACK#A<27>
IDECS#A3<27>
IDECS#B3<27>
IDEDB[0..15]<27>
IDEDB5
IDEDB9
IDEDB4
IDEDB11
IDEDB0
IDEDB15
IDEDB1
IDEDB14
IDEDB6
IDEDB10
IDEDB8
IDEDB7
IDEDB3
IDEDB12
IDEDB2
IDEDB13
IDEREQB<27>
IDEIOW#B<27>
IDEIOR#B<27>
IDECS#B1<27>
IDEDACK#B<27>
IDEIRQB<27>
IDEREQA<27>
IDEIOR#A<27>
IDEIRQA<27>
IDESAA0<27>
IDESAA1<27>
IDESAA2<27>
IDESAB0<27>
IDESAB1<27>
IDESAB2<27>
RP9
RP10
PCI_RST#<11,26,31,34,35,36,43,46>
IDERST_HD#<27>
IDEDA[0..15]
PD_D14
4 5
PD_D1
3 6
PD_D15
2 7
PD_D0
1 8
RP1 33_0804_8P4R_5%
RP2 33_0804_8P4R_5%
RP3 33_0804_8P4R_5%
RP4 33_0804_8P4R_5%
RP7 33_0804_8P4R_5%
RP8 33_0804_8P4R_5%
PD_D5
4 5
PD_D10
3 6
PD_D11
2 7
PD_D4
1 8
PD_D7
4 5
PD_D8
3 6
PD_D6
2 7
PD_D9
1 8
PD_D3
4 5
PD_D12
3 6
PD_D13
2 7
PD_D2
1 8
R11 33_0603_1%
4 5
3 6
RP124 33_0804_8P4R_5%
2 7
1 8
R18 33_0603_1%
5.6K_0402_5%
IDESAA0
IDESAA1
IDESAA2
IDECS#A3
RP5 33_0804_8P4R_5%
IDESAB0
IDESAB1
RP6 33_8P4R_0804_5%
IDEDB[0..15]
SD_D5
4 5
SD_D9
3 6
SD_D4
2 7
SD_D11
1 8
SD_D0
4 5
SD_D15
3 6
SD_D1
2 7
SD_D14
1 8
SD_D6
4 5
SD_D10
3 6
SD_D8
2 7
SD_D7
1 8
33_0804_8P4R_5%
SD_D3
4 5
SD_D12
3 6
SD_D2
2 7
SD_D13
1 8
33_0804_8P4R_5%
R26 33_0603_1%
4 5
3 6
RP125 33_0804_8P4R_5%
2 7
1 8
R31 33_0603_1%
5
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4
HDD_LED#
CDLED#
12
13
HD_IDERST#
R3
R4 33_0402_5%
1 2
R15
1 2
10K_0402_5%
R969 33_0402_5%
R970 33_0402_5%
1 2
SD_DREQ
4
+5VS
14
1
P
I0
2
I1
G
7
U1D
I0
O
I1
74HCT08PW_TSSOP14
10K_0402_5%
12
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#
+5VS
1 2
U1A
3
O
74HCT08PW_TSSOP14
11
SUYIN_200006FA044S503ZU
+3VS
+3VS
12
R25
4.7K_0402_5%
SD_SIORDY
+5VS
ACT_LED# <45>
JP1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
R8
4.7K_0402_5%
1 2
PD_IORDY
+5VS
1
2
4.7U_0805_10V4Z
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PCSEL
PD_A2
PD_CS#3
+5VS
C1
1000P_0402_50V7K
1
2
W=100mils
1
C14
2
10U_0805_16V4Z
1
C15
2
1U_0603_10V6K
1
2
0.1U_0402_10V6K
Placea caps. ne ar CDROM CONN.
+5VCD trace to CONN W=100mils
33P_0402_25V8K
1 2
C22
3
2
HDD/CD-ROM Module
1
C2
10U_0805_16V4Z
2
Placea caps. near HDD CONN.
1 2
+5VS
1
C7
1U_0603_25V4Z
2
C6
R9 470_0402_5%
1
C3
10U_0805_16V4Z
2
1
C8
4.7U_0805_10V4Z
2
1
C4
1U_0603_10V6K
2
+5VS+5VS
PIR BOM 92.07.30
C11 @10U_0805_6.3V6M
12
R611
R24
1 2
10K_0402_5%
470_0402_5%
C16
1000P_0402_50V7K
10K_0402_5%
R614
1 2
C17
12
CDROM_L
SD_IDERST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0
CDLED#
+5VS
+5VS
SD_CSEL
1
2
JP2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
CD-ROM CONN.
+5VS
1
C18
2
10U_0805_16V4Z
1U_0603_10V6K
Placea caps. ne ar CDROM CONN.
+5VCD trace to CONN W=100mils
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C5
0.1U_0402_10V6K
2
1
C9
1U_0603_25V4Z
2
@47P_0402_25V8K
C12
1 2
CD_AGND
CDROM_R
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#
SD_DACK#
R1110 @10K_0402_5%
SD_SBA2
SD_SCS3#SD_SCS1#
W=80mils
C610 0.1U_0402_10V6K
1 2
R613 @100K_0402_5%
W=100mils
1
C19
2
0.1U_0402_10V6K
1 2
12
1
C20
1000P_0402_50V7K
2
2
CD_AGND <37>
CDROM_R <37>CDROM_L<37>
+5VS
+5VS
+5VS
+5VS
C21
+5VS
1
2
1
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
HDD & CDROM Connector
星期四 八月
LA-1811
of
30 66, 07, 2003
1
0.7
Page 31
A
1 1
2 2
S2_RST<32,33>
S2_WE#<32,33>
S2_IOWR#<32>
S2_IORD#<32>
S2_REG#<32,33>
S2_OE#<32,33>
S2_INPACK#<32,33>
S2_RDY#<32,33>
S2_BVD2<32,33>
S2_WAIT#<32,33>
S2_BVD1<32,33>
3 3
S2_WP<32>
S2_VS1<32,33>
S2_VS2<32,33>
S2_CE1#<32,33>
S2_CE2#<32>
S2_CD1#<32,33>
S2_CD2#<32,33>
S2_D0
S2_D1
S2_D2
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8
S2_A9
S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
S2_A16
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25
PCI_CLKRUN#<26,34,35,36,43>
SIRQ<26,39,46>
CARD_LED#<42>
PCI_PIRQA#<10,17,26,35,36>
PCI_PIRQB#<26>
PCM_SUSP#<46>
SLDATA<32>
RTCCLK<32>
SLATCH<32>
PCM_SPK#<37>
0.1U_0402_10V6K
U37
W10
B_CAD27/B_D0
U10
B_CAD29/B_D1
P10
B_RSVD/B_D2
H3
B_CAD0/B_D3
H1
B_CAD1/B_D4
J2
B_CAD3/B_D5
J5
B_CAD5/B_D6
K2
B_CAD7/B_D7
V10
B_CAD28/B_D8
R10
B_CAD30/B_D9
V11
B_CAD31/B_D10
H2
B_CAD2/B_D11
J1
B_CAD4/B_D12
J3
B_CAD6/B_D13
J6
B_RSVD/B_D14
K3
B_CAD8/B_D15
R8
B_CAD26/B_A0
W7
B_CAD25/B_A1
V7
B_CAD24/B_A2
P8
B_CAD23/B_A3
V6
B_CAD22/B_A4
U6
B_CAD21/B_A5
V5
B_CAD20/B_A6
U5
B_CAD18/B_A7
M6
B_CC/BE1#/B_A8
M2
B_CAD14/B_A9
K6
B_CAD9/B_A10
L6
B_CAD12/B_A11
T1
B_CC/BE2#/B_A12
N2
B_CPAR/B_A13
N6
B_CPERR#/B_A14
P5
B_CIRDY#/B_A15
P6
B_CCLK/B_A16
M3
B_CAD16/B_A17
M5
B_RSVD/B_A18
N3
B_CBLOCK#/B_A19
P2
B_CSTOP#/B_A20
P3
B_CDEVSL#/B_A21
R2
B_CTRDY#/B_A22
R3
B_CFRAME#/B_A23
W4
B_CAD17/B_A24
R6
B_CAD19/B_A25
W5
B_CRST#/B_RESET
N5
B_CGNT/B_WE#
M1
B_CAD15/B_IOWR#
L5
B_CAD13/B_IORD#
U7
B_CC/BE3#/B_REG#
L3
B_CAD11/B_OE#
R7
B_CREQ#/B_INPACK#
V8
B_CINT#/B_IREQ#
V9
B_CAUDIO/B_SPKR#
W9
B_CSERR#/B_WAIT#
U9
B_CSTSCHG/B_STSCHG#
R9
B_CCLKRUN/B_IOIS16#
U8
B_CVS1/B_VS1#
P7
B_CVS2/B_VS2#
K5
B_CC/BE0#/B_CE1#
L2
B_CAD10/B_CE2#
H5
B_CCD1#/B_CD1#
P9
B_CCD2#/B_CD2#
C635
1 2
R833
0_0402_5%
F15
L1
F14
E18
E17
C15
K19
E5
NC
2.5V
DATA
LATCH
CLOCK
VR_EN#
SPKROUT
SLOT B
B
12
+3V
D19
SUSPEND#
FUNCTION
A16
MFUNC0
E14
MFUNC1
F13
MFUNC2
B15
MFUNC3
MFUNC4
A15
C14
MFUNC5
1 2
W11
NC
MFUNC6
R633
1620@0_0402_5%
A12
VCCA7VCC
VCCG1VCC
R939
0_0402_5%
G19
J19
N19
W13
VCC
VCCN1VCC
VCCW8VCC
POWER
CARDBUS CONTROLLER
PCI1520 PBGA 209
PCI INTERFACE
12
+3V+3VS
12
R940
@0_0402_5%
+S1_VCC
A10
VCCP
+S2_VCC
P19
VCCA
C
R1
VCCB
R1018
@10K_0402_5%
2
C909
@0.1U_0402_10V6K
1
A_CAD27/A_D0
A_CAD29/A_D1
A_RSVD/A_D2
A_CAD0/A_D3
A_CAD1/A_D4
A_CAD3/A_D5
A_CAD5/A_D6
A_CAD7/A_D7
A_CAD28/A_D8
A_CAD30/A_D9
A_CAD31/A_D10
A_CAD2/A_D11
A_CAD4/A_D12
A_CAD6/A_D13
A_RSVD/A_D14
A_CAD8/A_D15
A_CAD26/A_A0
A_CAD25/A_A1
A_CAD24/A_A2
A_CAD23/A_A3
A_CAD22/A_A4
A_CAD21/A_A5
A_CAD20/A_A6
A_CAD18/A_A7
A_CC/BE1#/A_A8
A_CAD14/A_A9
A_CAD9/A_A10
A_CAD12/A_A11
A_CC/BE2#/A_A12
A_CPAR/A_A13
A_CPERR#/A_A14
A_CIRDY#/A_A15
A_CCLK/A_A16
A_CAD16/A_A17
SLOT A
A_RSVD/A_A18
A_CBLOCK#/A_A19
A_CSTOP#/A_A20
A_CDEVSL#/A_A21
A_CTRDY#/A_A22
A_CFRAME#/A_A23
A_CAD17/A_A24
A_CAD19/A_A25
A_CRST#/A_RESET
A_CGNT#/A_WE#
A_CAD15/A_IOWR#
A_CAD13/A_IORD#
A_CC/BE3#/A_REG#
A_CAD11/A_OE#
A_CREQ#/A_INPACK#
A_CINT#/A_IREQ#
A_CAUDIO/A_SPKR#
A_CSERR#/A_WAIT#
A_CSTSCHG/A_STSCHG#
A_CCLKRUN#/A_IOIS16#
A_CVS1/A_VS1#
A_CVS2/A_VS2#
A_CAD10/A_CE2#
A_CC/BE0#/A_CE1#
A_CCD1#/A_CD1#
A_CCD2#/A_CD2#
CLK_SD_48M <24>
G17
F18
F17
P11
W12
U12
R12
U13
G14
G15
E19
R11
V12
P12
V13
P13
J14
J17
J18
K15
K18
L14
L17
M19
T19
U15
R13
P14
M17
P15
R18
N18
M14
W16
R17
N14
P17
N15
N17
M15
M18
L19
L15
P18
R14
V15
K14
W15
K17
H19
H17
H18
H14
H15
J15
L18
U14
V14
U11
G18
0.1U_0402_10V6K
S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
S1_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_RST <32>
S1_WE# <32>
S1_IOWR# <32>
S1_IORD# <32>
S1_REG# <32>
S1_OE# <32>
S1_INPACK# <32>
S1_RDY# <32>
S1_BVD2 <32>
S1_WAIT# <32>
S1_BVD1 <32>
S1_WP <32>
S1_VS1 <32>
S1_VS2 <32>
S1_CE2# <32>
S1_CE1# <32>
S1_CD1# <32>
S1_CD2# <32>
C633
+3V
D
2
1
+3V
1
2
0.1U_0402_10V6K
0.01U_0402_16V7K
2
C634
0.1U_0402_10V6K
1
0.1U_0402_10V6K
C845
C898
1
C846
2
+3V
0.1U_0402_10V6K
1
C847
2
0.1U_0402_10V6K
0.01U_0402_16V7K
1
1
C899
C900
2
2
0.01U_0402_16V7K
1
C848
2
0.1U_0402_10V6K
0.01U_0402_16V7K
1
1
C901
2
2
0.1U_0402_10V6K
1
C849
2
1
C902
2
0.01U_0402_16V7K
E
JP24A1
CARDBUS HOUSING
1
C850
2
0.1U_0402_10V6K
1
C903
0.01U_0402_16V7K
2
1
C851
2
GROUND
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD10D1AD9E3AD8F5AD7E2AD6F3AD5F2AD4G5AD3F1AD2H6AD1G3AD0
G2
B12
AD22B9AD21C9AD20F9AD19E9AD18A8AD17B8AD16C8AD15B5AD14E6AD13C5AD12A4AD11
F11
F12
F10
B10
C/BE3#
C/BE2#F8C/BE1#F6C/BE0#
RI_OUT#/PME#
GRST#
PRST#
PCLK
GNT#
REQ#
SERR#C6PERR#E7IDSEL
DEVSEL#F7STOP#B6IRDY#B7TRDY#C7FRAME#E8PAR
G6
E12
A11
B11
E11
B14
E13
B13
A13
C12
C11
E10
C13
C10
GNDA6GNDA9GND
GNDE1GNDK1GNDP1GND
GNDW6GND
GND
A5
A14
PCI1520GHK_PBGA209
F19
R19
W14
PCI_AD3
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD6
PCI_AD9
PCI_AD5
PCI_AD8
PCI_AD4
PCI_AD7
4 4
A
PCI_CBE#[0..3]<26,34,35,36,43>
S2_D[0..15]<32,33>
S2_A[0..25]<32,33>
S1_D[0..15]<32>
S1_A[0..25]<32>
PCI_AD[0..31]<26,29,34,35,36,43>
PCI_CBE#[0..3]
S2_D[0..15]
S2_A[0..25]
S1_D[0..15]
S1_A[0..25]
PCI_AD[0..31]
PCI_AD16
PCI_AD19
PCI_AD23
PCI_AD10
PCI_AD11
PCI_AD15
PCI_AD14
PCI_AD12
PCI_AD13
PCI_AD17
PCI_AD24
PCI_AD28
PCI_AD22
PCI_AD18
PCI_AD21
PCI_AD20
B
PCI_AD31
PCI_AD27
PCI_AD30
PCI_AD26
PCI_AD29
PCI_AD25
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
R634
0_0402_5%
PCI_CBE#0
12
PCI_AD20_R
R1098
1 2
100_0402_5%
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCI_PAR <26,34,35,36,43>
PCI_FRAME# <26,34,35,36,43>
PCI_TRDY# <26,34,35,36,43>
PCI_IRDY# <26,34,35,36,43>
PCI_STOP# <26,34,35,36,43>
PCI_DEVSEL# <26,34,35,36,43>
PCI_PERR# <26,34,35,36,43>
PCI_SERR# <26,34,35,36,43>
PCI_REQ#2 <26>
PCI_GNT#2 <26>
CLK_PCI_PCM <26>
PCI_RST# <11,26,30,34,35,36,43,46>
G_RST# <32,36,46>
PCM_PME# <34,36,43,46,47>
C
PCI_AD20
CLK_PCI_PCM
R1020
@10K_0402_5%
2
C910
@0.1U_0402_10V6K
1
D
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CardBus Controller OZ6912/CB1410 & Socket
星期四 八月
LA-1811
E
of
31 66, 07, 2003
0.7
Page 32
SOCKETCARDBUS
JP29
1
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#<31>
S1_OE#<31>
S1_WE#<31>
S1_RDY#<31>
+S1_VCC
+S1_VPP
S1_WP<31>
S2_CE1#<31,33>
S2_OE#<31,33>
S2_WE#<31,33>
S2_RDY#<31,33>
+S2_VCC +S2_VCC
S2_WP<31>
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_CE1#
S2_A10
S2_OE#
S2_A11
S2_A9
S2_A8
S2_A13
S2_A14
S2_WE#
S2_RDY#
S2_A16
S2_A15
S2_A12 S2_A24
S2_A7
S2_A6
S2_A5
S2_A4
S2_A3
S2_A2
S2_A1
S2_A0
S2_D0
S2_D1
S2_D2
S2_WP
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
69
GND
71
GND
73
GND
75
GND
77
GND
79
GND
81
GND
83
GND
FOX_WZ21131-G2-P4
JP30
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
69
GND
71
GND
73
GND
75
GND
77
GND
79
GND
81
GND
83
GND
1520@FOX_WZ21131-G2-P4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68
70
72
74
76
78
80
82
84
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
72
74
76
78
80
82
84
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#
S2_CD1#
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15
S2_CE2#
S2_VS1
S2_IORD#
S2_IOWR#
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A25
S2_VS2
S2_RST
S2_WAIT#
S2_INPACK#
S2_REG#
S2_BVD2
S2_BVD1
S2_D8
S2_D9
S2_D10
S2_CD2#
C652
1 2
1520@1000P_0402_50V7K
1
2
C636
1 2
1000P_0402_50V8J
S1_CD1# <31>
S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>
+S1_VCC
+S1_VPP
S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>
S1_CD2# <31>
1
C649
1000P_0402_50V7K
2
S2_CD1# <31,33>
S2_CE2# <31>
S2_VS1 <31,33>
S2_IORD# <31>
S2_IOWR# <31>
+S2_VPP+S2_VPP
S2_VS2 <31,33>
S2_RST <31,33>
S2_WAIT# <31,33>
S2_INPACK# <31,33>
S2_REG# <31,33>
S2_BVD2 <31,33>
S2_BVD1 <31,33>
S2_CD2# <31,33>
C654
1520@1000P_0402_50V7K
S1_D[0..15]<31>
S1_A[0..25]<31>
S2_D[0..15]<31,33>
S2_A[0..25]<31,33>
S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]
+5V
+S1_VCC
+S2_VCC
4.7U_0805_10V4Z
+S1_VCC
1
C647
0.1U_0402_10V6K
2
+S2_VCC
1
C650
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCMCIA POWER CTRL.
U38
12
15
21
19
10
17
18
3
4
5
8
9
DATA
CLOCK
LATCH
RESET#
OC#
SHDN#
AVPP
BVPP
AVCC
AVCC
BVCC
BVCC
TPS2224A
C645
SLDATA<31>
RTCCLK<31>
SLATCH<31>
G_RST#<31,36,46>
R635
+S1_VPP
+S2_VPP
1
2
1 2
4.7K_0402_5%
1
C643
4.7U_0805_10V4Z
2
1
C648
4.7U_0805_10V4Z
2
1
C651
4.7U_0805_10V4Z
2
@0_0603_5%
12V
12V
3.3V
3.3V
5V
5V
5V
GND
NC
NC
NC
NC
+12VALW
R1004
1 2
20
7
14
13
24
2
1
11
23
22
16
6
+S1_VPP
+S2_VPP
C637 @2.2U_0805_10V4Z
1 2
+3V
C638 4.7U_0805_10V4Z
1 2
C639 4.7U_0805_10V4Z
1 2
C640 4.7U_0805_10V4Z
1 2
+5V
C641 4.7U_0805_10V4Z
1 2
C642 4.7U_0805_10V4Z
1 2
C644 4.7U_0805_10V4Z
1 2
1
C646
4.7U_0805_10V4Z
2
1
C653
4.7U_0805_10V4Z
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CARD BUS SOCKET
07, 2003
八月
LA-1811
星期四
0.7
of
32 66,
Page 33
10
9
8
7
6
5
4
3
2
1
+3VS
H H
R636
@10K_0402_5%
S2_A22
R639 1620@0_0402_5%
S2_A22<31,32>
S2_A25<31,32>
S2_A25
1 2
R640
1 2
1620@0_0402_5%
DQRYDRV
G G
R648 1620@0_0402_5%
S2_WAIT#<31,32>
S2_INPACK#<31,32>
S2_D10<31,32>
F F
S2_D9<31,32>
S2_D8<31,32>
S2_BVD1<31,32>
S2_BVD2<31,32>
S2_REG#<31,32>
S2_RST<31,32>
S2_A18<31,32>
1 2
R649 1620@0_0402_5%
1 2
1 8
2 7
3 6
4 5
RP128 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP129 1620@0_0804_8P4R_5%
MC_CD#
1620@10K_0402_5%
R647
SQRY3
SQRY4
SQRY9
SQRY8
SQRY7
SQRY6
SQRY5
SQRY2
SQRY1
12
1620@10K_0402_5%
SQRY10
2
R641
12
3
2
3
D44
1620@BAT54C_SOT23~D
1
1620@BAT54C_SOT23~D
D45
SM_CD#
1
12
1 2
1620@0_0402_5%
R658
12
R637
@10K_0402_5%
1620@47K_0804_8P4R_5%
RP143
+S2_VCC
1 8
2 7
3 6
1620@MMBT3904_SOT23
4 5
MC_WP#
Q53
SD_CD#
E E
S2_A14<31,32>
S2_A19<31,32>
S2_A16<31,32>
S2_A20<31,32>
S2_RDY#<31,32>
D D
C C
S2_A21<31,32>
S2_D11<31,32>
S2_D5<31,32>
S2_D12<31,32>
S2_D6<31,32>
S2_D13<31,32>
S2_D7<31,32>
S2_D14<31,32>
S2_CE1#<31,32>
S2_D15<31,32>
S2_A10<31,32>
S2_A13<31,32>
S2_OE#<31,32>
S2_WE#<31,32>
S2_A8<31,32>
S2_A12<31,32>
S2_A24<31,32>
S2_A15<31,32>
1 8
2 7
3 6
4 5
RP141 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP130 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP131 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP132 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP133 1620@0_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP134 1620@0_0804_8P4R_5%
SD_DATA1
SD_DATA0
SD_CLK/MS_CLK
SD_CMD
SD_CD/DATA3
SD_DATA2
SM_D4
SM_D3/MS_BS
SM_D5
SM_D2/MS_SDIO
SM_D6
SM_D1/MS_RFU5
SM_D7
SM_D0/MS_RFU7
SM_LVD
SM_WP#
SM_WE#
SM_R/B#
SM_ALE
SM_RE#
SM_CLE
SM_CE#
MC_WP#
R665
1 2
@0_0402_5%
1620@47K_0804_8P4R_5%
RP144
1 8
2 7
3 6
4 5
RP145
1 8
2 7
3 6
4 5
1620@47K_0804_8P4R_5%
1 8
+S2_VCC
SD_WP
2
3 1
R646
1 2
1620@43_0402_5%
SD_CD#
SD_DATA1
SD_DATA0
SD_CLK/MS_CLK
SD_CMD
SD_CD/DATA3
SD_DATA2
SM_D4
SM_D3/MS_BS
SM_D5
SM_D2/MS_SDIO
SM_D6
SM_D1/MS_RFU5
SM_D7
SM_D0/MS_RFU7
SM_LVD
SM_WP#
SM_WE#
SM_R/B#
SM_ALE
SM_RE#
SM_CLE
SM_CE#
MC_WP#
MC_CD#
RP146
1620@47K_0804_8P4R_5%
2 7
3 6
4 5
R638
1620@43K_0402_5%
1 2
+S2_VCC
1620@0.1U_0402_10V6K
1
C655
1
C656
1620@0.1U_0402_10V6K
2
2
JP31
1
SSFDC_10P/SD_6P/SD_3P(GND)
2
SD_SW_CD1
3
SD_SW_WP1
4
SD_8P(DAT1)
5
SD_7P(DAT0)
6
SD_5P(CLK)
7
SD_2P(CMD)
8
SD_1P(DAT3)
9
SD_9P(DAT2)
10
SSFDC_12P & SD_4P(VCC)
11
SSFDC_11P(CD)
12
SSFDC_13P(D4)
13
SSFDC_9P(D3)
14
SSFDC_14P(D5)
15
SSFDC_8P(D2)
16
SSFDC_15P(D6)
17
SSFDC_7P(D1)
18
SSFDC_16P(D7)
19
SSFDC_6P(D0)
20
SSFDC_17P(LVD)
21
SSFDC_5P(WP_IN)
22
SSFDC_4P(WE)
23
SSFDC_19P(BSY)
24
SSFDC_3P(ALE)
25
SSFDC_20P(RE)
26
SSFDC_2P(CLE)
27
SSFDC_21P(CE)
28
SSFDC_WP2(SW_WP2)
29
SSFDC_CD2(SW_CD2)
30
SSFDC_22P/MS_3P/MS/9P(VCC)
31
MS_2P(BS)
32
MS_4P(SDIO)
33
MS_5P(RESERVED1)
34
MS_6P(INS)
35
MS_7P(RESERVED2)
36
MS_8P(SCLK)
37
MS_10P & MS_1P/SSFDC_1P &SSFDC_18P(GND)
1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR
B B
R987 1620@0_0402_5%
S2_CD1#<31,32>
S2_CD2#<31,32>
S2_VS2<31,32>
A A
10
1 2
R988 1620@0_0402_5%
1 2
R989 1620@0_0402_5%
1 2
9
S2_VS1 <31,32>
8
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
7
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
5
4
3
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
4 IN 1 CARD READER SOCKET
2
LA-1811
03
星期四 八月
0.7
of
33 66, 07, 20
1
Page 34
5
LANIO
1
C659
0.1U_0402_10V6K
2
C665
1U_0603_10V6K
PCI_AD[0..31]<26,29,31,35,36,43>
PCI_CBE#[0..3]<26,31,35,36,43>
PCI_PAR<26,31,35,36,43>
PCI_FRAME#<26,31,35,36,43>
PCI_IRDY#<26,31,35,36,43>
PCI_TRDY#<26,31,35,36,43>
PCI_DEVSEL#<26,31,35,36,43>
PCI_STOP#<26,31,35,36,43>
PCI_PERR#<26,31,35,36,43>
PCI_SERR#<26,31,35,36,43>
PCI_REQ#1<26>
PCI_GNT#1<26>
PCI_PIRQD#<26,36>
ONBD_LAN_PME#<31,36,43,46,47>
PCI_RST#<11,26,30,31,35,36,43,46>
CLK_PCI_LAN<26>
PCI_CLKRUN#<26,31,35,36,43>
@10P_0402_50V8K
+3VALW
1
2
@22_0402_5%
C682
1 2
0_0805_5%
PCI_AD[0..31]
PCI_CBE#[0..3]
PCI_AD19
12
R709
1
2
D D
C C
B B
A A
R1006
LANIO
1
C666
1U_0603_10V6K
2
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27 LAN_RXPCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
1 2
R703 100_0402_5%
LANIO
U39
47
AD0
46
AD1
45
AD2
43
AD3
42
AD4
41
AD5
40
AD6
39
AD7
36
AD8
35
AD9
34
AD10
33
AD11
32
AD12
30
AD13
29
AD14
28
AD15
15
AD16
14
AD17
13
AD18
12
AD19
11
AD20
10
AD21
9
AD22
8
AD23
96
AD24
93
AD25
92
AD26
91
AD27
89
AD28
87
AD29
86
AD30
85
AD31
38
C/BE#0
27
C/BE#1
17
C/BE#2
84
C/BE#3
98
IDSEL
24
PAR
18
FRAME#
19
IRDYB#
20
TRDY#
21
DEVSEL#
23
STOP#
25
PERR#
26
SERR#
83
REQ#
82
GNT#
80
INTA#
57
PME#
81
RST#
97
PCICLK
50
CLKRUN#
6
VDD
22
VDD
37
VDD
Power
49
VDD
90
VDD
95
VDD
RTL8101L_LQFP100
4
1
C660
0.1U_0402_10V6K
2
PCI I/F
1
2
48
VDD25
94
VDD25
58
AVDD25
59
AVDD
70
AVDD
75
AVDD
Power
52
EEDO
53
EEDI
54
EESK
55
EECS
51
ROMCS#
78
LED0
77
LED1
76
LED2
72
TXD+
71
TXD-
68
RXIN+
67
RXIN-
61
X1
60
X2
LAN I/F
64
LWAKE
74
ISOLATE#
65
RTSET
63
RTT3
56
VCTRL
69
NC
1
AC_RST#
3
AC_SYNC
4
AC_DOUT
5
AC_DIN
7
AC_BCK
79
INTB#
99
GPIO1
100
GPIO0
AC-Link
2
GND
16
GND
31
GND
44
GND
62
GND
66
GND
73
GND
88
GND
C661
0.1U_0402_10V6K
C672
0.1U_0402_10V6K
EEDO
EEDI
EESK
EECS
ACTIVITY#
LINK10_100#
LAN_TX+
LAN_TX-
LAN_RX+
CLKOUT
XTALFB
R701 15K_0402_5%
1 2
ISOB
R702 1K_0402_5%
R704 5.6K_0603_1%
1
C662
0.1U_0402_10V6K
2
1
C663
0.1U_0402_10V6K
2
LANVDD
Close to U39 pin58
LANVDD
LANVDD
2
2
C673
1
1
0.1U_0402_10V6K
R698 5.6K_0402_5%
1 2
12
12
CLKOUT XTALFB
25MHZ_20P_1BX25000CK1A
1
C680
27P_0402_50V8J
2
2
1
1
C657
0.1U_0402_10V6K
2
C667
10U_0805_10V4Z
L43
LAN_IO
1 2
KC FBM_L11-201209-601LMT 0805
2
C674
0.1U_0402_10V6K
1
+3VS
Y5
1 2
3
C664
0.1U_0402_10V6K
LANVDD
1
2
U40
4
DO
3
DI
2
SK
1
CS
AT93C46-10SI-2.7_SO8
LANIO
1
C658
0.1U_0402_10V6K
2
LANIO
GND
NC
NC
VCC
2
C681
27P_0402_50V8J
1
5
6
7
8
LANIO
RJ45_RXX-<41>
RJ45_RXX+<41>
RJ45_TXX-<41>
RJ45_TXX+<41>
LANIO
RJ45_GND<41>
2
C675
0.1U_0402_10V6K
1
LANIO
ACTIVITY#
R694 300_0603_5%
1 2
RJ45_RXX-
RJ45_RXX+
RJ45_TXXRJ45_TXX+
LINK10_100#
R695 300_0603_5%
1 2
R696
75_0402_1%
RJ45_GND
1
2
12
R699
49.9_0402_1%
LAN_TXLAN_TX+
LAN_RXLAN_RX+
C677
0.1U_0402_10V6K
1 2
49.9_0402_1%
12
R707
2
1
2
JP32
12
T=10mil
T=10mil
1 2
C676
0.1U_0402_10V6K
12
R700
49.9_0402_1%
12
R708
49.9_0402_1%
C679
0.1U_0402_10V6K
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
AMP RJ45 with LED
R697
75_0402_1%
1 2
C669
1 2
1000P_1206_2KV7K
C670
0.1U_0402_10V6K
Termination plane should be copled
to chassis ground and also depends
on safety concern
SHLD4
SHLD3
SHLD2
SHLD1
1
2
Please close to LAN IC
U41
1:1
TX+
RX+
9
10
11
CT
14
CT
15
RX-
16
TD-8TX-
7
TD+
6
CT
3
CT
2
RD-
1
RD+
NS0013_16P
16
15
14
13
LANGND
1
C671
2
4.7U_0805_10V4Z
RJ45_TXXRJ45_TXX+
RJ45_RXXRJ45_RXX+
R705
75_0402_1%
1000P_1206_2KV7K
CHASSIS GND
1
12
12
R706
75_0402_1%
RJ45_GND
1
C678
2
Layout Recommend :
1. LAN_RD+, LAN_RD- should be equal length as possible
2. LAN_TD+, LAN_TD- should be equal length as possible
3. The Maximum trace length between LAN chip(U22) and
Magnetic(U24) is 12cm(4.7")
4. The distance between RJ45(Conn.) and Magnetic(U24) should
be as short as possible
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
LAN RealT ech8101BL
LA-1811
星期四 八月
0.7
of
34 66, 07, 2003
1
Page 35
5
4
3
+3VS
+3VS
2
1
1
C692
1000P_0402_50V7K
2
12
R721
56.2_0402_1%
12
R723
56.2_0402_1%
12
R727
5.11K_0402_1%
1
C687
0.1U_0402_10V6K
2
1
C701
2
1
C688
0.1U_0402_10V6K
2
1
C693
1000P_0402_50V7K
2
1U_0603_10V6K
JP33
4
8
3
7
2
6
1
5
AMP_440168-2
The connector depend on
defferent project
1
C689
0.1U_0402_10V6K
2
1
C694
1000P_0402_50V7K
2
Connect To
Shielding GND
1
12
R711 10K_0402_5%
CYCLEIN
RP135
86
11
96
DVDD
CNA
DVDD
TEST1710TEST16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CYCLEOUT/CARDBUS
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD
NC/(TPBIAS1)
NC/(TPA1+)
NC/(TPA1-)
NC/(TPB1+)
NC/(TPB1-)
FILTER0
FILTER1
TPBIAS0
TPA0+
TPA0-
TPB0 +
TPB0 -
TEST9
TEST8
TEST3
TEST2
TEST1
TEST0
103
1
C705
0.1U_0402_10V6K
2
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
15
27
39
51
59
72
88
100
7
1
2
107
108
120
106
CPS
125
124
123
122
121
118
R0
119
R1
6
X0
5
X1
3
4
92
SDA
91
SCL
99
PC0
98
PC1
97
PC2
116
115
114
113
112
94
95
101
102
104
105
+3VS
1
C696
2
4.7U_0805_10V4Z
1 2
R715 1K_0402_5%
1 2
R716
6.34K_0603_1%
12
X3
24.576MHz_16P_3XG-24576-43E1
30ppm
1 2
C700
0.1U_0402_10V6K
SDA_1394
SCL_1394
XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-
+3VS
D D
PCI_AD[0..31]<26,29,31,34,36,43>
C C
PCI_CBE#3<26,31,34,36,43>
PCI_CBE#2<26,31,34,36,43>
PCI_CBE#1<26,31,34,36,43>
PCI_CBE#0<26,31,34,36,43>
CLK_PCI_1394<26>
PCI_GNT#0<26>
PCI_REQ#0<26>
ID: AD16
PCI_FRAME#<26,31,34,36,43>
PCI_IRDY#<26,31,34,36,43>
PCI_TRDY#<26,31,34,36,43>
PCI_DEVSEL#<26,31,34,36,43>
PCI_STOP#<26,31,34,36,43>
PCI_PERR#<26,31,34,36,43>
PCI_PIRQA#<10,17,26,31,36>
PCI_SERR#<26,31,34,36,43>
PCI_PAR<26,31,34,36,43>
PCI_CLKRUN#<26,31,34,36,43>
B B
PCI_RST#<11,26,30,31,34,36,43,46>
CLK_PCI_1394
PCI_AD16
PCI_AD[0..31]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1 2
R717 100_0402_5%
U42
84
PCI_AD0
82
PCI_AD1
81
PCI_AD2
80
PCI_AD3
79
PCI_AD4
77
PCI_AD5
76
PCI_AD6
74
PCI_AD7
71
PCI_AD8
70
PCI_AD9
69
PCI_AD10
67
PCI_AD11
66
PCI_AD12
65
PCI_AD13
63
PCI_AD14
61
PCI_AD15
46
PCI_AD16
45
PCI_AD17
43
PCI_AD18
42
PCI_AD19
41
PCI_AD20
40
PCI_AD21
38
PCI_AD22
37
PCI_AD23
32
PCI_AD24
31
PCI_AD25
29
PCI_AD26
28
PCI_AD27
26
PCI_AD28
25
PCI_AD29
24
PCI_AD30
22
PCI_AD31
34
PCI_C/BE3
47
PCI_C/BE2
60
PCI_C/BE1
73
PCI_C/BE0
16
PCI_CLK
18
PCI_GNT
19
PCI_REQ
36
PCI_IDSEL
49
PCI_FRAME
50
PCI_IRDY
52
PCI_TRDY
53
PCI_DEVSEL
54
PCI_STOP
56
PCI_PERR
13
PCI_INTA/CINT
21
PCI_PME/CSTSCHG
57
PCI_SERR
58
PCI_PAR
12
PCI_CLKRUN
85
PCI_RST
VDDP20VDDP35VDDP48VDDP62VDDP
TSB43AB21
/(TSB43AB22)
PCI BUS INTERFACE
87
78
BIAS CURRENT
OSCILLATOR
FILTER
EEPROM 2 WIRE BUS
POWER CLASS
PHY PORT 1
G_RST# connect to PCIRST#
CLK_PCI_1394
12
R726
@10_0402_5%
1
C703
@10P_0402_25V8K
2
RP142
1 8
2 7
3 6
4 5
220_0804_8P4R_5%
** GPIO2 and GPIO3 defaults as an input
and if it is not implemented, it is
recommended that it be pulled low to
ground with a 220 ohm resistor.
SDA_1394
SCL_1394
14
G_RST
89
GPIO3
90
GPIO2
TSB43AB21_PQFP128
PLLGND18REG_EN9AGND
AGND
109
110
0.1U_0402_10V6K
AGND
AGND
AGND
AGND
AGND
DGND17DGND23REG1830DGND33DGND44DGND55DGND64DGND68DGND75DGND83REG1893DGND
111
117
126
127
128
C704
1
2
C683
0.1U_0402_10V6K
2
L44
BLM21A601SPT_0805
1 2
1
C697
2
0.01U_0402_16V7K
Near 1394 IC
1 2
C698 22P_0402_25V8K
1 2
C699 22P_0402_25V8K
EEPROM cancel,
need System
Support
1
C684
0.1U_0402_10V6K
2
+3VS
1
C685
0.1U_0402_10V6K
2
C702
220P_0402_50V7K
1
C686
0.1U_0402_10V6K
2
+3VS
1
C691
1000P_0402_50V7K
2
12
R720
56.2_0402_1%
12
R722
56.2_0402_1%
1
2
Close Chip
1
C690
0.1U_0402_10V6K
2
1
C695
1000P_0402_50V7K
2
CLOSE CHIP
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
IEEE 1394 CONTROLLER
LA-1811
星期四
07, 2003
八月
0.7
35 66,
1
Page 36
1
2
3
4
5
R1060 NEC@0_0402_5%
+3VS
+3V
1 1
2 2
3 3
4 4
PCI_AD[0..31]<26,29,31,34,35,43>
CLK_PCI_USB20
12
R1028
@10_0402_5%
C915
@15P_0402_50V8J
PCI_CBE#[0..3]<26,31,34,35,43>
PCI_AD23
PCI_CLKRUN#<26,31,34,35,43>
PCI_REQ#3<26,43>
PCI_REQ#4<26,43>
PCI_GNT#3<26,43>
PCI_GNT#4<26,43>
PCI_AD[0..31]
PCI_CBE#[0..3]
PCI_PAR<26,31,34,35,43>
PCI_FRAME#<26,31,34,35,43>
PCI_IRDY#<26,31,34,35,43>
PCI_TRDY#<26,31,34,35,43>
PCI_STOP#<26,31,34,35,43>
R1112 NEC@100_0402_5%
1 2
PCI_DEVSEL#<26,31,34,35,43>
PCI_PERR#<26,31,34,35,43>
PCI_SERR#<26,31,34,35,43>
PCI_PIRQA#<10,17,26,31,35>
PCI_PIRQC#<26,43>
PCI_PIRQD#<26,34>
CLK_PCI_USB20<26>
G_RST#<31,32,46>
USB20_PME#<31,34,43,46,47>
USB_SMI#<27>
+3V
R1041 NEC@1.5K_0402_5%
1 2
R1042 NEC@1.5K_0402_5%
1 2
R1043 NEC@1.5K_0402_5%
1 2
PCI_RST#<11,26,30,31,34,35,43,46>
PCI_CLKRUN#
R1047 NEC@0_0402_5%
1 2
R1048 @0_0402_5%
1 2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#3
PCI_GNT#4
R1050 @0_0402_5%
1 2
R1051 NEC@0_0402_5%
1 2
R1052 @0_0402_5%
1 2
R1053 NEC@0_0402_5%
1 2
1 2
R1061 @0_0402_5%
1 2
U54
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18 USB20_NEC_P1+_R
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQD#
CLK_PCI_USB20
A6
AD31
B6
AD30
C5
AD29
A5
AD28
C4
AD27
B5
AD26
A4
AD25
B4
AD24
C1
AD23
C2
AD22
D2
AD21
D1
AD20
D3
AD19
E1
AD18
E3
AD17
F2
AD16
J1
AD15
J2
AD14
K3
AD13
K1
AD12
L3
AD11
K2
AD10
L1
AD9
L2
AD8
M1
AD7
N3
AD6
M3
AD5
N4
AD4
P4
AD3
N5
AD2
P5
AD1
M5
AD0
C3
CBE3#
F1
CBE2#
J3
CBE1#
M2
CBE0#
J4
PAR
F3
FRAME#
F4
IRDY#
G1
TRDY#
G3
STOP#
B3
IDSEL
G2
DEVSEL#
C6
REQ0#
D6
GNT0#
H2
PERR#
H1
SERR#
C7
INTA#
B7
INTB#
A7
INTC#
A8
PCLK
B8
VBBRST#
D9
PME#
L6
SMI#
L7
LEGC
P6
N.C.
M6
N.C
C9
VCCRST#
N6
CRUN#
PCI_REQ#
PCI_GNT#
+3V +3V_USB20
VDD
N10
D7
G12
F13
D13
H4
VDD
VDD
VDD
VDD
VDD
H3
M4
VDD_PCI
VDD_PCI
C8
VDD_PCI
P2
P3
P12
A13
A12
A3
E2
N8
L13
J13
H13
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
USB 2.0 CONTROLLER
uPD720101F1-EA8
FBGA144
VSS
VSS
VSS
VSS
VSS
B1
N1
P10
N14
H14
NEC@0.1U_0402_10V6K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
B2
N2
B14
L12
B13
N13
M11
C919
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
G4
J11
F11
D12
H12
+3V +3V_USB20
NEC@0.1U_0402_10V6K
1
2
P13
1
C920
C921
2
NEC@0.1U_0402_10V6K
N12
AVDD
AVDD
AVSS
AVSS
NEC@UPD720101F1-EA8_FBGA144
M12
1
2
L9
XT1/SCLK
P8
XT2
M14
RSDM1
M13
DM1
L14
DP1
K13
RSDP1
K14
RSDM2
K12
DM2
J14
DP2
J12
RSDP2
H11
RSDM3
G11
DM3
G13
DP3
G14
RSDP3
F12
RSDM4
F14
DM4
E12
DP4
E14
RSDP4
E13
RSDM5
D14
DM5
C13
DP5
C14
RSDP5
P11
RREF
N11
AVSS(R)
B12
OCI1
B11
OCI2
B10
OCI3
A10
OCI4
B9
OCI5
C12
PPON1
A11
PPON2
C11
PPON3
C10
PPON4
A9
PPON5
M8
NTEST1
M7
SMC
P7
AMC
N7
TEB
L8
TEST
M10
NANDTEST
M9
SRCLK
N9
SRDTA
P9
SRMOD
NEC@0.1U_0402_10V6K
1
C923
C922
2
NEC@0.1U_0402_10V6K
C964
NEC@16P_0603_50V8J
USB20_NEC_P0-_R
USB20_NEC_P0USB20_NEC_P0+
USB20_NEC_P0+_R
USB20_NEC_P1-_R
USB20_NEC_P1USB20_NEC_P1+
USB20_NEC_P2-_R
USB20_NEC_P2USB20_NEC_P2+
USB20_NEC_P2+_R
USB20_NEC_P3-_R
USB20_NEC_P3USB20_NEC_P3+
USB20_NEC_P3+_R
USB20_NEC_P4-_R
USB20_NEC_P4USB20_NEC_P4+
USB20_NEC_P4+_R
NEC@9.1K_0402_1%
R1038
OVCUR_USB20#0
OVCUR_USB20#1
OVCUR_USB20#3
OVCUR_USB20#4
1 2
R1045 NEC@1.5K_0402_5%
1 2
R1046 @1.5K_0402_5%
R1127
NEC@1.5K_0402_5%
1 2
NEC@10U_0805_10V4Z
1
1
C924
2
2
NEC@10U_0805_10V4Z
NEC@30MHZ_30PPM
Y7
1 2
1
NEC@100_0402_5%
2
R1025 NEC@36_0603_1%
R1026 NEC@36_0603_1%
R1027 NEC@42.2_0603_1%
R1029 NEC@42.2_0603_1%
R1030 NEC@42.2_0603_1%
R1031 NEC@42.2_0603_1%
R1032 NEC@42.2_0603_1%
R1033 NEC@42.2_0603_1%
R1034 NEC@42.2_0603_1%
R1035 NEC@42.2_0603_1%
+3V_USB20
1
C916
@0.1U_0402_10V6K
2
12
1
C917
@0.1U_0402_10V6K
2
R1039 NEC@10K_0402_5%
R1040 NEC@10K_0402_5%
1
C925
2
12
R1105
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PIR BOM 92.07.30
OVCUR_USB20#0 <44>
OVCUR_USB20#1 <44>
1 2
1 2
+3V
+3V
R1049
1 2
NEC@0_0603_5%
R1054
NEC@0_0603_5%
1 2
U55
8
VCC
7
WC
6
SCL
5
SDA
@AT24C02N-10SC-2.7_SO8
NEC@0.1U_0402_10V6K
C926
Note: PLACE CLOSE TO U54 .
For NEC USB2.0 only .
L
1
C965
NEC@16P_0603_50V8J
2
R1024 @0_0402_5%
1 2
USB20_NEC_P0- <44>
USB20_NEC_P0+ <44>
USB20_NEC_P1- <44>
USB20_NEC_P1+ <44>
USB20_NEC_P2- <44>
USB20_NEC_P2+ <44>
USB20_NEC_P3- <44>
USB20_NEC_P3+ <44>
USB20_NEC_P4- <41>
USB20_NEC_P4+ <41>
+3V
1
C918
@0.1U_0402_10V6K
GND
1
C927
2
NEC@0.1U_0402_10V6K
1
A0
2
A1
3
A2
4
NEC@10U_0805_10V4Z
1
C928
2
2
1
2
Note: PLACE CLOSE TO U54 .
L
For NEC USB2.0 only .
USB20_NEC_P0USB20_NEC_P0+
USB20_NEC_P1USB20_NEC_P1+
USB20_NEC_P2USB20_NEC_P2+
USB20_NEC_P3USB20_NEC_P3+
USB20_NEC_P4USB20_NEC_P4+
1
C929
NEC@10U_0805_10V4Z
2
R1036 NEC@15K_0402_5%
R1037 NEC@15K_0402_5%
NEC@15K_1206_8P4R_5%
NEC@15K_1206_8P4R_5%
1 2
1 2
RP147
1 8
2 7
3 6
4 5
RP148
1 8
2 7
3 6
4 5
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
NEC uPD720101 - USB2.0 Controller
星期五 八月
LA-1811
5
0.7
of
36 66, 08, 2003
Page 37
A
+3VALW
+3VALW
12
R729
@100K_0402_1%
1 1
2 2
3 3
4 4
BEEP#<46>
CDROM_L<30>
CDROM_R<30>
CD_AGND<30>
MD_SPK<44>
14
U18B
4
P
A
6
O
5
B
G
SN74LVC32APWLE_TSSOP14
7
R748 4.7K_0402_5%
R749 4.7K_0402_5%
1 2
R751 4.7K_0402_5%
R752 4.7K_0402_5%
1 2
R755 2.7K_0402_5%
1 2
R757 2.7K_0402_5%
12
R761 @0_0402_5%
R762 @4.7K_0402_5%
1 2
1 2
1 2
1 2
1 2
12
1 2
JOPEN6
PIR BOM & LAYOUT 92.07.30
12
JOPEN7
12
JOPEN8
12
R765
@0_1206_5%
R1165
@0_1206_5%
R1166
@0_1206_5%
R1167
0_1206_5%
R1168
0_1206_5%
GND
A
R731
1 2
10K_0402_1%
0.22U_0603_10V7K
PCM_SPK#<31>
@0.1U_0402_10V6K
SB_SPKR<27>
12
12
GNDA
B
C979
GNDA <38,41>
B
C
+3VALW
14
U45A
P
1
1
2
0.1U_0402_16V4Z
G
SN74LVC14APWLE_TSSOP14
C713
7
+3VALW
14
13
1
7
2
+3VALW
14
5
7
CDROM_R_L
CDROM_R_R
CD_GNA
MIC1<38>
MIC2<38>
MD_SPKR MD_SPKRC
C747
C712
O2I
U32F
P
O12I
G
SN74LVC14APWLE_TSSOP14
U45C
P
O6I
G
SN74LVC14APWLE_TSSOP14
2
C905
1
@0.1U_0402_16V4Z
12
1U_0603_10V6K
C721
1U_0603_10V6K
C722
1U_0603_10V6K
CONA#<41,46>
HPS<38>
@0.1U_0402_16V4Z
2
2
C749
1
1
1 2
12
12
1 2
+3VS
C
R732
1 2
560_0402_5%
R739
560_0402_5%
R741
560_0402_5%
@10K_0402
MUTE_LED<38,44>
+5VAMP_CODEC
2
B
12
R742
G
2
Q101 2N7002_SOT23
S
C734 2.2U_0603_6.3V4Z
1 2
C735 2.2U_0603_6.3V4Z
1 2
C736 2.2U_0603_6.3V4Z
1 2
C737 1U_0603_10V6K
1 2
C904 1U_0603_10V6K
1 2
C742 0_0402_5%
1 2
AC97_RST#<27,44>
AC97_SYNC<27,29,44>
AC97_SDOUT<27,29,44>
SPDIFO<41>
R1103
@0_0402_5%
SPDIF_OUT<27,29>
@4.7K_0402_5%
PIR LAYOUT 92.07.30
12
R733
10K_0402_1%
C714 1U_0603_10V6K
12
R735
10K_0402_1%
MONO_IN
1 2
39K_0603_1%
1
C
Q56
E
2SC2411K_SOT23
3
D46
RB751V_SOD323
2 1
MONO_INR
13
D
R766 4.7K_0402_5%
1 2
R767 4.7K_0402_5%
1 2
12
R770
1 2
D
12
R1063
R746
2.2K_0402_5%
12
CDROM_RC_L
CDROM_RC_R
CDGNDA
R763 33_0402_5%
1 2
R764 33_0402_5%
1 2
L99
1 2
CHB1608B121_0603
R769
0_0402_5%
R771
4.7K_0402_5%
1 2
D
E
W=40Mil
+5VS
1
1
2
2
0.1U_0402_10V6K
1
2
1
C728
0.1U_0402_10V6K
2
LINE_OUTL
LINE_OUTR
MDMIC
C731 1U_0603_25V4Z
R750 33_0402_5%
R753 33_0402_5%
CODEC_REF
AFILT1
AFILT2
AFILT3
AFILT4
C719
MONO_INRMONO_IN1
1 2
1U_0603_25V4Z
R738
1 2
10K_0402_5%
1
C723
0.1U_0402_10V6K
2
2
C727
0.1U_0402_10V6K
1
38
AVDD125AVDD2
43
AVDD434AVDD3
LINE_OUT_L
LINE_OUT_R
MONO_OUT
HP_LOUT_L
HP_LOUT_R
SDATA_IN
VREFOUT
E
U47
14
AUX_L
15
AUX_R
16
JS1
17
JS0
23
LINE_IN_L
24
LINE_IN_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1
22
MIC2
13
PHONE
11
RESET#
10
SYNC
5
SDATA_OUT
45
ID0
46
ID1
47
EAPD
48
12
SPDIFO
4
DVSS1
7
DVSS2
AD1981B_LQFP48
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4.7U_0805_10V4Z
+5VAMP_CODEC
1
2
9
DVDD11DVDD2
BIT_CLK
XTL_IN
XTL_OUT
VREF
AFILT1
AFILT2
AFILT3
AFILT4
NC
NC
AVSS1
AVSS2
AVSS3
AVSS4
C715
C724
0.1U_0402_10V6K
35
36
37
39
41
6
8
2
3
28
27
29
30
31
32
12
42
26
40
44
33
F
10K_0402_5%
C716
+5VAMP_CODEC
C725
0.1U_0402_10V6K
1
2
1 2
12
12
C744
C750
C751 270P_0402_50V7K
C752 270P_0402_50V7K
4
12
2
R956
8
1 2
1
2
C729
0.1U_0402_10V6K
LINE_OUTL <38>
LINE_OUTR <38>
L_HP <38>
R_HP <38>
1 2
1 2
1 2
1 2
F
U46
VIN
DELAY
ERROR7CNOISE
SD
SI9182DH-AD_MSOP8
R740
C726
10U_0805_6.3V6M
1
2
270P_0402_50V7K
270P_0402_50V7K
VOUT
SENSE or ADJ
GND
VDDA_CODEC
0_0805_5%
L98
1 2
CHB1608B121_0603
C730
10U_0805_10V4Z
MD_MIC <44>
AC97_BITCLK <27,44>
AC97_SDIN0 <27>
5
6
1
3
R754
AUD_REF
G
R736
1 2
12
30K_0603_1%
1
R737
C720
10K_0603_1%
2
0.01U_0402_16V7K
+3VS
CLK_14M_CODEC
12
0_0402_5%
1
C745
1U_0603_10V6K
2
VDDA_CODEC
1
C717
4.7U_0805_10V4Z
2
12
R758
@10_0402_5%
C743 @15P_0402_50V8J
1
C746
0.1U_0402_10V6K
2
H
1
C718
0.1U_0402_10V6K
2
CLK_14M_CODEC <24>
R767 R766 FREQ. SEL
X
Stuff
X
Title
Size Document Number Rev
LA-1811
Custom
Date: Sheet
星期二 九月
G
X
24.576MHZ
Stuff
Stuff
14.318MHZ
48MHZ
Compal Electronics, Inc.
AC97 CODEC
37 66, 02, 2003
H
Crystal
External
External
0.7
of
Page 38
A
B
C
D
E
+5VAMP+5VAMPP
0.1U_0402_10V6K
1
PVDD2
GAIN0
GAIN1
ROUT+
ROUT-
LOUT+
LOUT-
BYPASS
C890
NC
1
2
U52
2
3
18
14
4
8
12
10
C891
2
SPKR+
SPKR-
SPKL+
SPKL-
2
C897
0.47U_0603_10V7K
1
1 1
C893
1 2
0.047U_0603_10V7K
C894 0.1U_0402_16V7K
LINE_OUTR<37>
LINE_OUTL<37>
2 2
1 2
C896 0.1U_0402_16V7K
1 2
EC_MUTE#<46>
C895
1 2
R975 0_0402_5%
LINE_C_OUTR
0.047U_0603_10V7K
LINE_C_OUTL
1 2
7
17
9
5
19
RIN+
RIN-
LIN+
LIN-
SHUTDOWN
16
VDD
20
10U_0805_10V3M
15
6
PVDD1
GND41GND311GND213GND1
TI6017A2_TSSOP20
1 2
0_1206
1
C892
2
0.1U_0402_10V6K
L57
R971
@100K_0402_5%
R973
100K_0402_5%
R_HP<37>
L_HP<37>
12
100K_0402_5%
12
@100K_0402_5%
C773 100U_D2_10VM
C774 100U_D2_10VM
R734
1 2
+5VS +5VAMP
0_1206_5%
10 dB
R972
R974
+
1 2
+
1 2
+5VAMP
12
12
INTSPK_CR+
INTSPK_CL+
SPKL+
SPKLSPKR+
SPKR-
12
R1164
1K_0402_5%
L100 BLM11A121SPT_0805
1 2
L101 BLM11A121SPT_0805
1 2
L102 BLM11A121SPT_0805
1 2
L103 BLM11A121SPT_0805
1 2
47P_0402_50V8J
12
R1158
1K_0402_5%
C761
1
47P_0402_50V8J
2
1
C762
2
47P_0402_50V8J
JP34
1
1
2
2
3
3
4
1
C764
47P_0402_50V8J
2
4
ACES_85205-0400
1
C763
2
Gain Settings
GAIN0
3 3
AUDIO CONNECTOR
ACES_88028-1600_16P
D78
RB751V_SOD323
HPS <37>
JP41
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
+5VS
VOLBTN+# <41,44,46>
VOLBTN-# <41,44,46>
WIRELESS_BTN <42,46>
WIRELESS_LED# <42,43,44>
MUTE_LED <37,44>
+3VS
CODEC_REF
MIC1<37>
MIC2<37>
INTSPK_CR+
DOCK_LOUT_L<41>
DOCK_LOUT_R<41>
INTSPK_CL+
2 1
GAIN1
0
0
0
1
1 0
1
1
HEADPHONE OUT/LINE OUT
Av(inv)
6 dB
10 dB
15.6 dB
21.6 dB
4 4
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
AMP & Audio Jack
星期二 九月
LA-1811
E
0.7
of
38 66, 02, 2003
Page 39
5
D D
+3VS
0.1U_0402_10V6K
1
C784
0.1U_0402_10V6K
C C
C785
2
0.1U_0402_10V6K
+3VS
RP151 4.7K_0804_8P4R_5%
RP152 4.7K_0804_8P4R_5%
R1108
R1109
1
C786
2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
4.7K_0402_5%
4.7K_0402_5%
1
1
C787
0.1U_0402_10V6K
2
2
CTS1#
DSR1#
DCD1#
RI1#
CTS2#
DSR2#
DCD2#
RI2#
SIN1
12
SIN2
12
PIR BOM & LAYOUT 92.07.30
B B
+3VS+3VS+3VS
CLK_PCI_SIO CLK_LPC_48M
R794
1 2
1 2
@10K_0402
R797
10K_0402_1%
RTS1#
R792
@10K_0402
1 2
DTR1# SOUT1
R795
10K_0402_1%
1 2
R793
@10K_0402
1 2
R796
2.2K_0402_5%
1 2
LPC_DRQ#1<26>
4
R783
@4.7K_0402_5%
10K_0402
FIR@10K_0402
12
R790
@33_0402
12
C788
@15PF_0402
+3VS
12
R1173
R1174
NB_RST#<8,17,26>
CLK_PCI_SIO<26>
SIRQ<26,31,46>
LPC_FRAME#<26,46>
LPC_AD0<26,46>
LPC_AD1<26,46>
LPC_AD2<26,46>
LPC_AD3<26,46>
+3VS
+3VS
R787 4.7K_0402_5%
1 2
FIR_DET#
1 2
12
R791
@10_0402_5%
1
C789
@10P_0402_50V8J
2
R784
1 2
MDC_DET#<44>
CLK_PCI_SIO
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
@10K_0402
1 2
U51
28
19
21
20
27
26
25
24
23
128
127
126
125
124
123
122
121
106
103
104
107
108
109
110
111
113
114
115
116
117
118
94
93
92
91
89
88
87
86
85
84
83
82
81
80
79
78
77
76
74
73
72
71
70
69
68
67
66
LRESET#
PCICLK
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
JAB1/GP10
JBB11/GP11
JACX/GP12
JBCX/GP13
JBCY/GP14
JACY/GP15
JBB2/GP16
JAB2/GP17
VREF
UIC1
UIC2
UIC3
UIC4
UIC5
DTDN
DTDP
FANIO2/GP21
FANIO1/DTEST
FANOUT2/GP20
FANOUT1
OVTEMP#
BEEP
XD0/GP30
XD1/GP31
XD2/GP32
XD3/GP33
XD4/GP34
XD5/GP35
XD6/GP36
XD7/GP37
XA0/GP40
XA1/GP41
XA2/GP42
XA3/GP43
XA4/GP44
XA5/GP45
XA6/GP46
XA7/GP47
XA8/GP50
XA9/GP51
XA10/GP52
XA11/GP53
XA12/GP54
XA13/GP55
XA14/GP56
XA15/GP57
XA16/GP60
XA17/GP61
XA18/GP62
3
+3VS
HWMVCC
105
5
75
22
VCC
VCC45VCC
VCC
VCCA
LPC
FDD
GAME PORT
OVOLT/MSO/DSEL1
TRK00#/PD1
WRTPRT#/PD2
RDATA#/PD3
DSKCHG#/PD4
HARDWARE MONITOR
WGATE#/SLCT
WDATA#/PE
MTR1#/BUSY
PARALLEL PART
HDSEL#/ERR#
STEP#/SLCTIN#
DRVDEN0/AUTOFD#
IR
GP24/IRRX1
SERIAL POART 1
GP71/SMBDT/DCD2#
GP72/SMBCK/SOUT2
GP73/VID0/SIN2
GP74/VID1/DTR2#
GP75/VID2/RTS2#
GP76/VID3/DSR2#
GP77/VID4/CTS2#
SERIAL POART 2
GP70/SCLK/ITMOFF/RI2#
GP22/ITMOFF//OVOLT/PLED
GP23/ATEST/OVFAN/COPEN
OVFAN/MSI/WDTO
GP25/MEMW#
GP26/MEMR#
GP27/ROMCS#
GNDD18GNDD60GNDD90GNDA
GNDD
99
112
INDEX#
MTRA#
DRVB#
DRVA#
MTRB#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
DSEL0#
INDEX#PD0
PD5
PD6
PD7
DS1#/ACK#
DIR#/PINIT#
STB#
IRRX
IRTX
DCD1#
DSR1#
SIN1
RTS1#
SOUT1
CTS1#
DTR1#
RI1#
CLKIN
SMI#
VT1211_LQFP128
2
3
4
6
7
8
9
10
11
12
13
14
15
16
1
120
42
41
40
39
38
37
36
35
29
30
31
32
33
34
43
44
46
64
65
100
53
48
51
49
52
47
50
54
62
61
59
58
57
56
55
63
102
101
119
17
98
97
96
95
C781
10U_0805_10V4Z
INDEX#
TRACK0#
WP#
RDATA#
DSKCHG#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTSLCTIN#
LPTINIT#
LPTAFD#
LPTSTB#
DCD1#
DSR1#
SIN1
RTS1#
SOUT1
CTS1#
DTR1#
RI1#
DCD2#
SOUT2
SIN2
DSR2#
CTS2#
RI2#
CLK_LPC_48M
HWMVCC
1
1
2
2
INDEX# <40>
MTR0# <40>
DRV0# <40>
FDDIR# <40>
STEP# <40>
WDATA# <40>
WGATE# <40>
TRACK0# <40>
WP# <40>
RDATA# <40>
HDSEL# <40>
DSKCHG# <40>
3MODE# <40>
LPD0 <40>
LPD1 <40>
LPD2 <40>
LPD3 <40>
LPD4 <40>
LPD5 <40>
LPD6 <40>
LPD7 <40>
LPTSLCT <40>
LPTPE <40>
LPTBUSY <40>
LPTACK# <40>
LPTERR# <40>
LPTSLCTIN# <40>
LPTINIT# <40>
LPTAFD# <40>
LPTSTB# <40>
IRRX <45>
IRTXOUT <45>
IRMODE <45>
DCD 1# <41>
DSR1# <41>
SIN1 <41>
RTS1# <41>
SOUT1 <41>
CTS1# <41>
DTR1# <41>
RI1# <41>
CLK_LPC_48M <24>
2
L55
1 2
0_0805_5%
C782
0.1U_0402_10V6K
1
+3VS
A A
Base address 1:2Eh/2Fh
Base address 0:4Eh/4Fh 1:Test Mode
0:Normal Opreation
Super I/O strapping for VT1211
5
0: Enable ROM I/F as GPIO
1:Enable Flash Rom
W
R798
SOUT2
1 2
For Winbond 48M strapping
4.7K_0402_5%
4
+3VS
THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Compal Electronics, Inc.
Title
LPC SUPER I/O VIA VT1211
Size Document Number Re v
LA-1811
Date: Sheet
星期四 八
07, 2003
月
1
of
39 66,
0.7
Page 40
5
4
3
2
1
+5V_PRN
1
D D
C C
B B
A A
4.7U_0805_10V4Z
C790
2
LPTAFD#<39>
LPTERR#<39>
LPTINIT#<39>
LPTSLCTIN#<39>
+5V_PRN
+5V_PRN
Parallel Port
1SS355_SOD323
1 2
12
LPTACK#<39>
LPTBUSY<39>
LPTPE<39>
LPTSLCT<39>
10
9
8
7
6
10
LPTSLCT
9
LPTPE
8
LPTBUSY
7
LPTACK#
6
FD3
FD2
FD1
FD0
FD7
FD6
FD5
FD4
D48
+5V_PRN
FD7
FD6
FD5
FD4
+5V_PRN
1
C791
0.1U_0402_10V6K
2
LPTSTB#<39>
LPTAFD# AFD/3M#
LPTINIT#
LPTSLCTIN#
LPD[0..7]<39>
FD0
1
FD1
2
FD2
3
FD3
4
5
SLCTIN#
PRNINIT#
LPTERR#
AFD/3M#
LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4
1
2
3
4
5
+5VS
LPTSTB#
R800 33_0402_5%
R801
33_0402_5%
R802 33_0402_5%
1 2
R803 33_0402_5%
1 2
LPD[0..7]
RP120
2.7K_1206_10P8R_5%
RP122
2.7K_1206_10P8R_5%
RP123
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8 9
68_1206_16P8R_5%
+5V_PRN
w=10mils
12
12
R799
2.7K_0402_5%
PWRPRN
w=10mils
FD0
LPTERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3
FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
AFD/3M#
LPTERR#
PRNINIT#
SLCTIN#
220P_1206_8P4C_50V8K
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
220P_1206_8P4C_50V8K
FD3
FD2
FD1
FD0
220P_1206_8P4C_50V8K
FD7
FD6
FD5
FD4
220P_1206_8P4C_50V8K
C792
1 2
47P_0402_50V8J
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
JP39
SUYIN_070536FR025S204AU
CP11
CP12
CP13
CP14
81
7
6
81
7
6
81
7
6
81
7
6
2
3
4 5
2
3
4 5
2
3
4 5
2
3
4 5
+5VS
INDEX#
DRV0#
DSKCHG#
2
MTR0#
3
FDDIR#
4 5
220P_1206_8P4C_50V8K
3MODE#
STEP#
2
WDATA#
3
WGATE#
4 5
220P_1206_8P4C_50V8K
TRACK0#
WP#
2
RDATA#
3
HDSEL#
4 5
220P_1206_8P4C_50V8K
0.1U_0402_10V6K
1
C793
2
FDD CONN.
C975
1 2
220P_0402_25V8K
C976
1 2
220P_0402_25V8K
CP15
81
7
6
CP16
81
7
6
CP17
81
7
6
+5VS
1
C794
0.1U_0402_10V6K
2
RDATA#
WDATA#
R1159
330_0402_5%
R1160
330_0402_5%
INDEX#<39>
DRV0#<39>
DSKCHG#<39>
MTR0#<39>
FDDIR#<39>
3MODE#<39>
STEP#<39>
WDATA#<39>
WGATE#<39>
TRACK0#<39>
RDATA#<39>
HDSEL#<39>
DSKCHG#
INDEX#
WP#
TRACK0#
+5VS
JP38
1
INDEX#
DRV0#
DSKCHG#
MTR0#
FDDIR#
3MODE#
STEP#
WDATA#
WGATE#
TRACK0#
WP#<39>
+5VS
WP#
RDATA#
HDSEL#
+5VS
RP119
1 8
2 7
3 6
4 5
330_0804_8P4R_5%
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
ACES_85201-2605
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Pallel port and FDD
Size Docu ment Number Rev
LA-1811 0.7
B
of
星期
, 02, 2003
Date: Sheet
二九月
1
40 66
Page 41
A
1 1
B
C
CONA#<37,46>
DOCK_PRESENT
12
2
R880
470_0402_5%
+3VALW
12
R879
10K_0402_5%
Q65
MMBT3904_SOT23
3 1
D
E
FM1
1
CF2
SPR 36 PIN For X7
JP40
R1131 1K_0603_5%
1 2
+5VS
2 2
RJ45_GND TRACE AT LEAST 20 MIL
R1141 200_0402_5%
VOLBTN-#,46>
3 3
1 2
1
2
USB20P4+<27>
USB20_NEC_P4-<36>
USB20_NEC_P4+<36>
C972
1000P_0402_50V7K
USB20P4-<27>
USB20P4USB20P4+
USB20_NEC_P4USB20_NEC_P4+
Note: PLACE CLOSE TO SPR PORT (JP40)
L
USB_VCCA
DOCK_PRESENT
TV_COMPS<11,17,48>
TV_LUMA<11,17,48>
TV_CRMA<11,17,48>
TV_GND<48>
RJ45_RXX-<34>
RJ45_RXX+<34>
RJ45_TXX-<34>
RJ45_TXX+<34>
R1090 ATI@0_0402_5%
1 2
R1091 ATI@0_0402_5%
1 2
R1092 NEC@0_0402_5%
1 2
R1093 NEC@0_0402_5%
1 2
TV_GND
USB4USB4+
33 34
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
35 36
BOSS137BOSS2
FOX_QL11183-C6HQ
38
USB4USB4+
R1139 @10K_0603_5%
DOCK_LOUT_L
DOCK_LOUT_R
SPDIFO
DOCKVINDOCKVIN
+3V
DOCK_LOUT_L <38>
DOCK_LOUT_R <38>
JACK_DET# <46>
SPDIFO <37>
SIN1 <39>
SOUT1 <39>
DCD1# <39>
DTR1# <39>RJ45_GND<34>
RI1# <39>
DSR1# <39>
RTS1# <39>
CTS1# <39>
R1161
1 2
R1140 200_0402_5%
1 2
1
C971
1000P_0402_50V7K
2
0_0805_5%
VOLBTN+# <38,44,46>
L
SPDIFO
1
C963
@0.01U_0402_50V7K
2
Note: PLACE CLOSE TO SPR PORT (JP40)
CF1
CF14
1
1
H1
HOLEA
1
H6
HOLEA
1
H11
HOLEA
1
H16
HOLEA
1
H21
HOLEA
1
H26
HOLEA
1
CF15
1
1
1
CF3
CF16
H2
HOLEA
H7
HOLEA
H12
HOLEA
H17
HOLEA
H22
HOLEA
H27
HOLEA
1
1
CF5
CF4
CF6
1
1
1
CF18
CF17
CF19
1
1
1
H3
H4
HOLEA
HOLEA
1
H8
HOLEA
1
H13
HOLEA
1
H18
HOLEA
1
H23
HOLEA
1
H28
HOLEA
1
H9
HOLEA
1
H14
HOLEA
1
H19
HOLEA
1
H24
HOLEA
1
1
1
1
1
1
1
1
FM3
FM2
FM5
1
CF8
CF21
H30
HOLEA
1
FM6
1
CF13
CF11
CF9
1
1
CF22
1
1
H31
HOLEA
CF10
CF23
1
CF12
1
1
1
1
CF25
CF24
1
1
CF27
CF26
1
1
1
FM4
CF7
1
1
CF20
1
1
H5
HOLEA
1
H10
HOLEA
1
H20
HOLEA
1
H25
HOLEA
1
USB_VCCA
@10U_0805_16V4Z_V1
1
1
1
C798
C800
0.1U_0402_10V6K
4 4
L56
1 2
KC FBM-L18-453215-900LMA90T_1812
1
C804
1000P_0402_50V7K
2
A
DOCKVINDC_IN
1
C805
1000P_0402_50V7K
2
B
2
2
C801
@1000P_0402_50V7K
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SPR Connector
星期四 八月
LA-1811
E
of
41 66, 07, 2003
0.7
Page 42
5
KSO16<46>
D D
C C
KSO16
FOR CARDREADER INDICATOR
( PAV /PRES )
PIR BOM 92.07.30
B B
CARD_LED#<31>
A A
CARD_LED#
12
WIRELESS_LED#<38,43,44>
5
1K_0402_5%
R1138
10K_0402_5%
2
4
SW3 PAV@TC010-PS11CET_5P
5
2
4
SW4 PAV@TC010-PS11CET_5P
5
2
4
SW5 PAV@TC010-PS11CET_5P
5
2
4
SW6 PAV@TC010-PS11CET_5P
5
2
4
SW7 TC010-PS11CET_5P
5
12
R1136
91_0402_5%
R1137
PAV@10K_0402_5%
Q116
2
MMBT3904_SOT23
3 1
WIRELESS_LED#
12
R1058
PAV@1K_0402_5%
1
3
1
3
1
3
1
3
1
3
R1057
@.1UF_0402
C842
D57
1
PRES_1520@12-21SYGC/S530-E1/TR8_GRN
D59
PAV@HSMB-C172 BLUE_0805
12
R889
PAV@91_0402_5%
21
D62
PAV@HSMB-C172 BLUE_0805
12
Q70
2
PAV@MMBT3904_SOT23
3 1
4
+3VS
12
R1014
10K_0402_5%
@.1UF_0402
C831
C809
1 2
1 2
@.1UF_0402
PRES_LEDVCC
2
3
PAV_LEDVCC
21
PAV_LEDVCC
PIR BOM 92.07.30
4
KSI0
KSI1
KSI2
FOR WIRELESS ON OFF
WIRELESS_BTN
FOR TP ON OFF
KSI3
C810
1 2
@.1UF_0402
C811
@.1UF_0402
1 2
1 2
CAPSLED#<46>
PIR BOM 92.07.30
FOR WIRLESS LED
( PAV )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
KSI0 <45,46>
KSI1 <45,46>
3 FOR
PROGRAMING
KSI2 <45,46>
WIRELESS_BTN <38,46>
KSI3 <45,46>
PIR BOM 92.07.30
3
2
E
B
C
1
1 2
Q71
PDTA114EK_SC59
R890
3
PWR_ACTIVE_PAV#<46>
FOR POWER BUTTON
BACKLIGHT ( PAV
)
PAV@PDTA114EK_SC59
PIR BOM 92.07.30
PWR_BACK#<46>
PRES@HSMG-C170_GRN_0805
D63
PRES_LEDVCC
21
D65
PAV_LEDVCC
21
PAV@HSMB-C172 BLUE_0805
91_0402_5%
PIR BOM 92.07.30
PRES_LEDVCC <44,46>
PAV_LEDVCC <44>
TP_OFF_LED#<46>
PWR_ACTIVE_PAV#
PWR_BACK#
2
B
C
1
Q62
3
E
R882
1 2
2
PWR_ACTIVE_PRES#<46>
3
2
E
B
PRES@PDTA114EK_SC59
C
1
R881 PAV@91_0402_5%
1 2
D53
21
PAV@HSMB-C172 BLUE_0805
D54
21
PAV@HSMB-C172 BLUE_0805
D55
21
PAV@HSMB-C172 BLUE_0805
Q66
PDTA114EK_SC59
27_0402_5%
PRES@HSMG-C170_GRN_0805
D61
D64
PAV@HSMB-C172 BLUE_0805
D92
PAV@HSMB-C172 BLUE_0805
3
2
E
B
C
1
1 2
2
Q69
PDTA114EK_SC59
R888
27_0402_5%
1
PAV@HSMB-C172 BLUE_0805
D52
21
PAV_LEDVCC
PAV_LEDVCC
PWR_ACTIVE_PRES#
2
B
Q117
3
FOR POWER BUTTON
E
BACKLIGHT ( PRES )
C
1
R1146 PRES@300_0402_5%
1 2
PIR BOM 92.07.30
21
D56
PRES@HSMG-C170_GRN_0805
FOR 3 PROGRAMING
PAV_LEDVCC
BUTTON BACKLIGHT
(PAV)
PRES@HSMG-C170_GRN_0805
D58
PRES_LEDVCC
NUMLED#<46>
PAV@HSMB-C172 BLUE_0805
3
2
E
21
21
21
PRES_LEDVCC
PAV_LEDVCC
B
C
1
R885
1 2
PIR BOM 92.07.30
Title
Size Docu ment Number Rev
B
Date: Sheet
Compal Electronics, Inc.
LED INDICATOR
, 07, 2003
四八月
LA-1811
星期
1
21
D60
PAV_LEDVCC
21
Q68
PDTA114EK_SC59
91_0402_5%
42 66
of
+5V
0.7
Page 43
A
B
C
D
E
1 1
WIRELESS_LED#<38,42,44>
WL_ON<44,46>
PCI_PIRQC#<26,36>
CLK_PCI_MINI<26>
PCI_REQ#3<26,36>
PCI_AD31<26,31,34,35,36>
PCI_AD29<26,31,34,35,36>
PCI_AD27<26,31,34,35,36>
PCI_AD25<26,31,34,35,36>
MINIPCI_AD22<44>
PCI_CBE#3<26,31,34,35,36>
PCI_AD23<26,31,34,35,36>
PCI_AD21<26,31,34,35,36>
PCI_AD19<26,31,34,35,36>
PCI_AD17<26,31,34,35,36>
PCI_CBE#2<26,31,34,35,36>
PCI_IRDY#<26,31,34,35,36>
PCI_CLKRUN#<26,31,34,35,36>
PCI_SERR#<26,31,34,35,36>
PCI_PERR#<26,31,34,35,36>
PCI_CBE#1<26,31,34,35,36>
PCI_AD14<26,31,34,35,36>
PCI_AD12<26,31,34,35,36>
PCI_AD10<26,31,34,35,36>
PCI_AD8<26,31,34,35,36>
PCI_AD7<26,31,34,35,36>
C280
0.1U_0402_10V6K
1
C269
+3VS
2
4.7U_0805_10V4Z
CLK_PCI_MINI
12
2 2
R302
@10_0402_5%
1
C275
@15P_0402_50V8J
2
0.1U_0402_10V6K
1
1
C270
2
2
1000P_0402_50V7K
C271
1
2
LAN RESERVED LAN RESERVED
D88 1N4148_SOT23
WL_ON
1 2
D89 RB751V_SOD323
TIP
21
W=40mils
CLK_PCI_MINI
MINIPCI_AD22
PCI_AD5<26,31,34,35,36>
PCI_AD3<26,31,34,35,36>
+5VS
PCI_AD1<26,31,34,35,36>
3 3
+5VS
W=30mils
C282
@1000P_0402_50V7K
W=30mils
2
1
JP12
KEY KEY
101
103
105
107
109
111
113
115
117
119
121
123
AMP_1318644-1
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101
103
105
107
109
111
113
115
117
119
121
123
RING
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
W=30mils
PCI_PIRQC#
W=40mils
W=40mils
MDM_PME#
MINIPCI_PME#
1 2
R301 100_0402_5%
PCI_AD18
PCI_AD22
PCI_AD18
R304 @10K_0402_5%
1 2
W=40mils
+5VS
PCI_GNT#4 <26,36>PCI_REQ#4<26,36>
+3VALW
PCI_RST# <11,26,30,31,34,35,36,46>
PCI_GNT#3 <26,36>
MDM_PME# <31,34,36,46,47>
MINIPCI_PME# <44>
PCI_AD30 <26,31,34,35,36>
PCI_AD28 <26,31,34,35,36>
PCI_AD26 <26,29,31,34,35,36>
PCI_AD24 <26,31,34,35,36>
IDSEL : AD18
PCI_AD22 <26,31,34,35,36>
PCI_AD20 <26,31,34,35,36>
PCI_PAR <26,31,34,35,36>
PCI_AD18 <26,31,34,35,36>
PCI_AD16 <26,31,34,35,36>
PCI_FRAME# <26,31,34,35,36>
PCI_TRDY# <26,31,34,35,36>
PCI_STOP# <26,31,34,35,36>
PCI_DEVSEL# <26,31,34,35,36>
PCI_AD15 <26,31,34,35,36>
PCI_AD13 <26,31,34,35,36>
PCI_AD11 <26,31,34,35,36>
PCI_AD9 <26,31,34,35,36>
PCI_CBE#0 <26,31,34,35,36>
PCI_AD6 <26,31,34,35,36>
PCI_AD4 <26,31,34,35,36>
PCI_AD2 <26,31,34,35,36>
PCI_AD0 <26,31,34,35,36>
+3VALW
1
C272
0.1U_0402_10V6K
2
1
C273
2
1000P_0402_50V7K
4.7U_0805_10V4Z
C284
4.7U_0805_10V4Z
+5VS
1
C276
2
+3VALW
1
C285
2
0.1U_0402_10V6K
1
C274
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C278
C277
2
0.1U_0402_10V6K
1000P_0402_50V7K
1
C286
2
C281
4.7U_0805_10V4Z
+3VS
1
2
1
2
1
2
4 4
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Mini PCI Slot
LA-1811
星期四 八月
0.7
of
43 66, 07, 2003
E
Page 44
C303
4.7U_0805_10V4Z
USB20P3-<27>
USB20P3+<27>
+3VS
2
1
1
2
C304
0.1U_0402_10V6K
1000P_0402_50V7K
C954
+3V
1
2
1
C955
0.1U_0402_10V6K
2
Front Board CONNECTOR
Pavilion only
PIR BOM & LAYOUT 92.07.30
VOLBTN+#<38,41,46>
BATLED_0#<45,46>
VOLBTN-#<38,41,46>
ACT_LED<45>
+5VALW
MUTE_LED<37,38>
PAV_LEDVCC<42>
PMLED_1#<45,46>
+3VS
+5VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Front Board CONNECTOR
PRESARIO only
L90 PRES@CHB1608B121_0603
1 2
L91 PRES@CHB1608B121_0603
1 2
L92 PRES@CHB1608B121_0603
1 2
L93 PRES@CHB1608B121_0603
1 2
L94 PRES@CHB1608B121_0603
1 2
+5VS
PMLED_1<45>
BATLED_0<45>
ACT_LED
PRES_LEDVCC<42,46>
TP CONNECTOR
+5V
L95 CHB1608B121_0603
1 2
L96
CHB1608B121_0603
TP_DATA<46>
TP_CLK<46>
1 2
1 2
L97 CHB1608B121_0603
USB KEY
R1079 0_0402_5%
1 2
R1080 0_0402_5%
1 2
Note: Place close to JP46
L
+5V
1000P_0402_50V7K
L79PAV@CHB1608B121_0603
L80PAV@CHB1608B121_0603
L81PAV@CHB1608B121_0603
L83PAV@CHB1608B121_0603
L84PAV@CHB1608B121_0603
L85PAV@CHB1608B121_0603
L86PAV@CHB1608B121_0603
10
11
L87PAV@CHB1608B121_0603
12
L88PAV@CHB1608B121_0603
13
L89PAV@CHB1608B121_0603
14
USB3USB3+
ACES_85201-0405
1
C300
2
MD_MIC<37>
+3V
AC97_SDOUT<27,29,37>
AC97_RST#<27,37>
JP42
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
PAV@ACES_85201-1405
JP45
1
2
3
4
5
6
7
8
PRES@ACES_85201-0805
JP44
8
7
6
5
4
3
2
1
ACES_87152-0807
WL_ON<43,46>
JP46
1
2
3
4
+3VS
MDC Conn.
1
C301
0.1U_0402_10V6K
2
C310
12
0.1U_0402_10V6K
+5V USB_VCCB
C311
12
0.1U_0402_10V6K
+3VS
R1055 10K_0402_5%
2
G
Q100
2N7002_SOT23
USB20P5+<27>
USB20P5-<27>
WIRELESS_LED#<38,42,43>
MINIPCI_AD22<43>
MINIPCI_PME#<43>
USB20_NEC_P3+<36>
USB20_NEC_P3-<36>
JP17
1
MONO_OUT/PC_BEEP
3
GND
5
AUXA_RIGHT
7
AUXA_LEFT
9
CD_GND
11
CD_RIGHT
13
CD_LEFT
15
GND
17
3.3Vaux
19
GND
21
3.3Vmain
23
AC97_SDATA_OUT
25
AC97_RESET#
27
GND
29
AC97_MSTRCLK
ACES_88021-3000
U13
5
VIN
4
ON#
2
GND
AATI4610GV-T1_SOT23_5
U14
5
VIN
4
ON#
2
GND
AATI4610GV-T1_SOT23_5
Note: PLACE CLOSE TO EACH USB PORT
L
1 2
13
D
S
L
D87 1N4148_SOT23
R1083 100_0402_5%
R1084 100_0402_5%
@0.1U_0402_10V6K
1
C298
2
@1000P_0402_50V7K
1
VOUT
3
SET
R809
4.7K_0603_1%
1
VOUT
3
SET
R810
4.7K_0603_1%
1
C299
2
AUDIO_PWDN
MONO_PHONE
Bluetooth Enable
GND
USB Data+
USB Data-
PRIMARY DN
GND
AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0
GND
AC97_BITCLK
USB_VCCA+5V
12
R893
330K_0402_5%
12
12
R894
560K_0402_5%
12
R895
330K_0402_5%
12
12
R896
560K_0402_5%
+5V
5Vd
BT CONNECTOR
+3VS
3
2
S
G
D
1
R981 ATI@0_0402_5%
1 2
R980 ATI@0_0402_5%
1 2
Note: Place close to JP43
1 2
1 2
1 2
R1082 NEC@0_0402_5%
1 2
R1081 NEC@0_0402_5%
1 2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VMDC
1 2
R319 @0_0805_5%
C302
2
4
6
8
10
12
14
R323 10K_0402_5%
16
18
20
22
24
26
28
30
1 2
R325 22_0402_5%
R326 22_0402_5%
+5VS
12
@1000P_0402_50V7K
MD_SPK <37>
12
12
R327
10_0402_5%
1 2
1
C305
22P_0402_25V8K
2
+3VS
R320
100K_0402_5%
1 2
+3V
MDC_DET# <39>
AC97_SYNC <27,29,37>
AC97_SDIN1 <27>
AC97_BITCLK <27,37>
RIGHT USB CONNECTOR 0
1
C812
0.47U_0603_10V7K
2
R1071 ATI@0_0402_5%
1 2
R1072 NEC@0_0402_5%
1 2
1
C832
1000P_0402_50V7K
2
1
C813
0.47U_0603_10V7K
2
R1075 ATI@0_0402_5%
1 2
R1076 NEC@0_0402_5%
1 2
1
C833
1000P_0402_50V7K
2
USB20_NEC_P0-<36>
USB20_NEC_P0+<36>
OVCUR#0 <27>
OVCUR_USB20#0 <36>
OVCUR#1 <27>
OVCUR_USB20#1 <36>
USB20P0-<27>
USB20P0+<27>
USB20P0USB20P0+
USB20_NEC_P0-
USB20_NEC_P0+
Note: PLACE CLOSE TO EACH USB PORT (JP18)
L
LEFT USB CONNECTOR 2
USB20P2-<27>
USB20P2+<27>
USB20_NEC_P2-<36>
USB20_NEC_P2+<36>
USB20P2USB20P2+
USB20_NEC_P2USB20_NEC_P2+
Note: PLACE CLOSE TO EACH USB PORT (JP19)
L
R976 ATI@0_0402_5%
R977 ATI@0_0402_5%
R1069 NEC@0_0402_5%
R1070 NEC@0_0402_5%
LEFT USB CONNECTOR 1
USB20P1-<27>
USB20P1+<27>
USB20_NEC_P1-<36>
SI2301DS_SOT23
Q99
BT_VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
USB5+
USB5-
USB5+
USB5-
JP43
1
2
3
4
5
6
7
8
ACES_85201-0805
BT_VCC
1
C957
10U_0805_10V3M
L
2
Note: Place close to JP43.1
USB20_NEC_P1+<36>
1
C958
0.1U_0402_10V6K
2
USB20P1+
USB20_NEC_P1USB20_NEC_P1+
Note: PLACE CLOSE TO EACH USB PORT (JP20)
L
RJ11 CONN.
FOXCONN_JM34613-L002-TR
JP16
3
@220PF_3KV_1808
C307
100U_D2_6.3VM
1 2
1 2
1 2
1 2
C312
100U_D2_6.3VM
R978 ATI@0_0402_5%
1 2
R979 ATI@0_0402_5%
1 2
R1073 NEC@0_0402_5%
1 2
R1074 NEC@0_0402_5%
1 2
C315
100U_D2_6.3VM
R982 ATI@0_0402_5%
1 2
R983 ATI@0_0402_5%
1 2
R1077 NEC@0_0402_5%
1 2
R1078 NEC@0_0402_5%
1 2
Title
Size Document Number Rev
Date: Sheet
5
3
5
6
446
112
2
JP47
TIP
1
12
C978
@220PF_3KV_1808
1
1
2
2
1
1
2
2
1
1
2
2
1
2
2
MOLEX_53398_0290
USB_VCCA
C309
1000P_0402_50V7K
USB0USB0+
USB_VCCB
C314
1000P_0402_50V7K
USB2USB2+
USB_VCCB
C317
1000P_0402_50V7K
USB1-USB20P1USB1+
12
W=40mils
1
+
C308
2
0.1U_0402_10V6K
W=40mils
1
+
C313
2
0.1U_0402_10V6K
W=40mils
1
+
C316
2
0.1U_0402_10V6K
MRING
C977
Compal Electronics, Inc.
MDC , Bluetooth & USB CONN.
星期四 八月
LA-1811
JP18
1
2
3
4
suyin_020167mr004s511zu_4p
JP19
1
2
3
4
suyin_020167mr004s511zu_4p
JP20
1
2
3
4
suyin_020167mr004s511zu_4p
44 66, 07, 2003
0.7
of
Page 45
5
INT_KBD CONN.
KSI[0..7]
KSO[0..15]
D D
C C
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
ACES_85201-2405
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JP13
KSI[0..7] <42,46>
KSO[0..15] <46>
4
CP1
KSI3
KSO5
2
KSO1
3
KSI0
4 5
100P_1206_8P4C_50V8
CP2
KSO2
KSO4
2
KSO7
3
KSO8
4 5
100P_1206_8P4C_50V8
CP3
KSI1
KSI7
2
KSI6
3
KSO9
4 5
100P_1206_8P4C_50V8
CP4
KSI4
KSI5
2
KSO0
3
KSI2
4 5
100P_1206_8P4C_50V8
CP5
KSO14
KSO11
2
KSO10
3
KSO15
4 5
100P_1206_8P4C_50V8
CP6
KSO6
KSO3
2
KSO12
3
KSO13
4 5
100P_1206_8P4C_50V8
3
EC_ON
Q112
Power BTN
ON/OFFBTN#
+3VALW
12
R306
470_0402_5%
1 2
R307 0_0402_5%
13
D
2
G
S
D28
1
DAN202U_SC70
DTC124EK_SOT23
SW9
2
4
ESE11MV9_4P
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
81
7
6
EC_ON<46>
@2N7002_SOT23
PIR BOM 92.07.30
R305 100K_0402_5%
1 2
3
2
13
22K
2
22K
Q21
1
3
2
D30 @PSOT03C
ON/OFF#
1
C289
2
1000P_0402_50V7K
LID_SW# <46>
3
+3VALW
ON/OFF# <46>
EC_PWR_ON# <51>
12
D29
RLZ20A_LL34
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
FIR@0.1U_0402_10V6K
FIR@0.1U_0402_10V6K
2
ON/OFFBTN#
2
3
D27 @PSOT03C
FIR Module
+3VS
1
C290
C294
1
2
1
2
C291
FIR@22U_1206_16V4Z
2
T = 20mil
SW8
PRES@TC010-PS11CET_5P
2
4
2
4
FIR@10_1206_5%
U12
2
IRED_C
4
RXD
6
VCC
8
GND
FIR@IR_VISHAY_TFDU6101E-TR4_8P
1
3
5
SW1
PAV@TC010-PS11CET_5P
1
3
5
12
R308
1
IRED_A
3
TXD
5
SD/MODE
7
MODE
+5VS
12
R309
FIR@10_1206_5%
FIR@10U_0805_6.3VM
T = 40mil
+5VS_FIR
T = 12mil
T = 12mil
T = 12mil
1
1
+
C292
2
IRTXOUT
IRMODE
IRRX
1
C293
2
FIR@0.1U_0402_10V6K
IRTXOUT <39>
IRMODE <39>
IRRX <39>
Touch Pad & Status LED Conn.
+3VALW
31
Q92
DTA114EK
10K
E
B
PMLED_1#<44,46>
B B
ACT_LED#<30>
A A
5
4
2
10K
C
R923 220_0402_5%
1 2
+5VS
10K
B
2
10K
C
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIR BOM 92.07.30
31
Q94
DTA114EK
E
PIR BOM 92.07.30
R925 470_0402_5%
1 2
3
PMLED_1 <44> BATLED_0 <44>
ACT_LED <44>
BATLED_0#<44,46>
2
+3VALW
31
Q93
DTA114EK
10K
E
B
2
10K
C
R924 220_0402_5%
1 2
PIR BOM 92.07.30
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
KBD,ON/OFF,T/P,LED & FIR
星期四 八月
LA-1811
1
0.7
of
45 66, 07, 2003
Page 46
A
0.1U_0402_10V6K
+3VALW
1
C318
4.7U_0805_6.3V6K
+3VALW
1 1
CLK_PCI_EC
12
R337
@10_0402_5%
1
2 2
3 3
+3VALW
C329
@15P_0402_50V8J
2
R1169 10K_0402_5%
TP_DATA
1 2
TP_CLK
1 2
R1170 10K_0402_5%
R1171 10K_0402_5%
PS2_DATA
1 2
PS2_CLK
1 2
R1172 10K_0402_5%
FSEL#
1 8
SELIO#
2 7
FRD#
3 6
EC_SMI#
4 5
EC_SMD_2 ADB3
1 8
EC_SMC_2
2 7
EC_SMD_1
3 6
EC_SMC_1
4 5
1 2
R342 20K_0402_5%
C319
2
L32
1 2
MURATA BLM11A20PT_0603
0.1U_0402_10V6K
L33
1 2
MURATA BLM11A20PT_0603
PIR BOM & LAYOUT 92.07.30
+3VALW
RP23
10K_0804_8P4R_5%
SD309100200
RP24
10K_0804_8P4R_5%
LID_SW#
1
2
2
1
ECAGND
10P_0402_50V8K
1
C321
0.01U_0402_16V7K
2
EC_AVCC
1
C327
1000P_0402_50V7K
2
+3VALW
R1162 10K_0402_5%
KBD_DATA
1 2
KBD_CLK
1 2
R1163 10K_0402_5%
1
C330
2
32.768KHZ_12.5P_MC-306
1
C320
2
0.1U_0402_10V6K
C326
+5V
+5VS +5VS
+5VALW
+3VALW
+3VS
R332
1 2
10K_0402_5%
SCI#<27>
R340 20M_0603_5%
Y3
1 2
12
1
43
2
J1 JOPEN
SCI#
KBRST#<27>
KSI[0..7]<42,45>
KSO[0..15]<45>
R341
C331
10P_0402_50V8K
PIR BOM & LAYOUT 92.07.30
SUSP#<47,49>
VR_ON<55>
M_SEN#
1 2
R345 10K_0402_5%
4 4
A
+3VS
MMO_ON
12
12
R344
R1123
10K_0402_5%
@
@10K_0402_5%
B
R926 @0_0603_5%
1 2
R927 0_0603_5%
1 2
C323
4.7U_0805_6.3V6K
SIRQ<26,31,39>
LPC_FRAME#<26,39>
LPC_AD0<26,39>
LPC_AD1<26,39>
LPC_AD2<26,39>
LPC_AD3<26,39>
CLK_PCI_EC<26>
12
R984 0_0402_5%
1 2
GA20<27>
KSI[0..7]
KSO[0..15]
TP_CLK<44>
TP_DATA<44>
LID_SW#<45>
PWR_ACTIVE_PAV#<42>
12
120K_0402_5%
EC_SMI#<27>
EC_MUTE#<38>
G_RST#<31,32,36>
EC_SWI#<27>
BATLED_0#<44,45>
PWR_ACTIVE_PRES#<42>
SYSON<49>
PWR_BACK#<42>
EC_RSMRST#<27>
PCM_SUSP#<31>
ENAVDD<10,17,25>
BKOFF#<25>
FSEL#<47>
B
1
1
C324
2
2
0.1U_0402_10V6K
CLK_PCI_EC
EC_RST#
GA20
KBRST#
PWR_ACTIVE_PAV#
PWR_ACTIVE_PRES#
7
8
9
15
14
13
10
18
19
22
23
31
5
6
KSI0
71
KSI1
72
KSI2
73
KSI3
74
KSI4
77
KSI5
78
KSI6
79
KSI7
80
KSO0
49
KSO1
50
KSO2
51
KSO3
52
KSO4
53
KSO5
56
KSO6
57
KSO7
58
KSO8
59
KSO9
60
KSO10
61
KSO11
64
KSO12
65
KSO13
66
KSO14
67
KSO15
68
EC_TINIT#
105
EC_TCK
106
EC_TDO
107
EC_TDI
108
EC_TMS
109
KBD_CLK
110
KBD_DATA
111
PS2_CLK
114
PS2_DATA
115
TP_CLK
116
TP_DATA
117
LID_SW#
118
119
CRY1
158
CRY2
160
EC_SMI#
62
63
69
70
75
76
148
149
155
156
3
4
27
28
FSEL#
173
174
47
PC87591L-VPCN01 A2_LQFP176
16
U15
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#
IOPD3/ECSCI#
GA20/IOPB5
KBRST/IOPB6
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
TINT#
TCK
TDO
TDI
TMS
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
32KX1/32KCLKIN
32KX2
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
SEL0#
SEL1#
CLK
+3VALW
VDD
VCC134VCC245VCC3
Host interface
Key matrix scan
JTAG debug port
PS2 interface
PORTJ-2
PORTM
GND117GND235GND346GND4
122
C
PIR BOM & LAYOUT 92.07.30
EC_AVCC
123
159
95
136
157
166
VCC4
VCC5
VCC6
AD Input
DA output
PWM
or PORTA
PORTB
IOPB7/RING/PFAIL/RESET2
PORTC
PORTD-1
IOPD2/EXWINT24/RESET2
PORTE
IOPE7/CLKRUN/EXWINT46
PORTH
PORTI
PORTJ-1
PORTD-2
PORTK
PORTL
AGND
GND5
GND6
GND7
96
167
137
ECAGND
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
161
AVCC
VBAT
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
IOPJ0/RD
IOPJ1/WR0
IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#
NC212NC320NC421NC585NC686NC791NC892NC997NC10
NC1
11
2
C911
1U_0603_10V6K
1
C
AD0
AD1
AD2
AD3
DP/AD8
DN/AD9
DA0
DA1
DA2
DA3
IOPC0
SELIO#
IOPD4
IOPD5
IOPD6
IOPD7
98
R1175
2
1K_0402_5%
C322
1U_0603_10V6K
1
81
82
83
ADP_IR
84
PRES_DETECT
87
BID
88
89
VOLBTN-#
90
93
94
99
100
101
102
32
33
36
37
38
39
40
TP_OFF_LED#
43
KSO16
153
KSO17
154
PMLED_1#
162
EC_SMC_1
163
EC_SMD_1
164
165
168
EC_SMC_2
169
EC_SMD_2
170
FANSPEED1 BID
171
172
175
176
1
AC_IN
26
29
30
2
44
M_SEN#
24
25
KBA0
124
KBA1
125
KBA2
126
KBA3
127
KBA4
128
KBA5
131
KBA6
132
KBA7
133
ADB0
138
ADB1
139
ADB2
140
141
ADB4
144
ADB5
145
ADB6
146
ADB7
147
FRD#
150
FWR#
151
SELIO#
152
VOLBTN+#
41
42
54
55
KBA8
143
KBA9
142
KBA10
135
KBA11
134
KBA12
130
KBA13
129
KBA14
121
KBA15
120
KBA16
113
KBA17
112
KBA18
104
KBA19
103
48
BATT1.1
BATT_TEMPA <51>
1 2
0.01U_0402_16V7K
C325
BATT_OVP <52>
WIRELESS_BTN <38,42>
VOLBTN-# <38,41,44>
DAC_BRIG <25>
EN_FAN1 <7>
IREF <52>
EN_FAN2 <7>
INVT_PWM <25>
BEEP# <37>
ACOFF <52>
PM_BATLOW# <27>
EC_ON <45>
LID_OUT# <27>
TP_OFF_LED# <42>
KSO16 <42>
PMLED_1# <44,45>
EC_SMC_1 <47,51>
EC_SMD_1 <47,51>
PWRBTN_OUT# <27>
EC_SMC_2 <7>
EC_SMD_2 <7>
FANSPEED1 <7>
PME_EC# <31,34,36,43,47>
EC_THERM# <27>
FANSPEED2 <7>
WL_ON <43,44>
JACK_DET# <41>
SLP_S3# <27>
ON/OFF# <45>
SLP_S5# <27>
M_SEN# <25>
CONA# <37,41>
FRD# <47>
FWR# <47>
SELIO# <47>
VOLBTN+# <38,41,44>
NUMLED# <42>
CAPSLED# <42>
FSTCHG <52>
D
PRES_DETECT
ECAGND
R986
12
@0_0402_5%
EEPROM/BATTERY
1 2
R985 @0_0402_5%
1 2
R1135 33_0402_5%
THERMAL
+3VALW
ADB[0..7]
KBA[0..19]
D
1
2
SCI#
AC_IN
R1147
1 2
6.2K_0402_5%
R1148
10K_0402_5%
1 2
R331
1 2
10K_0402_5%
C328
0.22U_0603_10V7K
R338
1 2
ADB[0..7] <47>
KBA[0..19] <47>
E
BADDR1-0
*
Index
0 0
0 1
(HCFGBAH, HCFGBAL)
1 0
1 1
PRES_LEDVCC <42,44>
I/O Address
2E
4E
(HCFGBAH, HCFGBAL)+1
Reserved
ENV0
0
IRE
0
OBD
ADP_I <51,52>
SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the
signals for clip-on ISE use
PCI_RST# <11,26,30,31,34,35,36,43>
VTT_PWRGD <24,27,48>
10K_0402_5%
2 1
D36 RB751V_SOD323
KBA1
KBA2
KBA3
KBA5
*
(ENV1)
(BADDR0)
(BADDR1)
(SHBM)
1
DEV
1
PROG
R333
1 2
10K_0402_5%
R334
1 2
@10K_0402_5%
R335
1 2
10K_0402_5%
1 2
R336 10K_0402_5%
ACIN <27,50,53>
EC DEBUG port
JP21
1
1
EC_TINIT#
2
2
EC_TCK
3
3
EC_TDO
4
4
EC_TDI
5
5
EC_TMS
6
6
7
7
KSO16
8
8
KSO17
9
9
PMLED_1#
10
10
@96212-1011S
R959
VOLBTN+#
VOLBTN-#
10K_0402_5%
PIR LAYOUT 92.07.30
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
KBD EC CTRL -NS P C87591L
星期四 八月
+3VS
1 2
1 2
LA-1811
+5VALW
R960
10K_0402_5%
E
Data
ENV1
2F
4F
0
1
0
1
+3VALW
46 66, 07, 2003
TRIS
0
0
0
0
12
R929
@1K_0402_5%
12
R931
1K_0402_5%
of
0.7
Page 47
14
P
G
7
R352
O
U18ASN74LVC32APWLE_TSSOP14
OUTPUT
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
3
LARST#
C334
1 2
@1U_0603_10V6K
3
11
1
+5VALW
20
D0
VCC
D14Q1
D27Q2
D38Q3
D413Q4
D514Q5
D617Q6
D718Q7
CP
MR
GND
10
C333
U17
Q0
1 2
@0.1U_0402_16V7K
2
5
6
9
12
15
16
19
@SN74HCT273PW_TSSOP20
ADB[0..7]<46>
KBA[0..19]<46>
ADB[0..7]
KBA[0..19]
+3VALW
KBA2
1
A
SELIO#
+3VALW
2
B
1 2
@20K_0402_5%
SELIO#<46>
U19
KBA18
1
A18
KBA16
2
A16
KBA15
3
A15
KBA12
4
A12
KBA7
5
A7
KBA6
6
A6
KBA5
7
A5
KBA4
8
A4
KBA3
9
A3
KBA2
10
A2
KBA1
11
A1
KBA0
12
A0
ADB0
13
DQ0
ADB1
14
DQ1
ADB2
15
DQ2
16
VSS
512K8-90_PLCC32
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
FSEL#<46>
FRD#<46>
FSEL#
FRD#
FWE#
U20
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
READY/BUSY#
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
@SST39VF080-70_TSOP40
VCC0
VCC1
RP#
NC0
NC1
GND0
GND1
32
VDD
WE#
OE#
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
D0
D1
D2
D3
D4
D5
D6
D7
NC
FWE#
31
KBA17
30
A17
KBA14
29
A14
KBA13
28
A13
KBA8
27
A8
KBA9
26
A9
KBA11
25
A11
FRD#
24
KBA10
23
A10
FSEL#
22
ADB7
21
ADB6
20
ADB5
19
ADB4
18
ADB3
17
31
30
ADB0
25
ADB1
26
ADB2
27
ADB3
28
ADB4
32
ADB5
33
ADB6
34
ADB7
35
RESET#
10
11
12
29
38
23
39
2
C336
0.1U_0402_10V6K
1
+3VALW
1 2
R360
@100K_0402_5%
+3VALW
SN74LVC32APWLE_TSSOP14
1
C338
0.1U_0402_10V6K
2
+3VALW
FWE#
U18C
8
7
6
5
12
R359
100K_0402_5%
+3VALW
12
R356
4.7K_0402_5%
U21
A0
VCC
A1
WC
SCL
A2
SDA
GND
AT24C164-10SC_SO8
PME_EC# <31,34,36,43,46>
+3VALW+3VALW
12
R357
100K_0402_5%
1
2
3
4
12
R358
100K_0402_5%
+3VALW
12
+3VALW
14
P
A
8
O
B
G
7
KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
KBA18
KBA7
KBA6
KBA5
KBA3
KBA1
R354
10K_0402_5%
9
Q29 2N7002 1N_SOT23
10
JP22
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
@SUYIN-80065A-040G2T
1 3
D
2
G
S
SUSP# <46,49>
EC_FLASH# <27>
FWR# <46>
KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
FRD#KBA4
FSEL#KBA2
KBA0
+3VALW
PCM_PME#<31,34,36,43,46>
WLAN_PME#<31,34,36,43,46>
ONBD_LAN_PME#<31,34,36,43,46>
MDM_PME#<31,34,36,43,46>
USB20_PME#<31,34,36,43,46>
0.1U_0402_10V6K
EC_SMC_1<46,51>
EC_SMD_1<46,51>
C337
1
2
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
BIOS & EC I/O Port
星期四 八月
LA-1811
of
47 66, 07, 2003
0.7
Page 48
+3VS
SN74LVC32APWLE_TSSOP14
12
R601
10K_0402_5%
VCORE_PWRGD<56>
R605
1M_0402_5%
12
12
13
12
R1107
1K_0402_5%
+3VALW
A
B
14
U18D
P
G
7
O
11
SUSP<49,55>
R1106
1 2
330K_0402_5%
VTT_PWRGD <24,27,46>
0.1U_0402_16V7K
13
D
Q111
2
G
@2N7002_SOT23
S
+3VALW +3VALW
14
P
3
O4I
G
C606
1
2
U32B
7
SN74LVC14APWLE_TSSOP14
+3VALW
14
P
5
7
SN74LVC14APWLE_TSSOP14
+2.5VS
12
13
2
G
O6I
G
U32C
R608
1K_0402_5%
D
Q52
2N7002_SOT23
S
1 2
330K_0603_5%
R603
SUSP
12
R610
47K_0402_5%
2
G
NB_PWRGD <8>
0.47U_0603_10V7K
1
C607
2
13
D
Q110
@2N7002_SOT23
S
14
P
9
O8I
G
U32D
7
SN74LVC14APWLE_TSSOP14
+3VALW
14
P
11
G
7
R604 47_0603_5%
O10I
U32E
SN74LVC14APWLE_TSSOP14
1 2
12
R606
10K_0402_5%
SB_PWRGD <27>
1
1
2
2
1
D20
DAN217_SOT23
2
3
+3VS
JP7
1
2
TV_LUMAL
TV_CRMAL
TV_COMPSL
C115
68P_0402_50V8K
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
5
6
7
SUYIN_35138S-07T1-DF
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
POWER GOOD & P/S2 CKT
星期四 八月
LA-1811
of
48 66, 07, 2003
0.7
1
D19
TV_OUT CONNECTOR
TV_LUMA<11,17,41>
TV_CRMA<11,17,41>
TV_COMPS<11,17,41>
TV_GND<41>
TV_LUMA
TV_CRMA
TV_COMPS
R188
75_0402_5%
R961
0_0603_5%
12
R189
75_0402_5%
1 2
75_0402_5%
12
R190
68P_0402_50V8K
12
1
C111
C110
2
68P_0402_50V8K
1
2
DAN217_SOT23
L4 CHB1608B121_0603
1 2
L7 CHB1608B121_0603
1 2
L8 CHB1608B121_0603
1 2
1
C112
2
68P_0402_50V8K
2
C113
68P_0402_50V8K
3
1
C114
2
68P_0402_50V8K
Page 49
A
B
C
D
E
+2.5VALW to +2.5V Transfer
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C347
0.1U_0402_10V6K
+2.5V
C343
1
C344
10U_0805_6.3V6M
2
1
2
+2.5VALW
+12VALW
12
2
G
R362
100K_0402_5%
13
D
Q31
2N7002 1N_SOT23
S
1 1
SYSON#
1
2
8
7
6
C341
5
10U_0805_6.3V6M
U22
D
D
D
D
SI4800DY_SO8
1
2
+3VALW to +3V Transfer
+12VALW
12
R902
2
G
95.3K_0603_1%
13
D
Q74
2N7002 1N_SOT23
S
2 2
SYSON#
1
2
8
7
6
C351
5
10U_0805_6.3V6M
U25
D
D
D
D
SI4800DY_SO8
1
2
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C356
0.1U_0402_10V6K
+3V+3VALW
C354
1
C355
10U_0805_6.3V6M
2
1
2
+5VALW to +5V Transfer
+12VALW +12VALW
12
R904
47K_0402_5%
3 3
SYSON# SUSP
2
G
13
D
Q76
2N7002 1N_SOT23
S
1
2
8
7
6
C624
5
10U_0805_6.3V6M
U36
D
D
D
D
SI4800DY_SO8
1
2
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
C627
0.1U_0402_10V6K
+5V+5VALW
1
2
C625
1
C626
10U_0805_6.3V6M
2
+2.5V to +2.5VS Transfer
+12VALW
12
R903
100K_0402_5%
13
2
G
D
Q75
2N7002 1N_SOT23
S
SUSP SUSP
+2.5VALW
1
C357
2
10U_0805_6.3V6M
U26
8
D
7
D
6
D
5
D
SI4800DY_SO8
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C360
0.1U_0402_10V6K
2
+2.5VS
1
2
C358
1
C359
10U_0805_6.3V6M
2
(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
+3VALW to +3VS Transfer
R363
95.3K_0603_1%
SUSP
2
G
+12VALW
12
13
D
S
+3VALW
1
C342
2
10U_0805_6.3V6M
Q32
2N7002 1N_SOT23
U23
8
D
7
D
6
D
5
D
SI4800DY_SO8
1
S
2
S
3
S
4
G
1
C348
0.1U_0402_10V6K
2
+3VS
1
C345
2
0.1U_0402_10V6K
1
C346
10U_0805_6.3V6M
2
+5VALW to +5VS Transfer
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C844
0.1U_0402_10V6K
2
+5VS
1
2
C352
1
C353
10U_0805_6.3V6M
2
12
R901
6.8K_0402_5%
PIR BOM 92.07.30
13
D
2
G
S
1
C350
2
10U_0805_6.3V6M
Q73
2N7002 1N_SOT23
+5VALW
U24
8
D
7
D
6
D
5
D
SI4800DY_SO8
+1.5VSP to +1.5VS Transfer
12
R1101
56K_0402_5%
13
D
Q108
2
G
2N7002 1N_SOT23
S
Place close to PJP4
L
+1.5VSP +1.5VS+12VALW
1
C959
2
10U_0805_6.3V6M
SYSON<46>
SUSP<48,55>
SUSP#<46,47>
U56
8
D
7
D
6
D
5
D
SI4800DY_SO8
SYSON#
SYSON
SUSP
1
S
2
S
3
S
4
G
0.1U_0402_10V6K
1
C962
0.1U_0402_10V6K
2
1
2
C960
1
C961
10U_0805_6.3V6M
2
(6A,240mils ,Via NO.= 12)
+5VALW
12
R369
10K_0402_5%
13
D
Q34
2
2N7002 1N_SOT23
G
S
+5VALW
12
R373
10K_0402_5%
13
D
Q38
2
G
2N7002 1N_SOT23
S
Discharge circuit
+1.8VS
2
G
12
R375
470_0402_5%
13
D
Q40
2N7002 1N_SOT23
S
12
R374
470_0402_5%
13
D
2
G
Q39
2N7002 1N_SOT23
S
A
4 4
SUSP SUSP
+2.5VS
12
R376
470_0402_5%
13
D
2
G
Q41
2N7002 1N_SOT23
S
SUSPSUSP
SUSP
B
2
G
+3VS +5VS+1.25VS
12
13
D
S
R377
470_0402_5%
Q42
2N7002 1N_SOT23
2
G
12
R378
470_0402_5%
13
D
Q43
2N7002 1N_SOT23
S
+1.2VS_VGA
12
R1116
470_0402_5%
13
D
2
G
S
C
Q115
2N7002 1N_SOT23
SUSP
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R1094
470_0402_5%
13
D
2
G
Q102
2N7002 1N_SOT23
S
SUSP SYSON# SYSON#SYSON#
+5V+1.5VS +3V
12
R1095
470_0402_5%
13
D
Q103
2
G
2N7002 1N_SOT23
S
D
12
R1102
470_0402_5%
13
D
Q109
2
G
2N7002 1N_SOT23
S
Title
Size Document Number Rev
Date: Sheet
星期四 八月
+2.5V
12
R372
470_0402_5%
13
D
Q36
2
G
2N7002 1N_SOT23
S
Compal Electronics, Inc.
DC/DC Circuits
LA-1811
49 66, 07, 2003
E
0.7
of
Page 50
A
B
C
D
E
Detector
1 1
PCN1
FOX_JDP1021
2 2
ADPIN
PL1
1
2
3
4
12
PC1
100P_0603_50V8G
FBM-L18-453215-900LMA90T_1812
ADPIN
12
PC2
1000P_0402_50V8J
1 2
PC3
PD43
2
1
3
SBM1040-13_POWERMITE3
PJP17
12
12
100P_0603_50V8G
PAD-OPEN 4x4m
1000P_0402_50V8J
1 2
PJP18
1 2
PAD-OPEN 4x4m
PC4
DC_IN
PIR POWER 92.08.04
PR1
10K_0603_5%
3 3
Vin Detector
17.522 17.044 16.575
VL
17.026 16.544 16.090
DCSRD<52>
PR4
1M_0603_1%
DC_IN
12
PR6
150K_0603_0.1%
PR9
1K_0603_1%
1 2
12
PR11
66.5K_0603_1%
12
PC10
1000P_0603_16V7K
12
PC9
4 4
1000P_0603_16V7k
A
1 2
VS
8
5
+
6
-
4
PR14
10K_0603_5%
12
P
O
G
PU1B
LM393M_SO8
B
7
RLZ4.3B_LL34
VL
5V
PZD1
DC_IN
12
PR7
8.2K_0805_5%
12
PR8
1K_0603_5%
1 2
PACIN PACIN
12
PR12
10K_0603_5%
ACIN <27,46,53>
PACIN <52>
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
MAINPWON<7,51,53>
ACIN
Precharge detector
16.421 15.817 15.229
14.108 13.657 13.002
BATT
detector
15.029 14.095 13.187
12.636 11.850 10.860
1 2
PD22
12
RB751V_SOD323
PD1
12
RB751V_SOD323
12
D
PC7
0.1U_0603_25V7K
PU1A
LM393M_SO8
1
VL
PR2
1M_0402_5%
12
8
P
O
G
4
PR10
10K_0603_1%
PR191
499K_0603_1%
2
G
13
2N7002_SOT23
Detector
B+
12
PR3
432K_0603_1%
12
PR5
499K_0603_1%
PR192
1 2
47K_0603_5%
100K
2
DTC115EKA_SOT23
100K
E
PQ47
12
+5VALW
50 66, 07, 2003
VS
12
PC5
0.01U_0603_50V7K
3
+
2
-
12
PC8
1000P_0603_16V7K
12
Title
Size Document Number Rev
Date: Sheet
12
13
D
PQ46
S
Compal Electronics, Inc.
星期四 八月
PC6
1000P_0402_50V8J
0.7
of
Page 51
A
B
C
D
PCN2
1 1
SUYIN_200275MR009G130ZL
2 2
BATT+
BATT+
SMD
SMC
GND
GND
1
2
TS_A
3
TS
EC_SMDA
4
EC_SMCA
5
6
7
PR18
100_0603_5%
12
PR19
100_0603_5%
12
PR24
1 2
25.5K_0603_1%
12
PR26
1K_0603_5%
1
3
PD3
@BAS40-04_SOT23
2
@
VMB
CHT_C8BBPH853025_13A
12
+3VALWP
PL2
1 2
PC11
1000P_0603_50V7K
BATT_TEMPA <46>
ADP_I<46,52>
VREF
12
PC12
0.01U_0603_50V4Z
BATT+
1 2
1 2
100K_0603_1%
PR22
11.5K_0603_1%
PR23
200K_0603_1%
PR25
12
12
12
PC97
0.01U_0603_50V4Z
PR193
1 2
73.2K_0603_1%
PC14
1000P_0603_50V7K
3
2
1 2
1M_0603_1%
VS
8
P
+
-
G
4
PR17
12
PU2A
1
O
LM393M_SO8
PC13
0.1U_0603_50V4Z
VREF
12
PR21
47K_0603_1%
12
PC15
1000P_0603_50V7K
H_PROCHOT# <5,26>
13
D
S
PQ1
2N7002_SOT23
2
G
EC_SMD_1 <46,47>
EC_SMC_1 <46,47>
@BAS40-04_SOT23
PD4
1
@
3
2
+5VALWP
3 3
BATT+
PD8
12
RB751V_SOD323
PD9
12
RLZ4.3B_LL34
100K_0603_5%
EC_PWR_ON#<45>
1 2
PR38
PR39
22K_0603_5%
12
12
0.22U_1206_25V7M
RTCVREF
PR230
CHGRTC
4 4
1 2
200_0603_5%
PR43
1 2
200_0603_5%
A
3.3V
12
PC23
10U_1206_10V4Z
1
2
N1CHGRTCP
PC17
PU3
S-81233SGUP-T1_SOT89
3
3
@BAS40-04_SOT23
PD5
@
3
1
1
13
PQ2
TP0610T_SOT23
2
2
DC_IN
1 2
12
12
2
PD7
1N4148_SOD80
PR31
47_1206_5%
PC18
0.1U_0805_25V7M
12
PR41
200_0603_5%
N2
12
PC22
1U_0805_50V4Z
PD6
12
1N4148_SOD80
VS
2 1
N3
PD10
RLZ16B_LL34
B
PR27
1 2
1.5K_1206_5%
PR28
1 2
1.5K_1206_5%
PR29
1 2
1.5K_1206_5%
B+
PH2 near main Battery CONN :
BAT. thermal protection at 84 degree C
Recovery at 45 degree C
VL
PR30
2.15K_0603_1%
12
PR32
47K_0402_1%
1 2
VS
PR36
16.9K_0603_1%
1 2
12
PC21
1000P_0402_50V7K
12
PH1
10K_TH11-3H103FT_0603_1%
12
PC20
0.22U_0805_16V7K_V2
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY O
C
5
+
6
-
PR40
150K_0402_1%
PR42
100K_0402_1%
8
PU2B
P
O
G
LM393M_SO8
4
VL
12
7
Title
Compal Electronics, Inc.
BATTERY CONN / OTP
Size Document Number Rev
Date: Sheet of
星期四
07, 2003
八月
MAINPWON <7,50,53>
LA-1811
D
0.7
51 66,
Page 52
A
B
C
D
1
2
3
4
PC29
150K_0603_5%
2
G
PR65
P2
12
0.47U_0805_25V4Z
PR53
12
13
D
PQ9
2N7002_SOT23
S
12
1
2
3
4
AOS4407_SO8
12
PR47
200K_0603_5%
PC32
0.1U_0603_16V4Z
PQ4
S
S
S
G
ADP_I<46,51>
12
10K_0603_1%
D
D
D
D
12
PR56
8
7
6
5
12
12
12
P3
PR54
31.6K_0603_1%
1 2
VREF
4700P_0603_50V7K
PC35
1 2
0.1U_0603_16V4Z
1500P_0603_50V7K
PC42
0.1U_0603_16V4Z
Iadp=0~6A
PR44
0.01_2512_1%
PR52
12
47K_0603_1%
PR57
PC33
1 2
PR59
PC36
1 2
1K_0603_1%
PR62
10K_0603_1%
12
1K_0603_1%
12
47.5K_0603_0.1%
1
2
3
4
5
6
7
8
9
10
11
12
PR66
B+
PU4
-INC2
+INC2
OUTC2
GND
+INE2
-INE2
VCC(o)
FB2
OUT
VREF
FB1
VCC
-INE1
+INE1
-INE3
OUTC1
FB3
OUTD
CTL
-INC1
+INC1
MB3887_SSOP24
12
1 2
HCB4532K-800T90_1812
24
23
22
CS
21
20
19
VH
0.1U_0603_50V4Z
18
17
RT
16
15
47K_0603_1%
14
13
PL3
4.7U_1210_25V6K
CHGSS
PC34
1 2
PR60
1 2
68K_0603_5%
PR63
1 2
1500P_0603_50V7K
DCSRD
PC24
PC25
12
4.7U_1210_25V6K
12
PR50
0_0603_5%
PC30 2200P_0603_50V7K
1 2
PC31
1 2
0.1U_0805_25V7M
PC37
1 2
0.1U_0805_25V7M
PC38
1 2
4.2V
B++
PC26
12
12
@4.7U_1210_25V6K
@
143K_0603_0.1%
PR67
N18
12
12
PC28
2200P_0402_50V7K
36
241
PQ6
SI4835DY_SO8
578
LXCHRG
PL4
1 2
15U_SPC-1204P-150_4A_20%
PD14
2 1
SKS30-04AT_TSMA
ACOFF#
1 2
0.02_2512_1%
CC=0.5~3A
1
2
3
4
PR48
1 2
47K_0603_5%
12
PR51
10K_0603_5%
13
100K
2
100K
PQ8
DTC115EKA_SOT23
PR61
PQ5
S
D
S
D
S
D
G
D
AOS4407_SO8
PC39
4.7U_1210_25V6K
8
7
6
5
DC_IN
ACOFF <46>
PC40
PC41
12
12
4.7U_1210_25V6K
12
4.7U_1210_25V6K
BATT+
DC_IN
PD30
13
PQ49
DTC115EUA_SC70
PACIN<50>
ACOFF#
DTA144YKA_SC70
PQ48
2
PACIN
PD13
1 2
1SS355_SOD323
PR64
1 2
174K_0603_1%
1SS355_SOD323
12
12
<50>
PR240
0.1U_0603_25V4K
DCSRD
2
G
1 2
12
PR195
47K_0402_5%
2
13
D
PQ50
2N7002_SOT23
S
IREF<46>
1 1
1K_0603_1%
PC98
2 2
PQ3
8
S
D
7
S
D
6
S
D
5
G
D
AOS4407_SO8
47K
10K
1 3
PR58
1 2
3K_0603_5%
PIR POWER 92.08.04
100K_0603_1%
IREF=1.1*Icharge
IREF=0.73~3.3V
3 3
CV=16.8V(12 CELLS LI-ION)
OVP voltage : LI
4S3P : 18V--> BATT_OVP= 2.0V
3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V
(BAT_OVP=0.1111 *VMB)
VL
12
8
PU5A
3
P
+
1
BATT_OVP<46>
4 4
A
0
2
-
G
LM358A_SO8
4
105K_0603_0.5%
VMB
12
12
PC43
0.1U_0603_50V4Z
12
PR72
PR69
340K_0603_1%
PR70
499K_0603_1%
12
PC45
0.01U_0603_50V4Z
B
+3VALWP
13
C
D
PQ10
2N7002_SOT23
S
CHGSS
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
CHARGER
星期四
LA-1811
07, 2003
八月
D
52 66,
0.7
12
PR68
47K_0603_5%
2
13
100K
FSTCHG<46>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY O
2
100K
G
PQ11
DTC115EKA_SOT23
Page 53
A
B
C
D
B+
1 1
12
PL5
HCB4532K-800T90_1812
B++++
PC50
2200P_0402_25V7K
12
12
PC51
12
PC52
4.7U_1210_25V6K
@4.7U_1210_25V6K
578
3 6
241
5
D8D7D6D
2 2
PL6
10UH_SPC-1204P-100_4.5A_20%
+3VALWP
PC69
1
2
3 3
@150U_D_6.3VM
1
PD17
PC70
+
+
EP10QY03
2
150U_D_6.3VM
2 1
@
12
12
PC63
47P_0402_25V8K
PR83
1M_0402_5%
1 2
PIR POWER 92.08.04
3.32K_0603_1%
PR91
1 2
PR97
10K_0402_1%
1 2
S1S2S3G
4
1 2
1.27k_0603_1%
1.27k_0603_1%
1 2
0_0402_5%
12
PC71
100P_0402_50V8K
+3.3V Ipeak = 6.66A ~ 10A
PQ12
SI4800DY
DH31
PQ14
SI4810DY_SO8
PR81
PR241
1 2
PR85
ACIN<27,46,50>
PC48
1 2
0.1U_0805_25V7K_V2
1 2
0_0402_5%
BST31
PR74
LX3
DL3
PC67
12
0.47U_0603_10V6K
1 2
620_0402_5%
PR89
1 2
10K_0402_1%
300K_0402_5%
VS
12
PR99
47K_0402_1%
12
PC79
@0.047U_0603_16V7K
PR242
PR92
DH3
12
12
PR75
0_0402_5%
12
PC73
680P_0402_50V7K
1SS355_SOD323
12
PC60
0.1U_0805_25V7K_V2
PU6
25
BST3
27
DH3
26
LX3
24
DL3
1
CSH3
2
CSL3
3
FB3
10
SKIP#
23
SHDN#
7
TIME/ON5
28
RUN/ON3
VS
VL
PD19
1 2
22
V+
2
PC54
21
GND
MAX1632_SSOP28
8
VL
VL
12
PR101
100K_0603_1%
VL
3
1
12
4.7U_1206_10V6K
12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#
1 2
@0_0402_5%
PD16
DAP202U_SOT323
PQ51
ACIN
2
G
2N7002_SOT23
4
5
18
16
17
19
20
14
13
12
15
9
6
11
PR94
+12VALWP
12
PR239
13
D
S
1 2
BST51
2.7K_1206_5%
PR95
0_0402_5%
PC61
12
12
4.7U_1210_25V6K
2.5VREF
PC72
4.7U_1206_25V6K
PC53
1 2
0.1U_0805_25V7K_V1
PR77
0_0402_5%
1 2
PC68
12
0.47U_0603_10V6K
10.2K_0402_1%
10K_0402_1%
LX5
PC57
1 2
PR96
PR100
470P_0805_100V7K
12
12
PC58
4.7U_1210_25V6K
PR80
0_0402_5%
DL5
PR243
698_0402_1%
1 2
12
12
4.7U_1210_25V6K
12
100P_0402_25V8K
PC47
1 2
B++++
PQ13
SI4800DY
PR73
12
22_1206_5%
578
2200P_0402_25V7K
12
PC56
3 6
DH51DH5
241
5
D8D7D6D
S1S2S3G
4
PIR POWER 92.08.04
PD18
PC75
EP10QY03
2 1
FLYBACKSNB
12
PQ15
SI4810DY_SO8
12
PC46
4.7U_1210_25V6K
1 2
12
PD15
EC11FS2
PT1
1 4
3 2
9U_SDT-1204P-100-132A_5A_30%
12
1.54k_0603_1%
PC65
47P_0402_25V8K
PR82
2M_0402_1%
PR78
12
PR79
0_0402_5%
+5VALWP
PC76
1
+
PC74
2
@150U_D_6.3VM
1
+
2
150U_D_6.3VM
+5V Ipeak = 6.66A ~ 10A
MAINPWON <7,50,51>
12
PC80
1U_0603_16V6K
4 4
THIS SHEET OF EN GINE ERI NG DR AWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION I T CONTA INS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
A
B
INC.
C
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
星期四
07, 2003
八月
5V/3.3V/12V
D
53 66,
0.7
Page 54
5
D D
PQ16
SI4800DY_SO8
PC93
PD21
EP10QY03
220U_D2_6.3VM
2 1
PL8
12
1
+
12
2
PC94
4.7U_0805_6.3V6K
4.7U_SPC-1204P-4R7
+1.5VSP +2.5VALWP
C C
PIR POWER 92.04.16
B B
+2.5VALWP
+1.25VSP
+VCCVIDP
PJP1
PAD-OPEN 4x4m
1 2
PJP2
PAD-OPEN 4x4m
1 2
PJP4
1 2
PAD-OPEN 3x3m
PJP6
2 1
PAD-OPEN 2x2m
+2.5VALW
(8A,480mils ,Via NO.=24)
(2A,80mils ,Via NO.= 4)
+1.25VS
(150mA,40mils ,Via NO.= 2)
+VCCVID
4
PC81
2200P_0402_50V7K
12
DAP202U_SOT323
578
0.1U_0805_50V7M
3 6
241
5
PQ18
D8D7D6D
SI4810DY_SO8
S1S2S3G
4
+5VALWP
The related parts will be
L
placed close to power PU7.11
PJP16
PAD-OPEN 4x4m
1 2
+5VALWP
(6A,240mils ,Via NO.= 12)
+3VALWP
(6A,240mils ,Via NO.= 12)
PJP3
1 2
PAD-OPEN 4x4m
PJP5
1 2
PAD-OPEN 4x4m
12
PC83
4.7U_1210_25V6K
PD20
PC89
1 2
3
1 2
12
PR107
0_0603_5%
+5VALW
+3VALW
1
2
PR105
0_0603_5%
0_0603_5%
PR236
12
0_0603_5%
4.7U_1210_25V6K
PC84
12
PC90
0.1U_0805_50V7M
25
BST1
26
DH1
27
LX1
24
DL1
28
CS1
1
OUT1
2
FB1
11
ON1
3
PR102
1 2
12
VCC_MAX1845
12
4
1U_0805_16V7K
V+
MAX1845EEI_QSOP28
GND
OVP
8
23
PC91
22
VCC
SKIP
6
0_0603_5%
9
VDD
UVP
BST2
DH2
LX2
DL2
CS2
OUT2
FB2
ON2
PGOOD
TON
ILIM2
ILIM1
REF
10
16.9K_0603_0.1%
12
127K_0603_1%
PC99
0.22U_0603_16V7K
+5VALWP
PR103
12
PR104
20_0603_1%
PU7
21
19
18
17
20
16
15
14
12
7
5
13
3
PR114
12
12
PR115
100K_0603_1%
1 2
0_0603_5%
1 2
PR116
12
PC88
4.7U_0805_10V4Z
PR106
12
1 2
12
PR117
PC92
0.1U_0805_50V7M
12
PR108
0_0603_5%
100K_0603_1%
2
PL7
FBM-L11-322513-151LMAT_1210
PQ19
SI4810DY_SO8
12
PC85
2200P_0402_50V7K
PQ17
SI4800DY_SO8
+5VALWP
578
3 6
5
4
241
D8D7D6D
S1S2S3G
12
PL9
1 2
4.7U_SPC-1204P-4R7
1
12
PC87
4.7U_1210_25V6K
12
PC96
4.7U_0805_6.3V6K
B+
1
PC95
+
PD23
2 1
2
EP10QY03
220U_D2_6.3VM
PJP8
+12VALWP
A A
+1.8VSP
2 1
PAD-OPEN 2x2m
PJP10
1 2
PAD-OPEN 3x3m
5
(120mA,20mils ,Via NO.= 1)
+12VALW
(1.5A,120mils ,Via NO.= 6)
+1.8VS
PIR POWER 92.04.16
Compal Electronics, Inc.
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
DDR POWER 2.5V & 1.5V
Size Document Number Rev
B
Date: Sheet
星期四 八月
1
of
54 66, 07, 2003
0.7
Page 55
A
B
C
D
E
+5VS_1.2V
PD24
1 1
PU8
MAX1954
33P_0402_50V8J
12
PC107
COMP/SHDN#2PGND
180K_0603_5%
12
PR121
10U_0805_6.3V4Z
12
PC102
12
470P_0402_50V7K_A34
PC106
2 2
PJP15
1 2
+5VS_1.2V+5VS
PAD-OPEN 4x4m
1SS355_SOD323
5
1
IN
HSD
GND
4
12
12
PC100
PC101
10
BST
DH
LX
DL
FB
12
0.1U_0603_10V6K
8
PR119
0_0603_5%
9
6
7
3
1 2
578
3 6
241
578
PQ23
3 6
241
VGA_CORE
M9+
M10
22U_1210_6.3V6M
PQ21
SI4800DY_SO8
PL10
1 2
2.2UH_1205P_2R2B_13A
SI4810DY_SO8
1.5V
1.2V
12
1
1
+
PC103
2
2
220U_D_2VM
PR122
4.53K_0603_1%
+
PC104
12
@220U_D_2VM
9.09K_0603_1%
PR124//PR202 = 5.11K_0603_1%
PR124 = 9.09K_0603_1%
PR124
+1.2VS_VGA
12
PR202
11.5K_0603_1%
+3VALWP
PR217
0_0603_5%
4.7U_0805_10V4Z
VID_PWRGD<5,56>
VR_ON<46>
12
PC172
12
PR123
0_0603_5%
+VCCVIDP
12
PR218
100K_0402_1%
1 2
PU27
1
VIN
4
PG
3
EN
MIC5258_SOT23-5
OUT
GND
5
2
12
PC171
4.7U_0805_10V4Z
PIR POWER 92.04.16
PR235
12
+2.5VS +1.8VSP
3 3
4 4
A
PQ24
2SC4672_SOT89
213
CBE
15_0603_5%
12
PR128
22U_1210_10v
5.1K_0402_5%
1 2
PR127
PC184
68P_0402_50V8J
1 2
PC110
7
+2.5VS
1
+
5.1K_0402_5%
12
12
PR125
PU5B
LM358A_SO8
6
5
0.01U_0402_25V7K
1 2
PC112
PR126
100_0603_5%
12
PC111
560P_0402_50V7K
12
10K_0603_0.1%
PR130
PQ25
B
PR129
1 2
3.9K_0603_1%
13
D
G
S
2N7002_SOT23
2
2.5VREF
SUSP <48,49>
2
VL
-
0
+
(1.25V)
+1.25VREF
THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
12
0_0603_5%
PC176
10U_1206_10V4Z
0.1U_0402_16V4Z
12
PC179
7
STANDBY/
4
VD
RefOut8VttSense
1
VSS
NE57814
VDD
ExtRefIn
VTT
D
5
6
2
3
1
12
+
PC173
2
150U_D2_6.3VM
PC174
0.1U_0402_10V6K
PU16
PC177
0.1U_0402_10V6K
12
+1.25VSP
12
PC175
0.1U_0402_10V6K
Compal Electronics, Inc.
Title
1.2V/1.8V/ VCCVID/1.25V
Size Document Number Rev
B
Date: Sheet
星期四 八月
+2.5VS
12
PC178
1U_0603_10V6K
of
55 66, 07, 2003
E
0.7
Page 56
CORE_REF<57>
VID_PWRGD<5,55>
100K_0402_1%
+5VS_CORE
PR147
1 2
10_0603_1%
PR246
0.022U_0603_50V4Z
PR170
0_0402_5%
1 2
0_0402_5%
PC126
FB
12
PC139
12
PJP14
2 1
PAD-OPEN 2x2m
VSSSENSE<5>
+5VS +5VS_CORE
12
1000P_0402_50V7K
12
VCCSENSE<5>
12
12
PR140
12
PC123
1U_0603_10V6K
PR149
0_0402_5%
470P_0402_50V8J
@1.74K_0402_1%
PR158
2.7K_0603_1%
OAIN-
100P_0603_50V8G
30.1K_0603_1%
PR137
1 2
270P_0402_50V7K
12
PC122
PR109
1 2
1 2
PR2200_0402_5%
1 2
PR2210_0402_5%
1 2
PR2220_0402_5%
1 2
PR2230_0402_5%
1 2
PR2240_0402_5%
1 2
PR2250_0402_5%
1 2
PC180
12
100P_0402_50V8K
PR160
1 2
20K_0402_5%
PQ33
CORE_REF
PR144
47K _0402_1%
12
12
PC136
PR152
1 2
@
OAIN+
VCORE_PWRGD<48>
PR138
1 2
@0_0402_5%
PR139
1 2
0_0402_5%
12
0.22U_0603_10V7K
PC114
@100K_0402_1%
+VCCVID
VID5<5>
VID4<5>
VID3<5>
VID2<5>
VID1<5>
VID0<5>
12
PC142
(120mA,20mils ,Via NO.= 1)
PU9
1
TIME
2
TON
6
SHDN#
8
REF
9
ILIM
10
VCC
12
CCV
11
GND
13
GNDS
14
CCI
15
FB
17
OAIN+
16
OAIN-
19
D5
20
D4
21
D3
22
D2
23
D1
24
D0
25
VROK
7
OFS
PR15
0_0402_5%
1 2
PR165
100K_0402_1%
1 2
1 2
13
D
2
G
S
2N7002_SOT23
MAX1546
PR161
150K_0402_1%
PR168
9.31K_0603_1%
PR132
1 2
0_0402_5%
PR227
1 2
0_0402_5%
CORE_REF <57>
FB
SKIP
SUS
BSTM
LXM
DHM
DLM
VDD
BSTS
DHS
LXS
DLS
PGND
CSP
CSN
CMN
CMP
OAIN+
PL12
PR146
PC124
1 2
0.47U_1206_16V7K
+CPU_B+
OAIN+
PL13
1 2
PR162
1K_0603_1%
PC141
1 2
0.47U_1206_16V7K
+5VS_CORE
12
PR136
100K_0402_5%
1
D
G
2
12
PC116
12
12
PC131
PQ45
S
3
2N7002_SOT23
PC117
10U_1210_25V6K
1 2
12
PR110
H_BOOTSELECT<4>
5.1_0402_1%
PR111
1 2
33_0402_1%
12
PR153
499_0402_1%
OAIN+
PC132
10U_1210_25V6K
13
D
PQ20
2
G
2N7002_SOT23
S
PR171
1 2
1k_0603_1%
13
D
PQ40
2
G
2N7002_SOT23
S
PR173
1 2
1k_0603_1%
+CPU_B+
12
PC118
10U_1210_25V6K
PR145
0.0015_2512_1%
1 3
D
12
PC133
10U_1210_25V6K
12
12
12
PC120
PC119
10U_1210_25V6K
2
G
2N7002_SOT23
S
12
PR164
PQ43
499_0402_1%
OAIN-
12
10U_1210_25V6K
1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
2200P_0402_50V7K
12
PD27
EC31QS04
12
PC134
2200P_0402_50V7K
12
H_BOOTSELECT=1
H_BOOTSELECT=0
FB
OAIN-
OAIN+
2.7K_0603_1%
12
PR180
12
PC182
1000P_0402_50V7K
1 2
1 2
0_0402_5%
PR245
PIR POWER 92.08.04
FBM-L18-453215-900LMA90T_1812
0.1U_0805_25V7K
+VCC_CORE
PC135
0.1U_0805_25V7K
+VCC_CORE
PR244
0_0402_5%
PL11
12
PC130
100U_25V_M
+VCC_CORE
1
+
2
PRESCOTT
NORTHWOOD
VCCSENSE <5>
B+
DPRSLPVR<26>
+5VS_CORE
12
SKIP# <57>
4
S0
5
S1
18
3
36
V+
26
27
28
29
30
35
33
34
32
31
40
39
38
37
PC140
470P_0402_50V7K_A34
PR141
1 2
0_0402_5%
0_0402_5%
PR148
1 2
100P_0603_50V8G
12
1 2
100P_0603_50V8G
1 2
12
0_0402_5%
PR163
1 2
0_0402_5%
PR166
CPUCLK_STP# <5,11,26>
12
1 2
0.1U_0402_10V6K
PC115
2.2U_0805_10V6M
1
PD28
12
CHP202U_SC70
3
2
12
BSTM
PC128
0.1U_0402_10V6K
12
PC129
4700P_0402_25V7K
DLS<57>
CS+ <57>
1 2
0_0402_5%
PC138
PR156
0_0402_5%
PR157
CS- <4,5,6,7,8,26,57>
CM-
CM+
PC181
BSTM
DLM<57>
+5VS_CORE
PC125
PR135
100K_0402_5%
PQ26
1
C
E3B
1 2
PQ28
PR155
1 2
0_0603_5%
2
MMBT3904_SOT23
PR143
0_0603_5%
578
3 6
241
578
3 6
241
IRF7832_SO8
PIR POWER 92.04.18
PIR POWER 92.04.16
CORE_REF
PQ44
S3G
2N7002_SOT23
PQ27
SI7392DP_SO8
1 2
12
PD26
EC31QS04
IRF7832_SO8
PD29
PQ32
IRF7832_SO8
EC31QS04
12
1
D
PR154
100K_0402_1%
1 2
12
PR133
PQ29
PQ31
IRF7832_SO8
1 2
578
5
3
241
100k_0402_5%
5
3
241
3 6
241
PQ30
SI7392DP_SO8
578
3 6
241
PR167
100K_0402_5%
2
SKIP#
0.7U_ETQP2H0R7BFL_31A_20%
12
1K_0603_1%
CM+ <57>CM- <57>
PR159
100K_0402_1%
0.7U_ETQP2H0R7BFL_31A_20%
12
PIR POWER 92.04.16
Title
CPU_CORE(1)
Size Document Number Rev
LA-1811 0.7
A3
Date: Sheet
星期四
07, 2003
八月
of
56 66,
Page 57
DLM<56>
CORE_REF
>
200K_0603_1%
PC170
100P_0603_50V8J
12
100P_0603_50V8J
PR207
12
+VCC_CORE
12
PR184
2200P_0402_50V7K
200K_0603_1%
12
PR189
49.9K _0402_1%
PC156
0_0603_5%
+VCC_CORE
12
2200P_0402_50V7K
12
PR210
49.9K_0603_1%
+5VS_CORE
12
2.2U_0805_10V4Z
PR187
0_0603_5%
@1SS355_SOD323
1 2
PC153
DLS<56>
+5VS_CORE
1 2
12
PC158
2.2U_0805_10V4Z
PR188
0.22U_0603_16V7K
1 2
@1SS355_SOD323
1 2
PC167
PR172
1 2
0_0603_5%
12
10_0603_1%
PR176
PC149
1 2
12
0_0603_5%
PC151
0.22U_0603_16V7K
1 2
PD35
1 2
1 2
PR183
20K_0603_1%
PR196
0_0603_5%
1SS355_SOD323
12
PR198
10_0603_1%
PR201
1 2
12
0_0603_5%
PC165
PD41
1 2
1 2
PR206
20K_0603_1%
1SS355_SOD323
11
18
12
PR178
19
PD39
11
18
12
19
PD33
7
3
6
8
7
3
6
8
VDD
LIMIT
VCC
POL
TON
COMP
ILIM
GND
12
VDD
LIMIT
VCC
POL
TON
COMP
ILIM
GND
12
5
S
4
D8D7D6D
S1S3G
S
2
5
IRF7832_SO8
5
4
PQ34
SI7392DP_SO8
0.7U_ETQP2H0R7BFL_31A_20%
3
241
5
D8D7D6D
S1S3G
S
PQ36
4
2
5
PQ37
SI7392DP_SO8
3
241
5
D8D7D6D
S1S3G
S
IRF7832_SO8
PQ39
4
2
12
PD36
IRF7832_SO8
EC31QS04
0.7U_ETQP2H0R7BFL_31A_20%
12
PD42
EC31QS04
IRF7832_SO8
12
1K_0603_1%
12
1K_0603_1%
0.47U_1206_16V7K
1 2
PL14
PC152
PR181
1 2
0.47U_1206_16V7K
PL15
PR204
PC166
1 2
12
12
PC145
10U_1210_25V6K
12
PC159
10U_1210_25V6K
20
PU10
17
V+
TRIG
BST
DH
LX
DL
PGND
CS+
CS-
CM+
CM-
DD/
13
20
PU11
V+
TRIG
BST
DH
LX
DL
PGND
CS+
CS-
CM+
CM-
DD/
13
MAX1980
SKIP#
MAX1980
16
14
15
10
9
5
4
1
2
17
16
14
15
10
9
5
4
1
2
PR177
1 2
0_0603_5%
PR199
1 2
0_0603_5%
12
PC150
0.22U_0603_16V7K
12
PC154
1000P_0603_16V7K
12
PC155
1000P_0603_16V7K
12
PC164
0.22U_0603_16V7K
12
PC168
1000P_0603_16V7K
12
PC169
1000P_0603_16V7K
CM+ <56>
CM- <56>
CS+ <56>
CS- <4,5,6,7,8,26,56>
PR174
1 2
0_0603_5%
PQ35
PR200
1 2
0_0603_5%
D8D7D6D
S1S3G
2
PQ38
+CPU_B+
12
12
12
12
PC147
PC146
12
PC160
10U_1210_25V6K
10U_1210_25V6K
+CPU_B+
12
PC161
10U_1210_25V6K
10U_1210_25V6K
PC148
2200P_0402_25V7K
PC162
12
2200P_0402_25V7K
PC144
0.1U_0805_25V7K
+VCC_CORE
12
PC163
0.1U_0805_25V7K_V2
+VCC_CORE
SKIP# <56>
Compal Electronics, Inc.
Title
+CPU_CORE(2)
Size Document Number Rev
Date: Sheet of
星期四
07, 2003
八月
57 66,
0.7
Page 58
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
1 0.2
54,55,
56,57
2
Title
wrong layout
pad
DPRSLPVR56 03/25/2003
03/25/2003 Compal
Owner
Compal
wrong layout pad
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
3
4
57 Compal Change Netname of +5VS_CORE
CPU VR-Cont.
5 51 RTC charger Add PR230
C C
6 re-located both PL10 and PQ21, PQ23
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
03/25/2003
Compal
Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
Add PJP14
as well as 1.2VS_VGA related power circitry
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal
and add PR236 for SUSP# signal
Solution Description Rev.Page#
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Request
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期四 八月
LA-1811
1
58 66, 07, 2003
0.7
of
Page 59
1
2
3
4
5
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)
2.Modify the A udio r ela ted s chem atic for C usto mer request . <Page 37> 92.03.17.
-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
3.Change the USB 2. 0 C ont rol ler c hip from ATI to NEC and modify the net for Custom er request .
1 1
<Page 26,27, 36,44> 92.03.18.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,
U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
4.Modify the A udio r ela ted s chem atic for C usto mer request . <Page 37,38> 92.03.20.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)
-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.
-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)
-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
6.Modify the US B2. 0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) .
(Modify CKT,BOM&Layout)
2 2
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net .
(Modify CKT,BOM&Layout)
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request .
<Page 10> 92.03.21.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.
-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)
9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
10. Modify the ON1 r elat ed to spee d up th e pow er se que nce for ATI request . <Page 48,54> 92.03.23.
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);
Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify p owe r s our ce CAP .'s value by Brian . <Page 26,49> 92.03.24.
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348
3 3
from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
12. Del Via Hole on sc hema tic f or M E modify . <Page 41> 92.03.24.
-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
13.Modify t he Mi niP CI and BlueTooth conn related for Custom er request . <Page 43,44> 92.03.24.
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)
-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
14.Swap the U SB2 0*P 3* and USB20*P5* for Customer request . <Page 44> 92.03.24.
-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
A-TEST SMT BUILT
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;
Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;
R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;
R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
16.Modify th e s che ma ti c H _BOO TS ELECT related by Power Team . <Page 04> 92.03.25.
-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) .
4 4
(Modify CKT,BOM&Layout)
-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% .
(Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.
-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),
C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
1
2
18. Modify powe r s our ce Re sis tor an d CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K
to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)
-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 r elat ed to spee d up t he pow er se quen ce for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.
-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.
-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change th e R esi sto r' s value for ATI recommend . <Page 17 > 92.03.26.
-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.
-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.
-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
24. Change the p ower s eque nce r elat ed pa rt's powe r sour ce by Brian . <Page 5,37,48> 92.03.27.
-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.
-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K .
(Modify CKT&BOM)
-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify t he SPD IF rel ate d s che matic for Custom er request . <Page 37,41> 92.03.28.
-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify t he NEC US B2. 0 C ont rol ler Ch ip rel a ted schematic for Customer request . <Page 36> 92.03.28.
-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) .
(Modify CKT,BOM&Layout)
-Add R1104(@0_0402_5%) . (Modify CKT&Layout)
-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.
-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the rela ted s chem ati c aft er B rian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.
-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the rela ted s chem ati c aft er Lay out c heck <Page 44> 92.03.31.
-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.
-Update JP40 . (Modify CKT&Layout)
32. Modify the schem ati c for cost down . <Pa ge 10,12,26,37,> 92.04.04.
-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(1)
星期四 八月
LA-1811
5
of
59 66, 07, 2003
0.7
Page 60
1
2
3
4
5
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connect or JP38 PCB Footprint error. <Page 40> 92.04.09.
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE
Circuit)
2.LED Circui t t o P ower Button(PRES)modify . <Page 42, Page 46> 92.04.09.
-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)
1 1
-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_V GA Di scha rge Ci rcui t. < Pag e 49> 92.04.09.
-Add +1.2VS_ V GA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.
-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
5.PCMCIA U37 N ET S1 _CE 2# & S1_CE1# Sweep. <Page 31> 92.04.09.
6. MDC(JP17) N et AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.
-Update BOM add R326. (Modify EE Circuit)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.
-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)
BHR60 from DB-2 to SI -1 S TEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switc h U 53 PCB Footprint error. <Page 12> 92.04.09.
-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.
-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.
-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES
85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
5. Change BOM & L ayout LED D57 Footprint . <Page 42> 92.04.15.
-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
6. Change Lay out Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.
-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change Lay out Fr ontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.
-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
2 2
9. Add SUSP# pull Down. <Page 46> 92.04.14.
-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_S TP# pu ll Hi gh C ircuit. <Page 26, 5> 92.04.14.
-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)
-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
-Add CPUCLK_STP# s eria l resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
12. SIO Circu it All P ower Plan +3V -> +3VS. <Page 39> 92.04.15.
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.
-Add USB Const ra l or U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)
-Update BOM R1046 -> @. (Modify EE Circuit)
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
3 3
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
17. Change BO M D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
18. Change BOM C 191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BO M C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
25. Change BOM C 966 22U -> 0.1U. <Page 18> 92.04.18.
4 4
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.
1
2
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期四 八月
LA-1811
5
of
60 66, 07, 2003
0.7
Page 61
1
2
3
4
5
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
BHR60 from DB-2 to SI -1 S TEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->
AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
1 1
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull
High +3V. <Page 41> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
2 2
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R 40 @ - > Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI ad d R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI chan ge D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R 623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.
3 3
2. Change C963 -> @. <Page 41> 92.04.28.
3. Change C974 -> @. <Page 17> 92.04.28.
4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.
5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.
6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.
7. DEL R761,R762 <Page 37> 92.04.28.
4 4
----PLEASE SEE NEXT PAGE
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期四 八月
LA-1811
5
0.7
of
61 66, 07, 2003
Page 62
1
2
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR
<92.05.07.~92.05.30. >
1 Prevent CPUCLK_STP# abnormal state happened 5 Change R1125 from 4.7K to 12K
3
Reason for change PAGE Modify ListFixed IssueItem
4
5
M.B. Ver.
0.5
26 Delete R1126
29 Change R40 from 10K to 1K
1 1
2
3
Prevent power leakage
Power saving 7 Change the power of Fans from +5VALW to +5VS 0. 5
7 Change the power of U8 from +3VS to +3VALW
0.5
ATI recommendation 8 Add C974 0.54
Add VGA DRAM size detect function5 17 A dd R 1149 for 128MB VGA DRAM (un-populate for 64MB) 0. 5
6 Add CS1# for Hynix 8Mx32 VGA DRA M
18, 19,
22, 23
0.5Add Nets: NMCSA1# and NMCSB1#
7 Change M9+X VGA_CO RE from +1.5VS to individual power source 21 Delete JOPEN3 0.5
8
2 2
Update with Item23
10 Prevent DPRSLPVR abnormal state happened Cha nge R 1001 from 100K to 47K, R1002 from 0 to 47K 0. 5
11 Using rechargeable RTC battery for HP's request Delete D66, D7 1 and D72; Add D 91 (BAS40-04, the same as LA-1761 D30); Change
12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798
13 Enhance brightness of blue LEDs 0.5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,
3 3
Delete useless components
5 Delete R538
25 Delete C96
27 Delete Q114, Add R1145
25
Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5Solve power leakage from CRT9
26
BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)
from 22u to @10u; Change C801 from 1000p to @1000p
42, 45
R885, R888, R889, R890, R925 and R1136 to 220
44
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;
Change JP42.12 from PAV_GND to PAV_LEDVCC; Cha nge JP42.13 from PMLED_1 to
PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to
PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
0.5
0.526
0.5
14 Solve PWR_ACTIVE LED function fail issue 4 2 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0.5
46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change
U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to
PWR_ACTIVE_PAV#
15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5
16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0 .5
17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0.5
18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5
19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5
4 4
1
20 Decrease Audio AMP Ga in 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期四 八月
LA-1811
5
of
62 66, 07, 2003
0.7
Page 63
BHR60 from SI-1 to DB( 15 .4") LA-1811 REV:0.4 -> 0.5
1
HW PIR <92.05.07.~92.05.30. >
21 RTL8101L no need transistor for 3.3V to 2.5V anymore 3 4 Delete Q55, R944 and C668
2
Reason for change PAGE Modify ListFixed IssueItem
3
4
5
M.B. Ver.
0.5
Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation
Change PC B Footprint from SUYIN_020167MR004SX01ZR_4P to
22
1 1
23
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0 . 5
44
suyin_020167mr004s511zu_4p for JP18, JP19 and JP20
0.5Connector Sp ec. cha nge for ME's re quest
Delete useless components with BOM 1 0 Delete R574, R1086 and C952 0.524
24 Delete R210 for UMA only
Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.525
Add components for EMI 37 Add R1152 0.526
40 Add L65 ~ L78
40 Add L79 ~ L97
Solve DOS cold-boot shunt down issue 7 Delete C256 0.527
BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6
HW PIR <92.06.20.~92.07.03. >
2 2
Decrease overshoot & undershoot 2 5 Add R1153 a nd R1154 0.628
Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.629
Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0. 630
40The pin-de finit ion o f FDD conn. was error on rev0.5 M/B31 0.6Correct the pin-definition for JP38
32 0.6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation
33 0.6Change R880 from 10K to 470Enhance brightness of Docking LEDs
40
41
44To support wak e-up function with TP Change TP power from +5VS to +5V
5Delete useless components Delete R535, R536, R991 and R992
0.634
0.635
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251
3 3
20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
38 Delete R1142
39 Delete RP 153 and R1132
36 To improve RTC accuracy 2 6 Change Y1 from +/-20ppm to +/-10ppm
37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST#
0.6
0.6
Add components for EMI38 37 Add L98 and L99 0.6
40 Add C975, C976, CP15~CP17
4 4
39 Improve Audio quality
Delete C753~C756; Add R1165~R1168 and C97937
38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3
0.6
41 Add R1161
40 42 Add D92
41 Change R904 from 91K to 47K49Mod ify +5V pow er-up timing to lead + 3V
1
2
Add components for ID & ME
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期四 八月
LA-1811
5
of
63 66, 07, 2003
0.7
Page 64
BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7
1
HW PIR <92.07.03.~92.08.08. >
42 Correct Y1 a nd Y3 pin-out 26 Using pin-1 and pin-2 of these crystals
2
Reason for change PAGE Modify ListFixed IssueItem
3
4
5
M.B. Ver.
0.7
46
Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
43
1 1
44
ATI Product Advisory, refer to PA_218IXP0T1
Solve CD-ROM audio noise issue 30 Delete C11 0.7
44
0.7
Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0 .745
For EMI 38 Add L100, L101, L102 and L103 0.746
For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.747
ATI recommendation 2 7 Change RP12 from 10K to 2.2K 0.748
46 Add R1 175
Delete useless components 46 Delete D69 and D70 0.749
To support wake-up function with TP 4 6 Delete RP154; Add R1169, R1170, R1171 and R1172 0. 750
2 2
Solve M10 can't power up issue 4 9 Delete C844 0.751
Change R901 from 27K to 6.8K
Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0.752
Modify brightness of LED s 42 Change Transistors from BJT to PMOS and R esister s value for Pav; Change Resisters value for Pre. 0 . 753
45
Fast power on for battery only 45 Change R306 from 100K to 470; Delete Q112 0 .754
Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.755
Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.756
Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0 . 757
3 3
Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0.758 37
Improve USB2.0 signal quality Change R 1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 0. 759
36
4 4
Title
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
H/W2 EE Dept. PIR SHEET(2)
星期五 八月
LA-1811
5
0.7
of
64 66, 08, 2003
Page 65
5
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
1 0.2
54,55,
56,57
2
Title
wrong layout
pad
DPRSLPVR56 03/25/2003
03/25/2003 Compal
Owner
Compal
wrong layout pad
change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
3
4
57 Compal Change Netname of +5VS_CORE
CPU VR-Cont.
5 51 RTC charger Add PR230
C C
6 re-located both PL10 and PQ21, PQ23
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
03/25/2003
Compal
Change the netname +5VS_CORE for power
consumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
Add PJP14
as well as 1.2VS_VGA related power circitry
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP
to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V
and add a PR236 for SUSP# signal
10 54 +1.5VALWP
04/16/2003 Compal
change 1.5V time sequence
and add PR236 for SUSP# signal
Change power time-sequence of 1.5VSP input power
Solution Description Rev.Page#
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.4
Request
11 04/16/2003 Compal
56 CPU DPRSLPVR
B B
12 Change power JUMP SIZE to follow new jump role
13 CPU DPRSLPVR56
14
15
16 04/30/2003 Compal
17
56
5554
PWR JUMP
04/16/2003
Compal
04/18/2003 Compal
50
Vin DETECTOR 04/30/2003 Compal
50 Precharge 04/30/2003 Compal
51
Battery OTP
51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N
18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71
19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2
A A
5
04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V
Change DPRSLPVR design
For DFX issuse
Change DPRSLPVR design
to make ACIN to enable to pull low
BOM error
To change feekbeck time
4
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode
0.4
0.4
Reserve DPRSLPVR function
and add a PR136 for +5VS_CORE signal
Change PR8 form 10k_0603 to 0K_0603
Change PR1 from 10k_0603 to 100k_0603
Change PC20 from .22u to 1u ;PR40&PR42 from 100k to
150k; PC80 from 1u to .47u
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Title
Size Document Number Rev
3
2
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期四 八月
LA-1811
1
65 66, 07, 2003
0.7
of
Page 66
5
_S
4
Version Change List ( P. I. R. List ) for Power Circuit
3
2
1
Item Issue DescriptionDate
D D
21
Title
Owner
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors
Add
Precharge
22 50
23 51
detector
Colok THROTTLING
24 56,57 CPU_CORE(1&2) 05/16/2003 Compal
25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5
C C
26 55
27
53 3V/5V/12V
1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA
05/16/2003 Compal System can't power on by battery
05/16/2003 Compal
To modify the circuit
Change the freqeuce 300k to 200k
07/4/2003 Compal
To modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)
Add PR194(1K)
,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
Change PR5 from 150k to 180k
Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form
84.5K to 11.5K
delet PR138 ; add PR187(0_0603)&PR188(0_0603)
add PR124(11.5k_0603) 0.5
,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet
PR86,PR88,PR90,PR93
28
29 56,57
30
56 CPU_CORE
CPU_CORE(1&2) 07/4/2003
07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/A
Compal
To improve the CPU_CORE effecient
Change PR158,PR180 from 2k to 3.4k 0.6
Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6
50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)
Solution Description Rev.Page#
0.4
0.5
0.5
0.5
0.6
0.7
Request
31
B B
32
52
53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issue
Charger 08/4/2003 Compal
To modify the Precharge circuit
33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to
-1.5mV/A, and senes CPU VCC and VSS
34 52 Charger 08/4/2003 Compal
A A
5
To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7
4
3
Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA
0.7
change PR81(1.27k) ,PR78(1.54K),PR79(0_0402)
,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add
PR241(1.24k),PR242(620 ohm),PR243(698 ohm)
0.7
Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)
and PR245(0 ohm)
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Changed-List History-1
星期四 八月
LA-1811
1
0.7
66 66, 07, 2003
0.7
of
Page 67
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