COMPAL LA-1711-REV Schematics

5

[e-mail]

D D

4

3

2

1

Prescott & Springdale Schematic with Capture CIS
and Function field

C C

uFCPGA Prescott

2003-07-23

Cature library ball out check document

Prescott : Prescott processor Electrial,Mechanical and
Thermal Specification Rev0.5 [Check by HW:Henry,Steve]

B B

Springdale(GMCH): Springdale GMCH External Design
Specification (EDS) REV1.0 [Check by HW: Henry,Rita]

ICH5: N/A

REV: X02-D

@ : Depop Component
1@ : Depop on Nimitz(Inspiron)
2@ : Depop on Beijing(Precision)

A A

Compal Electronics, Inc.

Cover Sheet

LA-1711

1

160Wednesday , July 23, 2003

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5

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITH ER THIS S HEET NOR T HE INFORMA TION IT CONT AINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMP AL ELEC TRONICS , INC.

3

2

Size Document Number Re v

Dat e: Sheet

5

[e-mail]

4

3

2

1

Compal confidential

D D

ADT7460 Thermal sensor

page 19

HA#( 3..31)

VGA
Board

[CRT CONN. & TV-OUT]

C C

AGP CONN.

page 18

AGP4X/8X(1.5V)

Prescott

478 uFCPGA CPU

page 7,8,9

System Bus

533/800MHz

Springdale

GMCH

932 FC-BGA

page
10,11,12,13

HD#(0..63)

Block Diagram

Memory
BUS(DDR)

2.5V
266/333/400MHz

2.5V
266/333/400MHz

Channel A SO-DIMM

BANK 0, 1, 2,3

Channel B SO-DIMM

BANK 0, 1, 2,3

page 15

page 16

Fan Control

page 14

Clock Generator

CK409

page 6

HUB Link

MINI PCI

page 32

PCI BUS

IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)

B B

LAN
BCM5705M
BCM4401

Transformer

RJ45

page 28

page 29

page 29

CardBus Controller

PCI7510/PCI4510

1394, Smart
card

page31

3.3V 33MHz

page 30

Slot 0

page31

X BUS

LPC BUS

3.3V 33MHz

SST39VF080

A A

5

page 35

Touch Pad

page 35

4

1.5V
66Mhz
266MB/S

Macallen

LPC to X-BUS
& Super I/O

ICH5

460 BGA

Page
33,34

Int.KBD

3.3V 24.57 6MHz

3.3V ATA100

Page
20,21,22

SATA

ATA100

ATA100

HDD

page 21

CDROM

USB
FDD

page 23

USB2.0

page 26

page 27

page 35

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

USBPORT 4

USBPORT 1

USBPORT 2

USBPORT 3

USBPORT 4

USBPORT 6

BT

BACK

DOG

MOD

BACKUSBPORT 5

BACK

2

AC97
Codec

STAC9750

AMP& Phone
Jack Interface

page 25

AC-LINK

MDC

page 27

page 24

Subwoofer

page 50

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

LA-1711

DC IN

BATT
IN

3.3V/5V

1.5V/+VTT_GMCH

1.25V/2.5V

VCORE

VCORE_CTRL

CHARGER

Block Diagram

1

260Wednesday, July 23, 2003

page 41

page 42

page 43

page 44

page 45

page 47

page 46

page 48

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[e-mail]

PM TABLE

power
plane

State

D D

S0

S1

+3VALW

+5VALW

+3VSUS

+5VSUS

+2.5V_MEM

+3.3VRTC

+RTC_PWR

V_1P25V_DDR_VTT

ON

ON

ON

ON

+3VRUN

+5VRUN

+1.5VRUN

+VCC_CORE

+12V

+VCCVID

ON

ON

4

Bring up

SST-Build

PT-Build

ST-Build

QT-Build

Pilot-Build

3

MCH Rev. ICH5 Rev.

RG828SDGES FW82801EB

RG828SDGP

A2(QE45)

A1(QE16ES)A1(QE18)

FW82801EB

A3(QE51ES)

2

1

S3

S5 S4/AC

S5 S4/AC don't exist

ON

ON

ON

OFF

OFF

OFF

OFF

OFFOFF

Configuration List

BOM Structure

TABLE

PCI

C C

PCI DEVICE

CARD BUS

LAN

MINI PCI

IDSEL

AD17

AD16

AD19

REQ#/GNT#

1

4

3

VGA

B B

USB

A A

TABLE

USB PORT#

0

1

2

3

4

5

6

7

DESTINATION

Reserved

BT

BACK

DOG

MOD

BACK

BACK

Reserved

Note : "@" means all model depop

"1@" means Nimitz depoped only

"2@" means Beijing depoped only

Model

Function

Smart Card

LAN

Dog House

PIRQ

D,C

C

D,B(NP)

A,B(NP)

Nimitz Beijing

No

10/100
(4401)

YES YES

YES

1000
(5705M)

Function

5

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-1711

1

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4

3

2

1

RBAT

D D

ADAPTER

+RTCSRC

+RTC_PWR

+5VALW

+5VSUS

PWR_SRC

+3VALW+3.3VRTC

BATTERY

+3VSUS

SUSPWROK

DOCK _PWR_SRC

C C

+5VSUS

B B

+3VSRC

+2.5VMEMP

+VCCP

+VCC_CORE

+12V

+5VHDD

A A

+5VMOD

5

+5VRUN

VDDA

4

+3VRUN +3VSUS+1.5VRUN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

+2.5V_MEM

V_1P25V_DDR_VTTV3P3LAN

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

Power Rail

LA-1711

1

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4

3

2

1

ICH_SMBCLK

D D

ICH5

ICH_SMBDATA

+3VSUS

7002

+3VRUN

CK_SCLK

CLK GEN.

CK_SDATA

7002

V_3P3_LAN

DIMM0

DIMM1

7002

7002

LAN_SMBCLK

NIC

LAN_SMBDATA

7002

CLK_SMB

+3VALW

7002

DAT_SMB

7002

C C

24C05

ADT7460

AD7414 PCA9561

DH PORT

SIO

Macallen

SBAT_SMBCLK

SBAT_SMBDAT

+5VALW

VGA

7002

MPCI

EC SMBus Address

CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)

DDR Temp.(AD7414ART-0) : 90h/91h (P.15)

CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)

EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)

VID Select(PCA9561PW) : 9Ch/9Dh (P.38)

B B

PBAT_SMBCLK

1'nd

PBAT_SMBDAT

+5VALW

BATTERY

CHARGER

A A

Compal Electronics, Inc.

SMBUS TOPOLOGY

LA-1711

1

560Wednesday, July 23, 2003

X02-D

of

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Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

+3VRUN

5

4

3

2

1

Place near each pin
W>40 mil

1

C587

0.1U_0402_10V6K~D

2

36

42

48

VDD_48

VSS_CPU

VDD_SRC

VDD_CPU

VDD_CPU

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

48/66MHZ_OUT/3V66_4

66MHZ_OUT3/3V66_3

66MHZ_OUT2/3V66_2

66MHZ_OUT1/3V66_1

66MHZ_OUT0/3V66_0

PCICLK_F2

PCICLK_F1

PCICLK_F0

PCICLK6

PCICLK5

PCICLK4

PCICLK3

PCICLK2

PCICLK1

PCICLK0

VSS_48

VSS_SRC

VSS_IREF

CY28409ZCT_TSSOP56~D

39

53

1

C553

2

45

47

46

44

43

41

40

29

27

26

23

22

9

8

7

20

19

18

15

14

13

12

1

C585

0.1U_0402_10V6K~D

2

0.1U_0402_10V6K~D

CK_CPU2

CK_CPU2#

CK_CPU1

CK_CPU1#

CK_CPU0H_STP_PCI#

CK_CPU0#

CLK66M_OU T3

CLK66M_OU T1

CLK66M_OU T0

PCICLK_F2

PCICLK6

PCICLK5

PCICLK2

PCICLK1

PCICLK0

1

C554

0.1U_0402_10V6K~D

2

1

C193

4.7U_0805_6.3V6K~D

2

1 2

1 2

1 2

1 2

1 2

1 2

R543

1 2

33_0402_5%~D

R547

1 2

33_0402_5%~D
R546

1 2

33_0402_5%~D
R540

1 2

33_0402_5%~D

R545

1 2

33_0402_5%~D
R542

1 2

33_0402_5%~D

R541

1 2

33_0402_5%~D
R544

1 2

33_0402_5%~D

1 2

R587 33_0402_5%~D

2

Trace wide=20 mils

1

C552

0.1U_0402_10V6K~D

2

R488

33_0402_5%~D

R472

1 2

49.9_ 0402_1%~D

R473

1 2

49.9_ 0402_1%~D

R489

33_0402_5%~D

R490

33_0402_5%~D

R474

1 2

49.9_ 0402_1%~D

R475

1 2

49.9_ 0402_1%~D

R491

33_0402_5%~D

R492

33_0402_5%~D

R476

1 2

49.9_ 0402_1%~D

R477

1 2

49.9_ 0402_1%~D

R493

33_0402_5%~D

1

C551

0.1U_0402_10V6K~D

2

CK_BCLK

CK_BCLK#

CK_ITP

CK_ITP#

CK_HCLK

1

C588

0.1U_0402_10V6K~D

2

CK_BCLK <7>

CK_BCLK# <7>

CK_I TP <8>

CK_ ITP# <8>

CK_HCLK <10>

Place near CK409

CK_HCLK#

Title

Size Document Number Re v

Date: Sheet

CK_ HCLK # <10>

CK_66M_AGP <18>

CK_66M_MCH <12>

CK_66M_ICH <20>

CK_33M_ICHPCI <20>

CK_33M_MINIPCI <32>

CK_33M_CBPCI <30>

CK_33M_LANPCI <28>

CK_33M_SIOPCI <34>

CK_33M_CPLD <36>

Compal Electronics, Inc.

LA-1711

Clock Generator

1

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1
2

4

5

51
56

21
49
50

35

28
30

37

38

31

32

52

55

54

3

CK_VDD_MAIN+3VRUN

2

C204

U39

REF_1
REF_0

XTAL_IN

XTAL_OUT

SEL0
SEL1

PWRDWN#
PCI_STP#
CPU_STP#

VTT_PWRGD#

SCLK
SDATA

SRCLKN_100MHZ

SRCLKP_100MHZ

USB_48MHZ

DOT_48MHZ

IREF

VDD_PLL

VSS_PLL

1

C586

0.1U_0402_10V6K~D

1

2

24

16

34

3

VDD_PCI10VDD_PCI

VDD_REF

VDD_3V66

CK409

VSS_REF

VSS_PCI11VSS_PCI

VSS_3V66

6

17

25

33

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

+3VRUN

12

R518

1K_0603_1%~D

CLKSEL0

CLKSEL1

12

R519

2K_0603_1%~D

12

R208

2.49K _0603_1%~D

66 14.3 100/200 48

R215 0_0402_5%~D@

12

R206 0_0402_5%~D

12

R508 0_0402_5%~D

12

R509 0_0402_5%~D@

12

14.3

14.3

+3VRUN

12

R192
1K_0603_1%~ D

H_STP_PCI#

+3VRUN

12

R218
1K_0603_1%~ D@

ICH_SLP_S1#

+3VRUN

100K_0402_5%~D

D

1 3

2

2

1 3

D

D

1

G

14.3

12

R524

S

Q68

2N700 2_SOT23~D

G

G

Q69
2N7002_SOT23~ D

S

3

S2

66 14.3 100/2004848

ICH_ SMBDATA

MCH_CLKSEL0 <10>

MCH_CLKSEL1 <10>

REF

100/200

12

R536

100K_0402_5%~D

CPU_CLKSEL0 <8>

CPU_CLKSEL1 <8>

Bring Up: Populate R509 (Because CPU
is Nor thwood-MT, Frequency 533MHz)

Close to X'tal pin

48

Place near CK409

+3VRUN

CK_SDATA

CK_SCLKICH_SMBCLK

CK_14M_ICH<21>

CK_14M_SIO<34>

CK_14M_CODEC<24>

10P_04 02_50V8J~D@

10P_04 02_50V8J~D@

1 2

CK_100M_ICH#<21>

CK_100M_ICH<21>

Check SPEC (250mA,300 ohm)

49.9_ 0402_1%~D

1 2

CK_48M_ICH<20>

CK_48M_SCR<30>

L45

BLM11A601S_0603~D

1 2

L17

BLM21 PG600SN1D_0805~D

1 2

10U_1206_6.3V7K~D

CK_XTAL_IN and CK_XTAL_OUT equal length traces,
Please place R_J between Pins 4,5 of CK409 Pins
before X'tal

R538

33_0402_5%~D

33_0402_5%~D

33_0402_5%~D@

C597

C598

R479

R478

49.9_0402_1%~D

12

R539

12

R611

12

12

12

X6

14.31 818MHz_20P_1BX14318CC1A~D

12

Place crystal within
500 mils of CK409

ICH_SLP_S1#<21>

CLK_STP_CPU#<36>

CK_VTT_PG#<37>

1 2

33_0402_5%~D

1 2

33_0402_5%~D

33_0402_5%~D

33_0402_5%~D

CLK_VDD_PLL

1

C166

10U_1206_6.3V7K~D

2

R485

R484

CLKREF1
CLKREF0

CK_XTAL_IN

2M_0603_5%~D @

CK_XTAL_OUT

ICH_SLP_S1#

CLK_STP_CPU#

CK_VTT_PG#

R501

12

R500

12

R199

1 2

475_0603_1%~D

1

C550

0.1U_0402_16V4Z~D

2

R548

CLKSEL0
CLKSEL1

CK_SCLK
CK_SDATA

CK_SATA#

CK_SATA

CLK48M_OU T0

CLK48M_OU T1

12

R_J

12

R529

D D

1K_0603_1%~D

12

R530

2K_0603_1%~D

12

R214

2.49K _0603_1%~D

SL0 SL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot

0 0 100 66 14.3 14.3 100/200

C C

0 MID REF REF REF REF REF

0 1 200

1 0 133 66 14.3

1 1 166

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

B B

ICH_SMBDATA<15,16,21,32>

A A

ICH_SMBCLK<15,16,21,32>

2N7002

5

4

5

4

+VCC_CORE

3

2

1

D D

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

C C

H_REQ#[0..4]<10>

H_ADS#<10>

R339

62_0402_5%@

+VCC_CORE

+VCC_CORE

B B

R371

1 2

1 2

H_BR0#< 10>

H_BPRI#<10>
H_BNR#<10>
H_LOCK#<10>

CK_BCLK<6>
CK_BCLK#<6>

H_HIT#<10>
H_HITM#<10>

H_DEFER#<10>

200_0402_5%

CK_BCLK#

CK_BCLK

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_IERR#

AMP_3 -1565030-1_Prescott~D

AF22
AF23

A10

A12

A14

A16

A18

A20

AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19

C10

C12

C14

C16

C18

C20

D11

D13

D15

D17

D19

D9

VCC_65C8VCC_66

VCC_84

VCC_85

F9

F11

VCC_67

VCC_68

VCC_79E8VCC_80

E20

VCC_69

VCC_78

E18

VCC_70

VCC_77

E16

E10

VCC_71D7VCC_72

VCC_75

VCC_76

E12

E14

VCC_73

VCC_74

D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

H_D#0

B21

D#0

H_D#1

B22

D#1

H_D#2

A23

D#2

H_D#3

A25

D#3

H_D#4

C21

D#4

H_D#5

D22

D#5

H_D#6

B24

D#6

H_D#7

C23

D#7

H_D#8

C24

D#8

H_D#9

B25

D#9

H_D#10

G22

H_D#11

H21

H_D#12

C26

H_D#13

D23

H_D#14

J21

H_D#15

D25

H_D#16

H22

H_D#17

E24

H_D#18

G23

H_D#19

F23

H_D#20

F24

H_D#21

E25

H_D#22

F26

H_D#23

D26

H_D#24

L21

H_D#25

G26

H_D#26

H24

H_D#27

M21

H_D#28

L22

H_D#29

J24

H_D#30

K23

H_D#31

H25

H_D#32

M23

H_D#33

N22

H_D#34

P21

H_D#35

M24

H_D#36

N23

H_D#37

M26

H_D#38

N26

H_D#39

N25

H_D#40

R21

H_D#41

P24

H_D#42

R25

H_D#43

R24

H_D#44

T26

H_D#45

T25

H_D#46

T22

H_D#47

T23

H_D#48

U26

H_D#49

U24

H_D#50

U23

H_D#51

V25

H_D#52

U21

H_D#53

V22

H_D#54

V24

H_D#55

W26

H_D#56

Y26

H_D#57

W25

H_D#58

Y23

H_D#59

Y24

H_D#60

Y21

H_D#61

AA25

H_D#62

AA22

H_D#63

AA24

H_D#[ 0..63] <10>H_A#[3..31]<10>

JCPUA

VCC_0

VCC_1

VCC_2

VCC_3

VCC_4

VCC_5

VCC_6A8VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56B7VCC_57B9VCC_58

VCC_59

VCC_61

VCC_62

VCC_63

K2

A#3

K4

A#4

L6

A#5

K1

A#6

L3

A#7

M6

A#8

L2

A#9

M3

A#10

M4

A#11

N1

A#12

M1

A#13

N2

A#14

N4

A#15

N5

A#16

T1

A#17

R2

A#18

P3

A#19

P4

A#20

R3

A#21

T2

A#22

U1

A#23

P6

A#24

U3

A#25

T4

A#26

V2

A#27

R6

A#28

W1

A#29

T5

A#30

U4

A#31

V3

A#32

W2

A#33

Y1

A#34

AB1

A#35

J1

REQ#0

K5

REQ#1

J4

REQ#2

J3

REQ#3

H3

REQ#4

G1

ADS#

AC1

AP#0

V5

AP#1

AA3

BINIT#

AC3

IERR#

H6

BR0#

D2

BPRI#

G2

BNR#

G4

LOCK#

BCLK0
BCLK1

F3

HIT#

E3

HITM#

E2

DEFER#

VSS_0H1VSS_1H4VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12A3VSS_13A9VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

A11

A13

A15

A17

A19

A21

A24

H23

H26

A26

AA1

AA4

AA11

AA13

AA15

AA17

AA19

AA23

AA26

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

AA7

AA9

AB10

AB12

AB14

AB16

Prescott

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

AB3

AB6

AB8

AB18

AB20

AB21

AB24

AC11

AC13

AC15

AC17

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

AC2

AC5

AC7

AC9

AC19

AC22

AC25

AD10

AD12

AD14

AD16

AD18

AD21

AD23

VCC_64

BOOTSELECT

VSS_54

VSS_55

VCC_81

VCC_82

VCC_83

F13

F15

F17

F19

AD1

AD4

AD8

+VCC_CORE

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

A6 TESTHI11 G HIPull-up 200ohm

TESTHI11

B6 FERR# FERR#/PBE# Pull-up 62ohm

AA20 ITPCLKOUT0 Pull-up56ohm

AB22 ITPCLKOUT1 Pull-up 56ohm

AD2 NC VIDPWRGD Pull-up 2.43K ohm

AD3 NC float VID5 Pull-up1Kohm to

A A

AF3 NC float VCCVIDLB Connect to +VCCVID

AD20 VCCA VCCIOPLLConnect to CPU

VCCIOPLL VCCA

AF23 Connect to CPU

TESTHI12 TESTHI12AD25 DPSLP

Comment Comment

to +VCC_CORE

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

to +VCC_CORE

float

Filter

Filter

Pull-up 200ohm
to +VCC_CORE

5

Prescott
Pin name

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

TESTHI6 Pull-up 62ohm

TESTHI7 Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCCVID

+3VRUN & connect
to PWRIC

Connect to CPU
Filter

Connect to CPU
Filter

COMPAT#

float

Pull-up 62ohm
to +VCC_CORE

Northwood MT
Pin name

FERR#

ITPCLKOUT0

ITPCLKOUT1

NC

NC

NC

VCCA

VCCIOPLL

VSSAE26 VSS Connect to GND OPTIMIZED/

Comment

Connect to PLD
CPUPREF through
0ohm

Pull-up 62ohm
to +VCC_CORE

Pull-up56ohm
to +VCC_CORE

Pull-up 56ohm
to +VCC_CORE

float

float

float

Connect to CPU
Filter

Connect to CPU
Filter

Connect to GND

Connect to PLD
through 0ohm

4

Northwood

Prescott

Northwood
MT

PopPop Pop

Pop

Pop

Pop

Depop

Depop

Pop Pop

Pop

Pop

Pop

PopDepop

Pop

Pop

DepopPop

Pop

Pop

Pop

Pop

Depop

Depop

Depop

Pop

Note: AD2,AD3 pop(bring up)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

VCORE_BOOTSELECT <49>

2

Compal Electronics, Inc.

Title

Prescott Processor in uFCPGA478

Size Document Number Re v

C

LA-1711

Date: Sheet

1

of

760Wednesday, July 23, 2003

X02-D

5

+VCC_CORE

+VCC_CORE

CK_ITP_CPU

14

CK_ITP_CPU#

23

CK_ITP_JITP#

14

CK_ITP_JITP

23

Place near ICH

Place near CPU

1

+

2

ITP_TDO

+VCC_CORE

H_RS#[0..2]<10>

H_TRDY#<10>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21>

H_PWR GOOD<21>

H_STPCLK#<36>

H_RESET#<10>

H_DBSY#<10>

H_DRDY#<10>
CPU_CLKSEL0<6>
CPU_CLKSEL1<6>

H_THERMDA<19>
H_THERMDC<19>

H_THERMTRIP#<21,37>

R338 62_0402_5%

1 2

R341 62_0402_5%

1 2

R337 62_0402_5%

1 2

R346 62_0402_5%

1 2

R343 62_0402_5%

1 2

R342 62_0402_5%

1 2

C368

33U_D2_8M_R35~D

Pop: Prescott
Depop: Northwood

0.1U_ 0402_10V6K~D

R361

150_0402_5%~D

H_RESET#

1 2

R364

47_0402_5%~D

1 2

1 2

R370 2 7.4_0603_1%~D

1 2

R376

39.2_ 0603_1%~D

Close to the ITP

H_SMI#<21>

H_INTR<21>
H_NMI<21>
H_INIT#<21>

H_VCCA

+VCCVID

H_VSSA

C386

VCCSENSE<46>
VSSSENSE<46>

R333

R_D

R97

61.9_ 0603_1%

+VCC_CORE

1

2

ITP_DBRESET#

ITP_BPM#0

ITP_BPM#1

ITP_BPM#2

ITP_BPM#3

ITP_BPM#4

ITP_BPM#5

ITP_TCK

CK_ITP_JITP
CK_ITP_JITP#

ITP_TCK

ITP_TRST#
ITP_TMS
ITP_TDI

R131 62_0402_5%

R129 62_0402_5%

D D

R84 62_0402_5%@

C C

B B

+VCC_CORE

H_FERR#

1 2

H_THERMTRIP#

1 2

R111 130_0402_5%

H_PROCHOT#

1 2

R87 300_0402_5%~D

H_P WRGOOD

1 2

H_RESET#

1 2

10uH, DC current of 100mA parts
and close to cap

+VCC_CORE

L40 10U_LQH31M N100K01_100mA_10%_1206~D

1 2

1 2

L41 10U_LQH31M N100K01_100mA_10%_1206~D

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mils(min)

CK_ITP
CK_ITP#

0_4P2R_0404_5%~D

CK_ITP#

CK_ITP#<6>

CK_ITP

CK_ITP<6>

54.9_ 0603_1%~D

1 2

54.9_ 0603_1%~D

1 2

R363

R358

0_4P2R_0404_5%~D @

ITP_TDO

H_RESET#

RN9

RN8

Close to the ITP

+VCC_CORE

R377

47_0402_5%~D@

R108 150_0402_5%~D

A A

1 2

R379 47_0402_5%~D @

ITP_TMS

12

ITP_TDI

ITP_TCK

12

Close to the CPU

R381

680_0402_5%~D

1 2

Between the CPU and ITP

ITP_TRST#

5

4

H_RS#0
H_RS#1
H_RS#2

H_FERR#

H_P WRGOOD

H_RESET#

H_THERMDA
H_THERMDC

H_THERMTRIP#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

1 2

0_0402_5%~D

CK_ITP_CPU
CK_ITP_CPU#

12

12

R349

61.9_ 0603_1%

AMP_3 -1565030-1_Prescott~D

JITP

28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

4

VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI

AB23

AB25

AD20
AE23

AD22

AC26
AD26

G5

AB2

C6

D1

W5

H5

H2
AD6
AD5

C4

AC6
AB5
AC4

AA5
AB4

D4

C1

D5

AF3

L24

29

30

F1

F4

J6

B6
B2
B5

Y4

E5

B3

A2

Y6

F7
E6

A5
A4

P1

GND6

GND7

MOLEX_52435-2891_28P~D@

JCPUB

RS#0
RS#1
RS#2
RSP#
TRDY#

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCIOPLL
VCCA

VCCSENSE
VSSSENSE
VCCVIDLB

VSSA

ITP_CLK0
ITP_CLK1

COMP0
COMP1

+3VSUS

AE11

AE13

AE15

AE17

AE19

AE22

AE24

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_129F8VSS_130

VSS_131

VSS_132G3VSS_133G6VSS_134J2VSS_135

J22

G21

G24

R152

1 2

10K_0402_5%~ D

VID_PWRGD<46>

Level shift

+CPU_GMCH_GTLREF trace
wide 12mils(min),Space
15mils

3

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B10

B12

B14

B16

B18

B20

B23

B26

C11

C13

C15

C17

C19

C22

C25

D10

D12

D14

D16

D18

D20

D21

D24

E11

E13

E15

E17

E19

E23

E26

F10

VSS_63

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85B4VSS_86B8VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92C2VSS_93

VSS_94

VSS_95C5VSS_96C7VSS_97C9VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117E4VSS_118E7VSS_119E9VSS_120

Prescott

VID0

VID1

VID2

VID3

VSS_136

VSS_137J5VSS_138

VSS_139

VSS_140K3VSS_141K6VSS_142L1VSS_143

VSS_144

VSS_145L4VSS_146M2VSS_147

VSS_148

VSS_149M5VSS_150

VSS_151

VSS_152N3VSS_153N6VSS_154P2VSS_155

VSS_156

VSS_157P5VSS_158R1VSS_159

VSS_160

VSS_161R4VSS_162

VSS_163

VSS_164T3VSS_165T6VSS_166U2VSS_167

VSS_168

VSS_169U5VSS_170V1VSS_171

VSS_172

VSS_173V4VSS_174

VSS_175

VSS_176W3VSS_177W6VSS_178Y2VSS_179

VSS_180

VSS_181

J25

L23

L26

K21

K24

3

N21

N24

M22

M25

+3VSUS

1 2

5

U6A

P

1

O6I

G

SN74LVC2G07DBVR_SOT23-6~D

2

+3VSUS

5

U6B

P

O4I

G

SN74LVC2G07DBVR_SOT23-6~D

2

+CPU_GMCH_GTLREF

C131

0.1U_0402_16V4Z~D

H_VID_PWRGD

T21

P22

P25

R23

R26

R155 10K_ 0402_5%~D

1 2

1 2

+VCC_CORE

R_A

R_B

3

T24

C121

0.1U_0402_16V4Z~D

V23

V26

U22

U25

+3VSUS

VCORE_ENLL <46>

12

R357

200_0603_1%~D

12

R356

169_0603_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

Y5

Y22

Y25

W21

W24

H_VID0<36>
H_VID1<36>
H_VID2<36>
H_VID3<36>
H_VID4<36>
H_VID5<36>

GTL Reference Voltage

Layout note :

2

C369

0.1U_0402_16V4Z~D

1

VID4

AE5

AE4

AE3

AE2

AE1

AD3

1. +CPU_GTLREF Trace wide
12mils(min),Space 1 5mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+CPU_GTLREF

12

R340

0_0603_5%~D

F12

F14

F16

F18

VSS_121

VSS_122

VSS_123

VIDPWRGD

VID5

AD2

1

C372
220P_0402_50V7K

2

2

F22

F25

F5

VSS_124

VSS_125F2VSS_126

VSS_127

OPTIMIZED/COMPAT#

AF4

2

AF26

VSS_128

SKTOCC#

VCCVID

1 2

0_0402_5%~D

DP#0
DP#1
DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

TESTHI9
TESTHI10
TESTHI11
TESTHI12

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

PROCHOT#

MCERR#

SLP#

NC1
NC2
NC3
NC4
NC5

+VCCVID

H_VID_PWRGD

R71

J26
K25
K26
L25

AA21
AA6
F20
F6

AE26

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

E22
K22
R22
W22

F21
J23
P23
W23

L5
R5

E21
G25
P26
V21

AE25

C3
V6
AB26

A22
A7
AF25
AF24
AE21

R_E

R336
681_0603_1%

1 2

@

T1

PAD@

R70 0_0402_5%~D

1 2

H_TESTHI0
H_TESTHI1

H_TEST HI2_7

H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#

H_TESTHI12

ITP_DBRESET#

H_PROCHOT#

RE
Pop: Prescott
Depop: Northwood

+VCCVID

VID5<36,46>

VID4<36,46>

VID3<36,46>
VID2<36,46>
VID1<36,46>
VID0<36,46>

B_VID5
OPEN

2

2

1

1

@

1

+VCC_CORE

12

DPSLP#<36>

+CPU_GTLREF

Pop: Northwood

R_G

R77 62_0402_5%
R344 62_ 0402_5%

R82 62_0402_5%

R354 62_ 0402_5%
R350 62_ 0402_5%
R347 62_ 0402_5%
R382 62_ 0402_5%
R79 62_0402_5%

H_DSTBN#0 <10>
H_DSTBN#1 <10>
H_DSTBN#2 <10>
H_DSTBN#3 <10>

H_DSTBP#0 <10>
H_DSTBP#1 <10>
H_DSTBP#2 <10>
H_DSTBP#3 <10>

H_ADSTB#0 <10>
H_ADSTB#1 <10>

H_ DIN V#0 <10>
H_ DIN V#1 <10>
H_ DIN V#2 <10>
H_ DIN V#3 <10>

ITP_D BRESET# <37>

H_CPUSLP# <36>

R83 62_0402_5%@

1 2

B_VID4
OPEN

2

2

1

1

@

Title

Size Document Number Re v

C

Date: Sheet

Depop: Prescott

1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2

R_H

R380 0_0402_5%~D@

1 2

VID5

VID4

VID3
VID2
VID1
VID0

B_VID3

B_VID2

OPEN

2

1

OPEN

2

2

2

1

1

1

@

Compal Electronics, Inc.

Prescott Processor in uFCPGA478

LA-1711

CPLD Enable
Pop R76, R78

R76
200_0402_5%@

R78 0_0402_5%~D@

1 2

+VCC_CORE

RH
Pop: Prescott
Depop: Northwood MT

CPLD Enable
Pop R380

Closely Pin AE25

C660

12

1000P_0402_50V7K~D@

+VCC_CORE

R37 1K_04 02_5%~D

1 2

R35 1K_04 02_5%~D

1 2

RN7 1K_8P4R_1206_5%~D

B_VID1
OPEN

2

2

1

1

@

1

H_DPSLP#

CP UPR EF# <36>

H_PROCHOT# <10>

45
36
27
18

B_VID0
OPEN

2

2

1

1

@

860Wednesday, July 23, 2003

+3VRUN

X02-D

of

5

4

3

2

1

+VCC_CORE

1

C31
22U_1 206_6.3VAM~D

2

D D

+VCC_CORE

1

C46
22U_1 206_6.3VAM~D

2

+VCC_CORE

1

C381
22U_1 206_6.3VAM~D

2

C C

+VCC_CORE

1

C76
22U_1 206_6.3VAM~D

@

2

1

C27
22U_1 206_6.3VAM~D

@

2

1

C56
22U_1 206_6.3VAM~D

2

1

C411
22U_1 206_6.3VAM~D

2

1

C71
22U_1 206_6.3VAM~D

@

2

1

C28
22U_1 206_6.3VAM~D

2

1

C55
22U_1 206_6.3VAM~D

2

1

C72
22U_1 206_6.3VAM~D

@

2

Place 11 North of Socket(Stuff 6)

1

C29
22U_1 206_6.3VAM~D

2

1

C32
22U_1 206_6.3VAM~D @

2

1

2

Place 12 Inside Socket(Stuff all)

1

C45
22U_1 206_6.3VAM~D

2

1

C394
22U_1 206_6.3VAM~D

2

1

2

Place 9 South of Socket(Unstuff all)

1

C75
22U_1 206_6.3VAM~D

@

2

1

C69
22U_1 206_6.3VAM~D

@

2

1

@

2

C30
22U_1 206_6.3VAM~D

C403
22U_1 206_6.3VAM~D

C70
22U_1 206_6.3VAM~D

1

C77
22U_1 206_6.3VAM~D

@

2

1

C404
22U_1 206_6.3VAM~D

2

1

C73
22U_1 206_6.3VAM~D

@

2

1

C331
22U_1 206_6.3VAM~D

@

2

22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)

1

C412
22U_1 206_6.3VAM~D

2

1

C74
22U_1 206_6.3VAM~D

@

2

1

C395
22U_1 206_6.3VAM~D

2

1

C382
22U_1 206_6.3VAM~D

2

Note:For PT-phase

22uF depop reference
Springdale Chipset Platform Design Guide Rev1.2(12837)
Inside the socket cavity 12 pcs (all stuffed)
North side 12pcs (4 sites stuffed)
Delete south side

B B

+VCC_CORE

5

1

+

C302
470U_D4_2.5V_R10M~D

2

1

+

C294
470U_D4_2.5V_R10M~D

2

1

+

C423
470U_D4_2.5V_R10M~D

@

2

1

+

C303
470U_D4_2.5V_R10M~D

2

+VCC_CORE

1

+

C299
470U_D4_2.5V_R10M~D

@

2

+VCC_CORE

A A

1

+

C68
470U_D4_2.5V_R10M~D

2

470uF _ERS10m ohm* 15, ESR=0.5m ohm

1

+

C304
470U_D4_2.5V_R10M~D

2

1

+

C298
470U_D4_2.5V_R10M~D

2

1

+

C422
470U_D4_2.5V_R10M~D

2

1

+

C301
470U_D4_2.5V_R10M~D

@

2

1

+

C296
470U_D4_2.5V_R10M~D

@

2

4

1

+

C300
470U_D4_2.5V_R10M~D

2

1

+

C295
470U_D4_2.5V_R10M~D

2

1

+

C305
470U_D4_2.5V_R10M~D

2

1

+

C297
470U_D4_2.5V_R10M~D

@

2

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239

Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

Compal Electronics, Inc.

Title

CPU Decoupling

Size Document Number Re v

C

LA-1711

2

Date: Sheet

1

960Wednesday, July 23, 2003

X02-D

of

5

4

3

2

1

H_A#[3..31]<7>

D D

H_REQ#[0..4]<7>

H_ADSTB#0<8>

C C

H_RS#[0..2]<8> MCH_CLKSEL0 <6>

B B

+VTT_GMCH

12

R331
301_0402_1%~D

12

R332
102_0402_1%~D

HDRCOMP

12

A A

R335
20_0603_1%~D

H_ADSTB#1<8>

CK_HCLK<6>
CK_HCLK#<6>

H_DSTBP#0<8>
H_DSTBN#0<8>
H_DINV#0<8>
H_DSTBP#1<8>
H_DSTBN#1<8>
H_DINV#1<8>
H_DSTBP#2<8>
H_DSTBN#2<8>
H_DINV#2<8>
H_DSTBP#3<8>
H_DSTBN#3<8>
H_DINV#3<8>

H_ADS#<7>

H_TRDY#<8>

H_DRDY#<8>

H_DEFER#<7>
H_HITM#<7>
H_HIT#<7>

H_LOCK#<7>

H_BR0#<7>

H_BNR#<7>

H_BPRI#<7>

H_DBSY#<8>

+GMCH_GTLREF

Follow Intel design guide R1.11(12474) page80

Trace width 12mils,Space
10mils

HD_SWING

1

C365

0.01U _0402_16V7K~D

2

Trace width 10mils,Space
7mils

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_RESET#<8>

PWRGD_3V<21,37>

HDRCOMP
HD_SWING

U3A

D26

HA3#

D30

HA4#

L23

HA5#

E29

HA6#

B32

HA7#

K23

HA8#

C30

HA9#

C31

HA10#

J25

HA11#

B31

HA12#

E30

HA13#

B33

HA14#

J24

HA15#

F25

HA16#

D34

HA17#

C32

HA18#

F28

HA19#

C34

HA20#

J27

HA21#

G27

HA22#

F29

HA23#

E28

HA24#

H27

HA25#

K24

HA26#

E32

HA27#

F31

HA28#

G30

HA29#

J26

HA30#

G26

HA31#

B29

HREQ0#

J23

HREQ1#

L22

HREQ2#

C29

HREQ3#

J21

HREQ4#

B30

HADSTB0#

D28

HADSTB1#

B7

HCLKP

C7

HCLKN

B19

HDSTBP0#

C19

HDSTBN0#

C17

DINV0#

L19

HDSTBP1#

K19

HDSTBN1#

L17

DINV1#

G9

HDSTBP2#

F9

HDSTBN2#

L14

DINV2#

D12

HDSTBP3#

E12

HDSTBN3#

C15

DINV3#

F27

ADS#

D24

HTRDY#

G24

DRDY#

L21

DEFER#

E23

HITM#

K21

HIT#

E25

HLOCK#

B24

BREQ0#

B28

BNR#

B26

BPRI#

E27

DBSY#

G22

RS0#

C27

RS1#

B27

RS2#

E8

CPURST#

AE14

PWROK#

E24

HDRCOMP

C25

HDSWING

F23

HDVREF

RG828SDGES_FCBGA932_SPRINGDALE~D

HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#

FSB

HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

PROCHOT#

BSEL0
BSEL1

+CPU_GMCH_GTLREF

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#

B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8

L20

L13
L12

R329

0_0603_5%~D

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9

H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1 2

0_0402_5%~D

+VTT_GMCH

12

R608

12

R323

200_0603_1%~D

H_D#[0..63] <7>

+3VRUN

12

Q24

MMBT3904_SOT23~D

3 1

Settig CPU Output

H_PROCHOT#

MCH_CLKSEL1 <6>

GTL Reference Voltage

Layout note :

1. +GMCH_GTLREF Trace wide
12mils(min),Space 1 5mils.

2. Place decoupling cap 220PF near GMCH.

+GMCH_GTLREF

1

C366
220P_0402_50V7K

2

Create

R90

1.24K _0402_1%~D

2

H_PROCHOT#

R605

1 2

0_0402_5%~D@

H_PROCHOT_SIO# <34>

R91 10K_0402_5%~ D

1 2

C670

12

100P_0402_50V8J~D

H_PROCHOT# <8>

VCORE_PHOT# <34,46>

+VCC_CORE

U3F

AR32

VSS

AR29

VSS

AR27

VSS

AR25

VSS

AR23

VSS

AR20

VSS

AR16

VSS

AR13

VSS

AR11

VSS

AR9

VSS

AN32

VSS

AN30

VSS

AN28

VSS

AN26

VSS

AN24

VSS

AN22

VSS

AN20

VSS

AN18

VSS

AN16

VSS

AN14

VSS

AN12

VSS

AN10

VSS

AM35

VSS

AM29

VSS

AM27

VSS

AM25

VSS

AM23

VSS

AM21

VSS

AM19

VSS

AM17

VSS

AM15

VSS

AM13

VSS

AM11

VSS

AM9

VSS

AL32

VSS

AL1

VSS

AK28

VSS

AK26

VSS

AK24

VSS

AK22

VSS

AK20

VSS

AK18

VSS

AK16

VSS

AK14

VSS

AK12

VSS

AK10

VSS

AK8

VSS

AK3

VSS

AJ35

VSS

AJ32

VSS

AJ9

VSS

AJ4

VSS

AJ1

VSS

AH33

VSS

AH30

VSS

AH24

VSS

AH22

VSS

AH20

VSS

AH18

VSS

AH16

VSS

AH14

VSS

AH12

VSS

AH10

VSS

AH6

VSS

AH3

VSS

AG35

VSS

AG32

VSS

AG28

VSS

AG26

VSS

AG24

VSS

AG22

VSS

AG20

VSS

AG18

VSS

AG16

VSS

AG14

VSS

AG8

VSS

AG4

VSS

AF33

VSS

AF30

VSS

AF25

VSS

AF24

VSS

AF22

VSS

AF20

VSS

AF18

VSS

AF16

VSS

AF14

VSS

AF11

VSS

AF9

VSS

AF6

VSS

AF3

VSS

AE35

VSS

AE32

VSS

AE26

VSS

AE25

VSS

AE13

VSS

AE12

VSS

RG828SDGES_FCBGA932_SPRINGDALE~D

AE11

VSS

AE10

VSS

AE4

VSS

AE1

VSS

AD33

VSS

AD30

VSS

AD28

VSS

AD10

VSS

AD9

VSS

AD8

VSS

AD6

VSS

AD3

VSS

AC35

VSS

AC32

VSS

AC4

VSS

AC1

VSS

AB33

VSS

AB30

VSS

AB28

VSS

AB27

VSS

AB26

VSS

AB10

VSS

AB9

VSS

AB8

VSS

AB6

VSS

AB3

VSS

AA32

VSS

AA4

VSS

AA1

VSS

Y35

VSS

Y33

VSS

Y30

VSS

Y28

VSS

Y27

VSS

Y26

VSS

Y10

VSS

Y9

VSS

Y8

VSS

Y6

VSS

Y3

VSS

W32

VSS

W18

VSS

W17

VSS

W4

VSS

V33

GND

VSS

V30

VSS

V28

VSS

V27

VSS

V26

VSS

V19

VSS

V17

VSS

V10

VSS

V9

VSS

V8

VSS

V6

VSS

V3

VSS

U32

VSS

U19

VSS

U18

VSS

U4

VSS

T35

VSS

T33

VSS

T30

VSS

T28

VSS

T27

VSS

T26

VSS

T10

VSS

T9

VSS

T8

VSS

T6

VSS

T3

VSS

T1

VSS

R32

VSS

R4

VSS

R1

VSS

P33

VSS

P30

VSS

P28

VSS

P27

VSS

P26

VSS

P9

VSS

P8

VSS

P6

VSS

P3

VSS

N35

VSS

N32

VSS

N4

VSS

N1

VSS

M33

VSS

M30

VSS

M28

VSS

M27

VSS

M26

VSS

M6

VSS

M3

VSS

L35

VSS

U3G

L31

VSS

L26

VSS

L25

VSS

L24

VSS

K33

VSS

K29

VSS

K27

VSS

K25

VSS

K22

VSS

K20

VSS

K18

VSS

K16

VSS

K14

VSS

K12

VSS

K11

VSS

J35

VSS

J32

VSS

J28

VSS

J22

VSS

J20

VSS

J18

VSS

J16

VSS

J14

VSS

J12

VSS

J10

VSS

H33

VSS

H30

VSS

H26

VSS

H24

VSS

H22

VSS

H20

VSS

H18

VSS

H16

VSS

H14

VSS

H12

VSS

H9

VSS

H8

VSS

H5

VSS

H2

VSS

G35

VSS

G31

VSS

G28

VSS

F26

VSS

F24

VSS

F22

VSS

F20

VSS

F18

VSS

RG828SDGES_FCBGA932_SPRINGDALE~D

F16

VSS

F14

VSS

F12

VSS

F10

VSS

F8

VSS

F5

VSS

F3

VSS

F1

VSS

E3

VSS

E1

VSS

D35

VSS

D33

VSS

D31

VSS

D29

VSS

D27

VSS

D25

VSS

D23

VSS

D21

VSS

D19

VSS

D17

VSS

D15

VSS

D13

VSS

D11

VSS

D9

VSS

D1

VSS

C28

GND

VSS

C26

VSS

C24

VSS

C22

VSS

C20

VSS

C18

VSS

C16

VSS

C14

VSS

C12

VSS

C10

VSS

C8

VSS

C4

VSS

A32

VSS

A29

VSS

A27

VSS

A25

VSS

A23

VSS

A20

VSS

A16

VSS

A13

VSS

A11

VSS

A9

VSS

A7

VSS

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

Springdale-Host/GND

Size Document Number Re v

C

LA-1711

Date: Sheet

1

of

10 60Thurs day, July 24, 2003

X02-D

5

4

3

2

1

DDRA_SDQ[0..63]

DDRA_SMA[0..12]<15,17>

D D

C C

SM_VREF_A

SM_VREF_A trace width of 12mils and space
12mils(min)

2

C48

2.2U_0805_16VFZ~D

1

2

C47

0.1U_0402_16V4Z~D

1

Close to GMCH

+2.5V_MEM

Trace width of 12mils and space
10mils(min)

B B

2

C64

2.2U_0805_16VFZ~D

1

A A

Follow Intel design guide
R1.11(12474) page124,125

12

R372

42.2_ 0603_1%~D

SMXRCOMP

12

R367

42.2_ 0603_1%~D

2

C65

2.2U_0805_16VFZ~D

1

5

DDRA_SMA[0..12]

DDRA_SWE#<15,17>
DDRA_SCAS#<15,17>
DDRA_SRAS#<15,17>

DDRA_SBS0<15,17>
DDRA_SBS1<15,17>

DDRA_SCS#0<15,17>
DDRA_SCS#1<15,17>

DDRA_CKE0<15, 17>
DDRA_CKE1<15, 17>

DDRA_CLK0<15>
DDRA_CLK0#<15>
DDRA_CLK1<15>
DDRA_CLK1#<15>
DDRA_CLK2<15>
DDRA_CLK2#<15>

1

C637

0.01U _0402_16V7K~D

2

1

C406
1U_0603_6.3V6M~D

2

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12

DDRA_SCS#0
DDRA_SCS#1

DDRA_CKE0
DDRA_CKE1

SMXRCOMP

SMXRCOMPVOH

SMXRCOMPVOL

+2.5V_MEM

Trace width of 12mils and space
10mils(min)

12

R374
10K_0603_1%~ D

SMXRCOMPVOH

12

R369

30.9K _0603_1%~D

*

U3B

AJ34

SMAA_A0

AL33

SMAA_A1

AK29

SMAA_A2

AN31

SMAA_A3

AL30

SMAA_A4

AL26

SMAA_A5

AL28

SMAA_A6

AN25

SMAA_A7

AP26

SMAA_A8

AP24

SMAA_A9

AJ33

SMAA_A10

AN23

SMAA_A11

AN21

SMAA_A12

AL34

SMAB_A1

AM34

SMAB_A2

AP32

SMAB_A3

AP31

SMAB_A4

AM26

SMAB_A5

AB34

SWE_A#

Y34

SCAS_A#

AC33

SRAS_A#

AE33

SBA_A0

AH34

SBA_A1

AA34

SCS_A0#

Y31

SCS_A1#

Y32

SCS_A2#

W34

SCS_A3#

AL20

SCKE_A0

AN19

SCKE_A1

AM20

SCKE_A2

AP20

SCKE_A3

AK32

SCMDCLK_A0

AK31

SCMDCLK_A0#

AP17

SCMDCLK_A1

AN17

SCMDCLK_A1#

N33

SCMDCLK_A2

N34

SCMDCLK_A2#

AK33

SCMDCLK_A3

AK34

SCMDCLK_A3#

AM16

SCMDCLK_A4

AL16

SCMDCLK_A4#

P31

SCMDCLK_A5

P32

SCMDCLK_A5#

E34

SMVREF_A

AK9

SMXRCOMP

AN9

SMXRCOMPVOH

AL9

SMXRCOMPVOL

RG828SDGES_FCBGA932_SPRINGDALE~D

1

C400

0.01U _0402_16V7K~D

2

SDQS_A0

SDQS_A1

SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15

SDQS_A2

SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21

DDR Channel A

SDQ_A22
SDQ_A23

SDQS_A3

SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31

SDQS_A4

SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39

SDQS_A5

SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47

SDQS_A6

SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55

SDQS_A7

SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63

SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7

SDM_A1

SDQ_A8
SDQ_A9

SDM_A2

SDM_A3

SDM_A4

SDM_A5

SDM_A6

SDM_A7

AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13

AP15
AP16

AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18

AP23
AM24

AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27

AM30
AP30

AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34

AF34
AF31

AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34

V34
W33

AC34
AB31
V32
V31
AD31
AB32
U34
U33

M32
M34

T34
T32
K34
K32
T31
P34
L34
L33

H31
H32

J33
H34
E33
F33
K31
J34
G34
F34

2

C63

2.2U_0805_16VFZ~D

1

1

C407
1U_0603_6.3V6M~D

2

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

Close to GMCH <1" Close to GMCH <1"

Note: Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K

4

DDRA_SDQ[0..63] <15,17>

DD RA_SDQS 0 <15,17>
DDRA_SDM0 <15,17>

DD RA_SDQS 1 <15,17>
DDRA_SDM1 <15,17>

DD RA_SDQS 2 <15,17>
DDRA_SDM2 <15,17>

DD RA_SDQS 3 <15,17>
DDRA_SDM3 <15,17>

DD RA_SDQS 4 <15,17>
DDRA_SDM4 <15,17>

DD RA_SDQS 5 <15,17>
DDRA_SDM5 <15,17>

DD RA_SDQS 6 <15,17>
DDRA_SDM6 <15,17>

DD RA_SDQS 7 <15,17>
DDRA_SDM7 <15,17>

+2.5V_MEM

Trace width of 12mils and space
10mils(min)

12

R373

30.9K _0603_1%~D

*

SMXRCOMPVOL

12

R368
10K_0603_1%~ D

1

C401

0.01U _0402_16V7K~D

2

3

+2.5V_MEM

12

12

R104

150_0603_1%~D

R100

150_0603_1%~D

DDRB_SMA[0..12]<16,17>

2

C62

2.2U_0805_16VFZ~D

1

2

C52

2.2U_0805_16VFZ~D

1

DDRB_SMA[0..12]

DDRB_SWE#< 16,17>
DDRB_SCAS#<16,17>
DDRB_SRAS#<16,17>

DDRB_SBS0<16,17>
DDRB_SBS1<16,17>

DDRB_SCS#0<16,17>
DDRB_SCS#1<16,17>

DDRB_CKE0<16, 17>
DDRB_CKE1<16, 17>

DDRB_CLK0<16>
DDRB_CLK0#<16>
DDRB_CLK1<16>
DDRB_CLK1#<16>
DDRB_CLK2<16>
DDRB_CLK2#<16>

SM_VREF_B

SM_VREF_B trace width of
12mils and space
12mils(min)

2

C50

0.1U_0402_16V4Z~D

1

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDRB_SCS#0
DDRB_SCS#1

DDRB_CKE0
DDRB_CKE1

SMYRCOMP

SMYRCOMPVOH

SMYRCOMPVOL

AG31

AJ31
AD27
AE24
AK27
AG25

AL25
AF21

AL23

AJ22
AF29

AL21

AJ20

AE27
AD26

AL29

AL27
AE23

AA25

AK19
AF19
AG19
AE18

AG29
AG30
AF17
AG17

AJ30
AH29
AK15

AL15

AA33

W27
W31
W26

Y25

U26
T29
V25

W25

N27
N26

N31
N30

AP9

R34

R33

U3C

SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12

SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5

SWE_B#
SCAS_B#
SRAS_B#

SBA_B0
SBA_B1

SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#

SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3

SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#

SMVREF_B

SMYRCOMP

SMYRCOMPVOH

SMYRCOMPVOL

Close to GMCH

+2.5V_MEM

2

C66

2.2U_0805_16VFZ~D

1

Trace width of 12mils
and space 10mils(min)

+2.5V_MEM

1

C636

0.01U _0402_16V7K~D

2

1

C57
1U_06 03_6.3V6M~D

2

RG828SDGES_FCBGA932_SPRINGDALE~D

Trace width of 12mils and space
10mils(min)

12

R102

10K_0603_1%~ D

SMYRCOMPVOH

12

R101

30.9K _0603_1%~D

*

1

C54

0.01U _0402_16V7K~D

2

2

C53

2.2U_0805_16VFZ~D

1

12

R110

42.2_ 0603_1%~D

SMYRCOMP

12

R109

42.2_ 0603_1%~D

Close to GMCH <1" Close to GMCH <1"

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

DDRB_SDQ[0..63]

AF15

SDQS_B0

AG11

SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7

SDQS_B1

SDM_B1

SDQ_B8

SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15

SDQS_B2

SDM_B2

SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20

DDR Channel B

SDQ_B21
SDQ_B22
SDQ_B23

SDQS_B3

SDM_B3

SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31

SDQS_B4

SDM_B4

SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39

SDQS_B5

SDM_B5

SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47

SDQS_B6

SDM_B6

SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55

SDQS_B7

SDM_B7

SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63

DDRB_SDQ0

AJ10

DDRB_SDQ1

AE15

DDRB_SDQ2

AL11

DDRB_SDQ3

AE16

DDRB_SDQ4

AL8

DDRB_SDQ5

AF12

DDRB_SDQ6

AK11

DDRB_SDQ7

AG12

AG13
AG15

DDRB_SDQ8

AE17

DDRB_SDQ9

AL13

DDRB_SDQ10

AK17

DDRB_SDQ11

AL17

DDRB_SDQ12

AK13

DDRB_SDQ13

AJ14

DDRB_SDQ14

AJ16

DDRB_SDQ15

AJ18

AG21
AE21

DDRB_SDQ16

AE19

DDRB_SDQ17

AE20

DDRB_SDQ18

AG23

DDRB_SDQ19

AK23

DDRB_SDQ20

AL19

DDRB_SDQ21

AK21

DDRB_SDQ22

AJ24

DDRB_SDQ23

AE22

AH27
AJ28

DDRB_SDQ24

AK25

DDRB_SDQ25

AH26

DDRB_SDQ26

AG27

DDRB_SDQ27

AF27

DDRB_SDQ28

AJ26

DDRB_SDQ29

AJ27

DDRB_SDQ30

AD25

DDRB_SDQ31

AF28

AD29
AC31

DDRB_SDQ32

AE30

DDRB_SDQ33

AC27

DDRB_SDQ34

AC30

DDRB_SDQ35

Y29

DDRB_SDQ36

AE31

DDRB_SDQ37

AB29

DDRB_SDQ38

AA26

DDRB_SDQ39

AA27

U30
U31

DDRB_SDQ40

AA30

DDRB_SDQ41

W30

DDRB_SDQ42

U27

DDRB_SDQ43

T25

DDRB_SDQ44

AA31

DDRB_SDQ45

V29

DDRB_SDQ46

U25

DDRB_SDQ47

R27

L27
M29

DDRB_SDQ48

P29

DDRB_SDQ49

R30

DDRB_SDQ50

K28

DDRB_SDQ51

L30

DDRB_SDQ52

R31

DDRB_SDQ53

R26

DDRB_SDQ54

P25

DDRB_SDQ55

L32

J30
J31

DDRB_SDQ56

K30

DDRB_SDQ57

H29

DDRB_SDQ58

F32

DDRB_SDQ59

G33

DDRB_SDQ60

N25

DDRB_SDQ61

M25

DDRB_SDQ62

J29

DDRB_SDQ63

G32

2

C59

2.2U_0805_16VFZ~D

1

1

C61
1U_06 03_6.3V6M~D

2

Compal Electronics, Inc.

Title

Springdale-DDR Interface

Size Document Number Re v

C

Date: Sheet

LA-1711

DDRB_SDQ[0..63] <16,17>

DDR B_SDQS0 <16,17>
DDRB_SDM0 <16,17>

DDR B_SDQS1 <16,17>
DDRB_SDM1 <16,17>

DDR B_SDQS2 <16,17>
DDRB_SDM2 <16,17>

DDR B_SDQS3 <16,17>
DDRB_SDM3 <16,17>

DDR B_SDQS4 <16,17>
DDRB_SDM4 <16,17>

DDR B_SDQS5 <16,17>
DDRB_SDM5 <16,17>

DDR B_SDQS6 <16,17>
DDRB_SDM6 <16,17>

DDR B_SDQS7 <16,17>
DDRB_SDM7 <16,17>

+2.5V_MEM

Trace width of 12mils and space
10mils(min)

12

R106

30.9K _0603_1%~D

*

SMYRCOMPVOL

12

R105
10K_0603_1%~ D

1

C58

0.01U _0402_16V7K~D

2

1

11 60Wednesday, July 23, 2003

X02-D

of

5

+1.5VRUN

12

R64

43.2_ 0603_1%~D

GRCOMP

+1.5VRUN

D D

12

R328

52.3_ 0603_1%~D

HI_RCOMP_MCH

+1.5VRUN

12

R330

226_0603_1%~D

HI_SWIN G_MCH

12

R68

C C

B B

147_0603_1%~D

12

R69

113_0603_1%

2

C43

0.1U_0402_16V4Z~D

1

2

C360

0.1U_0402_16V4Z~D

1

+1.5VRUN

HI_VREF_MCH

Note:
HI_SWING_MCH, trace width of
12mils and space 10mils

2

C355

0.1U_0402_16V4Z~D

1

2

C41

0.1U_0402_16V4Z~D

1

Note:
HI_VREF_MCH trace width of
10mils and space 7mils

+1.5VRUN

12

R74

226_0603_1%~D

CI_SWING_GMCH

12

R75

147_0603_1%~D

CI_VREF_GMCH

12

R334

113_0603_1%

AGP8X_DET_GC<18>

1

C364

0.01U _0402_16V7K~D

2

Close to GMCH ball <250mils

1

C42

0.01U _0402_16V7K~D

2

Close to GMCH ball <250mils

Note:
CI_SWING_MCH, CI_VREF_MCH
trace width of 12mils and
space 20mils

0.8V

1

C44

0.01U _0402_16V7K~D

2

0.35V

1

C363

0.01U _0402_16V7K~D

2

+1.5VRUN

12

R45

8.2K_ 0402_5%~D

+12V

2

4

12

R48

8.2K_ 0402_5%~D

Q10

MMBT3904_SOT23~D

3 1

HUB_HL[0..10]<20>

+1.5VRUN

G_C/BE#[0..3]<18>

G_PIPE#_DBI_HI<18>

G_ST[0..2]<18>

HUB_HLSTRF<20>
HUB_HLSTRS<20>

CK_66M_MCH

G_FRAME#<18>

CK_66M_MCH<6>

G_DEVSEL#<18>

G_IRDY#<18>
G_TRDY#<18>
G_STOP#<18>

G_PAR<18>

G_REQ#<18>
G_GNT#<18>

G_RBF#< 18>

G_WBF#<18>

G_DBI_LO<18>

Trace 10mils, space 7mils

52.3_ 0603_1%~D

R81

1 2

R40

ICH_SYNC#<21>

PCI_PCIRST#<20, 36>

12

1

@

2

3

R55

1 2

39.2_ 0603_1%~D

2

G

GC_DET_REF

13

D

Q13

2N700 2_SOT23~D

S

Close to VGA Conn.

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

CK_66M_MCH G_AD3

G_PAR

GRCOMP
AGP_SWING
VREFGC

G_ST0
G_ST1
G_ST2

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

HI_RCOMP_MCH
HI_SWIN G_MCH
HI_VREF_MCH

CI_SWING_GMCH
CI_VREF_GMCH

0_0402_5%~D

12

R320
22_0402_5%~D @

C324
10P_04 02_50V8J~D

U3D

Y7

GCBE0

W5

GCBE1

AA3

GCBE2

U2

GCBE3

U6

GFRAME

H4

GCLKIN

AB4

GDEVSEL

V11

GIRDY

AB5

GTRDY

W11

GSTOP

AB2

GPAR/ADD_DETECT

N6

GREQ

M7

GGNT

AC2

GRCOMP/DVOBCGCOMP

AC3

GVSWING

AD2

GVREF

R10

GRBF

R9

GWBF

M4

DBI_HI

M5

DBI_LO

N3

GST0

N5

GST1

N2

GST2

AF5

HI0

AG3

HI1

AK2

HI2

AG5

HI3

AK5

HI4

AL3

HI5

AL2

HI6

AL4

HI7

AJ2

HI8

AH2

HI9

AJ3

HI10

AH5

HISTRF

AH4

HISTRS

AD4

HI_RCOMP

AE3

HI_SWING

AE2

HI_VREF

AK7

CI0

AH7

CI1

AD11

CI2

AF7

CI3

AD7

CI4

AC10

CI5

AF8

CI6

AG7

CI7

AE9

CI8

AH9

CI9

AG6

CI10

AJ6

CISTRF

AJ5

CISTRS

AG2

CI_RCOMP

AF2

CI_SWING

AF4

CI_VREF

G4

DREFCLK

AP8

EXTTS#

AJ8

ICH_SYNC#

AK4

RSTIN#

AG10

RESERVED_1

AG9

RESERVED_2

AN35

RESERVED_3

AP34

RESERVED_4

AR1

RESERVED_5

RG828SDGES_FCBGA932_SPRINGDALE~D

GADSTBF0

GADSTBS0#

AGP

GADSTBF1

GADSTBS1#

HUB

GSBSTBS#

CSA

DDCA_DATA

DDCA_CLK

VGA

GSBSTBF

GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#

GREEN#

REFSET

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8

GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15

GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

RED#
GREEN

BLUE

BLUE#

HSYNC
VSYNC

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20

+1.5VRUN

RED

12

R59

60.4_ 0603_1%

AGP_SWING

12

R58

39.2_ 0603_1%~D

VREFCG

1 2

R57 100_0603_1%~D

12

C385 0.1U_0402_16V4Z~D

AC6
AC5

G_AD0

AE6

G_AD1

AC11

G_AD2

AD5
AE5

G_AD4

AA10

G_AD5

AC9

G_AD6

AB11

G_AD7

AB7

G_AD8

AA9

G_AD9

AA6

G_AD10

AA5

G_AD11

W10

G_AD12

AA11

G_AD13

W6

G_AD14

W9

G_AD15

V7

V4
V5

G_AD16

AA2

G_AD17

Y4

G_AD18

Y2

G_AD19

W2

G_AD20

Y5

G_AD21

V2

G_AD22

W3

G_AD23

U3

G_AD24

T2

G_AD25

T4

G_AD26

T5

G_AD27

R2

G_AD28

P2

G_AD29

P5

G_AD30

P4

G_AD31

M2

U11
T11

G_SBA#0

R6

G_SBA#1

P7

G_SBA#2

R3

G_SBA#3

R5

G_SBA#4

U9

G_SBA#5

U10

G_SBA#6

U5

G_SBA#7

T7

R42

H3

R41

F2

R39

F4
E4

R43

H6
G5

R44

H7
G6

G3
E2

R38

D2

A3
A33
A35
AF13
AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25

Note:
AGP_SWING_MCH, trace width of
12mils a nd spa ce 10mils

Close GMCH ball less than 250mils

R66

G_SBA#[0..7] <18>

0_0402_5%~D

12

0_0402_5%~D

12

0_0402_5%~D

12

0_0402_5%~D

12

0_0402_5%~D

12

1

C362

0.01U _0402_16V7K~D

2

0_0402_5%~D

12

VRE FCG <18>

C361

0.01U _0402_16V7K~D

Close GMCH ball
less than
250mils

G_AD[ 0..31] <18>

G_AD[ 0..31] <18>

2

C38

0.1U_0402_16V4Z~D

1

G_AD_STBF0 <18>
G_AD_ STBS0# <18>

G_AD_STBF1 <18>
G_AD_ STBS1# <18>

G_SB_STBF <18>
G_SB_STBS# <18>

0_0402_5%~D

12

2

VR EFGC <18>

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

2

Note:

1

Springdale Customer Schematic R1.2 page18
AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design
guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.

1

Analog RGB/CRT guidelines for Springdale-P

R61

A A

10K_0402_5%~ D@

1 2

G_PAR

1: External AGP
0: Internal Graphics

5

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

Springdale-AGP/HUB/VGA/CSA

Size Document Number Re v

C

LA-1711

Date: Sheet

1

of

12 60Wednesday, July 23, 2003

X02-D

5

D D

0.82uH, DC current of 30mA

+1.5VRUN

C C

B B

parts and close to cap

0.82U _LQM21N NR82K10_150mA_10%_0805~D

VCCA_FSB1 VCCA_FSB

R301

0_0603_5%~D

+1.5VRUN

0_0603_5%~D

12

R351

1 2

Trace 14mils

1uH(0.54uH-D-IN), DC current of
1000mA parts and close to cap

1U_LQ H32CN1R 0M11_1A_20%_1210~D

VCCA_DDR

12

L34

1 2

L42

1

+

C276

100U_D_10VM~D

2

2

C280

0.1U_0402_16V4Z~D

1

Close to GMCH

Trace 50mils, min:35mils on ball field

VCCA1P5_DDR_SM

Trace 14mils

1

+

C398
100U_D_10VM~D

2

2

C402

0.1U_0402_16V4Z~D

1

Close to GMCH

4

Note:
Placed less than 100 mils from ball

1

C348

0.47U _0603_16V7K~D

2

2

C414

0.1U_ 0402_10V6K~D

1

1 2

C419

+3VRUN

Trace 14mils

R314

R315

Note:
Placed less than 100 mils from ball

1

2

+VTT_GMCH

+2.5V_MEM

C405 0.1 U_0402_10V6K~D

1 2

0.22U _0603_10V7M~D

C49 0.47U _0603_16V7K~D

1 2

1 2

0.22U _0603_10V7M~D

C410

C367 0.1 U_0402_10V6K~D

VCC_AGP_DCAP2

1 2

C371 0.1 U_0402_10V6K~D

1 2

0_0402_5%~D

12

0_0402_5%~D

12

1 2

C421 0.1U_0402_10V6K~D

VTT_DCAP1

VTT_DCAP2

C356

0.47U _0603_16V7K~D

VCC_DDR_DCAP5
VCC_DDR_DCAP4

VCC_DDR_DCAP1

+1.5VRUN

VTT_DCAP3
VCCA_FSB
VCCA_DPLL
VCCA_DAC

VCC_DDR_DCAP2

VCCA1P5_DDR_SM

3

+1.5VRUN

U3E

A15

VTT

A21

VTT

A4

VTT

A5

VTT

A6

VTT

B5

VTT

B6

VTT

C5

VTT

C6

VTT

D5

VTT

D6

VTT

D7

VTT

E6

VTT

E7

VTT

F7

VTT

AA35

VCC_DDR

AL6

VCC_DDR

AL7

VCC_DDR

AM1

VCC_DDR

AM2

VCC_DDR

AM3

VCC_DDR

AM5

VCC_DDR

AM6

VCC_DDR

AM7

VCC_DDR

AM8

VCC_DDR

AN2

VCC_DDR

AN4

VCC_DDR

AN5

VCC_DDR

AN6

VCC_DDR

AN7

VCC_DDR

AN8

VCC_DDR

AP3

VCC_DDR

AP4

VCC_DDR

AP5

VCC_DDR

AP6

VCC_DDR

AP7

VCC_DDR

AR15

VCC_DDR

AR21

VCC_DDR

AR31

VCC_DDR

AR4

VCC_DDR

AR5

VCC_DDR

AR7

VCC_DDR

E35

VCC_DDR

R35

VCC_DDR

G1

VCC_DAC

G2

VCC_DAC

AG1

VCCA_AGP

Y11

VCCA_AGP

A31

VCCA_FSB

B4

VCCA_FSB

B3

VCCA_DPLL

C2

VCCA_DAC

AL35

VCCA_DDR

AB25

VCCA_DDR

AC25

VCCA_DDR

AC26

VCCA_DDR

RG828SDGES_FCBGA932_SPRINGDALE~D

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page84

POWER

VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP

VSSA_DAC

J6

VCC

J7

VCC

J8

VCC

J9

VCC

K6

VCC

K7

VCC

K8

VCC

K9

VCC

L6

VCC

L7

VCC

L9

VCC

L10

VCC

L11

VCC

M8

VCC

M9

VCC

M10

VCC

M11

VCC

N9

VCC

N10

VCC

N11

VCC

P10

VCC

P11

VCC

R11

VCC

T16

VCC

T17

VCC

T18

VCC

T19

VCC

T20

VCC

U16

VCC

U17

VCC

U20

VCC

V16

VCC

V18

VCC

V20

VCC

W16

VCC

W19

VCC

W20

VCC

Y16

VCC

Y17

VCC

Y18

VCC

Y19

VCC

Y20

VCC

J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5

VCC_AGP_DCAP1

Y1

D3

+VTT_GMCH

+2.5V_MEM

+2.5V_MEM

C354

1 2

0.1U_ 0402_10V6K~D

2

+1.5VRUN

1

C337

0.1U_ 0402_10V6K~D

2

Place near GMCH Place near GMCH

1

C374

0.1U_ 0402_10V6K~D@

2

1

C389

0.1U_ 0402_10V6K~D@

2

1

C391

0.1U_ 0402_10V6K~D@

2

1

C378

0.1U_ 0402_10V6K~D@

2

1

C358

0.1U_ 0402_10V6K~D

2

Place near ball
Y11,routing trace
from cap to ball

1

2

1

2

+1.5VRUN

1

C387

0.1U_0402_10V6K~D@

2

+1.5VRUN

1

C319

0.1U_0402_10V6K~D@

2

+1.5VRUN

1

C380

0.1U_0402_10V6K~D@

2

C390

0.1U_0402_10V6K~D@

C373

0.1U_0402_10V6K~D@

+2.5V_MEM

1

C396

0.1U_ 0402_10V6K~D

2

1

C377

0.1U_0402_10V6K~D@

2

1

C393

0.1U_0402_10V6K~D@

2

1

C379

0.1U_0402_10V6K~D@

2

1

C359

0.1U_0402_10V6K~D@

2

1

C347

0.1U_0402_10V6K~D@

2

1

C338

0.1U_ 0402_10V6K~D@

2

1

C346

0.1U_ 0402_10V6K~D@

2

1

C345

0.1U_ 0402_10V6K~D@

2

1

1

C376

0.1U_ 0402_10V6K~D@

2

1

C375

0.1U_ 0402_10V6K~D@

2

1

C353

0.1U_ 0402_10V6K~D@

2

1

C351

0.1U_ 0402_10V6K~D@

2

+VTT_GMCH

Bulk Decopuling

1

+

C308

470U_D4_2.5V_R10M~D

2

A A

+2.5V_MEM

1

2

C384

22U_1206_10V4Z~D

5

2

C327

0.1U_0402_16V4Z~D

1

2

C370

4.7U_0805_6.3V6K~D

1

2

C288

4.7U_0805_6.3V6K~D

1

+1.5VRUN

2

C322

10U_0 805_10V4M~D

1

+1.5VRUN

1

+

C329
470U_D4_2.5V_R10M~D

2

1

C289

1U_0603_6.3V6M~D

2

2

C287

4.7U_0805_6.3V6K~D

1

Place at the output of the 1.5V VR

4

1

C290

0.47U _0603_16V7K~D

2

2

C284

4.7U_0805_6.3V6K~D

1

Place be tween th e VR and GMCH

3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

Compal Electronics, Inc.

Title

Springdale-Decoupling

Size Document Number Re v

C

LA-1711

Date: Sheet

1

of

13 60Wednesday, July 23, 2003

X02-D

5

4

3

2

1

C

B

FAN1 Control and Tachometer

D D

R286

100K_0402_5%~D

FAN1_PWM<34>

C C

1 2

1U_0805_10V6K~D

FAN1V REF

C254

1

2

FAN1_VFB

12

R150
100K_0402_5%~D

U30B

LM358M_SO8~D

5

6

C108

2200P_0603_50V7K~D @

1 2

+12V

8

P

IN+

O

IN-

G

4

R151

300K_0402_5%

1 2

RB751V_SOD323~D

1

C117

0.1U_0402_16V4Z~D

2

SI3457DV-T1_TSOP6~D

FAN1_ON

7

D2

+12V

2

+3VRUN

12

R133
10K_0402_5%~D

Q30

PMBT2222_SOT23~D

3 1

SI3457DV P channel
Vds max: +/- 30V
Vgs max: +/- 20V
Id max: 4.3A @ Vgs = -10V
65mohm @ Vgs = -10V

FAN1_TACH <34>

+5VRUN

Q31

S

3

G

D

6

2451

FAN1_VOUT

1

+

C110
47U_D_16VM_R70~D

2

2 1

1 2

1

C102

0.47U_0603_16V7K~D

2

R136
10K_0402_5%~D

R137

1K_0402_5%~D

1 2

FAN1_TACH_FB

FAN1T ACH_ON

FAN1

FAN1_VOUT <25>
FAN1_ TACH_FB <25>

E3

2222 S YMBOL(SOT23-NEW)

1

2

FAN2 Control and Tachometer

2

FAN2

JFAN2

4

4

3

3

2

2

1

1

MOLEX_53398-0490~D

+3VRUN+12V

12

R287
10K_0402_5%~D

Q61

PMBT2222_SOT23~D

3 1

FAN2_TACH <34>

+12V

U30A

R291

B B

FAN2_PWM<34>

100K_0402_5%~D

1 2

1U_0805_10V6K~D

FAN2V REF

C255

LM358M_SO8~D

3

IN+

2

IN-

1

2

FAN2_VFB

12

2200P_0603_50V7K~D@

1 2

R288
100K_0402_5%~D

C625

300K_0402_5%

1 2

8

P

1

O

G

4

R580

RB751V_SOD323~D

SI3457DV-T1_TSOP6~D

FAN2_ON

Q72

3

G

2451

D17

1

2

2 1

S

D

1

6

C256

0.47U_0603_16V7K~D

2

FAN2_VOUT

+

C622
47U_D_16VM_R70~D

+5VRUN

1 2

R289
10K_0402_5%~D

R290

1K_0402_5%~D

1 2

FAN2_TACH_FB

FAN2T ACH_ON

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

FAN CONTROL

LA-1711

1

14 60Wednesday, July 23, 2003

X02-D

of

5

DDRA_SDQ[0..63]<11, 17>

DDRA_SDQS[0..7]<11,17>

DDRA_SMA[0..12]<11,17>

DDRA_SDM[0..7]<11,17>

D D

C C

B B

4

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_SMA[0..12]

DDRA_SDM[0..7]

3

+2.5V_MEM

JDIM1

1

VREF

DDRA_SDQ0
DDRA_SDQ5

DDRA_SDQS0
DDRA_SDQ7

DDRA_SDQ6
DDRA_SDQ8

DDRA_SDQ13
DDRA_SDQS1

DDRA_SDQ10

DDRA_CLK1< 11>
DDRA_CLK1#<11>

DDRA_CLK0< 11>
DDRA_CLK0#<11>

DDRA_CKE1< 11,17>

DDRA_SBS0<11,17>
DDRA_SWE#<11,17>
DDRA_SCS#0<11,17>

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ17

DDRA_SDQS2
DDRA_SDQ22

DDRA_SDQ19
DDRA_SDQ28

DDRA_SDQ29
DDRA_SDQS3

DDRA_SDQ30
DDRA_SDQ27

DDRA_CKE1

DDRA_SMA12
DDRA_SMA9

DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0

DDRA_SDQ36
DDRA_SDQ32

DDRA_SDQS4
DDRA_SDQ33

DDRA_SDQ35
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5

DDRA_SDQ43
DDRA_SDQ42

DDRA_SDQ52
DDRA_SDQ49

DDRA_SDQS6
DDRA_SDQ51

DDRA_SDQ54
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7

DDRA_SDQ62
DDRA_SDQ59

ICH_ SMBDATA<6,16,21,32>
ICH_SMBCLK< 6,16,21,32>

+3VSUS

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

AMP_1565917-1~D

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU

DU/RESET#
VSS
CK2
CK2#
VDD
CKE1
DU/A13

DU/BA2
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DIMM0

STANDARD

DQ12

DQ13

DQ14
DQ15

DQ20
DQ21

DQ22

DQ23
DQ28

DQ29

DQ30
DQ31

CKE0

RAS#
CAS#

DQ36
DQ37

DQ38

DQ39
DQ44

DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54

DQ55
DQ60

DQ61

DQ62
DQ63

VSS
DQ4

DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD

DM1
VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD

DM3
VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

A11

A8

VSS

A6
A4
A2
A0

VDD

BA1

S1#

DU

VSS

VDD
DM4

VSS

VDD

DM5
VSS

VDD

CK1
VSS

VDD
DM6

VSS

VDD

DM7
VSS

VDD

SA0

SA1

SA2

DU

+2.5V_MEM

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ1
DDRA_SDQ4

DDRA_SDM0

DDRA_SDQ2

DDRA_SDQ3
DDRA_SDQ9

DDRA_SDQ12

DDRA_SDM1

DDRA_SDQ14
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ21

DDRA_SDM2

DDRA_SDQ18

DDRA_SDQ23
DDRA_SDQ24

DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26
DDRA_SDQ31

DDRA_CKE0

DDRA_SMA11
DDRA_SMA8

DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SDQ37
DDRA_SDQ34

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ40

DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ47
DDRA_SDQ46

DDRA_SDQ48
DDRA_SDQ53

DDRA_SDM6
DDRA_SDQ55

DDRA_SDQ50
DDRA_SDQ56

DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ63
DDRA_SDQ58

DDRA_VREF trace width of
12mils and space 12mils(min)

DD RA_CKE0 <11,17>

DDRA_SBS1 <11,17>
DDR A_SRAS# <11,17>
DDR A_SCAS# <11,17>

DDR A_SCS#1 <11,17>

DDRA_CLK2# <11>
DDRA_CLK2 <11>

DDR A_VREF

2

C507

0.1U_0402_16V4Z~D

1

2

+2.5V_MEM

12

R442

75_0603_1%~D

12

R440

75_0603_1%~D

1

Follow

+2.5V_MEM

1

C111

22U_1206_10V4Z~D

2

A A

+2.5V_MEM

1

C103

0.1U_0402_10V6K~D

2

1

2

1

2

System Memory Decoupling caps

C107

0.1U_ 0402_10V6K~D

C134

0.1U_ 0402_10V6K~D

5

1

C113

0.1U_0402_10V6K~D

2

1

C124

0.1U_0402_10V6K~D

2

1

C106

0.1U_ 0402_10V6K~D

2

1

C132

0.1U_ 0402_10V6K~D

2

1

C109

0.1U_ 0402_10V6K~D

2

1

C129

0.1U_ 0402_10V6K~D

2

1

C114

0.1U_0402_10V6K~D

2

1

C123

0.1U_0402_10V6K~D

2

4

1

C112

0.1U_ 0402_10V6K~D

2

1

C128

0.1U_ 0402_10V6K~D

2

1

C101

0.1U_ 0402_10V6K~D

2

1

C126

0.1U_0402_10V6K~D

2

1

C79

0.1U_ 0402_10V6K~D

2

1

C92

0.1U_ 0402_10V6K~D

2

1

C104

0.1U_ 0402_10V6K~D

2

1

C133

0.1U_ 0402_10V6K~D

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

1

C81

0.1U_ 0402_10V6K~D

2

1

C105

0.1U_ 0402_10V6K~D

2

2

Decoupling Reference Document:
Spring dale C ustome r Schem atic R 1.2 pa ge22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-1711

1

X02-D

of

15 60Wednesday, July 23, 2003

5

DDRB_SDQ[0..63]<11,17>

DDRB_SDQS[0..7]<11,17>

DDRB_SMA[0..12]<11,17>

DDRB_SDM[0..7]<11,17>

D D

C C

B B

System Memory Decoupling caps

+2.5V_MEM

1

C116

0.1U_0402_10V6K~D

2

+2.5V_MEM

1

2

C94

0.1U_0402_10V6K~D

A A

1

C100

0.1U_ 0402_10V6K~D

2

1

C86

0.1U_ 0402_10V6K~D

2

5

1

C82

0.1U_0402_10V6K~D

2

1

C97

0.1U_0402_10V6K~D

2

1

C84

0.1U_ 0402_10V6K~D

2

1

C80

0.1U_ 0402_10V6K~D

2

DDRB_SDQ[0..63]

DDRB_SDQS[0..7]

DDRB_SMA[0..12]

DDRB_SDM[0..7]

1

C98

0.1U_ 0402_10V6K~D

2

1

C90

0.1U_ 0402_10V6K~D

2

4

4

1

C95

0.1U_0402_10V6K~D

2

1

C78

0.1U_0402_10V6K~D

2

DDRB_CLK1<11>
DDRB_CLK1#<11>

DDRB_CLK0<11>
DDRB_CLK0#<11>

DDRB_CKE1<11, 17>

DDRB_SBS0<11,17>
DDRB_SWE#< 11,17>
DDRB_SCS#0<11,17>

ICH_SMBDATA<6,15,21,32>
ICH_SMBCLK<6,15, 21,32>

1

C87

0.1U_ 0402_10V6K~D

2

1

C91

0.1U_ 0402_10V6K~D

2

DDRB_SDQ5
DDRB_SDQ4

DDRB_SDQS0
DDRB_SDQ6

DDRB_SDQ1
DDRB_SDQ9

DDRB_SDQ13
DDRB_SDQS1

DDRB_SDQ14
DDRB_SDQ10

DDRB_SDQ20
DDRB_SDQ21

DDRB_SDQS2
DDRB_SDQ19

DDRB_SDQ22
DDRB_SDQ24

DDRB_SDQ25
DDRB_SDQS3

DDRB_SDQ30
DDRB_SDQ26

DDRB_CKE1

DDRB_SMA12
DDRB_SMA9

DDRB_SMA7
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0

DDRB_SDQ38
DDRB_SDQ39

DDRB_SDQS4
DDRB_SDQ33

DDRB_SDQ37
DDRB_SDQ46

DDRB_SDQ44
DDRB_SDQS5

DDRB_SDQ41
DDRB_SDQ45

DDRB_SDQ52
DDRB_SDQ49

DDRB_SDQS6
DDRB_SDQ48

DDRB_SDQ51
DDRB_SDQ60

DDRB_SDQ59
DDRB_SDQS7

DDRB_SDQ57
DDRB_SDQ56

+3VSUS

1

2

1

2

C125

0.1U_0402_10V6K~D

C83

0.1U_0402_10V6K~D

3

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

1

C85

0.1U_ 0402_10V6K~D

2

1

C127

0.1U_ 0402_10V6K~D

2

3

2

JDIM2

VREF

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

AMP_1565918-1~D

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD

CKE0

DU/BA2

A11

A8

VSS

A6
A4
A2
A0

VDD

BA1
RAS#
CAS#

S1#

DU

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0
SA1
SA2

DU

DIMM1

REVERSE

1

C93

0.1U_ 0402_10V6K~D

2

1

C99

0.1U_ 0402_10V6K~D

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+2.5V_MEM+2.5V_MEM

1

C96

0.1U_0402_10V6K~D

2

1

C122

0.1U_0402_10V6K~D

2

DDRB_SDQ7
DDRB_SDQ0

DDRB_SDM0

DDRB_SDQ2

DDRB_SDQ3
DDRB_SDQ12

DDRB_SDQ11

DDRB_SDM1

DDRB_SDQ8
DDRB_SDQ15

DDRB_SDQ16
DDRB_SDQ17

DDRB_SDM2

DDRB_SDQ23

DDRB_SDQ18
DDRB_SDQ28

DDRB_SDQ29

DDRB_SDM3

DDRB_SDQ27
DDRB_SDQ31

DDRB_CKE0

DDRB_SMA11
DDRB_SMA8

DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

DDRB_SDQ32
DDRB_SDQ36

DDRB_SDM4
DDRB_SDQ34

DDRB_SDQ35
DDRB_SDQ43

DDRB_SDQ40

DDRB_SDM5

DDRB_SDQ42
DDRB_SDQ47

DDRB_SDQ53
DDRB_SDQ54

DDRB_SDM6
DDRB_SDQ55

DDRB_SDQ50
DDRB_SDQ61

DDRB_SDQ63

DDRB_SDM7

DDRB_SDQ58
DDRB_SDQ62

+3VSUS

1

2

1

2

DDRB_VREF trace width of
12mils and space 12mils(min)

DDR B_VREF

2

C458

0.1U_0402_16V4Z~D

1

DDR B_CKE0 <11,17>

DDRB_SBS1 <11,17>
DDR B_SRAS# <11,17>
DDR B_SCAS# <11,17>
DDR B_SCS#1 <11,17>

DDRB_CLK2# <11>
DDRB_CLK2 <11>

C130

0.1U_ 0402_10V6K~D

C115

0.1U_ 0402_10V6K~D

2

+2.5V_MEM

12

R418

75_0603_1%~D

12

R415

75_0603_1%~D

Follow

Decoupling Reference Document:
Spring dale C ustome r Schem atic R 1.2 pa ge26
each Channel(two DIMMs) requirement 0.1uF*24

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT2

LA-1711

1

X02-D

of

1

16 60Wednesday, July 23, 2003

5

Channel A(DIMM0) Termination
resistors & Decoupling caps

V_1P25V_DDR_VTTV_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTTV_1P25V_DDR_VTT

RN97 56_4P2R_0404_5%~D

DDRA_SDQ1

1 4

DDRA_SDQ4

2 3

RN85 56_4P2R_0404_5%~D

DDRA_SDQ5

1 4

DDRA_SDQ0

D D

C C

2 3

RN84 56_4P2R_0404_5%~D

DDRA_SDQ7

1 4

DDRA_SDQS0

2 3

RN96 56_4P2R_0404_5%~D

DDRA_SDM0

1 4

DDRA_SDQ2

2 3

RN95 56_4P2R_0404_5%~D

DDRA_SDQ3

1 4

DDRA_SDQ9

2 3

RN83 56_4P2R_0404_5%~D

DDRA_SDQ8

1 4

DDRA_SDQ6

2 3

RN94 56_4P2R_0404_5%~D

DDRA_SDQ12

1 4

DDRA_SDM1

2 3

RN82 56_4P2R_0404_5%~D

DDRA_SDQS1

1 4

DDRA_SDQ13

2 3

RN81 56_4P2R_0404_5%~D

DDRA_SDQ15

1 4

DDRA_SDQ10

2 3

RN93 56_4P2R_0404_5%~D

DDRA_SDQ14

1 4
2 3

RN80 56_4P2R_0404_5%~D

DDRA_SDQ17

1 4

DDRA_SDQ20

2 3

RN109 56_4P2R_0404_5%~D

DDRA_SDQ16

1 4

DDRA_SDQ21

2 3

RN79 56_4P2R_0404_5%~D

DDRA_SDQ22

1 4

DDRA_SDQS2

2 3

RN108 56_4P2R_0404_5%~D

DDRA_SDM2

1 4

DDRA_SDQ18

2 3

RN78 56_4P2R_0404_5%~D

DDRA_SDQ28

1 4

DDRA_SDQ19

2 3

RN107 56_4P2R_0404_5%~D

DDRA_SDQ23

1 4

DDRA_SDQ24

2 3

RN77 56_4P2R_0404_5%~D

RN106 56_4P2R_0404_5%~D

RN64 56_4P2R_0404_5%~D

RN63 56_4P2R_0404_5%~D

RN87 56_4P2R_0404_5%~D

RN86 56_4P2R_0404_5%~D

RN62 56_4P2R_0404_5%~D

RN92 56_4P2R_0404_5%~D

RN91 56_4P2R_0404_5%~D

RN70 56_4P2R_0404_5%~D

RN69 56_4P2R_0404_5%~D

RN99 56_4P2R_0404_5%~D

RN68 56_4P2R_0404_5%~D

RN98 56_4P2R_0404_5%~D

RN67 56_4P2R_0404_5%~D

RN90 56_4P2R_0404_5%~D

DDRA_SDQS3

14

DDRA_SDQ29

23

DDRA_SDQ25

14

DDRA_SDM3

23

DDRA_SDQ51 DDRA_SDQ49

14

DDRA_SDQS6

23

DDRA_SDQ60

14

DDRA_SDQ54

23

DDRA_SDQ50

14

DDRA_SDQ56

23

DDRA_SDQ57

14

DDRA_SDM7

23

DDRA_SDQS7

14

DDRA_SDQ61

23

DDRA_SDQ37

14

DDRA_SDQ34

23

DDRA_SDM4

14

DDRA_SDQ38

23

DDRA_SDQ32

14

DDRA_SDQ36

23

DDRA_SDQ33

14

DDRA_SDQS4

23

DDRA_SDQ39

14

DDRA_SDQ40

23

DDRA_SDQ44

14

DDRA_SDQ35

23

DDRA_SDQ41

14

DDRA_SDM5

23

DDRA_SDQS5

14

DDRA_SDQ45

23

DDRA_SDQ47

14

DDRA_SDQ46

23

RN66 56_4P2R_0404_5%~D

RN89 56_4P2R_0404_5%~D

RN65 56_4P2R_0404_5%~D

RN88 56_4P2R_0404_5%~D

RN76 56_4P2R_0404_5%~D

RN105 56_4P2R_0404_5%~D

RN100 56_4P2R_0404_5%~D

RN61 56_4P2R_0404_5%~D

DDRA_CKE0<11, 15>
DDRA_CKE1<11, 15>

DDRA_SCS#0<11,15>
DDRA_SCS#1<11,15>

DDRA_SDQ[0..63]<11,15>

DDRA_SDQS[0..7]<11,15>

DDRA_SMA[0..12]<11,15>

DDRA_SDM[0..7]<11,15>

4

3

2

Channel B(DIMM1) Termination
resistors & Decoupling caps

R433 56_0402_5%~D

DDRA_SCS#0

DDRA_SDQ42 DDRB_SDQS3

14

DDRA_SDQ43

23

DDRA_SDQ48

14

DDRA_SDQ53

23

14

DDRA_SDQ52

23

DDRA_SDM6

14

DDRA_SDQ55

23

DDRA_SDQ27

14

DDRA_SDQ30

23

DDRA_SDQ26

14

DDRA_SDQ31

23

DDRA_SDQ63

14

DDRA_SDQ58 DDRB_SDM7

23

DDRA_SDQ59

14

DDRA_SDQ62

23

DDRA_CKE0
DDRA_CKE1

DDRA_SCS#0
DDRA_SCS#1

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_SMA[0..12]

DDRA_SDM[0..7]

1 2

RN103 56_4P2R_0404_5%~D

DDRA_SMA8

14

DDRA_SMA6

23

RN104 56_4P2R_0404_5%~D

DDRA_CKE0

14

DDRA_SMA11

23

RN73 56_4P2R_0404_5%~D

DDRA_SMA3

14

DDRA_SMA5

23

RN72 56_4P2R_0404_5%~D

DDRA_SMA10

14

DDRA_SMA1

23

RN110 56_4P2R_0404_5%~D

DDRA_SMA4

14

DDRA_SMA2

23

RN74 56_4P2R_0404_5%~D

DDRA_SMA7

14

DDRA_SMA9

23

RN102 56_4P2R_0404_5%~D

DDRA_SMA0

14

DDRA_SBS1

23

RN101 56_4P2R_0404_5%~D

14

DDRA_SCAS#

23

R443 56_0402_5%~D

DDRA_SCS#1

1 2

DDRA_SMA12
DDRA_CKE1

DDRA_SWE#<11,15>
DDRA_SBS0<11,15>

DDRA_SWE#
DDRA_SBS0

DDRA_SBS1 <11,15>

DDR A_SRAS# <11,15>
DDR A_SCAS# <11,15>

V_1P25V_DDR_VTT

RN75

1 4
2 3

56_4P2R_0404_5%~D

RN71

1 4
2 3

56_4P2R_0404_5%~D

RN38 56_4P2R_0404_5%~D

DDRB_SDQ7

1 4

DDRB_SDQ0

2 3

RN32 56_4P2R_0404_5%~D

DDRB_SDQ4

1 4

DDRB_SDQ5

2 3

RN31 56_4P2R_0404_5%~D

DDRB_SDQ6

1 4

DDRB_SDQS0

2 3

RN39 56_4P2R_0404_5%~D

DDRB_SDM0

1 4

DDRB_SDQ2

2 3

RN37 56_4P2R_0404_5%~D

DDRB_SDQ3

1 4

DDRB_SDQ12

2 3

RN30 56_4P2R_0404_5%~D

DDRB_SDQ9

1 4

DDRB_SDQ1

2 3

RN29 56_4P2R_0404_5%~D

DDRB_SDQS1

1 4

DDRB_SDQ13

2 3

RN36 56_4P2R_0404_5%~D

DDRB_SDQ11

1 4

DDRB_SDM1

2 3

RN28 56_4P2R_0404_5%~D

DDRB_SDQ10

1 4

DDRB_SDQ14

2 3

RN47 56_4P2R_0404_5%~D

DDRB_SDQ8

1 4

DDRB_SDQ15DDRA_SDQ11

2 3

RN27 56_4P2R_0404_5%~D

DDRB_SDQ21

1 4

DDRB_SDQ20

2 3

RN45 56_4P2R_0404_5%~D

DDRB_SDM2

1 4

DDRB_SDQ23

2 3

RN33 56_4P2R_0404_5%~D

DDRB_SDQ19

1 4

DDRB_SDQS2

2 3

RN44 56_4P2R_0404_5%~D

DDRB_SDQ18

1 4

DDRB_SDQ28

2 3

RN26 56_4P2R_0404_5%~D

DDRB_SDQ24

1 4

DDRB_SDQ22

2 3

RN46 56_4P2R_0404_5%~D

DDRB_SDQ16

1 4

DDRB_SDQ17

2 3

RN25 56_4P2R_0404_5%~D

14

DDRB_SDQ25

23

RN34 56_4P2R_0404_5%~D

RN58 56_4P2R_0404_5%~D

RN15 56_4P2R_0404_5%~D

RN52 56_4P2R_0404_5%~D

RN14 56_4P2R_0404_5%~D

RN51 56_4P2R_0404_5%~D

RN12 56_4P2R_0404_5%~D

RN41 56_4P2R_0404_5%~D

RN11 56_4P2R_0404_5%~D

RN40 56_4P2R_0404_5%~D

RN10 56_4P2R_0404_5%~D

RN49 56_4P2R_0404_5%~D

RN19 56_4P2R_0404_5%~D

RN48 56_4P2R_0404_5%~D

RN18 56_4P2R_0404_5%~D

DDRB_SDQ26

14

DDRB_SDQ30

23

DDRB_SDM6

14

DDRB_SDQ55

23

DDRB_SDQ60

14

DDRB_SDQ51

23

DDRB_SDQ50

14

DDRB_SDQ61

23

DDRB_SDQS7

14

DDRB_SDQ59

23

DDRB_SDQ63

14
23

DDRB_SDQ39

14
23

DDRB_SDQ32DDRA_SRAS#

14

DDRB_SDQ36

23

DDRB_SDQ33

14

DDRB_SDQS4

23

DDRB_SDM4

14

DDRB_SDQ34

23

DDRB_SDQ46

14

DDRB_SDQ37

23

DDRB_SDQ35

14

DDRB_SDQ43

23

DDRB_SDQS5

14

DDRB_SDQ44

23

DDRB_SDQ40

14

DDRB_SDM5

23

DDRB_SDQ45

14

DDRB_SDQ41

23

RN60 56_4P2R_0404_5%~D

DDRB_SDQ42

14

DDRB_SDQ47

23

RN17 56_4P2R_0404_5%~D

DDRB_SDQ49

14

DDRB_SDQ52

23

RN59 56_4P2R_0404_5%~D

DDRB_SDQ53

14

DDRB_SDQ54

23

RN16 56_4P2R_0404_5%~D

DDRB_SDQ48

14

DDRB_SDQS6

23

RN42 56_4P2R_0404_5%~D

DDRB_SDQ27

14

DDRB_SDQ31

23

RN43 56_4P2R_0404_5%~D

DDRB_SDQ29

14

DDRB_SDM3

23

RN13 56_4P2R_0404_5%~D

DDRB_SDQ56

14

DDRB_SDQ57

23

RN50 56_4P2R_0404_5%~D

DDRB_SDQ58

14

DDRB_SDQ62DDRB_SDQ38

23

RN55 56_4P2R_0404_5%~D

DDRB_SMA4

14

DDRB_SMA2

23

RN54 56_4P2R_0404_5%~D

DDRB_SMA0

14

DDRB_SBS1

23

RN53 56_4P2R_0404_5%~D

DDRB_SRAS#

14

DDRB_SCAS#

23

DDRB_SDQ[0..63]<11,16> DDRB_CKE0<11, 16>

DDRB_SDQS[0..7]<11,16>

DDRB_SMA[0..12]<11,16>

DDRB_SDM[0..7]<11,16>

DDR B_SRAS# <11,16>
DDR B_SCAS# <11,16>

DDRB_SDQ[0..63]

DDRB_SDQS[0..7]

DDRB_SMA[0..12]

DDRB_SDM[0..7]

1

R405 56_0402_5%~D

DDRB_SCS#0

1 2

RN24 56_4P2R_0404_5%~D

DDRB_SMA12

14

DDRB_CKE1

23

RN23 56_4P2R_0404_5%~D

DDRB_SMA7

14

DDRB_SMA9

23

RN56 56_4P2R_0404_5%~D

DDRB_SMA8

14

DDRB_SMA6

23

RN21 56_4P2R_0404_5%~D

DDRB_SMA10

14

DDRB_SMA1

23

R431 56_0402_5%~D

DDRB_SCS#1

1 2

RN22 56_4P2R_0404_5%~D

DDRB_SMA3

14

DDRB_SMA5

23

V_1P25V_DDR_VTT

DDRB_CKE0
DDRB_SMA11

DDRB_SWE#

DDRB_SBS0

RN57

1 4
2 3

56_4P2R_0404_5%~D

RN20

1 4
2 3

56_4P2R_0404_5%~D

DDRB_SWE#<11,16>

DDRB_SBS0<11,16>
DDRB_SBS1<11,16>

DDRB_CKE1<11, 16>

DDRB_SCS#0<11,16>
DDRB_SCS#1<11,16>

DDRB_SWE#

DDRB_SBS0
DDRB_SBS1

DDRB_CKE0
DDRB_CKE1

DDRB_SCS#0
DDRB_SCS#1

3

V_1P25V_DDR_VTT

1

C488

0.1U_0402_10V6K~D

2

V_1P25V_DDR_VTT

1

C484

0.1U_0402_10V6K~D

2

V_1P25V_DDR_VTT

1

C443

0.1U_0402_10V6K~D

2

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 4.7u*2 ;

0.1uF*26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

1

C482

0.1U_ 0402_10V6K~D

2

1

C478

0.1U_ 0402_10V6K~D

2

1

C442

0.1U_ 0402_10V6K~D

2

1

C481

0.1U_0402_10V6K~D

2

1

C476

0.1U_0402_10V6K~D

2

1

C434

2

0.1U_0402_10V6K~D

1

C487

2

1

C485

2

1

C441

0.1U_0402_10V6K~D

2

2

0.1U_ 0402_10V6K~D

0.1U_ 0402_10V6K~D

1

C477

0.1U_ 0402_10V6K~D

2

1

C479

0.1U_ 0402_10V6K~D

2

1

C505

4.7U_ 1206_16V6K~D

2

1

C483

0.1U_0402_10V6K~D

2

1

C480

0.1U_0402_10V6K~D

2

1

C664

0.1U_0402_10V6K~D

2

@

1

C436

0.1U_ 0402_10V6K~D

2

1

C439

0.1U_ 0402_10V6K~D

2

1

C665

0.1U_0402_10V6K~D

2

@

1

C437

0.1U_0402_10V6K~D

2

1

C440

0.1U_0402_10V6K~D

2

1

C666

0.1U_ 0402_10V6K~D

2

@

We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')

Title

DDR Termination Resistors

Size Document Number Re v

C

LA-1711

Date: Sheet

1

of

17 60Wednesday, July 23, 2003

X02-D

V_1P25V_DDR_VTT

B B

1

C519

0.1U_ 0402_10V6K~D

2

V_1P25V_DDR_VTT

1

C504

0.1U_ 0402_10V6K~D

2

V_1P25V_DDR_VTT

1

C492

0.1U_ 0402_10V6K~D

2

V_1P25V_DDR_VTT

1

A A

C499

0.1U_ 0402_10V6K~D

2

Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 4.7u*2 ;

0.1uF*28

1

C514

0.1U_ 0402_10V6K~D

2

1

C512

0.1U_ 0402_10V6K~D

2

1

C498

0.1U_ 0402_10V6K~D

2

1

C494

0.1U_ 0402_10V6K~D

2

5

1

C515

0.1U_0402_10V6K~D

2

1

C518

0.1U_0402_10V6K~D

2

1

C501

0.1U_0402_10V6K~D

2

1

C486

0.1U_0402_10V6K~D

2

1

C516

0.1U_ 0402_10V6K~D

2

1

C513

0.1U_ 0402_10V6K~D

2

1

C500

0.1U_ 0402_10V6K~D

2

1

C495

0.1U_ 0402_10V6K~D

2

1

C517

0.1U_0402_10V6K~D

2

1

C503

0.1U_0402_10V6K~D

2

1

C438

0.1U_0402_10V6K~D

2

1

C490

4.7U_ 1206_16V6K~D

2

1

C511

0.1U_0402_10V6K~D

2

1

C661

0.1U_0402_10V6K~D

2

@

1

C493

0.1U_0402_10V6K~D

2

1

C510

4.7U_1206_16V6K~D

2

1

C662

0.1U_ 0402_10V6K~D

2

@

1

C496

0.1U_0402_10V6K~D

2

1

C667

0.1U_ 0402_10V6K~D

2

@

1

C663

0.1U_ 0402_10V6K~D

2

@

1

C502

0.1U_0402_10V6K~D

2

1

C668

0.1U_ 0402_10V6K~D

2

@

We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02')

4

5

G_ST[0..2]<12>

G_AD[0..31]<12>

G_C/BE#[0..3]<12>

G_SBA#[0..7]<12>

CK_66M_AGP<6>

D D

G_REQ#<12>

G_ST0<12>
G_ST1<12>
G_ST2<12>

AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0

Note:
AGP8X_DET_GC :Pull low by an AGP3.0 graphics card
Floating by an AGP2.0 graphics card

C C

G_AD_STBF0<12>
G_AD_STBS0#<12>
G_AD_STBF1<12>
G_AD_STBS1#<12>

G_SB_STBF<12>
G_SB_STBS#<12>

G_FRAM E#<12>
G_DEV SEL#<12>

G_IRDY#<12>
G_TRDY#<12>
G_STOP#<12>

G_PAR<12>
G_REQ#<12>
G_GNT#<12>

G_PIPE#_DBI_HI<12>

G_DBI_LO<12>

B B

G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#

G_PAR

G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO

FPVCC

2

C317

0.1U_ 0402_10V6K~D

1

G_SBA#[0..7]

CK_6 6M_AGP
G_REQ#
G_ST0
G_ST1
G_ST2

AGP8X_DET_CG : low -->MB
support AGP3.0

VREFCG<12>

R322

1

C388

0.1U_0402_16V4Z~D

2

ICH_ SUS_STAT#<21>

GC_BL_SUSPEND<33>

PCI_PIRQB#<20,32>

+1.5VRUN

+1.5VRUN

RUNPWROK<34, 37,43,44,46>

4

12

FPVCC<34>

+1.5VRUN

SP_DIF<24>

+5VSUS

0_0402_5%~D

+12V

+3VSUS

G_PWR_SRC

+3VRUN

CK_6 6M_AGP

AGP8X_DET_CG
PCI_PIRQB#

G_ST0
G_ST2

G_SBA#2
G_SBA#4

G_SB_STBF
G_SB_STBS#

AGP_RST#

G_IRDY#
G_TRDY#
RUNPWROK

G_STOP#
G_FRAME#
G_C/BE#3

G_AD31
G_AD29

G_AD_STBS1#
G_AD_STBF1

G_AD27
G_AD25

G_C/BE#2
G_AD21

G_AD19

VREFCG

G_AD15
G_AD13
G_AD11
G_AD9

G_AD_STBS0#
G_AD_STBF0

G_AD5
G_AD3

G_AD1

G_AD0
FPVCC

ICH_ SUS_STAT#

GC_BL_SUSPEND

JVID

1

1

3

3

5

5

7

7

9

9

11

11

13

GND

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

GND

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

GND

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

GND

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

GND

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

GND

149

149

151

151

153

153

155

155

157

157

159

159

FOX_QT00160A-9120L~D

3

G_PWR_SRC

2

2

C26

1

0.1U_0603_25V7M~D

2

2

4

4

6

6

8

8

10

10

12

12

14

GND

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

GND

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

GND

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

GND

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

122

GND

124

124

126

126

128

128

130

130

132

132

134

134

136

136

138

138

140

140

142

142

144

144

146

146

148

GND

150

150

152

152

154

154

156

156

158

158

160

160

G_PWR_SRC

+3VRUN

+1.5VRUN

AGP8X_DET_GC
PCI_PIRQA#

G_REQ#
G_ST1

G_SBA#0
G_SBA#1

G_SBA#3
G_SBA#5

G_SBA#6
G_SBA#7
G_DEVSEL#

G_RBF#
G_WBF#
G_PIPE#_DBI_HI

G_AD30
G_AD28
G_AD26

G_AD24
G_AD22

G_AD20
G_AD18

G_AD23
G_AD17

G_AD16
G_DBI_LO

G_C/BE#1
VREFGC_R

G_AD14
G_AD12
G_AD10

G_AD8
G_AD7
G_AD6

G_AD4

G_AD2

G_C/BE#0

G_GNT#
G_PAR

SBAT_SMBDAT
SBAT_SMBCLK

STP_AGP_R#

+5VALW
+5VRUN

+5VSUS

G_AGPBUSY#

LID_CL# <33>

AGP8X_DET_GC <12>
PCI_PIRQA# <20>

G_ RBF# <12>
G_W BF# <12>

1 2

+1.5VRUN

SBAT_SMBDAT <34>

SBAT_SMBCLK <34>

2

C23

C24

1

1

0.1U_0603_25V7M~D

0.1U_0603_25V7M~D

R88

0_0402_5%~D @

+3VRUN

2

C22

1

0.1U_0603_25V7M~D

VR EFGC <12>

+3VRUN

1 2

2

1

C21

2

0.1U_0603_25V7M~D

R96
10K_0402_5%~ D

R98

0_0402_5%~D@

1 2

PWR_SRC

2

C19

1

0.1U_ 0603_25V7M~D

CPLD Disable
Pop R96, Depop R98

STP_AGP# < 36>

+1.5VRUN

C12

0.1U_ 0603_25V7M~D

1

PWR_SRC G_PWR_SRC

2

1

R30

RUN_ON<3 3,37,39,44>

1 2

100K_0402_5%~D

Make R571
100K ohm
after 6th
August

SI4435DY_SO8~D

1
2
3 6

2

G

FOXCONN QT00160A-9120L

Shielding Ground Pin

13,14
39,40
67,68
93,94
121,122
147,148

Q8

4

12

R28
100K_0402_5%~D

AGP_PWRON# GPWR_SRC_ON

13

D

Q7
2N7002_SOT23~ D

S

8
7

5

1

1

1

C417

+3VSUS

U7
TC7SH32FU_SSOP5~D@

5

SYS_SU SPEND

1

P

AGP_RST#

A A

5

4

O

R156
0_0402_5%~D

INB

INA

3

G

2

12

4

PCIRST_AGP#

SYS_SUSPEND <33,41>

PCIRST_AGP# <20>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

0.047U_0402_10V4M~D

+12V

1

C413

0.1U_0402_16V4Z~D

2

C418

2

0.047U_0402_10V4M~D

1

C339

2

0.047U_0402_10V4M~D

+5VRUN

1

C416

0.1U_0402_16V4Z~D

2

1

1

CLOSE

C325

C334

TO PIN

2

2

0.047U_0402_10V4M~D

0.047U_0402_10V4M~D

+5VALW

1

2

2

1

C342

2

0.047U_0402_10V4M~D

C415

0.1U_0402_16V4Z~D

C336

2

0.047U_0402_10V4M~D

1

1

C409

2

0.047U_0402_10V4M~D

Title

Size Document Number Re v

Date: Sheet

1

C397

2

0.047U_0402_10V4M~D

1

C352

C357

2

2

0.047U_0402_10V4M~D

0.047U_0402_10V4M~D

Compal Electronics, Inc.

VGA Daughter Board Conn.

LA-1711

1

of

18 60Wednesday, July 23, 2003

X02-D

5

+3VALW

4

3

2

1

CPU Temperature Sensor

D D

R375

1 2

DAT_SMB<26,34,35,47>
CLK_SMB< 26,34,35,47>

C C

DAT_SMB
CLK_SMB

FAN3 Control and Tachometer

R609

10K_0402_5%~D

+3VRUN

B B

10K_0402_5%~D

FAN3_PWM

R117

12

2

G

13

D

Q75
2N7002_SOT23~D

S

R610

2.7K_0402_5%

R378

1 2

6.8K_0402_5%~D

6.8K_0402_5%~D

0.1U_0402_16V4Z~D

+12V

+12V

1 2

Q28

12

SI4435DY_SO8~D

1
2
3 6

C408

1 2

FAN3_TACH

0.47U_0603_16V7K~D

4

+3VRUN

8
7

5

U37

3

VCC

16

SDA

1

SCL

6

TACH1

7

TACH2

4

TACH3

9

TACH4

2

GND

ADT7460ARQ_QSOP16~D

1

C89

2

FAN3_ON

2.5VIN

D1+

D1-

D2+

D2-

PWM1

PWM2/ALERT#

PWM3

+5VRUN

R118
10K_0402_5%~D

1 2

R120

1K_0402_5%~D

1 2

FAN3

JFAN3

1

1

2

2

3

3

SUYIN_250019MR003G400ZL~D

14

13
12

11
10

15

5

8

H_THERMDC

MCH_THERMDA
MCH_THERMDC

FAN3_PWM

1 2

R365 10K_0402_5%~D

R366

1 2

0_0402_5%~D

1

C420
2200P_0603_50V7K~D

2

+3VRUN

Address 0101 110X (X=1-->Read; X=0-->Write)

+3VRUN

12

R125
10K_0402_5%~D

FAN3_TACH

Q29

FAN3T ACH_ON

2

PMBT2222_SOT23~D

3 1

D1

RB751V_SOD323~D

2 1

1

C88
10U_1206_16V4Z~D

2

H_THERMDA <8>

H_THERMDC <8>

ATF_INT# <33,47>

1

C673

@

22U_1206_16V4Z_V1

2

MCH_THERMDAH_THERMDA

1

C657
2200P_0603_50V7K~D

2

MCH_THERMDC

Put Cap near pin 10,11 of U37

Q73

MMBT3904_SOT23~D

2

3 1

Put 3904 between MCH and DDR

+12V

8

R616

10K_0402_5%~D@

1 2

1

C671

1U_0805_10V6K~D@

A A

5

2

12

3

2

R618
100K_0402_5%~D@

IN+

IN-

2200P_0603_50V7K~D @

U46A

P

O

G

LM358M_SO8~D@

4

C672

1 2

R617

300K_0402_5%@

1 2

4

1

Item101: Reserved Op amp circuit (NP) to the High side FET

Compal Electronics, Inc.

CPU Thermal Sensor & FAN Control

LA-1711

1

of

19 60Thursday, July 24, 2003

X02-D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Title

Size Doc ument Number Re v

Date: Sheet

5

+3VRUN

RN3

182736

45

8.2K_ 8P4R_1206_5%~D

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#

+3VRUN

D D

+3VRUN

+3VRUN

+3VRUN

C C

+3VRUN

B B

+3VSUS

PCI_PCIRST#

A A

R386

10K_0402_5%~ D

R401

10K_0402_5%~ D

RN2

182736

45

8.2K_ 8P4R_1206_5%~D

RN4

182736

45

8.2K_ 8P4R_1206_5%~D

RN1

182736

45

8.2K_ 8P4R_1206_5%~D

12

R113

10K_0402_5%~ D

12

R426

10K_0402_5%~ D

1

IN1

2

IN2

4

IN1

5

IN2

10

IN1

9

IN2

13

IN1

12

IN2

12

R387

10K_0402_5%~ D

12

R139

10K_0402_5%~ D

U8A

14

74VHC 08MTC_TSSOP14~D

P

3

OUT

G

7

U8B
74VHC 08MTC_TSSOP14~D

6

OUT

U8C
74VHC 08MTC_TSSOP14~D

8

OUT

U8D
74VHC 08MTC_TSSOP14~D

11

OUT

5

PCI_FRAME#

12

R398

8.2K_ 0402_5%~D

@

PCI_GNTA#
PCI_IRDY#

PCI_SERR#
PCI_PERR#

12

R119

8.2K_ 0402_5%~D

PCI_PLOCK#
PCI_REQ0#
PCI_REQB#
PCI_PIRQB#
PCI_PIRQA#

PCI_PIRQD#
PCI_PIRQC#
PCI_REQ2#

12

PCI_REQ4#

PCI_REQ1#

PCI_REQ3#

12

IDE_IRQ15

IDE_IRQ14

IRQ_SERIR Q

IDE_I RQ15 <21,23>

IDE_IRQ14 <21>

IRQ _SERIRQ <21,30,33>

C118

0.1U_0402_16V4Z~D

R162

PCIRSTB1#

PCIRSTB2#

PCIRSTB3# PCIR ST_1#

PCIRSTB4#

33_0402_5%~D

1 2

R159

33_0402_5%~D

1 2

33_0402_5%~D

1 2

R153

33_0402_5%~D

1 2

33_0402_5%~D

1 2

R160

R157

+3VRUN

R393
10K_0402_5%~ D

1 2

PCI_REQA#

R414

CK_33M_ICHPCI

12

10_0402_5%~D@

CLK_ICH_TERM

1

C465

8.2P_ 0402_50V8J~D

@

2

+1.5VRUN

+1.5VRUN

12

R411

226_0603_1%~D

HI_SWING_ICH

12

R410

147_0603_1%~D

HI_VREF_ICH

12

R409

113_0603_1%

12

PCIRST_AGP#

PCIRST_SIO#

PCIRST_2#

PCI RST _AGP# <18>

PCIR ST_SIO# <33>

PCIRST_CB# <30>

PCIR ST_1# <28>

PCIR ST_2# <32>

+3VRUN

R124

1 2

52.3_ 0603_1%~D

4

RN35

182736

45

8.2K_ 8P4R_1206_5%~D

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

HI_RCOMP_ICH

Note:
HI_SWING_MCH, HI_VREF_MCH
trace width of 12mils and
space 10mils

2

C460

0.1U_0402_16V4Z~D

1

2

C456

0.1U_0402_16V4Z~D

1

4

R425
10K_0402_5%~ D@

+3VSUS

1

C455

0.01U _0402_16V7K~D

2

Close to ICH ball <250mils

1

C452

0.01U _0402_16V7K~D

2

Close to ICH ball <250mils

0.1"~6"

ICH_AC_RST_R#

ICH_AC_SYNC_R

ICH_AC_SDOUT_R

ICH_AC_SDOUT
ICH_AC_BITCLK
ICH_AC_SDIN0
ICH_AC_SDIN1

R389 33_0402_5%~D

R385 33_0402_5%~D

R390 33_0402_5%~D

R383
1K_0402_5%~D@

1 2

3

R396
10_0402_5%~D@

1 2

ICH_AC_ BITCLK_TERM

2

C427
10P_04 02_50V8J~D

@

1

U5A

D2

FRAME#

M3

IRDY#

E4

TRDY#

L3

DEVSEL#

E5

STOP#

F1

PAR

K2

PERR#

L2

PLOCK#

L4

SERR#

V2

PME#

V4

PCIRST#

N1

PCICLK

B3

PIRQA#

E1

PIRQB#

A2

PIRQC#

C2

PIRQD#

D7

PIRQE#/GPI2

A6

PIRQF#/GPI3

E2

PIRQG#/GPI4

B1

PIRQH#/GPI5

D5

REQ0#

C1

REQ1#

C5

REQ2#

B6

REQ3#

C6

REQ4#/GPI40

A5

REQA#/GPI0

E7

REQB#REQ5#/GPI1

D4

GNT0#

A3

GNT1#

B7

GNT2#

C7

GNT3#

A4

GNT4#/GPO48

E8

GNTA#/GPO16

B4

GNTB#/GNT5#/GPO17

FW82801EB_mBGA460_ICH5~D

U5B

H20

HI0

H21

HI1

J20

HI2

H23

HI3

M23

HI4

M21

HI5

N21

HI6

M20

HI7

L22

HI8

J22

HI9

K21

HI10

G22

HI11

K23

HI_STBF

J24

HI_STBS

N24

HIRCOMP

L20

HI_VSWING

L24

HIREF

N22

CLK66

C10

LAN_RXD0

C9

LAN_RXD1

C11

LAN_RXD2

D9

LAN_TXD0

E9

LAN_TXD1

B12

LAN_TXD2

D10

LAN_RSTSYNC

E10

LAN_CLK

AA1

LAN_RST#

B11

EE_DIN

B10

EE_CS

A12

EE_SHCLK

B9

EE_DOUT

B8

AC_SYNC

C12

AC_RST#

A9

AC_SDOUT

E12

AC_SDIN0

D12

AC_SDIN1

A13

AC_SDIN2

D8

AC_BIT_CLK

FW82801EB_mBGA460_ICH5~D

PCI_FRAME#<28,30,32>
PCI_IRDY#<28,30,32>
PCI_TRDY#<28,30,32>
PCI_DEVSEL#<28,30,32>
PCI_STOP#<28,30,32>
PCI_PAR<28,30,32>
PCI_PERR#<28,30,32>

HUB_HL[0..10]<12>

+3VRUN

3

PCI_SERR#<28,30,32>

PCI_PCIRST#<12, 36>

CK_33M_ICHPCI<6>

PCI_PIRQA#<18>
PCI_PIRQB#<18,32>
PCI_PIRQC#<28,30>
PCI_PIRQD#<30,32>

PCI_REQ1#<30>

PCI_REQ3#<32>
PCI_REQ4#<28>

PCI_REQB#<30>

PCI_GNT1#<30>

PCI_GNT3#<32>
PCI_GNT4#<28>

PCI_GNTB#<30>

R406 6 1.9_0603_1%

1 2

HUB_HLSTRF<12>

HUB_HLSTRS<12>

ICH_AC_SDIN0<24>
ICH_AC_SDIN1<27>

ICH_AC_BITCLK<24>

12

ICH_PME#<33>

12

12

12

R395

10K_0402_5%~ D@

12

ICH_ AC_RST# <24,27>

ICH _AC _SYNC < 24,27>

ICH_ AC_SDOUT <24,27>

12

R402

R397

10K_0402_5%~ D@

12

10K_0402_5%~ D@

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_PLOCK#

PCI_SERR#
ICH_PME#
PCI_PCIRST#
CK_33M_ICHPCI

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQA#
PCI_REQB#

PCI_GNT1#

PCI_GNT3#
PCI_GNT4#
PCI_GNTA#
PCI_GNTB#

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

HI_RCOMP_ICH
HI_SWING_ICH
HI_VREF_ICH
CK_66M_ICH

R430 0_0402_5%~D

R392 1K_0402_5%~ D@

LAN_RST#

12

NC_EE_DOUT

1 2

ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDOUT_R
ICH_AC_SDIN0
ICH_AC_SDIN1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

C/BE3#
C/BE2#
C/BE1#
C/BE0#

USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
USBP6P
USBP6N
USBP7P
USBP7N

OC0#
OC1#
OC2#
OC3#

OC4#/GPI9
OC5#/GPI10
OC6#/GPI14
OC7#/GPI15

USBRBIAS

USBRBIAS#

CLK48

2

1

PCI_AD31

P2

PCI_AD30

F4

PCI_AD29

P4

PCI_AD28

F5

PCI_AD27

N2

PCI_AD26

D3

PCI_AD25

P3

PCI_AD24

E6

PCI_AD23

N4

PCI_AD22

C4

PCI_AD21

N5

PCI_AD20

H3

PCI_AD19

P5

PCI_AD18

B2

PCI_AD17

L1

PCI_AD16

G4

PCI_AD15

G5

PCI_AD14

K1

PCI_AD13

G2

PCI_AD12

L5

PCI_AD11

H4

PCI_AD10

M4

PCI_AD9

F2

AD9

PCI_AD8

K5

AD8

PCI_AD7

J2

AD7

PCI_AD6

J3

AD6

PCI_AD5

H2

AD5

PCI_AD4

H5

AD4

PCI_AD3

K4

AD3

PCI_AD2

G3

AD2

PCI_AD1

J5

AD1

PCI_AD0

J4

AD0

M2
N3
J1
E3

C23
D23
A22
B22
C21
D21
A20
B20
C19
D19
A18
B18
C17
D17
A16
B16

C15
D15
D14
C14
B14
A14
D13
C13

A24
B24

F24

USBRBIAS

CK_48M_ICH

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

CK_48M_ICH <6>

CK_66M_ICH<6>

USBP1+ <26>
USBP1- <26>
USBP2+ <26>
USBP2- <26>
USBP3+ <26>
USBP3- <26>
USBP4+ <26>
USBP4- <26>
USBP5+ <26>
USBP5- <26>
USBP6+ <26>
USBP6- <26>

R394 2 2.6_0603_1%~D

PCI_A D[0..31] <28,30,32>

PCI_C _BE3# <2 8,30,32>
PCI_C _BE2# <2 8,30,32>
PCI_C _BE1# <2 8,30,32>
PCI_C _BE0# <2 8,30,32>

USB_OC2# <26>
USB_OC3# <26>
USB_OC4# <23>
USB_OC5# <26>

RN111

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%~D

12

R404

12

10_0402_5%~D@

Note:
USBRBIAS keep less than 500mils

CK_48M_ICH_TERM

2

C431

@

4.7P_0402_50V8C~D

1

CK_66M_ICH

R413
10_0402_5%~D@

1 2

CK_66M_ICH_TERM

2

C464
10P_04 02_50V8J~D

@

1

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

ICH5-PCI/HUB/USB/AC97

LA-1711

RN112

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

USB_O C6# <26>

1

USB_OC IS 5V
TOLERANT

+5VSUS

of

20 60Wednesday, July 23, 2003

X02-D

5

R274

IDE_P DIORDY

IDE_S DIORDY

IDE_PDDREQ

IDE_SDDREQ

D D

C C

B B

R154

1 2

180K_0402_5%~D

A A

15P_0603_50V8J~D

15P_0603_50V8J~D

4.7K_ 0402_5%~D

R562

4.7K_ 0402_5%~D

R279

0_0402_5%~D

1 2

R558

0_0402_5%~D

1 2

SIO_SLP_S3#

+3VRUN

12

12

12

12

0000

000

00 0

00

1

000

ICH_RTCRST#

2

C119

0.1U_ 0402_10V6K~D

1

+3.3VRTC

C509

12

C508

1 2

12

+3VRUN

12

12

2

C251

C608

1

33P_06 03_50V8J~D

@

1 2

R439 0_0402_5%~D

R399

1 2

1 2

10K_0402_5%~ D@

R13010K_0402_5%~ D

R12610K_0402_5%~ D@

R11510K_0402_5%~ D

R40310K_0402_5%~ D

BID0BID1BID2BID3 REV

X00

X01

1

2

5

CMOS_CLR

SHORT PADS@

2

1 2

ICH_RTCX1

ICH_RTCX2

X02

X03

X04

R158

1K_0402_5%~D

1

11

X4

32.768KHZ_12.5P_MC-306~D

RPDDREQ

RSDDREQ

2

1

33P_06 03_50V8J~D@

ICH_SLP_S1# <6>

R116

R123

1 2

1 2

10K_0402_5%~ D@

10K_0402_5%~ D

1 2

1

1

1K_0402_5%~D

3 2

1U_0805_10V6K~D

12

R437
10M_0402_5%~D

RSDDREQ <23>

R128

10K_0402_5%~ D

@

BID0

BID1

BID2

BID3

R471

C120

ICH_SYNC#<12>

D3

1

2

1

IDE_IRQ14<20>

MMBT3904_SOT23~D@

PWRGD_3V<10,37>

BAT54C_SOT23~D

VCC_RTC

+3VRUN

IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

IDE_PDIOW #
IDE_PDDACK#
IDE_PDDREQ
IDE_PDIOR#
IDE_P DIORDY

IDE_PDA2
IDE_PDA1
IDE_PDA0

IDE_PDCS3#
IDE_PDCS1#

+3VRUN

12

R167

Q33

BAT54C

K2 K1

1

2

+3VSUS

R419
10K_0402_5%~ D@

1 2

R121
10K_0402_5%~ D@

1 2

220_0402_5%@

2

3

VCC_RTC

AB17
AA16

Y16
AC16
AA15
AD16

Y15
AD15
AB14
AD14
AC15
AA14
AC14

Y14

Y13
AB16

AA17
AC18
AC17
AD18
AA18

AC19
AD19
AA19

Y18
AB19

Y17

12

R169

1K_0402_5%~ D@

3 1

A1A2

LPC_LDRQ0#

LPC_LDRQ1#

4

U5C

PDD15

SDD15

PDD14

SDD14

PDD13

SDD13

PDD12

SDD12

PDD11

SDD11

PDD10

SDD10
PDD9
PDD8
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDIOW#

SDIOW#

PDDACK#

SDDACK#

PDDREQ

SDDREQ

PDIOR#

SDIOR#

PIORDY

SIORDY

PDA2
PDA1
PDA0

PDCS3#

SDCS3#

PDCS1#

SDCS1#

IRQ14

R266

1 2

1K_0402_5%~ D@

IRQ15

IDE_RST _MOD_SFTON

R114

FW82801EB_mBGA460_ICH5~D

10K_0402_5%~ D@

1 2

SPKR

Disable timer timeout

+3VRUN

12

R161

Q32

2

MMBT3904_SOT23~D@

3 1

R438

1 2

0_0402_5%~D

4

IDE_SDD15

AA23

IDE_SDD14

AB24

IDE_SDD13

AC24

IDE_SDD12

AB22

IDE_SDD11

AA20

IDE_SDD10

AC22

IDE_SDD9

AD22

SDD9
SDD8
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

SDA2
SDA1
SDA0

IDE_SDD8

Y19

IDE_SDD7

AC20

IDE_SDD6

AB20

IDE_SDD5

AC21

IDE_SDD4

AB21

IDE_SDD3

AD24

IDE_SDD2

AD23

IDE_SDD1

AB23

IDE_SDD0

AA22

IDE_SDIOW #

Y22

IDE_SDDACK#

W20

IDE_SDDREQ

Y20

IDE_SDIOR#

Y23

IDE_S DIORDY

Y21

IDE_SDA2

W21

IDE_SDA1

W23

IDE_SDA0

W22

IDE_SDCS3#

V20

IDE_SDCS1#

V22

IDE_IRQ15

Y24

R263
0_0402_5%~D

1 2

3 1

Q46
MMBT3904_SOT23~D@

2

+3VRUN

IRQ_SERIRQ<20, 30,33>

H_SMI#<8>

220_0402_5%@

STPCLK#<36>

Note:
SATABIAS keep
less than
500mils

LPC_LAD[0..3]<33>

PWRGD_OK

ICH_SYNC# PWRGD_3V PWRGD_OK

0

0

111

+3VSUS

12

R138

10K_0402_5%~ D

R141 0_0402_5%~D

ID E_SD IOW # <23>
IDE_SDDACK# <23>

IDE_SDIOR# <23>
IDE_SDIORDY <23>
IDE _SD A[0. .2] <23>

IDE_SDCS3# <23>
IDE_SDCS1# <23>

IDE_I RQ15 <20,23>

+5VMOD

R269
1K_0603_5%~ D@

1 2

0

1

001

R140

0_0402_5%~D@

1 2

IDE_S DD[0.. 15] <23>

SIO_A20GATE<34>

CPUSLP#<36>
H_FERR#<8>

H_IGNNE#<8>

SIO_RCIN#<33>

R134

R127

0_0402_5%~D

SATA_M ODTX+<23>
SATA_M ODTX-<23>

SATA_MODRX-<23>
SATA_MODRX+<23>

1 2

R423 2 4.9_0603_1%~D

LPC_LFRAME#<33>

LPC_LDRQ0#<34>
LPC_LDRQ1#<33>

SUSPWROK< 36,37>

0

0

CBS_RI#ICH_RI#

12

3

+3VRUN

H_A20M#<8>

H_INIT#<8>
H_INTR<8>
H_NMI<8>

12

0_0402_5%~D

12

CK_100M_ICH<6>
CK_100M_ICH#<6>

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

CBS_RI# <30>

CPLD_WAKE# <36>

3

2

Top View

2

1

44

43

HH99227-S9

0_0402_5%~D

1 2

IDE_RST_HDD<33>IDE_RST_MOD<33> IDE_R ST_MOD_5V <23>

R271

SMI#

SATABIAS

LPC_LFRAME#
LPC_LDRQ0#
LPC_LDRQ1#

ICH_RTCX1
ICH_RTCX2
ICH_RTCRST#

12

R436

10K_0402_5%~ D

10K_0402_5%~ D@

IDE_RST _MOD_SFTON

1 2

U5D

T22

A20GATE

V23

A20M#

P22

CPUSLP#

U24

FERR#

R21

IGNNE#

R23

INIT#

U23

INTR

R22

NMI

P23

RCIN#

F23

SERIRQ

V24

SMI#

T24

STPCLK#

P20

DPRSLPVR(Mobile)

R24

DPSLP#(Mobile)

AA8

SATA0TXP

AB8

SATA0TXN

AD7

SATA0RXN

AC7

SATA0RXP

AA10

SATA1TXP

AB10

SATA1TXN

AD9

SATA1RXN

AC9

SATA1RXP

Y11

SATARBIASP

Y9

SATARBIASN

AC5

CLK100P

AD5

CLK100N

T5

LAD0

R4

LAD1

R3

LAD2

U4

LAD3

T4

LFRAME#

U5

LDRQ0#

R2

LDRQ1#/GPI41

AC11

RTCX1

AB12

RTCX2

AA12

RTCRST#

AB13

RSMRST#

AC12

PWROK

FW82801EB_mBGA460_ICH5~D

12

R432

10K_0402_5%~ D

CPLD Disable
Depop R141

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

3 1

CPUPWRGD/GPO49

PIDEACT#<38>

Connector on
bottom side

R265

Q51
MMBT3904_SOT23~D @

2

GPIO6
GPIO7
GPIO8

SMBALERT#/GPI11

GPIO12
GPIO13

GPO18

GPO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO27
GPIO28
GPIO32
GPIO33
GPIO34

SMBCLK

SMBDATA

SMLINK0
SMLINK1

LINKALERT#

SPKR

RI#

PWRBTN#

SUSCLK

TP0

SUS_STAT#

SLP_S3#
SLP_S4#
SLP_S5#

SYS_RESET#

VRMPWRGD

THRMTRIP#

THRM#

INTVRMEN

CLK14

INTRUDER#

NC

+VCC_CORE

10K_0402_5%~ D

H_THERMTRIP_R#

12/17/02 Changed by
Dell's Require

+5VHDD

1 2

+5VHDD

R568

1K_0402_5%~ D

PIDEACT#

R262
1K_0603_5%~ D

@

1 2

IDE_RST_HDD_5V

LK2-->USB2P0_SMI

R5
U3

SIO_EXT_SMI#

Y2

LAN_PME#

AC3

SIO_EXT_RTE#

W4

SIO_EXT_SCI#

W5
U21
T20
U22
R1
U20
F22
AC1
W3

BID2

V3

BID0

W2

BID1

T1

SATA_LED#

G23

BID3

F21

ICH_SMBCLK

AD2

ICH_SMBDATA

AD1

ICH_SMLINK0

AD3

ICH_SMLINK1

AA2

LINK_ALERT#

V5

R427

SPKR

E24

ICH_RI#

AB3
Y4

SUSCLK

Y1

ICH_BATLOW#

AB2
AB1

SIO_S LP_S3#

W1

SIO_S LP_S4#

U2

SIO_S LP_S5#

AA3

R122 10K_0402_5%~ D

U1

VRM_PWRGD

R20
P24

H_THERM TRIP_R#

T21

SIO_THRM#

T2

ICH_INTVRMEN

AD10
F20

ICH_THERM_PWRDN#

Y12

A11

R428

R422

1 2

0_0402_5%~D@

1

C469

0.1U_0402_16V4Z~D@

2

2

12

+5VHDD

R417

1 2

R421

1 2

R142

1 2

1 2

R135 10K_0 402_5%~D

1 2

H_TH ERMTRIP# <8,37>

IDE_RST_HDD_5V
IDE_PDD7 IDE_PDD8
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

RPDDREQ
IDE_PDIOW #
IDE_PDIOR#
IDE_P DIORDY
IDE_PDDACK#
IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#

10K_0402_5%~ D
10K_0402_5%~ D

10K_0402_5%~ D

+3VRUN

12

R388

10K_0402_5%~ D

10K_0402_5%~ D

SPKR <24>

SIO _PWR BTN# <33>

1 2

ICH_ SUS_STAT# <18>
SIO_SLP_S3# <33>

VRM _PWRGD <36>

H_PWR GOOD <8>

SIO_THRM# <33>

JHDD

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

SGND

49

SGND

B1

50

SGND

B2

SGND

FOX_H H99227-S9~D

+3VRUN

+3VSUS

+3VSUS

12

12

R143

R148

2.7K_ 0402_5%

2.7K_ 0402_5%

+3VSUS

+3VSUS

1 2

R424 0_0402_5%~D

1 2

R429 0_0402_5%~D

+3VSUS

CK_14M_ICH <6>

R400

10_0402_5%~D@

1 2

CK_14M_ICH_TERM

2

C428

+3.3VRTC

1

4.7P_ 0402_50V8C~D@

Title

Size Document Number Re v

Date: Sheet

IDE_PDD9

IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_CSEL_PRI

ATA_66_PRI/PDIAG
IDE_PDA2
IDE_PDCS3#

45
46
47
48

C238

R149

R132

@

@

R434 1 0K_0402_5%~D

1 2

R441

100K_0402_5%~D

1 2

Compal Electronics, Inc.

ICH5-IDE/LPC/PM/GPIO/LAN

LA-1711

1

470_0402_5%~D

1

2

C240

2

4.7U_ 1206_16V6K~D

R435 330K_0402_5%~D

1 2

C237

1

0.1U_0402_16V4Z~D

SIO_EXT_SMI#

SIO_EXT_RTE#

SIO_EXT_SCI#

SUSCLK

ICH_ SMBCLK < 6,15,16,32>
ICH_ SMBDATA < 6,15,16,32>

1 2
1 2

SIO_S LP_S4_S5# <33>

VRM_PWRGD

1 2

SIO_THRM#

1 2

R420 1 0K_0402_5%~D

ICH_THERM_PWRDN#

ICH_THERM_PWRDN# <37>

1

R570

12

T13
PAD@

2

1

0.1U_0402_16V4Z~D

SIO_EXT_SMI# <33>

SIO_EX T_RTE# <33>

SIO_EXT_SCI# <33>

SUS CLK <36>

10K_0402_5%~ D

10K_0402_5%~ D

VCC_RTC

R416

10K_0402_5%~ D

21 60Wednesday, July 23, 2003

+5VHDD

+3VSUS

+3VRUN

X02-D

of

5

4

3

2

1

+3VRUN +1.5VRUN

D D

+3VRUN

+5VRUN

21

1 2

D14

RB751V_SOD323~D

2

C468
1U_0805_10V6K~D

1

ICH_V5REF_RUN

2

C471

0.1U_0402_16V4Z~D

1

2

C472

0.1U_0402_16V4Z~D

1

+3VSUS

1K_0402_5%~ D

R391

Place near ball A8

+5VSUS

+3VSUS

21

1 2

D13

RB751V_SOD323~D

2

C447

1U_0805_10V6K~D

1

5

ICH_V5REF_SUS

2

C445

0.1U_0402_16V4Z~D

1

2

C444

0.1U_0402_16V4Z~D

1

Place near ball(VSS) A17

VCC_RTC

2

C506

0.1U_ 0402_10V6K~D

1

Place near ball AD11

4

C C

B B

A A

R384

1K_0402_5%~ D

B5

F6
G1
H6
K6

L6

M10

N10

P6

R13

V19
W15
W17
W24

AD13
AD20

G19
G21

E18

B15

E11

F10

F11

E13

E14

U6

V6
F16
F17
F18
K15

A8

W14

E16

AD11

AA11
AA13
AA21
AA24

AB11
AB15
AB18

AC10
AC13
AC23

AD17
AD21
AD12

U5E

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

V5REF
V5REF

V5REF_SUS

VCCRTC

FW82801EB_mBGA460_ICH5~D

U5F

A1

VSS

A7

VSS

A10

VSS

A15

VSS

A17

VSS

A19

VSS

A21

VSS

A23

VSS

AA5

VSS

AA7

VSS

AA9

VSS
VSS
VSS
VSS
VSS

AB5

VSS

AB7

VSS

AB9

VSS
VSS
VSS
VSS

AC2

VSS

AC4

VSS

AC6

VSS

AC8

VSS
VSS
VSS
VSS

AD4

VSS

AD6

VSS

AD8

VSS
VSS
VSS
VSS

B13

VSS

B17

VSS

B19

VSS

B21

VSS

B23

VSS

C3

VSS

C8

VSS

C16

VSS

C18

VSS

C20

VSS

C22

VSS

D1

VSS

D6

VSS

D11

VSS

D16

VSS

D18

VSS

D20

VSS

D22

VSS

D24

VSS

E17

VSS

E19

VSS

E20

VSS

E21

VSS

E23

VSS

F3

VSS

F9

VSS

FW82801EB_mBGA460_ICH5~D

VCCSUS1_5_A
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_C
VCCSUS1_5_C

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

VCCSATAPLL
VCCSATAPLL

VCCUSBPLL

V_CPU_IO
V_CPU_IO
V_CPU_IO

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K10
K12
K13
L19
P19
R10
R6
H24
J19
K19
M15
N15
N23
E15
F15
F14
W19
R12
W9
W10
W11
W6
W7
W8
E22

AA6
AB6
C24

F19
Y5
AA4
AB4
F7
F8

R15
R19
T19

G6
G20
G24
H1
H19
H22
J6
J21
J23
K3
K11
K14
K20
K22
K24
L10
L11
L12
L13
L14
L15
L21
L23
M1
M5
M11
M12
M13
M14
M22
M24
N11
N12
N13
N14
N20
P1
P10
P11
P12
P13
P14
P15
P21
R11
R14
T23
T3
T6
U19
V1
V21
W16
W18
Y3
Y6
Y7
Y8
Y10

3

Place near
ball (VSS)A19

C430 0 .01U_0402_16V7K~ D

VCCSUS15_A

VCCSUS15_B

VCCSUS15_C

1 2

C475 0 .01U_0402_16V7K~ D

1 2

1 2

C433 0 .01U_0402_16V7K~ D

Place near

+VCC_CORE

ball (VSS)A7

+VCC_CORE

Place near
ball T22

2

C470

0.1U_0402_16V4Z~D

1

Place0.1u near ball(VSS)
A17,A23,V1.Addition cap near

+3VSUS

A15,A19

C435

1U_0603_6.3V6M~D

1 2

C467

0.1U_0402_16V4Z~D

C424

0.1U_0402_16V4Z~D

C446

0.1U_0402_16V4Z~D

C425

0.01U _0402_16V7K~D

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

Place near ball(VSS)
D1,A7,H1,P1W24 and A21

Place near
ball ( VSS)AD4

12

12

12

+1.5VRUN +1.5VRUN

0.1U_0402_16V4Z~D

0.01U _0402_16V7K~D

1 2

2

C432

0.1U_0402_16V4Z~D

12

C457

0.1U_0402_16V4Z~D

12

C453

0.1U_0402_16V4Z~D

12

C463

0.1U_0402_16V4Z~D

12

C449

0.1U_0402_16V4Z~D

12

C466

0.1U_0402_16V4Z~D

12

Place near ball D24 Place near ball AD6

C429

12

C426

Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page278

+1.5VRUN+3VRUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U _0402_16V7K~D

1 2

C473

0.1U_0402_16V4Z~D

C489

0.01U _0402_16V7K~D

1 2

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

ICH5 Power & Decoupling

LA-1711

Place0.1u near ball(VSS)
G24,H24,K24,M24,AD4
and AD18; 0.01u near to

C491

ball AD8.

12

C451

12

C454

12

C474

12

C497

12

C448

12

C450

12

1

X02-D

of

22 60Wednesday, July 23, 2003

5

IDE_SDD[0..15]<21>

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9

D D

IDE_SDA[0..2]<21>

IDE_S DCS1#<21>
IDE_S DCS3#<21>

IDE_S DDACK#<21>

IDE_SDIOR#<21>
IDE_SDIOW#<21>
IDE_SDIORDY<21>

INT_CD_R<24>

INT_C D_L<24>

C C

B B

IDE_IRQ15<20,21>

BAY_MODPRES#<33>

RSDDREQ<21>

IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_S DCS1#
IDE_S DCS3#

IDE_S DDACK#

IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY

INT_CD_R

INT_CD_L

IDE_IRQ15

BAY_MODPRES#

RSDDREQ

IDE_RST_MOD_5V<21>

USB_IDE#<33>

+3VRUN +3VRUN

IDE_RST_MOD_5V

R554

100K_0402_5%~D

1 2

swap by Dell require
Please see sketch

SATA_MODTX+<21>

SATA_MODTX-<21>

R563

1 2

470_0402_5%~D

R555

0_0402_5%~D

1 2

CD_AUDIORET<24>

1 2

100K_0402_5%~D

SATA_MODRX+<21>

SATA_MODRX-<21>

R553

4

Reserved USB+

Reserved USB-

IDE_S DCS3#

IDE_SDA2

IDE_SDA0

IDE_SDA1

CSEL2

IDE_SDIOR#

IDE_SDIOW#

IDE_SDD15

IDE_SDD1

IDE_SDD2

IDE_SDD12

IDE_SDD11

IDE_SDD5

IDE_SDD6

IDE_SDD8

MOD_RST

USB_IDE#

CD_AU DIORET

BAY_MODPRES#

G69G

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

G70G

FOX_QL11343-A6B3-HT~D

3

JMOD1

73

71

M1

1

1

3

3

5

5

7

7

9

9

11

11

SATA_MOD_DETECT#

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

M2

74

72

+3VMOD

SATA_MOD_DETECT# <33>

MOD_PIN15

USBP4_D+

USBP4_D-

SIDEACT#

IDE_S DCS1#

PDIAG#

IDE_IRQ15

IDE_S DDACK#

IDE_SDIORDY

RSDDREQ

IDE_SDD0

IDE_SDD14

IDE_SDD13

IDE_SDD3

IDE_SDD4

IDE_SDD10

IDE_SDD9

IDE_SDD7

INT_CD_R

INT_CD_L

1

C614

C617

2

0.1U_0402_16V4Z~D

4.7U_1206_16V6K~D

R564 1K_0402_5%~D

T12

1

1

C602

C601

2

2

47P_0402_50V8J~D

47P_0402_50V8J~D

+5VMOD +3VMOD

1

1

1

C616

C615

2

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R567

1 2

0_0402_5%~D@

1 2

PAD@

INT_CD_R <24>

INT_CD_L <24>

+3VMOD

2

USBP4_D+ <26>

USBP4_D- <26>

USB_OC4# <20>

1

1

C613

0.1U_0402_16V4Z~D

2

1

C612

0.1U_0402_16V4Z~D

2

+3VRUN

SATA_MOD_DETECT#USB_OC4#

R569

1 2

100K_0402_5%~D

1

2

3

6

WF1F068N1A

4

5

MB side Module side

Connector

RX+

RX-

Host Chip

A A

ICH5

TX+

TX-

TX+

TX-

RX+

RX-

Device Chip

Direct connect

5

4

D-MODULE Detect

JMOD1

Device

Parallel IDE

USB Device

S-ATA IDE

None

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

Pin68

BAY_MODPRES#

LOW

LOW

LOW

Pin64

USB_IDE#

LOW

HIGH HIGH

HIGH

HIGH X X

Pin13

SATA_MOD_DETECT#

HIGH

LOW

2

TOP VIEW

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

D- MODULE

LA-1711

1

23 60Wednesday, July 23, 2003

X02-D

of

5

+5VSUS

1

C208

2

0.1U_0402_16V4Z~D

D D

+5VRUN

1

C158

0.1U_0402_16V4Z~D

2

SPDIF

5

A2Y

3

2

1

C198

C209

1

2

1U_0805_10V6K~D

0.01U_0402_16V7K~D

SPDIF_SHDN

1

U12

P

4

OE#

G

SN74AHCT1G125DCKR_SC70-5~D

AUDIO_AVDD_ON<34>

AUDIO_AVDD_ON TPS793475_BYPASS

SP_D IF <18>

1

2

3

4

U22

5

OUT

IN

GND

4

BYPASS

EN

TPS79 3475DBVR_SOT23-5~D

1

C224

2

0.1U_0402_16V4Z~D

VDDA=4.75V

1

C215

2

0.1U_0402_16V4Z~D

VDDA

1

C216

2

2.2U_0805_16VFZ~D

3

VDDA

L23
BLM11A121S_0603~D

1 2

U21

5

SN74AHCT1G86DCKR_SC70-5~D

1

SPKR<21>

BEEP<33>

CBS_SPK<30>

P

A

Y

2

B

G

3

Z2401

4

Z2402

R237
43K_0402_5%~ D

1 2

2

5

U20

1

P

A

4

Y

2

B

G

SN74AHCT1G86DCKR_SC70-5~D

3

1

C212

0.1U_0402_16V4Z~D

2

R223

20K_0402_5%

Z2403 PC_BEEPINZ2404

1 2

8.2K_ 0402_5%~D

4

5

1

2

single gate TTL

C192

0.1U_0402_16V4Z~D

1 2

12

R221

1

3

2

C190
1000P_0402_50V7K~D

@

1

+3VRUN

2

2

C170

C C

R531

33_0402_5%~D

ICH_AC_BITCLK<20>

MDC_AC_BITCLK<27>

ICH_AC_SDIN0<20>

C571

27P_06 03_50V8J~D@

2.2U_0805_16VFZ~D
C186

2

1

B B

A A

5

AC97VREFI

0.1U_0402_16V4Z~D
C578

2

1

ICH_AC_SDOUT

1 2

ICH_AC_SDOUT_TERM

1

@

2

1 2

R525

33_0402_5%~D

1 2

R534

33_0402_5%~D

1 2

1

1

2

R526
47_0402_5%~D

C570
22P_0402_50V8J~D

2

C579

27P_06 03_50V8J~D@

2

C573

0.1U_0402_16V4Z~D

1

CK_14M_CODEC<6>

7/22/2 003 Dell request (Mr. Richard)

22P_04 02_50V8J~D

0.1U_0402_16V4Z~D

ICH_AC_RST#<20,27>
ICH_AC_SYNC<20,27>
ICH_AC_SDOUT< 20,27>

C575 1000P_0402_50V7K~D

C171 1000P_0402_50V7K~D

SPK_SHUTDOWN#<25,50>

EAPD<25>

C183

22P_04 02_50V8J~D

1 2

C168

1 2

12

1

1 2

1 2

1 2

C161

C576

1

0.1U_0402_16V4Z~D

ICH_AC_RST#
ICH_AC_SYNC
ICH_AC_SDOUT

R_ICH_AC_BITCLK

R_ICH_AC_SDIN0

C176

0.1U_0603_16V7K~D

@

SPK_SHUTDOWN#

12

R512
10K_0402_5%~ D

R614

1 2

0_0402_5%~D@

X2

24.576 MHz_20P_1BX24576CC1A~D

PACKAGE : 8X4.5X1.5mm

1 2

R613

1 2

0_0402_5%~D@

R619
0_0402_5%~D

4

2

1

2.2U_0805_16VFZ~D

AFLT1

AFLT2

VREFOUT

SPDIF_SHDN

SPDIF

EAPD

XTL_24M+

XTL_24M-

12

R612
10_0402_5%~D@

1

C669

4.7P_0402_50V8C~D

@

2

W=30 mil

CAP2

11
10

5

6

8

29

30

28

27

32

43

44

48

47

31

33

34

46
45

3

2

U16

RESET#
SYNC
SDATA_OUT

BIT_CLK

SDATA_IN

AFLT1

AFLT2

VREFOUT

VREF

CAP2

GPIO0/NC

GPIO1/NC

SPDIF

EAPD

NC/BPCFG

NC/FLTIN

NC/FLTOUT

CID1
CID0

XTL_OUT

XTL_IN

9

DVDD11DVDD2

STAC9750

DVSS14DVSS2

7

C580

38

LINE_IN_L

AVDD125AVDD2

LINE_IN_R

VIDEO_L

VIDEO_R

PC_BEEP

HP_OUT_L

HP_COMM

HP_OUT_R

MONO_OUT

LOUT_L

LOUT_R

AVSS126AVSS2

STAC9 750_TQFP48~D

42

0.1U_0402_16V4Z~D

CD_L

CD_C

CD_R

AUX_L

AUX_R

MIC1

MIC2

PHONE

2

1

AUDI O_AVCC

2

C559

1

0.1U_0402_16V4Z~D

23

24

CD_L

18

CD_COMM

19

CD_R

20

14

15

CNB_MICIN

21

22

16

17

13

PC_BEEPIN

12

39

HP_COMM

40

41

37

35

36

3

L16

BLM31A260SPT_1206~D

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

VDDA

C195 1U_0805_10V6K~D

1 2

C196 1U_0805_10V6K~D

1 2

C197 1U_0805_10V6K~D

1 2

C201

0.22U _0603_10V7M~D

1 2

1 2

C199

0.1U_0402_16V4Z~D

1 2

C200

0.1U_0402_16V4Z~D

C162

1U_0805_10V6K~D

1 2

2

C569
1000P_0402_50V7K~D

1

2

C565
1000P_0402_50V7K~D

1

CD_AUDIORET

HP_OU T_L <25>

HP_ OUT_ R <25>

AUD_MONO_OUT <50>

AUD_LINE_OUT_L <25>

AUD _LI NE_O UT_R <25>

2

INT_CD_L <23>

CD_AUDIORET <23>

INT_CD_R <23>

NB_MICIN <25>

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

AC97 Codec

LA-1711

of

1

24 60Wednesday, July 23, 2003

X02-D

5

2

1K_0402_5%~ D

R_INT_MIC-

2

1K_0402_5%~ D

1

C169

1

1U_0805_10V6K~D

R505

1 2

R497

1 2

13

D

2

G

S

D D

INT_MIC-<38>

INT_MIC+<38>

C165

+3VRUN

R197
100K_0402_5%~D

2

G

1 2

13

D

Q39

2N700 2_SOT23~D

S

SPK_SHUTDOWN#<24,50>

C C

SPK_SHUTDOWN#

EAPD<24>

1U_0805_10V6K~D

HP_NB_SENSE

R_INT_MIC+

R517

INT_MIC-

INT_MIC+

Q40

2N700 2_SOT23~D

4

VDDA

R511
1K_0402_5%~ D

1 2

1 2

1K_0402_5%~ D

NB_MUTE<33>

2.2U_0805_16VFZ~D

C561

0.1U_0402_16V4Z~D

1 2

1 2

C179

0.1U_0402_16V4Z~D

2

G

AMPVCC

EXT_MIC_BIAS

MIC_SELECT

C178

1 2

3

W=15mils

R503
100K_0402_5%~D

1 2

AUD_LINE_OUT_R<24>

4

VSUP

EXT_MIC_BIAS

3

2

OUT

1

NB_MICIN <24>

EXT_MIC_PLUG

EMICIN

EXT_MIC_PLUG

EXT_MIC_BIAS
EMICIN

+5VRUN

FAN1_VOUT< 14> FAN1_TACH_FB <14>

AUD_LINE_OUT_L<24>

JAUDO

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

NAIS_ AXN320C038P~D

2
4
6
8
10
12
14
16
18
20

VDDA +3VRUN

L46

BLM11A121S_0603~D

1 2

C157

13

D

Q38
2N700 2_SOT23~D

S

2

1

C_INT_MIC-

C_INT_MIC+

C_EXT_MIC+

2

C545

0.1U_0402_16V4Z~D

1

U13

5

INT_MIC-

6

INT_MIC+

7

GND

8

EXT_MIC_IN

CMAMP110M_MSOP8~D

0.1U_0402_16V4Z~D

HP_NB_SENSE

HP_OUT_LMAX
HP_OUT_RM AX

2

+3VRUN

12

R459
10K_0402_5%~ D

C535

1U_06 03_6.3V6M~D

1 2

1 2

C539

1U_06 03_6.3V6M~D

1

C537
1U_06 03_6.3V6M~D

2

HP_NB_SENSE

AUD_LINE_IN_R

AUD_LINE_IN_L

14

18

15

13

1U_0603_6.3V6M~D

1

1

C529
1U_06 03_6.3V6M~D

2

10

19

U38

SHDNR#

SVDD

PVDD

SHDNL#

INR

INL

1

C1P

3

C1N

C547

PGND

PVss

SVss

SGND

2

5

7

17

1

2

HP_OUT_RM AX

11

OUTR

HP_OUT_LMAX

9

OUTL

4

NC-4

6

NC-6

8

NC-8

12

NC-12

16

NC-16

20

NC-20

MAX4411ETP-T_TQFN20~D

60mil single end connection near JACK

1
2
3
4
5
6
7
8

1

2

JSPK
MOLEX_53398-0890~D

9

9

1
2
3
4
5
6
7
8

10

10

D9

DDA204U@

3

INT_ SPK_L1
INT_ SPK_L2
INT_ SPK_R1
INT_ SPK_R2

D8

1

DDA204U@

3

2

TRACE>15 mil

INT_ SPK_L2
INT_ SPK_L1
INT_ SPK_R2

INT_ SPK_L1

L48

1 2

W=40mils

1

C626

0.1U_0402_16V4Z~D

B B

HP_OUT_R<24>

HP_OUT_L<24>

2

C630

1 2

0.47U _0603_16V4Z

C631

1 2

0.47U _0603_16V4Z

C632

1 2

0.47U _0603_16V4Z

C633

1 2

0.47U _0603_16V4Z

1

C627

0.1U_0402_16V4Z~D

2

15

16

U18

7

17

9

5

VDD

RIN+

RIN-

LIN+

LIN-

BLM21A05_0805

+5VA MPVCC

6

PVDD1

PVDD2

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

1

C628
10U_0805_10V4M~ D

2

AUD_GAIN0

AUD_GAIN1

INT_SPK_R1

INT_SPK_R2

INT_ SPK_L1

INT_ SPK_L2

+5VRUN

1

C629

0.1U_0402_16V4Z~D

2

AUD_GAIN0

AUD_GAIN1

+5VRUN

12

12

R582
10K_0402_5%~ D

R584
10K_0402_5%~ D @

Gain Setting

12

R583
10K_0402_5%~ D@

12

R585
10K_0402_5%~ D

INT_SPK_R1

+5VRUN

1 2

1 2

C638

22U_1206_16V4Z_V1

D7

1

2

C639

22U_1206_16V4Z_V1

INT_ SPK_R1
INT_ SPK_L2
INT_TWT_L1
INT_ SPK_R2
INT_TWT_R1

D6

1

DDA204U@

3

DDA204U@

3

2

12

NC

BYPASS

10

SPK_SHUTDOWN#<24,50>

A A

5

19

SHUTDOWN

BYPASS

GND41GND311GND213GND1

TPA6017A2PWPR_TSSOP20~D

20

4

1

C634

0.47U _0603_16V4Z

2

1

C635

0.1U_0402_16V4Z~D

@

2

GAIN0 GAIN1 AV(inv) INPUT

0

0

10dB0

1

0

1

*

11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

15.6dB

21.6dB

6dB

IMPEDANCE

90K ohm

70K ohm

45K ohm

25K ohm

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

AMP and Phone Jack Interface

LA-1711

1

X02-D

of

25 60Wednesday, July 23, 2003

5

R8 0_0402_5%~D

1 2

L2

DLW21SN900SQ2_0805~D@

USBP5-<20>

USBP5+<20>

D D

USBP1+<20> USBP1_D+ <27>

USBP1-<20>

USBP2-<20>

USBP2+<20>

USBP3-<20>

C C

USBP3+<20>

USBP4+<20>

USBP4-<20>

USBP6-<20>

USBP6+<20>

B B

1

1

4

4

R7 0_0402_5%~D

1 2

R408 0_0402_5%~D

1 2

DLW21SN900SQ2_0805~D@

1

1

4

4

1 2

R6 0_0402_5%~D

1 2

DLW21SN900SQ2_0805~D@

1

1

4

4

R5 0_0402_5%~D

1 2

R12 0_0402_5%~D

1 2

DLW21SN900SQ2_0805~D @

1

1

4

4

R11 0_0402_5%~D

1 2

R565 0_0402_5%~D

1 2

DLW21SN900SQ2_0805~D@

1

1

4

4

R566 0_0402_5%~D

1 2

R10 0_0402_5%~D

1 2

DLW21SN900SQ2_0805~D@

1

1

4

4

R9 0_0402_5%~D

1 2

2

2

3

3

L44

2

2

3

3

R407 0_0402_5%~D

L1

2

2

3

3

L4

2

2

3

3

L47

2

2

3

3

L3

2

2

3

3

C3

C462

C2

C610

C5

47P_0402_50V8J@

47P_0402_50V8J@

47P_0402_50V8J@

C8
47P_04 02_50V8J@

47P_0402_50V8J@

47P_0402_50V8J@

C4

C461

C1

C611

C6

47P_0402_50V8J@

47P_0402_50V8J@

47P_0402_50V8J@

C7
47P_0402_50V8J@

47P_0402_50V8J@

47P_0402_50V8J@

4

USBP5_D-

USBP5_D+

USBP1_D+ USBP2_D+

USBP1_D-

USBP2_D-

USBP2_D+

USBP3_D-

USBP3_D+

USBP4_D+

USBP4_D-

USBP6_D-

USBP6_D+

PLACE CHOKE(Resistors)
NEAR CONNECTOR

USBP1_D- <27>

USBP4_D+ <23>

USBP4_D- <23>

+5VSUS

1 2

13

DH_POW ER_EN

D

2

G

S

R17
10K_0402_5%~ D

DH_POWER_EN #

Q4
2N7002_SOT23~ D

2

G

3

+5VSUS

1 2

13

D

S

USBP5_PWR

USBP2_PWR

USBP6_PWR

R27
10K_0402_5%~ D

Q1
2N7002_SOT23~ D

L27

BLM21 PG600SN1D_0805~D

1 2

L30

BLM21 PG600SN1D_0805~D

1 2

1 2

L24

BLM21 PG600SN1D_0805~D

1 2

L25

BLM21 PG600SN1D_0805~D

L29

BLM21 PG600SN1D_0805~D

1 2

L28

BLM21 PG600SN1D_0805~D

1 2

DAT_SMB<19,34,35,47>

CLK_SMB<19 ,34,35,47>

C262

150U _D2_6.3VM~D

C261

150U _D2_6.3VM~D

C263

150U _D2_6.3VM~D

DAT_SMB

2

1

1

+

C257

2

2

USBP5_VCC
USBP5_D­USBP5_D+

0.1U_0402_16V4Z~D

USBP5_GND

USBP2_VCC
USBP2_D-

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

2

G

2

2

G

S

Q6

2N700 2_SOT23~D

S

Q2

2N700 2_SOT23~D

USBP2_GND

1

+

C258

2

1

+

C259

2

D

1 3

1 3

D

USBP6_VCC
USBP6_D­USBP6_D+
USBP6_GND

USBP3_PWR

DH_S MBDAT

DH_SMBCLKCLK_SMB

PWR_SRC

JUSB1

1
2
3
4

SUYIN_2569A-04G3T

JUSB2

1
2
3
4

SUYIN_2569A-04G3T

JUSB3

1
2
3
4

SUYIN_2569A-04G3T

L31

BLM21 PG600SN1D_0805~D

1 2

C265

150U _D2_6.3VM~D

1 2

L26

BLM21 PG600SN1D_0805~D

1

2

+

1

2

USB PORT#

C260

0.1U_0402_16V4Z~D

DH_MOD_PRES#<34>

0

1

2

3
4

5

6

7

1

DESTINATION

USBP3_VCC
USBP3_D­USBP3_D+
USBP3_GND

DH_PORT_PWRSRC
DH_S MBDAT

DH_SMBCLK

Reserved

BT

BACK

DOG

MOD

BACK

BACK

Reserved

JDOG

1

T1

2

T2

3

T3

4

T4

5

PWR_SRC

6

SMB_DATA

7

SMB_ALERT

8

SMB_CLK

9

GND

10

SHILD1

11

SHILD2

12

SHILD3

13

SHILD4

FOX_U B11193-P01-TR~D

R318

100K_0402_5%~D

1 2

36

241

Q66

578

Q9
2N7002_SOT23~ D

2

G

2

SI4435DY_SO8~D

DH_PW RSRC

DH_POW ER_EN <33>

R307

100K_0402_5%~D

F1

1.8A_33VDC_SMD185~D

1 2

F2

RAY_RUE250@

DH_PWR_OC#

12

USBP6_PWR

8
7
6
5

8
7
6
5

USBP3_PWR

USBP5_PWR

USBP2_PWR

USB_OC6# <20>

USB_OC3# <20>

USB_OC5# <20>

USB_OC2# <20>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

+5VSUS

U32

1

GND

OC1#

2

IN

OUT1

1

C268

0.1U_0402_16V4Z~D

A A

0.1U_0402_16V4Z~D

USB_EN#<33>

5

C269

2

+5VSUS

1

2

4

3

EN1#

4

EN2#

TPS2042ADR_SO8~D

U31

1

GND

2

IN

3

EN1#

4

EN2#

TPS2042ADR_SO8~D

OUT2

OC2#

OC1#
OUT1
OUT2

OC2#

Z2501

12

R317

1

C292

100K_0402_5%~D

2

0.022U_0603_50V4Z~D

Z2502

13

D

S

Follow LK2 and need confirm final SPEC

L5

DH_F USE_PWRSRC

R306

1 2

100K_0402_5%~D

2

G

Title

Size Document Number Re v

Date: Sheet

BLM21 PG600SN1D_0805~D

1 2

+3VRUN

12

R316
10K_0402_5%~ D

DH_PWRSRC_OC

13

D

Q64
2N700 2_SOT23~D

S

Compal Electronics, Inc.

LA-1711

DH_PORT_PWRSRC

C9

0.1U_ 0603_25V7M~D

DH_PWRSRC_OC <33>

USB(2.0) Connector

1

26 60Wednesday, July 23, 2003

1

2

X02-D

of

5

4

3

2

1

TOP view

MDC cable wire clip

D D

PAD2

1

MDC_ CLIP

PAD3

1

MDC_ CLIP

BT_ACTIVE<38>

T2
PAD

@

C C

COEX2_WLAN_ACTIVE<32>

HW_RADIO_DIS#<32,34>

COEX1_BT_ACTIVE<32>

USBP1_D-<26>
USBP1_D+<26>

0.1U_0402_16V4Z~D

COEX2_WLAN_ACTIVE
HW_RADIO_DIS#
COEX1_BT_ACTIVE
COEX3
USBP1_D­USBP1_D+

C459

+3VSUS

12

L43

BLM11A601S_0603~D

1

2

BT_PWR

JBT

10

10

9

9

8

8

7

7

6

12

6

12

5

11

5

11

4

4

3

3

2

2

1

1

12

JST_BM10B-SRSS-TB~D

R412

10K_0402_5%~D@

+3VSUS

FOX_HS6210_10P

1

10

JMDC

2

MDM_MONO_PHONE

R449

10K_0402_5%~D@

+3VSUS

ICH_AC_SDIN1<20>

7/28 Changed to NP

B B

A A

5

by Dell's require

1 2

ICH_AC_SYNC<20,24>

MDC_AC_BITCLK<24>

33_0402_5%~D

1 2

1

C527
22P_0402_50V8J~D

@

2

R457

4

Z2602

MDC_SDIN

12

R454

10K_0402_5%~D@

R462

10_0402_5%~D@

1 2

MDC_AC_BITCLK_TERM

2

C530
10P_0402_50V8J~D

@

1

AUDIO_PWDN

4

MONO_PHONE

6

RESERVED

8

GND

10

+5V

12

RESERVED

14

RESERVED

16

PRIMARY_DN

18

RESERVED

20

RESERVED

22

AC97_SYNC

24

AC97_SDATA_IN1

26

AC97_SDATA_IN0

28

GND

30

AC97_BITCLK

AMP_3-1612118-0~D

MONO_OUT/PC_BEEP

AUXA_RIGHT

AUXA_LEFT

AC97_SDATA_OUT

AC97_RESET#

AC97_MSTRCLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

AGND

CD_GND

CD_RIGHT

CD_LEFT

GND

3.3Vaux
GND

3.3Vmain

GND

3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

W=20 mil

Z2604

12

R463

0_0402_5%~D @

1

C159

2

4.7U_1206_16V6K~D

R458

10_0402_5%~D@

1 2

ICH_AC_SDOUT_MDCTERM

2

C526
10P_0402_50V8J~D

@

1

1

C525

2

0.1U_0402_16V4Z~D

ICH_A C_SDOUT <20,24>
ICH_A C_RST# <20,24>

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

BT PORT and MDC

LA-1711

1

27 60Wednesday, July 30, 2003

X02-D

of

+3VSRC

SI3456DV-T1_TSOP6~D

6

2
1

ENAB_3VLAN<39>

D D

V_1P2_LAN

BLM11A601S_0603~D

Place within 100 mils to pins H14

PCI_AD [0..31]<20,30,32>

C C

B B

V_3P3_LAN

A A

SYS_PME#<30,32,33>

CK_33M_LANPCI

Q18

D

S

G

3

L33

1 2

PCI_C_BE3#<20,30,32>
PCI_C_BE2#<20,30,32>
PCI_C_BE1#<20,30,32>
PCI_C_BE0#<20,30,32>

PCI_AD16

PCI_FRAME#<20,30,32>
PCI_IRDY#<20,30,32>
PCI_TRDY#<20,30,32>
PCI_DEVSEL#<20,30,32>
PCI_STOP#<20,30,32>

PCI_PERR#<20,30,32>
PCI_SERR#<20,30,32>

PCI_PAR<20,30,32>

CK_33M_LANPCI<6>

PCI_PIRQC#<20,30>
PCIRST_1#<20>
PCI_GNT4#<20>
PCI_R EQ4#<20>

1K_0402_5%~D

SYS_PME#

R319

10_0402_5%~D@

5

VAUX_LAN

45

C11

2.2U_0 805_16VFZ~D

R49

100_0402_5%~D

1 2

R303

12

CLK_82540_TERM

12

5

BLM31A260SPT_1206~D

1 2

V_1P2 _PLLVDD_PHY

20mils trace width

2

1

C17

1

2

0.1U_0402_16V4Z~D

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

LAN_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
CK_33M_LANPCI

PCI_PIRQC#
PCIRST_1#
PCI_GNT4#
PCI_R EQ4#

LAN_AUXPWR

L37

2

C343

1

10U_1206_6.3V7K~D

2

C281

C282

1

0.1U_0402_16V4Z~D

2

C315

C310

1

0.1U_0402_16V4Z~D

BCM5705M

OR
BCM4401

8.2P_0402_50V8J~D@

C321

1 2

2

C350

1

10U_1206_6.3V7K~D

+3V_LOM_PCI

U2A

B8

AD31

A8

AD30

C7

AD29

C6

AD28

B6

AD27

B5

AD26

A5

AD25

B4

AD24

B2

AD23

B1

AD22

C1

AD21

D3

AD20

D2

AD19

D1

AD18

E3

AD17

K1

AD16

L2

AD15

L1

AD14

M3

AD13

M2

AD12

M1

AD11

N2

AD10

N3

AD9

P3

AD8

N4

AD7

P4

AD6

M5

AD5

N5

AD4

P5

AD3

P6

AD2

M7

AD1

N7

AD0

C4

CBE3

F3

CBE2

L3

CBE1

M4

CBE0

A4

IDSEL

F2

FRAME

F1

IRDY

G3

TRDY

H3

DEVSEL

H1

STOP

J2

PERR

A2

SERR

J1

PAR

A3

PCI_CLK

H2

INTA

C2

PCI_RST

J3

GNT

C3

REQ

J12

VAUXPRSNT

F4

M66EN

A6

PME

BCM5705M_FBGA196~D1@

5705M :1.24K_0402_1%
4401: 1.27K_0402_1%

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

1

2

1

C272

0.1U_0402_16V4Z~D

C330

0.1U_0402_16V4Z~D

4

2

2

1

2

1

C286

C278

1

0.1U_0402_16V4Z~D

2

C341

C340

1

0.1U_0402_16V4Z~D

TRD3+

TRD3-

TRD2+

TRD2-

TRD1+

TRD1-

TRD0+

TRD0-

REGSUP12

REGCTL12

REGSEN12

REGSUP25

REGCTL25

REGSEN25

VESD1
VESD2
VESD3

EEDATA

EECLK

GPIO0
GPIO1
GPIO2

LINKLEDB

SPD100LEDB
SPD1000LEDB
TRAFFICLEDB

PLLVDD2

XTALVDD

XTALO

BIASVDD

RDAC

SMB_CLK

SMB_DATA

TCK

TDO
TMS

TRST

XTALI

SCLK

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

NC

TDI

SO

CS

2

C275

1

2

C323

1

E13
E14
D13
D14
C13
C14
B13
B14

B9
B10
A9

B11
C11
C10

P1
G2
A1

P10
M10

H12
K13
J13

G13
H13
G12
G14

H14
P7

C12
D12
B12
A12
D11

J14
N10
N11

G11
E10

SI

E11
H11

A14
D10

A10
C9

2@ BCM4401

Place within 50 mils of
ASIC pin D10

8-10mils trace width

4

V_3P3_LAN

2

1

0.1U_0402_16V4Z~D

V_3P3_LAN

2

1

0.1U_0402_16V4Z~D

LAN_TX3+
LAN_TX3­LAN_TX2+
LAN_TX2­LAN_RX1+
LAN_RX1­LAN_TX0+
LAN_TX0-

LAN_CTRL_1P2V

LAN_CTRL_2P5V

LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK

LAN_GPIO0
LAN_EEPROM_W
LAN_GPIO2

LINK_LED_10#
LINK_LED_100#
LINK_LED_1000#
LAN_ACT#

V_1P2 _PLLVDD_PHY

4.7K_0402_1%~D

LAN_TRST#

XTALO
XTALI

22P_0402_50V8J~D

Place within 100 mils to pins N10 and N11

LAN_BIAS
LAN_RDAC

LAN_SMBCLK
LAN_SMBDATA

B

1

BCP69_SOT-2231@

LAN_CTRL_2P5V

LAN_TX3+ <29>
LAN_TX3- <29>
LAN_TX2+ <29>
LAN_TX2- <29>
LAN_RX1+ <29>
LAN_RX1- <29>
LAN_TX0+ <29>
LAN_TX0- <29>

V_2P5_LAN

V_1P2_LAN

V_3P3_LAN

V_2P5_LAN

+3VRUN

T8 PAD@

T7 PAD@

LINK_LED_10# <29>
LINK_LED_100# <29>
LINK_LED_1000# <29>
LAN_ACT# <29>

R310

12

V_2P5_LAN

25MHz_20P_1BX25000CK1A~D

2

C18

22P_0402_50V8J~D

1

12

R311

1.24K_0402_1%~D 1@

2@ 1.27K_0402_1%~D

3

V_2P5_LAN

BCP69

C

2

C

E

4

3

Q65

1

X1

2

C271
1000P_0402_50V7K~D

1

Place within 100 mils of ASIC
pin A14, 10mils trace width

C332

3

2

4

C333

LAN_SMBCLK
LAN_SMBDATA

+3V_LOM_PCI

12

2

C34

1

1 2

L35

BLM11A601S_0603~D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

2

C316

1

1

10U_1206_6.3V7K~D

0.1U_0402_16V4Z~D

1

1

C344

2

2

10U_1206_6.3V7K~D

10U_1206_6.3V7K~D

V_3P3_LAN +3VRUN

L39

10U_1206_6.3V7K~D

V_2P5_LAN

LAN_CTRL_1P2V

C312

LAN_SMBCLK <32>
LAN_SMBDATA <32>

1 2

C25

Q5

BCP69_SOT-2231@

2

1

0.1U_0402_16V4Z~D

BLM11A601S_0603~D2@

V_2P5_LAN

V_3P3_LAN

C270

0.1U_0402_16V4Z~D

L38

C349

5705M_CLKRUN#

R321

1 2

3

2

1

0.1U_0402_16V4Z~D

V_1P2_LAN

2

4

V_2P5_LAN

10U_1206_6.3V7K~D

C266

10U_1206_6.3V7K~D

1

2

C279

1

1 2

BLM11A601S_0603~D 1@

2

1

10K_0402_5%~D

Should be pulled down for both 4401 and 5705M

2

1

1

2

E12

H5
H6
H7
H8

J5
J6
J7
J8
J9

J10

K5
K6
K7
K8
K9

K10

L5
L10
M14
N14

P8
P12
P13
P14

A7

B3

C5

E1

E4

G1

K3

L4

N6

P2

K14
L13
P11

A11
F11
K12
L12

C8
H4

H10

J4

K4

J11

K11

L7

L8

2

C291

1

0.1U_0402_16V4Z~D

1

C267

2

10U_1206_6.3V7K~D

U2B

VDDC_E12
VDDC_H5
VDDC_H6
VDDC_H7
VDDC_H8
VDDC_J5
VDDC_J6
VDDC_J7
VDDC_J8
VDDC_J9
VDDC_J10
VDDC_K5
VDDC_K6
VDDC_K7
VDDC_K8
VDDC_K9
VDDC_K10
VDDC_L5
VDDC_L10
VDDC_M14
VDDC_N14
VDDC_P8
VDDC_P12
VDDC_P13
VDDC_P14

VDDIO-PCI_A7
VDDIO-PCI_B3
VDDIO-PCI_C5
VDDIO-PCI_E1
VDDIO-PCI_E4
VDDIO-PCI_G1
VDDIO-PCI_K3
VDDIO-PCI_L4
VDDIO-PCI_N6
VDDIO-PCI_P2

VDDP_K14
VDDP_L13
VDDP_P11

VDDIO_A11
VDDIO_F11
VDDIO_K12
VDDIO_L12

CSTSCHG
CLKRUN
NC_H10
NC_J4
NC_K4
NC_J11
NC_K11
NC_L7
NC_L8

BCM5705M_FBGA196~D1@

2

2

C335

C328

1

0.1U_0402_16V4Z~D

BCM5705M

OR
BCM4401

2

0.1U_0402_16V4Z~D

2

C283

1

2

2

C320

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9

VSS_E2

VSS_E5

VSS_E6

VSS_E7

VSS_E8

VSS_E9

VSS_F5

VSS_F6

VSS_F7

VSS_F8

VSS_F9

VSS_F10

VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9

VSS_G10

VSS_H9

VSS_K2

VSS_L6

VSS_L9
VSS_M6

VSS_M12
VSS_M13

VSS_N1

VSS_N12
VSS_N13

AVDDL_F12
AVDDL_F13

AVDD_F14
AVDD_A13

NC_L11

NC_L14

NC_M8
NC_M9

LOW_POWER

NC_N8
NC_N9
NC_P9

2@ BCM4401

C313

1

Beijing 5705MNimitz 4401

Depop Depop

@

1@

Depop

2@

Pop

DepopPop

R311(1.24K_1%)R311(1.27K_1%)

L32(H5015T)L32(H1238)

2

2

C274

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

LAN_EECLK_SPROM_CLK

LAN_EEDATA_SPROM_CS

B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13

AVDD1P2

F12
F13

AVDD2P5

F14
A13

L11
L14
M8
M9

5705M_LOWPWR

M11
N8
N9
P9

Title

Size Doc ument Number Re v

Date: Sheet

2

2

C326

0.1U_0402_16V4Z~D

LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS

LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_SPROM_DOUT
LAN_S PROM_DIN

R313 0_0402_5%~D 2@

R308 0_0402_5%~D2@

C307

C314

1

1

0.1U_0402_16V4Z~D

R302

10K_0402_5%~D1@

2

C20

C273

1

1U_0805_10V6K~D

0.1U_0402_16V4Z~D1@

R300 0_0603_5%~D1@

1 2

1 2
1 2

0.1U_0402_16V4Z~D

R299 is poped for 4401 with AT93C86 (16KB)
R299 is poped for 5705M EEPROM 376KHz mode
R299 is depop for 4401 with AT93C46 (1KB)

12

2

1

Compal Electronics, Inc.

LA-1711

Wednesday, July 23, 2003

2

1

No pullup for 16KB

Pullup for 16KB

R299

2

2

C309

C318

C306

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

V_3P3_LAN

12

12

R296

1K_0402_5%~D 1@

4.7K_0402_5%~D1@

U34

1

CS

VCC

2

SK

NC

3

DI

ORG

4

DO

GND

AT93C46-10SI-2.7_SO8~D2@

POP
4401

L36

BLM11A601S_0603~D

1 2

1 2

L6

1@

BLM11A601S_0603~D

Place within 100 mils of ASIC
pins, 10-20mils trace width

LAN_SPROM_DOUT
LAN_S PROM_DIN

ETHERNET

1

V_1P2_LAN

2

2

C285

C293

1

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

5705M4401Signal

Pullup for 376KHz mode

No pullup

1

C277

2

0.1U_0402_16V4Z~D1@

POP
5705

U33

8

VCC

7

WP

6

SCL

5

SDA

AT24C256N-10SC_SO81@

8
7
6
5

V_1P2_LAN

V_2P5_LAN

LAN_LOW_PWR <34>

28 60

A0
A1

NC

GND

V_3P3_LAN

12

1

2

of

1
2
3
4

2

1

10K_0402_5%~D2@

R312

0.01U_0402_16V7K~D 2@

C311

X02-D

5

V_2P5_LAN

Magnetics pop options
4401: H1238
5705M: H5015D

D D

LAN_TX3-<28>

LAN_TX3-

2

C16

0.01U_0402_16V7K~D

1@

1

L32

1

1:1

2

4

Z2805

24

NB_LAN_TX3-

23

3

V_2P5_LAN

R20 49.9_0402_1%~D

1 2

R19 49.9_0402_1%~D

1 2

R22 49.9_0402_1%~D

1 2

R21 49.9_0402_1%~D

1 2
1 2
1 2
1 2
1 2

1
2

5

JST_SM05B-SRSS-TB~D

1@

JPH_RJ

1
2

6

6

7

7

5

R24 49.9_0402_1%~D
R23 49.9_0402_1%~D1@
R26 49.9_0402_1%~D1@
R25 49.9_0402_1%~D1@

RJ_RING
RJ_TIP

LAN_TX0­LAN_TX0+
LAN_RX1­LAN_RX1+
LAN_TX2­LAN_TX2+
LAN_TX3­LAN_TX3+

2

B2

NB_LAN_TX+
NB_LAN_TX­NB_LAN_RX+
NB_LAN_TX2+
NB_LAN_TX2­NB_LAN_RX­NB_LAN_TX3+
NB_LAN_TX3-

RJ_TIP
RJ_RING

B1

A2

10

V_3P3_LAN

1

JLOM

B2

B1

YEL

GRN

A2

AMBER

1

P1_1

2

P1_2

3

P1_3

4

P1_4

5

P1_5

6

P1_6

7

P1_7

8

P1_8

SGND1
SGND2

RJ45/LED

P2_2

9

P2_1

RJ11

FOX_JM34F23-P3552-TR~D

LAN_A CTLED_YEL#

B3

LED_10_GRN#

A3

LED_100_ORG#

A1

17
18

C264

1 2

22

21

20

19

18

17

16

15

14

NB_LAN_TX3+

Z2806

NB_LAN_TX2-

NB_LAN_TX2+

Z2807

NB_LAN_RX-

NB_LAN_RX+

Z2808

NB_LAN_TX-

NB_LAN_TX+

2 7

3 6

4 5

RN6
75_1206_8P4R_5%~D

1 8

D22

Q3
2N7002_SOT23~D

1

2

1

3

12

R602
10K_0402_5%~D

2

3

BAT54A_SOT23~D

D11
RB495D_SOT23~D

3

R601
10K_0402_5%~D

1

LINK CS 21.5

V_3P3_LAN

2

LAN_ACT#<28>

13

D

WLAN _LED_ACTIVITY<32>

LINK_LED_100#<28>

LED_WLAN5_RADIOSTATE<32>

LED_WLAN24_RADIOSTATE<32>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

12

R600
10K_0402_5%~D

LINK_LED_10#<28>

RB495D_SOT23~D

R309

10K_0402_5%~D

R294

10K_0402_5%~D

2

G

S

D10

2

12

12

12

V_3P3_LAN

V_3P3_LAN

R33

10K_0402_5%~D

12

1 2

R32

150_0402_5%~D

R305

1 2

10K_0402_5%~D1@

R304

10K_0402_5%~D

1 2

R295

10K_0402_5%~D

1 2

LAN_A CTLED_YEL#

47K

2

47K

47K

2

47K

V_3P3_LAN

V_3P3_LAN

12

R297
10K_0402_5%~D

V_3P3_LAN

12

R293
10K_0402_5%~D

D12

3

1

2

1@

RB495D_SOT23~D

13

Q63

DTC144EKA_SOT23~D

13

Q62

DTC144EKA_SOT23~D

Title

Size Doc ument Number Re v

LA-1711

Date: Sheet

LINK_LED_1000# <28>

R292

200_0402_5%~D

1 2

R298

200_0402_5%~D

1 2

LED_100_ORG#

LED_10_GRN#

Compal Electronics, Inc.

LAN TRANSFOMER

1

29 60Wednesday, July 23, 2003

of

X02-D

LAN_TX3+<28>

LAN_TX2-<28>

C C

LAN_TX2+<28>

LAN_RX1-<28>

LAN_RX1+<28>

LAN_TX0-<28>

B B

LAN_TX0+<28>

LAN_TX3+

LAN_TX2-

2

C14

0.01U_0402_16V7K~D

1@

1

LAN_TX2+

LAN_RX1-

2

C13

0.01U_0402_16V7K~D

1

LAN_RX1+

LAN_TX0-

2

C15

0.01U_0402_16V7K~D

1

LAN_TX0+

DTC144EKA

1

C

23

3

T1

4

1:1

5

6

T5

T2 T6

7

1:1

8

9

T3 T7

10

1:1

11

12 13

T4 T8

H5015D~D1@

2@ H1238

EB

1000P_1808_3KV7K~D

A A

@

Depop Depop

1@

Depop

2@

Bejing 5705MNimitz 4401

GND

Pop

DepopPop

5

CHASIS

4

5

PCI_AD [0..31]<20,28,32>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21

D D

PCI_C_BE3#<20,28,32>
PCI_C_BE2#<20,28,32>
PCI_C_BE1#<20,28,32>
PCI_C_BE0#<20,28,32>

C C

CK_33M_CBPCI<6>

B B

A A

PCI_AD17

PCI_PAR<20,28,32>

PCI_DEVSEL#<20,28,32>
PCI_FRAME#<20,28,32>

PCI_GNT1#<20>

PCI_IRDY#<20,28,32>
PCI_PERR#<20,28,32>
PCI_R EQ1#<20>
PCI_SERR#<20,28,32>

PCI_STOP#<20,28,32>

PCI_TRDY#<20,28,32>

PCIRST_CB#<20>

CBS_GRST#<33>

1 2

R481 10K_0402_5%~D @

R470 100_0402_5%~D

1 2

@

1 2

CK33M_CBS_TERM

2

1

R163
10_0402_5%~D

C139

4.7P_0402_50V8C~D @

PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#

PCI_PAR

PCI_DEVSEL#
PCI_FRAME#
PCI_GNT1#

PCI_IRDY#
PCI_PERR#
PCI_R EQ1#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCIRST_CB#

CBS_GRST# IRQ_SERIRQ

CBS_IDSEL

+3VSUS

U9A

J5

AD31

J6

AD30

K2

AD29

K3

AD28

K5

AD27

K6

AD26

L2

AD25

L3

AD24

M2

AD23

M3

AD22

M6

AD21

M5

AD20

N2

AD19

N3

AD18

N6

AD17

P1

AD16

R6

AD15

P7

AD14

V5

AD13

U6

AD12

V6

AD11

R7

AD10

P8

AD9

U7

AD8

W7

AD7

R8

AD6

U8

AD5

V8

AD4

W9

AD3

V9

AD2

U9

AD1

R9

AD0

L6

C/BE3

P2

C/BE2

U5

C/BE1

V7

C/BE0

W4

PAR

R2

DEVSEL

N5

FRAME

J1

GNT

P3

IRDY

R3

PERR

J2

REQ

T1

SERR

P5

STOP

P6

TRDY

H3

PCIRST

H2

GRST

L5

IDSEL

H1

PCICLK

2@ PCI4510

+3VSUS

BLM21A601SPT_0805~D

1 2

2

C160

1

0.047U_0402_10V4M~D

BLM21A601SPT_0805~D

1 2

1

C562

2

0.1U_0402_16V4Z~D

PCI75 10GHK_PBGA209~D1@

L15

L13

C164

10U_0805_10V4M~D

C532

0.1U_0402_16V4Z~D

PCI7510

2

C536

1

1

C173

2

0.047U_0402_10V4M~D

10U_0805_10V4M~D

1

2

1

2

4

CAD31/D10

CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6

CAD19/A25

CAD18/A7
CAD17/A24
CAD16/A17

CAD15/IOWR#

CAD14/A9

CAD13/IORD#

CAD12/A11

CAD11/OE#

CAD10/CE2#

CAD9/A10

CAD8/D15

CAD7/D7

CAD6/D13

CAD5/D6

CAD4/D12

CAD3/D5

CAD2/D11

CAD1/D4
CAD0/D3

CC/BE3/REG#

CC/BE2/A12

CC/BE1/A8

CC/BE0/CE1#

CRST/RESET
CFRAME/A23

CIRDY/A15

CTRDY/A22

CDEVSEL/A21

CSTOP/A20

CPERR/A14

CSERR/WAIT#

CPAR/A13

CREQ/INPACK#

CGNT/WE#

CCLK/A16

CSTSCHG/BVD1

CCLKRUN/WP

CBLOCK/A19
CINT/READY

CAUDIO/BVD2

CCD2/CD2#
CCD1/CD1#

CVS2/VS2#
CVS1/VS1#

CRSVD/D2
CRSVD/A18
CRSVD/D14

2

C542

1

0.047U_0402_10V4M~D

1

C172

2

10U_0805_10V4M~D

+3V_CBSA

2

C544

1

0.047U_0402_10V4M~D

1

C521

2

0.047U_0402_10V4M~D

E8
C8
B8
E9
F9
F11
E11
C11
A12
C12
E12
C13
A14
E13
B14
F18
G17
F19
G18
H15
H14
H17
H18
J14
J17
K14
J19
K17
K15
L14
K18
L15

B11
C14
G15
J15

B13
B15
F13
E14
A16
E17
F15
E10
F14
B12
D19

CBS_C CLK_INTERNAL

C15

A9
B9

E18
C10

CBS_CAUDIO

F10

CBS_C CD2#_INTERNAL

C9

CBS_C CD1#_INTERNAL

L17

F12
B10

CBS_R SVD/D2

F8

CBS_R SVD/A18

F17

CBS_R SVD/D14

J18

1

C522

2

0.047U_0402_10V4M~D

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CBS_C C/BE3#
CBS_C C/BE2#
CBS_C C/BE1#
CBS_C C/BE0#

CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#

CBS_CSTSCHNG
CBS_C CLKRUN#

CBS_CBLOCK#
CBS_CINT#

CBS_CVS2
CBS_CVS1

1

C524

C533

2

0.047U_0402_10V4M~D

1

C556

2

0.047U_0402_10V4M~D

CBS_CAD[0..31] <31>

+3V_CBSD

R177

R191

1 2

0_0402_5%~D

@

@

R186

R188

1 2

0_0402_5%~D

CBS_C C/BE3# <31>
CBS_C C/BE2# <31>
CBS_C C/BE1# <31>
CBS_C C/BE0# <31>

CBS_CRST# <31>
CBS_CFRAME# <31>
CBS_CIRDY# <31>
CBS_C TRDY# <31>
CBS_CDEVSEL# <31>
CBS_CSTOP# <31>
CBS_C PERR# <31>
CBS_C SERR# <31>
CBS_CPAR <31>
CBS_CREQ# <31>
CBS_CGNT# <31>

CBS_C STSCHNG <31>

CBS_CBLOCK# <31>
CBS_CINT# <31>

CBS_CAUDIO <31>

CBS_CVS2 <31>
CBS_CVS1 <31>

CBS_R SVD/D2 <31>
CBS_R SVD/A18 <31>
CBS_R SVD/D14 <31>

1

2

0.047U_0402_10V4M~D

12

47_0402_5%~D

+3V_CBSD

1

C543

2

0.047U_0402_10V4M~D

0_0402_5%~D

0_0402_5%~D

R494

3

2

1

Remove R756

8/12 Changed by

R483

1K_0402_5%~D

R510

1 2

12

12

R502

12

1K_0402_5%~D

R486

12

1K_0402_5%~D

R515

12

1K_0402_5%~D@

12

Dell's Require

PHY_CPS

12

PHY_CNA

CBS_PC0
CBS_PC1
CBS_PC2

PCI4510_R0

PCI4510_R1

IEEE1394_TPA0P

IEEE1394_TPA0N

IEEE1394_TPA1P

IEEE1394_TPA1N

IEEE1394_TPB0P

IEEE1394_TPB0N

IEEE1394_TPB1P

IEEE1394_TPB1N

IEEE1394_TPBIAS0

IEEE1394_TPBIAS1

+3V_CBSA

+3V_CBSA

FILTER0
FILTER1

SCR_IF_GPIO5

SCR_IF_GPIO4
SCR_IF_GPIO3
SCR_IF_GPIO2

SCR_DETECT
SCR_I F_RST
SCR_IF_CLK
SCR_I F_DATA
SCR_IF_PWR
SCR_IF_GPIO0
SCR_IF_GPIO1

U9B

P10

CPS

P17

CNA

V10

PC0

W10

PC1

P9

PC2

PCI7510

W13

R0

V13

R1

V12

TPA0P

W12

TPA0N

V15

TPA1P

W15

TPA1N

V11

TPB0P

W11

TPB0N

V14

TPB1P

W14

TPB1N

U12

TPBIAS0

U15

TPBIAS1

R11

ANALOGVCC

U13

ANALOGVCC

U14

ANALOGVCC

U11

ANALOGGND

R12

ANALOGGND

R13

ANALOGGND

P15

VDPLL

N14

VSPLL/RSVD

T19

FILTER0

R17

FILTER1

N15

RSVD

M14

RSVD

N17

RSVD

N18

RSVD

N19

SC_GPIO5

M15

RSVD

M17

SC_GPIO6

M18

SC_GPIO1

M19

SC_GPIO0

B7

SC_CD

C7

SC_RST

F7

SC_CLK

A6

SC_DATA

B6

SC_GPIO3

E7

SC_GPIO2

C6

SC_GPIO4

PCI75 10GHK_PBGA209~D 1@

2@ PCI4510

+1.8V_CBSD

1

1

C560

0.1U_0402_16V4Z~D

C520

2

2

0.1U_0402_16V4Z~D

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCCB
VCCCB

VCCP
VCCP

VR_PORT
VR_PORT

VD1/VCCD0
VD0/VCCD1

VD3/VPPD0
VD2/VPPD1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VR_EN

SUSPEND

RI_OUT/PME

SPKROUT

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

SCL
SDA

PHY_TEST_MA

SKT_SEL0

SKT_SEL1

CLK_48

XI

XO

8/12 Changed by
Dell's Require

R444

220_0402_5%~D

R165

220_0402_5%~D

+3V_CBSA

R495

1M_0603_5%~D@

1 2

1 2

R487

6.34K_0603_1%~D

IEEE1394_TPA0P<31>

R507

1K_0402_5%~D @

R496

@

1K_0402_5%~D

IEEE1394_TPB0P<31>

IEEE1394_TPB0N<31>

C167

1U_0805_10V6K~D

CBS_CCLK <31>

CBS_C CD1# <31>
CBS_C CD2# <31>CBS_C CLKRUN# <31>

C557

0.1U_0402_10V6K~D

1 2

SCR_IF_GPIO5<31>

SCR_IF_GPIO4<31>
SCR_IF_GPIO3<31>
SCR_IF_GPIO2<31>

SCR_DETECT<31>
SCR_I F_RST<31>
SCR_IF_CLK<31>

SCR_I F_DATA<31>

SCR_IF_PWR<31>

SCR_IF_GPIO0<31>
SCR_IF_GPIO1<31>

10K_0402_5%~D

R174

1 2

1 2

0_0402_5%~D

@

R171

1 2

1 2

0_0402_5%~D

IEEE1394_TPA0N<31>

IEEE1394_TPBIAS0<31>

CBS_CCLK

R482

R516

0_0402_5%~D

270P_0603_50V7K~D@

C566

0_0402_5%~D

1 2

1 2

2

2

270P_0603_50V7K~D

C540

1

1

@

+3V_CBSD

G1
M1
R1
W8
L19
H19
E19
A13
A8
A5

G14
A11

L1
W5

G2
L18

This shall be output

E6
B5

A4
C5

E1
K1
N1
W6
P19
K19
G19
A15
A10
A7

1V8_VR_EN#

H5

TI_SU SPEND#_INTERNAL

G3

SYS_PME#

J3

CBS_SPK

E2

PCI_PIRQD#

F5

PCI_PIRQC#

G6

PCI_R EQB#

F3
F2

CBS_RI#

G5

PCI_GNTB#

F1

CBS_MFUNC6

H6

CBS_SCL

E3

CBS_SDA

D1

PHY_TEST_MA

P18

CBS_TEST0

U10

CBS_TEST1

R10

CK_48M_SCR

F6

PCI4510XI

R18

PCI4510XO

R19

24.576MHz_16P_1BG24576CKIA~D

1

C184

2

22P_0402_50V8J~D

2.7K_0603_5%~D@

CBS_SCL

12

CBS_SDA

12

2.7K_0603_5%~D@

+1.8V_CBSD

CBS_VCCD0# <31>
CBS_VCCD1# <31>

CBS_VPPD0 <31>
CBS_VPPD1 <31>

CBS_SPK <24>

PCI_R EQB# <20>
IRQ_SE RIRQ <20,21,33>
CBS_RI# <21>
PCI_GNTB# <20>

R504 4.7K_0402_5%~D

R450 200_0402_5%~D

R447 200_0402_5%~D

X3

1 2

C185

+3V_CBSD

R445

12
12

R164

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R452

10K_0402_5%~D@

12

R451

0_0402_5%~D

12

R446

10K_0402_5%~D

12

2 1

D15

RB751V_SOD323~D

SYS_PME# <28,32,33>

PCI_P IRQD# <20,32>
PCI_P IRQC# <20,28>

1 2

R455 10K_0402_5%~D

12

12

12

R453
10_0402_5%~D

@

1 2

1

CK48M_CBS_TERM

2

2

22P_0402_50V8J~D

@

1

CBS_VCC

0.1U_0402_16V4Z~D

C541

1

1

2

2

+3V_CBSD

0.1U_0402_16V4Z~D

C531

C555

2

2

1

1

+3V_CBSD

+3V_CBSD

TI_SUSPEND# <34>

+3V_CBSD

+3V_CBSD

CK_48M_SCR <6>

C523

4.7P_0402_50V8C~D

C538

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

PCMCIA Controller

LA-1711

1

30 60Wednesday, July 23, 2003

X02-D

of

5

Beijing PCI7510Nimitz PCI4510

Depop Depop

@

1@

Depop

2@

D D

SCR_DETECT<30>

C C

SCR_IF_GPIO2<30>
SCR_IF_GPIO3<30>
SCR_IF_GPIO0<30>

SCR_IF_PWR<30>

SCR_IF_GPIO1<30>

SCR_IF_GPIO5<30>

SCR_I F_RST<30>
SCR_I F_DATA<30>
SCR_IF_GPIO4<30>

SCR_IF_CLK<30>

+3VSUS

1

C174

B B

1

2

2

10U_1206_6.3V7K~D 1@

T3
PAD

@

T4
PAD

@

C182

0.1U_0402_16V4Z~D1@

Pop

DepopPop

NC_SCR_C4

NC_SCR_C8

SCR_DETECT

SCR_IF_GPIO2
SCR_IF_GPIO3
SCR_IF_GPIO0
SCR_IF_PWR
SCR_IF_GPIO1
SCR_IF_GPIO5
SCR_I F_RST
SCR_I F_DATA
SCR_IF_GPIO4
SCR_IF_CLK

1
2
3
4
5
6
7
8
9

10

12

R173
10K_0402_5%~D

U17

A0
A1
PGM#
PWR_ON
STATUS
CS#
RESET#
I/O
INT#
CLOCK_IN

NCN6000_TSSOP20~D1@

R172

R194
0_0402_5%~D @

R193
0_0402_5%~D @

12

12

12

0_0402_5%~D2@

R170

10K_0402_5%~D1@

SCR_C4_C

SCR_C8_C

SCR_DETECT_C

C175

LOUT_H

LOUT_L

PWR_GND

GROUND

CRD_VCC

CRD_IO
CRD_CLK
CRD_RST
CRD_DET

SCR_VCC_C

12

C150

1

2

0.1U_0402_16V4Z~D 1@

VBAT

1

2

4.7U_1206_16V6K~D

1@

Place near connectorPlace near NCN6000

TPS2211VCC

U10

9

+12V

1

C144

0.1U_0402_16V4Z~D

2

+5VSUS

A A

+3VSUS

1

C156

0.1U_0402_16V4Z~D

2

1

C155

0.1U_0402_16V4Z~D

2

12V

5

5V_1

6

5V_2

3

3.3V_1

4

3.3V_2

GND

7

5

13

AVCC1

12

AVCC2

11

AVCC3

10

AVPP

1

VCCD0#

2

VCCD1#

15

VPPD0

14

VPPD1

8

OC#

SHDN#

TPS2211ADBR_SSOP16~D

16

CBS_V CCD0#
CBS_V CCD1#
CBS_VPPD0
CBS_VPPD1

1

2

1

C145

2

4.7U_1206_16V6K~D

SUSPWROK_5V <39,43,45>

4

Depop if support Smart Card

SCR_VCC_C

Place near ncn6000

+3VSUS

20

LOUT_H

19

LOUT_L

18
17
16
15
14
13
12
11

1

C149

2

0.1U_0402_16V4Z~D 1@

L10

BLM31A260SPT_1206~D

1 2

C143

4.7U_1206_16V6K~D

1

C142

2

0.1U_0402_16V4Z~D

CBS_V CCD0# <30>
CBS_V CCD1# <30>
CBS_VPPD0 <30>
CBS_VPPD1 <30>

4

+3VSUS

L14

22U_LQH43MN220J01K_2OHM_1812~D1@

1 2

SCR_VCC_C
SCR_DATA_C
SCR_C LK_C
SCR_RST_C
SCR_DETECT_C

SCR_RST_C SCR_ CLK_C

1

C151

C137

12

2

R187

22K_0402_5%1@

470P_0402_50V7K~D 1@

1

1

C135

2

2

0.1U_0402_16V4Z~D

10U_1206_6.3V7K~D

3

R468

10K_0402_5%~D

R464

10K_0402_5%~D

R202

10K_0402_5%~D

R203

10K_0402_5%~D

R201

10K_0402_5%~D

R200

10K_0402_5%~D

R461

10K_0402_5%~D

IEEE1394_TPBIAS0<30>

IEEE1394_TPA0P<30>
IEEE1394_TPA0N<30>
IEEE1394_TPB0P<30>
IEEE1394_TPB0N<30>

1

12

C154

2

R189

22K_0402_5%1@

56P_0402_50V8J~D 1@

CBS_VCC

1

C136

2

1000P_0402_50V7K~D

CBS_VPP

AVPP:150mA

AVCC:1A

SCR_IF_GPIO0

12

SCR_IF_GPIO1

12

SCR_IF_GPIO2

12

SCR_IF_GPIO3

12

SCR_IF_GPIO4

12

SCR_IF_GPIO5

12

SCR_IF_PWR

12

12

R480

56.2_0603_1%~D

R460

1 2

56.2_0603_1%~D

2

C528

1

270P_0603_50V7K~D

SHDN#

1

1

1

1

0

SHDN#

1

1

1

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

Z3008

VPPD1

VCCD1#

12

2

C163

R469

56.2_0603_1%~D

R456

56.2_0603_1%~D

R448

5.1K_0603_1%~D

IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPB0P
IEEE1394_TPB0N

1 2

1 2

1

1U_0805_10V6K~D

VPPD0

0

0

0

1

1

0

1

1

X

X

VCCD0#

0

0

0

1

0

1

1

1

X0

X

100P_0402_50V8J~D1@

CBS_VPP

CBS_VCC

+5VSUS

C656

1 2

R185

0_0402_5%~D@

1 2

CBS_VPP
CBS_VCC

R204

0_0603_5%~D

1 2

2

CBS_C CD2# CBS_CCL KRUN#
CBS_CAD31
CBS_CAD30
CBS_CAD28
CBS_CSTSCHNG

CBS_CAUDIO
CBS_C C/BE3#
CBS_CREQ#
CBS_CSERR# CBS_CAD22

CBS_CRST#
CBS_CVS2
SCR_V PP_PIN66
CBS_CAD19
CBS_CAD17
SCR_DATA_C
CBS_CFRAME#
CBS_CTRDY#
SCR_C8_C

CBS_CDEVSEL#
CBS_CSTOP#
CBS_CBLOCK#
CBS_R SVD/A18
CBS_CAD16
CBS_CAD15
CBS_CAD13
CAGE50_GND
CBS_CVS1
CBS_CAD10
CBS_CAD8
CBS_R SVD/D14
CBS_CAD6
CBS_CAD4
CBS_CAD2
CBS_C CD1#

L7

5

6
7

8

857CM-0009~D@

CBS_CCLK
CBS_C C/BE3#
CBS_C C/BE2#
CBS_C C/BE1#
CBS_C C/BE0#

CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#

CBS_CGNT#
CBS_CSTSCHNG
CBS_C CLKRUN#
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CVS2
CBS_CVS1

CBS_R SVD/D14
CBS_R SVD/D2

CBS_R SVD/A18

CBS_C CD1#

CBS_C CD2#

2

CBS_CCLK <30>
CBS_C C/BE3# <30>
CBS_C C/BE2# <30>
CBS_C C/BE1# <30>
CBS_C C/BE0# <30>

CBS_CRST# <30>
CBS_CFRAME# <30>
CBS _CIRDY# <30>
CBS_C TRDY# <30>
CBS_CDEVSEL# <30>
CBS_CSTOP# <30>
CBS_CPERR# <30>
CBS_CSERR# <30>
CBS_CPAR <30>
CBS_CREQ# <30>

CBS_CGNT# <30>
CBS_CSTSCHNG <30>
CBS_C CLKRUN# <30>
CBS_CBLOCK# <30>
CBS_CINT# <30>
CBS_C AUDIO <30>
CBS_CVS2 <30>
CBS_CVS1 <30>

CBS_R SVD/D14 <30>
CBS_R SVD/D2 <30>
CBS_R SVD/A18 <30>

CBS_C CD1# <30>

CBS_C CD2# <30>

JCBUS

40

80

40

80

39

79

39

79

38

78

38

78

37

77

37

77

36

76

36

76

35

75

35

75

34

74

34

74

33

73

33

73

32

72

32

72

31

71

31

71

30

70

30

70

29

69

29

69

28

68

28

68

27

67

27

67

26

66

26

66

25

65

25

65

24

64

24

64

23

63

23

63

22

62

22

62

21

61

21

61

20

60

20

60

19

59

19

59

18

58

18

58

17

57

17

57

16

56

16

56

15

55

15

55

14

54

14

54

13

53

13

53

12

52

12

52

11

51

11

51

10

50

10

50

9

49

9

49

8

48

8

48

7

47

7

47

6

46

6

46

5

45

5

45

4

44

4

44

3

43

3

43

2

42

2

42

1

41

1

41

82

G81G

84

G83G

86

858586

FOX_QT8R080A-1910_LB~D

4

4

5

3

3

6
7

8

R144

0_0402_5%~D

1 2

R145

0_0402_5%~D

1 2

R146

0_0402_5%~D

1 2

R147

0_0402_5%~D

1 2

2

2

1

1

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

LA-1711

1

CBS_R SVD/D2
CBS_CAD29
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
SCR_DETECT_C
CBS_CAD23

SCR_VCC_C
CBS_CAD21
CBS_CAD20
SCR_RST_C
CBS_CAD18
CBS_C C/BE2#
SCR_C LK_C
CBS_CIRDY#
CBS_CCLK
SCR_C4_C

CBS_CINT#
CBS_CGNT#
CBS_CPERR#
CBS_CPAR
CBS_C C/BE1#
CBS_CAD14
CBS_CAD12
CAGE10_GND
CBS_CAD11
CBS_CAD9
CBS_C C/BE0#
CBS_CAD7
CBS_CAD5
CBS_CAD3
CBS_CAD1
CBS_CAD0

TPA0+
TPA0­TPB0+
TPB0-

CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0

CardBus Socket

1

SCR_DETECT_C <34>

CBS_VPP
CBS_VCC

R205

@

0_0603_5%~D

1 2

J1394

8

SGND4

7

SGND3

6

SGND2

5

SGND1

4

4

3

3

2

2

1

1

MOLEX_54515-0411~D

CBS_C AD[0..31] <30>

31 60Monday, August 11, 2003

of

X02-D

5

PCI_AD [0..31]<20,28,30>

D D

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

COEX2_WLAN_ACTIVE<27>

CK_33 M_MINIPCI

R248
10_0402_5%~D @

1 2

C C

CK_33M_MINPCI_TERM

2

C230

4.7P_0402_50V8C~D

@

1

PCI_CLKRUN#

12

R264

B B

10K_0402_5%~D

4

3

2

1

+3VRUN+3VRUN

JPCI

1

TIP

3

8PMJ-3

5

8PMJ-6

7

8PMJ-7

9

8PMJ-8

11

LED1_GRNP

13

LED1_GRNN

15

CHSGND

17

INTB#

19

3.3V

21

RESERVED

23

GROUND

25

CLK

27

GROUND

29

REQ#

31

3.3V

33

AD31

35

AD29

37

GROUND

39

AD27

41

AD25

43

RESERVED

45

C/BE3#

47

AD23

49

GROUND

51

AD21

53

AD19

55

GROUND

57

AD17

59

C/BE2#

61

IRDY#

63

3.3V

65

CLKRUN#

67

SERR#

69

GROUND

71

PERR#

73

C/BE1#

75

AD14

77

GROUND

79

AD12

81

AD10

83

GROUND

85

AD8

87

AD7

89

3.3V

91

AD5

93

RESERVED

95

AD3

97

5V

99

AD1

101

GROUND

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND

115

SYS_AUDIO_OUT

117

SYS_AUDIO_OUT GND

119

AUDIO_GND

121

RESERVED

123

VCC5A

AMP_1318644-1~D

AC_SDATA_OUT

AC_CODEC_ID0#

SYS_AUDIO_IN

SYS_AUDIO_IN GND

R255

0_0402_5%~D@

1 2

WLAN _LED_ACTIVITY
HW_RADIO_DIS#

PCI_PIRQD#

CK_33 M_MINIPCI

PCI_R EQ3#

PCI_AD31
PCI_AD29

PCI_AD27
PCI_AD25

PCI_C_BE3#
PCI_AD23

PCI_AD21
PCI_AD19

PCI_AD17
PCI_C_BE2#
PCI_IRDY#

PCI_CLKRUN#
PCI_SERR# PCI_STOP#

PCI_PERR#
PCI_C_BE1#
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

WLAN _LED_ACTIVITY<29>

HW_RADIO_DIS#<27,34>

PCI_PIRQD#<20,30>

CK_33 M_MINIPCI<6>

PCI_R EQ3#<20>

PCI_C_BE3#<20,28,30>

PCI_C_BE2#<20,28,30>

PCI_IRDY#<20,28,30>

PCI_SERR#<20,28,30>

PCI_PERR#<20,28,30>

PCI_C_BE1#<20,28,30>

PCI_AD5

+5VRUN

PCI_AD3

PCI_AD1

+5VRUN

2

C249

0.1U_0402_16V4Z~D

1

RING

8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5

LED2_YELP

LED2_YELN

RESERVED

INTA#

RESERVED

3.3VAUX
RST#

3.3V

GNT#

GROUND

PME#

RESERVED

AD30

3.3V
AD28
AD26
AD24

IDSEL

GROUND

AD22
AD20

PAR
AD18
AD16

GROUND

FRAME#

TRDY#
STOP#

3.3V

DEVSEL#

GROUND

AD15
AD13
AD11

GROUND

AD9

C/BE0#

3.3V

AD6

AD4

AD2

AD0

RESERVED
RESERVED

GROUND

M66EN

AC_RESET#

RESERVED

GROUND

AUDIO_GND

MCPIACT#

3.3VAUX

2

4
6
8
10
12
14
16
18

5V

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

LED_WLAN24_RADIOSTATE
LED_WLAN5_RADIOSTATE

R250

0_0402_5%~D@

MPCI_M66EN

MPCIACT#

PCI_PIRQB#

PCIRST_2#

PCI_GNT3#

SYS_PME#

1 2

PCI_AD30

PCI_AD28
PCI_AD26
PCI_AD24
MINIDSEL

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#

PCI_DEVSEL#

PCI_AD15
PCI_AD13
PCI_AD11

PCI_AD9
PCI_C_BE0#

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
LAN_SMBCLK
LAN_SMBDATA

V_3P3_LAN

2

C229

0.1U_0402_16V4Z~D

1

LED_WLAN24_RADIOSTATE <29>
LED_WLAN5_RADIOSTATE <29>

PCI_P IRQB# <18,20>

PCIRST_2# <20>

PCI_GNT3# <20>

SYS_PME# <28,30,33>

1 2

100_0402_5%~D

PCI_PAR <20,28,30>

PCI_FRAME# <20,28,30>
PCI_T RDY# <20,28,30>
PCI_STOP# <20,28,30>

R249

10K_0402_5%~D@

R261

COEX1_BT_ACTIVE <27>

12

PCI_AD19

PCI_DEVSEL# <20,28,30>

PCI_C_BE0# <20,28,30>

R278

1K_0402_5%~D

12

R284

10K_0402_5%~D

1 2

+3VSUS

V_3P3_LAN

2

C252

0.1U_0402_16V4Z~D

1

+5VRUN

2

C253

0.1U_0402_16V4Z~D

1

V_3P3_LAN

R270
10K_0402_5%~D

D

+3VSUS

S

G

G

S

13

Q52
2N7002_SOT23~D

2

NIC_M INI_SMBDAT

1 3

2

NIC_M INI_SMBCLK LAN_SMBCLK

13

D

Q48
2N7002_SOT23~D

1 3

ICH_SMBDATA<6, 15,16,21>

ICH_SMBCLK<6, 15,16,21>

ICH_SMBDATA

ICH_SMBCLK

D

G

2

2

G

D

1 2

S

Q53
2N7002_SOT23~D

Q49
2N7002_SOT23~D

S

R268
10K_0402_5%~D

1 2

LAN_SMBDATA

LAN_SMBDATA <28>

LAN_SMBCLK <28>

+3VRUN

A A

2

C232

0.047U_0402_10V4M~D

1

2

C241

0.047U_0402_10V4M~D

1

5

2

C227

0.047U_0402_10V4M~D

1

2

C246

0.047U_0402_10V4M~D

1

2

C234

0.047U_0402_10V4M~D

1

4

2

C242

0.047U_0402_10V4M~D

1

2

C247

0.047U_0402_10V4M~D

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

C231

0.047U_0402_10V4M~D

1

2

C244

0.047U_0402_10V4M~D

1

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

MINIPCI

LA-1711

1

32 60Wednesday, July 23, 2003

X02-D

of

+3VALW

R233

D D

KSO_17<35,38>

C C

Dell GPIO rev0.7
D-Bay USB power

+3VALW

B B

+3VRUN

+3VRUN

A A

5

12

12

R465

R181

10K_0402_5%~D

10K_0402_5%~D

KSO_17

T6
PAD

@

J1397

1.5mm SMT@

1

1

2

2

3

3

T5
PAD

@

1

C549

C546

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C577

C574

1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

12

R182

10K_0402_5%~D

RB751V_SOD323~D

+3VALW

R226

1 2

10K_0402_5%~D

+3.3VRTC

1

C589

2

0.1U_0402_16V4Z~D

2

1

BLM11A121S_0603~D

1 2

12

10K_0402_5%~D

SUB_DETECT#<42,50>

D4

2 1

1

2

L12

1

C568

2

0.1U_0402_16V4Z~D

PWR SW_SIO#
ATF_INT#
SYS_PME#
DEBUG_ENABLE LPCPD#

CBS_GRST#<30>

R615

GV_HI_LO#<36>

VAUX_EN<39,43>

USB_EN#<26>

BAY_MODPRES#<23>
USB_IDE#<23>

SIO_EXT_SMI#<21>
SIO_EXT_SCI#<21>
SIO_EXT_RTE#<21>
SIO_RCIN#<21>
NB_MUTE<25>
BEEP<24>

PWR SW_SIO#<39>
SIO_SLP_S3#<21>
SYS_PME#<28,30,32>
ATF_INT#<19,47>
SIO_SLP_S4_S5#<21>

NOCREG<36>

DT/MT_SELECT<49>

SIO_PWRBTN#<21>
RUN_ON<1 8,37,39,44>
ICH_PME#<20>
SIO_THRM#<21>
SUS_ON<43>
SYS_SUSPEND<18,41>

SATA_MOD_DETECT#<23>

DH_PW RSRC_OC<26>

IDE_R ST_HDD<21>
IDE_RST_MOD<21>
GC_BL _SUSPEND<18>
DH_PO WER_EN<26>

SATA_HDD_DETECT#

MODC_EN#<39>
HDDC_EN#<39>

+3.3VRTC

C558

C548

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

2

1

2

1

R232

0_0402_5%~D

1

C572

2

0.1U_0402_16V4Z~D

2

C567

1

0.1U_0402_16V4Z~D

C152

0.1U_0402_16V4Z~D

CBS_GRST#

1 2

VAUX_EN
KSO17
USB_EN#
BAY_MODPRES#
USB_IDE#

SIO_EXT_SMI#
SIO_EXT_SCI#

SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT

PWR SW_SIO#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S4_S5#

LID_C L_SIO#

RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
SYS_SUSPEND

DH_PW RSRC_OC

IDE_R ST_HDD
IDE_RST_MOD
GC_BL_SUSPEND
DH_PO WER_EN
AC_LOW_PRES2#

MODC_EN#
HDDC_EN#

12

C581

0.1U_0402_16V4Z~D

C563

0.1U_0402_16V4Z~D

4

0_0402_5%~D

254VCC0

2

C211

0.1U_0402_10V6K~D

1

1

2

2

1

KPLLVCC

U15A

F13

SGPIO30

F14

SGPIO31

E16

SGPIO32

E15

SGPIO33

E12

SGPIO34

E13

SGPIO35

D16

SGPIO36

D15

SGPIO37

E14

SGPIO40

C16

SGPIO41

C15

SGPIO42

A16

SGPIO43

D14

SGPIO44

C14

SGPIO45

C13

SGPIO46

B14

SGPIO47

T5

LGPIO50

N6

LGPIO51

L6

LGPIO52

R6

LGPIO53

T6

LGPIO54

L7

LGPIO55

P7

LGPIO56

N7

LGPIO57

A15

LGPIO60

D13

LGPIO61

A14

LGPIO62

C12

LGPIO63

B13

LGPIO64

A13

LGPIO65

D12

LGPIO66

F11

LGPIO67

B12

LGPIO70

A12

LGPIO71

C11

LGPIO72

D11

LGPIO73

E11

LGPIO74

B11

LGPIO75

A11

LGPIO76

C10

LGPIO77

A4

VCC0/BAT

M7

VCC1_1

R13

VCC1_2

L11

VCC1_3

H10

VCC1_4

B16

VCC1_5

F10

VCC1_6

A6

VCC1_7

D3

VCC2_1

H2

VCC2_2

K6

VCC2_3

P4

VCC2_4

E1

VCC2_5

R5

VCC2_6/PLL

P6

VSS13/PLL

LPC47N254V12FBGA_LBGA256~D

8051
GPIO

LPC
GPIO

VCC

LPC47N254

MACALLEN

GPIO10/WK_SE14/IRMODE/IRRX3B

256 - LBGA

3

DOCK LPC

LPC

FDD

COM1

IR

LPT

GND

LPCPD#

LRESET#

DLDRQ1#

DLFRAME#

DLAD0
DLAD1
DLAD2
DLAD3

DSER_IRQ

DCLKRUN#

LDRQ1#

LFRAME#

LAD0
LAD1
LAD2
LAD3

SER_IRQ

CLKRUN#

WPROT#

RDATA#
HDSEL#

INDEX#

DSKCHG#

TRK0#

MTR0#

DIR#

STEP#

WDATA#

WGATE#

DS0#

FPD
DRVDEN0
DRVDEN1

RXD1

TXD1

RTS1#

CTS#
DTR#
DSR#
DCD#

RI1#

IRRX
IRTX

ACK#

SLCTIN#

INIT#

ALF#

STROBE#

BUSY

SLCT

ERROR#

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10
VSS11
VSS12

AGND

2

+3VRUN

RN5
10K_8P4R_1206_5%~D

12

R195
100K_0402_5%~D

+3VRUN

+3VALW

+3VRUN

D_CLKRUN#

D_SERIRQSIO_EXT_RTE#

+3VRUN

LID_C L_SIO#

TXD0

+3VALW

12

1

2

A3Y

R466
100K_0402_5%~D

10_0402_5%~D

C534

0.047U_0402_10V4M~D

LPC_LAD[0..3] <21>

1 2

1 2

1 2
1 2

1 2

D_IRMODE <38>
IRRX <38>
IRTX <38>

10K_0402_5%~D

1 2
1 2
1 2
1 2

+3VRUN

IRQ_SE RIRQ <20,21,30>

1 8
2 7
3 6
4 5

1 2

R520

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D
10K_0402_5%~D

10K_0402_5%~D

+3VRUN

10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D

R523

H4
H3

R2
T2

N2
P1
P2
N3
R4
T3

R3
N4

M3
R1
T1
P3
T4
P5

L3
M1
L2
L5
M2
L4
K1
K2
K4
K3
L1
K5
M5
J7
K7

G5
G2
H7
H8
H6
G1
H5

B10

H15
K14
M4

C1
F2
F1
G3
G4
D4
B1

PE

B2
G6
F4

PD0

F3

PD1

E2

PD2

F5

PD3

E4

PD4

D1

PD5

D2

PD6

E3

PD7

C2
F6
J5
N1
N5
T10
R15
J11
G11
B15
H9
D6

A2

PCIRS T_SIO#

D_DLRQ1#

D_SERIRQ
D_CLKRUN#

LPC_LDRQ1#
LPC_LFRAME#

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
IRQ_SERIRQ
EC_CL KRUN#

WRPRT#
RDATA#

INDEX#
DISKCHG#
TRK0#

RXD0
TXD0

CTS0#

DSR0#
DCD0#

RI0#

D_IRMODE
IRRX
IRTX

ACK#

BUSY
PE
SLCT
ERROR#

KAGND

1 2

BLM11A121S_0603~D

4.7K_0402_5%~D

1 2

PCIRS T_SIO# <20>

LPC_LDRQ1# <21>
LPC_LFRAME# <21>

1 2

R196 10K_0402_5%~D

R532

R537

R211
R527

R227

R217

1 2

R231
R220
R222
R535

L22

12

R183
100K_0402_5%~D

+5VSUS

8

U42C

P

5

G

TC7W14FU_SSOP8~D

4

R467

12

1

LID_CL#

+3VRUN

12

R184
100K_0402_5%~D

T11

PAD

@

LID_CL# <18>

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

SIO (1/2)

LA-1711

1

33 60Wednesday, July 23, 2003

X02-D

of

5

4

3

2

1

+3VALW +3VALW

12

R229

D D

DH_MOD_PRES#<26>

ACAV<39,48>

+3VALW

R213

C C

+5VRUN

R506

1 2

4.7K_0402_5%~D

DAT_KBD

CLK_KBD

CLK_SM1

DAT_SM1

B B

A A

10K_0402_5%~D

D23 RB751V_SOD323~D

1 2

4.7K_0402_5%~D

12

R514

R225

1 2

4.7K_0402_5%~D

4.7K_0402_5%~D

PBAT_ALARM#

R224

4.7K_0402_5%~D

12

R606
100K_0402_5%~D

DOCKED

DOCK_SMB_INT#

SIO_THERM_PWRDN<37>

H_PRO CHOT_SIO#<10>

SCR_DETECT_C<31>

KSO16<35>
CAP_LED#<38>
NUM_LED#<38>
SRL_LED#<38>

VCORE_PHOT#<10,46>

KSO[0..15]<35>

KSI[0..7 ]<35,38>

22P_0402_50V8J~D

22P_0402_50V8J~D

PBAT_PRES#<42>

FPVCC<18>

SBAT_PRES#

NB_PSID<41>

C592

1 2

C593

1 2

T10
PAD@

T9
PAD@

21

CLK_SM2<35>
DAT_SM2<35>

PBAT_ALARM#<42>

12

12

FPVCC

SBAT_ALARM#

PBAT_PRES#

SIO_THERM_PWRDN
H_PRO CHOT_SIO#
SCR_DETECT_C

KSO16
CAP_LED#
NUM_LED#
SRL_LED#

SIO_MSCLK
SIO_MSDAT

CLK_SM1
DAT_SM1

CLK_SM2
DAT_SM2

CLK_KBD
DAT_KBD

PBAT_ALARM#

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1 SIO_FA17
KSI0

CLK_32KX2

X5

32.768 KHZ_12.5P_MC-306~D

3.8X12.1mm

CLK_32KX1

U15B

B9

IN0/WK_EE4

B8

IN1/WK_EE2

A8

IN2/WK_EE3

C8

IN3/GPWKUP

D8

IN4/WK_SE00

E8

IN5/WK_SE01

F8

IN6/WK_SE05

G8

IN7/WK_EE1

H13

GPIO0/WK_SE02

H12

GPIO1/WK_SE03

H11

GPIO2/WK_SE04

G10

GPIO3/TRIGGER

G13

GPIO7/WK_SE06

J14

GPIO8/WK_SE12/IRRX2

J16

GPIO9/WK_SE13/IRTX2

G14

GPIO17/WK_SE23/A20M

F15

GPIO20/WK_SE25/PS2CLK/8051RX

F12

GPIO21/WK_SE26/PS2DAT/8051TX

GPIO

D10

MSCLK

E10

MSDAT

C4

EMCLK

C3

EMDAT

B3

IMCLK

A1

IMDAT

J4

KBCLK

J6

KBDAT

G15

GPIO6/WK_SE11/IRMODE/IRRX3A

G12

GPIO5/WK_SE10/KSO15

G16

GPIO4/WK_SE07/KSO14

R7

KSO13/GPIO18

T7

KSO12/OUT8/KBRST

K8

KSO11

J8

KSO10

L8

KSO9

M8

KSO8

N8

KSO7

P8

KSO6

T8

KSO5

R8

KSO4

R9

KSO3

T9

KSO2

P9

KSO1

N9

KSO0

M9

KSI7

L9

KSI6

K9

KSI5

K10

KSI4

M10

KSI3

R10

KSI2

N10

KSI1

P10

KSI0

A3

XTAL1

C5

XTAL2

LPC47N254V12FBGA_LBGA256~D

K/B

LPC47N254

MACALLEN

MISC

GPIO11/WK_SE15/AB2A_DATA

GPIO12/WK_SE16/AB2A_CLK

GPIO13/WK_SE17/AB2B_DATA

GPIO14/WK_SE20/AB2B_CLK
GPIO15/WK_SE21/FAN_TACH1
GPIO16/WK_SE22/FAN_TACH2

CLOCK

FLASH

256 - LBGA

FPGM

FDC_PP#

TEST_PIN

XOSEL

EC_SCI#

MODE

FDD_LED#
BAT_LED#

LDRQ0#

PWR_LED#

OUT0
OUT1
OUT2
OUT3
OUT4

OUT5/DS1/KBRST

OUT6/MTR1

OUT7/SMI

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

PWRGD

VCC1_PWRGD

RESET_OUT#

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

GPIO19/WK_SE24

PCI_CLK

24MHZ_OUT

32KHZ_OUT

CLOCKI

FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22

FRD#

FWR#

FCS#

L10

A10

K12

B4
K16
E5

J12
J9
M6
J10

C7
F7
B6
E6
C6
A5
B5
D7
B7
E7
A7
G7

K13
K15
H1

C9
A9
E9
D9
H16
H14
J15
J13
G9
F9
F16

J3
J2
D5
J1

N12

FA0

T13

FA1

P12

FA2

T14

FA3

T15

FA4

R16

FA5

N13

FA6

P16

FA7

M14

FA8

N15

FA9

N16
M13
L12
M15
M16
L14
L13
L15
L16
K11
R14
T16
P13

P14
N14
P15

M12

FD7

R12

FD6

T12

FD5

P11

FD4

N11

FD3

M11

FD2

R11

FD1

T11

FD0

SIO_KAH_PGM

FDD_PP#

XOSEL

MODE

BAT1_LED#
LPC_LDRQ0#
BAT2_LED#

EEPROM_WC

HW_RADIO_DIS#
LAN_LOW_PWR
CHG_PBATT
TI_SUSPEND#
AUDIO_ AVDD_ON
LIVE_ON_BATT

FAN2_PWM
BREATH_LED
FAN1_PWM

RUNPWROK
VCC1_PWROK
RESET_OUT#

DAT_SMB
CLK_SMB
DOCK_SMBDAT
DOCK_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH
FAN2_TACH
SIO_A20GATE

CK_33M_SIOPCI

CK_14M_SIO

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16

SIO_FA18
SIO_FA19

FRD#
FWR#
FCS#

SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0

+3VALW

12

R179
1K_0402_5%~D

@

BAT1_LED# <38>
LPC_LDRQ0# <21>
BAT2_LED# <38>

EEPROM_WC <35>
SATA_3V_ENABLE# <39>
HW_R ADIO_DIS# <27,32>
LAN_LOW_PWR <28>
CHG_PBATT <48>
TI_SUSPEND# <30>
AUDIO_ AVDD_ON <24>

QBUFEN#

FAN2_PWM <14>
BREATH_LED <38>
FAN1_PWM <14>

RUNPWROK <18,37,43,44,46>

RESET_OUT# <37>

DAT_SMB <1 9,26,35,47>
CLK_SMB <19,26,35,47>

SBAT_SMBDAT <18>
SBAT_SMBCLK <18>
PBAT_SMBDAT <42,48>

PBAT_SMBCLK <42,48>
FAN1_TACH <14>
FAN2_TACH <14>
SIO_A20GATE <21>

SIO_F A[0..19] <35>

FRD# <35>
FW R# <35>
FCS# <35>

SIO_ FD[0..7] <35>

R180

10K_0402_5%~D

R236

10K_0402_5%~D

R550

10K_0402_5%~D

R207

1 2

10_0402_5%~D@

CK_14M_SIO_TERM

2

C177

1

4.7P_0402_50V8C~D@

12

12

12

R521

C564

1 2

10_0402_5%~D

@

CK_33M_SIOPCI_TERM

2

1

4.7P_0402_50V8C~D @

R230

10K_0402_5%~D

1 2

+3VALW

12

12

LIVE_ON_BATT <39>

CK_33 M_SIOPCI <6>

CK_14M_SIO <6>

R234
10K_0402_5%~D @

R228
1K_0402_5%~D

3

SBAT_SMBDAT

SBAT_SMBCLK

PBAT_SMBDAT

PBAT_SMBCLK

DOCK_SMBDAT

DOCK_SMBCLK

1

3

2

MAX6326

U11

1

VCC

RESET#

2

GND

MAX6326_SOT23~D

VCC1_PWROK <35>

22K_0402_5%~D

22K_0402_5%~D

22K_0402_5%~D

22K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

HW_RADIO_DIS#

LAN_LOW_PWR

CHG_PBATT

+3VALW

R209

1 2

R522

1 2

R198

1 2

R513

1 2

R528

1 2

R533

1 2

12

R235

10K_0402_5%~D

2

C153

0.1U_0402_16V4Z~D

1

+3VALW

12

R551

10K_0402_5%~D

+5VALW

R549

10K_0402_5%~D

12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

LA-1711

SIO (2/2)

1

X02-D

of

34 60Wednesday, July 23, 2003

5

4

3

2

1

+3VALW

12

R552
0_0402_5%~D@

U40

1

D D

DAT_SM2<34>

CLK_SM2<34>

C C

DAT_SM2

CLK_SM2

R166

C140

+5VRUN

12

4.7K_0402_5%~D

1

2

10P_0402_50V8J~D

12

R168

4.7K_0402_5%~D

C146

10P_0402_50V8J~D

BLM11A601S_0603~D

1 2

1 2

BLM11A601S_0603~D

1

2

L8

L9

1

10P_0402_50V8J~D

1

C141

2

2

10P_0402_50V8J~D

C138

+5VRUN

L11

BLM31A260SPT_1206~D

12

1

KSO_17<33,38>

C147

2

0.1U_0402_16V4Z~D

MOUSEDAT

MOUSECLK

MOUSEVDD

KSO_17
KSI3
KSI2
KSI1
KSI0

NC

2

A1

3

A2

4

VSS

FM24C05U_SO8~D

SUB_6782U

SMbus address A2

JPALM

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

HRS_FX6A-20P-0.8SV~D

Keep no nosie coupled,
Especially the TP_GND

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7

B B

KSO[0..15]<34>

KSI[0..7 ]<34,38>

A A

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

5

KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16

KSO16<34>

KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

CN1

CN6

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

@

CN5

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

4

CN4

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

CN3

1 8

2 7

3 6

4 5

100P_1206_8P4C_50V8~D

@

CN2

1 8

2 7

3 6

4 5

1 8

2 7

3 6

100P_1206_8P4C_50V8~D

4 5

100P_1206_8P4C_50V8~D

@

JKYBRD

25
24
23

JAE_FK2S030W11~D

1

C148
100P_0603_50V8J~D

@

2

22
21
20
19
18
17
16
15

30
29

14
13

28
27

12
11

26
10
9
8

31
7

32
6
5

33
4

34
3
2
1

TP_V+
TP_ X
TP_GND
TP_Y
TP_Z

SIO_FA[0..19]<34>

G

2N7002

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

+3VALW

1

C599

0.1U_0402_16V4Z~D

2

8

VCC

SDA

WP

SCL

EEPROM_WC

7

CLK_SMB

6

DAT_SMB

5

EEPROM_WC <34>
CLK_SMB <19,26,34,47>
DAT_SMB < 19,26,34,47>

Address 1010 00XX

JP2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

ACES_6278-34P-DEBUG@

TP_Z
TP_V+
TP_Y
TP_ X
TP_GND

+3VALW

FCS#
FRD#
FWR#
SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0
SIO_FA19
SIO_FA18
SIO_FA17
SIO_FA16
SIO_FA15
SIO_FA14
SIO_FA13
SIO_FA12
SIO_FA11
SIO_FA10
SIO_FA9
SIO_FA8
SIO_FA7
SIO_FA6
SIO_FA5
SIO_FA4
SIO_FA3
SIO_FA2
SIO_FA1
SIO_FA0
FWH_RST

For Compal Flash Tools

SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19

FCS#<34>
FRD#<34>
FWR#<34>

FCS#
FRD#
FWR#

D

S

U14

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

MX29LV008T/B_TSOP40~D

C
1

B
2

VCC
VCC

RP#/RESET#

WP#/RY/BY#

GND
GND

E
3

VPP

31
30
11

SIO_FD0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC
NC

26
27
28
32
33
34
35

10
12
29
38

23
39

SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7

FWH_RST

R219

0_0603_5%~D

12

DTC114

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

LA-1711

+3VALW

1

1

C203

0.1U_0402_16V4Z~D

VCC1_PWROK

C202

2

2

0.1U_0402_16V4Z~D

INT KB & ROM

1

SIO_F D[0..7] <34>

VCC1_PWROK <34>

of

35 60Wednesday, July 23, 2003

X02-D

5

4

3

2

1

CPLD Function options Table

No.

D D

1

2

3

1 2

H_VID0<8 > VID0 <8,46>
H_VID1<8 >
H_VID2<8 >
H_VID3<8 >
H_VID4<8 >
H_VID5<8 >

R15

1 2

R16

1 2

R29

1 2

R31

1 2

R34

1 2

R36

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

VID1 <8,46>
VID2 <8,46>
VID3 <8,46>
VID4 <8,46>
VID5 <8,46>

4

5

6

7

8

9

10

Function

CPLD (U27)

STPCL K# (From ICH to CPU) Pop Q42, R254, Depop R259

CPUSLP# (From ICH to CPU)

Speedstep enable Speedstep disable

Pop U27, C233, C606, R557, Depop U27, JPLD, C233, C606, R557,

Depop Q42, R254, Pop R259

Pop Q43, R561, Depop R251 Depop Q43, R561, Pop R251

VRMPWRG D (From Reset to ICH) Depop R243 Pop R243

STP_AGP# (PLD to AGP) Pop R96, Depop R98 (P.18)Depop R96, Pop R98 (P.18)

CPUPREF# (From PLD to CPU) Depop R380 (P.8)Pop R380(P.8)

STPCPU _VR (From PLD to CPU Power)

DPRSLP VR (Fro m PLD to CPU power)

Depop PR94, Pop PR95 (P.46)Pop PR94, Depop PR95 (P.46)

Depop PR93, Pop PR92 (P.46)Pop PR93, Depop PR92 (P.46)

PLD_WAKE# (From PLD to ICH) Depop R141 (P.21)Pop R141 (P.21)

PLD_DISABLE# Pop R256, Depop R252 Depop R256, Pop R252

11 DPSLP# Pop R76, R78(P.8) Depop R76, R78(P.8)

12 PCI_PC IRST#(From ICH to PLD) Pop R245 Depop R245

GV_HI_LO#13 Pop R253 Depop R253

C C

+3VSUS

Pop when use CPLD

12

R253
10K_0402_5%~D@

GV_HI_LO#

+VCC_ CORE

12

R246
100_0402_5%~D@

+3VRUN

12

H_STPCLK#

R559
10K_0402_5%~D@

CLK_STP_CPU#

5

B B

A A

Pull low disables PLD assertion
of SSTEP or sleep and deeper
sleep on CPU

+3VSUS

12

R256
10K_0402_5%~D@

R557

CLK_STP_CPU#<6>

VCORE _DRSEN<46>

H_CPUSLP#<8>

VRM_PWRGD<21>

+3VSUS

STP_AGP#<18>

PLD_DISABLE#

GV_HI_LO#<33>

NOCREG<33>

H_STPCLK#<8>

SUSPWROK<21,37>

1 2

LONG/SHRT#

1

@

2

12

R252

1K_0402_5%~D@

1K_0402_5%~D

@

C3/C4#

C233

0.1U_0402_16V4Z~D

GV_HI_LO#

H_STPCLK#

PLD_DISABLE#
I_STPCLK#
L_CPUSLP#
H_CPUSLP#

VRM_PWRGD

1

2

Pop when use CPLD

+3VSUS

C606

0.1U_0402_16V4Z~D

@

JPLD

1
2
3
4
5
6

MOLEX_53261-0690~D@

Depop when use CPLD

U27

1

TDI

7

TMS

26

TCK

32

TDO

43

I/O_5

44

I/O_6

2

I/O_8

8

I/O_14

12

I/O_18

13

I/O_19

20

I/O_26

14

I/O_20

42

I/O_4

5

I/O_11

6

I/O_12

10

I/O_16

18

I/O_24

23

I/O_29

41

VCCINT

17

VCCINT

9

VCCIO

29

VCCIO

EPM3032ATC44-10_TQFP44~D@

I/O_40

I/O_9
I/O_21
I/O_25
I/O_27
I/O_28
I/O_31
I/O_39

I/O_41
I/O_43

I/O_33
I/O_34
I/O_37

GND
GND
GND
GND
GND
GND
GND
GND
GND

34

3

DPSLP#

15

CLK_CPLD I_STPCLK#L_CPUSLP#

19
21
22
25
33

35
37

27
28
31

38
36
30
24
16
11
4
40
39

Dell Speedstep Support PLD

4

O_GMUXSEL

R243

1 2

0_0402_5%~D

R245

VRM_PWRGD

1 2

I_VRMPWRGD <37>
DPSLP# <8>

CPUP REF# <8>

0_0402_5%~D@

VCORE _DSEN# <46>

CPLD_WAKE# <21>
SUSCLK <21>

CLK_CPLD

12

R244
22_0402_5%~D @

1

C225

@

10P_0402_50V8J~D

2

R588

1 2

@

0_0402_5%~D

CK_33M_CPLD <6>

PCI_P CIRST# <12,20>

BC2

+VCC_CORE +VCC_CORE

12

R603
680_0402_5%~D@

MMBT3904_SOT23~D@

CPUSLP#<21> STPCLK#<21>

R251

1 2

0_0402_5%~D

1

3

E

DTC114TKA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

+3VSUS +3VSUS

12

R561
470_0402_5%~D@

12

R604
680_0402_5%~D@

Q43

2

3 1

MMBT3904_SOT23~D@

12

R254
470_0402_5%~D@

Q42

2

3 1

Pop when use CPLDPop when use CPLD

H_STPCLK#H_CPUSLP#

R259

1 2

0_0402_5%~D

Depop when use CPLD

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

PLD

LA-1711

1

X02-D

of

36 60Wednesday, July 23, 2003

5

A6Y

THERM_FF_GATE

RUN_ON

R355

1 2

100K_0402_1%~D

R360

1 2

100K_0402_1%~D

+5VSUS

C228 0.1U_0402_16V4Z~D

1 2

U42B

8

TC7W14FU_SSOP8~D

P

2

G

4

Z3805Z3804

Z3806

R362

48.7K_0402_1%~D

12

U36

1

IN+

VCC+

2

GND

3

IN-

OUT

LMV331__DCK

+3VSUS

5

4

+5VRUN

12

R560
100K_0402_5%~D

D D

5VRUNRC

1

C609

0.22U_0603_10V7M~D

2

+3VSUS

R353

1 2

C C

2.21K_0402_1%~D

2

C51

1

1000P_0402_50V7K~D

R94

A1Y

thermistor

1 2

8

U42A

P

7

G

TC7W14FU_SSOP8~D

4

RUN_ON<1 8,33,39,44>

R352

16.2K_0402_1%~D

12

2

C392

1

1000P_0402_50V7K~D

Thermistor goes in CPU cavity.

Dell P/N 8K573

Semitech P/N 103KT2125-1P

B B

C

BE

1

2

3

Dell request populate for SST phase. 2003/0326

3904 SYMBOL(SOT23-NEW)

R272

5

8.2K_0402_5%~D

THERM_TRUE

R282
0_0402_5%~D

@

1 2

THERMTRIP_3P3#

THERM_CPU#

12

13

D

2

G

S

+3VSUS

2

Q60

+3VSUS

R285

8.2K_0402_5%~D

1 2

3 1

+VCC_CORE

R280
1K_0402_5%~D

1 2

Z3808

MMBT3904_SOT23~D

A A

H_THERMTRIP#<8,21>

THERM_FF_GATE

Q57
2N7002_SOT23~D

+3VSUS

5

1

P

B

2

A

G

3

POWER_SW_DB#<39>

Z3809

C619 0.1U_0402_16V4Z~D

1 2

U29

4

O

TC7SH08FU_SSOP5~D

0.1U_0402_16V4Z~D

4

RUNPWROK_1P5V<44>

U26D

74VHC08MTC_TSSOP14~D

12

IN2

OUT

13

IN1

SUSPWROK_3V<39>

V_2P5V_PWRGD<45>

+3VSUS

R359

48.7K_0402_1%~D

1 2

1

C399

0.047U_0402_10V4M~D

2

Q56

2

G

2N7002_SOT23~D

1 3

D

S

THERM_TRUE

C618

1 2

4

11

THERM_CPU#

1 2

1 2

THERM_CLEAR

RUNOK

+3VSUS

1

2

14

1

P

IN1

OUT

2

IN2

G

7

5

4

C226

0.1U_0402_16V4Z~D

3

U26A
74VHC08MTC_TSSOP14~D

MAX6509 goes in CPU cavity.

Discretes go outside.

MAX6509SET

R89

1 2

18.2K_0603_1%~D@

Z3811

R281
0_0402_5%~D

Z3812

Z3813

R275
100K_0402_5%~D

D16

RB751V_SOD323~D

2 1

2

3

+3.3VRTC

12

R572

20K_0402_5%~D

U25B
74VHC08MTC_TSSOP14~D

IN2

6

OUT

IN1

+3VSUS

10

9

POWER
SEQUENCING

HYST:

VCC for 10 degree

GND for 2 degree

U4

1

SET

2

3

VCC

GND

OUT#

HYST

MAX6509CHU-K_SOT23-5~D@

SET-HOT Vrsion

+3.3VRTC

1

R283

1K_0402_5%~D

D

CLK

GND7CLR

C620

0.1U_0402_16V4Z~D

2

1 2

U28A
SN74LVC74APWR_TSSOP14~D

4

14

PRE

VCC

5

Q

6

Q

1

3

150_0402_5%~D

ITP_DBRESET#<8>

U26C
74VHC08MTC_TSSOP14~D

IN1

8

OUT

IN2

+3VSUS

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

RUNPWROK <18,34,43,44,46>

SUSPWROK <21,36>

MAX6509HYST

R607

1 2

56_0402_5%~D

2

G

+3VSUS

1 2

1 2

R93
10K_0402_5%~D

@

R95
10K_0402_5%~D@

13

D

Q71
2N7002_SOT23~D

@

S

1

2

+3VSUS

12

R247

RESET_OUT#<34>

VCORE _PWRGD<44,46>

SIO_THERM_PWRDN

THERM_STP#<43>

THERM_PWRDWN

C659

0.22U_0603_10V7M~D

VTT_PWRGD<44>

IMVP_PWRGD

2

SD 1.11(12474 page292) is request 8.2K ohm

+3VSUS

IMVP_PWRGD

RUNPWROK

+3VRUN

100K_0402_5%~D

1U_0603_6.3V6M~D

+3VALW

R571
10K_0402_5%~D

@

1 2

2

G

R556

1 2

13

D

Q70
2N7002_SOT23~D

S

2

G

2

U26B
74VHC08MTC_TSSOP14~D

4

IN1

OUT

5

IN2

+3VSUS

12

IN2

OUT

13

IN1

U25D
74VHC08MTC_TSSOP14~D

R581

1 2

10K_0402_5%~D

1

C605

2

SIO_THERM_PWRDN <34>

13

D

Q55
2N7002_SOT23~D

S

6

11

1

+3VSUS

9

IN2

8

OUT

10

IN1

U25C
74VHC08MTC_TSSOP14~D

+3VSUS

C603 0.1U _0402_16V4Z~D

1 2

14

U25A

1

P

IN1

2

IN2

A1Y

ICH_T HERM_PWRDN# <21>

IMVP_PWRGD

3

OUT
G

74VHC08MTC_TSSOP14~D

7

shall be VHC14

8

U41A

P

7

G

TC7W14FU_SSOP8~D

4

C607 0.4 7U_0603_16V7K~D

1 2

Title

Size Doc ument Number Re v

LA-1711

Date: Sheet

PWR GD_3V <10,21>

+3VRUN

8

U41C
TC7W14FU_SSOP8~D

P

5

A3Y

G

4

+3VRUN

1

C604

0.1U_0402_10V6K~D

2

8

U41B
TC7W14FU_SSOP8~D

P

2

A6Y

G

shall be VHC14

4

Compal Electronics, Inc.

Thermtrip & PowerGOOD

1

CK_VTT_PG# <6>

I_VRMPWRGD <36>

of

37 60Wednesday, July 23, 2003

X02-D

5

4

3

+5VHDD

2

1

OUT

IN

2 3

+3VRUN

D D

47K

2

CAP_LED#<34>

2

47K

+5VALW

47K

1 3

2

1 3

10K

Q11
DTA114YKA_SOT23~D

10K

Q21
DTA114YKA_SOT23~D

NUM_LED#<34>

SRL_LED#<34>

C C

BAT1_LED#<34>

BAT2_LED#<34>

2

10K

2

10K

10K

47K

1 3

47K

1 3

1 3

R_CAP

Q12
DTA114YKA_SOT23~D

R_SRL

Q22
DTA114YKA_SOT23~D

R_BAT1_LED

R_BAT2_LED BAT2_LED

GND

1

DTA114YKA

Q16
DTA114YKA_SOT23~D

470_0402_5%~D

470_0402_5%~D

R80

470_0402_5%~D

12

R73

470_0402_5%~D

12

R56

12

R52

470_0402_5%~D

12

R46

12

BAT1_LED

CAP_LED

NUM_LEDR_NUM

SRL_LED

47K

1 3

R_PIDEACT

Q44
DTA114YKA_SOT23~D

R60

470_0402_5%~D

0_0402_5%~D

D_IRMODE<33>

1 2

IRTX<33>

R576

12

+3VRUN

R579

1K_0402_5%~D

R_BT_MPCI_ACT
BAT1_LED
BAT2_LED
R_BREATH_LED
ACTLED

CAP_LED
NUM_LED
SRL_LED

LID_CL#

R574

47_0805_5%~D

12

12

R578

1K_0402_5%~D

PIDEACT#<21>

2

10K

+3VRUN

JLED1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

FOX_QTS1030A-2021~D

12

SD_MODE

1

2

C621

1

0.1U_0402_16V4Z~D

C624

2

4.7U_1206_16V6K~D

+3VRUN

U43

6

VCC

5

SD_MODE

2

IRED_CATHODE

3

TXD

TFDU6101E_TR4~D

TFDU6102

IRED_ANODE

RXD

MODE

GND

KSO_17
KSI4
KSI5
KSI6

INT_MIC+
INT_MIC-

POWER_SW#

POWER_SW_EMI

R575

1.8_1206_5%~D

1

4

7

8

0_0402_5%~D

12

0_0402_5%~D @

IRRX <33>

KSO_17 <33,35>
KSI4 <34,35>
KSI5 <34,35>
KSI6 <34,35>

INT_MIC+ <25>
INT_MIC- <25>

POWER_SW# <39>

12

R47

R573

1.8_1206_5%~D

Z3903IRVCC

R577

12

IR_ANODE

+3.3VRTC

12

C623

4.7U_1206_16V6K~D

1

2

B B

+3VALW

R72
150_0402_5%~D

1 2

R92

BREATH_LED<34>

A A

10K_0402_5%~D

5

BREATH_LED_B BT_ACTIVE

1 2

Z3901

2

3 1

Q19
MMBT3904_SOT23~D

R_BREATH_LED

BT_ACTIVE<27>

4

R86

10K_0402_5%~D

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

BT_MPCI_ACTIVE

3

+3VALW

1 2

Z3902

2

3 1

R85
150_0402_5%~D

Q23
MMBT3904_SOT23~D

R_BT_MPCI_ACT

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Electronics, Inc.

LED Interface & IrDA

LA-1711

1

38 60Wednesday, July 23, 2003

X02-D

of

5

PWR _SRC

Run Planes Enable

2

1

R107

2

+5VSUS

G

3

1

C248

2

0.01U_0402_16V7K~D

12

R103
30K_0402_5%~D

Z4002

Q26

TP0610T_SOT23~D

1 3

RUN_ENABLE

12

330K_0402_5%~D

6

2

1

D

Q54
SI3456DV-T1_TSOP6~D

S

+5VHDD

4 5

1

12

R267

2

SUSPWROK_5V

100K_0402_5%~D

2N7002_SOT23~D

C243

4.7U_1206_16V6K~D

SUSPWROK_5V <31,43,45>

12

R99
330K_0402_5%~D

D D

Q25

2N7002_SOT23~D

RUN_ON<1 8,33,37,44>

C C

2

G

+5HDD Source

DTC144EKA_SOT23~D

HDDC_EN#<33>

B B

Q58

Z4001

13

D

C60

S

0.22U_1206_25V7M~D

+12V

12

R276
100K_0402_5%~D

HDD_EN

13

47K

2

47K

+3VSRC

+5VSUS

Q15

2

G

4

Q27
SI3456DV-T1_TSOP6~D

D

6

S

2
1

G

3

Q47
SI3456DV-T1_TSOP6~D

D

6

S

2
1

G

3

VAUX_EN<33,43>

+3VSRC

1
12

R51
100K_0402_5%~D

13

D

S

45

1

C67

2

4.7U_1206_16V6K~D

45

1

C239

2

4.7U_1206_16V6K~D

Q17

2N7002_SOT23~D

+3VRUN Source

+3VRUN

12

R112
10K_0402_5%~D

+5VRUN Source

+5VRUN

12

R260
10K_0402_5%~D

PWR _SRC

12

R62
100K_0402_5%~D

13

D

2

G

S

+3VSRC +3VSUS

0.1U_0402_10V6K~D

12

R63

200K_0402_5%~D

Q20
SI3443DV_TSOP6~D

4

3

1

C33

2

2

G

6
5
2
1

PWR _SRC

11

12

R65
100K_0402_5%~D

13

D

Q67
2N7002_SOT23~D

S

1

2

DTC144EKA_SOT23~D@

RUN_ON<1 8,33,37,44>

C40

4.7U_1206_16V6K~D

3

Q37

ENAB_3VLAN <28>

12

R67
470K_0402_5%~D

+3.3VRTC

47K

2

47K

+VCC_CORE

12
1121

R190
100K_0402_5%~D

@

Z4003

2

2

G

13

12

R176
47_0805_5%~D

@

Z4005

2

Q36
2N7002_SOT23~D@

13

D

S

2

V_1P25V_DDR_VTT +3VRUN

2

G

12

R175
22_0805_5%~D

@

Z4006

Q35
2N7002_SOT23~D@

13

D

S

12
1

2

13

2

G

+5VMOD Source

+3VMOD Source

SATA_3V_ENABLE#<34>

R178
150_0805_5%

@

Q34
2N7002_SOT23~D@

D

S

DTC144EKA_SOT23~D

MODC_EN#<33>

DTC144EKA_SOT23~D@

1

Bridge Battery Conn.

JRBATT

3

+5VSUS

G

C245

3

2

1

4.7U_1206_16V6K~D

+3VSUS

1

G

C235

1
2

6

S

4 5

1

2

2

4 5

1

2

4.7U_1206_16V6K~D@

1
2

MOLEX_53398-0290~D

D

Q50
SI3456DV-T1_TSOP6~D

+5VMOD

12

R273
100K_0402_5%~D

6

D

Q41

S

SI3456DV-T1_TSOP6~D@

+3VMOD

12

R258
100K_0402_5%~D@

RBAT<41>

+12V

12

R277
100K_0402_5%~D

2

MOD_EN

Q59

Q45

13

47K

2

47K

+12V

47K

2

47K

1

C250

2

0.01U_0402_16V7K~D

12

R257
100K_0402_5%~D@

13

1

2

0.01U_0603_50V7K~D@

C236

LIVE_ON_BATT<34>

+3.3VRTC

5

12

10K_0402_5%~D

1

C223

2

0.1U_0402_16V4Z~D

PWR SW_SIO# <33>

POWER_SW#<38>

D5

RB751V_SOD323~D

A A

2 1

+3.3VRTC

C220

R242

1 2

0.1U_0402_16V4Z~D

14

U24A

P

1

2

IN

O

G

SN74LVC14APWR_TSSOP14~D

7

ACAV<34,48>

3

+3.3VRTC

14

U23D

12

P

IN0

13

IN1

G

SN74LVC32APWR_TSSOP14~D

7

+3.3VRTC

14

U24B

P

4

IN

O

G

SN74LVC14APWR_TSSOP14~D

7

4

11

O

+3.3VRTC

C600

1 2

0.1U_0402_16V4Z~D

14

U23A

1

P

IN0

3

O

2

IN1

G

SN74LVC32APWR_TSSOP14~D

7

POWER_SW_DB# <37>

+3.3VRTC

14

U24F

P

13

IN

O

G

SN74LVC14APWR_TSSOP14~D

7

ALWON <43>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

ALW_ENABLE#

12

ALW_ENABLE# <43>

+3VSUS

12

R238
100K_0402_5%~D

1

C214

0.1U_0402_16V4Z~D

2

2

+3.3VRTC +3.3VRTC

14

U24C

P

5

IN

O

G

SN74LVC14APWR_TSSOP14~D

7

14

U24D

6

Title

Size Doc ument Number Re v

Date: Sheet

P

9

8

IN

O

G

SN74LVC14APWR_TSSOP14~D

7

Compal Electronics, Inc.

POWER CONTROL

LA-1711

SUSPWROK_3V <37>

1

X02-D

of

39 60Wednesday, July 23, 2003

5

4

3

2

1

Fiducial Mark

FD13

FD10

FD15

FD2

@

12

11

1

FIDUCIAL MARK

FD9

@

1

FIDUCIAL MARK

FD3

@

1

FIDUCIAL MARK

FD19

@

1

FIDUCIAL MARK

+3.3VRTC

10

14

PRE

VCC

D

CLK

GND7CLR

13

CPU screw hole

D D

H8

H_C315D177@

H12

H_C315D177@

1

1

H11

H7

C315D110@

C315D110@

1

1

MCH screw hole

H9

C315D165

1

H5

C315D165

1

H23

C315D165

1

H6

C315D165

1

C C

VGA Conn. screw hole

H10

C315D165

1

MDC

H15

C217D157

B B

1

PCMCIA Slot screw hole

H26

C197D91@

1

H28

H27

C197D91@

1

H29

C197D91@

C197D91@

1

1

Others screw hole

H2

H1

H_C99D79@

1

H17

C315D110@

1

H34

C315D165

@

1

H_C150D110@

1

H16

C315D110@

1

H35

H_O181X40D181X40N@

1

H3

H_O115X177D95X157@

1

H21

H_C315D110@

1

H19

H_O115X177D95X157@

1

H30

H31

C315D110@

C315D110@

1

1

H36

H_C71 D71N@

1

H4

H_C150D110@

1

H20

C150D110@

1

H33

H32

H_C315D110@

C315D110@

1

1

+3.3VRTC

@

1

FIDUCIAL MARK

FD8

@

1

FIDUCIAL MARK

FD6

@

1

FIDUCIAL MARK

FD20

@

1

FIDUCIAL MARK

U28B
SN74LVC74APWR_TSSOP14~D

9

Q

8

Q

@

1

FIDUCIAL MARK

FD1

@

1

FIDUCIAL MARK

FD5

@

1

FIDUCIAL MARK

+3.3VRTC +3.3VRTC

14

9

IN0

10

IN1

7

+3.3VRTC +12V

14

11

IN

7

FD12

@

1

FIDUCIAL MARK

FD14

@

1

FIDUCIAL MARK

FD16

@

1

FIDUCIAL MARK

U23C
SN74LVC32APWR_TSSOP14~D

P

8

O

G

U24E

P

10

O

G

SN74LVC14APWR_TSSOP14~D

@

1

FIDUCIAL MARK

FD7

@

1

FIDUCIAL MARK

FD17

@

1

FIDUCIAL MARK

4

IN0

5

IN1

FD11

@

1

FIDUCIAL MARK

FD4

@

1

FIDUCIAL MARK

FD18

@

1

FIDUCIAL MARK

U23B
SN74LVC32APWR_TSSOP14~D

14

P

6

O

G

7

8

U46B

5

P

IN+

7

O

6

IN-

G

LM358M_SO8~D@

4

FAN Conn. screw hole

H25

H24

C315D165

1

C315D165

1

PCB

LA1711

PCB

1

EMI Cilps

EMI_CLIP

1

EMI_CLIP

1

PAD5

@

PAD12

@

PAD4

A A

@

PAD11

@

5

EMI_CLIP

1

EMI_CLIP

1

PAD6

@

PAD13

@

EMI_CLIP

1

EMI_CLIP

1

@

@

PAD10

1

PAD14

1

EMI_CLIP

EMI_CLIP

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

PAD,Screw Hole and Spare Parts

LA-1711

1

X02-D

of

40 60Wednesday, July 30, 2003

5

+12V

21

PD1

RB751V-40_SOD323~D

PC1

D D

RBAT<39>

PWR_SRC

PC4

2200P_0402_50V7K

12

C C

12

PC5

2200P_0402_50V7K

0.01U _0402_50V7K~D

1000P_0402_50V7K~D

PFS1

RBAT

0.75A_24V_MINISMDM075/24~D

PR1:19.1K;PR3:13.3K Trickle charger current is 0.45mA for Nimitz.
PR1:16.9K;PR3:8.06K Trickle charger current is 0.5mA for Beijing.

PC6

12

21

12

PC7

0.01U _0402_50V7K~D

Z4201

12

SBATT_VCC

PR1

1 2

19.1K _0402_1%1@

2@ 16.9K_0402_1%~D

12

PR3

13.3K _0402_1%1@

2@ 8.06K_0402_1%~D

2 1

EC10QS04_SOD106~D

SYS_SUSPEND< 18,33>

Z4202

+RTCSRC

PD4

100K_0402_5%~D

SYS_SU SPEND

4

DC_IN+

21

PD2

RB751V-40_SOD323~D

+RTCSRC Source

EC10QS04_SOD106~D

12

PR4

Z4203

2

PD3

21

13

PQ1

IRLM L5103_SOT23~D

2

FET on w hen in suspend, current flow is from Rbat to
PWR_SR C to sustain system during battery swap mode

13

47K

47K

PQ2

DTC1 44EKA_SOT23~D

PWR_SRC

3

+RTCSRC

RTC_SHDN#

1 2

PR2

0_0402_5%~D

NC_LDO_EN

1 2

PR5

0_0402_5%~D@

2

RTC_PWR Source

PU1

1

IN

OUT

5

#SHDN

5/3+

GND

2

MAX1615EUK_SOT23-5~D

@

PU2

1

IN

5

#SHDN

MAX1615EUK_SOT23-5~D

+RTC_PWR

3

4

12

3.3VRTC Source

3

OUT

4

5/3+

GND

2

PC2

10U_1206_6.3V7K~D@

+3.3VRTC

12

PC3

10U_1206_6.3V7K~D

1

D

1

2

3

IRLML5103

S

9

8

7

6

PJPDC1

GND_4

GND_3

GND_2

GND_1

MH1

MH2

Low_PWR

DC+_1

DC+_2

DC-_1

DC-_2

HRS_HR33-DL-7~D

5

PL1

PWR_ID

1

2

DCIN+

3

4

5

CHT_C8BBPH853025

DCIN-

BLM11A121S_0603~D

PL2
CHT_C8BBPH853025

1 2

PL4

1 2

12

PS_ID NB _PSI D <34>PS_ID

+DC_IN

PC15

1 2

0.47U _1812_50V7M~D

100K_0402_5%~D

4

PQ3
SI7447DP_SO8

1
2
3

12

PR8

150K_0402_5%

Z4206

PR12

4

1000P_0402_50V7K~D

12

5

PC10

0.01U _0402_50V7K~D

PC9

1 2

THE POINT

NOTE: "THE POINT LOCATED
AT PS MODULE

12

12

PC11

0.1U_ 0805_50V7M~D

PC12

0.1U_ 0805_50V7M~D

12

0.1U_ 0805_50V7M~D

12

PC13

THESECAPSMUBTBE
NEXT TO JCHG

DC_IN+ Source

PC14

0.1U_ 0805_50V7M~D

12

15U_D2_25M_R90~D@

3

DC_IN+

1

1

+

2

PC8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

PD28

VZ0603M220APT_0603@

2

PS_ID N B_PSID

2

PR6

1 2

0_0402_5%~D

PR13

1 2

0_0402_5%~D

G

Z-series AC Adaptor
Connctor

B B

A A

PR224

0_0402_5%~D@

1 2

PQ4

2N7002_SOT23~ D

D

S

1 3

G

2

12

PR10

100K_0402_5%~D@

+3VALW

PR7

4.7K_ 0402_5%~D

1 2

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

DC-IN

LA-1711

of

1

41 60Wednesday, July 23, 2003

X02-D

5

D D

Primary Battery Connector

PJPB1

SUB_DETECT

BATT2-(GND)
BATT1-(GND)

PC17

C C

B B

2200P_0402_50V7K

1 2

TRACE

THE POINT

BATT_PRES#

14

G

13

G

SUYIN_200275MR012G536ZL~D

SUB_OUT1
SUB_OUT2

BAT_ALERT
SYS_PRES#

SMB_DAT
SMB_CLK

BATT2+
BATT1+

12

11

10

9

8

7

6

5

4

3

2

1

1
2
3
4
5
6
7
8
9
10
11
12

SUBOUT1
SUBOUT2

4

@

DA204U_SOT323~D

SUB_DETECT# <33,50>

PR15

1 2

100_0402_5%~D

+5VALW

3

PD5

1

1 2

100_0402_5%~D

+12V

3

2

PD6

@

DA204U_SOT323~D

PR16

ESD Diodes

2

@

1

DA204U_SOT323~D

PR17

1 2

100_0402_5%~D

1

2

3

PD7

1

PD31
DA204U_SOT323~D

@

3

PC227

1000P_0402_50V7K~D@

1 2

PC226

1000P_0402_50V7K~D@

1 2

3

2

SUBOUT2

SUBOUT1

3

2

PD8

@

1

DA204U_SOT323~D

2

PBAT_ALARM# <34>

PBAT_SMBDAT <34,48>
PBAT_SMBCLK <34,48>

SUBOUT1

SUBOUT2

1

PD32
DA204U_SOT323~D

@

3

Please closely PJPB1

PR238

0_0402_5%~D

PR237

0_0402_5%~D

SUB_OUT2

SUB_OUT1

1 2

1 2

SUB_OUT2 <50>

SUB_OUT1 <50>

2

PC16

0.1U_0805_50V7M~D

1 2

PBATT+

12

PL21

CHT_C8BBPH853025

+5VALW

12

PR14
10K_0402_5%~D

PBAT_PRES# <34>

1

SUYIN_200275MRQ12G536ZL_12P
TOP v iew

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

Battery CONN.

LA-1711

1

42 60Wednesday, July 23, 2003

X02-D

of

5

PL5

HCB4532K-800T90_1812~D

PC34

330U_E_6.3VM~D

SUS_ON<33>

VAUX_EN<33,39>

1 2

PC18

10U_1210_25V6K~D

1

12

+

0.1U_ 0805_50V7M~D

2

12

10U_1210_25V7M~ D

Place these CAPs
close to FETs

PC35

SUS_ON<33>

PC45

12

0.1U_ 0805_50V7M~D

PWR_SRC

Current limit at 4A for +3.3V

D D

+3VSRCP

PR228

0_0402_5%~D@

1 2

PR230

0_0402_5%~D

1 2

C C

B B

PC20

15U_D 2_25M_R90~D@

1

12

PC19

+

2

PC27

0.1U_ 0805_50V7M~D

PC29

2200P_0402_50V7K

PL7

1 2

4.7U_ SPC-1205P-4R7B_+40-20%~D

1

I1

2

I0

+3.3VRTC

PD10

EP10QY03

3

PU4

G

4

O

P

TC7SH32FU_SSOP5~D

5

THERM_STP#<37>

PC21

1

+

15U_D 2_25M_R90~D@

2

12

12

2 1

240K_0402_5%

PC201

4.7U_ 1210_25V6K~D

578

SI4800DY_SO8~D

3 6

241

578

SI4810DY_SO8~D

3 6

241

PR33

1 2

ALWON<39>

12

PQ58

PQ59

2K_0402_1%~ D

4

Adding RC filter

PR18

4.7_1206_5%

1 2

VCC_MAX1999

PC28

12

0.1U_ 0805_50V7M~D

1U_0603_6.3V6M~D

PC31

0.1U_ 0805_50V7M~D

BST_3 LX5

12

1 2

2.2_0 402_5%

LX3

DL3

SKIP#

1 2

PR31

12

PC37

1000P_0402_50V7K~D

PR40

1 2

1K_0402_5%~ D

PC26

PR29

47_0402_5%~D

12

PU3

20

V+

17

VCC

6

SHDN

BST3

28

BST3

26

DH3

27

LX3

24

DL3

22

OUT3

7

FB3

12

SKIP

3

ON3

4

ON5

25

LDO3

MAX1999EEI_QSOP28~ D

12

PC38

10U_1206_10V4Z~D

12

PC232
1U_0805_25V4Z~D

@

+3VALW

PR23

12

RB717F_SOT323~D

+3VSRCP

PD9

4.7U_0805_6.3V6K~D

312

LDO5

BST5

DH5

LX5

DL5

OUT5

N.C.

FB5

PRO

ILIM5
ILIM3

REF
TON
GND

PGOOD

PR34

1 2

100K_0402_5%~D

3

12

12

PC23

2200P_0402_50V7K

Place these CAPs
close to FETs

PQ56

SI4800DY_SO8~D

PL6

1 2

4.7U_ SPC-1205P-4R7B_+40-20%~D
PQ57
SI4810DY_SO8~D

PD11

EP10QY03

2 1

PR30

1 2

0_1206_5%~D

12

PC41

4.7U_ 1210_25V6K~D

RUNPWROK<18, 34,37,44,46>

PC39

4.7U_0805_6.3V6K~D

Current limit at 6A for +5VSUSP

12

0.1U_ 0805_50V7M~D

12

PC43

1U_0805_25V4Z~D

PC42

12

12

0.1U_0402_10V6K~D

PC33

+5VALW

12

PC24

1U_0603_6.3V6M~D

BST_5

PC30

PR28

18

BST5

14

DH5

16

15

DL5

19

21
1
9

PRO#

10

ILIM5

11

ILIM3

5
8

TON

13
23
2

2.2_0 402_5%

1 2

PR218

0_0402_5%~D

REF

12

PC36
1U_0805_25V4Z~D

SUSPW ROK_5V < 31,39,45>

0.1U_ 0805_50V7M~D

1 2

12

0.1U_ 0805_50V7M~D

12

PC25

PC22

578

3 6

241

578

3 6

241

PWR_SRC

10

PU19

7

SHDN

2

VL

3

REF

MAX1745_10uMAX

2

1

PC32

+

2

150U _D2_6.3VM~D

12

PC44

4.7U_1210_25V6K~D

8

IN

VH

EXT

CS

OUT

FB

GND

1

1

ILIM5

ILIM3

PRO#

TON

+5VSUSP

PR19

18.2K _0402_1%

PR24

43K_0402_1%~ D

REF

1 2

20K_0402_1%

1 2

20K_0402_1%

PR20

PR25

VCC_MAX1999

1 2

1 2

0_0402_5%~D

PR22

0_0402_5%~D@

PR21

1 2

1 2

0_0402_5%~D@

PR27

0_0402_5%~D

PR26

1 2

1 2

SKIP#

VCC_MAX1999

PR32

0_0402_5%~D

1 2

@

PR37

0_0402_5%~D

1 2

Adding SKIP control

PR227

0_0402_5%~D@

1 2

PR229

0_0402_5%~D

1 2

36

241

PQ7

9

6

5

4

SI4835DY_SO8~D

578

PD13

EC31QS04~D

Add the current limit

PL8

22U_SIL104-220_2.9A_30%

1 2

2 1

PR223

1 2

0.028 _2512_1%~D

270P_0402_50V7K~D

PC224

(+12V+-5%,2A)

12

PR36

12

182K_0402_1%

PC40

47U_16V

PR41

21K_0402_1%~ D

1 2

+12VP

1

+

2

1

PC225

+

47U_16V@

2

(2A,80mils ,Via NO.= 4)

+12VP

+5VSUSP

+3VSRCP

A A

PJP1

1 2

PAD-OPEN 4x4m

PJP2

1 2

PAD-OPEN 4x4m

PJP3

1 2

PAD-OPEN 4x4m

+12V

(6A,240mils ,Via NO.= 12)

+5VSUS

(4A,160mils ,Via NO.= 8)

+3VSRC

5

+5VALW Source

+5VALW

+RTC_PWR

PR45

100K_0402_5%~D@

ALW_ENABLE#<39>

1 2

PD14

2 1

RB751V-40_SOD323~D@

4

PQ13

@SI2301DS 1P_SOT23~D

1

D3S

G

2

Z4704ALW_ENABLE#

12

PC51

0.1U_0402_10V6K~D@

1

+

PC49

47U_D2_6.3VM~D@

2

3

+3VALW Source

+3.3VRTC

PR46

100K_0402_5%~D@

1 2

PD15

2 1

RB751V-40_SOD323~D@

PQ12

SI2301DS 1P_SOT23~D@

1

G

2

12

PC50

0.1U_ 0402_10V6K~D@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

+3VALW

D3S

1

+

PC48
47U_D2_6.3VM~D@

2

2

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

3.3V/5V

LA-1711

of

1

43 60Wednesday, July 23, 2003

X02-D

5

4

3

2

1

D D

PC52

2200P_0402_50V7K

+1.5VRUNP

PC69

470U_D2_2.5VM

PR55

PR61

+VTT_GMCHP

PR232

0_0402_5%~D

12

12

12

+1.5VRUNP

PC72

47P_04 02_50V8J~D@

C C

36.5K _0402_1%~D

18.2K _0402_1%

B B

1

+

PC220

2

220U_D2_4VM~D

12

PJP4

1 2

PAD-OPEN 4x4m

PJP5

1 2

PAD-OPEN 4x4m

1

+

2

12

+1.5VRUN

+VTT_GMCH

PC54

4.7U_ 1210_25V6K~D

12

1 2

PC53

0.1U_ 0603_25V7M~D

PL10

1 2

2.2U

PC70

4.7U_0805_6.3V6K~D

EC31QS04~D

12

PC55

4.7U_ 1210_25V6K~D

PD17

1

12

+

2

PQ15

FDS6672A_SO8~D

2 1

RUN_ON<18 ,33,37,39>

RUNPWROK_1P5V<37>

PC56
@15U_ D2_25M_R90~D

578

PQ14
IRF7811A_SO8~D

12

3 6

241

578

3 6

241

PR65

0_0402_5%~D

DAP202U_SOT323~D

1U_0805_10V7K~D

PR247
100K_0402_5%~D

PC67

0.1U_0805_25V7K~D

12

0_0402_5%~D

+3VSUS

12

PR68
10K_0402_5%~ D

PD16

12

PR51

1 2

0_0402_5%~D

PR53

1 2

8.87K _0402_1%~D

PR215

+1.5VRUNP/+VTT_GMCHP

PR47

1M_0402_5%~D

1

3

PC65

12

1 2

2

12

12

PC57

1000P_0402_50V7K~D

PR49

1 2

0_0402_5%~D

PR231
10_0402_5%~D

1 2

PC58

1U_0603_6.3V6M~D

1 2

23

25

3

7

6

5

4

2

24

26

22

27

1

28

TON1

VCCA1

VDDP1

BST1

DH1

LX1

ILIM1

DL1

VOUT1

FBK1

EN/PSV1

PGOOD1

PGND1

AGND1

PU7

SC1485

SC1485

PR48
10_0402_5%~D

PC59

1U_06 03_6.3V6M~D

12

TON2

VCCA2

VDDP2

BST2

DH2

LX2

ILIM2

DL2

VOUT2

FBK2

EN/PSV2

PGOOD2

PGND2

AGND2

+5VSUS

9

11

17

21

20

19

18

16

10

12

8

13

15

14

1 2

1 2

0_0402_5%~D

1 2

0_0402_5%~D

1 2

1U_0805_10V7K~D

PC66

1 2

PR50

PR52

PR54

6.04K _0402_1%~D

12

PR57

715K_0402_1%

2200P_0402_50V7K

PC76

12

1000P_0402_50V7K~D

12

PC68

0.1U_0805_25V7K~D

12

PR214

0_0402_5%~D

PL9

1 2

HCB4532K-800T90_1812~D

12

PC61

PC62

0.1U_0603_25V7K~D

PQ16

1

G1

D1

2

D1

S1/D2

3

G2

S1/D2

4

S1/D2

S2

SI4814DY_SO8~D

+5VSUS

12

PR216
10K_0402_5%~ D

PC63

4.7U_ 1206_25V

12

8
7
6
5

12

PC64

4.7U_ 1206_25V

12

PR248
100K_0402_5%~D

PR236

0_0402_5%~D

PR66

0_0402_5%~D@

PWR_SRC

1

12

+

PC60
@15U_ D2_25M_R90~D

2

PL11

1 2

3U

4.7U_0805_6.3V6K~D

12

VC ORE_PWR GD <37,46>

12

RUNPWROK <18,34,37,43,46>

VTT_PWRGD <37>

+VTT_GMCHP

PC221

220U_D2_4VM~D@

PC74

1

12

+

2

CPU_PSC_LOW<46>

2N7002_SOT23~ D

0.01U _0402_50V7K~D@

PQ64

1

220U_D2_4VM~D

+

2

PC73

2

G

PC71

13

D

S

12

12

PR58

30K_0402_1%

12

PR60

15.8K _0402_1%

12

PR240

4.87K _0402_1%~D

A A

Dell-Compal Confidential

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

+1.5VRUNP & +VTT_GMCHP

Size Document Number Re v

B

LA-1711

Date: Sheet

1

of

44 60Wednesday, July 23, 2003

X02-D

5

4

3

2

1

D D

2200P_0402_50V7K

+2.5V_MEMP

1

PC90

1 2

PR234

12

PC92

47P_04 02_50V8J~D

+

2

220U_D2_4VM~D

PR76

220U_D2_4VM~D

0_0402_5%~D

12

12

C C

42.2K _0402_1%~D

PR82
10K_0402_1%~ D

B B

PL13

1 2

2.2UH

1

100_0603_5%~D@

+

PC91

2

PC93

1000P_0402_50V7K~D@

PC77

PR73

PC78

0.1U_0805_25V7K~D

12

12

PD19

EC31QS04~D

12

SUSPWROK_5V<31,39,43>

12

12

PC79

4.7U_ 1210_25V6K~D

PQ47

FDS6672A_SO8~D

2 1

241

V_2P5V_PWRGD<37>

PC80

4.7U_ 1210_25V6K~D

12

PC81

4.7U_1210_25V6K~D

578

3 6

12

578

PQ17
IRF7811A_SO8~D

3 6

241

578

PQ18
FDS6672A_SO8~D

3 6

241

PR86
10K_0402_5%~ D

@

1 2

V_2P5V_PWRGD

1

+

PC82
@15U_D2_25M_R90~D

2

12

PR249
100K_0402_5%~D

0.1U_ 0805_50V7M~D

+5VSUS

PR89
10K_0402_5%~ D

1 2

21

RB751V-40_SOD323~D
PD29

PC218

1U_0805_10V7K~D

12

PC88

12

PR74

1 2

0_0402_5%~D

1 2

12

PC85
1000P_0402_50V7K~D

PR71

1 2

0_0402_5%~D

PR78

1 2

7.5K_ 0402_1%

PR217

0_0402_5%~D

PR69
1M_0402_5%~D

1 2

12

PR77

10_0402_5%~D

PC83

1U_0603_6.3V6M~D

1 2

23

TON1

25

VCCA1

3

VDDP1

7

BST1

6

DH1

5

LX1

2

DL1

4

ILIM1

24

VOUT1

26

FBK1

22

EN/PSV1

27

PGOOD1

1

PGND1

28

AGND1

PU8

SC1486

SC1486

+5VSUS

PR70

10_0402_5%~D

PC84

1U_0603_6.3V6M~D

12

TON2

VCCA2

VDDP2

BST2

DH2

LX2

ILIM2

DL2

FBK2

REFOUT

PGOOD2

REFIN

PGND2

AGND2

0.1U_0402_10V6K~D

1 2

9

11

17

21

20

19

18

16

12

10

13

8

15

14

12

PR85

750K_0402_5%~D

PD30

RB751V-40_SOD323~D

PC86

1000P_0402_50V7K~D

1 2

PR72

1 2

0_0402_5%~D

PR75

1 2

0_0402_5%~D

PR79

1 2

10.7K _0402_1%

+2.5V_MEMP

12

PC101

+5VRUN

21

PC89

12

0.1U_ 0805_50V7M~D

12

PR87
10K_0402_1%~ D

12

PR88
10K_0402_1%~ D

4.7U_1210_25V6K~D

12

PC219

1U_0805_10V7K~D

PR81
10_0402_5%~D

1 2

PC100
1U_06 03_6.3V6M~D

1 2

PC216

1
2
3
4

PC217

0.1U_ 0805_25V7K~D

12

PQ19

8

G1

D1

7

D1

S1/D2

6

G2

S1/D2

5

S1/D2

S2

SI4814DY_SO8~D

PL12

1 2

HCB4532K-800T90_1812~D

1

12

+

PC222

2

@15U_ D2_25M_R90~D

12

12

2200P_0402_50V7K

PR250
100K_0402_5%~D

12

12

PWR_SRC

PC223

PL14

1 2

3uH

PR80

100_0603_5%~D@

PC97
1000P_0402_50V7K~D

@

+2.5V/+1.25V

DDR Termination Voltage

4.7U_0805_6.3V6K~D

150U _D2_6.3VM~D

PC96

1 2

PC94

V_1P25V_DDR_VTTP

1

1

PC95

+

+

150U _D2_6.3VM~D

2

2

PJP6

PAD-OPEN 4x4m

1 2

PJP7

PAD-OPEN 4x4m

+2.5V_MEMP

A A

V_1P25V_DDR_VTTP

5

1 2

PJP8

1 2

PAD-OPEN 4x4m

+2.5V_MEM

(12A,360mils ,Via NO.=24)

V_1P25V_DDR_VTT

(3A,200mils ,Via NO.=6)

4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

1.25V/2.5V

LA-1711

1

45 60Wednesday, July 23, 2003

X02-D

of

5

4

3

2

1

D D

+5VRUN

12

PR92

0_0402_5%~D

1 2

VCORE_DRSEN<36>

C C

VCORE_DSEN#<36>

7

O

PU20B

LM358M_SO8~D

B B

+5VRUN

8

P

IN+

IN-

G

4

PR93

1 2

0_0402_5%~D@

PR94

0_0402_5%~D@

0_0402_5%~D@

5

6

VID_PWRGD<8>

PR226

+3VSUS

PR117

0_0402_5%~D

A A

RUNPWROK<18,3 4,37,43,44>

PR225

0_0402_5%~D@

1 2

12

PR95

12

100P_0402_50V8K~D

5

0_0402_5%~D

+5VRUN

PR99

12

1 2

0_0402_5%~D@

12

PC104

1.2VDD

12

12

PC110

4.7U_1206_16V6K~D

PR122

12

0_0402_5%~D

VID4<8,36>
VID3<8,36>
VID2<8,36>
VID1<8,36>
VID0<8,36>
VID5<8,36>

VCORE _ENLL<8>

12

PR100
365_0402_1%~D

12

PR101
21K_0402_1%~D

PR108

45.3K_0402_1%

PU10

1

4

3

MIC5258

PR124

100K_0402_5%~D

1 2

12

PR98

66.5K_0402_1%

LM358M_SO8~D

PR103

10K_0402_1%~D

1 2

VIN

PG

EN

PU20A

1

12

90.9K_0603_1%~D

12

VCORE_PHOT#<10,34>

VOUT

GND

+5VRUN

8

P

IN+

O

IN-

G

4

PR104

PR113

32.4K_0402_1%

5

2

3

2

+3VRUN

12

+VCCVID

12

1. When mode control signal is
low/ high, the VR will operate to
Northwood/ Prescott load line.

2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.

4

PC102
1U_1210_50V7M

PC103

12

0.033U_0603_25V7M~D

Frequency Select

PR106

0_0402_5%~D

1 2

12

PC108

220P_0402_50V8J~D
PR114
10K_0402_5%~D

1 2

PC112

4.7U_1206_16V6K~D

Panasonic ERTJ0EV334J (0402)
Locate this NTC resistor on
PCB between phase 2 and 3
for thermal compensation.

2N7002_SOT23~D

12

PR96
1K_0402_1%~D

@

PR112

330K_0603_5%~D

1 2

PQ61

PU9

32

VCC

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

VID12.5

34

ENLL

33

DRSEN

35

DSEN#

10

OCSET

11

SOFT

9

DSV

36

FS

37

DRSV

38

VR-TT#

40

NTC

12

GND

19

GND

ISL6247CR_QFN40~D

TP0610T_SOT23~D

13

D

2

G

S

CPU_PSC_HI<49>

100K_0402_5%~D

PR109

3

RAMPS

PGOOD

PWM1

ISEN1+

ISEN1-

PWM2

ISEN2+

ISEN2-

PWM3

ISEN3+

ISEN3-

PWM4

ISEN4+

ISEN4-

1M_0402_5%~D

PQ60

2

CPU_P SC_LOW<44>

12

22K_0402_5%

PR90

80.6K_0402_1%~D

7

10K_0402_5%~D

39

25

24
23

26

27
28

20

21
22

31

30
29

15

COMP

13

FB

14

NC

16

VDIFF

17

VSEN

18

VRTN

8

OFS

12

PR110

13

PR220

604K_0402_1%

PR123

12

MMBT3904_SOT23~D

PWR_SRC

Battery Feed
Forward

PR91

1 2

PR107

0_0402_5%~D

0.1U_0402_10V6K~D

PC214

PR118

27K_0402_5%

1 2

1 2

2

G

PQ62

2

3 1

12

PR97

0_0402_5%~D@

12

+5VRUN

PR205

5.1K_0402_1%~D

1 2

13

D

S

12

+5VRUN

1000P_0402_50V7K~D@

PC105

PC109

4700P_0402_25V7K~D

Place close to IC

1 2

12

PC111

1U_0603_6.3V6M~D

PQ46

2N7002_SOT23~D

PR120

0_0402_5%~D

PR121

0_0402_5%~D@

12

1000P_0402_50V7K~D@

12

2N7002_SOT23~D

12

12

2

VCORE _PWRGD <37,44>

PWM1 <47>

ISEN1+ <47>
ISEN1- <47>

PWM2 <47>

ISEN2+ <47>
ISEN2- <47>

PWM3 <47>

ISEN3+ <47>
ISEN3- <47>

PWM4 <47>

ISEN4+ <47>
ISEN4- <47>

PR102

10K_0402_1%~D

1 2

PC106

12

PR115
0_0402_5%~D@

12

PR111

1.87K_0402_1%~D

1 2

S

PQ45

G

PR116

1 2

0_0402_5%~D

PR119

0_0402_5%~D@

Place near +VCC_CORE
output capacitor

VSSSENSE <8>

Title

Size Docu men t Number R ev

Dat e: Sheet

D

13

9.31K_0402_1%~D

2

12

LA-1711

PR204

12

+VCC_CORE

VCCSENSE <8>

Compal Electronics, Inc.

12

PR241
39K_0402_1%

PQ65

13

D

2N7002_SOT23~D

2

G

S

Remote
Sensing

CPU_CORE_Controller

1

DT/MT# <49>

46 60Wednesday, July 23, 2003

X02-D

of

5

PR125
0_0402_5%~D

PU11

6

VCC

3

PWM

7

EN

4

GND

ISL62 07CB-T_SO8~D

PR134
0_0402_5%~D

PU12

6

VCC

3

PWM

7

EN

4

GND

ISL62 07CB-T_SO8~D

PR143
0_0402_5%~D

PU13

6

VCC

3

PWM

7

EN

4

GND

ISL6207CB-T_SO8~D

0.15U_0805_16V7K~D
PR152
0_0402_5%~D

PU14

6

VCC

3

PWM

7

EN

4

GND

ISL62 07CB-T_SO8~D

PC113

12

0.15U _0805_16V7K~D

2

BOOT

1

UGTE

0_0402_5%~D

8

PHSE

5

LGTE

PC145

1 2

0.15U _0805_16V7K~D

2

BOOT

1

UGTE

0_0402_5%~D

8

PHSE

5

LGTE

PC152

1 2

0.15U _0805_16V7K~D

2

BOOT

1

UGTE

0_0402_5%~D

8

PHSE

5

LGTE

PC159

1 2

2

BOOT

1

UGTE

0_0402_5%~D

8

PHSE

5

LGTE

IRF7811W_SO8~D

PR210

12

Phase1

PQ22

SI4362DY_SO8~D

LG1 UG1UG2

PQ24

IRF7811W_SO8~D

PR211

12

Phase2

PQ26

SI4362DY_SO8~D

LG2UG3

PQ28

IRF7811W_SO8~D

PR212

12

Phase3

PQ30

SI4362DY_SO8~D

LG3UG4

PQ32

IRF7811W_SO8~D

PR213

12

Phase4

PQ34

SI4362DY_SO8~D

LG4

PQ20

+5VRUN

1 2

PWM1<46>

D D

PWM2<46>

C C

PWM3<46>

B B

PWM4<46>

A A

PR127

@

499K_0603_1%

1 2

PR136

@

499K_0603_1%

1 2

PR145

@

499K_0603_1%

1 2

PR154

@

499K_0603_1%

1 2

PR153

12

0_0402_5%~D

PC132

0.1U_0402_10V6K~D

ISEN1-<46>

ISEN1+<46>

1U_0805_25V4Z~D

ISEN2-<46>
ISEN2+<46>

1U_0805_25V4Z~D

ISEN3-<46>
ISEN3+<46>

1U_0805_25V4Z~D

ISEN4-<46>
ISEN4+<46>

5

1 2

1U_0805_25V4Z~D

PC149

PC157

PC164

PC133

1 2

1 2

1 2

1 2

1 2

1 2

1 2

578

3 6

578

3 6

578

3 6

578

3 6

578

3 6

578

3 6

578

3 6

578

3 6

241

241

241

241

241

241

241

241

4

578

PQ21

IRF7811W_SO8~D

578

PQ48
FDS7064N_SO8

@

3 6

578

PQ25

IRF7811W_SO8~D

578

PQ50

FDS7064N_SO8@

3 6

241

578

PQ29

IRF7811W_SO8~D

578

PQ52

FDS7064N_SO8@

3 6

241

578

PQ33

IRF7811W_SO8~D

578

PQ54

FDS7064N_SO8@

3 6

4

CPU_PWR_SRC

1U_0603_6.3V6M~D

3 6

241

9

241

DUAL FOOTPRINT

PC146

1U_0603_6.3V6M~D

3 6

241

9

SI4362DY_SO8~D

DUAL FOOTPRINT

PC153

1U_06 03_6.3V6M~D

3 6

241

9

PC160

1U_06 03_6.3V6M~D

3 6

241

9

241

DUAL FOOTPRINT

PC114

12

10U_1210_25V6K~D

578

SI4362DY_SO8~D

3 6

241

CPU_PWR_SRC

10U_1 210_25V6K~D

12

578

PQ27

3 6

241

CPU_PWR_SRC

10U_1210_25V6K~D

12

PQ31

SI4362DY_SO8~D

578

3 6

241

DUAL FOOTPRINT

CPU_PWR_SRC

10U_1210_25V6K~D

12

PQ35

SI4362DY_SO8~D

578

3 6

241

0.1U_ 0603_25V7M~D

PC115

1 2

578

PQ23

3 6

241

PC147

12

0.1U_ 0603_25V7M~D

578

3 6

FDS7064N_SO8@

PC154

12

PC204

0.1U_ 0603_25V7M~D

578

3 6

241

FDS7064N_SO8@

PC161

12

12

PC205

0.1U_ 0603_25V7M~D

578

3 6

FDS7064N_SO8@

PC202

12

FDS7064N_SO8@

12

PC203

241

12

PQ53

241

9

PQ49

9

PQ51

9

9

PQ55

Local Transistor
Swtich Decoupling

PC206

12

2200P_0402_50V7K

12

PC131

Snubber

@

1000P_0402_50V7K~D

PR129

@

2.2_0805

1 2

12

PC207
2200P_0402_50V7K

12

PC148

Snubber

@

1000P_0402_50V7K~D

PR138

@

2.2_0805

1 2

12

PC208

2200P_0402_50V7K

12

PC155

Snubber

@

1000P_0402_50V7K~D

PR147

2.2_0805

@

1 2

12

PC209
2200P_0402_50V7K

12

Snubber

PC162

@

1000P_0402_50V7K~D

PR156

@

2.2_0805

1 2

3

Panasonic ETQ-P4LR56WFC

PL16

1 2

0.56U _ETQP4LR 56WFC_21A_20%~D

PR130

12

25.5K _0402_1%

Local Transistor
Swtich Decoupling

Panasonic ETQ-P4LR56WFC

PL17

1 2

0.56U _ETQP4LR 56WFC_21A_20%~D

PR139

12

25.5K _0402_1%

Local Transistor
Swtich Decoupling

Panasonic ETQ-P4LR56WFC

PL18

1 2

0.56U _ETQP4LR 56WFC_21A_20%~D

PR148

12

25.5K _0402_1%

Local Transistor
Swtich Decoupling

Panasonic ETQ-P4LR56WFC

PL19

1 2

0.56U _ETQP4LR 56WFC_21A_20%~D

PR157

12

25.5K _0402_1%

3

PC134

12

0.01U _0402_50V7K~D

PR133

12

820_0603_1%~D

PTC resistor

PC151

12

0.01U _0402_50V7K~D

PR142

12

820_0603_1%~D

PTC resistor

PC158

12

0.01U _0402_50V7K~D

PR151

12

820_0603_1%~D

PTC resistor

PC165

12

0.01U _0402_50V7K~D

PTC resistor

PR160
820_0603_1%~D

1 2

CPU_PWR_SRC

10U_1 210_25V6K~D

CPU_PWR_SRC

PC135

@

15U_D2_25M_R90~D

2

PL15

PWR_SRC CPU_PWR_SRC

1 2

CHT_C8BBPH853025

Input Bulk and HF Capacitors

PC116

PC117

12

12

10U_1 210_25V6K~D

1

+

PC136

2

15U_D 2_25M_R90~D@

PC118

12

10U_1210_25V6K~D

10U_1 210_25V6K~D

PC137

1

15U_D 2_25M_R90~D@

+

2

PC119

1

+

2

15U_D2_25M_R90~D@

PC120

12

12

10U_1 210_25V6K~D

10U_1210_25V6K~D

1

15U_D2_25M_R90~D@

+

PC138

2

PC139

PC121

12

1

2

PC122

12

10U_1210_25V6K~D

1

+

+

PC140

2

15U_D 2_25M_R90~D@

PC123

12

10U_1 210_25V6K~D

PC141

1

15U_D 2_25M_R90~D@

+

2

PC142

15U_D 2_25M_R90~D@

12

0.1U_ 0603_25V7M~D

PC143

1

15U_D 2_25M_R90~D@

+

2

PC215

1

+

2

1

1

+

PC144

2

15U_D2_25M_R90~D@

Low-side two population options

FDS7064N_SO8:
PQ48,PQ49,PQ50,PQ51,
PQ52,PQ53,PQ54,PQ55

1

2

3

PC210

0.1U_ 0402_10V6K~D

+3VALW

12

PR219
10K_0402_5%~ D

PU18

SDA

AS

ALERT

GND

SCL

VDD

AD7414ART-0_SOP23-6

6

5

4

DAT_SMB < 19,26,34,35>

1 2

PR222 0_0402_5%~D

CLK_SMB <19,26,34, 35>

Address 1001 001X (X=1-->Read; X=0-->Write)

ATF_INT# <19,33>

+VCC_CORE

SI4362DY_SO8:
PQ22,PQ23,PQ26,PQ27,
PQ30,PQ31,PQ34,PQ35

Address select(7414ART-0)
Float: 1001 000
GND: 1001 001
VDD: 1001 010

+3VALW

12

Notes:

The ISL6561(ISL6427) supports lossless current sensing including
Inductor DCR and MOSFET rDSon sensing. Schematic components are
color coded accordingly. In addition an external sense resistor
can be used for higher load-line accuracy but this will impact
system cost and efficiency.

Sync. Rectifiers use thermally enhanced "PowerPak" technology in
an SO-8 form-factor. Optimal MOSFETS will be chosen based on
thermal performance.

Depending on the processor final requirments and empirical
thermal result testing a 3 phase solution may be possible. In
the 4 phase configuration a single upper mosfet may also be
sufficient.

Add thermal venting vias to board. Vias under parts must have a
minimum pitch of 1mm and hole size of 0.3mm to avoid solder
wicking.

DCR
Inductor
Sensing

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

CPU_CORE_Power-Stage

LA-1711

1

X02-D

of

47 60Wednesday, July 23, 2003

5

D D

PD25

5

PR198

PR178
0_0402_5%~D

12

PR188

10K_0402_1%~D

1 2

PQ40
BSS138_SOT23~D

13

D

2

G

S

B540C~D@

2 1

SI7447DP_SO8

12

ACAV<34,39>

12

TM

1 2

PR191

100K_0402_5%~D

1 2

DC_IN+ discharge path

DC_IN+

PR197
10K_0402_5%~D

2

G

PR169

365K_0402_1%~D

PC168

1 2

1U_0805_25V4Z~D

1 2

PC180

1 2

1 2

+5VALW

1 2

59K_0402_1%~D

PR190

1 2

1 2

13

D

10K_0402_5%~D
PQ43
BSS138_SOT23~D

S

PR179

0_0402_5%~D

PC193

1U_0805_25V4Z~D

PR187

TH

PQ42

BSS138_SOT23~D

PR200

2K_0402_1%~D

PC213

12

100K_0402_5%~D

12

PC172

0.01U_0402_50V7K~D@

0.01U_0402_50V7K~D

10U_1210_25V6K~D

ACAV<34,39>

C C

DC_IN+

10U_1210_25V6K~D

B B

2

G

PR201

12

12

PC166

PR174

1 2

49.9K_0402_1%~D

1 2

0.01U_0402_50V7K~D

PC183

13

D

S

0.01U_0402_50V7K~D

PC181

12

10K_0402_1%~D

4

PQ41

1
2
3

4

PR199

12

100K_0402_5%~D

12

PR251
0_0402_5%~D

@

PR173

75K_0402_1%~D@

PR176

1 2

20K_0402_1%

PC192
1500P_0402_50V7K~D

PBAT_SMBDAT<34,42>

1 2

PBAT_SMBCLK<34,42>

T16

PC185

0.1U_0603_25V7K~D
PD23

21

RB751V-40_SOD323~D

+SDC_IN

0_0402_5%~D

0.1U_0805_25V7K~D@

ACOK#

12

CCV

PAD@

1645_DAC

1 2

CHG_PBATT <34>

1U_0603_6.3V6M~D

PR166

PC169

31

27

32

12

13

14

15

16

11

1

3

6

7

8

PC186

1 2

1 2

PU6

PDS

SRC

DCIN

ACIN

ACOK

CCS

CCI

CCV

VDD

THM

SDA

SCL

/INT

DAC

PR165

1 2

0.01_2512_1%~D

CSSP

29

CSSP

MAX1535X_QFN32~D

REF4GND18IMAX

GND

5

CHVREF

1 2

PWR _SRC

CSSN

28

CSSN

PR167

0_0402_5%~D

1 2

PC170

0.1U_0805_25V7K~D

@

1 2

17

I.C.

25

DHIV

30

PDL

2

LDO

24

DLOV

26

DHI

23

DLO

22

PGND

21

CSIP

20

CSIN

19

BATT

9

VMAX

PR185

10

280K_0402_1%~D

PR184

182K_0402_1%

1 2

+3.3VRTC

PR239

@

100K_0402_5%~D

1 2

ACOK#

PWR _SRC

PC182

1U_0805_25V4Z~D

12

PR175

33_0402_5%~D

DLOV

DLO

CHVREF

12

3

1

2

3

PL22

1 2

MCK4532800YAT_1812

PDL <49>

PC171

1 2

1U_0603_6.3V6M~D

1 2

PC174

0.1U_0402_10V6K~D

CSIP

CSIN

PBATT+

0.1U_0603_25V7K~D@

PR182

12

31.6K_0603_0.1%~D

PR189
182K_0603_0.1%~D

1 2

PU21

NC

A

GND

@

TC7SH14

FDS6679Z

12

CHVREF

PQ37

VCC

PC194

Y

5

4

CHAGE R_SRC

36

241

578

578

3 6

241

1 2

PC228

12

@

0.1U_0402_10V6K~D

ACAV

PQ69

FDS66 79Z

PQ38
FDS6672A_SO8~D

PD22
EC31QS04~D

2 1

PR183

1 2

0_0402_5%~D

1 2

36

578

PL20

1 2

3.2UH _12.8A

PC195

0.1U_0603_25V7K~D@

241

2200P_0402_50V7K

2

+5VALW

1 2

ACOK#

PC175

12

PC176

0.1U_0805_50V7M~D

PR177

CHG_CS

1 2

0.01_2512_1%~D

PR186

1 2

0_0402_5%~D

PR172
100K_0402_5%~D

@

PC177

0.1U_0805_50V7M~D

1 2

4.7U_1210_25V6K~D

1 2

15U_D2_25M_R90~D@

PC187

PC173

12.7K_0402_1%

10U_1210_25V6K~D

1

+

2

0.1U_0805_50V7M~D

12

12

PC188

4.7U_1210_25V6K~D

PR161

75K_0402_1%~D

PR170

PC211

12

PC189

1 2

ACAV

DC_IN+

12

12

12

PC212
10U_1210_25V6K~D

PR181

1 2

1.2K_1206_5%~D@

13

D

2

G

S

1

12

PR162
1K_0402_5%~D

PR164

1 2

10K_0402_1%~D

PR168

1 2

1M_0402_5%~D

PU15

2

AS2431_SOT23~D

1 3

PBATT+

PC190

4.7U_1210_25V6K~D

12

PQ63
BSS138_SOT23~D@

+3.3VRTC

2

1

+

PC184
15U_D2_25M_R90~D

@

2

PQ36

31

2SA1036K_SOT23~D

ACAV

12

PR171
100K_0402_5%~D

VMAX=3.49V

A A

5

4

Maximum charger voltage=17.45V

IMAX=1.6V
Maximum charger current=8A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

2

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

CHARGER CONTROL

LA-1711

1

48 60Wednesday, July 23, 2003

X02-D

of

5

D D

DC_IN+

C C

PBATT+

4

PD26

2 1

B540C~D

PQ44

SI7447DP_SO8

5

4

PR252

1 2

0_0402_5%~D

PR253

PDL<48>

1 2

0_0402_5%~D

@

12

3

1
2
3

2200P_0402_50V7K

PR202
470K_0402_5%~D

PC199

2

1

PWR _SRC

12

PC200

0.1U_0805_50V7M~D

1 2

+5VSUS

12

PC229

0.1U_0402_10V6K~D

PR242

PR245

1 2

12K_0402_5%~D

2.7K_0402_5%~D

B B

DT/MT_SELECT<33>

A A

5

2

G

+5VSUS

12

13

D

S

PR244
10K_0402_5%~D

PQ68
2N7002_SOT23~D

DT/MT# <46>

4

VCORE_BOOTSELECT<7>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVIS ION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRON ICS, INC .

3

1 2

2

3 1

PQ67

MMBT3904_SOT23~D

12

PR243
10K_0402_5%~D

B

2

12

PR246
10K_0402_5%~D

E

3

MMBT3906_SOT23~D
PQ66

C

1

2

12

PC230

0.1U_0402_10V6K~D

CPU_PSC_HI <46>

12

PC231

0.1U_0402_10V6K~D

Title

Size Doc ument Number Re v

Date: Sheet

Compal Electronics, Inc.

Battery Discharge

LA-1711

1

49 60Wednesday, July 23, 2003

X02-D

of

5

4

3

2

1

D D

+3VRUN

12

SUB_DETECT#<33,42>

C C

SUB_VREF

12

SUB_GAIN0

SUB_GAIN1

12

R589
10K_0402_5%~ D

2

G

Gain Setting

R592
100K_0402_5%~D

R596
100K_0402_5%~D@

SPK_SHUTDOWN#<24,25>

12

R590
10K_0402_5%~ D

13

D

Q74
2N7002_SOT23~ D

S

12

12

R593
100K_0402_5%~D @

R597
100K_0402_5%~D

+3VRUN

5

1

B

2

A

3

U44

P

G

TC7SH08FU_SSOP5~D

C640 0. 1U_0402_16V4Z~D

1 2

SUB_SHUTDOWN#

4

O

AUD_MONO_OUT<24>

SUB_VREF

1

C651
1U_0805_25V4Z~D

2

C658

1000P_0402_50V7K~D

1 2

C655

1000P_0402_50V7K~D

1 2

C645

1 2

0.22U _0603_10V7M~D

1

2

1 2

0.22U _0603_10V7M~D

1U_0805_25V4Z~D

1

C653

2

1U_0805_25V4Z~D

SUB_SHUTDOWN#

C644

SUB_GAIN0

SUB_GAIN1

C648

1 2

12

C654

220P_0402_50V7K

Need to FILTER!!!

2

C641

1U_08 05_16V7K

1

U45

24

VCC

5

SHDN

1

INN

2

INP

3

GAIN0

4

GAIN1

7

VCLAMP

23

VREF

22

BYPASS

21

COSC

20

ROSC

PGND

R595

6

120K_0402_5%~D

PGND12PGND

AGND18AGND

13

+12V

1

C642
10U_1206_16V4Z~D

2

8

BSN

9

PVCC

11

OUTN

10

OUTN

14

OUTP

15

OUTP

16

PVCC

17

BSP

TPA3001D1PWP_TSSOP24~D

19

+12V

C646

1U_08 05_16V7K

C650

1U_08 05_16V7K

+12V

R591

1 2

51_0603_1%

12

12

R594

1 2

51_0603_1%

C643

1 2

0.22U _0603_16V7K

D20

2 1

B130-13_SMA~D

D21

2 1

B130-13_SMA~D

C652

1 2

0.22U _0603_16V7K

L49

1 2

BLM21 PG600SN1D_0805~D

L50

1 2

BLM21 PG600SN1D_0805~D

1

C647
1000P_0402_50V7K~D

2

1

C649
1000P_0402_50V7K~D

2

SUB_OUT1AUD_MONO_OUT

SUB_OUT2

SUB_OUT1 <42>

SUB_OUT2 <42>

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELE CTRON ICS, I NC. N EITHER THIS S HEET N OR THE I NFORM ATION IT CON TAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOU T PRIO R WRIT TEN CO NSENT OF COMP AL ELEC TRONI CS, IN C.

2

Subwoofer

Size Document Number Re v

LA-1711

Date: Sheet

1

of

50 60Wednesday, July 23, 2003

X02-D