Page 1
5
D D
4
3
2
1
Prescott & Springdale Schematic with Capture CIS
and Function field
C C
uFCPGA Prescott
REV: A00-B
Cature library ball out check document
Prescott : Prescott processor Electrial,Mechanical and
Thermal Specification Rev0.5 [Check by HW:Henry,Steve]
B B
Springdale(GMCH): Springdale GMCH External Design
Specification (EDS) REV1.0 [Check by HW: Henry,Rita]
ICH5: N/A
2004-01-28
@ : Depop Component
1@ : Depop on Nimitz(Inspiron)
2@ : Depop on Alcatraz
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
Cover Sheet
LA-1711
1
1 65
A00-B
Page 2
5
4
3
2
1
Block Diagram
D D
ADT7460 Thermal sensor
page 19
HA#(3..31)
VGA
Board
AGP CONN.
[CRT CONN. & TV-OUT]
C C
AGP4X/8X(1.5V)
page 18
Prescott
478 uFCPGA CPU
page 7,8,9
System Bus
533/800MHz
Springdale
GMCH
932 FC-BGA
page
10,11,12,13
HD#(0..63)
Memory
BUS(DDR)
2.5V
266/333/400MHz
2.5V
266/333/400MHz
Channel A SO-DIMM
BANK 0, 1, 2,3
Channel B SO-DIMM
BANK 0, 1, 2,3
page 15
page 16
Fan Control
page 14
Clock Generator
CK409
page 6
HUB Link
MINI PCI
page 32
PCI BUS
IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)
B B
LAN
BCM5705M
BCM4401
page 28
Transformer
page 29
RJ45
page 29
CardBus Controller
PCI4510
1394 Conn.
page31
3.3V 33MHz
page 30
Slot 0
page31
X BUS
LPC BUS
3.3V 33MHz
SST39VF080
A A
5
page 35
Touch Pad
page 35
4
1.5V
66Mhz
266MB/S
Macallen
LPC to X-BUS
& Super I/O
SATA
ATA100
3.3V 24.576MHz
3.3V ATA100
ATA100
HDD
page 21
ICH5
460 BGA
Page
20,21,22
CDROM
USB
FDD
Page
33,34
USB2.0
Int.KBD
page 35
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
USBPORT 4
page 23
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
page 26
page 27
USBPORT 6
AMP& Phone
Jack Interface
BT
BACK
DOG
MOD
BACKUSBPORT 5
BACK
2
AC-LINK
AC97
Codec
STAC9750
page 24
page 25
MDC
page 27
Subwoofer
page 50
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DC IN
BATT
IN
3.3V/5V
1.5V/+VTT_GMCH
1.25V/2.5V
VCORE
VCORE_CTRL
CHARGER
Block Diagram
LA-1711
1
2 65Wednesday, January 28, 2004
page 41
page 42
page 43
page 44
page 45
page 47
page 46
page 48
A00-B
Page 3
5
PM TABLE
power
plane
State
D D
S0
S1
+3VALW
+5VALW
ON
ON
+3VSUS
+5VSUS
+2.5V_MEM
+3.3VRTC
+RTC_PWR
V_1P25V_DDR_VTT
ON
ON
+3VRUN
+5VRUN
+1.5VRUN
+VCC_CORE
+12V
+VCCVID
ON
ON
4
Bring up
SST-Build
PT-Build
ST-Build
QT-Build
Pilot-Build
3
MCH Rev. ICH5 Rev.
RG828SDGES FW82801EB
RG828SDGP
A2(QE45)
RG82865PE
A2(SL722)
RG82865PE
A2(SL722)
RG82865PE
A2(SL722)
A1(QE16ES)A1(QE18)
FW82801EB
A3(QE51ES)
FW82801EB
A3(SL73Z)
FW82801EB
A3(SL73Z)
FW82801EB
A3(SL73Z)
2
1
IDSEL
Reserved
BT
BACK
DOG
MOD
BACK
BACK
Reserved
ON
ON
ON
OFF
OFF
REQ#/GNT#
AD17
AD16
AD19
Note : "@" means all model depop
1
4
3
"1@" means Nimitz depoped only
"2@" means Alcatraz depoped only
Model
Function
Smart Card
LAN
Dog House
OFF
OFF
OFFOFF
PIRQ
D,C
C
D,B(NP)
A,B(NP)
Nimitz Alcatraz
No
10/100
(4401)
YES YES
No
1000
(5705M)
Configuration List
BOM Structure
Function
Bridge/Cell battery circuit options Table
No.
1
2
3
4
Bridge battery
Pop D3 and R158 ; Depop R623
Pop R232 ; Depop R624 Pop R624 ; Depop R623 33
Pop PD1,PD2,PD3,PD4,PQ1,PQ2,PFS1,
PR1,PR3,PR4 and PC1; Depop PR258,PR259
Cell battery
Pop R623 ; Depop D3 and R158
Pop D23Depop D23 39
Depop PD1,PD2,PD4,PQ1,PQ2,PFS1,PR1
PR3,PR4 and PC1; Pop PR258,PR259,PD3
Page
21
41
S3
S5 S4/AC
S5 S4/AC don't exist
TABLE
PCI
C C
PCI DEVICE
CARD BUS
LAN
MINI PCI
VGA
B B
TABLE
USB
USB PORT#
0
1
2
3
4
5
A A
6
7
DESTINATION
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
Index and Config.
LA-1711
1
3 65
A00-B
Page 4
5
4
3
2
1
RBAT
D D
ADAPTER
+RTCSRC
+RTC_PWR
+5VALW
+5VSUS
PWR_SRC
+3VALW+3.3VRTC
+3VSUS
BATTERY
SUSPWROK
DOCK _PWR_SRC
C C
+5VSUS
B B
+5VHDD
+5VMOD
+5VRUN
VDDA
+3VRUN +3VSUS+1.5VRUN
+3VSRC
+2.5VMEMP
+2.5V_MEM
+VCCP
V_1P25V_DDR_VTTV3P3LAN
+VCC_CORE
+12V
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Power Rail
LA-1711
1
4 65Wednesday, January 28, 2004
A00-B
Page 5
5
4
3
2
1
ICH_SMBCLK
D D
ICH5
ICH_SMBDATA
+3VSUS
7002
+3VRUN
CK_SCLK
CK_SDATA
CLK GEN.
7002
V_3P3_LAN
DIMM1
7002
7002
7002
7002
7002
CLK_SMB
DIMM0
+3VALW
DAT_SMB
7002
C C
24C05
SIO
Macallen
SBAT_SMBCLK
SBAT_SMBDAT
B B
ADT7460
AD7414 PCA9561
+5VALW
DH PORT
EC SMBus Address
CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)
DDR Temp.(AD7414ART-0) : 90h/91h (P.15)
CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)
EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)
VID Select(PCA9561PW) : 9Ch/9Dh (P.38)
VGA
LAN_SMBCLK
LAN_SMBDATA
NIC
MPCI
PBAT_SMBCLK
1'nd
PBAT_SMBDAT
+5VALW
BATTERY
CHARGER
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
SMBUS TOPOLOGY
Wednesday, January 28, 2004
LA-1711
1
65
5
A00-B
Page 6
+3VRUN
5
4
3
2
1
12
R529
D D
1K_0603_1%~D
12
R530
2K_0603_1%~D
12
R214
2.49K_0603_1%~D
SL0 SL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot
0 0 100 66 14.3 14.3 100/200
C C
0 MID REF REF REF REF REF
0 1 200
1 0 133 66 14.3
1 1 166
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
B B
ICH_SMBDATA
A A
ICH_SMBCLK
+3VRUN
12
R518
1K_0603_1%~D
CLKSEL0
CLKSEL1
12
R519
2K_0603_1%~D
12
R208
2.49K_0603_1%~D
66 14.3 100/200 48
R215 0_0402_5%~D@
12
R206 0_0402_5%~D
12
R508 0_0402_5%~D
12
R509 0_0402_5%~D@
12
14.3
14.3
66 14.3 100/2004848
ICH_SMBDATA
+3VRUN
12
R192
1K_0603_1%~D
H_STP_PCI#
+3VRUN
12
R218
1K_0603_1%~D@
ICH_SLP_S1#
+3VRUN
100K_0402_5%~D
D
1 3
2
2
1 3
D
D
1
14.3
12
R524
S
Q68
2N7002_SOT23~D
G
G
Q69
2N7002_SOT23~D
S
3G
S2
MCH_CLKSEL0
MCH_CLKSEL1
100/200
12
48
REF
R536
100K_0402_5%~D
CK_SDATA
CK_SCLKICH_SMBCLK
CPU_CLKSEL0
CPU_CLKSEL1
Bring Up: Populate R509 (Because CPU
is Northwood-MT, Frequency 533MHz)
CK_14M_ICH
CK_14M_SIO
CK_14M_CODEC
Close to X'tal pin
Place near CK409
CK_100M_ICH#
CK_100M_ICH
Check SPEC (250mA,300 ohm)
+3VRUN
CK_XTAL_IN and CK_XTAL_OUT equal length traces,
Please place R_J between Pins 4,5 of CK409 Pins
before X'tal
R538
12
33_0402_5%~D
R539
12
33_0402_5%~D
R611
12
24_0402_5%
C597
22P_0402_50V8J~D
12
X6
14.31818MHz_20P_1BX14318CC1A~D
12
C598
22P_0402_50V8J~D
R479
1 2
49.9_0402_1%~D
1 2
49.9_0402_1%~D
CK_48M_ICH
CK_48M_SCR
L45
BLM11A601S_0603~D
1 2
12
R478
CK_XTAL_OUT
Place crystal within
500 mils of CK409
ICH_SLP_S1#
CLK_STP_CPU#
CK_VTT_PG#
R485
1 2
33_0402_5%~D
R484
1 2
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
CLK_VDD_PLL
1
C166
10U_1206_6.3V7K~D
2
ICH_SLP_S1#
CLK_STP_CPU#
CK_VTT_PG#
R501
R500
1
C550
0.1U_0402_16V4Z~D
2
BLM21PG600SN1D_0805~D
CLKREF1
CLKREF0
CK_XTAL_IN
R548
2M_0603_5%~D @
1 2
R629 0_0402_5%~D
CLKSEL0
CLKSEL1
CK_SCLK
CK_SDATA
CK_SATA#
CK_SATA
CLK48M_OUT0
12
CLK48M_OUT1
12
R199
1 2
475_0603_1%~D
L17
1 2
10U_1206_6.3V7K~D
12
R_J
2N7002
5
4
CK_VDD_MAIN+3VRUN
2
1
C586
0.1U_0402_10V6K~D
1
2
24
16
3
VDD_PCI10VDD_PCI
VDD_REF
VDD_3V66
CK409
VSS_REF
VSS_PCI11VSS_PCI
VSS_3V66
6
17
25
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
2
4
5
51
56
21
49
50
35
28
30
37
38
31
32
52
55
54
3
C204
U39
REF_1
REF_0
XTAL_IN
XTAL_OUT
SEL0
SEL1
PWRDWN#
PCI_STP#
CPU_STP#
VTT_PWRGD#
SCLK
SDATA
SRCLKN_100MHZ
SRCLKP_100MHZ
USB_48MHZ
DOT_48MHZ
IREF
VDD_PLL
VSS_PLL
Place near each pin
W>40 mil
1
C587
0.1U_0402_10V6K~D
2
36
42
48
34
VDD_48
VSS_CPU
VDD_SRC
VDD_CPU
VDD_CPU
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
48/66MHZ_OUT/3V66_4
66MHZ_OUT3/3V66_3
66MHZ_OUT2/3V66_2
66MHZ_OUT1/3V66_1
66MHZ_OUT0/3V66_0
PCICLK_F2
PCICLK_F1
PCICLK_F0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
VSS_48
VSS_SRC
VSS_IREF
CY28409ZCT_TSSOP56~D
33
39
53
1
C553
2
45
47
46
44
43
41
40
29
27
26
23
22
9
8
7
20
19
18
15
14
13
12
1
C585
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
CK_CPU2
CK_CPU2#
CK_CPU1
CK_CPU1#
CK_CPU0H_STP_PCI#
CK_CPU0#
CLK66M_OUT3
CLK66M_OUT1
CLK66M_OUT0
PCICLK_F2
PCICLK6
PCICLK5
PCICLK2
PCICLK1
PCICLK0
1
C554
0.1U_0402_10V6K~D
2
1
C193
4.7U_0805_6.3V6K~D
2
1 2
1 2
1 2
1 2
1 2
1 2
R543
1 2
33_0402_5%~D
R547
1 2
33_0402_5%~D
R546
1 2
33_0402_5%~D
R540
1 2
33_0402_5%~D
R545
1 2
33_0402_5%~D
R542
1 2
33_0402_5%~D
R541
1 2
33_0402_5%~D
R544
1 2
33_0402_5%~D
1 2
R587 33_0402_5%~D
2
Trace wide=20 mils
1
C552
0.1U_0402_10V6K~D
2
R488
33_0402_5%~D
R472
1 2
49.9_0402_1%~D
R473
1 2
49.9_0402_1%~D
R489
33_0402_5%~D
R490
33_0402_5%~D
R474
1 2
49.9_0402_1%~D
R475
1 2
49.9_0402_1%~D
R491
33_0402_5%~D
R492
33_0402_5%~D
R476
1 2
49.9_0402_1%~D
R477
1 2
49.9_0402_1%~D
R493
33_0402_5%~D
1
C551
0.1U_0402_10V6K~D
2
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CK_HCLK
1
C588
0.1U_0402_10V6K~D
2
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CK_HCLK
Place near CK409
CK_HCLK#
Title
Size Document Number Rev
Date: Sheet of
CK_HCLK#
CK_66M_AGP
CK_66M_MCH
CK_66M_ICH
CK_33M_ICHPCI
CK_33M_MINIPCI
CK_33M_CBPCI
CK_33M_LANPCI
CK_33M_SIOPCI
CK_33M_CPLD
DELL CONFIDENTIAL/PROPRIETARY
Clock Generator
LA-1711
1
6 65Wednesday, January 28, 2004
A00-B
Page 7
5
4
+VCC_CORE
3
2
1
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C C
H_REQ#[0..4]
H_ADS#
R339
62_0402_5%@
R371
1 2
1 2
H_BR0#
H_BPRI#
H_BNR#
H_LOCK#
CK_BCLK
CK_BCLK#
H_HIT#
H_HITM#
H_DEFER#
+VCC_CORE
+VCC_CORE
B B
200_0402_5%
CK_BCLK
CK_BCLK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
AMP_3-1565030-1_Prescott~D
AF22
AF23
A10
A12
JCPUA
VCC_0
VCC_1
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
BCLK0
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
A14
A16
A18
VCC_2
VCC_3
VSS_0H1VSS_1H4VSS_2
H23
A20
VCC_4
H26
VCC_5
VSS_3
A11
AA10
AA12
VCC_6A8VCC_7
VSS_4
VSS_5
A13
A15
AA14
VCC_8
VSS_6
A17
AA16
VCC_9
VSS_7
A19
AA18
VCC_10
VCC_11
VSS_8
VSS_9
A21
AA8
VCC_12
VSS_10
A24
AB11
AB13
VCC_13
VCC_14
VSS_11
VSS_12A3VSS_13A9VSS_14
A26
AB15
VCC_15
AB17
AB19
VCC_16
AA1
AA11
AB7
VCC_17
VCC_18
VSS_15
VSS_16
AA13
AB9
VCC_19
VSS_17
AA15
AC10
VCC_20
VSS_18
AA17
AC12
VCC_21
VSS_19
AA19
AC14
VCC_22
VSS_20
AA23
AC16
AC18
VCC_23
VSS_21
AA4
AA26
AC8
VCC_24
VCC_25
VSS_22
VSS_23
AA7
AD11
VCC_26
VSS_24
AA9
AD13
VCC_27
VSS_25
AB10
AD15
VCC_28
VSS_26
AB12
AD17
VCC_29
VSS_27
AB14
AD19
AB16
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
Prescott
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
AB3
AB6
AB8
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AF15
VCC_42
VCC_43
VSS_40
VSS_41
AC2
AF17
VCC_44
VSS_42
AC22
AF19
VCC_45
VSS_43
AC25
AF2
VCC_46
VSS_44
AC5
AF21
VCC_47
VSS_45
AC7
AF5
VCC_48
VSS_46
AC9
AF7
VCC_49
VSS_47
AD10
AF9
VCC_50
VSS_48
AD12
B11
VCC_51
VSS_49
AD14
B13
VCC_52
VSS_50
AD16
B15
VCC_53
VSS_51
AD18
B17
B19
VCC_54
VSS_52
AD21
AD23
VCC_55
VCC_56B7VCC_57B9VCC_58
VSS_53
VSS_54
VSS_55
AD4
AD8
C10
C12
C14
VCC_59
VCC_61
BOOTSELECT
AD1
C16
VCC_62
VCC_81
F13
C18
VCC_63
VCC_82
F15
C20
VCC_64
VCC_83
F17
F19
D11
D13
VCC_65C8VCC_66
VCC_67
VCC_84
VCC_85
F9
F11
D15
VCC_68
VCC_79E8VCC_80
D17
VCC_69
VCC_78
E20
D19
VCC_70
VCC_77
E18
D9
VCC_71D7VCC_72
VCC_75
VCC_76
E14
E16
E10
VCC_73
VCC_74
E12
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
H_D#0
B21
D#0
H_D#1
B22
D#1
H_D#2
A23
D#2
H_D#3
A25
D#3
H_D#4
C21
D#4
H_D#5
D22
D#5
H_D#6
B24
D#6
H_D#7
C23
D#7
H_D#8
C24
D#8
H_D#9
B25
D#9
H_D#10
G22
H_D#11
H21
H_D#12
C26
H_D#13
D23
H_D#14
J21
H_D#15
D25
H_D#16
H22
H_D#17
E24
H_D#18
G23
H_D#19
F23
H_D#20
F24
H_D#21
E25
H_D#22
F26
H_D#23
D26
H_D#24
L21
H_D#25
G26
H_D#26
H24
H_D#27
M21
H_D#28
L22
H_D#29
J24
H_D#30
K23
H_D#31
H25
H_D#32
M23
H_D#33
N22
H_D#34
P21
H_D#35
M24
H_D#36
N23
H_D#37
M26
H_D#38
N26
H_D#39
N25
H_D#40
R21
H_D#41
P24
H_D#42
R25
H_D#43
R24
H_D#44
T26
H_D#45
T25
H_D#46
T22
H_D#47
T23
H_D#48
U26
H_D#49
U24
H_D#50
U23
H_D#51
V25
H_D#52
U21
H_D#53
V22
H_D#54
V24
H_D#55
W26
H_D#56
Y26
H_D#57
W25
H_D#58
Y23
H_D#59
Y24
H_D#60
Y21
H_D#61
AA25
H_D#62
AA22
H_D#63
AA24
H_D#[0..63]H_A#[3..31]
+VCC_CORE
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
AD20 VCCA VCCIOPLLConnect to CPU
AF23 Connect to CPU
VCCIOPLL VCCA VCCIOPLL
TESTHI12 TESTHI12AD25 DPSLP
Comment Comment
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Filter
Pull-up 200ohm
to +VCC_CORE
5
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
to +VCC_CORE
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
float
COMPAT#
Pull-up 62ohm
to +VCC_CORE
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VSSAE26 VSS Connect to GND OPTIMIZED/
Comment
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
float
float
float
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to PLD
through 0ohm
4
Northwood
Prescott
Northwood
MT
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
DepopPop
Pop Pop
Pop
Pop
Pop
Pop
Depop
Note: AD2,AD3 pop(bring up)
Depop
Depop
Pop
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCORE_BOOTSELECT
DELL CONFIDENTIAL/PROPRIETARY
Title
Prescott Processor in uFCPGA478
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
A00-B
7 65Wednesday, January 28, 2004
Page 8
5
+VCC_CORE
+VCC_CORE
CK_ITP_CPU
14
CK_ITP_CPU#
23
CK_ITP_JITP#
14
CK_ITP_JITP
23
Place near ICH
Place near CPU
1
+
2
ITP_TDO
+VCC_CORE
Pop: Prescott
Depop: Northwood
H_RS#[0..2]
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PWRGOOD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
CPU_CLKSEL0
CPU_CLKSEL1
H_THERMDA
H_THERMDC
H_THERMTRIP#
R338 62_0402_5%
1 2
R341 62_0402_5%
1 2
R337 62_0402_5%
1 2
R346 62_0402_5%
1 2
R343 62_0402_5%
1 2
R342 62_0402_5%
1 2
C368
33U_D2_8M_R35~D
H_RESET#
47_0402_5%~D
R370 27.4_0603_1%~D
0.1U_0402_10V6K~D
150_0402_5%~D
1 2
R364
1 2
1 2
1 2
R376
39.2_0603_1%~D
+VCCVID
R361
Close to the ITP
H_VCCA
H_VSSA
C386
VCCSENSE
VSSSENSE
R_D
R97
61.9_0603_1%
+VCC_CORE
1
2
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CK_ITP_JITP
CK_ITP_JITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
R131 62_0402_5%
R129 62_0402_5%
D D
R84 62_0402_5%@
C C
B B
+VCC_CORE
H_FERR#
1 2
H_THERMTRIP#
1 2
R111 130_0402_5%
H_PROCHOT#
1 2
R87 300_0402_5%~D
H_PWRGOOD
1 2
H_RESET#
1 2
10uH, DC current of 100mA parts
and close to cap
+VCC_CORE
L40 10U_LQH31MN100K01_100mA_10%_1206~D
1 2
1 2
L41 10U_LQH31MN100K01_100mA_10%_1206~D
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
CK_ITP
CK_ITP#
0_4P2R_0404_5%~D
CK_ITP#
CK_ITP#
CK_ITP
CK_ITP
R363
54.9_0603_1%~D
1 2
R358
54.9_0603_1%~D
1 2
0_4P2R_0404_5%~D @
ITP_TDO
H_RESET#
RN9
RN8
Close to the ITP
+VCC_CORE
R377
47_0402_5%~D@
R108 150_0402_5%~D
A A
1 2
R379 47_0402_5%~D @
680_0402_5%~D
1 2
Between the CPU and ITP
12
12
Close to the CPU
R381
ITP_TMS
ITP_TDI
ITP_TCK
ITP_TRST#
5
R333
H_FERR#
H_PWRGOOD
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
1 2
CK_ITP_CPU
CK_ITP_CPU#
12
4
H_RS#0
H_RS#1
H_RS#2
F1
G5
F4
AB2
J6
C6
B6
B2
B5
AB23
Y4
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
AE23
A5
A4
AF3
0_0402_5%~D
AD22
AC26
AD26
L24
P1
12
R349
61.9_0603_1%
AMP_3-1565030-1_Prescott~D
29
JITP
28
VTT1
27
GND6
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
30
4
JCPUB
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
MOLEX_52435-2891_28P~D@
AE11
VSS_57
VSS_129F8VSS_130
+3VSUS
VID_PWRGD
AE13
VSS_58
G21
AE15
AE17
VSS_59
VSS_131
G24
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_132G3VSS_133G6VSS_134J2VSS_135
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
J22
J25
K21
K24
R152
1 2
10K_0402_5%~D
3
Level shift
+CPU_GMCH_GTLREF trace
wide 12mils(min),Space
15mils
AF18
AF20
AF6
AF8
B10
B12
B14
B16
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
L23
L26
N21
M22
M25
+3VSUS
5
U6A
P
1
G
SN74LVC2G07DBVR_SOT23-6~D
2
+3VSUS
5
U6B
P
O4I
G
SN74LVC2G07DBVR_SOT23-6~D
2
+CPU_GMCH_GTLREF
B18
B20
B23
VSS_80
VSS_81
VSS_82
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
N24
1 2
O6I
3
B26
C11
C13
C15
C17
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
Prescott
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
P22
P25
R23
R26
C131
0.1U_0402_16V4Z~D
H_VID_PWRGD
R155 8.2K_0402_5%~D
1 2
3
2
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
F10
F12
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
VSS_121
VID0
VID1
VID2
VID3
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
T21
T24
V23
V26
U22
U25
+3VSUS
C121
1 2
1U_0603_6.3V6M~D
+VCC_CORE
R_A
R_B
VCORE_ENLL
12
R357
200_0603_1%~D
12
R356
169_0603_1%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Y5
Y22
Y25
W21
W24
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
GTL Reference Voltage
Layout note :
2
C369
0.1U_0402_16V4Z~D
1
VID4
VSS_181
VID5
AE5
AE4
AE3
AE2
AE1
AD3
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
12
R340
0_0603_5%~D
1
2
F14
F16
F18
F22
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VIDPWRGD
AD2
C372
220P_0402_50V7K
AF26
F25
F5
VSS_127
VSS_128
SKTOCC#
GTLREF0
GTLREF1
GTLREF2
GTLREF3
OPTIMIZED/COMPAT#
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
PROCHOT#
VCCVID
AF4
+VCCVID
H_VID_PWRGD
2
DP#0
DP#1
DP#2
DP#3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
MCERR#
SLP#
R71
1 2
0_0402_5%~D
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
R_E
R336
681_0603_1%
1 2
2
2
1
1
@
T1
PAD@
R70 0_0402_5%~D@
1 2
H_TESTHI0
H_TESTHI1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
RE
Pop: Prescott
Depop: Northwood
+VCCVID
VID5
VID4
VID3
VID2
VID1
VID0
B_VID5
OPEN
@
1
+VCC_CORE
R76
200_0402_5%@
R78 0_0402_5%~D@
1 2
+VCC_CORE
RH
Pop: Prescott
Depop: Northwood MT
CPLD Enable
Pop R380
Closely Pin AE25
C660
12
1000P_0402_50V7K~D@
+VCC_CORE
R37 1K_0402_5%~D
R35 1K_0402_5%~D
B_VID2
OPEN
2
1
@
LA-1711
1
CPLD Enable
Pop R76, R78
H_DPSLP#
CPUPREF#
H_PROCHOT#
1 2
1 2
45
36
27
18
RN7 1K_8P4R_1206_5%~D
B_VID0
B_VID1
OPEN
OPEN
2
2
2
1
1
1
@
8 65Wednesday, January 28, 2004
12
DPSLP#
+CPU_GTLREF
Pop: Northwood
R_G
R77 62_0402_5%
R344 62_0402_5%
R82 62_0402_5%
R354 62_0402_5%
R350 62_0402_5%
R347 62_0402_5%
R382 62_0402_5%
R79 62_0402_5%
ITP_DBRESET#
H_CPUSLP#
R83 62_0402_5%@
1 2
B_VID4
OPEN
2
2
1
1
@
Title
Size Document Number Rev
Date: Sheet of
Depop: Prescott
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R_H
R380 0_0402_5%~D@
1 2
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
VID5
VID4
VID3
VID2
VID1
VID0
B_VID3
OPEN
2
2
2
2
1
1
1
1
@
DELL CONFIDENTIAL/PROPRIETARY
Prescott Processor in uFCPGA478
+3VRUN
A00-B
Page 9
5
4
3
2
1
+VCC_CORE
1
C31
22U_1206_6.3VAM~D
2
D D
+VCC_CORE
1
C46
22U_1206_6.3VAM~D
@
2
+VCC_CORE
1
C381
22U_1206_6.3VAM~D
2
C C
+VCC_CORE
1
C76
22U_1206_6.3VAM~D
@
2
1
C27
22U_1206_6.3VAM~D
@
2
1
C56
22U_1206_6.3VAM~D
@
2
1
C411
22U_1206_6.3VAM~D
2
1
C71
22U_1206_6.3VAM~D
2
1
C28
22U_1206_6.3VAM~D
2
1
C55
22U_1206_6.3VAM~D
@
2
1
C72
22U_1206_6.3VAM~D
2
Place 11 North of Socket(Stuff 6)
1
C29
22U_1206_6.3VAM~D
2
1
C32
22U_1206_6.3VAM~D @
2
Place 12 Inside Socket(Stuff all)
1
C45
22U_1206_6.3VAM~D
@
2
1
C394
22U_1206_6.3VAM~D
2
Place 9 South of Socket(Unstuff all)
1
C75
22U_1206_6.3VAM~D
@
2
1
C69
22U_1206_6.3VAM~D
@
2
1
C30
22U_1206_6.3VAM~D
2
1
C403
22U_1206_6.3VAM~D
2
1
C70
22U_1206_6.3VAM~D
@
2
1
C77
22U_1206_6.3VAM~D
2
1
C404
22U_1206_6.3VAM~D
2
1
C73
22U_1206_6.3VAM~D
@
2
1
C331
22U_1206_6.3VAM~D
2
22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)
1
C412
22U_1206_6.3VAM~D
2
1
2
C74
22U_1206_6.3VAM~D
@
1
C395
22U_1206_6.3VAM~D
2
1
C382
22U_1206_6.3VAM~D
2
Note:For PT-phase
22uF depop reference
Springdale Chipset Platform Design Guide Rev1.2(12837)
Inside the socket cavity 12 pcs (all stuffed)
North side 12pcs (4 sites stuffed)
Delete south side
B B
+VCC_CORE
1
+
C303
@
330U_D_2VM~D
2
+VCC_CORE
1
+
C299
330U_D_2VM~D
@
2
+VCC_CORE
A A
1
+
C68
330U_D_2VM~D
2
1
+
2
1
+
2
1
+
C423
330U_D_2VM~D
@
2
5
470uF _ERS10m ohm* 15, ESR=0.5m ohm
330uF _ERS7m ohm* 8, ESR=0.875m ohm
1
C302
330U_D_2VM~D
C294
330U_D_2VM~D
+
2
1
+
2
1
+
C422
330U_D_2VM~D
2
C304
330U_D_2VM~D
C298
330U_D_2VM~D
1
+
C301
330U_D_2VM~D @
2
1
+
C296
330U_D_2VM~D
2
Per Dell power team test, used Panasonic 330U_2V ESR
7m ohm * 8 (Implement on PT phase X02)
1
+
C300
330U_D_2VM~D
2
1
+
C295
330U_D_2VM~D
@
2
4
1
+
C305
330U_D_2VM~D
@
2
1
+
C297
330U_D_2VM~D
@
2
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239
Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
CPU Decoupling
LA-1711
1
9 65Wednesday, January 28, 2004
A00-B
Page 10
5
4
3
2
1
H_A#[3..31]
D D
H_REQ#[0..4]
H_ADSTB#0
C C
H_RS#[0..2] MCH_CLKSEL0
B B
+VTT_GMCH
12
R331
301_0402_1%~D
12
R332
102_0402_1%~D
A A
12
R335
20_0603_1%~D
H_ADSTB#1
CK_HCLK
CK_HCLK#
H_DSTBP#0
H_DSTBN#0
H_DINV#0
H_DSTBP#1
H_DSTBN#1
H_DINV#1
H_DSTBP#2
H_DSTBN#2
H_DINV#2
H_DSTBP#3
H_DSTBN#3
H_DINV#3
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
+GMCH_GTLREF
Follow Intel design guide R1.11(12474) page80
Trace width 12mils,Space
10mils
HD_SWING
HDRCOMP
1
C365
0.01U_0402_16V7K~D
2
Trace width 10mils,Space
7mils
H_RESET#
PWRGD_3V
HDRCOMP
HD_SWING
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
U3A
D26
HA3#
D30
HA4#
L23
HA5#
E29
HA6#
B32
HA7#
K23
HA8#
C30
HA9#
C31
HA10#
J25
HA11#
B31
HA12#
E30
HA13#
B33
HA14#
J24
HA15#
F25
HA16#
D34
HA17#
C32
HA18#
F28
HA19#
C34
HA20#
J27
HA21#
G27
HA22#
F29
HA23#
E28
HA24#
H27
HA25#
K24
HA26#
E32
HA27#
F31
HA28#
G30
HA29#
J26
HA30#
G26
HA31#
B29
HREQ0#
J23
HREQ1#
L22
HREQ2#
C29
HREQ3#
J21
HREQ4#
B30
HADSTB0#
D28
HADSTB1#
B7
HCLKP
C7
B19
C19
C17
L19
K19
L17
G9
F9
L14
D12
E12
C15
F27
D24
G24
L21
E23
K21
E25
B24
B28
B26
E27
G22
C27
B27
E8
AE14
E24
C25
F23
RG828SDGES_FCBGA932_SPRINGDALE~D
HCLKN
HDSTBP0#
HDSTBN0#
DINV0#
HDSTBP1#
HDSTBN1#
DINV1#
HDSTBP2#
HDSTBN2#
DINV2#
HDSTBP3#
HDSTBN3#
DINV3#
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS0#
RS1#
RS2#
CPURST#
PWROK#
HDRCOMP
HDSWING
HDVREF
FSB
PROCHOT#
+CPU_GMCH_GTLREF
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
BSEL0
BSEL1
B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8
L20
L13
L12
R329
0_0603_5%~D
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R608
1 2
0_0402_5%~D
+VTT_GMCH
12
12
R323
200_0603_1%~D
H_D#[0..63]
PROCHOT_GATE PROCHOT_GATE
H_PROCHOT#
MCH_CLKSEL1
GTL Reference Voltage
Layout note :
1. +GMCH_GTLREF Trace wide
12mils(min),Space 15mils.
2. Place decoupling cap 220PF near GMCH.
+GMCH_GTLREF
MMBT3904_SOT23~D@
1
C366
220P_0402_50V7K
2
Create
2
Q76
31
+3VRUN
12
Q24
MMBT3904_SOT23~D
3 1
OVP_AC_ADAPT#
R90
1.24K_0402_1%~D
2
H_PROCHOT#
R605
1 2
0_0402_5%~D@
H_PROCHOT_SIO#
R91 10K_0402_5%~D
1 2
C670
12
100P_0402_50V8J~D
H_PROCHOT#
VCORE_PHOT#
+VCC_CORE
U3F
AR32
VSS
AR29
VSS
AR27
VSS
AR25
VSS
AR23
VSS
AR20
VSS
AR16
VSS
AR13
VSS
AR11
VSS
AR9
VSS
AN32
VSS
AN30
VSS
AN28
VSS
AN26
VSS
AN24
VSS
AN22
VSS
AN20
VSS
AN18
VSS
AN16
VSS
AN14
VSS
AN12
VSS
AN10
VSS
AM35
VSS
AM29
VSS
AM27
VSS
AM25
VSS
AM23
VSS
AM21
VSS
AM19
VSS
AM17
VSS
AM15
VSS
AM13
VSS
AM11
VSS
AM9
VSS
AL32
VSS
AL1
VSS
AK28
VSS
AK26
VSS
AK24
VSS
AK22
VSS
AK20
VSS
AK18
VSS
AK16
VSS
AK14
VSS
AK12
VSS
AK10
VSS
AK8
VSS
AK3
VSS
AJ35
VSS
AJ32
VSS
AJ9
VSS
AJ4
VSS
AJ1
VSS
AH33
VSS
AH30
VSS
AH24
VSS
AH22
VSS
AH20
VSS
AH18
VSS
AH16
VSS
AH14
VSS
AH12
VSS
AH10
VSS
AH6
VSS
AH3
VSS
AG35
VSS
AG32
VSS
AG28
VSS
AG26
VSS
AG24
VSS
AG22
VSS
AG20
VSS
AG18
VSS
AG16
VSS
AG14
VSS
AG8
VSS
AG4
VSS
AF33
VSS
AF30
VSS
AF25
VSS
AF24
VSS
AF22
VSS
AF20
VSS
AF18
VSS
AF16
VSS
AF14
VSS
AF11
VSS
AF9
VSS
AF6
VSS
AF3
VSS
AE35
VSS
AE32
VSS
AE26
VSS
AE25
VSS
AE13
VSS
AE12
VSS
RG828SDGES_FCBGA932_SPRINGDALE~D
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE11
AE10
AE4
AE1
AD33
AD30
AD28
AD10
AD9
AD8
AD6
AD3
AC35
AC32
AC4
AC1
AB33
AB30
AB28
AB27
AB26
AB10
AB9
AB8
AB6
AB3
AA32
AA4
AA1
Y35
Y33
Y30
Y28
Y27
Y26
Y10
Y9
Y8
Y6
Y3
W32
W18
W17
W4
V33
V30
V28
V27
V26
V19
V17
V10
V9
V8
V6
V3
U32
U19
U18
U4
T35
T33
T30
T28
T27
T26
T10
T9
T8
T6
T3
T1
R32
R4
R1
P33
P30
P28
P27
P26
P9
P8
P6
P3
N35
N32
N4
N1
M33
M30
M28
M27
M26
M6
M3
L35
U3G
L31
VSS
L26
VSS
L25
VSS
L24
VSS
K33
VSS
K29
VSS
K27
VSS
K25
VSS
K22
VSS
K20
VSS
K18
VSS
K16
VSS
K14
VSS
K12
VSS
K11
VSS
J35
VSS
J32
VSS
J28
VSS
J22
VSS
J20
VSS
J18
VSS
J16
VSS
J14
VSS
J12
VSS
J10
VSS
H33
VSS
H30
VSS
H26
VSS
H24
VSS
H22
VSS
H20
VSS
H18
VSS
H16
VSS
H14
VSS
H12
VSS
H9
VSS
H8
VSS
H5
VSS
H2
VSS
G35
VSS
G31
VSS
G28
VSS
F26
VSS
F24
VSS
F22
VSS
F20
VSS
F18
VSS
RG828SDGES_FCBGA932_SPRINGDALE~D
GND
F16
VSS
F14
VSS
F12
VSS
F10
VSS
F8
VSS
F5
VSS
F3
VSS
F1
VSS
E3
VSS
E1
VSS
D35
VSS
D33
VSS
D31
VSS
D29
VSS
D27
VSS
D25
VSS
D23
VSS
D21
VSS
D19
VSS
D17
VSS
D15
VSS
D13
VSS
D11
VSS
D9
VSS
D1
VSS
C28
VSS
C26
VSS
C24
VSS
C22
VSS
C20
VSS
C18
VSS
C16
VSS
C14
VSS
C12
VSS
C10
VSS
C8
VSS
C4
VSS
A32
VSS
A29
VSS
A27
VSS
A25
VSS
A23
VSS
A20
VSS
A16
VSS
A13
VSS
A11
VSS
A9
VSS
A7
VSS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Springdale-Host/GND
LA-1711
1
10 65Wednesday, January 28, 2004
A00-B
Page 11
5
4
3
2
1
DDRA_SDQ[0..63]
DDRA_SMA[0..12]
D D
C C
SM_VREF_A
SM_VREF_A trace width of 12mils and space
12mils(min)
2
C48
2.2U_0805_16VFZ~D
1
2
C47
0.1U_0402_16V4Z~D
1
Close to GMCH
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
B B
2
C64
2.2U_0805_16VFZ~D
1
A A
Follow Intel design guide
R1.11(12474) page124,125
12
R372
42.2_0603_1%~D
SMXRCOMP
12
R367
42.2_0603_1%~D
2
C65
2.2U_0805_16VFZ~D
1
5
DDRA_SMA[0..12]
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS0
DDRA_SBS1
DDRA_SCS#0
DDRA_SCS#1
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK2
DDRA_CLK2#
1
C637
0.01U_0402_16V7K~D
2
1
C406
1U_0603_6.3V6M~D
2
U3B
AJ34
SMAA_A0
AL33
SMAA_A1
AK29
SMAA_A2
AN31
SMAA_A3
AL30
SMAA_A4
AL26
SMAA_A5
AL28
SMAA_A6
AN25
SMAA_A7
AP26
SMAA_A8
AP24
SMAA_A9
AJ33
SMAA_A10
AN23
SMAA_A11
AN21
SMAA_A12
AL34
SMAB_A1
AM34
SMAB_A2
AP32
SMAB_A3
AP31
SMAB_A4
AM26
SMAB_A5
AB34
SWE_A#
Y34
SCAS_A#
AC33
SRAS_A#
AE33
SBA_A0
AH34
SBA_A1
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AL20
AN19
AM20
AP20
AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32
E34
AK9
AN9
AL9
Trace width of 12mils and space
10mils(min)
1
2
DDR Channel A
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCMDCLK_A0
SCMDCLK_A0#
SCMDCLK_A1
SCMDCLK_A1#
SCMDCLK_A2
SCMDCLK_A2#
SCMDCLK_A3
SCMDCLK_A3#
SCMDCLK_A4
SCMDCLK_A4#
SCMDCLK_A5
SCMDCLK_A5#
SMVREF_A
SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL
RG828SDGES_FCBGA932_SPRINGDALE~D
C400
0.01U_0402_16V7K~D
SDQS_A0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQS_A1
SDM_A1
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQS_A2
SDM_A2
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQS_A3
SDM_A3
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQS_A4
SDM_A4
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQS_A5
SDM_A5
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQS_A6
SDM_A6
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQS_A7
SDM_A7
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13
AP15
AP16
AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18
AP23
AM24
AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27
AM30
AP30
AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34
AF34
AF31
AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34
V34
W33
AC34
AB31
V32
V31
AD31
AB32
U34
U33
M32
M34
T34
T32
K34
K32
T31
P34
L34
L33
H31
H32
J33
H34
E33
F33
K31
J34
G34
F34
2
C63
2.2U_0805_16VFZ~D
1
1
C407
1U_0603_6.3V6M~D
2
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL
+2.5V_MEM
12
12
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SCS#0
DDRA_SCS#1
DDRA_CKE0
DDRA_CKE1
R374
10K_0603_1%~D
SMXRCOMPVOH
R369
30.9K_0603_1%~D
*
Close to GMCH <1" Close to GMCH <1"
Note: Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K
4
DDRA_SDQ[0..63]
DDRA_SDQS0
DDRA_SDM0
DDRA_SDQS1
DDRA_SDM1
DDRA_SDQS2
DDRA_SDM2
DDRA_SDQS3
DDRA_SDM3
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQS6
DDRA_SDM6
DDRA_SDQS7
DDRA_SDM7
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R373
30.9K_0603_1%~D
*
SMXRCOMPVOL
12
R368
10K_0603_1%~D
1
2
C401
0.01U_0402_16V7K~D
DDRB_SMA[0..12]
DDRB_SWE#
DDRB_SCAS#
DDRB_SRAS#
DDRB_SBS0
DDRB_SBS1
DDRB_SCS#0
DDRB_SCS#1
DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CLK2
DDRB_CLK2#
SM_VREF_B
SM_VREF_B trace width of
12mils and space
12mils(min)
2
C50
0.1U_0402_16V4Z~D
1
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SCS#0
DDRB_SCS#1
DDRB_CKE0
DDRB_CKE1
SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL
+2.5V_MEM
12
12
R104
300_0603_1%~D
R100
300_0603_1%~D
DDRB_SMA[0..12]
2
C62
2.2U_0805_16VFZ~D
1
2
C52
2.2U_0805_16VFZ~D
1
Close to GMCH
+2.5V_MEM
2
12
R110
42.2_0603_1%~D
SMYRCOMP
12
R109
42.2_0603_1%~D
2
C53
2.2U_0805_16VFZ~D
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C66
2.2U_0805_16VFZ~D
1
Trace width of 12mils
and space 10mils(min)
1
C636
0.01U_0402_16V7K~D
2
1
C57
1U_0603_6.3V6M~D
2
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R102
10K_0603_1%~D
SMYRCOMPVOH
12
R101
30.9K_0603_1%~D
*
2
U3C
AG31
SMAA_B0
AJ31
SMAA_B1
AD27
SMAA_B2
AE24
SMAA_B3
AK27
SMAA_B4
AG25
SMAA_B5
AL25
SMAA_B6
AF21
SMAA_B7
AL23
SMAA_B8
AJ22
SMAA_B9
AF29
SMAA_B10
AL21
SMAA_B11
AJ20
SMAA_B12
AE27
SMAB_B1
AD26
SMAB_B2
AL29
SMAB_B3
AL27
SMAB_B4
AE23
SMAB_B5
W27
SWE_B#
W31
SCAS_B#
W26
SRAS_B#
Y25
SBA_B0
AA25
SBA_B1
U26
SCS_B0#
T29
SCS_B1#
V25
SCS_B2#
W25
AK19
AF19
AG19
AE18
AG29
AG30
AF17
AG17
AJ30
AH29
AK15
AL15
AA33
N27
N26
N31
N30
AP9
R34
R33
DDR Channel B
SCS_B3#
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMVREF_B
SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL
RG828SDGES_FCBGA932_SPRINGDALE~D
1
C54
0.01U_0402_16V7K~D
2
SDQS_B0
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQS_B1
SDM_B1
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQS_B2
SDM_B2
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQS_B3
SDM_B3
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQS_B5
SDM_B5
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQS_B6
SDM_B6
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQS_B7
SDM_B7
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
DDRB_SDQ[0..63]
AF15
AG11
AJ10
AE15
AL11
AE16
AL8
AF12
AK11
AG12
AG13
AG15
AE17
AL13
AK17
AL17
AK13
AJ14
AJ16
AJ18
AG21
AE21
AE19
AE20
AG23
AK23
AL19
AK21
AJ24
AE22
AH27
AJ28
AK25
AH26
AG27
AF27
AJ26
AJ27
AD25
AF28
AD29
AC31
AE30
AC27
AC30
Y29
AE31
AB29
AA26
AA27
U30
U31
AA30
W30
U27
T25
AA31
V29
U25
R27
L27
M29
P29
R30
K28
L30
R31
R26
P25
L32
J30
J31
K30
H29
F32
G33
N25
M25
J29
G32
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
2
C59
2.2U_0805_16VFZ~D
1
1
C61
1U_0603_6.3V6M~D
2
DDRB_SDQ[0..63]
DDRB_SDQS0
DDRB_SDM0
DDRB_SDQS1
DDRB_SDM1
DDRB_SDQS2
DDRB_SDM2
DDRB_SDQS3
DDRB_SDM3
DDRB_SDQS4
DDRB_SDM4
DDRB_SDQS5
DDRB_SDM5
DDRB_SDQS6
DDRB_SDM6
DDRB_SDQS7
DDRB_SDM7
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R106
30.9K_0603_1%~D
*
SMYRCOMPVOL
12
R105
10K_0603_1%~D
1
2
Close to GMCH <1" Close to GMCH <1"
DELL CONFIDENTIAL/PROPRIETARY
Title
Springdale-DDR Interface
Size Document Number Rev
Date: Sheet of
LA-1711
1
C58
0.01U_0402_16V7K~D
11 65Wednesday, January 28, 2004
A00-B
Page 12
5
+1.5VRUN
12
R64
43.2_0603_1%~D
GRCOMP
+1.5VRUN
D D
12
R328
52.3_0603_1%~D
HI_RCOMP_MCH
+1.5VRUN
12
R330
226_0603_1%~D
HI_SWING_MCH
12
R68
C C
B B
147_0603_1%~D
12
R69
113_0603_1%
2
C43
0.1U_0402_16V4Z~D
1
2
C360
0.1U_0402_16V4Z~D
1
+1.5VRUN
HI_VREF_MCH
Note:
HI_SWING_MCH, trace width of
12mils and space 10mils
2
C355
0.1U_0402_16V4Z~D
1
2
C41
0.1U_0402_16V4Z~D
1
+1.5VRUN
12
R74
226_0603_1%~D
CI_SWING_GMCH
12
R75
147_0603_1%~D
CI_VREF_GMCH
12
R334
113_0603_1%
AGP8X_DET_GC
1
C364
0.01U_0402_16V7K~D
2
Close to GMCH ball <250mils
1
C42
0.01U_0402_16V7K~D
2
Close to GMCH ball <250mils
Note:
HI_VREF_MCH trace width of
10mils and space 7mils
Note:
CI_SWING_MCH, CI_VREF_MCH
trace width of 12mils and
space 20mils
0.8V
1
C44
0.01U_0402_16V7K~D
2
0.35V
1
C363
0.01U_0402_16V7K~D
2
+1.5VRUN
12
R45
8.2K_0402_5%~D
+12V
2
4
12
R48
8.2K_0402_5%~D
Q10
MMBT3904_SOT23~D
3 1
HUB_HL[0..10]
+1.5VRUN
PCI_PCIRST#
G_C/BE#[0..3]
G_PIPE#_DBI_HI
G_ST[0..2]
HUB_HLSTRF
HUB_HLSTRS
CK_66M_MCH
G_FRAME#
CK_66M_MCH
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_RBF#
G_WBF#
G_DBI_LO
Trace 10mils, space 7mils
52.3_0603_1%~D
R81
1 2
R40
ICH_SYNC#
12
1
@
2
3
GC_DET_REF
13
D
2
G
Q13
2N7002_SOT23~D
S
R55
1 2
39.2_0603_1%~D
Close to VGA Conn.
G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3
CK_66M_MCH G_AD3
G_PAR
GRCOMP
AGP_SWING
VREFGC
G_ST0
G_ST1
G_ST2
HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10
HI_RCOMP_MCH
HI_SWING_MCH
HI_VREF_MCH
CI_SWING_GMCH
CI_VREF_GMCH
0_0402_5%~D
12
1
C680
10P_0402_50V8J~D
@
2
R320
22_0402_5%~D @
C324
10P_0402_50V8J~D
U3D
Y7
GCBE0
W5
GCBE1
AA3
GCBE2
U2
GCBE3
U6
GFRAME
H4
GCLKIN
AB4
GDEVSEL
V11
GIRDY
AD11
AC10
AG10
AN35
AP34
AB5
W11
AB2
AC2
AC3
AD2
R10
AF5
AG3
AK2
AG5
AK5
AL3
AL2
AL4
AJ2
AH2
AJ3
AH5
AH4
AD4
AE3
AE2
AK7
AH7
AF7
AD7
AF8
AG7
AE9
AH9
AG6
AJ6
AJ5
AG2
AF2
AF4
AP8
AJ8
AK4
AG9
AR1
AGP
GTRDY
GSTOP
GPAR/ADD_DETECT
N6
GREQ
M7
GGNT
GRCOMP/DVOBCGCOMP
GVSWING
GVREF
GRBF
R9
GWBF
M4
DBI_HI
M5
DBI_LO
N3
GST0
N5
GST1
N2
GST2
HI0
HI1
HI2
HUB
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HISTRF
HISTRS
HI_RCOMP
HI_SWING
HI_VREF
CI0
CI1
CI2
CI3
CI4
CSA
CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
G4
DREFCLK
EXTTS#
ICH_SYNC#
RSTIN#
RESERVED_1
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5
RG828SDGES_FCBGA932_SPRINGDALE~D
GADSTBF0
GADSTBS0#
GADSTBF1
GADSTBS1#
GSBSTBF
GSBSTBS#
DDCA_DATA
DDCA_CLK
VGA
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#
RED#
GREEN
GREEN#
BLUE
BLUE#
HSYNC
VSYNC
REFSET
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
RED
+1.5VRUN
12
R59
60.4_0603_1%
AGP_SWING
12
R58
39.2_0603_1%~D
1 2
R57 100_0603_1%~D
C385 0.1U_0402_16V4Z~D
AC6
AC5
G_AD0
AE6
G_AD1
AC11
G_AD2
AD5
AE5
G_AD4
AA10
G_AD5
AC9
G_AD6
AB11
G_AD7
AB7
G_AD8
AA9
G_AD9
AA6
G_AD10
AA5
G_AD11
W10
G_AD12
AA11
G_AD13
W6
G_AD14
W9
G_AD15
V7
V4
V5
G_AD16
AA2
G_AD17
Y4
G_AD18
Y2
G_AD19
W2
G_AD20
Y5
G_AD21
V2
G_AD22
W3
G_AD23
U3
G_AD24
T2
G_AD25
T4
G_AD26
T5
G_AD27
R2
G_AD28
P2
G_AD29
P5
G_AD30
P4
G_AD31
M2
U11
T11
G_SBA#0
R6
G_SBA#1
P7
G_SBA#2
R3
G_SBA#3
R5
G_SBA#4
U9
G_SBA#5
U10
G_SBA#6
U5
G_SBA#7
T7
H3
F2
F4
E4
H6
G5
H7
G6
G3
E2
R38
D2
A3
A33
A35
AF13
AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25
Note:
AGP_SWING_MCH, trace width of
12mils and space 10mils
2
C38
0.1U_0402_16V4Z~D
1
VREFCG
12
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
R42
12
R41
12
R39
12
R43
12
R44
12
0_0402_5%~D
12
2
Close GMCH ball less than 250mils
1
C362
0.01U_0402_16V7K~D
2
R66
0_0402_5%~D
12
VREFCG
2
C361
0.01U_0402_16V7K~D
G_AD[0..31]
G_AD[0..31]
G_SBA#[0..7]
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
1
Close GMCH ball
less than
250mils
1
VREFGC
Follow Springdale Chipset Platform Design guide Rev1.11(12474)
Note:
Springdale Customer Schematic R1.2 page18
AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design
guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.
Analog RGB/CRT guidelines for Springdale-P
R61
A A
10K_0402_5%~D@
1 2
G_PAR
1: External AGP
0: Internal Graphics
5
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Springdale-AGP/HUB/VGA/CSA
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
12 65Wednesday, January 28, 2004
A00-B
Page 13
5
D D
0.82uH, DC current of 30mA
+1.5VRUN
C C
B B
parts and close to cap
0.82U_LQM21NNR82K10_150mA_10%_0805~D
VCCA_FSB1 VCCA_FSB
1 2
12
R301
Trace 14mils
0_0603_5%~D
1uH(0.54uH-D-IN), DC current of
1000mA parts and close to cap
+1.5VRUN
1U_LQH32CN1R0M11_1A_20%_1210~D
VCCA_DDR
12
R351
0_0603_5%~D
L34
1 2
Trace 14mils
L42
1
+
C276
100U_D_10VM~D
2
2
1
Trace 50mils, min:35mils on ball field
VCCA1P5_DDR_SM
1
+
C398
100U_D_10VM~D
2
C280
0.1U_0402_16V4Z~D
Close to GMCH
2
C402
0.1U_0402_16V4Z~D
1
Close to GMCH
4
Note:
Placed less than 100 mils from ball
1
C348
0.47U_0603_16V7K~D
2
+VTT_GMCH
2
C414
0.1U_0402_10V6K~D
1
C405 0.1U_0402_10V6K~D
1 2
1 2
C419
0.22U_0603_10V7M~D
C49 0.47U_0603_16V7K~D
1 2
R314
R315
C410
C367 0.1U_0402_10V6K~D
C371 0.1U_0402_10V6K~D
1 2
0.22U_0603_10V7M~D
VCC_AGP_DCAP2
1 2
1 2
0_0402_5%~D
12
0_0402_5%~D
12
1 2
C421 0.1U_0402_10V6K~D
+3VRUN
Trace 14mils
Note:
Placed less than 100 mils from ball
VTT_DCAP1
VTT_DCAP2
1
C356
0.47U_0603_16V7K~D
2
+2.5V_MEM
VCC_DDR_DCAP5
VCC_DDR_DCAP4
VCC_DDR_DCAP1
VTT_DCAP3
VCCA_FSB
VCCA_DPLL
VCCA_DAC
VCC_DDR_DCAP2
VCCA1P5_DDR_SM
3
U3E
A15
VTT
A21
VTT
A4
VTT
A5
VTT
A6
VTT
B5
VTT
B6
VTT
C5
VTT
C6
VTT
D5
VTT
D6
VTT
D7
VTT
E6
VTT
E7
VTT
F7
VTT
AA35
VCC_DDR
AL6
VCC_DDR
AL7
VCC_DDR
AM1
VCC_DDR
AM2
VCC_DDR
AM3
VCC_DDR
AM5
VCC_DDR
AM6
VCC_DDR
AM7
VCC_DDR
AM8
VCC_DDR
AN2
VCC_DDR
AN4
VCC_DDR
AN5
VCC_DDR
AN6
VCC_DDR
AN7
VCC_DDR
AN8
VCC_DDR
AP3
VCC_DDR
AP4
VCC_DDR
AP5
VCC_DDR
AP6
VCC_DDR
AP7
VCC_DDR
AR15
VCC_DDR
AR21
VCC_DDR
AR31
VCC_DDR
AR4
VCC_DDR
AR5
VCC_DDR
AR7
VCC_DDR
E35
VCC_DDR
R35
VCC_DDR
G1
VCC_DAC
G2
VCC_DAC
AG1
VCCA_AGP
+1.5VRUN
Y11
VCCA_AGP
A31
VCCA_FSB
B4
VCCA_FSB
B3
VCCA_DPLL
C2
VCCA_DAC
AL35
VCCA_DDR
AB25
VCCA_DDR
AC25
VCCA_DDR
AC26
VCCA_DDR
RG828SDGES_FCBGA932_SPRINGDALE~D
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page84
POWER
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSSA_DAC
J6
VCC
J7
VCC
J8
VCC
J9
VCC
K6
VCC
K7
VCC
K8
VCC
K9
VCC
L6
VCC
L7
VCC
L9
VCC
L10
VCC
L11
VCC
M8
VCC
M9
VCC
M10
VCC
M11
VCC
N9
VCC
N10
VCC
N11
VCC
P10
VCC
P11
VCC
R11
VCC
T16
VCC
T17
VCC
T18
VCC
T19
VCC
T20
VCC
U16
VCC
U17
VCC
U20
VCC
V16
VCC
V18
VCC
V20
VCC
W16
VCC
W19
VCC
W20
VCC
Y16
VCC
Y17
VCC
Y18
VCC
Y19
VCC
Y20
VCC
J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5
Y1
D3
+1.5VRUN
VCC_AGP_DCAP1
2
1
C391
0.1U_0402_10V6K~D@
2
1
C378
0.1U_0402_10V6K~D@
2
+1.5VRUN
1
C358
0.1U_0402_10V6K~D
2
Place near ball
Y11,routing trace
from cap to ball
+1.5VRUN
1
2
+1.5VRUN
1
2
+1.5VRUN
1
2
1
C390
0.1U_0402_10V6K~D@
2
1
C373
0.1U_0402_10V6K~D@
2
C387
0.1U_0402_10V6K~D@
C319
0.1U_0402_10V6K~D@
C380
0.1U_0402_10V6K~D@
1
2
1
2
1
2
+VTT_GMCH
1
C337
0.1U_0402_10V6K~D
2
Place near GMCH Place near GMCH
+2.5V_MEM
1
C374
0.1U_0402_10V6K~D@
2
+2.5V_MEM
1
C389
0.1U_0402_10V6K~D@
2
C354
1 2
0.1U_0402_10V6K~D
C379
0.1U_0402_10V6K~D@
C359
0.1U_0402_10V6K~D@
C347
0.1U_0402_10V6K~D@
+2.5V_MEM
1
2
1
C377
0.1U_0402_10V6K~D@
2
1
C393
0.1U_0402_10V6K~D@
2
C396
0.1U_0402_10V6K~D
1
C338
0.1U_0402_10V6K~D@
2
1
C346
0.1U_0402_10V6K~D@
2
1
C345
0.1U_0402_10V6K~D@
2
1
1
C376
0.1U_0402_10V6K~D@
2
1
C375
0.1U_0402_10V6K~D@
2
1
C353
0.1U_0402_10V6K~D@
2
1
C351
0.1U_0402_10V6K~D@
2
+VTT_GMCH
Bulk Decopuling
1
+
C308
470U_D4_2.5V_R10M~D
2
A A
+2.5V_MEM
1
2
C384
22U_1206_10V4Z~D
5
2
C327
0.1U_0402_16V4Z~D
1
2
C370
4.7U_0805_6.3V6K~D
1
2
C288
4.7U_0805_6.3V6K~D
1
+1.5VRUN
2
C322
10U_0805_10V4M~D
1
2
C287
4.7U_0805_6.3V6K~D
1
1
C289
1U_0603_6.3V6M~D
2
+1.5VRUN
1
+
C329
470U_D4_2.5V_R10M~D
2
2
C284
4.7U_0805_6.3V6K~D
1
Place at the output of the 1.5V VR
4
1
C290
0.47U_0603_16V7K~D
2
Place between the VR and GMCH
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Springdale-Decoupling
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
13 65Wednesday, January 28, 2004
A00-B
Page 14
5
4
3
2
1
C
E 3
FAN1 Control and Tachometer
D D
R286
100K_0402_5%~D
FAN1_PWM
C C
1 2
1U_0805_10V6K~D
FAN1VREF
C254
1
2
FAN1_VFB
12
U30B
LM358M_SO8~D
5
6
2200P_0603_50V7K~D @
R150
100K_0402_5%~D
+12V
8
P
IN+
IN-
G
4
C108
1 2
R151
300K_0402_5%
1 2
1
C117
0.1U_0402_16V4Z~D
2
SI3457DV-T1_TSOP6~D
FAN1_ON
7
O
D2
RB751V_SOD323~D
+12V
2
+3VRUN
12
R133
10K_0402_5%~D
Q30
PMBT2222_SOT23~D
3 1
SI3457DV P channel
Vds max: +/- 30V
Vgs max: +/- 20V
Id max: 4.3A @ Vgs = -10V
65mohm @ Vgs = -10V
FAN1_TACH
+5VRUN
Q31
S
3
G
D
6
2451
FAN1_VOUT
1
+
C110
47U_D_16VM_R70~D
2
2 1
1
C102
0.47U_0603_16V7K~D
2
R136
10K_0402_5%~D
1 2
1 2
R137
1K_0402_5%~D
FAN1_TACH_FB
FAN1TACH_ON
FAN1
FAN1_VOUT
FAN1_TACH_FB
B
2222 SYMBOL(SOT23-NEW)
1
2
FAN2 Control and Tachometer
2
FAN2
JFAN2
4
4
3
3
2
2
1
1
MOLEX_53398-0490~D
+3VRUN+12V
12
Q61
PMBT2222_SOT23~D
3 1
R287
10K_0402_5%~D
FAN2_TACH
+12V
U30A
3
2
2200P_0603_50V7K~D@
IN+
IN-
C625
1 2
1 2
8
P
O
G
4
R580
300K_0402_5%
RB751V_SOD323~D
1
R291
B B
FAN2_PWM
100K_0402_5%~D
1 2
1U_0805_10V6K~D
FAN2VREF
C255
LM358M_SO8~D
1
2
FAN2_VFB
12
R288
100K_0402_5%~D
Q72
SI3457DV-T1_TSOP6~D
FAN2_ON
3
D17
2 1
G
S
D
6
2451
FAN2_VOUT
1
+
C622
47U_D_16VM_R70~D
2
+5VRUN
R289
10K_0402_5%~D
1 2
1
C256
0.47U_0603_16V7K~D
2
R290
1K_0402_5%~D
1 2
FAN2_TACH_FB
FAN2TACH_ON
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
FAN CONTROL
LA-1711
1
14 65Wednesday, January 28, 2004
A00-B
Page 15
5
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
D D
C C
B B
+2.5V_MEM
1
C111
22U_1206_10V4Z~D
2
A A
+2.5V_MEM
1
C103
0.1U_0402_10V6K~D
2
System Memory Decoupling caps
1
C107
0.1U_0402_10V6K~D
2
1
C134
0.1U_0402_10V6K~D
2
1
C113
0.1U_0402_10V6K~D
2
1
C124
0.1U_0402_10V6K~D
2
5
1
C106
0.1U_0402_10V6K~D
2
1
C132
0.1U_0402_10V6K~D
2
1
C109
0.1U_0402_10V6K~D
2
1
C129
0.1U_0402_10V6K~D
2
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
1
C114
0.1U_0402_10V6K~D
2
1
C123
0.1U_0402_10V6K~D
2
4
1
C112
0.1U_0402_10V6K~D
2
1
C128
0.1U_0402_10V6K~D
2
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE1
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
ICH_SMBDATA
ICH_SMBCLK
1
C101
2
1
C126
0.1U_0402_10V6K~D
2
+2.5V_MEM
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDQS0
DDRA_SDQ7
DDRA_SDQ6
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ27
DDRA_CKE1
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQS4
DDRA_SDQ33
DDRA_SDQ35
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5
DDRA_SDQ43
DDRA_SDQ42
DDRA_SDQ52
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ51
DDRA_SDQ54
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ59
+3VSUS
0.1U_0402_10V6K~D
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
C79
0.1U_0402_10V6K~D
2
1
C92
0.1U_0402_10V6K~D
2
3
+2.5V_MEM
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
AMP_1565917-1~D
DIMM0
STANDARD
3
2
VREF
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
DQ12
22
VDD
24
DQ13
26
DM1
28
VSS
30
DQ14
32
DQ15
34
VDD
36
VDD
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VDD
48
DM2
50
DQ22
52
VSS
54
DQ23
56
DQ28
58
VDD
60
DQ29
62
DM3
64
VSS
66
DQ30
68
DQ31
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
DU/RESET#
88
VSS
90
VSS
92
VDD
94
VDD
96
CKE0
98
DU/BA2
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
RAS#
120
CAS#
122
S1#
124
DU
126
VSS
128
DQ36
130
DQ37
132
VDD
134
DM4
136
DQ38
138
VSS
140
DQ39
142
DQ44
144
VDD
146
DQ45
148
DM5
150
VSS
152
DQ46
154
DQ47
156
VDD
158
CK1#
160
CK1
162
VSS
164
DQ52
166
DQ53
168
VDD
170
DM6
172
DQ54
174
VSS
176
DQ55
178
DQ60
180
VDD
182
DQ61
184
DM7
186
VSS
188
DQ62
190
DQ63
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
1
C104
0.1U_0402_10V6K~D
2
1
C133
0.1U_0402_10V6K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDRA_SDQ1
DDRA_SDQ4
DDRA_SDM0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ9
DDRA_SDQ12
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ18
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ31
DDRA_CKE0
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1
DDRA_SDQ37
DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ47
DDRA_SDQ46
DDRA_SDQ48
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ55
DDRA_SDQ50
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ63
DDRA_SDQ58
1
C81
0.1U_0402_10V6K~D
2
1
C105
0.1U_0402_10V6K~D
2
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
2
DDRA_VREF trace width of
12mils and space 12mils(min)
DDRA_VREF
2
C507
0.1U_0402_16V4Z~D
1
DDRA_CKE0
DDRA_SCS#1
DDRA_CLK2#
DDRA_CLK2
2
1
+2.5V_MEM
12
R442
150_0603_1%~D
12
R440
150_0603_1%~D
Follow
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DDR-SODIMM SLOT1
LA-1711
1
A00-B
15 65Wednesday, January 28, 2004
Page 16
5
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
D D
C C
B B
System Memory Decoupling caps
+2.5V_MEM
1
C116
0.1U_0402_10V6K~D
2
+2.5V_MEM
1
2
C94
0.1U_0402_10V6K~D
A A
1
C100
0.1U_0402_10V6K~D
2
1
C86
0.1U_0402_10V6K~D
2
5
1
C82
0.1U_0402_10V6K~D
2
1
C97
0.1U_0402_10V6K~D
2
1
C84
0.1U_0402_10V6K~D
2
1
C80
0.1U_0402_10V6K~D
2
1
C98
0.1U_0402_10V6K~D
2
1
C90
0.1U_0402_10V6K~D
2
4
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
4
1
C95
0.1U_0402_10V6K~D
2
1
C78
0.1U_0402_10V6K~D
2
DDRB_CLK1
DDRB_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE1
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
ICH_SMBDATA
ICH_SMBCLK
1
C87
0.1U_0402_10V6K~D
2
1
C91
0.1U_0402_10V6K~D
2
DDRB_SDQ5
DDRB_SDQ4
DDRB_SDQS0
DDRB_SDQ6
DDRB_SDQ1
DDRB_SDQ9
DDRB_SDQ13
DDRB_SDQS1
DDRB_SDQ14
DDRB_SDQ10
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQS2
DDRB_SDQ19
DDRB_SDQ22
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQS3
DDRB_SDQ30
DDRB_SDQ26
DDRB_CKE1
DDRB_SMA12
DDRB_SMA9
DDRB_SMA7
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQS4
DDRB_SDQ33
DDRB_SDQ37
DDRB_SDQ46
DDRB_SDQ44
DDRB_SDQS5
DDRB_SDQ41
DDRB_SDQ45
DDRB_SDQ52
DDRB_SDQ49
DDRB_SDQS6
DDRB_SDQ48
DDRB_SDQ51
DDRB_SDQ60
DDRB_SDQ59
DDRB_SDQS7
DDRB_SDQ57
DDRB_SDQ56
+3VSUS
1
C125
0.1U_0402_10V6K~D
2
1
C83
0.1U_0402_10V6K~D
2
3
1
C85
0.1U_0402_10V6K~D
2
1
C127
0.1U_0402_10V6K~D
2
3
2
JDIM2
1
VREF
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
AMP_1565918-1~D
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DIMM1
REVERSE
1
C93
0.1U_0402_10V6K~D
2
1
C99
0.1U_0402_10V6K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
+2.5V_MEM+2.5V_MEM
1
C96
0.1U_0402_10V6K~D
2
1
C122
0.1U_0402_10V6K~D
2
DDRB_SDQ7
DDRB_SDQ0
DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ12
DDRB_SDQ11
DDRB_SDM1
DDRB_SDQ8
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDM2
DDRB_SDQ23
DDRB_SDQ18
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDM3
DDRB_SDQ27
DDRB_SDQ31
DDRB_CKE0
DDRB_SMA11
DDRB_SMA8
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1
DDRB_SDQ32
DDRB_SDQ36
DDRB_SDM4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ43
DDRB_SDQ40
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDM6
DDRB_SDQ55
DDRB_SDQ50
DDRB_SDQ61
DDRB_SDQ63
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ62
+3VSUS
1
2
1
2
DDRB_VREF trace width of
12mils and space 12mils(min)
2
C458
0.1U_0402_16V4Z~D
1
DDRB_CKE0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1
DDRB_CLK2#
DDRB_CLK2
C130
0.1U_0402_10V6K~D
C115
0.1U_0402_10V6K~D
DDRB_VREF
2
+2.5V_MEM
12
R418
150_0603_1%~D
12
R415
150_0603_1%~D
Follow
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 0.1uF*24
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DDR-SODIMM SLOT2
LA-1711
1
A00-B
1
16 65Wednesday, January 28, 2004
Page 17
5
Channel A(DIMM0) Termination
resistors & Decoupling caps
RN97 56_4P2R_0404_5%~D
DDRA_SDQ1
1 4
DDRA_SDQ4
2 3
RN85 56_4P2R_0404_5%~D
DDRA_SDQ5
1 4
DDRA_SDQ0
D D
C C
2 3
RN84 56_4P2R_0404_5%~D
DDRA_SDQ7
1 4
DDRA_SDQS0
2 3
RN96 56_4P2R_0404_5%~D
DDRA_SDM0
1 4
DDRA_SDQ2
2 3
RN95 56_4P2R_0404_5%~D
DDRA_SDQ3
1 4
DDRA_SDQ9
2 3
RN83 56_4P2R_0404_5%~D
DDRA_SDQ8
1 4
DDRA_SDQ6
2 3
RN94 56_4P2R_0404_5%~D
DDRA_SDQ12
1 4
DDRA_SDM1
2 3
RN82 56_4P2R_0404_5%~D
DDRA_SDQS1
1 4
DDRA_SDQ13
2 3
RN81 56_4P2R_0404_5%~D
DDRA_SDQ15
1 4
DDRA_SDQ10
2 3
RN93 56_4P2R_0404_5%~D
DDRA_SDQ14
1 4
2 3
RN80 56_4P2R_0404_5%~D
DDRA_SDQ17
1 4
DDRA_SDQ20
2 3
RN109 56_4P2R_0404_5%~D
DDRA_SDQ16
1 4
DDRA_SDQ21
2 3
RN79 56_4P2R_0404_5%~D
DDRA_SDQ22
1 4
DDRA_SDQS2
2 3
RN108 56_4P2R_0404_5%~D
DDRA_SDM2
1 4
DDRA_SDQ18
2 3
RN78 56_4P2R_0404_5%~D
DDRA_SDQ28
1 4
DDRA_SDQ19
2 3
RN107 56_4P2R_0404_5%~D
DDRA_SDQ23
1 4
DDRA_SDQ24
2 3
RN77 56_4P2R_0404_5%~D
DDRA_SDQS3
14
DDRA_SDQ29
23
RN106 56_4P2R_0404_5%~D
DDRA_SDQ25
14
DDRA_SDM3
23
RN64 56_4P2R_0404_5%~D
DDRA_SDQ51 DDRA_SDQ49
14
DDRA_SDQS6
23
RN63 56_4P2R_0404_5%~D
DDRA_SDQ60
14
DDRA_SDQ54
23
RN87 56_4P2R_0404_5%~D
DDRA_SDQ50
14
DDRA_SDQ56
23
RN86 56_4P2R_0404_5%~D
DDRA_SDQ57
14
DDRA_SDM7
23
RN62 56_4P2R_0404_5%~D
DDRA_SDQS7
14
DDRA_SDQ61
23
RN92 56_4P2R_0404_5%~D
DDRA_SDQ37
14
DDRA_SDQ34
23
RN91 56_4P2R_0404_5%~D
DDRA_SDM4
14
DDRA_SDQ38
23
RN70 56_4P2R_0404_5%~D
DDRA_SDQ32
14
DDRA_SDQ36
23
RN69 56_4P2R_0404_5%~D
DDRA_SDQ33
14
DDRA_SDQS4
23
RN99 56_4P2R_0404_5%~D
DDRA_SDQ39
14
DDRA_SDQ40
23
RN68 56_4P2R_0404_5%~D
DDRA_SDQ44
14
DDRA_SDQ35
23
RN98 56_4P2R_0404_5%~D
DDRA_SDQ41
14
DDRA_SDM5
23
RN67 56_4P2R_0404_5%~D
DDRA_SDQS5
14
DDRA_SDQ45
23
RN90 56_4P2R_0404_5%~D
DDRA_SDQ47
14
DDRA_SDQ46
23
V_1P25V_DDR_VTTV_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTTV_1P25V_DDR_VTT
RN66 56_4P2R_0404_5%~D
RN89 56_4P2R_0404_5%~D
RN65 56_4P2R_0404_5%~D
RN88 56_4P2R_0404_5%~D
RN76 56_4P2R_0404_5%~D
RN105 56_4P2R_0404_5%~D
RN100 56_4P2R_0404_5%~D
RN61 56_4P2R_0404_5%~D
DDRA_CKE0
DDRA_CKE1
DDRA_SCS#0
DDRA_SCS#1
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
4
R433 56_0402_5%~D
DDRA_SCS#0
DDRA_SDQ42 DDRB_SDQS3
14
DDRA_SDQ43
23
DDRA_SDQ48
14
DDRA_SDQ53
23
14
DDRA_SDQ52
23
DDRA_SDM6
14
DDRA_SDQ55
23
DDRA_SDQ27
14
DDRA_SDQ30
23
DDRA_SDQ26
14
DDRA_SDQ31
23
DDRA_SDQ63
14
DDRA_SDQ58 DDRB_SDM7
23
DDRA_SDQ59
14
DDRA_SDQ62
23
DDRA_CKE0
DDRA_CKE1
DDRA_SCS#0
DDRA_SCS#1
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
1 2
RN103 56_4P2R_0404_5%~D
DDRA_SMA8
14
DDRA_SMA6
23
RN104 56_4P2R_0404_5%~D
DDRA_CKE0
14
DDRA_SMA11
23
RN73 56_4P2R_0404_5%~D
DDRA_SMA3
14
DDRA_SMA5
23
RN72 56_4P2R_0404_5%~D
DDRA_SMA10
14
DDRA_SMA1
23
RN110 56_4P2R_0404_5%~D
DDRA_SMA4
14
DDRA_SMA2
23
RN74 56_4P2R_0404_5%~D
DDRA_SMA7
14
DDRA_SMA9
23
RN102 56_4P2R_0404_5%~D
DDRA_SMA0
14
DDRA_SBS1
23
RN101 56_4P2R_0404_5%~D
14
DDRA_SCAS#
23
R443 56_0402_5%~D
DDRA_SCS#1
1 2
DDRA_SMA12
DDRA_CKE1
DDRA_SWE#
DDRA_SBS0
DDRA_SWE#
DDRA_SBS0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
V_1P25V_DDR_VTT
RN75
1 4
2 3
56_4P2R_0404_5%~D
RN71
1 4
2 3
56_4P2R_0404_5%~D
3
Channel B(DIMM1) Termination
resistors & Decoupling caps
RN38 56_4P2R_0404_5%~D
DDRB_SDQ7
1 4
DDRB_SDQ0
2 3
RN32 56_4P2R_0404_5%~D
DDRB_SDQ4
1 4
DDRB_SDQ5
2 3
RN31 56_4P2R_0404_5%~D
DDRB_SDQ6
1 4
DDRB_SDQS0
2 3
RN39 56_4P2R_0404_5%~D
DDRB_SDM0
1 4
DDRB_SDQ2
2 3
RN37 56_4P2R_0404_5%~D
DDRB_SDQ3
1 4
DDRB_SDQ12
2 3
RN30 56_4P2R_0404_5%~D
DDRB_SDQ9
1 4
DDRB_SDQ1
2 3
RN29 56_4P2R_0404_5%~D
DDRB_SDQS1
1 4
DDRB_SDQ13
2 3
RN36 56_4P2R_0404_5%~D
DDRB_SDQ11
1 4
DDRB_SDM1
2 3
RN28 56_4P2R_0404_5%~D
DDRB_SDQ10
1 4
DDRB_SDQ14
2 3
RN47 56_4P2R_0404_5%~D
DDRB_SDQ8
1 4
DDRB_SDQ15DDRA_SDQ11
2 3
RN27 56_4P2R_0404_5%~D
DDRB_SDQ21
1 4
DDRB_SDQ20
2 3
RN45 56_4P2R_0404_5%~D
DDRB_SDM2
1 4
DDRB_SDQ23
2 3
RN33 56_4P2R_0404_5%~D
DDRB_SDQ19
1 4
DDRB_SDQS2
2 3
RN44 56_4P2R_0404_5%~D
DDRB_SDQ18
1 4
DDRB_SDQ28
2 3
RN26 56_4P2R_0404_5%~D
DDRB_SDQ24
1 4
DDRB_SDQ22
2 3
RN46 56_4P2R_0404_5%~D
DDRB_SDQ16
1 4
DDRB_SDQ17
2 3
2
RN25 56_4P2R_0404_5%~D
14
DDRB_SDQ25
23
RN34 56_4P2R_0404_5%~D
RN58 56_4P2R_0404_5%~D
RN15 56_4P2R_0404_5%~D
RN52 56_4P2R_0404_5%~D
RN14 56_4P2R_0404_5%~D
RN51 56_4P2R_0404_5%~D
RN12 56_4P2R_0404_5%~D
RN41 56_4P2R_0404_5%~D
RN11 56_4P2R_0404_5%~D
RN40 56_4P2R_0404_5%~D
RN10 56_4P2R_0404_5%~D
RN49 56_4P2R_0404_5%~D
RN19 56_4P2R_0404_5%~D
RN48 56_4P2R_0404_5%~D
RN18 56_4P2R_0404_5%~D
DDRB_SDQ26
14
DDRB_SDQ30
23
DDRB_SDM6
14
DDRB_SDQ55
23
DDRB_SDQ60
14
DDRB_SDQ51
23
DDRB_SDQ50
14
DDRB_SDQ61
23
DDRB_SDQS7
14
DDRB_SDQ59
23
DDRB_SDQ63
14
23
DDRB_SDQ39
14
23
DDRB_SDQ32DDRA_SRAS#
14
DDRB_SDQ36
23
DDRB_SDQ33
14
DDRB_SDQS4
23
DDRB_SDM4
14
DDRB_SDQ34
23
DDRB_SDQ46
14
DDRB_SDQ37
23
DDRB_SDQ35
14
DDRB_SDQ43
23
DDRB_SDQS5
14
DDRB_SDQ44
23
DDRB_SDQ40
14
DDRB_SDM5
23
DDRB_SDQ45
14
DDRB_SDQ41
23
1
RN60 56_4P2R_0404_5%~D
DDRB_SDQ42
14
DDRB_SDQ47
23
RN17 56_4P2R_0404_5%~D
DDRB_SDQ49
14
DDRB_SDQ52
23
RN59 56_4P2R_0404_5%~D
DDRB_SDQ53
14
DDRB_SDQ54
23
RN16 56_4P2R_0404_5%~D
DDRB_SDQ48
14
DDRB_SDQS6
23
RN42 56_4P2R_0404_5%~D
DDRB_SDQ27
14
DDRB_SDQ31
23
RN43 56_4P2R_0404_5%~D
DDRB_SDQ29
14
DDRB_SDM3
23
RN13 56_4P2R_0404_5%~D
DDRB_SDQ56
14
DDRB_SDQ57
23
RN50 56_4P2R_0404_5%~D
DDRB_SDQ58
14
DDRB_SDQ62DDRB_SDQ38
23
RN55 56_4P2R_0404_5%~D
DDRB_SMA4
14
DDRB_SMA2
23
RN54 56_4P2R_0404_5%~D
DDRB_SMA0
14
DDRB_SBS1
23
RN53 56_4P2R_0404_5%~D
DDRB_SRAS#
14
DDRB_SCAS#
23
DDRB_SDQ[0..63] DDRB_CKE0
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
DDRB_SRAS#
DDRB_SCAS#
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
R405 56_0402_5%~D
1 2
RN24 56_4P2R_0404_5%~D
RN23 56_4P2R_0404_5%~D
RN56 56_4P2R_0404_5%~D
RN21 56_4P2R_0404_5%~D
R431 56_0402_5%~D
1 2
RN22 56_4P2R_0404_5%~D
DDRB_CKE0
DDRB_SMA11
DDRB_SWE#
DDRB_SBS0
DDRB_SCS#0
DDRB_SMA12
14
DDRB_CKE1
23
DDRB_SMA7
14
DDRB_SMA9
23
DDRB_SMA8
14
DDRB_SMA6
23
DDRB_SMA10
14
DDRB_SMA1
23
DDRB_SCS#1
DDRB_SMA3
14
DDRB_SMA5
23
1 4
2 3
56_4P2R_0404_5%~D
1 4
2 3
56_4P2R_0404_5%~D
DDRB_SWE#
DDRB_SBS0
DDRB_SBS1
DDRB_CKE1
DDRB_SCS#0
DDRB_SCS#1
V_1P25V_DDR_VTT
RN57
RN20
DDRB_SWE#
DDRB_SBS0
DDRB_SBS1
DDRB_CKE0
DDRB_CKE1
DDRB_SCS#0
DDRB_SCS#1
V_1P25V_DDR_VTT
B B
1
C519
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C504
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C492
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
A A
C499
0.1U_0402_10V6K~D
2
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*28
1
C514
0.1U_0402_10V6K~D
2
1
C512
0.1U_0402_10V6K~D
2
1
C498
0.1U_0402_10V6K~D
2
1
C494
0.1U_0402_10V6K~D
2
5
1
C515
0.1U_0402_10V6K~D
2
1
C518
0.1U_0402_10V6K~D
2
1
C501
0.1U_0402_10V6K~D
2
1
C486
0.1U_0402_10V6K~D
2
1
C516
0.1U_0402_10V6K~D
2
1
C513
0.1U_0402_10V6K~D
2
1
C500
0.1U_0402_10V6K~D
2
1
C495
0.1U_0402_10V6K~D
2
1
C517
0.1U_0402_10V6K~D
2
1
C503
0.1U_0402_10V6K~D
2
1
C438
0.1U_0402_10V6K~D
2
1
2
We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02')
1
C511
0.1U_0402_10V6K~D
2
1
C661
0.1U_0402_10V6K~D
2
@
1
C493
0.1U_0402_10V6K~D
2
C490
4.7U_1206_16V6K~D
1
C510
4.7U_1206_16V6K~D
2
4
1
C662
0.1U_0402_10V6K~D
2
@
1
C496
0.1U_0402_10V6K~D
2
1
C667
0.1U_0402_10V6K~D
2
@
1
2
@
1
C502
0.1U_0402_10V6K~D
2
1
2
@
C663
0.1U_0402_10V6K~D
C668
0.1U_0402_10V6K~D
V_1P25V_DDR_VTT
1
C488
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C484
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C443
0.1U_0402_10V6K~D
2
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*26
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C482
0.1U_0402_10V6K~D
2
1
C478
0.1U_0402_10V6K~D
2
1
C442
0.1U_0402_10V6K~D
2
1
C481
0.1U_0402_10V6K~D
2
1
C476
0.1U_0402_10V6K~D
2
1
C434
0.1U_0402_10V6K~D
2
2
1
C487
0.1U_0402_10V6K~D
2
1
C485
0.1U_0402_10V6K~D
2
1
C441
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
1
C437
0.1U_0402_10V6K~D
2
1
C440
0.1U_0402_10V6K~D
2
1
C666
0.1U_0402_10V6K~D
2
@
1
C477
0.1U_0402_10V6K~D
2
1
C479
0.1U_0402_10V6K~D
2
1
C505
4.7U_1206_16V6K~D
2
1
C483
0.1U_0402_10V6K~D
2
1
C480
0.1U_0402_10V6K~D
2
1
C664
0.1U_0402_10V6K~D
2
@
1
C436
0.1U_0402_10V6K~D
2
1
C439
0.1U_0402_10V6K~D
2
1
C665
2
@
We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')
Compal Electronics, Inc.
Title
DDR Termination Resistors
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
17 65Wednesday, January 28, 2004
A00-B
Page 18
5
G_ST[0..2]
G_AD[0..31]
G_C/BE#[0..3]
G_SBA#[0..7]
CK_66M_AGP
D D
G_REQ#
AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0
Note:
AGP8X_DET_GC :Pull low by an AGP3.0 graphics card
Floating by an AGP2.0 graphics card
C C
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO
B B
G_ST0
G_ST1
G_ST2
2
1
G_SBA#[0..7]
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO
FPVCC
C317
0.1U_0402_10V6K~D
CK_66M_AGP
G_REQ#
G_ST0
G_ST1
G_ST2
AGP8X_DET_CG : low -->MB
support AGP3.0
VREFCG
R322
1
C388
0.1U_0402_16V4Z~D
2
GC_BL_SUSPEND
4
PCI_PIRQB#
+1.5VRUN
+1.5VRUN
RUNPWROK
FPVCC
+1.5VRUN
SP_DIF
ICH_SUS_STAT#
12
+5VSUS
+3VSUS
+3VRUN
0_0402_5%~D
+12V
G_PWR_SRC
CK_66M_AGP
AGP8X_DET_CG
PCI_PIRQB#
G_ST0
G_ST2
G_SBA#2
G_SBA#4
G_SB_STBF
G_SB_STBS#
AGP_RST#
G_IRDY#
G_TRDY#
RUNPWROK
G_STOP#
G_FRAME#
G_C/BE#3
G_AD31
G_AD29
G_AD_STBS1#
G_AD_STBF1
G_AD27
G_AD25
G_C/BE#2
G_AD21
G_AD19
VREFCG
G_AD15
G_AD13
G_AD11
G_AD9
G_AD_STBS0#
G_AD_STBF0
G_AD5
G_AD3
G_AD1
G_AD0
FPVCC
ICH_SUS_STAT#
GC_BL_SUSPEND
JVID
1
1
3
3
5
5
7
7
9
9
11
11
13
GND
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
GND
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
GND
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
GND
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
GND
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
GND
149
149
151
151
153
153
155
155
157
157
159
159
FOX_QT00160A-9120L~D
3
2
2
4
4
6
6
8
8
10
10
12
12
14
GND
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
GND
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
GND
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
GND
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
GND
124
124
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
142
142
144
144
146
146
148
GND
150
150
152
152
154
154
156
156
158
158
160
160
G_PWR_SRC
G_PWR_SRC
AGP8X_DET_GC
PCI_PIRQA#
G_REQ#
G_ST1
G_SBA#0
G_SBA#1
G_SBA#3
G_SBA#5
G_SBA#6
G_SBA#7
G_DEVSEL#
G_RBF#
G_WBF#
G_PIPE#_DBI_HI
G_AD30
G_AD28
G_AD26
G_AD24
G_AD22
G_AD20
G_AD18
G_AD23
G_AD17
G_AD16
G_DBI_LO
G_C/BE#1
VREFGC_R
G_AD14
G_AD12
G_AD10
G_AD8
G_AD7
G_AD6
G_AD4
G_AD2
G_C/BE#0
G_GNT#
G_PAR
SBAT_SMBDAT
SBAT_SMBCLK
STP_AGP_R#
+3VRUN
+1.5VRUN
2
C26
1
0.1U_0603_25V7M~D
R626 0_0402_5%~D
AGP8X_DET_GC
PCI_PIRQA#
G_RBF#
G_WBF#
+1.5VRUN
G_AGPBUSY#
SBAT_SMBCLK
+5VALW
+5VRUN
LID_CL#
+5VSUS
2
C23
1
0.1U_0603_25V7M~D
12
R88
1 2
0_0402_5%~D @
SBAT_SMBDAT
2
C24
1
0.1U_0603_25V7M~D
GC_THERMTRIP#
+3VRUN
2
C22
1
0.1U_0603_25V7M~D
VREFGC
+3VRUN
1 2
2
1
C21
2
0.1U_0603_25V7M~D
R96
10K_0402_5%~D
R98
0_0402_5%~D@
1 2
PWR_SRC
2
C19
1
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
CPLD Disable
Pop R96, Depop R98
STP_AGP#
+1.5VRUN
1
PWR_SRC G_PWR_SRC
2
C12
Q8
SI4435DY_SO8~D
1
2
3 6
4
8
7
5
1
R30
1 2
100K_0402_5%~D
Make R571
100K ohm
after 6th
August
RUN_ON
12
R28
100K_0402_5%~D
AGP_PWRON# GPWR_SRC_ON
13
D
Q7
2
G
2N7002_SOT23~D
S
FOXCONN QT00160A-9120L
Shielding Ground Pin
13,14
39,40
67,68
93,94
121,122
147,148
1
1
C325
C334
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
2
1
CLOSE
TO PIN
2
+5VALW
1
2
C415
0.1U_0402_16V4Z~D
1
+3VSUS
U7
TC7SH32FU_SSOP5~D@
5
SYS_SUSPEND
1
P
AGP_RST#
A A
5
4
O
R156
0_0402_5%~D
INB
PCIRST_AGP#
2
INA
G
3
12
4
SYS_SUSPEND
PCIRST_AGP#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C417
2
0.047U_0402_10V4M~D
+12V
1
C413
0.1U_0402_16V4Z~D
2
C418
2
0.047U_0402_10V4M~D
C339
2
0.047U_0402_10V4M~D
+5VRUN
1
C416
0.1U_0402_16V4Z~D
2
1
1
C342
C336
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1
2
1
1
C397
C409
2
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
1
1
C357
C352
2
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
VGA Daughter Board Conn.
LA-1711
1
18 65Wednesday, January 28, 2004
A00-B
Page 19
5
+3VALW
4
3
2
1
CPU Temperature Sensor
D D
R378
R375
1 2
1 2
DAT_SMB
CLK_SMB
C C
DAT_SMB
CLK_SMB
6.8K_0402_5%~D
6.8K_0402_5%~D
FAN3 Control and Tachometer
+12V
12
8
U46A
P
O
G
LM358M_SO8~D
4
C672
R617
4
+12V
1 2
1
R609
10K_0402_5%~D@
+3VRUN
B B
A A
5
10K_0402_5%~D
FAN3_PWM
R117
R616
1M_0402_5%~D
1 2
C671
1U_0805_10V6K~D
12
2
G
1
2
13
D
S
2.7K_0402_5%@
Q75
2N7002_SOT23~D@
3
2
2200P_0603_50V7K~D @
12
R618
100K_0402_5%~D
R610
+12V
IN+
IN-
1 2
300K_0402_5%
1 2
C408
1 2
0.1U_0402_16V4Z~D
FAN3_TACH
0.47U_0603_16V7K~D
Q28
SI3457DV-T1_TSOP6~D
D
S
4 5
G
3
+3VRUN
6
2
1
U37
3
VCC
16
SDA
1
SCL
6
TACH1
7
TACH2
4
TACH3
9
TACH4
PWM2/ALERT#
2
GND
ADT7460ARQ_QSOP16~D
2.5VIN
PWM1
PWM3
14
13
D1+
D1-
D2+
D2-
H_THERMDC
12
MCH_THERMDA
11
MCH_THERMDC
10
FAN3_PWM
15
5
8
R365 10K_0402_5%~D
Address 0101 110X (X=1-->Read; X=0-->Write)
+5VRUN
R118
10K_0402_5%~D
1 2
R120
1K_0402_5%~D
1 2
1
C89
FAN3_ON
2
1
2
3
SUYIN_250019MR003G400ZL~D
Item101: Reserved Op amp circuit (NP) to the High side FET
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JFAN3
1
2
3
FAN3TACH_ON
FAN3
3
1 2
2 1
1 2
0_0402_5%~D
+3VRUN
12
R125
10K_0402_5%~D
Q29
2
PMBT2222_SOT23~D
3 1
D1
RB751V_SOD323~D
R366
FAN3_TACH
1
C420
2200P_0603_50V7K~D
2
+3VRUN
1
+
C88
47U_D_16VM_R70~D
2
ATF_INT#
H_THERMDA
H_THERMDC
2
MCH_THERMDAH_THERMDA
1
C657
2200P_0603_50V7K~D
2
MCH_THERMDC
Q73
2
MMBT3904_SOT23~D
Put 3904 between MCH and DDR
Put Cap near pin 10,11 of U37
DELL CONFIDENTIAL/PROPRIETARY
Title
CPU Thermal Sensor & FAN Control
Size Document Number Rev
Date: Sheet of
LA-1711
1
3 1
19 65Wednesday, January 28, 2004
A00-B
Page 20
5
+3VRUN
RN3
182736
45
8.2K_8P4R_1206_5%~D
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
+3VRUN
D D
+3VRUN
+3VRUN
C C
+3VRUN
+3VRUN
B B
+3VSUS
PCI_PCIRST#
A A
182736
182736
182736
12
R386
10K_0402_5%~D
12
R401
10K_0402_5%~D
10
13
12
RN2
45
8.2K_8P4R_1206_5%~D
RN4
45
8.2K_8P4R_1206_5%~D
RN1
45
8.2K_8P4R_1206_5%~D
12
R113
10K_0402_5%~D
12
R426
10K_0402_5%~D
U8A
14
74VHC08MTC_TSSOP14~D
1
P
IN1
OUT
2
IN2
G
7
U8B
74VHC08MTC_TSSOP14~D
4
IN1
OUT
5
IN2
U8C
74VHC08MTC_TSSOP14~D
IN1
OUT
9
IN2
U8D
74VHC08MTC_TSSOP14~D
IN1
OUT
IN2
R387
10K_0402_5%~D
R139
10K_0402_5%~D
3
6
8
11
5
PCI_FRAME#
12
R398
8.2K_0402_5%~D
@
PCI_GNTA#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
12
R119
8.2K_0402_5%~D
PCI_PLOCK#
PCI_REQ0#
PCI_REQB#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_REQ2#
12
PCI_REQ4#
PCI_REQ1#
PCI_REQ3#
12
IDE_IRQ15
IDE_IRQ14
IRQ_SERIRQ
IDE_IRQ15
IDE_IRQ14
IRQ_SERIRQ
C118
0.1U_0402_16V4Z~D
R162
33_0402_5%~D
PCIRSTB1#
1 2
R159
33_0402_5%~D
PCIRSTB2#
1 2
33_0402_5%~D
1 2
R153
33_0402_5%~D
PCIRSTB3# PCIRST_1#
1 2
PCIRSTB4#
33_0402_5%~D
1 2
+3VRUN
R393
10K_0402_5%~D
1 2
PCI_REQA#
R414
CK_33M_ICHPCI
12
10_0402_5%~D@
CLK_ICH_TERM
1
C465
8.2P_0402_50V8J~D
@
2
+1.5VRUN
+1.5VRUN
12
R411
226_0603_1%~D
HI_SWING_ICH
12
R410
147_0603_1%~D
12
R409
113_0603_1%
12
PCIRST_AGP#
PCIRST_SIO#
R160
R157
PCIRST_2#
PCIRST_AGP#
PCIRST_SIO#
PCIRST_CB#
PCIRST_1#
PCIRST_2#
R124
1 2
52.3_0603_1%~D
HI_VREF_ICH
4
+3VRUN
RN35
182736
45
8.2K_8P4R_1206_5%~D
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
HI_RCOMP_ICH
Note:
HI_SWING_MCH, HI_VREF_MCH
trace width of 12mils and
space 10mils
2
C460
0.1U_0402_16V4Z~D
1
2
C456
0.1U_0402_16V4Z~D
1
4
+3VSUS
1
C455
0.01U_0402_16V7K~D
2
Close to ICH ball <250mils
1
C452
0.01U_0402_16V7K~D
2
Close to ICH ball <250mils
0.1"~6"
ICH_AC_RST_R#
ICH_AC_SYNC_R
ICH_AC_SDOUT_R
ICH_AC_SDOUT
ICH_AC_BITCLK
ICH_AC_SDIN0
ICH_AC_SDIN1
R389 33_0402_5%~D
R385 33_0402_5%~D
R390 33_0402_5%~D
R383
1K_0402_5%~D@
1 2
3
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
R425
10K_0402_5%~D@
12
ICH_PME#
PCI_PERR#
PCI_SERR#
PCI_PCIRST#
CK_33M_ICHPCI
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#
PCI_REQB#
PCI_GNT1#
PCI_GNT3#
PCI_GNT4#
PCI_GNTB#
HUB_HL[0..10]
R406 61.9_0603_1%
1 2
HUB_HLSTRF
HUB_HLSTRS
ICH_AC_SDIN0
ICH_AC_SDIN1
ICH_AC_BITCLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
ICH_PME#
PCI_PCIRST#
CK_33M_ICHPCI
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQA#
PCI_REQB#
PCI_GNT1#
PCI_GNT3#
PCI_GNT4#
PCI_GNTA#
PCI_GNTB#
R430 0_0402_5%~D
R392 1K_0402_5%~D@
1 2
LAN_RST#
12
NC_EE_DOUT
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDOUT_R
ICH_AC_SDIN0
ICH_AC_SDIN1
HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10
HI_RCOMP_ICH
HI_SWING_ICH
HI_VREF_ICH
CK_66M_ICH
U5A
D2
FRAME#
M3
IRDY#
E4
TRDY#
L3
DEVSEL#
E5
STOP#
F1
PAR
K2
PERR#
L2
PLOCK#
L4
SERR#
V2
PME#
V4
PCIRST#
N1
PCICLK
B3
PIRQA#
E1
PIRQB#
A2
PIRQC#
C2
PIRQD#
D7
PIRQE#/GPI2
A6
PIRQF#/GPI3
E2
PIRQG#/GPI4
B1
PIRQH#/GPI5
D5
REQ0#
C1
REQ1#
C5
REQ2#
B6
REQ3#
C6
REQ4#/GPI40
A5
REQA#/GPI0
E7
REQB#REQ5#/GPI1
D4
GNT0#
A3
GNT1#
B7
GNT2#
C7
GNT3#
A4
GNT4#/GPO48
E8
GNTA#/GPO16
B4
GNTB#/GNT5#/GPO17
FW82801EB_mBGA460_ICH5~D
H20
H21
J20
H23
M23
M21
N21
M20
L22
J22
K21
G22
K23
J24
N24
L20
L24
N22
C10
C9
C11
D9
E9
B12
D10
E10
AA1
B11
B10
A12
B9
B8
C12
A9
E12
D12
A13
D8
FW82801EB_mBGA460_ICH5~D
R396
10_0402_5%~D@
U5B
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11
HI_STBF
HI_STBS
HIRCOMP
HI_VSWING
HIREF
CLK66
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
LAN_CLK
LAN_RST#
EE_DIN
EE_CS
EE_SHCLK
EE_DOUT
AC_SYNC
AC_RST#
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_BIT_CLK
2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
C/BE3#
C/BE2#
C/BE1#
C/BE0#
USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
USBP6P
USBP6N
USBP7P
USBP7N
OC0#
OC1#
OC2#
OC3#
OC4#/GPI9
OC5#/GPI10
OC6#/GPI14
OC7#/GPI15
USBRBIAS
USBRBIAS#
CLK48
1
USBP1+
USBP1ÂUSBP2+
USBP2ÂUSBP3+
USBP3ÂUSBP4+
USBP4ÂUSBP5+
USBP5ÂUSBP6+
USBP6-
PCI_AD[0..31]
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
12
R404
12
10_0402_5%~D@
Note:
USBRBIAS keep less than 500mils
CK_48M_ICH_TERM
2
C431
@
4.7P_0402_50V8C~D
1
RN111
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%~D
RN112
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
USB_OC6#
USB_OC IS 5V
TOLERANT
+3VSUS
PCI_AD31
P2
PCI_AD30
F4
PCI_AD29
P4
PCI_AD28
F5
PCI_AD27
N2
PCI_AD26
D3
PCI_AD25
P3
PCI_AD24
E6
PCI_AD23
N4
PCI_AD22
C4
PCI_AD21
N5
PCI_AD20
H3
PCI_AD19
P5
PCI_AD18
B2
PCI_AD17
L1
PCI_AD16
G4
PCI_AD15
G5
PCI_AD14
K1
PCI_AD13
G2
PCI_AD12
L5
PCI_AD11
H4
PCI_AD10
M4
PCI_AD9
F2
AD9
PCI_AD8
K5
AD8
PCI_AD7
J2
AD7
PCI_AD6
J3
AD6
PCI_AD5
H2
AD5
PCI_AD4
H5
AD4
PCI_AD3
K4
AD3
PCI_AD2
G3
AD2
PCI_AD1
J5
AD1
PCI_AD0
J4
AD0
M2
N3
J1
E3
C23
D23
A22
B22
C21
D21
A20
B20
C19
D19
A18
B18
C17
D17
A16
B16
USB_OC0#
C15
USB_OC1#
D15
USB_OC2#
D14
USB_OC3#
C14
USB_OC4#
B14
USB_OC5#
A14
USB_OC6#
D13
USB_OC7#
C13
A24
B24
F24
USBRBIAS
CK_48M_ICH
CK_48M_ICH
R394 22.6_0603_1%~D
1 2
CK_66M_ICH
12
12
12
R395
10K_0402_5%~D@
ICH_AC_RST#
ICH_AC_SYNC
ICH_AC_SDOUT
+3VRUN
12
12
12
R397
R402
10K_0402_5%~D@
10K_0402_5%~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
ICH_AC_BITCLK_TERM
2
C427
10P_0402_50V8J~D
@
1
2
CK_66M_ICH
R413
10_0402_5%~D
1 2
CK_66M_ICH_TERM
2
C464
10P_0402_50V8J~D
1
DELL CONFIDENTIAL/PROPRIETARY
Title
ICH5-PCI/HUB/USB/AC97
Size Document Number Rev
Date: Sheet of
LA-1711
1
A00-B
20 65Wednesday, January 28, 2004
Page 21
5
+3VRUN
R274
4.7K_0402_5%~D
IDE_PDIORDY
IDE_SDIORDY
IDE_PDDREQ
IDE_SDDREQ
D D
SIO_SLP_S3#
C C
@
0 0 0 0
B B
A A
0 0 0
0 0 0
0 0
0 0 0
0 1 10 A00
R154
ICH_RTCRST#
1 2
180K_0402_5%~D
C509
15P_0603_50V8J~D
12
C508
15P_0603_50V8J~D
12
12
R562
4.7K_0402_5%~D
12
R279
0_0402_5%~D
1 2
R558
0_0402_5%~D
1 2
C251
1 2
R439 0_0402_5%~D
+3VRUN
1 2
R13010K_0402_5%~D
12
R12610K_0402_5%~D
12
R11510K_0402_5%~D @
12
R40310K_0402_5%~D
12
BID0BID1BID2BID3 REV
1
1
1 1
1
SHORT PADS@
2
2
1
+VRBATT_RTC
2
C119
0.1U_0402_10V6K~D
+3.3VRTC
ICH_RTCX1
X4
32.768KHZ_12.5P_MC-306~D
1 2
ICH_RTCX2 RTCX2
5
2
2
C608
1
1
33P_0603_50V8J~D
33P_0603_50V8J~D@
@
R116
R399
1 2
10K_0402_5%~D
10K_0402_5%~D@
X00
X01
X02
X03
X04
CMOS_CLR
1
R158
1K_0402_5%~D@
1 2
R623
1K_0402_5%~D
1 2
1 2
R630 0_0402_5%~D
RPDDREQ
RSDDREQ
RSDDREQ
ICH_SLP_S1#
R128
R123
1 2
1 2
10K_0402_5%~D
10K_0402_5%~D
@
BID0
BID1
BID2
BID3
R471
1 2
1
1K_0402_5%~D
3 2
C120
1U_0805_10V6K~D
12
R437
10M_0402_5%~D
ICH_SYNC#
D3
1
2
1
IDE_IRQ14
PWRGD_3V
BAT54C_SOT23~D @
MMBT3904_SOT23~D@
VCC_RTC
BAT54C
K2 K1
2
+3VSUS
+3VRUN
IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PDD9
IDE_PDD8
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDIOW#
IDE_PDDACK#
IDE_PDDREQ
IDE_PDIOR#
IDE_PDIORDY
IDE_PDA2
IDE_PDA1
IDE_PDA0
IDE_PDCS3#
IDE_PDCS1#
+3VRUN
12
R167
220_0402_5%@
Q33
2
1
VCC_RTC
R419
10K_0402_5%~D@
1 2
R121
10K_0402_5%~D@
1 2
12
3 1
3
A1A2
4
U5C
AB17
PDD15
AA16
PDD14
Y16
PDD13
AC16
PDD12
AA15
PDD11
AD16
PDD10
Y15
PDD9
AD15
PDD8
AB14
PDD7
AD14
PDD6
AC15
PDD5
AA14
PDD4
AC14
PDD3
Y14
PDD2
Y13
PDD1
AB16
PDD0
AA17
PDIOW#
AC18
PDDACK#
AC17
PDDREQ
AD18
PDIOR#
AA18
PIORDY
AC19
PDA2
AD19
PDA1
AA19
PDA0
Y18
PDCS3#
AB19
PDCS1#
Y17
IRQ14
FW82801EB_mBGA460_ICH5~D
R266
10K_0402_5%~D@
1 2
SPKR
1 2
1K_0402_5%~D@
Disable timer timeout
+3VRUN
R169
1K_0402_5%~D@
Q32
2
MMBT3904_SOT23~D@
3 1
R438
1 2
0_0402_5%~D
LPC_LDRQ0#
LPC_LDRQ1#
4
SDD15
SDD14
SDD13
SDD12
SDD11
SDD10
SDIOW#
SDDACK#
SDDREQ
SDIOR#
SIORDY
SDCS3#
SDCS1#
IRQ15
SDD9
SDD8
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
SDA2
SDA1
SDA0
AB24
AC24
AB22
AA20
AC22
AD22
Y19
AC20
AB20
AC21
AB21
AD24
AD23
AB23
AA22
Y22
W20
Y20
Y23
Y21
W21
W23
W22
V20
V22
Y24
IDE_SDD14
IDE_SDD13
IDE_SDD12
IDE_SDD11
IDE_SDD10
IDE_SDD9
IDE_SDD8
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0
IDE_SDIOW#
IDE_SDDACK#
IDE_SDDREQ
IDE_SDIOR#
IDE_SDIORDY
IDE_SDA2
IDE_SDA1
IDE_SDA0
IDE_SDCS3#
IDE_SDCS1#
IDE_IRQ15
R263
0_0402_5%~D
1 2
IDE_SDD15
AA23
3 1
2
IDE_RST_MOD_SFTON
R114
+3VRUN
12
R161
220_0402_5%@
LPC_LAD[0..3]
PWRGD_OK
ICH_SYNC# PWRGD_3V PWRGD_OK
0
0
1 1 1
+3VSUS
12
R138
10K_0402_5%~D
+5VMOD
Q46
MMBT3904_SOT23~D@
IRQ_SERIRQ
H_SMI#
STPCLK#
Note:
SATABIAS keep
less than
500mils
0
1
0 01
R140
0_0402_5%~D@
1 2
R141 0_0402_5%~D@
1 2
IDE_SDD[0..15]
IDE_SDIOW#
IDE_SDDACK#
IDE_SDIOR#
IDE_SDIORDY
IDE_SDA[0..2]
IDE_SDCS3#
IDE_SDCS1#
IDE_IRQ15
R269
1K_0603_5%~D@
R134
CBS_RI#ICH_RI#
12
SIO_A20GATE
CPUSLP#
H_FERR#
SIO_RCIN#
R127
0_0402_5%~D
SATA_MODTX+
SATA_MODTXÂSATA_MODRXÂSATA_MODRX+
R423 24.9_0603_1%~D
LPC_LFRAME#
LPC_LDRQ0#
LPC_LDRQ1#
SUSPWROK
0
0
CPLD Disable
Depop R141
CPLD_WAKE#
H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
12
0_0402_5%~D
12
1 2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CBS_RI#
3
2
Top View
2
1
44
43
HH99227-S9
1 2
IDE_RST_HDDIDE_RST_MOD IDE_RST_MOD_5V
R271
10K_0402_5%~D@
IDE_RST_MOD_SFTON
1 2
+3VRUN
U5D
T22
A20GATE
V23
A20M#
P22
CPUSLP#
U24
FERR#
R21
IGNNE#
R23
INIT#
U23
INTR
R22
NMI
P23
RCIN#
F23
12
R432
10K_0402_5%~D
SERIRQ
V24
SMI#
T24
STPCLK#
P20
DPRSLPVR(Mobile)
R24
DPSLP#(Mobile)
AA8
SATA0TXP
AB8
SATA0TXN
AD7
SATA0RXN
AC7
SATA0RXP
AA10
SATA1TXP
AB10
SATA1TXN
AD9
SATA1RXN
AC9
SATA1RXP
Y11
SATARBIASP
Y9
SATARBIASN
AC5
CLK100P
AD5
CLK100N
T5
LAD0
R4
LAD1
R3
LAD2
U4
LAD3
T4
LFRAME#
U5
LDRQ0#
R2
LDRQ1#/GPI41
AC11
RTCX1
AB12
RTCX2
AA12
RTCRST#
AB13
RSMRST#
AC12
PWROK
FW82801EB_mBGA460_ICH5~D
SMI#
SATABIAS
CK_100M_ICH
CK_100M_ICH#
LPC_LFRAME#
LPC_LDRQ0#
LPC_LDRQ1#
ICH_RTCX1
RTCX2
ICH_RTCRST#
12
R436
10K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3 1
CPUPWRGD/GPO49
PIDEACT#
Connector on
bottom side
R265
0_0402_5%~D
Q51
MMBT3904_SOT23~D @
2
GPIO6
GPIO7
GPIO8
SMBALERT#/GPI11
GPIO12
GPIO13
GPO18
GPO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO27
GPIO28
GPIO32
GPIO33
GPIO34
SMBCLK
SMBDATA
SMLINK0
SMLINK1
LINKALERT#
SPKR
PWRBTN#
SUSCLK
SUS_STAT#
SLP_S3#
SLP_S4#
SLP_S5#
SYS_RESET#
VRMPWRGD
THRMTRIP#
THRM#
INTVRMEN
CLK14
INTRUDER#
+VCC_CORE
H_THERMTRIP_R#
12/17/02 Changed by
Dell's Require
1K_0402_5%~D
PIDEACT#
+5VHDD
R262
1K_0603_5%~D
@
1 2
IDE_RST_HDD_5V
LK2-->USB2P0_SMI
R5
U3
SIO_EXT_SMI#
Y2
LAN_PME#
AC3
SIO_EXT_RTE#
W4
SIO_EXT_SCI#
W5
U21
T20
U22
R1
U20
F22
AC1
W3
BID2
V3
BID0
W2
BID1
T1
SATA_LED#
G23
BID3
F21
ICH_SMBCLK
AD2
ICH_SMBDATA
AD1
ICH_SMLINK0
AD3
ICH_SMLINK1
AA2
LINK_ALERT#
V5
SPKR
E24
ICH_RI#
AB3
RI#
Y4
SUSCLK
Y1
ICH_BATLOW#
AB2
TP0
AB1
SIO_SLP_S3#
W1
SIO_SLP_S4#
U2
SIO_SLP_S5#
AA3
U1
VRM_PWRGD
R20
P24
H_THERMTRIP_R#
T21
SIO_THRM#
T2
ICH_INTVRMEN
AD10
F20
ICH_THERM_PWRDN#
Y12
A11
NC
R428
1 2
10K_0402_5%~D
1
2
2
R568
1 2
IDE_RST_HDD_5V
IDE_PDD7 IDE_PDD8
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
+5VHDD
IDE_PDD0
RPDDREQ
IDE_PDIOW#
12
IDE_PDIOR#
IDE_PDIORDY
IDE_PDDACK#
IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
+5VHDD
1 2
1 2
1 2
+3VRUN
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
R417
R421
R142
12
R388
10K_0402_5%~D
1 2
R427
R122 10K_0402_5%~D
0_0402_5%~D@
C469
0.1U_0402_16V4Z~D@
10K_0402_5%~D
SPKR
R135 10K_0402_5%~D
1 2
ICH_SUS_STAT#
SIO_SLP_S3#
1 2
VRM_PWRGD
R422
H_THERMTRIP#
SIO_PWRBTN#
H_PWRGOOD
SIO_THRM#
JHDD
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
SGND
49
SGND
B1
50
SGND
B2
SGND
FOX_HH99227-S9~D
+3VRUN
+3VSUS
+3VSUS
12
12
R143
R148
2.7K_0402_5%
2.7K_0402_5%
+3VSUS
+3VSUS
1 2
R424 0_0402_5%~D
1 2
R429 0_0402_5%~D
+3VSUS
CK_14M_ICH
R400
10_0402_5%~D@
1 2
CK_14M_ICH_TERM
2
VCC_RTC
C428
1
4.7P_0402_50V8C~D@
Title
Size Document Number Rev
Date: Sheet of
1
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
R570
2
1
C240
1
2
0.1U_0402_16V4Z~D
4.7U_1206_16V6K~D
SIO_EXT_SMI#
SIO_EXT_RTE#
SIO_EXT_SCI#
SUSCLK
ICH_SMBCLK
ICH_SMBDATA
1 2
1 2
R435 330K_0402_5%~D
1 2
VRM_PWRGD
SIO_THRM#
ICH_THERM_PWRDN#
ICH_THERM_PWRDN#
470_0402_5%~D
12
T13
PAD@
2
C237
1
0.1U_0402_16V4Z~D
SIO_EXT_SMI#
SIO_EXT_RTE#
SIO_EXT_SCI#
SUSCLK
10K_0402_5%~D
10K_0402_5%~D
SIO_SLP_S4_S5#
VCC_RTC
R416
1 2
10K_0402_5%~D
1 2
R420 10K_0402_5%~D
IDE_CSEL_PRI
ATA_66_PRI/PDIAG
IDE_PDA2
IDE_PDCS3#
45
46
47
48
C238
R149
R132
@
@
R434 10K_0402_5%~D
1 2
R441
100K_0402_5%~D
1 2
DELL CONFIDENTIAL/PROPRIETARY
ICH5-IDE/LPC/PM/GPIO/LAN
LA-1711
1
21 65Wednesday, January 28, 2004
+5VHDD
+3VSUS
+3VRUN
A00-B
Page 22
5
4
3
2
1
+3VRUN +1.5VRUN
D D
+3VRUN
+5VRUN
21
1 2
D14
RB751V_SOD323~D
2
C468
1U_0805_10V6K~D
1
ICH_V5REF_RUN
2
C471
0.1U_0402_16V4Z~D
1
2
C472
0.1U_0402_16V4Z~D
1
+3VSUS
1K_0402_5%~D
R391
Place near ball A8
+5VSUS
+3VSUS
21
C C
B B
A A
R384
1K_0402_5%~D
D13
RB751V_SOD323~D
1 2
2
C447
1U_0805_10V6K~D
1
ICH_V5REF_SUS
2
C445
0.1U_0402_16V4Z~D
1
2
C444
0.1U_0402_16V4Z~D
1
Place near ball(VSS) A17
5
VCC_RTC
C506
0.1U_0402_10V6K~D
Place near ball AD11
4
2
1
U5E
B5
VCC3_3
F6
VCC3_3
G1
VCC3_3
H6
VCC3_3
K6
VCC3_3
L6
VCC3_3
M10
VCC3_3
N10
VCC3_3
P6
VCC3_3
R13
VCC3_3
V19
VCC3_3
W15
VCC3_3
W17
VCC3_3
W24
VCC3_3
AD13
VCC3_3
AD20
VCC3_3
G19
VCC3_3
G21
VCC3_3
E18
VCCSUS3_3
B15
VCCSUS3_3
E11
VCCSUS3_3
F10
VCCSUS3_3
F11
VCCSUS3_3
E13
VCCSUS3_3
E14
VCCSUS3_3
U6
VCCSUS3_3
V6
VCCSUS3_3
F16
VCCSUS3_3
F17
VCCSUS3_3
F18
VCCSUS3_3
K15
VCCSUS3_3
A8
V5REF
W14
V5REF
E16
V5REF_SUS
AD11
VCCRTC
FW82801EB_mBGA460_ICH5~D
U5F
A1
VSS
A7
VSS
A10
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
AA5
VSS
AA7
VSS
AA9
VSS
AA11
VSS
AA13
VSS
AA21
VSS
AA24
VSS
AB5
VSS
AB7
VSS
AB9
VSS
AB11
VSS
AB15
VSS
AB18
VSS
AC2
VSS
AC4
VSS
AC6
VSS
AC8
VSS
AC10
VSS
AC13
VSS
AC23
VSS
AD4
VSS
AD6
VSS
AD8
VSS
AD17
VSS
AD21
VSS
AD12
VSS
B13
VSS
B17
VSS
B19
VSS
B21
VSS
B23
VSS
C3
VSS
C8
VSS
C16
VSS
C18
VSS
C20
VSS
C22
VSS
D1
VSS
D6
VSS
D11
VSS
D16
VSS
D18
VSS
D20
VSS
D22
VSS
D24
VSS
E17
VSS
E19
VSS
E20
VSS
E21
VSS
E23
VSS
F3
VSS
F9
VSS
FW82801EB_mBGA460_ICH5~D
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCCSATAPLL
VCCSATAPLL
VCCUSBPLL
VCCSUS1_5_A
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_C
VCCSUS1_5_C
V_CPU_IO
V_CPU_IO
V_CPU_IO
K10
K12
K13
L19
P19
R10
R6
H24
J19
K19
M15
N15
N23
E15
F15
F14
W19
R12
W9
W10
W11
W6
W7
W8
E22
AA6
AB6
C24
F19
Y5
AA4
AB4
F7
F8
R15
R19
T19
G6
VSS
G20
VSS
G24
VSS
H1
VSS
H19
VSS
H22
VSS
J6
VSS
J21
VSS
J23
VSS
K3
VSS
K11
VSS
K14
VSS
K20
VSS
K22
VSS
K24
VSS
L10
VSS
L11
VSS
L12
VSS
L13
VSS
L14
VSS
L15
VSS
L21
VSS
L23
VSS
M1
VSS
M5
VSS
M11
VSS
M12
VSS
M13
VSS
M14
VSS
M22
VSS
M24
VSS
N11
VSS
N12
VSS
N13
VSS
N14
VSS
N20
VSS
P1
VSS
P10
VSS
P11
VSS
P12
VSS
P13
VSS
P14
VSS
P15
VSS
P21
VSS
R11
VSS
R14
VSS
T23
VSS
T3
VSS
T6
VSS
U19
VSS
V1
VSS
V21
VSS
W16
VSS
W18
VSS
Y3
VSS
Y6
VSS
Y7
VSS
Y8
VSS
Y10
VSS
3
Place near
ball (VSS)A19
C430 0.01U_0402_16V7K~D
VCCSUS15_A
VCCSUS15_B
VCCSUS15_C
1 2
C475 0.01U_0402_16V7K~D
1 2
1 2
C433 0.01U_0402_16V7K~D
Place near
+VCC_CORE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
ball (VSS)A7
+VCC_CORE
Place near
ball T22
2
C470
0.1U_0402_16V4Z~D
1
+3VSUS
1U_0603_6.3V6M~D
1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1 2
Place near ball(VSS)
D1,A7,H1,P1W24 and A21
Place near
ball (VSS)AD4
+1.5VRUN +1.5VRUN
Place0.1u near ball(VSS)
A17,A23,V1.Addition cap near
A15,A19
C435
C467
12
C424
12
C446
12
C425
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
2
C432
0.1U_0402_16V4Z~D
12
C457
0.1U_0402_16V4Z~D
12
C453
0.1U_0402_16V4Z~D
12
C463
0.1U_0402_16V4Z~D
12
C449
0.1U_0402_16V4Z~D
12
C466
0.1U_0402_16V4Z~D
12
Place near ball D24 Place near ball AD6
C429
12
C426
1 2
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page278
+1.5VRUN+3VRUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1 2
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1 2
DELL CONFIDENTIAL/PROPRIETARY
Title
ICH5 Power & Decoupling
Size Document Number Rev
Date: Sheet of
C473
C489
C491
12
C451
12
C454
12
C474
12
C497
12
C448
12
C450
12
LA-1711
Place0.1u near ball(VSS)
G24,H24,K24,M24,AD4
and AD18; 0.01u near to
ball AD8.
1
22 65Wednesday, January 28, 2004
A00-B
Page 23
5
IDE_SDD[0..15]
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
D D
IDE_SDA[0..2]
IDE_SDCS1#
IDE_SDCS3#
IDE_SDDACK#
IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY
INT_CD_R
INT_CD_L
C C
B B
IDE_IRQ15
BAY_MODPRES#
RSDDREQ
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_SDA0
IDE_SDA1
IDE_SDA2
IDE_SDCS1#
IDE_SDCS3#
IDE_SDDACK#
IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY
INT_CD_R
INT_CD_L
IDE_IRQ15
BAY_MODPRES#
RSDDREQ
IDE_RST_MOD_5V
USB_IDE#
+3VRUN +3VRUN
IDE_RST_MOD_5V
R554
100K_0402_5%~D
1 2
swap by Dell require
Please see sketch
R563
1 2
470_0402_5%~D
R555
0_0402_5%~D
1 2
CD_AUDIORET
SATA_MODTX+
SATA_MODTX-
1 2
100K_0402_5%~D
SATA_MODRX+
SATA_MODRX-
R553
4
Reserved USB+
Reserved USB-
IDE_SDCS3#
IDE_SDA2
IDE_SDA0
IDE_SDA1
CSEL2
IDE_SDIOR#
IDE_SDIOW#
IDE_SDD15
IDE_SDD1
IDE_SDD2
IDE_SDD12
IDE_SDD11
IDE_SDD5
IDE_SDD6
IDE_SDD8
MOD_RST
USB_IDE#
CD_AUDIORET
BAY_MODPRES#
G69G
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
G70G
FOX_QL11343-A6B3-HT~D
3
JMOD1
73
71
M1
1
1
3
3
5
5
7
7
9
9
11
11
SATA_MOD_DETECT#
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
M2
74
72
+3VMOD
MOD_PIN15
USBP4_D+
USBP4_D-
SIDEACT#
IDE_SDCS1#
PDIAG#
IDE_IRQ15
IDE_SDDACK#
IDE_SDIORDY
RSDDREQ
IDE_SDD0
IDE_SDD14
IDE_SDD13
IDE_SDD3
IDE_SDD4
IDE_SDD10
IDE_SDD9
IDE_SDD7
INT_CD_R
INT_CD_L
1
C617
2
4.7U_1206_16V6K~D
SATA_MOD_DETECT#
1
C601
C602
2
47P_0402_50V8J~D
C614
0.1U_0402_16V4Z~D
R564 1K_0402_5%~D
T12
1
2
47P_0402_50V8J~D
+5VMOD +3VMOD
1
2
1 2
1
C616
C615
2
0.1U_0402_16V4Z~D
PAD@
INT_CD_R
INT_CD_L
1
2
0.1U_0402_16V4Z~D
R567
1 2
0_0402_5%~D@
+3VMOD
USBP4_D+
USBP4_D-
2
USB_OC4#
1
1
C613
0.1U_0402_16V4Z~D
2
1
C612
0.1U_0402_16V4Z~D
2
+3VRUN
SATA_MOD_DETECT#USB_OC4#
R569
1 2
100K_0402_5%~D
1
2
3
6
WF1F068N1A
4
5
MB side Module side
Connector
RX+
RX-
Host Chip
ICH5
A A
TX+
TX-
Direct connect
5
TX+
TX-
RX+
RX-
Device Chip
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
D-MODULE Detect
Device
Parallel IDE
USB Device
S-ATA IDE
None
3
Pin68
BAY_MODPRES#
LOW
LOW
LOW
Pin64
USB_IDE#
LOW
HIGH HIGH
HIGH
HIGH X X
Pin13JMOD1
SATA_MOD_DETECT#
HIGH
LOW
2
TOP VIEW
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
D- MODULE
LA-1711
1
23 65Wednesday, January 28, 2004
A00-B
Page 24
5
+5VSUS
1
1
C208
2
0.1U_0402_16V4Z~D
D D
+5VRUN
1
C158
0.1U_0402_16V4Z~D
2
SPDIF
A2Y
2
C209
C198
2
1
1U_0805_10V6K~D
0.01U_0402_16V7K~D
SPDIF_SHDN
1
5
U12
P
4
OE#
G
SN74AHCT1G125DCKR_SC70-5~D
3
AUDIO_AVDD_ON
AUDIO_AVDD_ON TPS793475_BYPASS
SP_DIF
1
2
3
4
U22
5
OUT
IN
GND
4
BYPASS
EN
TPS793475DBVR_SOT23-5~D
VDDA=4.75V
C215
1
C224
2
0.1U_0402_16V4Z~D
VDDA
1
1
C216
2
2
0.1U_0402_16V4Z~D
2.2U_0805_16VFZ~D
3
VDDA
SPKR
BEEP
CBS_SPK
L23
BLM11A121S_0603~D
1 2
U21
5
SN74AHCT1G86DCKR_SC70-5~D
1
P
A
2
B
G
3
4
Y
R237
43K_0402_5%~D
1 2
Z2401
Z2402
2
1
A
2
B
1
C212
0.1U_0402_16V4Z~D
2
5
U20
P
G
SN74AHCT1G86DCKR_SC70-5~D
3
300K_0402_5%
Z2403 PC_BEEPINZ2404
1 2
4
Y
1
4
5
1
2 3
single gate TTL
R223
8.2K_0402_5%~D
C192
0.1U_0402_16V4Z~D
1 2
12
R221
2
C190
1000P_0402_50V7K~D
@
1
+3VRUN
2
2
C170
C576
1
C C
22P_0402_50V8J~D@
22P_0402_50V8J~D@
ICH_AC_RST#
ICH_AC_SYNC
ICH_AC_SDOUT
SPK_SHUTDOWN#
C183
1 2
C168
1 2
R531
33_0402_5%~D
1
2
C579
27P_0603_50V8J~D@
2
1
ICH_AC_SDOUT
R526
47_0402_5%~D@
C570
22P_0402_50V8J~D
@
1 2
R525
33_0402_5%~D
1 2
R534
33_0402_5%~D
1 2
1
2
27P_0603_50V8J~D@
C573
0.1U_0402_16V4Z~D
CK_14M_CODEC
ICH_AC_BITCLK
MDC_AC_BITCLK
ICH_AC_SDIN0
C571
AC97VREFI
0.1U_0402_16V4Z~D
2.2U_0805_16VFZ~D
C186
2
1
B B
A A
C578
2
1
1 2
ICH_AC_SDOUT_TERM
1
2
AlcatrazNimitz
@
Depop Depop
1@
Depop
2@
5
Pop
DepopPop
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
ICH_AC_RST#
ICH_AC_SYNC
ICH_AC_SDOUT
R_ICH_AC_BITCLK
R_ICH_AC_SDIN0
C575 1000P_0402_50V7K~D
1 2
C171 1000P_0402_50V7K~D
1 2
C176
1 2
0.1U_0603_16V7K~D
@
EAPD
12
R512
10K_0402_5%~D
R614
1 2
0_0402_5%~D
X2
@
24.576 MHz_20P_1BX24576CC1A~D
PACKAGE : 8X4.5X1.5mm
1 2
R613
1 2
0_0402_5%~D
12
R619
0_0402_5%~D@
4
2
C161
1
2.2U_0805_16VFZ~D
AFLT1
AFLT2
VREFOUT
CAP2
SPK_SHUTDOWN#
SPDIF_SHDN
SPDIF
EAPD
XTL_24M+
XTL_24M-
12
R612
10_0402_5%~D@
1
C669
4.7P_0402_50V8C~D
@
2
W=30 mil
U16
11
RESET#
10
SYNC
5
SDATA_OUT
6
BIT_CLK
8
SDATA_IN
29
AFLT1
30
AFLT2
28
VREFOUT
27
VREF
32
CAP2
43
GPIO0/NC
44
GPIO1/NC
48
SPDIF
47
EAPD
31
NC/BPCFG
33
NC/FLTIN
34
NC/FLTOUT
46
CID1
45
CID0
3
XTL_OUT
2
XTL_IN
9
DVDD11DVDD2
STAC9750
DVSS14DVSS2
7
C580
38
LINE_IN_L
AVDD125AVDD2
LINE_IN_R
VIDEO_L
VIDEO_R
PC_BEEP
HP_OUT_L
HP_COMM
HP_OUT_R
MONO_OUT
LOUT_L
LOUT_R
AVSS126AVSS2
STAC9750_TQFP48~D
42
AUDIO_AVCC
2
C559
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
23
24
18
CD_L
19
CD_C
20
CD_R
14
AUX_L
15
AUX_R
21
MIC1
22
MIC2
16
17
13
PHONE
12
39
40
41
37
35
36
3
2
1
CD_L
CD_COMM
CD_R
CNB_MICIN
PC_BEEPIN
HP_COMM
L16
BLM31A260SPT_1206~D
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VDDA
C195 1U_0805_10V6K~D
1 2
C196 1U_0805_10V6K~D
1 2
C197 1U_0805_10V6K~D
1 2
C201
0.22U_0603_10V7M~D
1 2
1 2
C199
0.1U_0402_16V4Z~D
1 2
C200
0.1U_0402_16V4Z~D
C162
1U_0805_10V6K~D
1 2
2
C569
1000P_0402_50V7K~D
1
2
C565
1000P_0402_50V7K~D
1
CD_AUDIORET
HP_OUT_L
HP_OUT_R
AUD_MONO_OUT
AUD_LINE_OUT_L
AUD_LINE_OUT_R
2
INT_CD_L
CD_AUDIORET
INT_CD_R
NB_MICIN
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
AC97 Codec
LA-1711
1
24 65Wednesday, January 28, 2004
A00-B
Page 25
5
1K_0402_5%~D
R_INT_MIC-
2
1K_0402_5%~D
1
1U_0805_10V6K~D
C169
R505
R497
2
G
1U_0805_10V6K~D
13
D
S
D D
INT_MICÂINT_MIC+
C165
Q39
2N7002_SOT23~D
HP_NB_SENSE
+3VRUN
R197
100K_0402_5%~D
SPK_SHUTDOWN#
C C
SPK_SHUTDOWN#
EAPD
1 2
13
D
2
G
S
R_INT_MIC+
2
1
INT_MICÂINT_MIC+
1 2
1 2
Q40
2N7002_SOT23~D
4
VDDA
1 2
R517
1 2
1K_0402_5%~D
NB_MUTE
R511
1K_0402_5%~D
C561
0.1U_0402_16V4Z~D
1 2
1 2
C179
0.1U_0402_16V4Z~D
C157
2.2U_0805_16VFZ~D
13
D
2
G
S
AMPVCC
EXT_MIC_BIAS
MIC_SELECT
C178
0.1U_0402_16V4Z~D
1 2
3
W=15mils
R503
100K_0402_5%~D
1 2
AUD_LINE_OUT_R
4
VSUP
EXT_MIC_BIAS
3
2
OUT
1
NB_MICIN
EXT_MIC_PLUG
EMICIN
EXT_MIC_PLUG
EXT_MIC_BIAS
EMICIN
+5VRUN
FAN1_VOUT FAN1_TACH_FB
AUD_LINE_OUT_L
JAUDO
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
13
13
14
15
15
16
17
17
18
19
19
20
NAIS_AXN320C038P~D
2
4
6
8
10
12
14
16
18
20
VDDA +3VRUN
L46
BLM11A121S_0603~D
1 2
2
1
Q38
2N7002_SOT23~D
C_INT_MICÂC_INT_MIC+
C_EXT_MIC+
2
C545
0.1U_0402_16V4Z~D
1
U13
5
INT_MIC-
6
INT_MIC+
7
GND
8
EXT_MIC_IN
CMAMP110M_MSOP8~D
HP_NB_SENSE
HP_OUT_LMAX
HP_OUT_RMAX
2
+3VRUN
12
R459
10K_0402_5%~D
C535
1U_0603_6.3V6M~D
1 2
1 2
C539
1U_0603_6.3V6M~D
1
C537
1U_0603_6.3V6M~D
2
HP_NB_SENSE
AUD_LINE_IN_R
AUD_LINE_IN_L
U38
14
SHDNR#
18
SHDNL#
15
INR
13
INL
1
C1P
3
C1N
C547
1U_0603_6.3V6M~D
19
PVss
5
1
2
PVDD
7
10
SVDD
SVss
2
1
2
OUTR
OUTL
NC-4
NC-6
NC-8
NC-12
NC-16
NC-20
PGND
SGND
MAX4411ETP-T_TQFN20~D
17
1
C529
1U_0603_6.3V6M~D
HP_OUT_RMAX
11
HP_OUT_LMAX
9
4
6
8
12
16
20
60mil single end connection near JACK
1
2
3
4
5
6
7
8
1
2
LA-1711
1
JSPK
MOLEX_53398-0890~D
9
9
1
2
3
4
5
6
7
8
10
10
D9
DDA204U@
3
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
D8
1
DDA204U@
3
2
A00-B
25 65Wednesday, January 28, 2004
TRACE>15 mil
INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_L1
L48
1 2
W=40mils
1
C626
0.1U_0402_16V4Z~D
B B
HP_OUT_R
HP_OUT_L
SPK_SHUTDOWN#
A A
5
2
1 2
1 2
1 2
1 2
C630
0.01U_0603_16V7K~D
C632
0.01U_0603_16V7K~D
C631
0.01U_0603_16V7K~D
C633
0.01U_0603_16V7K~D
1
C627
0.1U_0402_16V4Z~D
2
7
17
9
5
19
U18
RIN+
RIN-
LIN+
LIN-
SHUTDOWN
16
15
VDD
20
4
BLM21A05_0805
+5VAMPVCC
6
PVDD1
PVDD2
2
GAIN0
3
GAIN1
18
ROUT+
14
ROUT-
4
LOUT+
8
LOUT-
12
NC
10
BYPASS
GND41GND311GND213GND1
TPA6017A2PWPR_TSSOP20~D
+5VRUN
1
C628
10U_0805_10V4M~D
2
AUD_GAIN0
AUD_GAIN1
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
R632 0_0402_5%~D
1 2
BYPASS
1
C634
0.47U_0603_16V4Z
2
1
C629
0.1U_0402_16V4Z~D
2
1
@
2
AUD_GAIN0
AUD_GAIN1
C635
0.1U_0402_16V4Z~D
+5VRUN
12
12
GAIN0 GAIN1 AV(inv) INPUT
0
1
*
1 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
R582
10K_0402_5%~D
R584
10K_0402_5%~D @
0
1
0
Gain Setting
12
R583
10K_0402_5%~D@
12
R585
10K_0402_5%~D
6dB
10dB0
15.6dB
21.6dB
IMPEDANCE
90K ohm
70K ohm
45K ohm
25K ohm
2
INT_SPK_R1
+5VRUN
1 2
1 2
C638
4.7U_1206_16V6K~D
D7
1
2
C639
4.7U_1206_16V6K~D
INT_SPK_R1
INT_SPK_L2
INT_TWT_L1
INT_SPK_R2
INT_TWT_R1
D6
1
DDA204U@
3
Title
Size Document Number Rev
Date: Sheet of
DDA204U@
3
2
DELL CONFIDENTIAL/PROPRIETARY
AMP and Phone Jack Interface
Page 26
5
R8 0_0402_5%~D
1 2
L2
DLW21SN900SQ2_0805~D@
USBP5-
USBP5+
D D
USBP1+ USBP1_D+
USBP1-
USBP2-
USBP2+
USBP3-
C C
USBP3+
USBP4+
USBP4-
USBP6-
USBP6+
B B
A A
0.1U_0402_16V4Z~D
USB_EN#
1
4
R7 0_0402_5%~D
R408 0_0402_5%~D
DLW21SN900SQ2_0805~D@
1
4
R6 0_0402_5%~D
DLW21SN900SQ2_0805~D@
1
4
R5 0_0402_5%~D
R12 0_0402_5%~D
DLW21SN900SQ2_0805~D @
1
4
R11 0_0402_5%~D
R565 0_0402_5%~D
DLW21SN900SQ2_0805~D@
1
4
R566 0_0402_5%~D
R10 0_0402_5%~D
DLW21SN900SQ2_0805~D@
1
4
R9 0_0402_5%~D
+5VSUS
C268
0.1U_0402_16V4Z~D
+5VSUS
1
C269
2
1
2
4
3
1 2
1 2
L44
1
2
4
3
R407 0_0402_5%~D
1 2
1 2
L1
1
2
4
3
1 2
1 2
L4
1
2
4
3
1 2
1 2
L47
1
2
4
3
1 2
1 2
L3
1
2
4
3
1 2
1
2
5
2
3
2
3
2
3
2
3
2
3
2
3
1
2
1
2
1
@
2
1
2
1
@
2
1
@
2
U32
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
U31
1
GND
2
IN
3
EN1#
4
EN2#
TPS2062DR_SO8~D
C3
47P_0402_50V8J~D @
C462
47P_0402_50V8J~D
@
C2
47P_0402_50V8J~D
C8
47P_0402_50V8J~D @
C610
47P_0402_50V8J~D
C5
47P_0402_50V8J~D
8
OC1#
7
OUT1
6
OUT2
5
OC2#
8
OC1#
7
OUT1
6
OUT2
5
OC2#
USBP6_PWR
USBP5_PWR
1
@
2
1
@
2
1
@
2
1
2
1
@
2
1
2
USBP3_PWR
USBP2_PWR
C4
47P_0402_50V8J~D
C461
47P_0402_50V8J~D
C1
47P_0402_50V8J~D
C7
47P_0402_50V8J~D@
C611
47P_0402_50V8J~D
C6
47P_0402_50V8J~D@
USB_OC6#
USB_OC3#
4
USBP5_D-
USBP5_D+
USBP1_D+ USBP2_D+
USBP1_D-
USBP2_D-
USBP2_D+
USBP3_D-
USBP3_D+
USBP4_D+
USBP4_D-
USBP6_D-
USBP6_D+
USB_OC5#
USB_OC2#
PLACE CHOKE(Resistors)
NEAR CONNECTOR
USBP1_D-
USBP4_D+
USBP4_D-
DH_POWER_EN
4
PWR_SRC
1
2
+5VSUS
R17
10K_0402_5%~D
1 2
DH_POWER_EN#
13
D
Q4
2
G
2N7002_SOT23~D
S
JP3
1 2
PAD-OPEN 4x4m@
U48
1
VIN1
2
VIN2
3
VIN3
4
CDELAY
GND5CUR_LIMIT
LM3726SD/X_LLP10~D @
C675
0.1U_0603_25V7M~D @
If depop U48 circuit : JP3 short , JP4 open
If pop U48 circuit : JP3 open, JP4 short
VOUT10
VOUT9
VOUT8
GATE
3
USBP5_PWR
USBP2_PWR
USBP6_PWR
+5VSUS
R27
10K_0402_5%~D
1 2
13
D
Q1
2
G
2N7002_SOT23~D
S
10
9
8
7
6
1 2
R633 75K_0402_5%~D@
+5VSUS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
L27
BLM21PG600SN1D_0805~D
1 2
L30
BLM21PG600SN1D_0805~D
1 2
1 2
L24
BLM21PG600SN1D_0805~D
1 2
L25
BLM21PG600SN1D_0805~D
L29
BLM21PG600SN1D_0805~D
1 2
L28
BLM21PG600SN1D_0805~D
1 2
DAT_SMB
CLK_SMB
1 2
R634 100K_0402_5%~D@
1
+
C262
2
150U _D2_6.3VM~D
1
+
C261
2
150U _D2_6.3VM~D
1
+
C263
2
150U _D2_6.3VM~D
DAT_SMB
100K_0402_5%~D
DH_GATE
3726_ON
1
C292
2
0.022U_0603_50V4Z~D
1
C257
2
0.1U_0402_16V4Z~D
1
C258
2
0.1U_0402_16V4Z~D
1
C259
2
0.1U_0402_16V4Z~D
D
S
1 3
G
2
2
G
1 3
D
S
R318
1 2
12
R317
100K_0402_5%~D
13
D
S
2
USBP5_VCC
USBP5_DÂUSBP5_D+
USBP5_GND
USBP2_VCC
USBP2_D-
USBP2_GND
Q6
2N7002_SOT23~D
Q2
2N7002_SOT23~D
Q9
2N7002_SOT23~D
2
G
2
USBP6_VCC
USBP6_DÂUSBP6_D+
USBP6_GND
USBP3_PWR
DH_SMBDAT
DH_SMBCLKCLK_SMB
DH_PWR_SRC
36
241
578
Q66
SI4435DY_SO8~D
DH_PWRSRC
DH_POWER_EN
R307
100K_0402_5%~D
JUSB1
1
2
3
4
SUYIN_2569A-04G3T
JUSB2
1
2
3
4
SUYIN_2569A-04G3T
JUSB3
1
2
3
4
SUYIN_2569A-04G3T
L31
BLM21PG600SN1D_0805~D
1 2
C265
150U _D2_6.3VM~D
1 2
L26
BLM21PG600SN1D_0805~D
1
+
C677
5.6U_B2_25VM_R100~D@
2
F1
1.8A_33VDC_SMD185~D
1 2
JP4
1 2
PAD-OPEN 4x4m@
DH_PWR_OC#
12
1
DESTINATION
USBP3_VCC
USBP3_DÂUSBP3_D+
USBP3_GND
DH_PORT_PWRSRC
DH_SMBDAT
DH_SMBCLK
1
+
@
2
Reserved
BT
BACK
DOG
MOD
BACK
BACK
Reserved
1
2
3
4
5
6
7
8
9
10
11
12
13
C679
5.6U_B2_25VM_R100~D
1
+
2
USB PORT#
2
C260
0.1U_0402_16V4Z~D
1
DH_MOD_PRES#
1
+
C678
5.6U_B2_25VM_R100~D
@
2
0
1
2
3
4
5
6
7
Dell request 10/09
L5
DH_FUSE_PWRSRC
R306
1 2
100K_0402_5%~D
2
Title
Size Document Number Rev
Date: Sheet of
BLM21PG600SN1D_0805~D
12
R316
10K_0402_5%~D
DH_PWRSRC_OC
13
D
Q64
2N7002_SOT23~D
S
1 2
+3VRUN
G
DELL CONFIDENTIAL/PROPRIETARY
USB(2.0) Connector
DH_PWRSRC_OC
LA-1711
1
DH_PORT_PWRSRC
0.1U_0603_25V7M~D
26 65Wednesday, January 28, 2004
JDOG
T1
T2
T3
T4
PWR_SRC
SMB_DATA
SMB_ALERT
SMB_CLK
GND
SHILD1
SHILD2
SHILD3
SHILD4
FOX_UB11193-P01-TR~D
1
C9
2
A00-B
Page 27
5
4
3
2
1
MDC cable wire clip
PAD1
1
D D
C C
B B
MDC_CLIP
PAD2
MDC_CLIP
PAD3
MDC_CLIP
1
JMDC
2
AUDIO_PWDN
4
MONO_PHONE
6
RESERVED
8
GND
10
+5V
12
RESERVED
14
RESERVED
16
PRIMARY_DN
18
RESERVED
20
RESERVED
22
AC97_SYNC
24
AC97_SDATA_IN1
26
AC97_SDATA_IN0
28
GND
30
AC97_BITCLK
AMP_3-1612118-0~D
0.1U_0402_16V4Z~D
COEX2_WLAN_ACTIVE
HW_RADIO_DIS#
COEX1_BT_ACTIVE
COEX3
USBP1_DÂUSBP1_D+
MONO_OUT/PC_BEEP
AC97_SDATA_OUT
1
BT_ACTIVE
10K_0402_5%~D@
+3VSUS
ICH_AC_SDIN1
7/28 Changed to NP
by Dell's require
1 2
ICH_AC_SYNC
MDC_AC_BITCLK
R449
1
2
R457
33_0402_5%~D
1 2
C527
22P_0402_50V8J~D
@
T2
PAD
@
MDM_MONO_PHONE
Z2602
12
R454
MDC_SDIN
10K_0402_5%~D@
COEX2_WLAN_ACTIVE
HW_RADIO_DIS#
COEX1_BT_ACTIVE
USBP1_DÂUSBP1_D+
1
C459
2
R412
AGND
AUXA_RIGHT
AUXA_LEFT
CD_GND
CD_RIGHT
CD_LEFT
GND
3.3Vaux
GND
3.3Vmain
AC97_RESET#
GND
AC97_MSTRCLK
+3VSUS
12
10K_0402_5%~D@
12
L43
BLM11A601S_0603~D
BT_PWR
JBT
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JST_BM10B-SRSS-TB~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
12
12
11
11
W=20 mil
Z2604
12
R463
0_0402_5%~D @
+3VSUS
1 2
R458
C159
10_0402_5%~D@
FOX_HS6210_10P
1
1
C525
2
2
0.1U_0402_16V4Z~D
4.7U_1206_16V6K~D
ICH_AC_SDOUT
ICH_AC_RST#
1
10
TOP view
R462
10_0402_5%~D@
1 2
ICH_AC_SDOUT_MDCTERM
2
C526
10P_0402_50V8J~D
@
1
MDC_AC_BITCLK_TERM
2
C530
10P_0402_50V8J~D
@
A A
5
4
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
BT PORT and MDC
LA-1711
1
27 65Wednesday, January 28, 2004
A00-B
Page 28
+3VSRC
SI3456DV-T1_TSOP6~D
ENAB_3VLAN
D D
V_1P2_LAN
Place within 100 mils to pins H14
PCI_AD[0..31]
C C
B B
V_3P3_LAN
SYS_PME#
A A
CK_33M_LANPCI
Q18
D
6
2
1
G
L33
BLM11A601S_0603~D
1 2
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_AD16
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
CK_33M_LANPCI
R319
10_0402_5%~D@
5
S
VAUX_LAN
45
3
C11
2.2U_0805_16VFZ~D
R49
100_0402_5%~D
1 2
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_PIRQC#
PCIRST_1#
PCI_GNT4#
PCI_REQ4#
R303
1K_0402_5%~D
SYS_PME#
CLK_82540_TERM
12
5
V_1P2_PLLVDD_PHY
2
C17
1
0.1U_0402_16V4Z~D
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
LAN_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PAR
CK_33M_LANPCI
PCI_PIRQC#
PCIRST_1#
PCI_GNT4#
PCI_REQ4#
LAN_AUXPWR
12
L37
BLM31A260SPT_1206~D
1 2
20mils trace width
1
2
C321
8.2P_0402_50V8J~D@
1 2
2
2
C343
C350
+3V_LOM_PCI
U2A
B8
AD31
A8
AD30
C7
AD29
C6
AD28
B6
AD27
B5
AD26
A5
AD25
B4
AD24
B2
AD23
B1
AD22
C1
AD21
D3
AD20
D2
AD19
D1
AD18
E3
AD17
K1
AD16
L2
AD15
L1
AD14
M3
AD13
M2
AD12
M1
AD11
N2
AD10
N3
AD9
P3
AD8
N4
AD7
P4
AD6
M5
AD5
N5
AD4
P5
AD3
P6
AD2
M7
AD1
N7
AD0
C4
CBE3
F3
CBE2
L3
CBE1
M4
CBE0
A4
IDSEL
F2
FRAME
F1
IRDY
G3
TRDY
H3
DEVSEL
H1
STOP
J2
PERR
A2
SERR
J1
PAR
A3
PCI_CLK
H2
INTA
C2
PCI_RST
J3
GNT
C3
REQ
J12
VAUXPRSNT
F4
M66EN
A6
PME
BCM5705M_FBGA196~D1@
C281
1
1
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
C310
BCM5705M
5705M :1.24K_0402_1%
4401: 1.27K_0402_1%
2
C282
1
0.1U_0402_16V4Z~D
2
C315
1
0.1U_0402_16V4Z~D
OR
BCM4401
4
2
2
C272
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
C330
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2@ BCM4401
4
2
C275
C278
1
0.1U_0402_16V4Z~D
2
C340
C323
1
0.1U_0402_16V4Z~D
E13
TRD3+
E14
TRD3-
D13
TRD2+
D14
TRD2-
C13
TRD1+
C14
TRD1-
B13
TRD0+
B14
TRD0-
B9
B10
A9
B11
C11
C10
P1
VESD1
G2
VESD2
A1
VESD3
P10
EEDATA
M10
EECLK
H12
GPIO0
K13
GPIO1
J13
GPIO2
G13
H13
G12
G14
H14
P7
NC
C12
TCK
D12
TDI
B12
TDO
A12
TMS
D11
TRST
J14
N10
XTALO
N11
XTALI
G11
SO
E10
SI
E11
SCLK
H11
CS
A14
D10
RDAC
A10
C9
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
LAN_CTRL_2P5V
LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_GPIO0
LAN_EEPROM_W
LAN_GPIO2
2
C286
1
0.1U_0402_16V4Z~D
2
C341
1
0.1U_0402_16V4Z~D
REGSUP12
REGCTL12
REGSEN12
REGSUP25
REGCTL25
REGSEN25
LINKLEDB
SPD100LEDB
SPD1000LEDB
TRAFFICLEDB
PLLVDD2
XTALVDD
BIASVDD
SMB_CLK
SMB_DATA
Place within 50 mils of
ASIC pin D10
8-10mils trace width
BCP69
V_3P3_LAN
BCP69_SOT-2231@
LAN_CTRL_2P5V
LAN_TX3+
LAN_TX3ÂLAN_TX2+
LAN_TX2ÂLAN_RX1+
LAN_RX1ÂLAN_TX0+
LAN_TX0-
V_2P5_LAN
V_1P2_LAN
V_3P3_LAN
V_2P5_LAN
+3V_LOM_PCI
T8 PAD@
T7 PAD@
LINK_LED_10#
LINK_LED_100#
LINK_LED_1000#
LAN_ACT#
R310
12
V_2P5_LAN
25MHz_20P_1BX25000CK1A~D
2
C18
1
12
R311
1.24K_0402_1%~D 1@
2@ 1.27K_0402_1%~D
B
Q65
1
X1
22P_0402_50V8J~D
2
C271
1000P_0402_50V7K~D
1
Place within 100 mils of ASIC
pin A14, 10mils trace width
V_3P3_LAN
LAN_TX3+
LAN_TX3ÂLAN_TX2+
LAN_TX2ÂLAN_RX1+
LAN_RX1ÂLAN_TX0+
LAN_TX0-
LAN_CTRL_1P2V
LINK_LED_10#
LINK_LED_100#
LINK_LED_1000#
LAN_ACT#
V_1P2_PLLVDD_PHY
4.7K_0402_1%~D
LAN_TRST#
XTALO
R631 0_0402_5%~D
1 2
XTALI
22P_0402_50V8J~D
Place within 100 mils to pins N10 and N11
LAN_BIAS
LAN_RDAC
LAN_SMBCLK
LAN_SMBDATA
3
V_2P5_LAN
3
2
2
1
V_1P2_LAN
2
C25
C291
1
10U_1206_6.3V7K~D
4
1
C266
C267
2
10U_1206_6.3V7K~D
V_2P5_LAN
E12
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L5
L10
M14
N14
P8
P12
P13
P14
A7
B3
C5
E1
E4
G1
K3
L4
N6
P2
K14
L13
P11
A11
F11
K12
L12
C8
H4
H10
J4
K4
J11
K11
L7
L8
0.1U_0402_16V4Z~D
10U_1206_6.3V7K~D
U2B
VDDC_E12
VDDC_H5
VDDC_H6
VDDC_H7
VDDC_H8
VDDC_J5
VDDC_J6
VDDC_J7
VDDC_J8
VDDC_J9
VDDC_J10
VDDC_K5
VDDC_K6
VDDC_K7
VDDC_K8
VDDC_K9
VDDC_K10
VDDC_L5
VDDC_L10
VDDC_M14
VDDC_N14
VDDC_P8
VDDC_P12
VDDC_P13
VDDC_P14
VDDIO-PCI_A7
VDDIO-PCI_B3
VDDIO-PCI_C5
VDDIO-PCI_E1
VDDIO-PCI_E4
VDDIO-PCI_G1
VDDIO-PCI_K3
VDDIO-PCI_L4
VDDIO-PCI_N6
VDDIO-PCI_P2
VDDP_K14
VDDP_L13
VDDP_P11
VDDIO_A11
VDDIO_F11
VDDIO_K12
VDDIO_L12
CSTSCHG
CLKRUN
NC_H10
NC_J4
NC_K4
NC_J11
NC_K11
NC_L7
NC_L8
BCM5705M_FBGA196~D1@
C
2
C1E
4
3
C332
3
2
4
C333
LAN_SMBCLK
LAN_SMBDATA
+3V_LOM_PCI
12
2
C34
1
1 2
L35
BLM11A601S_0603~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
LAN_CTRL_1P2V
2
2
C316
1
1
0.1U_0402_16V4Z~D
10U_1206_6.3V7K~D
1
1
C344
2
2
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
LAN_SMBCLK
LAN_SMBDATA
V_3P3_LAN +3VRUN
L39
1 2
10U_1206_6.3V7K~D
V_2P5_LAN
C312
Q5
BCP69_SOT-2231@
1
2
2
C270
C279
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
BLM11A601S_0603~D2@
0.1U_0402_16V4Z~D
L38
1 2
BLM11A601S_0603~D 1@
2
C349
1
V_2P5_LAN
V_3P3_LAN
5705M_CLKRUN#
R321
1 2
10K_0402_5%~D
Should be pulled down for both 4401 and 5705M
2
1
2
1
C328
1
2
0.1U_0402_16V4Z~D
BCM5705M
2
2
C335
C283
1
0.1U_0402_16V4Z~D
OR
BCM4401
2
2
1
0.1U_0402_16V4Z~D
AVDDL_F12
AVDDL_F13
LOW_POWER
2@ BCM4401
2
C320
C313
1
0.1U_0402_16V4Z~D
VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9
VSS_F10
VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9
VSS_G10
VSS_H9
VSS_K2
VSS_L6
VSS_L9
VSS_M6
VSS_M12
VSS_M13
VSS_N1
VSS_N12
VSS_N13
AVDD_F14
AVDD_A13
NC_L11
NC_L14
NC_M8
NC_M9
NC_N8
NC_N9
NC_P9
1
Alcatraz 5705MNimitz 4401
Depop Depop
@
1@
Depop
2@
Pop
DepopPop
R311(1.24K_1%)R311(1.27K_1%)
L32(H5015T)L32(H1238)
2
2
2
2
C326
C274
1
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS
B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13
F12
F13
F14
A13
L11
L14
M8
M9
M11
N8
N9
P9
LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS
LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_SPROM_DOUT
LAN_SPROM_DIN
AVDD1P2
AVDD2P5
C273
5705M_LOWPWR
R313 0_0402_5%~D 2@
R308 0_0402_5%~D2@
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
2
C307
C314
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
No pullup for 16KB
Pullup for 16KB
R299 is poped for 4401 with AT93C86 (16KB)
R299 is poped for 5705M EEPROM 376KHz mode
R299 is depop for 4401 with AT93C46 (1KB)
12
R302
R299
10K_0402_5%~D1@
1 2
1 2
1@
2
2
C20
1
1
1U_0805_10V6K~D
0.1U_0402_16V4Z~D1@
R300 0_0603_5%~D1@
1 2
1 2
1 2
2
2
C318
C306
4.7K_0402_5%~D1@
L36
BLM11A601S_0603~D
L6
BLM11A601S_0603~D
Place within 100 mils of ASIC
pins, 10-20mils trace width
1
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V_3P3_LAN
12
12
R296
1K_0402_5%~D 1@
U34
1
CS
VCC
2
SK
3
DI
ORG
4
DO
GND
AT93C46-10SI-2.7_SO8~D2@
POP
4401
LAN_SPROM_DOUT
LAN_SPROM_DIN
C309
ETHERNET
LA-1711
1
V_1P2_LAN
2
2
C285
C293
1
1
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D1@
POP
5705
U33
VCC
WP
SCL
SDA
AT24C256N-10SC_SO81@
8
7
6
5
28 65
0.1U_0402_16V4Z~D
A0
A1
NC
GND
V_3P3_LAN
12
1
2
0.1U_0402_16V4Z~D
5705M4401Signal
Pullup for 376KHz mode
No pullup
C277
8
7
6
5
NC
V_1P2_LAN
V_2P5_LAN
LAN_LOW_PWR
2
1
1
2
3
4
10K_0402_5%~D2@
R312
0.01U_0402_16V7K~D 2@
C311
A00-B
Page 29
5
V_2P5_LAN
Magnetics pop options
4401: H1238
5705M: H5015D
D D
LAN_TX3-
LAN_TX3-
2
C16
0.01U_0402_16V7K~D
1@
1
L32
1
1:1
2
4
Z2805
24
NB_LAN_TX3-
23
3
V_2P5_LAN
R20 49.9_0603_1%~D
1 2
R19 49.9_0603_1%~D
1 2
R22 49.9_0603_1%~D
1 2
R21 49.9_0603_1%~D
1 2
1 2
1 2
1 2
1 2
JST_SM05B-SRSS-TB~D
1@
JPH_RJ
1
1
2
2
6
6
7
7
5
5
R24 49.9_0603_1%~D
R23 49.9_0603_1%~D1@
R26 49.9_0603_1%~D1@
R25 49.9_0603_1%~D1@
RJ_RING
RJ_TIP
LAN_TX0ÂLAN_TX0+
LAN_RX1ÂLAN_RX1+
LAN_TX2ÂLAN_TX2+
LAN_TX3ÂLAN_TX3+
2
B2
NB_LAN_TX+
NB_LAN_TXÂNB_LAN_RX+
NB_LAN_TX2+
NB_LAN_TX2ÂNB_LAN_RXÂNB_LAN_TX3+
NB_LAN_TX3-
RJ_TIP
RJ_RING
B1
A2
V_3P3_LAN
1
JLOM
B2
B1
YEL
GRN
A2
AMBER
1
P1_1
2
P1_2
3
P1_3
4
P1_4
5
P1_5
6
P1_6
7
P1_7
8
P1_8
SGND1
SGND2
RJ45/LED
10
P2_2
9
P2_1
RJ11
FOX_JM34F23-P3552-TR~D
LAN_ACTLED_YEL#
B3
LED_10_GRN#
A3
LED_100_ORG#
A1
17
18
C264
1 2
22
21
20
19
18
17
16
15
14
NB_LAN_TX3+
Z2806
NB_LAN_TX2-
NB_LAN_TX2+
Z2807
NB_LAN_RX-
NB_LAN_RX+
Z2808
NB_LAN_TX-
NB_LAN_TX+
3 6
4 5
RN6
75_1206_8P4R_5%~D
1 8
2 7
D22
Q3
2N7002_SOT23~D
1
2
3
12
R602
10K_0402_5%~D
2
3
1
2
3
12
R601
10K_0402_5%~D
1
BAT54A_SOT23~D
D11
RB495D_SOT23~D
V_3P3_LAN
V_3P3_LAN
2
1 2
V_3P3_LAN
LAN_ACT#
13
D
WLAN_LED_ACTIVITY
LINK_LED_100#
LED_WLAN5_RADIOSTATE
LED_WLAN24_RADIOSTATE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
R600
10K_0402_5%~D
LINK_LED_10#
RB495D_SOT23~D
R309
10K_0402_5%~D
R294
10K_0402_5%~D
2
G
S
D10
12
12
R33
10K_0402_5%~D
12
R32
150_0402_5%~D
R305
1 2
10K_0402_5%~D1@
R304
10K_0402_5%~D
1 2
R295
10K_0402_5%~D
1 2
V_3P3_LAN
LAN_ACTLED_YEL#
V_3P3_LAN
12
R297
10K_0402_5%~D
V_3P3_LAN
12
R293
10K_0402_5%~D
D12
3
1
2
1@
RB495D_SOT23~D
13
Q63
DTC144EKA_SOT23~D
47K
2
47K
13
Q62
DTC144EKA_SOT23~D
47K
2
47K
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
LINK_LED_1000#
R292
200_0402_5%~D
1 2
R298
200_0402_5%~D
1 2
LAN TRANSFOMER
LA-1711
1
LED_100_ORG#
LED_10_GRN#
29 65Wednesday, January 28, 2004
A00-B
LAN_TX3+
LAN_TX2-
C C
LAN_TX2+
LAN_RX1-
LAN_RX1+
LAN_TX0-
B B
LAN_TX0+
LAN_TX3+
LAN_TX2-
2
C14
0.01U_0402_16V7K~D
1@
1
LAN_TX2+
LAN_RX1-
2
C13
0.01U_0402_16V7K~D
1
LAN_RX1+
LAN_TX0-
2
C15
0.01U_0402_16V7K~D
1
LAN_TX0+
DTC144EKA
1
C
2 3
3
T1
4
1:1
5
6
T5
T2 T6
7
1:1
8
9
T3 T7
10
1:1
11
12 13
T4 T8
H5015D~D1@
2@ H1238
EB
1000P_1808_3KV7K~D
A A
@
Depop Depop
1@
Depop
2@
Alcatraz 5705MNimitz 4401
GND
Pop
DepopPop
5
CHASIS
4
Page 30
5
PCI_AD[0..31]
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
D D
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
C C
CK_33M_CBPCI
PCI_AD17
PCI_PAR
PCI_DEVSEL#
PCI_FRAME#
PCI_GNT1#
PCI_IRDY#
PCI_PERR#
PCI_REQ1#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCIRST_CB#
CBS_GRST#
1 2
R481 10K_0402_5%~D @
R470 100_0402_5%~D
1 2
@
R163
10_0402_5%~D
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_PAR
PCI_DEVSEL#
PCI_FRAME#
PCI_GNT1#
PCI_IRDY#
PCI_PERR#
PCI_REQ1#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCIRST_CB#
CBS_GRST# IRQ_SERIRQ
CBS_IDSEL
U9A
J5
AD31
J6
AD30
K2
AD29
K3
AD28
K5
AD27
K6
AD26
L2
AD25
L3
AD24
M2
AD23
M3
AD22
M6
AD21
M5
AD20
N2
AD19
N3
AD18
N6
AD17
P1
AD16
R6
AD15
P7
AD14
V5
AD13
U6
AD12
V6
AD11
R7
AD10
P8
AD9
U7
AD8
W7
AD7
R8
AD6
U8
AD5
V8
AD4
W9
AD3
V9
AD2
U9
AD1
R9
AD0
L6
C/BE3#
P2
C/BE2#
U5
C/BE1#
V7
C/BE0#
W4
PAR
R2
DEVSEL#
N5
FRAME#
J1
GNT#
P3
IRDY#
R3
PERR#
J2
REQ#
T1
SERR#
P5
STOP#
P6
TRDY#
H3
PRST#
H2
GRST#
L5
IDSEL
H1
PCLK
PCI4510GHK_PBGA209~D
PCI4510
CSTSCHG/BVD1(STSCHG#/RI#)
1 2
B B
+3VSUS
CK33M_CBS_TERM
2
C139
4.7P_0402_50V8C~D @
1
A A
C160
+3VSUS
C562
L13
BLM21A601SPT_0805~D
1 2
2
1
0.047U_0402_10V4M~D
L15
BLM21A601SPT_0805~D
1 2
1
2
0.1U_0402_16V4Z~D
2
C536
C164
1
10U_0805_10V4M~D
1
C173
C532
2
0.1U_0402_16V4Z~D
4
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD6/D13
CAD4/D12
CAD2/D11
CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#
CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16
CCLKRUN#/WP(IOIS16#)
CBLOCK#/A19
CINT#/READY(IREQ#)
CAUDIO/BVD2(SPKR#)
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#
CRSVD/D2
CRSVD/A18
CRSVD/D14
1
2
C542
2
1
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1
1
C172
2
2
10U_0805_10V4M~D
10U_0805_10V4M~D
E8
C8
B8
E9
F9
F11
E11
C11
A12
C12
E12
C13
A14
E13
B14
F18
G17
F19
G18
H15
H14
H17
H18
J14
J17
CAD7/D7
K14
J19
CAD5/D6
K17
K15
CAD3/D5
L14
K18
CAD1/D4
L15
CAD0/D3
B11
C14
G15
J15
B13
B15
F13
E14
A16
E17
F15
E10
F14
B12
D19
C15
A9
B9
E18
C10
F10
C9
L17
F12
B10
F8
F17
J18
+3V_CBSA
2
C544
1
0.047U_0402_10V4M~D
1
C521
2
0.047U_0402_10V4M~D
CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#
CBS_CCLK_INTERNAL
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CCD2#_INTERNAL
CBS_CCD1#_INTERNAL
CBS_CVS2
CBS_CVS1
CBS_RSVD/D2
CBS_RSVD/A18
CBS_RSVD/D14
1
C522
C524
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1
C533
2
0.047U_0402_10V4M~D
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CVS2
CBS_CVS1
CBS_RSVD/D2
CBS_RSVD/A18
CBS_RSVD/D14
1
C556
2
0.047U_0402_10V4M~D
CBS_CAD[0..31]
+3V_CBSD
R191
1 2
0_0402_5%~D
@
R188
1 2
0_0402_5%~D
+3V_CBSD
1
C543
2
0.047U_0402_10V4M~D
R177
R186
1
2
1 2
0_0402_5%~D
@
1 2
0_0402_5%~D
R494
12
47_0402_5%~D
R516
0_0402_5%~D
270P_0603_50V7K~D@
C566
3
R174
1 2
0_0402_5%~D
@
R171
1 2
0_0402_5%~D
IEEE1394_TPA0N
CBS_CCLK
R482
0_0402_5%~D
1 2
1 2
2
2
270P_0603_50V7K~D
C540
1
1
@
R495
1M_0603_5%~D@
1 2
1 2
R487
6.34K_0603_1%~D
IEEE1394_TPA0P
1K_0402_5%~D @
@
1K_0402_5%~D
IEEE1394_TPB0P
IEEE1394_TPB0N
IEEE1394_TPBIAS0
1U_0805_10V6K~D
CBS_CCLK
CBS_CCD1#
CBS_CCD2#CBS_CCLKRUN#
0.1U_0402_10V6K~D
SCR_IF_GPIO5
SCR_IF_GPIO4
SCR_IF_GPIO3
SCR_IF_GPIO2
SCR_DETECT
SCR_IF_RST
SCR_IF_CLK
SCR_IF_DATA
SCR_IF_PWR
SCR_IF_GPIO0
SCR_IF_GPIO1
+3V_CBSA
1K_0402_5%~D
10K_0402_5%~D
1 2
R507
R496
C167
C557
1 2
R483
12
R510
12
12
R502
12
1K_0402_5%~D
R486
12
1K_0402_5%~D
R515
12
1K_0402_5%~D@
12
+3V_CBSA
+3V_CBSA
Remove R756
8/12 Changed by
Dell's Require
PHY_CPS
PHY_CNA
CBS_PC0
CBS_PC1
CBS_PC2
PCI4510_R0
PCI4510_R1
IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPA1P
IEEE1394_TPA1N
IEEE1394_TPB0P
IEEE1394_TPB0N
IEEE1394_TPB1P
IEEE1394_TPB1N
IEEE1394_TPBIAS0
IEEE1394_TPBIAS1
FILTER0
FILTER1
SCR_IF_GPIO5
SCR_IF_GPIO4
SCR_IF_GPIO3
SCR_IF_GPIO2
SCR_DETECT
SCR_IF_RST
SCR_IF_CLK
SCR_IF_DATA
SCR_IF_PWR
SCR_IF_GPIO0
SCR_IF_GPIO1
1
C560
2
0.1U_0402_16V4Z~D
2
U9B
P10
CPS
P17
CNA
V10
PC0
W10
PC1
P9
PC2
W13
R0
V13
R1
V12
TPA0P
W12
TPA0N
V15
TPA1P
W15
TPA1N
V11
TPB0P
W11
TPB0N
V14
TPB1P
W14
TPB1N
U12
TPBIAS0
U15
TPBIAS1
R11
AVD2
U13
AVD3
U14
AVD4
U11
AGN2
R12
AGN3
R13
AGN4
P15
VDPLL
N14
VSPLL
T19
FILTER0
R17
FILTER1
N15
MC_RSVD1
M14
MC_RSVD2
N17
MC_RSVD3
N18
MC_RSVD4
N19
MC_RSVD5
M15
MC_RSVD6
M17
MC_RSVD7
M18
MC_RSVD8
M19
MC_RSVD9
B7
SC_CD#
C7
SC_RST
F7
SC_CLK
A6
SC_DATA
B6
SC_PWR
E7
SC_MODE
C6
SC_FCB
PCI4510GHK_PBGA209~D
+1.8V_CBSD
1
C520
2
0.1U_0402_16V4Z~D
PCI4510
8/12 Changed by
Dell's Require
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCCCB1
VCCCB2
VCCP1
VCCP2
1.8V_1
1.8V_2
VD1/VCCD0#
VD0/VCCD1#
VD3/VPPD0
VD2/VPPD1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
VR_EN#
SUSPEND#
RI_OUT#/PME#
SPKROUT
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PHY_TEST_MA
TEST0
TEST1
CLK_48_RSVD
R444
220_0402_5%~D
R165
220_0402_5%~D
G1
M1
R1
W8
L19
H19
E19
A13
A8
A5
G14
A11
L1
W5
G2
L18
E6
B5
A4
C5
E1
K1
N1
W6
P19
K19
G19
A15
A10
A7
H5
G3
J3
E2
F5
G6
F3
F2
G5
F1
H6
E3
SCL
D1
SDA
P18
U10
R10
F6
R18
XI
R19
XO
CBS_SCL
12
CBS_SDA
12
+3V_CBSD
+1.8V_CBSD
This shall be output
CBS_VCCD0#
CBS_VCCD1#
CBS_VPPD0
CBS_VPPD1
1V8_VR_EN#
TI_SUSPEND#_INTERNAL
SYS_PME#
CBS_SPK
PCI_PIRQD#
PCI_PIRQC#
PCI_REQB#
CBS_RI#
PCI_GNTB#
CBS_MFUNC6
CBS_SCL
CBS_SDA
PHY_TEST_MA
CBS_TEST0
CBS_TEST1
CK_48M_SCR
PCI4510XI
PCI4510XO
24.576MHz_16P_1BG24576CKIA~D
R504 4.7K_0402_5%~D
R450 200_0402_5%~D
R447 200_0402_5%~D
X3
1 2
CBS_SPK
PCI_REQB#
IRQ_SERIRQ
CBS_RI#
PCI_GNTB#
1
C184
2
22P_0402_50V8J~D
R445
2.7K_0603_5%~D@
12
12
R164
2.7K_0603_5%~D@
C185
+3V_CBSD
1
R452
10K_0402_5%~D@
12
R451
0_0402_5%~D
12
R446
10K_0402_5%~D
12
2 1
D15
RB751V_SOD323~D
SYS_PME#
PCI_PIRQD#
PCI_PIRQC#
1 2
R455 10K_0402_5%~D
12
12
12
1 2
1
CK48M_CBS_TERM
2
2
22P_0402_50V8J~D
1
CBS_VCC
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C541
1
1
2
2
+3V_CBSD
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C531
2
2
1
1
+3V_CBSD
+3V_CBSD
TI_SUSPEND#
+3V_CBSD
+3V_CBSD
CK_48M_SCR
R453
10_0402_5%~D
@
C523
4.7P_0402_50V8C~D
@
C538
C555
ST: Due to Nimitz and Alcatraz no support smart card,used PCI4510
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
PCMCIA Controller
LA-1711
1
30 65Wednesday, January 28, 2004
A00-B
Page 31
5
D D
C C
SCR_IF_GPIO2
SCR_IF_GPIO3
SCR_IF_GPIO0
SCR_IF_PWR
SCR_IF_GPIO1
SCR_IF_GPIO5
SCR_IF_RST
SCR_IF_DATA
SCR_IF_GPIO4
SCR_IF_CLK
+3VSUS
1
C174
2
10U_1206_6.3V7K~D@
B B
+12V
+5VSUS
A A
+3VSUS
SCR_DETECT
1
C182
2
0.1U_0402_16V4Z~D@
1
C144
0.1U_0402_16V4Z~D
2
1
C156
0.1U_0402_16V4Z~D
2
1
C155
0.1U_0402_16V4Z~D
2
T3
PAD
@
T4
PAD
@
SCR_IF_GPIO2
SCR_IF_GPIO3
SCR_IF_GPIO0
SCR_IF_PWR
SCR_IF_GPIO1
SCR_IF_GPIO5
SCR_IF_RST
SCR_IF_DATA
SCR_IF_GPIO4
SCR_IF_CLK
5
NC_SCR_C4
NC_SCR_C8
SCR_DETECT
U10
9
12V
5
5V_1
6
5V_2
3
3.3V_1
4
3.3V_2
1
2
3
4
5
6
7
8
9
10
12
R173
10K_0402_5%~D
U17
A0
A1
PGM#
PWR_ON
STATUS
CS#
RESET#
I/O
INT#
CLOCK_IN
NCN6000_TSSOP20~D@
AVCC1
AVCC2
AVCC3
AVPP
VCCD0#
VCCD1#
VPPD0
VPPD1
OC#
GND
SHDN#
TPS2211ADBR_SSOP16~D
7
16
R172
R194
0_0402_5%~D @
R193
0_0402_5%~D @
13
12
11
10
1
2
15
14
8
SCR_C4_C
12
SCR_C8_C
12
SCR_DETECT_C
12
0_0402_5%~D
12
R170
10K_0402_5%~D@
CBS_VCCD0#
CBS_VCCD1#
CBS_VPPD0
CBS_VPPD1
C175
0.1U_0402_16V4Z~D@
VBAT
LOUT_H
LOUT_L
PWR_GND
GROUND
CRD_VCC
CRD_IO
CRD_CLK
CRD_RST
CRD_DET
SCR_VCC_C
C150
4.7U_1206_16V6K~D
@
Place near connectorPlace near NCN6000
TPS2211VCC
1
C145
2
4.7U_1206_16V6K~D
SUSPWROK_5V
1
2
1
2
1
2
4
Depop if support Smart Card
SCR_VCC_C
Place near ncn6000
+3VSUS
20
LOUT_H
19
LOUT_L
18
17
16
15
14
13
12
11
1
C149
2
0.1U_0402_16V4Z~D@
L10
BLM31A260SPT_1206~D
1 2
C143
4.7U_1206_16V6K~D
1
C142
2
0.1U_0402_16V4Z~D
CBS_VCCD0#
CBS_VCCD1#
CBS_VPPD0
CBS_VPPD1
4
+3VSUS
L14
22U_LQH43MN220J01K_2OHM_1812~D@
1 2
SCR_VCC_C
SCR_DATA_C
SCR_CLK_C
SCR_RST_C
SCR_DETECT_C
SCR_RST_C SCR_CLK_C
1
C151
C137
12
2
R187
22K_0402_5%@
470P_0402_50V7K~D
@
1
1
C135
2
2
0.1U_0402_16V4Z~D
10U_1206_6.3V7K~D
C154
56P_0402_50V8J~D@
1
C136
2
1000P_0402_50V7K~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
2
3
R468
R464
R202
R203
R201
R200
R461
IEEE1394_TPBIAS0
IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPB0P
IEEE1394_TPB0N
12
R189
22K_0402_5%@
CBS_VCC
CBS_VPP
AVPP:150mA
AVCC:1A
SCR_IF_GPIO0
12
SCR_IF_GPIO1
12
SCR_IF_GPIO2
12
SCR_IF_GPIO3
12
SCR_IF_GPIO4
12
SCR_IF_GPIO5
12
SCR_IF_PWR
12
12
R480
56.2_0603_1%~D
R460
1 2
56.2_0603_1%~D
2
C528
1
270P_0603_50V7K~D
SHDN#
1
1
1
1
0
SHDN#
1
1
1
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Z3008
VPPD1
VCCD1#
R469
R456
R448
0
1
1
X
0
0
1
1
X
12
C163
56.2_0603_1%~D
IEEE1394_TPA0P
IEEE1394_TPA0N
IEEE1394_TPB0P
IEEE1394_TPB0N
1 2
56.2_0603_1%~D
1 2
5.1K_0603_1%~D
VPPD0
0
10
0
1
X
VCCD0#
0
1
0
1
X0
2
1
1U_0805_10V6K~D
100P_0402_50V8J~D @
CBS_VPP
CBS_VCC
+5VSUS
C656
1 2
0_0402_5%~D@
1 2
CBS_VPP
CBS_VCC
R204
0_0603_5%~D
1 2
R185
2
CBS_CCD2# CBS_CCLKRUN#
CBS_CAD31
CBS_CAD30
CBS_CAD28
CBS_CSTSCHNG
CBS_CAUDIO
CBS_CC/BE3#
CBS_CREQ#
CBS_CSERR# CBS_CAD22
CBS_CRST#
CBS_CVS2
SCR_VPP_PIN66
CBS_CAD19
CBS_CAD17
SCR_DATA_C
CBS_CFRAME#
CBS_CTRDY#
SCR_C8_C
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CBLOCK#
CBS_RSVD/A18
CBS_CAD16
CBS_CAD15
CBS_CAD13
CAGE50_GND
CBS_CVS1
CBS_CAD10
CBS_CAD8
CBS_RSVD/D14
CBS_CAD6
CBS_CAD4
CBS_CAD2
CBS_CCD1#
5
6
7
8
CBS_CCLK
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CVS2
CBS_CVS1
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
CBS_CCD1#
CBS_CCD2#
2
CBS_CCLK
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CRST#
CBS_CFRAME#
CBS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPERR#
CBS_CSERR#
CBS_CPAR
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CBLOCK#
CBS_CINT#
CBS_CAUDIO
CBS_CVS2
CBS_CVS1
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
CBS_CCD1#
CBS_CCD2#
JCBUS
40
80
40
80
39
79
39
79
38
78
38
78
37
77
37
77
36
76
36
76
35
75
35
75
34
74
34
74
33
73
33
73
32
72
32
72
31
71
31
71
30
70
30
70
29
69
29
69
28
68
28
68
27
67
27
67
26
66
26
66
25
65
25
65
24
64
24
64
23
63
23
63
22
62
22
62
21
61
21
61
20
60
20
60
19
59
19
59
18
58
18
58
17
57
17
57
16
56
16
56
15
55
15
55
14
54
14
54
13
53
13
53
12
52
12
52
11
51
11
51
10
50
10
50
9
49
9
49
8
48
8
48
7
47
7
47
6
46
6
46
5
45
5
45
4
44
4
44
3
43
3
43
2
42
2
42
1
41
1
41
82
G81G
84
G83G
86
858586
FOX_QT8R080A-1910_LB~D
L7
5
6
7
8
857CM-0009~D@
0_0402_5%~D
1 2
0_0402_5%~D
1 2
0_0402_5%~D
1 2
0_0402_5%~D
1 2
4
4
3
3
2
2
1
1
R144
R145
R146
R147
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
CBS_RSVD/D2
CBS_CAD29
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
SCR_DETECT_C
CBS_CAD23
SCR_VCC_C
CBS_CAD21
CBS_CAD20
SCR_RST_C
CBS_CAD18
CBS_CC/BE2#
SCR_CLK_C
CBS_CIRDY#
CBS_CCLK
SCR_C4_C
CBS_CINT#
CBS_CGNT#
CBS_CPERR#
CBS_CPAR
CBS_CC/BE1#
CBS_CAD14
CBS_CAD12
CAGE10_GND
CBS_CAD11
CBS_CAD9
CBS_CC/BE0#
CBS_CAD7
CBS_CAD5
CBS_CAD3
CBS_CAD1
CBS_CAD0
TPA0+
TPA0ÂTPB0+
TPB0-
CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0
CardBus Socket
LA-1711
1
CBS_VPP
CBS_VCC
R205
@
0_0603_5%~D
1 2
J1394
8
SGND4
7
SGND3
6
SGND2
5
SGND1
4
4
3
3
2
2
1
1
MOLEX_54515-0411~D
CBS_CAD[0..31]
A00-B
65
31
1
Page 32
5
PCI_AD[0..31]
D D
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
CK_33M_MINIPCI
R248
10_0402_5%~D @
COEX2_WLAN_ACTIVE
1 2
C C
CK_33M_MINPCI_TERM
2
C230
4.7P_0402_50V8C~D
@
1
PCI_CLKRUN#
12
R264
B B
10K_0402_5%~D
4
WLAN_LED_ACTIVITY
HW_RADIO_DIS#
PCI_PIRQD#
CK_33M_MINIPCI
PCI_REQ3#
PCI_C_BE3#
PCI_C_BE2#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_C_BE1#
+5VRUN
WLAN_LED_ACTIVITY
HW_RADIO_DIS#
PCI_PIRQD#
R255
0_0402_5%~D@
1 2
0.1U_0402_16V4Z~D
3
+3VRUN+3VRUN
JPCI
1
TIP
3
8PMJ-3
5
8PMJ-6
7
8PMJ-7
9
8PMJ-8
11
LED1_GRNP
13
LED1_GRNN
15
CHSGND
17
INTB#
19
3.3V
21
RESERVED
23
CK_33M_MINIPCI
PCI_REQ3#
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C_BE3#
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C_BE2#
PCI_IRDY#
PCI_CLKRUN#
PCI_SERR# PCI_STOP#
PCI_PERR#
PCI_C_BE1#
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
+5VRUN
2
C249
1
GROUND
25
CLK
27
GROUND
29
REQ#
31
3.3V
33
AD31
35
AD29
37
GROUND
39
AD27
41
AD25
43
RESERVED
45
C/BE3#
47
AD23
49
GROUND
51
AD21
53
AD19
55
GROUND
57
AD17
59
C/BE2#
61
IRDY#
63
3.3V
65
CLKRUN#
67
SERR#
69
GROUND
71
PERR#
73
C/BE1#
75
AD14
77
GROUND
79
AD12
81
AD10
83
GROUND
85
AD8
87
AD7
89
3.3V
91
AD5
93
RESERVED
95
AD3
97
5V
99
AD1
101
GROUND
103
AC_SYNC
105
AC_SDATA_IN
107
AC_BIT_CLK
109
AC_CODEC_ID1#
111
MOD_AUDIO_MON
113
AUDIO_GND
115
SYS_AUDIO_OUT
117
SYS_AUDIO_OUT GND
119
AUDIO_GND
121
RESERVED
123
VCC5A
AMP_1318644-1~D
V_3P3_LAN
AC_SDATA_OUT
AC_CODEC_ID0#
SYS_AUDIO_IN
SYS_AUDIO_IN GND
RING
8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5
LED2_YELP
LED2_YELN
RESERVED
INTA#
RESERVED
3.3VAUX
RST#
GNT#
GROUND
PME#
RESERVED
AD30
AD28
AD26
AD24
IDSEL
GROUND
AD22
AD20
AD18
AD16
GROUND
FRAME#
TRDY#
STOP#
DEVSEL#
GROUND
AD15
AD13
AD11
GROUND
C/BE0#
RESERVED
RESERVED
GROUND
M66EN
AC_RESET#
RESERVED
GROUND
AUDIO_GND
MCPIACT#
3.3VAUX
3.3V
3.3V
PAR
3.3V
AD9
3.3V
AD6
AD4
AD2
AD0
2
4
6
8
10
12
14
16
18
5V
20
22
24
26
28
30
32
34
36
0_0402_5%~D@
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
2
LED_WLAN24_RADIOSTATE
LED_WLAN5_RADIOSTATE
PCI_PIRQB#
PCIRST_2#
PCI_GNT3#
SYS_PME#
R250
1 2
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
MINIDSEL
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_DEVSEL#
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C_BE0#
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
LAN_SMBCLK
LAN_SMBDATA
MPCI_M66EN
MPCIACT#
V_3P3_LAN
2
C229
0.1U_0402_16V4Z~D
1
LED_WLAN24_RADIOSTATE
LED_WLAN5_RADIOSTATE
PCI_PIRQB#
PCIRST_2#
PCI_GNT3#
SYS_PME#
R249
10K_0402_5%~D@
12
1 2
R261
100_0402_5%~D
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_C_BE0#
R278
1K_0402_5%~D
12
R284
10K_0402_5%~D
1 2
COEX1_BT_ACTIVE
PCI_AD19
+3VSUS
1
2
C252
0.1U_0402_16V4Z~D
1
V_3P3_LAN
2
C253
0.1U_0402_16V4Z~D
1
+5VRUN
R270
10K_0402_5%~D
D
ICH_SMBDATA
ICH_SMBCLK
+3VRUN
A A
2
C232
0.047U_0402_10V4M~D
1
2
C241
0.047U_0402_10V4M~D
1
5
2
C227
0.047U_0402_10V4M~D
1
2
C246
0.047U_0402_10V4M~D
1
2
C234
0.047U_0402_10V4M~D
1
4
ICH_SMBDATA
ICH_SMBCLK
2
1
S
+3VSUS
S
C242
0.047U_0402_10V4M~D
NIC_MINI_SMBDAT
13
Q52
G
2N7002_SOT23~D
2
G
2
NIC_MINI_SMBCLK LAN_SMBCLK
13
D
Q48
2N7002_SOT23~D
2
C247
0.047U_0402_10V4M~D
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 3
1 3
2
1
3
1 2
D
S
Q53
2N7002_SOT23~D
G
2
2
G
Q49
2N7002_SOT23~D
D
S
C231
0.047U_0402_10V4M~D
R268
10K_0402_5%~D
1 2
2
C244
0.047U_0402_10V4M~D
1
LAN_SMBDATA
LAN_SMBDATA
LAN_SMBCLK
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
MINIPCI
LA-1711
32 65Wednesday, January 28, 2004
1
A00-B
Page 33
+3VALW
D D
KSO_17
EC Debug
Pin1,3 connect to GND.
Pin2 connect to serial port pin3
C C
Dell GPIO rev0.7
D-Bay USB power
+3VALW
B B
+3VRUN
+3VRUN
A A
12
R233
10K_0402_5%~D
C549
0.1U_0402_16V4Z~D
C574
0.1U_0402_16V4Z~D
5
12
R465
10K_0402_5%~D
J1397
1.5mm SMT@
1
1
2
2
3
3
1
C546
2
2
C577
1
12
R181
R182
10K_0402_5%~D
KSO_17
RB751V_SOD323~D
T6
PAD
@
T5
PAD
@
+3VALW
R226
1 2
10K_0402_5%~D
+3.3VRTC
+VRBATT_RTC
1
C589
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
BLM11A121S_0603~D
0.1U_0402_16V4Z~D
1 2
12
10K_0402_5%~D
SUB_DETECT#
D4
2 1
R624 0_0402_5%~D
1
C568
2
0.1U_0402_16V4Z~D
L12
PWRSW_SIO#
ATF_INT#
SYS_PME#
DEBUG_ENABLE LPCPD#
CBS_GRST#
R615
GV_HI_LO#
VAUX_EN
USB_EN#
BAY_MODPRES#
USB_IDE#
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_RTE#
SIO_RCIN#
NB_MUTE
BEEP
PWRSW_SIO#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S4_S5#
NOCREG
DT/MT_SELECT
SIO_PWRBTN#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
SYS_SUSPEND
SATA_MOD_DETECT#
DH_PWRSRC_OC
IDE_RST_HDD
IDE_RST_MOD
GC_BL_SUSPEND
DH_POWER_EN
PS_ID_DISABLE#
MODC_EN#
HDDC_EN#
+3.3VRTC
12
1
C558
2
C548
R232
0_0402_5%~D @
1
C572
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C567
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C152
0.1U_0402_16V4Z~D
1
1
2
2
1
1 2
12
C581
0.1U_0402_16V4Z~D
C563
0.1U_0402_16V4Z~D
4
CBS_GRST#
0_0402_5%~D
VAUX_EN
KSO17
USB_EN#
BAY_MODPRES#
USB_IDE#
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT
PWRSW_SIO#
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S4_S5#
LID_CL_SIO#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
SYS_SUSPEND
DH_PWRSRC_OC
IDE_RST_HDD
IDE_RST_MOD
GC_BL_SUSPEND
DH_POWER_EN
AC_LOW_PRES2#
MODC_EN#
HDDC_EN#
254VCC0
2
C211
0.1U_0402_10V6K~D
1
1
2
2
1
KPLLVCC
U15A
F13
SGPIO30
F14
SGPIO31
E16
SGPIO32
E15
SGPIO33
E12
SGPIO34
E13
SGPIO35
D16
SGPIO36
D15
SGPIO37
E14
SGPIO40
C16
SGPIO41
C15
SGPIO42
A16
SGPIO43
D14
SGPIO44
C14
SGPIO45
C13
SGPIO46
B14
SGPIO47
T5
LGPIO50
N6
LGPIO51
L6
LGPIO52
R6
LGPIO53
T6
LGPIO54
L7
LGPIO55
P7
LGPIO56
N7
LGPIO57
A15
LGPIO60
D13
LGPIO61
A14
LGPIO62
C12
LGPIO63
B13
LGPIO64
A13
LGPIO65
D12
LGPIO66
F11
LGPIO67
B12
LGPIO70
A12
LGPIO71
C11
LGPIO72
D11
LGPIO73
E11
LGPIO74
B11
LGPIO75
A11
LGPIO76
C10
LGPIO77
A4
VCC0/BAT
M7
VCC1_1
R13
VCC1_2
L11
VCC1_3
H10
VCC1_4
B16
VCC1_5
F10
VCC1_6
A6
VCC1_7
D3
VCC2_1
H2
VCC2_2
K6
VCC2_3
P4
VCC2_4
E1
VCC2_5
R5
VCC2_6/PLL
P6
VSS13/PLL
LPC47N254V12FBGA_LBGA256~D
LPC47N254
MACALLEN
8051
GPIO
LPC
GPIO
VCC
256 - LBGA
3
LPCPD#
LRESET#
DLDRQ1#
DLFRAME#
DLAD0
DLAD1
DOCK LPC
LPC
FDD
COM1
GPIO10/WK_SE14/IRMODE/IRRX3B
IR
LPT
GND
DLAD2
DLAD3
DSER_IRQ
DCLKRUN#
LDRQ1#
LFRAME#
LAD0
LAD1
LAD2
LAD3
SER_IRQ
CLKRUN#
WPROT#
RDATA#
HDSEL#
INDEX#
DSKCHG#
TRK0#
MTR0#
DIR#
STEP#
WDATA#
WGATE#
DS0#
DRVDEN0
DRVDEN1
RXD1
TXD1
RTS1#
CTS#
DTR#
DSR#
DCD#
RI1#
IRRX
IRTX
ACK#
SLCTIN#
INIT#
ALF#
STROBE#
BUSY
SLCT
ERROR#
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
AGND
2
+3VRUN
RN5
10K_8P4R_1206_5%~D
+3VRUN
12
R195
100K_0402_5%~D
+3VRUN
+3VALW
+3VRUN
D_CLKRUN#
D_SERIRQSIO_EXT_RTE#
LID_CL_SIO#
+3VRUN
TXD0
A3Y
System Debug
Pin5 connect to serial port pin3
+3VALW
12
R466
100K_0402_5%~D
10_0402_5%~D
1
C534
0.047U_0402_10V4M~D
2
1 2
1 2
1 2
1 2
1 2
D_IRMODE
IRRX
IRTX
10K_0402_5%~D
1 2
1 2
1 2
1 2
+3VRUN
LPC_LAD[0..3]
IRQ_SERIRQ
1 8
2 7
3 6
4 5
1 2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
R520
10K_0402_5%~D
R523
H4
PCIRST_SIO#
H3
D_DLRQ1#
R2
T2
N2
P1
P2
N3
D_SERIRQ
R4
D_CLKRUN#
T3
LPC_LDRQ1#
R3
LPC_LFRAME#
N4
LPC_LAD0
M3
LPC_LAD1
R1
LPC_LAD2
T1
LPC_LAD3
P3
IRQ_SERIRQ
T4
EC_CLKRUN#
P5
WRPRT#
L3
RDATA#
M1
L2
INDEX#
L5
DISKCHG#
M2
TRK0#
L4
K1
K2
K4
K3
L1
K5
M5
FPD
J7
K7
RXD0
G5
TXD0
G2
H7
CTS0#
H8
H6
DSR0#
G1
DCD0#
H5
RI0#
B10
D_IRMODE
H15
IRRX
K14
IRTX
M4
ACK#
C1
F2
F1
G3
G4
BUSY
D4
PE
B1
PE
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
B2
ERROR#
G6
F4
F3
E2
F5
E4
D1
D2
E3
C2
F6
J5
N1
N5
T10
R15
J11
G11
B15
H9
D6
KAGND
A2
1 2
1 2
1 2
R196 10K_0402_5%~D
R217
1 2
L22
BLM11A121S_0603~D
4.7K_0402_5%~D
PCIRST_SIO#
LPC_LDRQ1#
LPC_LFRAME#
R532
R537
R211
R527
R227
R231
R220
R222
R535
12
R183
100K_0402_5%~D
+5VSUS
8
U42C
P
5
G
TC7W14FU_SSOP8~D
4
R467
12
1
LID_CL#
+3VRUN
12
R184
100K_0402_5%~D
T11
PAD
@
LID_CL#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
SIO (1/2)
LA-1711
33 65Wednesday, January 28, 2004
1
A00-B
Page 34
5
4
3
2
1
LIVE_ON_BATT
CK_33M_SIOPCI
CK_14M_SIO
+3VALW
12
R234
10K_0402_5%~D @
12
R228
1K_0402_5%~D
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
DOCK_SMBDAT
DOCK_SMBCLK
1
2
MAX6326
U11
VCC
3
RESET#
GND
MAX6326_SOT23~D
VCC1_PWROK
HW_RADIO_DIS#
LAN_LOW_PWR
CHG_PBATT
3
1
2
R209
22K_0402_5%~D
1 2
R522
22K_0402_5%~D
1 2
R198
8.2K_0402_5%~D
1 2
R513
8.2K_0402_5%~D
1 2
R528
10K_0402_5%~D
1 2
R533
10K_0402_5%~D
1 2
R235
10K_0402_5%~D
+3VALW
12
2
C153
0.1U_0402_16V4Z~D
1
+3VALW
12
R551
10K_0402_5%~D
+5VALW
12
R549
10K_0402_5%~D
+3VALW
12
R229
D D
DH_MOD_PRES#
+3VALW
R213
1 2
4.7K_0402_5%~D
+5VRUN
R506
DAT_KBD
CLK_KBD
CLK_SM1
DAT_SM1
9
10
1 2
4.7K_0402_5%~D
ACAV
C C
B B
A A
10K_0402_5%~D
R620 0_0402_5%~D@
1 2
+3.3VRTC
U23C
SN74LVC32APWR_TSSOP14~D
14
IN0
IN1
7
P
8
O
G
PBAT_ALARM#
R621
1 2
47K_0402_5%~D
12
R514
R225
R224
1 2
4.7K_0402_5%~D
4.7K_0402_5%~D
12
4.7K_0402_5%~D
SIO_THERM_PWRDN
H_PROCHOT_SIO#
OVP_AC_ADAPT#
CLK_SM2
DAT_SM2
PBAT_ALARM#
KSO[0..15]
KSI[0..7]
DOCK_SMB_INT#
FPVCC
SBAT_PRES#
PBAT_PRES#
KSO16
CAP_LED#
NUM_LED#
SRL_LED#
VCORE_PHOT#
NB_PSID
T10
PAD@
T9
PAD@
C592
22P_0402_50V8J~D
1 2
C593
22P_0402_50V8J~D
1 2
DOCKED
R637 0_0402_5%~D
12
FPVCC
SBAT_ALARM#
PBAT_PRES#
SIO_THERM_PWRDN
H_PROCHOT_SIO#
1 2
KSO16
CAP_LED#
NUM_LED#
SRL_LED#
SIO_MSCLK
SIO_MSDAT
CLK_SM1
DAT_SM1
CLK_SM2
DAT_SM2
CLK_KBD
DAT_KBD
PBAT_ALARM#
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1 SIO_FA17
KSI0
CLK_32KX2
X5
32.768KHZ_12.5P_MC-306~D
3.8X12.1mm
CLK_32KX1
U15B
B9
IN0/WK_EE4
B8
IN1/WK_EE2
A8
IN2/WK_EE3
C8
IN3/GPWKUP
D8
IN4/WK_SE00
E8
IN5/WK_SE01
F8
IN6/WK_SE05
G8
IN7/WK_EE1
H13
GPIO0/WK_SE02
H12
GPIO1/WK_SE03
H11
GPIO2/WK_SE04
G10
GPIO3/TRIGGER
G13
GPIO7/WK_SE06
J14
GPIO8/WK_SE12/IRRX2
J16
GPIO9/WK_SE13/IRTX2
G14
GPIO17/WK_SE23/A20M
F15
GPIO20/WK_SE25/PS2CLK/8051RX
F12
GPIO21/WK_SE26/PS2DAT/8051TX
GPIO
D10
MSCLK
E10
MSDAT
C4
EMCLK
C3
EMDAT
B3
IMCLK
A1
IMDAT
J4
KBCLK
J6
KBDAT
G15
GPIO6/WK_SE11/IRMODE/IRRX3A
G12
GPIO5/WK_SE10/KSO15
G16
GPIO4/WK_SE07/KSO14
R7
KSO13/GPIO18
T7
KSO12/OUT8/KBRST
K8
KSO11
J8
KSO10
L8
KSO9
M8
KSO8
N8
KSO7
P8
KSO6
T8
KSO5
R8
KSO4
R9
KSO3
T9
KSO2
P9
KSO1
N9
KSO0
M9
KSI7
L9
KSI6
K9
KSI5
K10
KSI4
M10
KSI3
R10
KSI2
N10
KSI1
P10
KSI0
A3
XTAL1
C5
XTAL2
LPC47N254V12FBGA_LBGA256~D
LPC47N254
MACALLEN
K/B
256 - LBGA
FPGM
FDC_PP#
TEST_PIN
XOSEL
EC_SCI#
MODE
FDD_LED#
BAT_LED#
LDRQ0#
PWR_LED#
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5/DS1/KBRST
OUT6/MTR1
OUT7/SMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1
PWRGD
VCC1_PWRGD
MISC
GPIO11/WK_SE15/AB2A_DATA
GPIO13/WK_SE17/AB2B_DATA
GPIO15/WK_SE21/FAN_TACH1
GPIO16/WK_SE22/FAN_TACH2
CLOCK
RESET_OUT#
AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK
GPIO12/WK_SE16/AB2A_CLK
GPIO14/WK_SE20/AB2B_CLK
GPIO19/WK_SE24
PCI_CLK
24MHZ_OUT
32KHZ_OUT
CLOCKI
FLASH
FRD#
FWR#
FCS#
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22
SIO_KAH_PGM
L10
FDD_PP#
A10
K12
XOSEL
B4
K16
MODE
E5
J12
BAT1_LED#
J9
LPC_LDRQ0#
M6
BAT2_LED#
J10
EEPROM_WC
C7
F7
HW_RADIO_DIS#
B6
LAN_LOW_PWR
E6
CHG_PBATT
C6
TI_SUSPEND#
A5
AUDIO_AVDD_ON
B5
LIVE_ON_BATT
D7
B7
FAN2_PWM
E7
BREATH_LED
A7
FAN1_PWM
G7
RUNPWROK
K13
VCC1_PWROK
K15
RESET_OUT#
H1
DAT_SMB
C9
CLK_SMB
A9
DOCK_SMBDAT
E9
DOCK_SMBCLK
D9
SBAT_SMBDAT
H16
SBAT_SMBCLK
H14
PBAT_SMBDAT
J15
PBAT_SMBCLK
J13
FAN1_TACH
G9
FAN2_TACH
F9
SIO_A20GATE
F16
CK_33M_SIOPCI
J3
J2
D5
CK_14M_SIO
J1
SIO_FA0
N12
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
SIO_FA1
T13
SIO_FA2
P12
SIO_FA3
T14
SIO_FA4
T15
SIO_FA5
R16
SIO_FA6
N13
SIO_FA7
P16
SIO_FA8
M14
SIO_FA9
N15
SIO_FA10
N16
SIO_FA11
M13
SIO_FA12
L12
SIO_FA13
M15
SIO_FA14
M16
SIO_FA15
L14
SIO_FA16
L13
L15
SIO_FA18
L16
SIO_FA19
K11
R14
T16
P13
FRD#
P14
FWR#
N14
FCS#
P15
SIO_FD7
M12
SIO_FD6
R12
SIO_FD5
T12
SIO_FD4
P11
SIO_FD3
N11
SIO_FD2
M11
SIO_FD1
R11
SIO_FD0
T11
+3VALW
QBUFEN#
SIO_FA[0..19]
FRD#
FWR#
FCS#
12
R179
1K_0402_5%~D
@
10K_0402_5%~D
BAT1_LED#
LPC_LDRQ0#
BAT2_LED#
EEPROM_WC
SATA_3V_ENABLE#
HW_RADIO_DIS#
LAN_LOW_PWR
CHG_PBATT
TI_SUSPEND#
AUDIO_AVDD_ON
FAN2_PWM
BREATH_LED
FAN1_PWM
RUNPWROK
RESET_OUT#
DAT_SMB
CLK_SMB
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH
FAN2_TACH
SIO_A20GATE
C177
SIO_FD[0..7]
R180
R236
10K_0402_5%~D
R550
10K_0402_5%~D
R207
1 2
10_0402_5%~D@
CK_14M_SIO_TERM
2
1
4.7P_0402_50V8C~D@
12
12
12
R230
10K_0402_5%~D
1 2
R521
1 2
10_0402_5%~D
@
CK_33M_SIOPCI_TERM
2
C564
1
4.7P_0402_50V8C~D @
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
SIO (2/2)
LA-1711
1
34 65Wednesday, January 28, 2004
A00-B
Page 35
5
4
3
2
1
+3VALW
12
R552
0_0402_5%~D@
U40
1
D D
DAT_SM2
CLK_SM2
C C
B B
A A
KSO16
KSO[0..15]
KSI[0..7]
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
DAT_SM2
CLK_SM2
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
CN1
1 8
2 7
100P_1206_8P4C_50V8~D
5
R166
C140
CN6
3 6
4 5
1 8
100P_1206_8P4C_50V8~D
+5VRUN
12
R168
4.7K_0402_5%~D
4.7K_0402_5%~D
1
C146
2
10P_0402_50V8J~D
10P_0402_50V8J~D
CN5
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
12
BLM11A601S_0603~D
1 2
1 2
BLM11A601S_0603~D
1
2
CN4
2 7
3 6
4 5
L8
L9
1
C138
2
10P_0402_50V8J~D
CN3
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
1 8
100P_1206_8P4C_50V8~D
1
C141
2
10P_0402_50V8J~D
CN2
2 7
3 6
4 5
4
+5VRUN
BLM31A260SPT_1206~D
R628 33_0402_5%~D
RN113 33_1206_8P4R_5%~D
RN114 33_1206_8P4R_5%~D
RN115 33_1206_8P4R_5%~D
RN116 33_1206_8P4R_5%~D
RN117 33_1206_8P4R_5%~D
RN118
1
C148
100P_0603_50V8J~D
2
1 8
2 7
3 6
4 5
100P_1206_8P4C_50V8~D
L11
1 2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
12
1
C147
2
0.1U_0402_16V4Z~D
33_1206_8P4R_5%~D
MOUSEDAT
MOUSECLK
MOUSEVDD
KSO_17
Keep no nosie coupled,
Especially the TP_GND
KBD25
KBD24
KBD23
KBD22
KBD21
KBD20
KBD19
KBD18
KBD17
KBD16
KBD15
KBD14
KBD13
KBD12
KBD11
KBD10
KBD9
KBD8
KBD7
KBD6
KBD5
KBD4
KBD3
KBD2
KBD1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
KSO_17
KSI3
KSI2
KSI1
KSI0
JKYBRD
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JAE_FK2S030W11~D
3
TP_V+
30
TP_X
29
TP_GND
28
TP_Y
27
TP_Z
26
31
32
33
34
NC
2
A1
3
A2
4
VSS
FM24C05U_SO8~D
SUB_6782U
SMbus address A2
JPALM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HRS_FX6A-20P-0.8SV~D
SIO_FA[0..19]
G
2N7002
+3VALW
1
C599
0.1U_0402_16V4Z~D
2
8
VCC
WP
SCL
SDA
EEPROM_WC
7
CLK_SMB
6
DAT_SMB
5
EEPROM_WC
CLK_SMB
DAT_SMB
Address 1010 00XX
JP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ACES_6278-34P-DEBUG@
TP_Z
TP_V+
TP_Y
TP_X
TP_GND
+3VALW
FCS#
FRD#
FWR#
SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0
SIO_FA19
SIO_FA18
SIO_FA17
SIO_FA16
SIO_FA15
SIO_FA14
SIO_FA13
SIO_FA12
SIO_FA11
SIO_FA10
SIO_FA9
SIO_FA8
SIO_FA7
SIO_FA6
SIO_FA5
SIO_FA4
SIO_FA3
SIO_FA2
SIO_FA1
SIO_FA0
FWH_RST
For Compal Flash Tools
1
C203
2
0.1U_0402_16V4Z~D
VCC1_PWROK
12
LA-1711
1
+3VALW
1
C202
2
0.1U_0402_16V4Z~D
SIO_FD[0..7]
VCC1_PWROK
35 65Wednesday, January 28, 2004
A00-B
SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19
FCS#
FRD#
FWR#
FCS#
FRD#
FWR#
D
S
U14
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
MX29LV008T/B_TSOP40~D
C
1
B
2
VCC
VCC
VPP
RP#/RESET#
WP#/RY/BY#
GND
GND
E
3
31
30
11
SIO_FD0
25
D0
SIO_FD1
26
D1
SIO_FD2
27
D2
SIO_FD3
28
D3
SIO_FD4
32
D4
SIO_FD5
33
D5
SIO_FD6
34
D6
SIO_FD7
35
D7
FWH_RST
10
12
29
NC
38
NC
23
39
R219
0_0603_5%~D
DTC114
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet of
INT KB & ROM
Page 36
5
4
3
2
1
CPLD Function options Table
No.
D D
1 2
1 2
1 2
1 2
1 2
1 2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
VID1
VID2
VID3
VID4
VID5
H_VID0 VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
R15
R16
R29
R31
R34
R36
1
2
3
4
5
6
7
8
9
Function
CPLD (U27)
STPCLK# (From ICH to CPU) Pop Q42, R254, Depop R259
CPUSLP# (From ICH to CPU)
VRMPWRGD (From Reset to ICH) Depop R243 Pop R243
STP_AGP# (PLD to AGP) Pop R96, Depop R98 (P.18)Depop R96, Pop R98 (P.18)
CPUPREF# (From PLD to CPU) Depop R380 (P.8)Pop R380(P.8)
STPCPU_VR (From PLD to CPU Power)
DPRSLPVR (From PLD to CPU power)
PLD_WAKE# (From PLD to ICH) Depop R141 (P.21)Pop R141 (P.21)
Speedstep enable Speedstep disable
Pop U27, C233, C606, R557, Depop U27, JPLD, C233, C606, R557,
Depop Q42, R254, Pop R259
Pop Q43, R561, Depop R251 Depop Q43, R561, Pop R251
Depop PR94, Pop PR95 (P.46)Pop PR94, Depop PR95 (P.46)
Depop PR93, Pop PR92 (P.46)Pop PR93, Depop PR92 (P.46)
10 PLD_DISABLE# Pop R256, Depop R252 Depop R256, Pop R252
11 DPSLP# Pop R76, R78(P.8) Depop R76, R78(P.8)
12 PCI_PCIRST#(From ICH to PLD) Pop R245 Depop R245
GV_HI_LO#13 Pop R253 Depop R253
C C
+3VSUS
Pop when use CPLD
12
R253
10K_0402_5%~D@
GV_HI_LO#
+VCC_CORE
12
R246
100_0402_5%~D@
+3VRUN
12
H_STPCLK#
R559
1K_0402_5%~D
CLK_STP_CPU#
5
B B
A A
Pull low disables PLD assertion
of SSTEP or sleep and deeper
sleep on CPU
+3VSUS
12
R256
10K_0402_5%~D@
PLD_DISABLE#
R557
GV_HI_LO#
NOCREG
CLK_STP_CPU#
STP_AGP#
VCORE_DRSEN
H_STPCLK#
H_CPUSLP#
SUSPWROK
VRM_PWRGD
+3VSUS
1 2
LONG/SHRT#
1
@
2
12
R252
1K_0402_5%~D@
1K_0402_5%~D
@
C3/C4#
C233
0.1U_0402_16V4Z~D
GV_HI_LO#
H_STPCLK#
PLD_DISABLE#
I_STPCLK#
L_CPUSLP#
H_CPUSLP#
VRM_PWRGD
Pop when use CPLD
1
C606
0.1U_0402_16V4Z~D
@
2
+3VSUS
JPLD
1
2
3
4
5
6
MOLEX_53261-0690~D@
Depop when use CPLD
U27
1
TDI
7
TMS
26
TCK
32
TDO
43
I/O_5
44
I/O_6
2
I/O_8
8
I/O_14
12
I/O_18
13
I/O_19
20
I/O_26
14
I/O_20
42
I/O_4
5
I/O_11
6
I/O_12
10
I/O_16
18
I/O_24
23
I/O_29
41
VCCINT
17
VCCINT
9
VCCIO
29
VCCIO
EPM3032ATC44-10_TQFP44~D@
I/O_40
I/O_9
I/O_21
I/O_25
I/O_27
I/O_28
I/O_31
I/O_39
I/O_41
I/O_43
I/O_33
I/O_34
I/O_37
GND
GND
GND
GND
GND
GND
GND
GND
GND
34
3
15
19
21
22
25
33
35
37
27
28
31
38
36
30
24
16
11
4
40
39
Dell Speedstep Support PLD
4
+3VSUS +3VSUS
R243
1 2
0_0402_5%~D
DPSLP#
CLK_CPLD I_STPCLK#L_CPUSLP#
O_GMUXSEL
VRM_PWRGD
I_VRMPWRGD
DPSLP#
CPUPREF#
R245
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCORE_DSEN#
CPLD_WAKE#
SUSCLK
12
1
2
3
0_0402_5%~D@
CLK_CPLD
R244
22_0402_5%~D @
C225
@
10P_0402_50V8J~D
R588
1 2
@
0_0402_5%~D
CK_33M_CPLD
PCI_PCIRST#
CPUSLP# STPCLK#
2
+VCC_CORE +VCC_CORE
12
R603
680_0402_5%~D@
MMBT3904_SOT23~D@
R251
1 2
0_0402_5%~D
12
R561
470_0402_5%~D@
Q43
2
3 1
Depop when use CPLD
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
12
R254
470_0402_5%~D@
12
R604
680_0402_5%~D@
Q42
2
MMBT3904_SOT23~D@
3 1
Pop when use CPLDPop when use CPLD
H_STPCLK#H_CPUSLP#
R259
1 2
0_0402_5%~D
PLD
LA-1711
1
36 65Wednesday, January 28, 2004
A00-B
Page 37
5
+5VRUN
12
R560
100K_0402_5%~D
D D
5VRUNRC
1
C609
0.22U_0603_10V7M~D
2
+3VSUS
R353
1 2
C C
1.82K_0402_1%~D
2
C51
1
1000P_0402_50V7K~D
R94
thermistor
A1Y
8
U42A
P
G
TC7W14FU_SSOP8~D
4
16.2K_0402_1%~D
1 2
7
RUN_ON
R352
12
2
C392
1
1000P_0402_50V7K~D
+5VSUS
A6Y
THERM_FF_GATE
RUN_ON
R355
1 2
100K_0402_1%~D
Z3805Z3804
Z3806
R360
1 2
100K_0402_1%~D
C228 0.1U_0402_16V4Z~D
1 2
U42B
8
TC7W14FU_SSOP8~D
P
2
G
4
R362
48.7K_0402_1%~D
12
U36
1
IN+
VCC+
2
GND
3
IN-
LMV331__DCK
OUT
+3VSUS
5
4
Thermistor goes in CPU cavity.
Dell P/N 8K573
Semitech P/N 103KT2125-1P
B B
C
B E
1
3
2
Dell request populate for SST phase. 2003/0326
3904 SYMBOL(SOT23-NEW)
+3VSUS
2
Q60
R285
8.2K_0402_5%~D
1 2
3 1
+3VSUS
+3VRUN
GC_THERMTRIP#
+3VSUS
5
+VCC_CORE
R280
1K_0402_5%~D
1 2
Z3808
MMBT3904_SOT23~D
A A
H_THERMTRIP#
R272
8.2K_0402_5%~D
12
THERM_TRUE#
@
1 2
R636 10K_0402_5%~D@
R625 10K_0402_5%~D
R282
0_0402_5%~D
THERMTRIP_3P3#
NB_THERMTRIP#
TC7SH08FU_SSOP5~D
1 2
1 2
2
G
13
D
S
Q57
2N7002_SOT23~D
+3VSUS
5
U29
1
P
B
2
A
G
3
1
2
O
PWRGD_3V
Z3809
4
C619
0.1U_0402_16V4Z~D
THERM_MB#
R635 0_0402_5%~D @
4
RUNPWROK_1P5V
U26D
74VHC08MTC_TSSOP14~D
12
IN2
13
IN1
SUSPWROK_3V
V_2P5V_PWRGD
+3VSUS
R359
48.7K_0402_1%~D
1 2
NB_THERMTRIP#
1
C399
0.047U_0402_10V4M~D
2
Q56
2
G
2N7002_SOT23~D
1 3
D
S
+3VSUS
1
C674
2
0.1U_0402_16V4Z~D
1
B
2
A
1 2
POWER_SW_DB#
4
11
OUT
1 2
1 2
5
U47
P
THERM_TRUE#
4
O
G
TC7SH08FU_SSOP5~D
3
C618
0.1U_0402_16V4Z~D
1 2
RUNOK
+3VSUS
1
C226
0.1U_0402_16V4Z~D
2
14
1
P
IN1
3
OUT
2
IN2
G
U26A
74VHC08MTC_TSSOP14~D
7
MAX6509 goes in CPU cavity.
Discretes go outside.
MAX6509SET
R89
1 2
18.2K_0603_1%~D@
Z3811
R281
0_0402_5%~D
Z3812
Z3813
R275
100K_0402_5%~D
D16
2 1
RB751V_SOD323~D
THERM_CLEAR
U25B
74VHC08MTC_TSSOP14~D
5
IN2
6
OUT
4
IN1
+3VSUS
POWER
SEQUENCING
U4
1
SET
2
GND
3
OUT#
HYST
MAX6509CHU-K_SOT23-5~D@
SET-HOT Vrsion
+3.3VRTC
1
R283
2
1 2
1K_0402_5%~D
U28A
SN74LVC74APWR_TSSOP14~D
14
4
PRE
VCC
5
Q
2
D
3
CLK
6
Q
GND7CLR
1
+3.3VRTC
12
R572
20K_0402_5%~D
10
9
+3VSUS
HYST:
3
U26C
74VHC08MTC_TSSOP14~D
IN1
8
OUT
IN2
SUSPWROK
ITP_DBRESET#
RUNPWROK
+3VSUS
R247
150_0402_5%~D
+3VSUS
12
RESET_OUT#
VTT_PWRGD
VCORE_PWRGD
VCC for 10 degree
GND for 2 degree
5
VCC
4
MAX6509HYST
C620
0.1U_0402_16V4Z~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
G
R607
1 2
56_0402_5%~D
R93
10K_0402_5%~D
@
1 2
R95
10K_0402_5%~D@
1 2
13
D
Q71
2N7002_SOT23~D
@
S
1
2
SIO_THERM_PWRDN
THERM_STP#
THERM_PWRDWN
C659
0.22U_0603_10V7M~D
IMVP_PWRGD
2
SD 1.11(12474 page292) is request 8.2K ohm
IMVP_PWRGD
RUNPWROK
+3VRUN
1U_0603_6.3V6M~D
+3VALW
R571
10K_0402_5%~D
@
1 2
2
G
4
5
12
13
R556
100K_0402_5%~D
1 2
C605
13
D
Q70
2N7002_SOT23~D
S
13
D
2
G
S
2
+3VSUS
IN1
IN2
+3VSUS
IN2
IN1
1 2
10K_0402_5%~D
SIO_THERM_PWRDN
Q55
2N7002_SOT23~D
U26B
74VHC08MTC_TSSOP14~D
6
OUT
11
OUT
U25D
74VHC08MTC_TSSOP14~D
R581
1
2
1
+3VSUS
9
IN2
10
IN1
+3VSUS
14
U25A
1
P
IN1
OUT
2
IN2
G
74VHC08MTC_TSSOP14~D
7
shall be VHC14
8
U41A
P
A1Y
G
TC7W14FU_SSOP8~D
4
ICH_THERM_PWRDN#
Title
Size Document Number Rev
Date: Sheet of
PWRGD_3V
8
OUT
U25C
74VHC08MTC_TSSOP14~D
C603 0.1U_0402_16V4Z~D
1 2
IMVP_PWRGD
3
7
C607 0.47U_0603_16V7K~D
1 2
A3Y
+3VRUN
8
U41B
TC7W14FU_SSOP8~D
P
A6Y
G
4
PWRGD_3V
+3VRUN
8
U41C
TC7W14FU_SSOP8~D
P
5
G
4
1
C604
0.1U_0402_10V6K~D
2
2
shall be VHC14
DELL CONFIDENTIAL/PROPRIETARY
Thermtrip & PowerGOOD
LA-1711
1
37 65Wednesday, January 28, 2004
CK_VTT_PG#
I_VRMPWRGD
A00-B
Page 38
5
4
3
+5VHDD
2
1
OUT
1
DTA114YKA
Q16
DTA114YKA_SOT23~D
R_CAP
R_SRL
R80
470_0402_5%~D
12
R73
470_0402_5%~D
12
GND
R56
470_0402_5%~D
R52
470_0402_5%~D
R46
470_0402_5%~D
BAT1_LED
47K
10K
1 3
R_PIDEACT
Q44
DTA114YKA_SOT23~D
R60
470_0402_5%~D
D_IRMODE
IRTX
12
R576
0_0402_5%~D
1 2
+3VRUN
R579
1K_0402_5%~D
12
R578
R_BT_MPCI_ACT
BAT1_LED
BAT2_LED
R_BREATH_LED
ACTLED
CAP_LED
NUM_LED
SRL_LED
LID_CL#
R574
47_0805_5%~D
12
1K_0402_5%~D
PIDEACT#
CAP_LED
12
NUM_LEDR_NUM
12
SRL_LED
12
2
+3VRUN
12
SD_MODE
2
C621
1
0.1U_0402_16V4Z~D
1
C624
2
4.7U_1206_16V6K~D
JLED1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
FOX_QTS1030A-2021~D
+3VRUN
U43
6
VCC
5
SD_MODE
2
IRED_CATHODE
3
TXD
TFDU6101E_TR4~D
TFDU6102
C676 270P_0402_50V7K
1 2
KSO_17
KSI4
KSI5
KSI6
INT_MIC+
INT_MIC-
POWER_SW#
POWER_SW_EMI (Delete, board band
issue. Approval by Dell 10/9)
R575
1.8_1206_5%~D
RXD
MODE
GND
1
4
7
8
IRED_ANODE
12
KSO_17
KSI4
KSI5
KSI6
INT_MIC+
INT_MIC-
POWER_SW#
Z3903IRVCC
R577
0_0402_5%~D @
IR_ANODE
IRRX
12
R573
1.8_1206_5%~D
12
1
C623
2
4.7U_1206_16V6K~D
IN
2 3
+3VRUN
D D
47K
47K
2
10K
1 3
Q11
DTA114YKA_SOT23~D
47K
2
10K
1 3
Q21
DTA114YKA_SOT23~D
2
10K
1 3
Q12
DTA114YKA_SOT23~D
Q22
DTA114YKA_SOT23~D
R_BAT1_LED
R_BAT2_LED BAT2_LED
CAP_LED#
NUM_LED#
47K
SRL_LED#
2
10K
1 3
C C
BAT1_LED#
BAT2_LED#
+5VALW
47K
2
10K
1 3
B B
+3VALW
R72
150_0402_5%~D
1 2
BREATH_LED
R92
10K_0402_5%~D
1 2
BREATH_LED_B BT_ACTIVE
2
Z3901
Q19
MMBT3904_SOT23~D
BT_ACTIVE
R86
10K_0402_5%~D
1 2
BT_MPCI_ACTIVE
3 1
A A
5
R_BREATH_LED
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
+3VALW
2
R85
150_0402_5%~D
1 2
Z3902
Q23
MMBT3904_SOT23~D
3 1
R_BT_MPCI_ACT
DELL CONFIDENTIAL/PROPRIETARY
Title
LED Interface & IrDA
Size Document Number Rev
2
Date: Sheet of
LA-1711
38 65Wednesday, January 28, 2004
1
A00-B
Page 39
5
PWR_SRC
Run Planes Enable
12
R99
330K_0402_5%~D
D D
Q25
2N7002_SOT23~D
RUN_ON
C C
2
G
+5HDD Source
Q58
DTC144EKA_SOT23~D
HDDC_EN#
B B
Z4001
13
D
C60
S
0.22U_1206_25V7M~D
+12V
12
R276
100K_0402_5%~D
HDD_EN
13
47K
2
47K
12
Z4002
Q26
2
TP0610T_SOT23~D
1 3
12
1
R107
2
330K_0402_5%~D
+5VSUS
2
1
G
3
1
C248
C243
2
0.01U_0402_16V7K~D
4.7U_1206_16V6K~D
SUSPWROK_5V
R103
30K_0402_5%~D
RUN_ENABLE
6
D
Q54
SI3456DV-T1_TSOP6~D
S
4 5
1
2
SUSPWROK_5V
+5VHDD
12
R267
100K_0402_5%~D
2N7002_SOT23~D
+3VSRC
+5VSUS
2
Q15
G
6
2
1
6
2
1
+3VSRC
D
D
1
12
13
4
Q27
SI3456DV-T1_TSOP6~D
S
45
C67
G
3
Q47
4.7U_1206_16V6K~D
SI3456DV-T1_TSOP6~D
S
45
G
C239
3
VAUX_EN
R51
100K_0402_5%~D
D
S
+3VRUN Source
+3VRUN
12
1
R112
10K_0402_5%~D
2
+5VRUN Source
+5VRUN
1
12
R260
10K_0402_5%~D
2
4.7U_1206_16V6K~D
2N7002_SOT23~D
R622
100K_0402_5%~D
1 2
+3VSRC +3VSUS
4
C33
0.1U_0402_10V6K~D@
PWR_SRC
12
R62
100K_0402_5%~D
Q17
13
D
2
G
S
Q20
SI3443DV_TSOP6~D
6
5
2
1
3
1
2
DTC144EKA_SOT23~D@
RUN_ON
2
G
12
R63
200K_0402_5%~D
1
C40
4.7U_1206_16V6K~D
2
3
PWR_SRC
11
12
R65
100K_0402_5%~D
13
D
Q67
2N7002_SOT23~D
S
Q37
47K
2
47K
+3.3VRTC
12
1 1
R190
100K_0402_5%~D
@
Z4003
2
13
ENAB_3VLAN
12
R67
470K_0402_5%~D
+VCC_CORE
2
G
12
R176
47_0805_5%~D
@
Z4005
2
Q36
2N7002_SOT23~D@
13
D
S
2
V_1P25V_DDR_VTT +3VRUN
12
1
R175
22_0805_5%~D
@
Z4006
2
Q35
2N7002_SOT23~D@
13
D
2
G
S
2
G
SATA_3V_ENABLE#
12
1
R178
150_0805_5%
@
2
Q34
2N7002_SOT23~D@
13
D
S
+5VMOD Source
DTC144EKA_SOT23~D
MODC_EN#
+3VMOD Source
Q45
DTC144EKA_SOT23~D@
Q59
+CHGRTC
47K
2
47K
2
+VRBATT_RTC
+12V
47K
+12V
47K
12
R277
100K_0402_5%~D
2
MOD_EN
13
C250
12
R257
100K_0402_5%~D@
13
C236
1
Bridge Battery/Cell
Battery Conn.
RBAT
D23
3
1
2
BAS40-04_SOT23
+5VSUS
6
2
1
D
Q50
G
S
4 5
1
C245
2
4.7U_1206_16V6K~D
+3VSUS
6
2
1
G
3
S
4 5
1
2
4.7U_1206_16V6K~D@
C235
SI3456DV-T1_TSOP6~D
D
3
1
2
0.01U_0402_16V7K~D
1
2
0.01U_0603_50V7K~D@
1
2
+5VMOD
12
R273
100K_0402_5%~D
Q41
SI3456DV-T1_TSOP6~D@
+3VMOD
JRBATT
1
2
MOLEX_53398-0290~D
L P/N?
12
R258
100K_0402_5%~D@
LIVE_ON_BATT
+3.3VRTC
POWER_SW#
D5
RB751V_SOD323~D
A A
2 1
C223
0.1U_0402_16V4Z~D
5
12
R242
10K_0402_5%~D
1
1
2
PWRSW_SIO#
+3.3VRTC
C220
1 2
0.1U_0402_16V4Z~D
14
U24A
P
2
IN
O
G
SN74LVC14APWR_TSSOP14~D
7
ACAV
3
+3.3VRTC
14
12
P
IN0
13
IN1
G
7
+3.3VRTC
14
U24B
P
4
IN
O
G
SN74LVC14APWR_TSSOP14~D
7
4
U23D
11
O
SN74LVC32APWR_TSSOP14~D
+3.3VRTC
1 2
0.1U_0402_16V4Z~D
14
U23A
1
P
IN0
3
O
2
IN1
G
SN74LVC32APWR_TSSOP14~D
7
POWER_SW_DB#
C600
+3.3VRTC
14
U24F
P
13
IN
O
G
SN74LVC14APWR_TSSOP14~D
7
ALWON
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
ALW_ENABLE#
12
ALW_ENABLE#
+3VSUS
12
R238
100K_0402_5%~D
1
C214
0.1U_0402_16V4Z~D
2
2
5
+3.3VRTC +3.3VRTC
14
U24C
P
6
IN
O
G
SN74LVC14APWR_TSSOP14~D
7
Title
Size Document Number Rev
Date: Sheet of
14
9
IN
7
DELL CONFIDENTIAL/PROPRIETARY
U24D
P
8
O
G
SN74LVC14APWR_TSSOP14~D
POWER CONTROL
LA-1711
1
SUSPWROK_3V
39 65Wednesday, January 28, 2004
A00-B
Page 40
5
4
3
2
1
Fiducial Mark
FD12
FD2
@
12
11
FIDUCIAL MARK
@
FIDUCIAL MARK
@
FIDUCIAL MARK
@
FIDUCIAL MARK
+3.3VRTC
10
PRE
D
CLK
GND7CLR
1
FD9
1
FD3
1
FD19
1
U28B
SN74LVC74APWR_TSSOP14~D
14
VCC
Q
Q
13
CPU screw hole
D D
H8
H_C315D177@
H12
H_C315D177@
1
H7
H11
C315D110@
C315D110@
1
1
1
MCH screw hole
H6
H9
C315D165
C315D165
C315D165
1
1
C C
H23
H5
C315D165
1
1
VGA Conn. screw hole
H10
C315D165
1
MDC
H15
C217D157
B B
1
PCMCIA Slot screw hole
H28
H27
H26
C197D91@
C197D91@
1
1
H29
C197D91@
C197D91@
1
1
Others screw hole
H1
H_C99D79@
C315D110@
C315D165
@
H2
H_C150D110@
1
H17
H16
C315D110@
1
H34
H35
H_O181X40D181X40N@
1
H3
H_O115X177D95X157@
1
1
1
1
H21
H_C315D110@
1
H19
H_O115X177D95X157@
1
H31
H30
C315D110@
C315D110@
1
1
H36
H_C71D71N@
1
H4
H_C150D110@
1
H20
C150D110@
1
H33
H32
H_C315D110@
C315D110@
1
1
+3.3VRTC
9
8
FD15
@
1
FIDUCIAL MARK
FD8
@
1
FIDUCIAL MARK
FD6
@
1
FIDUCIAL MARK
FD20
@
1
FIDUCIAL MARK
@
1
FIDUCIAL MARK
@
1
FIDUCIAL MARK
@
1
FIDUCIAL MARK
11
@
FD10
FD1
FD5
IN
1
FIDUCIAL MARK
FD14
@
1
FIDUCIAL MARK
FD16
@
1
FIDUCIAL MARK
+3.3VRTC +12V
14
U24E
P
10
O
G
SN74LVC14APWR_TSSOP14~D
7
FD13
@
1
FIDUCIAL MARK
FD7
@
1
FIDUCIAL MARK
FD17
@
1
FIDUCIAL MARK
4
5
FD11
@
1
FIDUCIAL MARK
FD4
@
1
FIDUCIAL MARK
FD18
@
1
FIDUCIAL MARK
+3.3VRTC
U23B
SN74LVC32APWR_TSSOP14~D
14
P
IN0
6
O
IN1
G
7
8
U46B
5
P
IN+
7
O
6
IN-
G
LM358M_SO8~D
4
FAN Conn. screw hole
H24
C315D165
1
H25
C315D165
1
PCB
PCB
LA1711
1
EMI Cilps
EMI_CLIP
1
EMI_CLIP
1
PAD5
EMI_CLIP
1
@
@
PAD12
EMI_CLIP
1
@
@
PAD4
A A
@
PAD11
@
5
PAD6
PAD13
1
1
EMI_CLIP
EMI_CLIP
PAD10
EMI_CLIP
1
@
PAD14
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
EMI_CLIP
1
@
4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
PAD,Screw Hole and Spare Parts
Size Document Number Rev
Date: Sheet of
LA-1711
1
40 65Wednesday, January 28, 2004
A00-B
Page 41
5
+12V
21
PD1
RB751V-40_SOD323~D@
PR1
1@ 19.1K_0402_1%~D
2@ 16.9K_0402_1%~D
PD4
2 1
EC10QS04_SOD106~D@
Z4202Z4201
+RTCSRC
100K_0402_5%~D@
1 2
@
12
PC1
D D
RBAT
PWR_SRC
PC4
2200P_0402_50V7K~D
C C
12
12
PC5
2200P_0402_50V7K~D
1000P_0402_50V7K~D@
PFS1
RBAT
0.75A_24V_MINISMDM075/24~D@
PR1:19.1K;PR3:13.3K Trickle charger current is 0.45mA for Nimitz.
PR1:16.9K;PR3:8.06K Trickle charger current is 0.5mA for Beijing.
PC6
0.01U_0402_25V7K~D
21
12
12
PC7
0.01U_0402_25V7K~D
SBATT_VCC
12
PR3
@
1@ 13.3K_0402_1%~D
2@ 8.06K_0402_1%~D
SYS_SUSPEND
4
DC_IN+
21
PD2
RB751V-40_SOD323~D @
+RTCSRC Source
EC10QS04_SOD106~D
12
PR4
SYS_SUSPEND
Z4203
3
+RTCSRC
PD3
21
13
PQ1
IRLML5103_SOT23~D@
2
FET on when in suspend, current flow is from Rbat to
PWR_SRC to sustain system during battery swap mode
13
47K
2
PQ2
DTC144EKA_SOT23~D@
47K
PWR_SRC
NC_LDO_EN
1 2
PR2
0_0402_5%~D
0_0402_5%~D@
RTC_SHDN#
1 2
PR5
2
RTC_PWR Source
PU1
1
IN
OUT
5
#SHDN
5/3+
GND
2
MAX1615EUK_SOT23-5~D
@
PU2
1
IN
5
#SHDN
MAX1615EUK_SOT23-5~D
+RTC_PWR
3
4
3.3VRTC Source
3
OUT
4
5/3+
GND
2
PC2
12
10U_1206_6.3V7K~D@
12
PC3
10U_1206_6.3V7K~D
+3.3VRTC
1 2
PR258
200_0402_5%~D
1 2
PR259
200_0402_5%~D
1
+CHGRTC
D
1
2
3
S
G
IRLML5103
PL1
Z-series AC Adaptor
Connctor
PJPDC1
Low_PWR
9
GND_4
DC+_1
8
B B
A A
7
6
GND_3
GND_2
GND_1
MH1
DC+_2
DC-_1
DC-_2
MH2
AMP_1566065-1~D
5
PWR_ID
1
2
DCIN+
3
4
5
DCIN-
BLM11A121S_0603~D
PL2
1 2
C8B BPH 853025_2P~D
PL4
1 2
C8B BPH 853025_2P~D
12
PS_ID NB_PSIDPS_ID
+DC_IN
PC15
0.47U_1812_50V7M~D
1 2
12
100K_0402_5%~D
4
DC_IN+ Source
PQ3
SI7447DP_SO8~D
1
2
3
PR8
150K_0402_5%~D
Z4206
PR12
4
1000P_0402_50V7K~D
12
5
PC9
NOTE: "THE POINT LOCATED
AT PS MODULE
PC10
12
0.01U_0402_25V7K~D
1 2
0.1U_0805_50V7M~D
THE POINT
0.1U_0805_50V7M~D
12
PC11
PC12
12
0.1U_0805_50V7M~D
DC_IN+
PC14
0.1U_0805_50V7M~D
12
12
PC13
15U_D2_25M_R90~D@
THESE CAPS MUBT BE
NEXT TO JCHG
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
1
+
2
PC8
PD28
VZ0603M220APT_0603@
2
PS_ID
+3VALW
PR267
4.7K_0402_5%~D
1 2
PR254
100K_0402_1%~D @
PR256
15K_0402_1%~D@
3
2
PD33
@
12
12
2
DA204U_SOT323~D@
1
MMBT3904_SOT23~D @
PQ4
2N7002_SOT23~D
D
1 3
G
2
PQ70
C
2
B
E
3 1
+5VALW+DC_IN
NB_PSID
12
DC-IN
LA-1711
1
ACAV
+3VALW
PR7
1.5K_0402_5%~D
1 2
PS_ID_DISABLE#
41 65Wednesday, January 28, 2004
3
2
PD34
DA204U_SOT323~D
1
PR276
0_0805_5%~D
S
1 2
+5VALW
PR224
@
100K_0402_5%~D
PR268
1 2
1 2
0_0402_5%~D@
PR266
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
A00-B
Page 42
5
D D
Primary Battery Connector
PJPB1
C C
B B
PC17
2200P_0402_50V7K~D
1 2
TRACE
THE POINT
14
G
13
G
SUYIN_200275MR012G536ZL~D
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
12
11
10
9
8
7
6
5
4
3
2
1
SUBOUT1
SUBOUT2
4
SUB_DETECT#
100_0402_5%~D
+5VALW
3
@
DA204U_SOT323~D
PR15
1 2
PD5
1
1 2
100_0402_5%~D
2
@
DA204U_SOT323~D
PR16
3
PD6
ESD Diodes
2
1
PR17
1 2
100_0402_5%~D
2
+12V
3
2
PD7
@
1
DA204U_SOT323~D
PR262
1 2
100_0402_5%~D
1
PD31
DA204U_SOT323~D
@
3
SUBOUT2
PC227
1000P_0402_50V7K~D@
1 2
PC226
1000P_0402_50V7K~D@
1 2
SUBOUT1
3
3
PD8
@
DA204U_SOT323~D
2
1
1
2
Please closely PJPB1
PR238
1 2
0_0805_5%~D
PR237
1 2
0_0805_5%~D
PBAT_ALARM#
PBAT_SMBDAT
PBAT_SMBCLK
SUBOUT1
SUBOUT2
PD32
DA204U_SOT323~D
@
3
SUB_OUT2
SUB_OUT1
SUB_OUT2
SUB_OUT1
2
PC16
0.1U_0805_50V7M~D
1 2
PBATT+
12
PL21
C8B BPH 853025_2P~D
+5VALW
12
PR14
10K_0402_5%~D
PBAT_PRES#
1
SUYIN_200275MRQ12G536ZL_12P
TOP view
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Battery CONN.
LA-1711
1
42 65Wednesday, January 28, 2004
A00-B
Page 43
5
PL5
HCB4532K-800T90_1812~D
PWR_SRC
Current limit at 4A for +3.3V
D D
+3VSRCP
PR228
0_0402_5%~D@
1 2
PR230
0_0402_5%~D
1 2
C C
B B
1 2
10U_1210_25V6M~D
1
PC34
+
2
330U_D3L_6.3VM_R25~D
SUS_ON
VAUX_EN
PC18
12
0.1U_0805_50V7M~D
12
10U_1210_25V6M~D
PC35
SUS_ON
PC45
12
0.1U_0805_50V7M~D
PC20
15U_D2_25M_R90~D@
1
12
PC19
Place these CAPs
close to FETs
+
2
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
1 2
4.7U_SPC-1205P-4R7B_+40-20%~D
3
PU4
1
G
I1
4
O
2
I0
P
TC7SH32FU_SSOP5~D
5
+3.3VRTC
PC27
PC29
PL7
THERM_STP#
PC21
1
+
15U_D2_25M_R90~D@
2
12
12
PD10
EP10QY03~D
2 1
240K_0402_5%~D
PC201
4.7U_1210_25V6K~D
578
3 6
241
578
3 6
241
PR33
1 2
ALWON
SI4810DY_SO8~D
1 2
PC28
12
12
0.1U_0805_50V7M~D
PQ58
SI4800DY-T1_SO8~D
PC31
0.1U_0805_50V7M~D
PQ59
1 2
PR31
2K_0402_1%~D
1000P_0402_50V7K~D
PR40
1 2
1K_0402_5%~D
4
Adding RC filter
PR18
4.7_1206_5%~D
VCC_MAX1999
PC26
1U_0603_6.3V6M~D
PR29
BST_3 LX5
12
1 2
2.2_0402_5%~D
LX3
DL3
SKIP#
12
PC37
12
RB717F_SOT323~D
20
17
6
BST3
28
26
27
24
22
7
12
3
4
25
12
PC38
10U_1206_6.3V7K~D
12
PR23
12
47_0402_5%~D
1
PD9
2
3
PU3
V+
VCC
SHDN
BST3
DH3
LX3
DL3
OUT3
FB3
SKIP
ON3
ON5
LDO3
MAX1999EEI_QSOP28~D
+3VSRCP
+3VALW
PC232
1U_0805_25V4Z~D
4.7U_0805_6.3V6K~D
LDO5
BST5
DH5
LX5
DL5
OUT5
N.C.
FB5
PRO
ILIM5
ILIM3
REF
TON
GND
PGOOD
PR34
1 2
100K_0402_5%~D
18
14
16
15
19
21
1
9
10
11
5
8
13
23
2
+5VALW
PC24
2.2_0402_5%~D
BST5
DH5
DL5
PRO#
ILIM5
ILIM3
TON
12
BST_5
PR28
1 2
REF
12
PC36
1U_0805_25V4Z~D
SUSPWROK_5V
3
1U_0603_6.3V6M~D
PC30
0.1U_0805_50V7M~D
1 2
PR218
12
0_0402_5%~D
0.1U_0805_50V7M~D
12
PC25
PC22
578
3 6
578
3 6
PWR_SRC
241
241
12
Place these CAPs
close to FETs
PQ56
SI4800DY-T1_SO8~D
PQ57
SI4810DY_SO8~D
1 2
0_1206_5%~D
12
PC23
2200P_0402_50V7K~D
Current limit at 6A for +5VSUSP
PL6
1 2
4.7U_SPC-1205P-4R7B_+40-20%~D
PD11
EP10QY03~D
2 1
PR30
12
PC41
4.7U_1210_25V6K~D
RUNPWROK
PC39
4.7U_0805_6.3V6K~D
0.1U_0805_50V7M~D
12
PC43
1U_0805_25V4Z~D
12
12
PC33
12
10
PU19
7
SHDN
2
VL
3
REF
PC42
0.1U_0402_10V6K~D
2
1
PC32
+
2
150U _D2_6.3VM~D
12
PC44
4.7U_1210_25V6K~D
8
IN
VH
EXT
CS
OUT
FB
GND
MAX1745EUB_10UMAX~D
1
1
ILIM5
ILIM3
PRO#
TON
+5VSUSP
PR19
18.2K_0402_1%~D
PR24
43K_0402_1%~D
REF
1 2
20K_0402_1%~D
1 2
20K_0402_1%~D
VCC_MAX1999
PR20
1 2
PR25
1 2
PR21
1 2
0_0402_5%~D@
PR26
1 2
0_0402_5%~D
PR22
0_0402_5%~D@
1 2
PR27
0_0402_5%~D
1 2
VCC_MAX1999
PR32
0_0402_5%~D
1 2
@
SKIP#
PR37
0_0402_5%~D
1 2
Adding SKIP control
PR227
0_0402_5%~D@
1 2
PR229
0_0402_5%~D
1 2
36
241
PQ7
9
6
5
SI4835DY_SO8~D
578
PD13
EC31QS04~D
4
Add the current limit
PL8
22U_SIL104-220_2.9A_30%~D
1 2
2 1
PR223
1 2
0.028_2512_1%~D
270P_0402_50V7K~D
PC224
(+12V+-5%,2A)
12
PR36
12
182K_0402_1%~D
PC40
47U_D3L_16VM_R70~D
PR41
21K_0402_1%~D
1 2
+12VP
1
+
2
1
+
2
PC225
47U_D3L_16VM_R70~D@
1 2
1 2
+5VSUSP
1 2
+3VSRCP
A A
+12V
PAD-OPEN 4x4m
(6A,240mils ,Via NO.= 12)
PJP2
+5VSUS
PAD-OPEN 4x4m
PJP3
PAD-OPEN 4x4m
(4A,160mils ,Via NO.= 8)
+3VSRC
5
ALW_ENABLE#
+RTC_PWR
4
+5VALW Source
PQ13
SI2301DS_SOT23~D@
D
S
13
G
PR45
100K_0402_5%~D@
1 2
PD14
2 1
RB751V-40_SOD323~D@
2
Z4704ALW_ENABLE#
12
PC51
0.1U_0402_10V6K~D@
+5VALW
1
+
2
+3VALW Source
+3.3VRTC
S
G
2
PR46
100K_0402_5%~D@
1 2
PC49
47U_D2_6.3VM~D@
PD15
2 1
RB751V-40_SOD323~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
PC50
0.1U_0402_10V6K~D@
PQ12
D
SI2301DS_SOT23~D
13
@
1
+
2
PC48
47U_D2_6.3VM~D@
+3VALW
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet of
3.3V/5V
LA-1711
1
43 65Wednesday, January 28, 2004
A00-B
(2A,80mils ,Via NO.= 4)
PJP1
+12VP
Page 44
5
4
3
2
1
D D
PC52
2200P_0402_50V7K~D
+1.5VRUNP
C C
12
PR55
36.5K_0402_1%~D
12
PR61
18.2K_0402_1%~D
B B
+VTT_GMCHP
PC69
470U_D2_2.5VM_R12~D
PR232
12
0_0402_5%~D
PC72
12
100P_0402_50V8K~D
+1.5VRUNP
1 2
1 2
1
+
PC220
2
220U_D2_4VM~D
PJP4
PAD-OPEN 4x4m
PJP5
PAD-OPEN 4x4m
1
2
+
+1.5VRUN
+VTT_GMCH
12
PC53
0.1U_0603_25V7K~D
PC70
12
4.7U_0805_6.3V6K~D
RUN_ON
PC54
4.7U_1210_25V6K~D
12
12
1 2
PC55
4.7U_1210_25V6K~D
PL10
1 2
2.2U_SPC-1205P-2R2B_13A_30%~D
PD17
EC31QS04~D
FDS6672A_SO8~D
2 1
PR65
12
0_0402_5%~D
RUNPWROK_1P5V
1
+
2
PQ15
+3VSUS
PC56
15U_D2_25M_R90~D
@
578
PQ14
SI4392DY-T1_SO8~D
3 6
241
578
3 6
241
PR215
0_0402_5%~D
12
PR68
10K_0402_5%~D
DAP202U_SOT323~D
12
PR247
100K_0402_5%~D
0.1U_0805_25V7K~D
12
PD16
1U_0805_10V7K~D
PC67
12
1 2
0_0402_5%~D
PR53
1 2
8.87K_0402_1%~D
+1.5VRUNP/+VTT_GMCHP
PR47
PR51
1M_0402_5%~D
1
3
2
PC65
12
12
PC57
1000P_0402_50V7K~D
PR49
1 2
0_0402_5%~D
PJP9
1 2
AGNDJMP1
1 2
PR231
10_0402_5%~D
1 2
PC58
1U_0603_6.3V6M~D
1 2
23
25
24
26
22
27
28
3
7
6
5
4
2
1
PU7
TON1
SC1485
VCCA1
VDDP1
BST1
DH1
LX1
ILIM1
DL1
VOUT1
FBK1
EN/PSV1
PGOOD1
PGND1
AGND1
SC1485ITSTR_TSSOP28~D
PR48
10_0402_5%~D
PC59
1U_0603_6.3V6M~D
12
TON2
VCCA2
VDDP2
BST2
DH2
LX2
ILIM2
DL2
VOUT2
FBK2
EN/PSV2
PGOOD2
PGND2
AGND2
+5VSUS
9
11
17
21
20
19
18
16
10
12
8
13
15
14
1 2
1 2
1 2
0_0402_5%~D
0_0402_5%~D
1U_0805_10V7K~D
PC66
1 2
PR50
PR52
PR54
1 2
5.11K_0402_1%~D
PJP10
1 2
AGNDJMP2
12
PR57
715K_0402_1%~D
2200P_0402_50V7K~D
PC76
12
1000P_0402_50V7K~D
12
PC68
0.1U_0805_25V7K~D
PL9
1 2
HCB4532K-800T90_1812~D
12
PC61
PC62
0.1U_0603_25V7K~D
PQ16
1
G1
D1
2
D1
S1/D2
3
G2
S1/D2
4
S1/D2
S2
SI4814DY_SO8~D
12
PR214
0_0402_5%~D
+5VSUS
12
PC63
4.7U_1210_25V6K~D
12
12
8
7
6
5
PR216
10K_0402_5%~D
PWR_SRC
12
PC64
4.7U_1210_25V6K~D
3U_SPC-07040-3R0_5A_30%~D
12
PR248
100K_0402_5%~D
PR236
12
0_0402_5%~D
PR66
12
0_0402_5%~D@
VTT_PWRGD
1
+
PC60
15U_D2_25M_R90~D
@
2
PL11
1 2
4.7U_0805_6.3V6K~D
VCORE_PWRGD CPU_PSC_LOW
RUNPWROK
PC221
220U_D2_4VM~D@
1
PC74
12
+
2
PC71
1
220U_D2_4VM~D
+
PR257
2
0_0402_5%~D
10P_0402_50V8J~D
PQ64
2N7002_SOT23~D
+VTT_GMCHP
12
12
PR58
12
PC73
2
G
30K_0402_1%~D
12
PR60
15.8K_0402_1%~D
12
PR240
4.87K_0402_1%~D
13
D
S
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
+1.5VRUNP & +VTT_GMCHP
Size Document Number Rev
Date: Sheet of
LA-1711
1
6544
A00-B
Page 45
5
4
3
2
1
D D
2200P_0402_50V7K~D
+2.5V_MEMP
1
PC90
1 2
PR234
12
PC92
47P_0402_50V8J~D
+
2
220U_D2_4VM~D
SUSPWROK_5V
C C
220U_D2_4VM~D
0_0402_5%~D
12
PR76
42.2K_0402_1%~D
PR82
10K_0402_1%~D
B B
12
1
+
PC91
2
V_2P5V_PWRGD
1 2
100_0603_5%~D@
1000P_0402_50V7K~D@
PL13
2.2U_SPC-1205P-2R2B_13A_30%~D
PC93
PC77
PR73
PC78
0.1U_0805_25V7K~D
12
12
PD19
EC31QS04~D
12
PR86
10K_0402_5%~D
@
1 2
V_2P5V_PWRGD
12
12
PC79
4.7U_1210_25V6K~D
PQ47
FDS6672A_SO8~D
2 1
241
+5VSUS
PR89
10K_0402_5%~D
1 2
PC80
4.7U_1210_25V6K~D
12
4.7U_1210_25V6K~D
578
3 6
PR217
0_0402_5%~D
1 2
PC81
241
241
12
578
PQ17
SI4392DY-T1_SO8~D
3 6
578
PQ18
FDS6672A_SO8~D
3 6
1
+
PC82
15U_D2_25M_R90~D
@
2
12
PR249
100K_0402_5%~D
0.1U_0805_50V7M~D
21
RB751V-40_SOD323~D
PD29
PC218
1U_0805_10V7K~D
PC88
12
PR74
1 2
0_0402_5%~D
PJP11
1 2
AGNDJMP3
12
12
PC85
1000P_0402_50V7K~D
PR71
1 2
0_0402_5%~D
PR78
1 2
7.5K_0402_1%~D
PR69
1M_0402_5%~D
1 2
12
PR77
10_0402_5%~D
PC83
1U_0603_6.3V6M~D
1 2
PU8
23
TON1
SC1486
25
VCCA1
3
VDDP1
7
BST1
6
DH1
5
LX1
2
DL1
4
ILIM1
24
VOUT1
26
FBK1
22
EN/PSV1
27
PGOOD1
1
PGND1
28
AGND1
SC1486ITSTR_TSSOP28~D
+5VSUS
PR70
10_0402_5%~D
PC84
1U_0603_6.3V6M~D
12
TON2
VCCA2
VDDP2
BST2
DH2
LX2
ILIM2
DL2
FBK2
REFOUT
PGOOD2
REFIN
PGND2
AGND2
1 2
9
11
17
21
20
19
18
16
12
10
13
8
15
14
12
PR85
750K_0402_5%~D
PD30
RB751V-40_SOD323~D
PC86
1000P_0402_50V7K~D
1 2
PR72
1 2
0_0402_5%~D
PR75
1 2
0_0402_5%~D
PR79
1 2
10.7K_0402_1%~D
PJP12
1 2
AGNDJMP4
21
PC89
0.1U_0805_50V7M~D
+5VRUN
12
12
PC216
4.7U_1210_25V6K~D
PC219
1U_0805_10V7K~D
PC101
0.1U_0402_10V6K~D
12
PQ19
1
D1
2
D1
S1/D2
3
G2
S1/D2
4
S1/D2
S2
SI4814DY_SO8~D
12
PC217
0.1U_0805_25V7K~D
8
G1
7
6
5
+2.5V_MEMP
12
12
PR87
10K_0402_1%~D
12
PR88
10K_0402_1%~D
15U_D2_25M_R90~D@
PL12
1 2
HCB4532K-800T90_1812~D
1
+
PC222
2
12
PR250
100K_0402_5%~D
PR81
10_0402_5%~D
1 2
PC100
1U_0603_6.3V6M~D
1 2
PWR_SRC
12
PC223
2200P_0402_50V7K~D
1 2
12
PR80
100_0603_5%~D@
12
PC97
1000P_0402_50V7K~D
@
+2.5V/+1.25V
DDR Termination Voltage
PL14
3U_SPC-07040-3R0_5A_30%~D
PC96
4.7U_0805_6.3V6K~D
150U _D2_6.3VM~D
1
PC94
+
1 2
2
V_1P25V_DDR_VTTP
1
PC95
+
150U _D2_6.3VM~D
1 2
2
0_0402_5%~D
PR260
PJP6
PAD-OPEN 4x4m
1 2
PJP7
PAD-OPEN 4x4m
+2.5V_MEMP
A A
V_1P25V_DDR_VTTP
5
1 2
PJP8
1 2
PAD-OPEN 4x4m
+2.5V_MEM
(12A,360mils ,Via NO.=24)
V_1P25V_DDR_VTT
(3A,200mils ,Via NO.=6)
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
1.25V/2.5V
LA-1711
1
45 65Wednesday, January 28, 2004
A00-B
Page 46
5
D D
PR92
0_0402_5%~D
1 2
PR93
VCORE_DRSEN
VCORE_DSEN#
C C
B B
1 2
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
+5VRUN
8
PU20B
5
P
IN+
7
O
6
IN-
G
LM358M_SO8~D
4
VID_PWRGD
+3VSUS
0_0402_5%~D
RUNPWROK
PR94
12
PR226
100P_0402_50V8K~D
PR117
PR225
0_0402_5%~D@
1 2
12
PR95
0_0402_5%~D
+5VRUN
PR99
12
1 2
0_0402_5%~D@
PC104
1.2VDD
12
12
PC110
4.7U_1206_16V6K~D
PR122
12
0_0402_5%~D
VID4
VID3
VID2
VID1
VID0
VID5
VCORE_ENLL
12
12
12
45.3K_0402_1%~D
PR124
100K_0402_5%~D
1 2
12
PR100
365_0402_1%~D
PR101
21K_0402_1%~D
PR103
10K_0402_1%~D
PR108
PU10
1
VIN
4
PG
3
EN
MIC5258-1.2BM5_SOT23-5~D
0.1U_0402_10V6K~D
PR98
66.5K_0402_1%~D
1
O
12
115K_0402_1%~D
12
PR113
32.4K_0402_1%~D
1 2
VCORE_PHOT#
5
VOUT
2
GND
4
PC233
+5VRUN
8
P
IN+
IN-
G
4
PR104
12
12
PU20A
3
2
LM358M_SO8~D
12
PC102
1U_1210_50V7M~D
PC103
0.033U_0603_25V7M~D
Frequency Select
PR106
0_0402_5%~D
1 2
+3VRUN
12
PC108
220P_0402_50V8J~D
PR114
10K_0402_5%~D
1 2
Panasonic ERTJ0EV334J (0402)
Locate this NTC resistor on
PCB between phase 2 and 3
for thermal compensation.
12
330KB_0402_5%_ ERTJ0EV334J~D
+VCCVID
12
PC112
4.7U_1206_16V6K~D
1. When mode control signal is
low/ high, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
2N7002_SOT23~D
12
PR96
1K_0402_1%~D
@
PR112
+5VRUN
PQ61
PU9
32
VCC
1
VID4
2
VID3
3
VID2
4
VID1
5
VID0
6
VID5
34
ENLL
33
DRSEN
35
DSEN#
10
OCSET
11
SOFT
9
DSV
36
FS
37
DRSV
38
VR-TT#
40
NTC
12
GND
19
GND
ISL6247CR_QFN40~D
TP0610T_SOT23~D
13
D
2
G
S
CPU_PSC_HI
100K_0402_5%~D
@
@
PQ60
PR109
3
1M_0402_5%~D
@
2
G
CPU_PSC_LOW
12
PR90
80.6K_0402_1%~D
RAMPADJ
PGOOD
PWM1
ISEN1+
ISEN1-
PWM2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
COMP
FB
NC
VDIFF
VSEN
VRTN
OFS
PR110
13
D
S
PR123
22K_0402_5%~D
PWR_SRC
1 2
7
10K_0402_5%~D
39
25
24
23
26
27
28
20
21
22
31
30
29
15
13
PR107
14
0_0402_5%~D
16
17
18
8
0.1U_0402_10V6K~D
12
PR118
27K_0402_5%~D
1 2
PR220
681K_0402_1%~D
PQ62
12
2
B
MMBT3904_SOT23~D
Battery Feed
Forward
PR91
12
PR97
12
0_0402_5%~D@
12
+5VRUN
PC214
1 2
PR205
5.1K_0402_1%~D
1 2
1 2
13
D
PQ46
2
2N7002_SOT23~D
G
S
C
E
3 1
+5VRUN
PC105
4700P_0402_25V7K~D
12
1000P_0402_50V7K~D@
PC109
1000P_0402_50V7K~D@
12
Place close to IC
12
2N7002_SOT23~D
PC111
1U_0603_6.3V6M~D
PR120
12
0_0402_5%~D
PR121
12
0_0402_5%~D@
2
VCORE_PWRGD
PWM1
ISEN1+
ISEN1-
PWM2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
PR102
20K_0402_1%~D
1 2
PC106
12
PR115
0_0402_5%~D@
12
PR111
2.43K_0402_1%~D
1 2
D
S
13
PQ45
1 2
0_0402_5%~D
0_0402_5%~D@
VSSSENSE
11.5K_0402_1%~D
G
2
PR116
PR119
12
Place near +VCC_CORE
output capacitor
PR204
+VCC_CORE
VCCSENSE
12
Remote
Sensing
12
13
D
@
S
PR241
39K_0402_1%~D
@
PQ65
2N7002_SOT23~D
2
G
1
DT/MT#
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
CPU_CORE_Controller
LA-1711
46 65Wednesday, January 28, 2004
1
A00-B
Page 47
5
PR125
3_0402_5%~D
PU11
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8~D
PR134
3_0402_5%~D
PU12
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8~D
PR143
3_0402_5%~D
PU13
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8~D
0.15U_0805_16V7K~D
PR152
3_0402_5%~D
PU14
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8~D
PC113
12
0.15U_0805_16V7K~D
SI4392DY-T1_SO8~D
2
BOOT
1
UGTE
0_0402_5%~D
8
PHSE
5
LGTE
PC145
1 2
0.15U_0805_16V7K~D
2
BOOT
1
UGTE
0_0402_5%~D
8
PHSE
5
LGTE
PC152
1 2
0.15U_0805_16V7K~D
SI4392DY-T1_SO8~D
2
BOOT
1
UGTE
0_0402_5%~D
8
PHSE
5
LGTE
PC159
1 2
SI4392DY-T1_SO8~D
2
BOOT
1
UGTE
0_0402_5%~D
8
PHSE
5
LGTE
PQ20
PR210
12
Phase1
PQ22
SI4368_SO8~D
LG1UG2
PQ24
SI4392DY-T1_SO8~D
PR211
12
Phase2
PQ26
SI4368_SO8~D
LG2UG3
PQ28
PR212
12
Phase3
PQ30
SI4368_SO8~D
LG3UG4
PQ32
PR213
12
Phase4
PQ34
SI4368_SO8~D
LG4 UG1
+5VRUN
1 2
PWM1
D D
PWM2
C C
PWM3
B B
PWM4
A A
PR127
@
499K_0603_1%~D
1 2
PR136
@
499K_0603_1%~D
1 2
PR145
@
499K_0603_1%~D
1 2
PR154
@
499K_0603_1%~D
1 2
PR153
0_0402_5%~D
PC132
0.1U_0402_10V6K~D
ISEN1-
ISEN1+
470P_0805_100V7K~D
ISEN2-
ISEN2+
470P_0805_100V7K~D
ISEN3-
ISEN3+
470P_0805_100V7K~D
ISEN4-
ISEN4+
5
12
1 2
470P_0805_100V7K~D
PC149
PC157
PC164
PC133
1 2
1 2
1 2
1 2
1 2
1 2
1 2
578
PQ21
SI4392DY-T1_SO8~D
3 6
241
578
3 6
241
578
SI4392DY-T1_SO8~D
3 6
241
578
3 6
241
578
SI4392DY-T1_SO8~D
3 6
241
578
3 6
241
578
SI4392DY-T1_SO8~D
3 6
241
578
3 6
241
PQ25
4
578
PQ29
578
PQ33
4
578
578
3 6
FDS7064N_SO8~D@
578
3 6
241
FDS7064N_SO8~D @
578
3 6
241
578
578
3 6
3 6
241
3 6
3 6
3 6
241
CPU_PWR_SRC
PC114
1U_0603_25VKK~D
241
SI4368_SO8~D
9
PQ48
DUAL FOOTPRINT
PC146
1U_0603_25VKK~D
241
9
PQ27
SI4368_SO8~D
PQ50
DUAL FOOTPRINT
PC153
1U_0603_25VKK~D
241
SI4368_SO8~D
9
PQ52
FDS7064N_SO8~D
@
DUAL FOOTPRINT
PC160
1U_0603_25VKK~D
241
SI4368_SO8~D
9
PQ54
FDS7064N_SO8~D
@
DUAL FOOTPRINT
12
10U_1210_25V6M~D
PQ23
578
3 6
241
CPU_PWR_SRC
10U_1210_25V6M~D
12
578
3 6
241
CPU_PWR_SRC
10U_1210_25V6M~D
12
PQ31
578
3 6
241
CPU_PWR_SRC
10U_1210_25V6M~D
12
PQ35
578
3 6
241
0.1U_0603_25V7K~D
PC115
1 2
578
3 6
PC147
12
0.1U_0603_25V7K~D
578
PC154
12
PC204
0.1U_0603_25V7K~D
578
3 6
FDS7064N_SO8~D@
PC161
12
0.1U_0603_25V7K~D
578
FDS7064N_SO8~D@
241
FDS7064N_SO8~D@
3 6
FDS7064N_SO8~D @
241
12
PC205
3 6
PC202
12
12
PC203
241
12
241
9
PQ49
PQ51
9
PQ53
PQ55
12
12
PC131
Snubber
@
1000P_0402_50V7K~D
PR129
2.2_0805_1%~D@
1 2
12
9
12
Snubber
PR138
2.2_0805_1%~D@
1 2
2200P_0402_50V7K~D
12
Snubber
@
PR147
2.2_0805_1%~D@
1 2
12
PC209
2200P_0402_50V7K~D
9
12
Snubber
@
2.2_0805_1%~D@
1 2
Local Transistor
Swtich Decoupling
PC206
2200P_0402_50V7K~D
0.56U_ETQP4LR56WFC_21A_20%~D
PR130
30.1K_0402_1%~D
Local Transistor
Swtich Decoupling
PC207
2200P_0402_50V7K~D
0.56U_ETQP4LR56WFC_21A_20%~D
PC148
@
1000P_0402_50V7K~D
PR139
30.1K_0402_1%~D
12
PC208
0.56U_ETQP4LR56WFC_21A_20%~D
PC155
1000P_0402_50V7K~D
PR148
30.1K_0402_1%~D
0.56U_ETQP4LR56WFC_21A_20%~D
PC162
1000P_0402_50V7K~D
PR157
PR156
30.1K_0402_1%~D
3
Panasonic ETQ-P4LR56WFC
PL16
1 2
12
820B_0603_5%_ERAV33J821V~D
Panasonic ETQ-P4LR56WFC
PL17
1 2
12
Local Transistor
Swtich Decoupling
Panasonic ETQ-P4LR56WFC
PL18
1 2
12
820B_0603_5%_ERAV33J821V~D
Local Transistor
Swtich Decoupling
Panasonic ETQ-P4LR56WFC
PL19
1 2
12
820B_0603_5%_ERAV33J821V~D
3
PC134
12
0.01U_0402_25V7K~D
PR133
PTC resistor
PC151
12
0.01U_0402_25V7K~D
PR142
820B_0603_5%_ERAV33J821V~D
PTC resistor
PC158
12
0.01U_0402_25V7K~D
PR151
PTC resistor
PC165
12
0.01U_0402_25V7K~D
PTC resistor
PR160
CPU_PWR_SRC
10U_1210_25V6M~D
CPU_PWR_SRC
PC135
@
15U_D2_25M_R90~D
2
PL15
PWR_SRC CPU_PWR_SRC
1 2
C8B BPH 853025_2P~D
Input Bulk and HF Capacitors
PC117
PC116
12
12
10U_1210_25V6M~D
1
+
PC136
2
15U_D2_25M_R90~D@
PC118
10U_1210_25V6M~D
PC137
1
15U_D2_25M_R90~D@
+
2
PC119
12
10U_1210_25V6M~D
1
+
2
15U_D2_25M_R90~D@
PC120
12
12
10U_1210_25V6M~D
10U_1210_25V6M~D
PC139
1
15U_D2_25M_R90~D@
+
PC138
2
PC121
12
10U_1210_25V6M~D
1
+
2
15U_D2_25M_R90~D@
PC122
PC140
12
PC123
12
10U_1210_25V6M~D
PC141
1
15U_D2_25M_R90~D@
+
2
1
+
PC142
2
15U_D2_25M_R90~D@
12
0.1U_0603_25V7K~D
PC143
1
15U_D2_25M_R90~D@
+
2
PC215
1
+
2
1
1
+
PC144
2
15U_D2_25M_R90~D@
Low-side two population options
12
PC210
0.1U_0402_10V6K~D
FDS7064N_SO8:
PQ48,PQ49,PQ50,PQ51,
PQ52,PQ53,PQ54,PQ55
+3VALW
12
PR219
10K_0402_5%~D
PU18
1
AS
2
GND
3
VDD
AD7414ART-0_SOT23-6~D
#ALERT
6
SDA
SCL
5
4
1 2
PR222 0_0402_5%~D
Address 1001 001X (X=1-->Read; X=0-->Write)
DAT_SMB
CLK_SMB
ATF_INT#
+VCC_CORE
SI4362DY_SO8:
PQ22,PQ23,PQ26,PQ27,
PQ30,PQ31,PQ34,PQ35
Address select(7414ART-0)
Float: 1001 000
GND: 1001 001
VDD: 1001 010
+3VALW
Notes:
The ISL6561(ISL6427) supports lossless current sensing including
Inductor DCR and MOSFET rDSon sensing. Schematic components are
color coded accordingly. In addition an external sense resistor
can be used for higher load-line accuracy but this will impact
system cost and efficiency.
Sync. Rectifiers use thermally enhanced "PowerPak" technology in
an SO-8 form-factor. Optimal MOSFETS will be chosen based on
thermal performance.
Depending on the processor final requirments and empirical
thermal result testing a 3 phase solution may be possible. In
the 4 phase configuration a single upper mosfet may also be
sufficient.
Add thermal venting vias to board. Vias under parts must have a
minimum pitch of 1mm and hole size of 0.3mm to avoid solder
wicking.
DCR
Inductor
Sensing
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Title
CPU_CORE_Power-Stage
Size Document Number Rev
Date: Sheet of
LA-1711
1
A00-B
47 65Wednesday, January 28, 2004
Page 48
5
D D
PWR_SRC
DC_IN+ discharge path
DC_IN+
PR197
PR169
1 2
+5VALW
PR190
2
G
1 2
PC180
10K_0402_5%~D
1 2
13
D
S
PC168
1U_0805_25V4Z~D
PR179
0_0402_5%~D
PC193
1U_0805_25V4Z~D
1 2
PR187
59K_0402_1%~D
TH
1 2
C C
PR200
ACAV<34,39,41>
2K_0402_1%~D
DC_IN+
10U_1210_25V6M~D
B B
A A
PC213
12
0.01U_0402_50V7K~D@
BSS138_SOT23~D
12
PR201
100K_0402_5%~D
10U_1210_25V6M~D
1 2
49.9K_0402_1%~D
1 2
PC172
1000P_0402_50V7K~D
5
12
PR174
PQ42
2
G
PC166
PC183
12
13
D
S
365K_0402_1%~D
1 2
0.01U_0402_25V7K~D
1 2
PC181
0.01U_0402_25V7K~D
12
10K_0402_1%~D
5
PR198
10K_0402_5%~D
PQ43
BSS138_SOT23~D
PR178
0_0402_5%~D
12
PR188
10K_0402_1%~D
1 2
PQ40
BSS138_SOT23~D
13
D
2
G
S
2 1
12
12
PR191
100K_0402_5%~D
1 2
PU23
1
GND
2
GND
3
VCC
12
MAX4173FEUT-T_SOT23-6~D
PC239
0.1U_0603_25V7K~D
PQ41
SI7447DP_SO8~D
1
2
3
4
PR199
100K_0402_5%~D
12
PR251
0_0402_5%~D
@
ACAV<34,39,41>
75K_0402_1%~D@
PR176
1 2
10K_0402_1%~D
PC192
1500P_0402_50V7K~D
PBAT_SMBDAT<34,42>
TM
1 2
PBAT_SMBCLK<34,42>
1 2
0.1U_0603_25V7K~D
PD23
RB751V-40_SOD323~D
4
PWR_SRC
5
IN+
6
IN-
PD25
B540C~D@
12
PR173
T16
PC185
21
CHG_PBATT <34>
4
8
PU22B
P
O
G
LM393_SO8~D
4
OUT
RS-
RS+
+SDC_IN
0_0402_5%~D
0.1U_0805_25V7K~D@
ACOK#
12
CCV
PAD@
1645_DAC
1 2
1U_0603_6.3V6M~D
7
PR166
PC169
6
5
4
1 2
1 2
PU6
31
PDS
27
SRC
1
DCIN
3
ACIN
32
ACOK
6
CCS
7
CCI
8
CCV
12
VDD
13
THM
14
SDA
15
SCL
16
INT
11
DAC
PC186
PR165
1 2
0.01_2512_1%~D
CSSP
29
CSSP
REF4GND18IMAX
GND
5
CHVREF
1 2
PR272
10K_0402_1%~D
1 2
+5VALW
PWR_SRC
PR167
0_0402_5%~D
1 2
CSSN
@
1 2
28
17
I.C.
DHIV
CSSN
PDL
LDO
DLOV
DHI
DLO
PGND
CSIP
CSIN
BATT
VMAX
MAX1535AETJ_TQFN32~D
10
280K_0402_1%~D
PR184
182K_0402_1%~D
1 2
3
PC237
PC228
12
@
0.1U_0402_10V6K~D
ACAV
PQ69
SI4835DY_SO8~D
PQ38
FDS6672A_SO8~D
3.2U_CEP125-3R2_9.9A_20%~D
PD22
EC31QS04~D
2 1
PR183
1 2
0_0402_5%~D
1 2
+5VALW
12
PR271
100K_0402_1%~D
12
36
241
578
PL20
1 2
PC195
0.1U_0603_25V7K~D@
PR269
1 2
499K_0402_1%~D
PWR_SRC
12
12
IN+
IN-
VCC
8
4
PC194
P
G
Y
PC235
0.1U_0603_25V7K~D
PU22A
1
O
LM393_SO8~D
10P_0402_50V8J~D
5
4
CHAGER_SRC
36
241
578
578
3 6
241
1 2
PC236
12
0.1U_0402_10V6K~D
PR273
11K_0402_1%~D
1 2
1 2
PR274
PR275
PR239
@
100K_0402_5%~D
12
23.7K_0402_1%~D
100K_0402_1%~D
+3.3VRTC
1 2
ACOK#
PC182
1U_0805_25V4Z~D
25
30
2
DLOV
24
26
23
0.1U_0603_25V7K~D@
22
21
20
PWR_SRC
12
33_0402_5%~D
PR265
1 2
4.99_0805_1%~D
DLO
CSIP
CSIN
PDL <49>
PR175
PC234
PC170
0.1U_0805_25V7K~D
19
9
PR185
12
PR189
182K_0603_0.1%~D
CHVREF
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3
2
12
PC238
1000P_0402_50V7K~D
PU21
1
NC
2
A
3
GND
@
TC7SH14
PL22
1 2
MCK4532800YAT_1812~D
PQ37
SI4835DY_SO8~D
PC171
1 2
1U_0603_6.3V6M~D
1 2
PC174
0.1U_0402_10V6K~D
1 2
PBATT+
0.1U_0603_25V7K~D@
PR182
CHVREF
12
31.6K_0603_0.1%~D
VMAX=3.49V
Maximum charger voltage=17.45V
IMAX=1.6V
Maximum charger current=8A
+3VRUN
12
PR270
100K_0402_5%~D
13
D
2
G
S
PC175
2200P_0402_50V7K~D
0.1U_0805_50V7M~D
CHG_CS
2
PQ71
2N7002_SOT23~D
+3.3VRTC
PR172
100K_0402_5%~D
@
1 2
ACOK#
12
PC176
PR177
1 2
0.01_2512_1%~D
PR186
1 2
0_0402_5%~D
2
OVP_AC_ADAPT# <10,34>
160W Throttling
150W Recovery
PC177
0.1U_0805_50V7M~D
1 2
1 2
15U_D2_25M_R90~D@
PC187
4.7U_1210_25V6K~D
1
DC_IN+
12
12
10K_0402_1%~D
12
PU15
2
AS2431_SOT23~D
1 3
PC212
10U_1210_25V6M~D
PBATT+
PC190
4.7U_1210_25V6K~D
1 2
13
D
PQ63
BSS138_SOT23~D@
S
LA-1711
PR162
1K_0402_5%~D
PR164
1 2
PR168
1 2
330K_0402_5%~D
PD35
1SS355_SOD323~D
PR277
1K_0402_5%~D
12
1
PR161
75K_0402_1%~D
PR170
12.7K_0402_1%~D
PC211
10U_1210_25V6M~D
1
12
+
2
PC173
12
PC188
4.7U_1210_25V6K~D
Title
Size Document Number Rev
Date: Sheet of
12
PC189
0.1U_0805_50V7M~D
12
PR181
1 2
1.2K_1206_5%~D@
ACAV
2
G
DELL CONFIDENTIAL/PROPRIETARY
CHARGER CONTROL
+3.3VRTC
31
E
2
B
C
12
+5VSUS
1
+
PC184
15U_D2_25M_R90~D
@
2
48 64Wednesday, January 28, 2004
PQ36
2SA1036K_SOT23~D
ACAV
PR171
100K_0402_5%~D
21
12
A00-B
Page 49
5
D D
DC_IN+
C C
PBATT+
4
PD26
2 1
B540C~D@
5
PR252
1 2
0_0402_5%~D
PR253
PDL
1 2
0_0402_5%~D
@
PQ44
SI7447DP_SO8~D
1
2
3
4
2200P_0402_50V7K~D
12
PR202
470K_0402_5%~D
3
PWR_SRC
PC199
12
+5VSUS
PC200
0.1U_0805_50V7M~D
1 2
2
1
12
PC229
0.1U_0402_10V6K~D
12
PR243
10K_0402_5%~D
0_0402_5%~D@
PR255
1 2
PR242
B B
DT/MT_SELECT
A A
5
2
G
+5VSUS
12
PR244
10K_0402_5%~D
@
13
D
PQ68
2N7002_SOT23~D
S
@
DT/MT#
4
VCORE_BOOTSELECT
PR245
1 2
12
PR264
100K_0402_5%~D
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12K_0402_5%~D
3
1 2
2.7K_0402_5%~D
PQ67
MMBT3904_SOT23~D
C
2
B
E
3 1
2
12
PR246
10K_0402_5%~D
PQ66
MMBT3906_SOT23~D
E
3
B
C
1
CPU_PSC_HI
12
PC230
0.1U_0402_10V6K~D
2
12
PC231
0.1U_0402_10V6K~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Battery Discharge
LA-1711
1
49 65Wednesday, January 28, 2004
A00-B
Page 50
5
4
3
2
1
D D
+3VRUN
12
SUB_DETECT#
C C
SUB_VREF
12
SUB_GAIN0
SUB_GAIN1
12
B B
R589
10K_0402_5%~D
Gain Setting
R592
100K_0402_5%~D
R596
100K_0402_5%~D@
SPK_SHUTDOWN#
12
13
2
G
R590
10K_0402_5%~D
D
Q74
2N7002_SOT23~D
S
12
12
R593
100K_0402_5%~D
R597
100K_0402_5%~D@
GAIN0 GAIN1 Amplifier gain(db) INPUT
0
1
1 1
0
1
0
12dB
18dB0
23.6dB
36dB
+3VRUN
1
B
2
A
AUD_MONO_OUT
IMPEDANCE
241K ohm
168K ohm
104K ohm
33K ohm
C640 0.1U_0402_16V4Z~D
1 2
5
U44
P
SUB_SHUTDOWN#
4
O
G
TC7SH08FU_SSOP5~D
3
SUB_VREF
0.22U_0603_10V7M~D
C645
1 2
0.056U_0603_16V7K
1
C651
1U_0805_25V4Z~D
2
C658
1000P_0402_50V7K~D
1 2
C655
1 2
R627
1 2
1.21K_0603_1%
1
2
0.22U_0603_10V7M~D
1
C653
2
1U_0805_25V4Z~D
SUB_SHUTDOWN#
C644
1 2
SUB_GAIN0
SUB_GAIN1
C648
1 2
1U_0805_25V4Z~D
12
C654
220P_0402_50V7K
Need to FILTER!!!
2
C641
1U_0805_16V7K
1
U45
24
VCC
5
SHDN
1
INN
2
INP
3
GAIN0
4
GAIN1
7
VCLAMP
23
VREF
22
BYPASS
21
COSC
20
ROSC
R595
6
120K_0402_5%~D
PGND
PGND12PGND
+12V
1
2
AGND18AGND
TPA3001D1PWP_TSSOP24~D
13
19
C642
10U_1206_16V4Z~D
8
BSN
9
PVCC
11
OUTN
10
OUTN
14
OUTP
15
OUTP
16
PVCC
17
BSP
+12V
C646
1U_0805_16V7K
C650
1U_0805_16V7K
+12V
1 2
51_0603_1%
12
12
1 2
51_0603_1%
R591
R594
C643
1 2
0.22U_0603_16V7K~D
D20
2 1
B130-13_SMA~D
D21
2 1
B130-13_SMA~D
C652
1 2
0.22U_0603_16V7K~D
L49
1 2
BLM21PG600SN1D_0805~D
L50
1 2
BLM21PG600SN1D_0805~D
1
C647
1000P_0402_50V7K~D
2
1
C649
1000P_0402_50V7K~D
2
SUB_OUT1AUD_MONO_OUT
SUB_OUT2
SUB_OUT1
SUB_OUT2
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Subwoofer
LA-1711
1
50 65Wednesday, January 28, 2004
A00-B
Page 51
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 1/10
Request
Page#
Item Issue DescriptionDate
D D
1 8
2
3 Compal
11 2/17/2003
21 ICH5-IDE/LPC/
4 23 D-MODULE Compal
5 23 D-MODULE
6 26 USB(2.0)
C C
7 37 Thermtrip &
8 25 AMP and
Title
Prescott
Processor
SpringdaleÂDDR Interface
PM/GPIO/LAN
Connector
PowerGOOD
PHONE JACK
Owner
Compal2/17/2003
Compal
2/17/2003
2/17/2003
2/17/2003 DELL Need to cross the TX and RX lines on the motherboard side
2/17/2003 DELL Del all mark "2@" symbol, All components default must
2/17/2003 Compal
2/27/2003 DELL Change OP amplifier power from +12V to +5V ,change audio
ITP Connector default depopulate Depop RN8 (RN8 is populted on M00)
Resistor value SPEC isn't meet Intel recommend
Dell M00 Board Bring up issue item4:
ICH5 PIN Y18, A19 are swapped on JHDD in the schematics and
Pins V20, V22 are also swapped. HDD can't boot.
Dell M00 Board Bring up issue item5:
+3.3VMOD power net no power source.we have two signal names
for +3.3VMOD /+3VMOD, need jump wire.
populate. Nimitz and Beijing both are support Dog House.
Dell M00 Board Bring up issue item3:
No generate system clock.
U25 Pin1 and Pin 2 need to be shorted together, VCORE_PWRGD is
an OD signal and it does not have a pullup.
amplifier as same as Abacus-MT
Correct R367,R109 from 40.2_0603_1% to 42.2_0603_1%
(M00 R109,R367 are mount 42.2_0603_1%)
Swap IDE_PDCS1# and IDE_PDCS3#;
Swap IDE_SDCS1# and IDE_SDCS3#.
Correct power net from +3.3VMOD to +3VMOD
Change JMOD1 pin8 from SATA_MODTX+ to SATA_MODRX+
Change JMOD1 pin10 from SATA_MODTX- to SATA_MODRXÂChange JMOD1 pin14 from SATA_MODRX+ to SATA_MODTX+
Change JMOD1 pin16 from SATA_MODRX- to SATA_MODTX-
Del all mark "2@" symbol, All components default must
populate. (All mark"2@" components are populate on M00 Board)
VCORE_PWRGD signal add a 10K_0402_5%(R581) resistor pull up
to +3VSUS.
Change audio amplifier from TPA3002D2PHP to TI6017A2
(BOM need change)
9 29 LAN Transfomer 2/27/2003 DELL ME Connectors are interfere Change RJ11/RJ45 receptacle connector to staddle type
10 18 VGA Daughter
Board Conn.
11 6,34,36 Clock Generator 3/05/2003 DELL
B B
12 8
13 21
Prescott
Processor
ICH5-IDE/LPC/
PM/GPIO/LAN
14 33,36 SIO (1/2) & PLD 3/05/2003 DELL Dell EE issue item26:
3/05/2003 Compal
Dell EE issue item38:
Change AGP connector vendor
Dell EE issue item22: 1.Del 24M_CLK net and R210(33_0402_5%)
This change is required due to not getting the 24MHz clk
of the EC to work.
Change connector from ACES_88075-1600 to FOXCONN
FOXCONN_QT00160A-9120L (BOM need change)
2.Add series termination R587(33_0402_5%) near CK409 and
R588(0_0402_5%) near the CPLD. Add net name from CK409 to
CPLD. (BOM need change)
3/05/2003 DELL Dell EE issue item23: To prevent backdrive in S3 Change RN7,R35,R37 pullups from +3VSUS to +3VRUN.
3/05/2003 DELL Dell EE issue item25: This pin is not 5V tolerant. Change R388 pullup from +5VRUN to +3VRUN.
Change name of the follow signal from GV_LO_HI# to GV_HI_LO#
Change name of the follow signal from GV_LO_HI# to GV_HI_LO#
15 25 AMP and Phone
16 18 VGA Daughter
17 12 Springdale-AGP
A A
Jack Interface
Board Conn.
/HUB/VGA/CSA
3/05/2003 DELL Dell EE issue item39:
1.Change the population option for R583 and R584 to no pop
2.Change the voltage rai lto D7, D6, D9, D8 to +5VRUN
3/05/2003 DELL
Dell EE issue item37:
Table for ST1 and ST2, were did this table come from?
3/05/2003 DELL
Dell EE issue item36:
AGP8X_DET_GC circuit need to change per the errata change.
1.R583,R584 Add "@" symbol and depop.
2.Change power from +12V to +5VRUN.
Delete ST1,ST2 table and R324~R327 (BOM need change) X00-D
Change Q13 from MMBT3904 to 2N7002; R55 from 33.2_0603_1% to
39.2_0603_1% (BOM need change)
Solution Description Rev.
X00-A
X00-A
X00-A
X00-A
X00-A
X00-A
X00-A
X00-C
X00-C
X00-D
X00-D
X00-D
X00-D
X00-D
X00-D
X00-D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
51 65Wednesday, January 28, 2004
A00-B
Page 52
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 2/10
Request
Page#
Item Issue DescriptionDate
18 21 HDD pinout are reversed Change pinout and and connector part number(BOM need change)
D D
2319
20 26 USB(2.0)
21 Springdale-DDR
11 3/07/2003 Compal
Title
ICH5-IDE/LPC/
PM/GPIO/LAN
D- MODULE 3/07/2003 Compal Change D- Module connector (Mating Height issue) X00-E
Connector
Interface
3/07/2003 Compal Change connector to staddle type. Foxconn Fox_UB11193-P01-TR
Owner
Compal3/07/2003
Change connector from JAE_WM1F068N1A to Foxconn
QL11343-A6B3-HT
ME Connectors are interfere X00-E
Dell M00 Board Bring up issue item34,35:
(BOM need change)
Add C636 and C637(0.1U_0402_16V4Z) [BOM need change] X00-E
SMXRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C65) to GND
SMYRCOMPVOH - add 0.1UF cap from +2.5V (pin2 of C53) to GND
22 Dell M00 Board Bring up issue item27
Follow CPLD rework instruction, correct U27 symbol pin out. X00-E3/08/200336 PLD DELL
Need to change PLD pinout per the right package program.
23 36 PLD 3/08/2003 DELL Dell M00 Board Bring up issue item28
Del U1,C10,R14,R18,RP1,R13 (BOM need change) X00-E
Eliminate the VID MUX and keep the zero Ohm resistors
24 8,18,36 3/08/2003 DELL Dell M00 Board Bring up issue item24
C C
25 8 Prescott
26 11 Springdale-DDR
Processor
Interface
3/12/2003 DELL Dell M00 Board Bring up issue item32
3/12/2003 DELL Value is not correct Change C636,C637 (0.01U_0402_16V7K) [Add it on BOM]
Change the table on pg 36 to reflect the correct refdes and
components see PLD rework instructions
Depop pullup R84 on H_RESET# since we have another pullup R358
27 14 FAN CONTROL 3/12/2003 Compal ME connector design change Change JFAN2 from MOLEX_53261-0310 to MOLEX_53398-0390; Delete
28 15,19 CPU Thermal
B B
29 19 CPU Thermal
30 25
Sensor & FAN
Control
Sensor & FAN
Control
AMP and
PHONE JACK
3/12/2003 DELL To saving cost Delete U35(AD7414ART-0),R345(10K_0402_5%),R348(0_0402_5%),
3/12/2003 Compal ME connector design change Change JFAN3 from MOLEX_53261-0310 to SUYIN_250019MR003G400ZL
3/12/2003 Compal ME connector design change for phone Jack and Int.SPK Change JSPK from MOLEX_53261-0690 to MOLEX_53398_0890;
Page36: Pop U27, C233, C606, R557 ;Pop Q42, R254, Depop R259 ;
Pop Q43, R561, Depop R251,R243 ; Pop R256, Depop R252; pop
R245, R253
Page18: Depop R96, Pop R98
Page8 :Pop R76,R78,R380
Page46: PR94,PR93, Depop PR95,PR92 [BOM need change]
Depop R84 ,62_0402_5%(BOM need change) X00-F
JFAN1 [BOM need change]
C383(0.1U_0402_16V4Z); Add Q73(MMBT3904) [BOM change]
[BOM need change]
change JP1 from HRS_DF20-10DP-1V to NAIS_AXN320C038P; Add
C638,C639(22U_1206_16V4Z) [BOM need change]
Solution Description Rev.
X00-E
X00-E
X00-F
X00-F
X00-F
X00-F
X00-F
31 24,25,50 Subwoofer 3/12/2003 DELL Add Subwoofer circuit Page24: U16 pin37 connect to C646 pin1(AUD_MONO_OUT)
Page25: Del R586(100K_0402_5%) [BOM need change]
Page50 : Add subwoofer circuit [Add ]
X00-F
32 31 CardBus Socket 3/12/2003 DELL All model support smart card function Update page3 Table and change mark "1@" symbol to "@" X00-F
33 21
34 31 CardBus Socket 3/13/2003 Compal X00-GCorrect Item32 Populate U17 and L14, delete "1@" symbol [Don't need change
A A
ICH5-IDE/LPC/
PM/GPIO/LAN
5
3/12/2003 DELL Follow Intel DG (12837)ICH_SYNC# circuit implementation Depop R161,R167,R169,Q32,Q33 and pop R438(0_0402_5%) [BOM
need change]
BOM]
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
X00-F
52 65Wednesday, January 28, 2004
A00-B
Page 53
5
4
3
2
1
Version Change List ( P. I. R. List )
Page3/10
Request
Page#
Item Issue DescriptionDate
35 27,31 Page27 :Change JMDC from FOX_QT8A0301-3011 to AMP_3-1612118-0
D D
36 31 CardBus Socket 3/14/2003 DELL
Title
Owner
Compal3/14/2003
ME connector design change
Page31: Change JCBUS form FCI_61082-081001 to
FOX_1CA87501-T1~D; Change J1394 from FOX_UV31413-K8 [BOM need
change]
Dell Schematic issue item12 Add C656(100P_0402_50V7K). [BOM need change] X00-G
Please add a 100PF cap to SC_DATA_C per TI late recommendation
37 Prescott
8 3/14/2003 DELL H_DPSLP# doubule pull up Depop R79(62_0402_5%) , [BOM need change] X00-G
Processor
38 25 AMP and
39 25 AMP and
PHONE JACK
PHONE JACK
40 29 LAN TRANSFOMER 3/14/2003 DELL Dell Schematic issue item45,46
C C
41
50 Subwoofer 3/14/2003 DELL
42 6 Clock Generator 3/14/2003 DELL Dell Schematic issue item30
Delete by Dell's update issue_0314 ;X00-H
43 Springdale-DDR
11 3/18/2003 Compal Intel recommend is 31.12K,the value isn't popularize.
Interface
44 25 AMP and
PHONE JACK
45 36,39,40 3/18/2003 Compal Single name issue Delete pin 22 of U27 net and show text ; move U25B from page39
46 23 D- MODULE 3/18/2003 DELL
B B
47 19 CPU Thermal
48 37 Thermtrip &
49 20,26 3/20/2003 DELL Dell Schematic issue item65ICH5-PCI/HUB/
Sensor & FAN
Control
PowerGOOD
USB/AC97
50 BT PORT and MDC27 3/20/2003 DELL Dell Schematic issue item66
3/14/2003 DELL Dell Schematic issue item48
Connect C638 and C639 to INT_TWT_R1 and INT_TWT_L1 at JSPK X00-G
Remove comment above U18 and remove the wires in the bottom
3/14/2003 DELL Dell Schematic issue item48
Change the pinout of JAUDO
the BJT werent driving the LED enough
Dell Schematic issue item48
Move D18 and D19 to page 42, and update all component Symbols
Springdale DG P65 recommed a 10 Ohm resistor from CK_VDD_MAIN
to Pin VDD_48 (pin34) of Ck409
Follow Dell's DT team use 30.9K
Change net FAN1_TACH_FN from pin16 to pin18, pin15,16 connect
to GND
2.LED_WLAN5_RADIOSTATE, LED_WLAN24_RADIOSTATE, and
WLAN_LED_ACIVITY. Add 10K_0402_5% pulldown resistor(R600~R602)
[BOM need change]
Move D18 and D19 to page 42, and update all component
Symbols , move C655 from current location to in between
C645 and U45 pin 2 and change value to 1000P_0402_50V7K
Reserved power source option: populate R589, depopulate R599
[BOM need change]
Change R101,106,369,373 from 31.12K_0603_1% to 30.9K_0603_1%
;[BOM need change]
3/18/2003 Compal Add one net for Phone Jack board pullup source. Change JAUDO pin11 from NC to AMPVCC X00-H
to page40, change pin4,5 to GND and pin6 to NC.
Dell Schematic issue item59
Please make R569 100K Ohm
3/18/2003 DELL Dell Schematic issue item57
Change R569 from 1K_0402_5% to 100K_0402_5% ;[BOM need change] X00-H
Add C657(2200P_0603_5V7K);[BOM need change]
Please add a cap pad (2200PF) across MCH_THERMDA MCH_THERMDC
3/18/2003 DELL Dell Schematic issue item61
Change R581 pin1 pullup from +3VSUS to +3VRUN X00-H
change the pullup rail for R581. to +3VRUN
Change JUSB1 port signal from USBP0+/- to USBP5+/- ; from
Can we move the USB port 0 (BaACK) to Port 5 and Keep port 0
as Reserved
USB_OC0# to USB_OC5#; USBP0_PWR to USBP5_PWR
Depop R449(10K_0402_5%) and R463(0_0402_5%) ;[BOM need change] X00-I
Depop R449 And R463 per our MDC team
51 28 3/20/2003 DELL Dell Schematic issue item67ETHERNET
Pop option R311 1.24K – 5705 and 1.27K -- 4401
A A
change]
Solution Description Rev.
X00-G
X00-G
X00-G1.Change Q3 from DTC144KA_SOT23 to 2N7002
X00-G
X00-G
X00-H
X00-H
X00-H
X00-I
X00-IChange R311 to 1.27K_0402_1% for Nimitz only;[Nimitz BOM need
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
EE_P.I.R History
Size Document Number Rev
Date: Sheet of
LA-1711
53 65Wednesday, January 28, 2004
1
A00-B
Page 54
5
4
3
2
1
Version Change List ( P. I. R. List )
Page4/10
Request
Page#
D D
52 28
53 50 Subwoofer Dell Dell Schematic issue item73
54 25 AMP and
55 23 D-MODULE 3/20/2003 Dell Dell Schematic issue item84,85
C C
56 14 FAN CONTROL 3/21/2003 Compal Follow Compal standard FAN connector pin define for 12V FAN 1.Change FAN2 from Molex 53398-0390 to 53398-0490.
57 31 CardBus Socket 3/21/2003 Dell
58 Prescott
9 3/25/2003 Change 22uF decoupling Caps from 22U_1210_10V6K to
59 Thermtrip &
37
60 CPU Thermal
B B
19 3/25/2003 Dell Dell Schematic issue item64 X00-L
61 LAN TRANSFOMER29 3/25/2003 Dell Dell Schematic issue item74
TitleItem Issue DescriptionDate
ETHERNET Populate R302 (10K_0402_5%) ; [BOM need change]
PHONE JACK
Processor
PowerGOOD
Sensor & FAN
Control
3/20/2003
3/20/2003
3/20/2003 Dell Dell Schematic issue item75
Owner
Dell
Dell
Dell Schematic issue item70
EPROM R302 should always be popped according to Ron
(COMMS/LAN guy)
Note : Only Beijing populate, R302 change to mark"1@"
BOM Update on SST X00-I
1. C648 needs to be at least a 25V rated capacitor
2. C643, C646, C650 and C652 need to change to at lease 16V
rated capacitors
3.Add a 1000PF(C658) cap to the INN signal similar to the INP
signal
4.Change C641 to a 1uF 16V capacitor
1.BOM update on SST
1. Change C634 and C633 back to 0.47uF 0603 capacitors
2. Change JAUDIO pin 11 from AMPVCC to 5VRUN
3. Change the pullup on HP_NB_SENSE (R459) from 3VALW to 3VRUN.
1.SATA_MOD pull up R569, can be changed to 3VRUN
2.Please change the pull ups on BAYPRES# R553, and USB/IDE#,
R554 to +3VRUN
Dell Schematic issue item84,85 Change C175 from 4.7u_1206_16V6K to 0.1U_0402_16V4Z; change
TI Cardbus review issue: Please change C175 value to 0.1UF cap,
change C150 value to 4.7UF cap
Height Interference Issue with C46, C45, C56, C55 inside the
CPU socket cavity
Dell Schematic issue item54
Issue of draining RBAT
2. Change JAUDIO pin 11 from AMPVCC to 5VRUN
3. Change the pullup on HP_NB_SENSE (R459) from 3VALW to 3VRUN.
1.Change R569 pullup to +3VRUN
2.Change R553, and R554 pullup to +3VRUN
2.Pin1 connect to GND; Pin2 connect to FAN2_TACH_FB,
Pin3 NC, Pin4 connect to FAN2_VOUT
C150 from 100P_0402_16V4Z to 4.7u_1206_16V6K [BOM need change]
22U_1206_6.3VAM; [BOM need change]
Q55
Change Q50,Q71 from DTC144EKA_SOT23 to 2N7002_SOT23 ;
[BOM need change]
Pin14 of U37 change to NC.
Maybe cause a problem if the system is in battery optimized
mode, or a lower VCORE voltage.
Delete R1, R2, R3, and R4 ; [Nimitz BOM change only] X00-L
Delete R1, R2, R3, and R4
62 Dell Schematic issue item74
37 X00-MPopulate U36, R353,R352,R355,R360,R362,R94
PowerGOOD
3/26/2003 DellThermtrip &
Please depop the MAX6509 and pop the LMV331 circuit
C51,C392 ; Depop U4,R89 and R93 [BOM need change]
63 36 PLD 3/31/2003 Dell Dell Schematic issue item73(3/28)
Please replace Q42 and Q43 with FETs (3904)
Solution Description Rev.
X00-I
X00-L
X00-I
X00-I
X00-J
X00-J
X00-LDell Schematic issue item62
X00-L3/25/2003 Dell
X00-NChange Q42,Q43 from DTC114TKA to MMBT3904; [BOM need change]
64 26 USB(2.0)
Connector
65 31 CardBus Socket 6/16/2003 Compal Compal EMC Team suggestion mount 0 ohm resistors to substitute
A A
66 28 ETHERNET 6/16/2003 Compal Change EEPROM from 16KB(93C86) to 1KB(93C46).Save cost Depop R299; [BDQ20 BOM need change], we used 93C46 on SST BOM X01-A
5
6/16/2003 Compal Compal EMC Team suggestion mount 0 ohm resistors to substitute
choke. The result was PASS for mockup2 EMI test and save cost
choke. The result was PASS for mockup2 EMI test and save cost
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Depop L1~L4,L44,L47 ; Pop R5~R12,R407,R408,R565,R566 [BOM
need change]
X01-A
Depop L7; Pop R144~R147 [BOM need change] X01-A
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet of
EE_P.I.R History
LA-1711
1
54 65Wednesday, January 28, 2004
A00-B
Page 55
5
4
3
2
1
Version Change List ( P. I. R. List )
Page5/10
Request
Owner
D D
36 PLD 6/16/2003 Compal X01-A
68 36 PLD 6/16/2003 Dell Change R246 from 10K_0402_5% to 100_0402_5%
69 37 Thermtrip &
70 30,31
71 +RTC_PWR circuit elimination37~41,43,
48
72 39 Power Control 6/16/2003 Compal Depop V_1P25V_DDR_VTT,+VCC_CORE,+3VRUN discharge circuit to
C C
PowerGOOD
PCMCIA
Controller &
CardBus Socket
6/16/2003 Dell Add the RUNPWROK_1P5V to PowerGood sequence circuit RUNPWROK_1P5V signal connect to pin5 of U25, Del original
6/16/2003 Remove Nimitz Smart card function supportDell Depop U17, L14, C174,C149,C175,C182, C150,C151,
6/16/2003 Compal 1.Change power source from +RTC_PWR to +3.3VRTC
73 50 Subwoofer 6/16/2003 Compal Change subwoofer detect signal to low active. Change net from SUB_DETECT to SUB_DETECT# X01-A
74 BT PORT and MDC 6/19/2003 Compal27 X01-BME design change. Change BT connector type to vertical
75 27 BT PORT and MDC 6/19/2003 Compal Add MDC cable clips to fixed the wire X01-B
76 39 Power Control 6/19/2003 Compal Depop +3VMOD circuit components.(Reserved for 3.3V SATA)
77 Power Control 6/19/2003 Due to PWR_SRC voltage range (6V-11V)during batty swap, there
39
78 Dell Schematic issue REV00, item2
29 6/25/2003 DellLAN Transfomer
B B
79 37
80
40 6/25/2003 Dell Reverse EMI Clips position X01-C
Thermtrip &
PowerGOOD
PAD,Screw Hole
6/25/2003 Dell Dell Schematic issue REV00, item 4,5
Compal
+3VRUN leakage issue when system enter S3 Change pin1 of R559 from +3VSUS to +3VRUN
Fixed huang up when BIOS enable C2 mode and throttling mode.
H_STPCLK# and CLK_STP_CPU# pullup resistor too large.
save cost.
is an issue with Q20 not turning on due to VGS requirements.
The +3VSUS rail measured around 2.8Votls.
The issues occurs when the LOM is not active and the wireless is
active. BCM570M to drive significant current through the FET.
Kapalua added a gate to and SUSPWROK_5V with SUS_ON for faster turn off
Kapalua team have changed the ALW_ENABLE# circuit Ored pin12 of Y24
with THERM_TRIP from OTP to generate ALW_ENABLE#.
R254,R561 from 10K_0402_5% to 470_0402_5%
Add R603,R604(680_0402_5%) [BOM need change]
RUNOK net, pin11 of U26 connect to pin4 of U25, pin6 of U25
connect to pin10 of U26
C154,C656,R170,R187,R189; Change U9 to PCI4510
[BDQ20 BOM change]
2.Change U28 to SN74LVC74; U23 to SN74LVC32; U24
to SN74LVC14; Remove U19
3.U24C,U24D to substitute U19. [BOM need change]
Depop R175,R176,R178,R190,Q34~Q37 [BOM need change] X01-A
Change type from JST_SM10B-SRSS to JST_BM10B-SRSS [BOM need change]
Add PAD1~3 [BOM update]
Depop R257,R258(100K_0402),Q41,Q45,C236(.01U_0603),C235(4.7U_1206)
[BOM need change]
1.Change Q20 from SI3456DV to SI3443DV
2.Change R51 from 470K to 100K ohm, pin1 pullup to +3VSRC. pin2
connect to pin1 of Q15 and pin3 of Q20
3.Remove R50,R53(470K_0402),R54(200K_0402)and Q14 [BOM need change]
Add a BAT54A on the LOM leg and the WLAN leg, and changing R32 from
200 Ohm 150 Ohms works well and maintains the same LED brightness.
[BOM Change]
1.Depop Q71 and R571 [BOM need change]
2.Add RC delay(R607,C659)on THERM_PWRDWN signal. [BOM need change]
3.Prevent leakage, add D23(RB751) and R606 during D8 of U15B and
ACAV.[BOM need change]
Add EMI Clips. Defaule depopulate.
Solution Description Rev.Page#67TitleItem Issue DescriptionDate
X01-A
X01-A
X01-A
X01-A
X01-B
X01-B
X01-C
X01-C
81 10,34 6/25/2003 Dell Dell Schematic issue REV00, item20
Connect the VCORE_VTT (PROCHOT pin of the core regulator) to a
Wake pin on the keyboard controller and add a zero Ohm (No
pop) resistor to the pin3 of Q4
82
83 Need to assign a GPIO from keyboard controller to SUB_DETECT#
A A
CPU Decoupling
5
6/26/2003
6/26/200333,36,50 Dell Del C3/C4# net. Connect SUB_DETECT# signal to pin F14 of U15 X01-D
Compal Increase CPU_vore plane Remove C35~37,C39(Original depop) X01-D9
signal
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
VCORE_PHOT# connect to (pin F15) of U15. Add R605 zero ohm
(depop) resistor from PR106 pin 1 to pin 3 of Q24.
DELL CONFIDENTIAL/PROPRIETARY
Title
EE_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
55 65Wednesday, January 28, 2004
X01-C
A00-B
Page 56
5
4
3
2
1
Version Change List ( P. I. R. List )
Page6/10
Request
Owner
D D
24,25 6/27/2003 X01-EDell Dell Schematic issue REV00, item 25
Audio circuit changes to fix SNR+HD fix- Motherboard changes
85 Prescott
8 6/27/2003 Dell Dell Schematic issue REV00, item 25
Processor
Change R336 value to 681 Ohm per yhe Springdale/Prescott/ICH5
platform field messages WW17
86 Dell Schematic issue REV00, item 26
Please add a zero Ohm to H_PROCHOT# pin to the GMCH pin L20.
Please add a 1000pF cap to GND (filtering) close to the
H_PROCHOT#
87 6/30/2003 Dell
C C
88 7/3/2003 CompalICH5-IDE/LPC/
21 Change board ID for Pre-PT Depop R130(10K_0402); Pop R128(10K_0402) [BOM need change] X01-G
PM/GPIO/LAN
Dell Schematic issue REV00, item 27 Rename net name from LONG/SHRT# to DT/MT_SELECT, connect to
Please rename LGPIO57 of KBC pin N7.as the DT#/MT GPIO>
89 CPU Decoupling9 7/3/2003 Compal Cost down (reduce cap Q'ty per vendor test)
90 14 FAN CONTROL 7/3/2003 Compal Dell request don't use tantalum cap
91 8,10,50 7/3/2003 Compal Cost down Change C366,C372,C654 from 220P_NPO to X7R [BOM need change] X01-G
92 8,18,36 7/3/2003 Dell PLD Disable X01-G
93 26 USB(2.0)
B B
94 ICH5-PCI/HUB/
20 7/15/2003 Compal Implement Compal standar part(Save cost) Del RP2,add 2pcs 8P4R(RN111,RN112). [BOM need change]
95 ICH5-IDE/LPC/
21 7/18/2003 Dell NIMITZ_PT_EE_ISSUES_LIST_REV00, item 28 Depop R126,R128; Pop R123,R130 [BOm need change]
96 17 DDR Termination
Connector
USB/AC97
PM/GPIO/LAN
Resistors
97 Clock Generator6,24 7/18/2003 Dell NIMITZ_PT_EE_ISSUES_LIST_REV00, item 30
98
99 33 7/18/2003 Dell NIMITZ_PT_EE_ISSUES_LIST_REV00, item 29SIO (1/2) Add R615(0_0402_5%)between SUB_DETECT# and pin D16 of U15.
A A
100 40 7/18/2003 Compal
CPU Thermal Sensor
& FAN Control
PAD,Screw Hole
5
7/15/2003
Compal Heigh limit issue(Move L47,R565,R566,C610,C611 to top side) Swap USBP4-/+ and USBP4_D-/+ for trace routed.
Change board id to reflect X02
7/15/2003 Dell Add V_1P25V_DDR_VTT decoupling cap Reserve C661~C668 and depop
Please add the 14MHz clcok to the AC97 codec path. This will be for
testing only. We need to add two zero Ohm resistors to disable the path.
7/18/2003 Dell19 NIMITZ_PT_EE_ISSUES_LIST_REV00, item 31
Change the third fan circuit to the high side FET
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
1. Remove R498 and R499 from the HP_OUT lines on page 24 and
short across them.
2. Connect HP_OUT_L and HP_OUT_R to C633.1 and C631.1
respectively (page 25)
3. Rename pin 9 of U38 to HP_OUT_LMAX and pin 11 to
HP_OUT_RMAX.
4. Rename pin 6 of JAUDO to HP_OUT_LMAX and pin 8 to
HP_OUT_RMAX.
Change R336 from 2.43K_0603_1% to 681_0603_1%[BOM need change] X01-E
Add C660(Depop) close to pin C3 of JCPU and R608(0_0402)
close to pin L20 of U3 [BOM need change]
pin2 of PQ68 and NC pin12 of U27
Depop C296,C297,C299,C301,C423(470uF) ; Depop C27,C32(22uF)
[BOM need change]
Change C110,C622 from 100uF/16V Tan cap to 47uF/16V [BOM need
change]
Depop Q42,Q43,R254,R561,R603,R604,R256,R245,
R252,R253,R246,R559,R557,U27,C233,C606,R588,R98
,R76,R78,R380
Pop R96, R243,R251,R259 [BOM need change]
Reserve R611~R614 and C669; Depop
Change Q28 from SI3456DV to SI4435DY, pin1,2,3 of Q28 connect
to 12V, pin5,6,7,8 connect to pin1 of JFAN3, pin3 of JFAN3
connect to GND. Add R609,R610,Q75 for Gate control. [BOM need
change]
[BOM need change]
Del PAD8, PAD9 X02-ADelete reserved EMI cilps
Solution Description Rev.Page#84TitleItem Issue DescriptionDate
,Add R83(7/9)
2
X01-F8,10 6/30/2003 Dell
X01-F33,36,49
X01-G
X01-G
X02-A
X02-A
X02-A
X02-A
X02-A
X02-A
X02-A
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
56 65Wednesday, January 28, 2004
A00-B
Page 57
5
4
3
2
1
Version Change List ( P. I. R. List )
Page7/10
Request
TitleItem Issue DescriptionDate
D D
101
102 Springdale-Host
103
104 7/22/2003 Dell The original fan circuit has a D pack 100uF cap. This
105 20 ICH5-PCI/HUB/
C C
106 11,15,16 8/27/2003 Dell Reduce power consumption when system enter S3 mode 1.Change R415,R418,R440,R442 from 75_0603_1% to 150_0603_1%
CPU Thermal Sensor
19 7/21/2003 Dell X02-B
& FAN Control
10 7/21/2003 Dell
/GND
24 AC97 Codec 7/22/2003 Dell
CPU Thermal Sensor
19
& FAN Control
USB/AC97
8/27/2003 Compal Compal EMC fine tune and request add CK_66M_ICH AC termination. X02-EPopulate R413(10_0402_5%) and C464(10P_0402_50V8J) [Change
Owner
NIMITZ_PT_EE_ISSUES_LIST_REV00, item 32
Add the Op amp circuit (NP) to the High side FET circuit.
NIMITZ_PT_EE_ISSUES_LIST_REV00, item 33 1. Change R90 to 1.24K_0402_5% ; R91 to 10K_0402_5%
Modify the PROCHOT circuit:Change R90 to 1.24K Ohm
Change R91 to 10K Ohm, add a 100pF cap across R91
NIMITZ_PT_EE_ISSUES_LIST_REV00, item 51 Add R619(0_0402_5%), pin1 of R619 connect to R613,
CK_14M_CODEC is a floating antenna as it currently exists,
please add 0 ohm resistor to GND
circuit doesn't have it. This may cause an issue.
1. Reserve one OP(LM358) circuit. Defaule depop.
2. Del PAD7 location for LM358
2. Add C670 (100P_0402_NPO) [BOM need change]
pin2 of R619 connect to GND. [BOM need change]
have not enough space to put 47uF D type capacitor. So change
C88 to 22uF/16V_1206 and add one more C673 [BOM need change]
Have not enough space to put 47uF D type capacitor. So keep
C88 to 10uF/16V_1206 and reserve C673(22uF_16V)depop.
by PT memo; BOM need update]
2.Change R100,R104 from 150_0603_1% to 300_0603_1%[Change by
PT memo]
107 21,24 8/27/2003 Dell Unnecessary populate components Depop R141 and R526 [Change by PT memo; BOM need change] X02-E
108 34 SIO (2/2) 8/27/2003 Dell System erroneous to detect AC always exist. Depop R606 and change D23 to 47K ohm [Change by PT
109 9 CPU Decoupling 8/27/2003 Dell power team request change.Dell Change all from 470uF to 330uF. Populate
memo; BOM need change]
C68,C294,C296,C298,C300,C302,C304,C422. [Change by PT phase,
BOM need change]
Nimitz(BDQ20) +3VRUN back drive when system enter S3Compal9/17/2003110 ETHERNET28 Change pin P1,G2,A1 of U2A from +3VRUN to +3V_LOM_PCI X03-A
Solution Description Rev.Page#
X02-B
X02-C
X02-C
X02-D
X02-E
X02-E
X02-E
111 LAN Transfomer29 9/17/2003 Dell For LAN signals power requirement Change R19~R26 from 0402 to 0603 [BOM need change] X03-A
112 37,39 Dell System can't reboot after flashing the BIOS(Thermal event)9/17/2003Thermtrip &
B B
PowerGOOD
113 34,40 9/17/2003 Dell ACAV back drive issue Use the spare gate U23C, pin9 and pin10 connect to ACAV side
114 9/29/200321,33,39 Change bridge battery to cell batteryDell Depop bridge battery circuit: Depop R158,R232 and D3
115 39 10/02/2003 Compal NIMITZ_ST_GERBER_ISSUES, item 5
Power Control
1.Change pin2 of Q56 net from THERM_FF_GATE to PWRGD_3V
2.VAUX_EN signal add R622(100K)pull down to GND
of the reserve 0 ohm, pin8 to a 47K ohm resistor and place
closely to EC. Connect the other side of the 47K ohm resistor
to pin D8 of U15 [BOM need change]
Pop cell battery circuit: Pop R623,R624 and D23(BAS40-04)
Depop C33 [BOM need change]
X03-A
X03-A
X03-C
X03-D
Fix power up sequencing issue with the +3VSRC to +3VSUS
116
18,37 10/02/2003 Dell
8
117 10/07/2003 Dell
A A
Processor
5
NIMITZ_ST_GERBER_ISSUES, item 12
Add the Graphics contrroller thermtrip circuit
NIMITZ_ST_GERBER_ISSUES, item 13
Adjust the VID_PWRGD to GMCH_VTT PWRGD, need change C121 value
from 0.1uf to 0.47uf
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Add a 0 ohm(R626) from pin 28 of JVID to pin1 of U47 and make net name
to GC_THERMTRIP#. Add a 10K(R625) pull-up resistor from GC_THERMTRIP#
to +3VSUS, make Pin 2 of U47 to pin4 of U29, pin4 of U47 connect to
THERM_TRUE#. Rename THERM_CPU# to NB_THERMTRIP#
Change C121 from 0.1uf to 0.47uf [BOM need change]
DELL CONFIDENTIAL/PROPRIETARY
Title
EE_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
X03-D
X03-DPrescott
57 65Wednesday, January 28, 2004
A00-B
Page 58
5
4
3
2
1
Version Change List ( P. I. R. List )
Pag 8/10
Request
TitleItem Issue DescriptionDate
D D
24 10/07/2003 Dell X03-D
118
Owner
NIMITZ_ST_GERBER_ISSUES, item 18AC97 Codec
Change R223 from 20k_0402 to 43K_0402[BOM need change]
To change the PCBEEP volume
119 10/07/2003 Dell NIMITZ_ST_GERBER_ISSUES, item 15
Audio circuit value changes to adjust EQ values and gain
120 24,50 10/8/2003 Dell
NIMITZ_ST_GERBER_ISSUES, item 15
Audio circuit value changes to adjust EQ values and gain
121 10/8/2003 Dell NIMITZ_ST_GERBER_ISSUES, item 19
Please add a zero Ohm resistors to the X_Out side of the
crystal to reduce the drive level
122 10/8/2003 Compal35 INT KB & ROM Int.KB connector EOS protect X03-E
123 Thermtrip &
C C
37 10/8/2003 Compal Change R625 pullup from +3VSUS to +3VRUNTo prevent leakage when system enter S3. X03-E
124 19 CPU Thermal
PowerGOOD
Sensor & FAN
Control
10/8/2003 Dell NIMITZ_ST_GERBER_ISSUES, item 1
3rd Fan circuit modiy to linear
125 6,21 10/9/2003 Dell Modify Item 121
126 35 INT KB & ROM 10/9/2003 Compal Int.KB connector ESD protect
127
128 18 VGA Daughter
129
25 AMP and
B B
130 10/9/2003 Dell
26
131 LED Interface
38 10/13/2003 Compal Board band issue on net POWER_SW# Del POWER_SW_EMI net, also del R47 and pin1 of R47 net
132 ICH5-IDE/LPC/
21 10/13/2003 Compal Change board ID for ST Pop R128; Depop R130 [BOM need change] X03-G
PowerGOOD
Board Conn.
PHONE JACK
Connector
& IrDA
PM/GPIO/LAN
10/9/2003 Dell
10/9/2003 Dell
10/9/2003 Dell
NIMITZ_ST_GERBER_ISSUES, item 21
Please add a zero Ohm resistor between pins 2 and 4 of U47
NIMITZ_ST_GERBER_ISSUES, item 22
Please Make R626 NP to be able to plug the currnet video cards
NIMITZ_ST_GERBER_ISSUES, item 23
Pin 12 of U18 needs a zero Ohm to GND
NIMITZ_ST_GERBER_ISSUES, item 16
Add the National Power switch to control Q68
133 31 CardBus Socket 10/14/2003 Compal Remove smart card function on Alcatraz X03-HDepop U17,L14,R170,R172,R187,R189,C149,
134 34 SIO (2/2) 10/14/2003 Dell Dell recommended PS_ID circuit,add one GPI pin to EC
135 19,31,37 11/17/2003 Compal Correct BOM error items to meet ST PCBA
136 10 12/09/2003 DellSpringdale-Host
A A
/GND
Need to separate the CPU GTLREF from the GMCH GTL REF per
Intel's errata.
1. Change C630~C633 from 0.47u_0603 to 0.022u_0603
2.Change C655 to 0.22uf; add R627(1K ohm) from pin2 of C645 to pin2 of
U45
3.Pop R593 and depop R597 [BOM need change]
1. Change C630~C633 from 0.22u_0603 to 0.01u_0603
2.Change C645 to 0.056uf; change R627 to 1.21K, pin1 of R627 connect
to pin2 of C645, pin2 of R627 connect to
pin2 of U45 and pin 2 of C655
3.Change C638,C639 from 22u to 4.7u [BOM need change]
Add R629 between pin2 of X6 and pin 5 of U39; add R630 between pin1
of X4 and pin AB12 of U5D; add R631 between pin1 of X1 and pin N10
of U2A [BOM need change]
Add RN113~RN118, R628 [BOM need change]
Depop R609,R610 ; Pop R617,R618,C671 and U46; pop R616 and change
value to 1M ohm; change Q28 from SI4435DV to SI3457; Change C88 to
47uF_D_16V [BOM need change]
Modify: pin1 of R629 connect to pin2 of X6 , pin 2 connect to pin5 of
U39; pin1 of R630 connect to pin1 of X4 , pin2 connect to pin AB12
of U5D
Pop CN1~CN6, C148 [BOM need change]
Add R635 between pins 2 and 4 of U47 (Depop)
Depop R626 for used PT VGA cards.
Add R632, pin1 connect to pin 12 of U18, pin2 connect to GND
[BOM need change]
Reserved LM3726 circuit X03-FUSB(2.0)
+3.3VRTC [BOM need change]
C150,C151,C154,C174,C175,C182 [BOM need change]
Connect pin G10 of U15 to pin2 of PR268. Net name:PS_ID_DISABLE#
Depop C656 , Q75; Pop C674 [BOM change by ST memo]
Depop R329 [BOM need change]
Solution Description Rev.Page#
X03-D24,50
X03-E
X03-E6,21,25
X03-E
X03-F
X03-F
X03-F37 Thermtrip &
X03-F
X03-F
X03-G
X03-H
X03-I
X04-A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
58 65Wednesday, January 28, 2004
A00-B
Page 59
5
4
3
2
1
Version Change List ( P. I. R. List )
Pag 9/10
Request
TitleItem Issue DescriptionDate
18 12/09/2003 Dell X04-A
137
D D
138 21 ICH5-IDE/LPC/
VGA Daughter
Board Conn.
PM/GPIO/LAN
12/09/2003 Compal Fix false OTP failure when AC or battery are plugged in. Change R441 pullup from +3.3VRTC to VCC_RTC
Owner
Enable Gfx OTP
Pop R626 [BOM need change]
31,34139 12/09/2003 Dell Add the AC adapter over current sense GPIO Change pinH11 of U15 from SCR_DETECT_C to OVP_AC_ADAPT
140 34 SIO (2/2) 12/09/2003 Dell PBAT_SMBDAT/CLK rise time have risk over SPEC Change R198 and R513 to 8.2K_0402 [BOM need change]
141 38 12/09/2003 DellLED Interface
& IrDA
Move the ESD issue cap from the LED flex to the motherboard Add C676 near pin2 of JLED1[Update BOM]
142 36 12/17/2003 Dell Please Pop R559, with 1K resistor pullup to STP_CPU# Pop R559 [Update BOM] X04-BPLD
143 12/17/2003 Dell Please change the PS_ID_DISABLE to LGPIO75 Change PS_ID_DISABLE from pin G10 of U15B to pin B11 of U15A33,34
26
144 12/17/2003 Compal Noise form doghouse data transfer Add C677,C678 and C679(5.6U_B2_25V)on DH_PORT_PWRSRC signal
C C
30
146 26
147 add a pullup resistor to +3VSUS to GC_THERMTRIP#Dell12/18/2003Thermtrip &
37 Reserve R636 and depop it.
148 26 12/20/2003 Dell Noise form doghouse data transfer Depop C677,C678 and C679(5.6U_B2_25V) for reserve.
149 ICH5-IDE/LPC/
21 12/20/2003 Dell Change board ID for QT X04-DDepop R123,R128 and R115; Pop R116,R126 and R130 [BOM need
150 12/20/2003 Dell
151 Springdale-Host
10 12/22/2003 Dell Update Item 136 (Nimitz_QT_GERBER_ISSUE item2) Pop R329, keep the circuit as it was in ST X04-D
B B
152 Prescott
8 Depop R70 [BOM need change] X04-D
153 12/22/2003 Dell12 X04-DWe have found some ringing on the signal while investigating
154 6,24 12/22/2003 Dell Nimitz_QT_GERBER_ISSUE item33(AC97 X'tal cost down) Pop R611(24_0402),R613 and R614(0_0402), Depop X2,C168,C183
155 12/22/2003 Dell Nimitz_QT_GERBER_ISSUE item32(Change VID_PWRGD to VCORE_ENLL
8 Prescott
156 ICH5-PCI/HUB/
20 12/22/2003 Dell Nimitz_QT_GERBER_ISSUE item28 (Confirm the pullups to from 5V
USB(2.0)
Connector
PCMCIA Controller
USB(2.0)
Connector
PowerGOOD
USB(2.0)
Connector
PM/GPIO/LAN
/GND
Processor
Processor
USB/AC97
12/17/2003 Dell145 Change cardbus controller symbol to PCI4510 None
12/17/2003 Dell Change the USB Swiches to the Ti2062 parts Change U31,U32 to TPS2026 [BOM need change]
change]
Need to add a zero Ohm connection from the AC adapter current sense
GPIO to H_PROCHOT# as a path in case the GPIO does not work.
12/22/2003 Dell Nimitz_QT_GERBER_ISSUE item18: need to populate R70, optimized
per the design guide
the S3 isuse.
Add R637(0ohm) between OVP_AC_ADAPT# and pin H11 of U15;
reserve Q76(3904) for over current occure to throttle down
CPU speed. [BOM need change]
Reserve C680 to the PCI_PCIRST# signal going to the MCH, move
R245 near U8 to reduce stub.
and R619 [DDQ21 only]
delay time)
for the USB Ocs are OK?)
Change R155 to 8.2K and C121 to 1UF [BOM need change] X04-D
ICH5 Spec are 5V tolerance, we change to +3VSUS X04-D
157 12/29/2003 Dell24 PC Beep issue-Too loudAC97 Codec Change R223 to 300K [BOM need change] X04-D
Solution Description Rev.Page#
X04-A
X04-A
X04-A
X04-A
X04-B
X04-B
X04-B
X04-B
X04-C
X04-D
X04-D10,34
X04-D
158 37 Thermtrip &
A A
PowerGOOD
12/29/2003 Dell Change OTP point to 90 deg.C Change R353 to 1.82K [BOM need change] X04-D
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
59 65Wednesday, January 28, 2004
A00-B
Page 60
5
4
3
2
1
Version Change List ( P. I. R. List )
Pag 10/10
Request
Owner
158 Clock Generator6
D D
159 9 1/09/2004 CompalPrescott
160 21 ICH5-IDE/LPC/
Processor
PM/GPIO/LAN
1/19/2004 Compal Change board ID to A00 Depop R130 ; Pop R128 [BOM need change] A00-A
Changes to the Load caps per the measurements from TDK 1/09/2004 Dell X04-E
Capacitors under Prescott CPU interfere with socket inside cap. Depop inside cap C45,C46,C55 and C56; Pop C77,C331,C71 and
161 6,24 Dell1/28/2004 Same as PIR item 154 (AC97 X'tal cost down) A00-B
C C
Pop C598 and C597(22pf_0402) [BOM need change]
C72 [BOM need change]
Pop R611(24_0402),R613 and R614(0_0402), Depop X2,C168,C183
and R619 [For BDQ20 BOM change]
Solution Description Rev.Page# TitleItem Issue DescriptionDate
X04-E
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet of
EE_P.I.R History
LA-1711
1
60 65Wednesday, January 28, 2004
A00-B
Page 61
5
4
POWER Version Change List ( P. I. R. List )
3
2
1
Request
Page#
Item Issue DescriptionDate
D D
1 45
Title
1.25V/2.5V
Owner
Compal2/26/2003
Dell M00 Board Bring up issue item13:
Depop PR86 (PR86 is populted on M00)
Make SUSPOWROK_5V a strong pullup.
3.3V/5V2
43 2/26/2003
46,47
3 DELL
CPU_CORE_Controller
CPU_CORE_Power-Stage
2/26/2003
4 46 CPU_CORE_Controller
C C
5 44,45 +1.5VRUNP/ +VTT_GMCHP
3/07/2003 DELL Intersil ISL6225B IC issue. So change controller IC. Change PU7 to SC1485 and PU8 to SC1486.
DELL
Dell M00 Board Bring up issue item21:
Need to add pads for voltage/temp tolerance measurements.
Request from our Reliability engineers.
Dell M00 Board Bring up issue item29:
Change CPU controller and driver VCC to +5VRUN
to reduce S3 current.
Dell X00 Board issue item40,41:
Change the power rail to the following components PR99,
PU20A/B, PC214 from +5VSUS to +5VRUN
Change the power rail to the following component PR114
from +3VSRC to +3VRUN
Add voltage divider at +5VSUSP(PR227, PR229)
Add voltage divider at +3VSRCP(PR228, PR230)
Change PU9 and PU11, PU12, PU13, PU14 VCC
to +5VRUN
Change the power rail of PR99 and PU20A/B,
PC214,PR97 from +5VSUS to +5VRUN
Change the power rail of PR114 from +3VSRC to +3VRUN
1.25V/2.5V
6 45 1.25V/2.5V 3/12/2003 DELL
7 44
+1.5VRUNP/ +VTT_GMCHP 3/18/2003 DELL
8 46 CPU_CORE_Controller 3/18/2003 DELL
B B
Dell X00 Board issue item47:
Intle in the DG 1.21 update have changed the DDR voltage
to 2.6V and Term voltage to 1.3.
Dell X00 Board issue item52:
A new requirement from Intel in the Springdale Design
guide update 1.21. VTT_GMCHP enable changed from
RUNPWROK to VCORE_PWRGD.
1.Loadline and offset fine tuning.
2.NW processor OCP trip point and DSV setting tuning.
3.Prescott processor OCP trip point tuning.
4.DRSV setting.
5.Loop compensation.
6.Switching frequency setting.
Change PR72 to 42.2K
Depop PR66 and add PR236 connect to VCORE_PWRGD.
1.Change PR111 from 1.91K to 1.87K;change PR204
from 16.2K to 9.31K;change PR110 from 1.2M to 1M.
2.Change PR100 from 274 Ohm to 47 Ohm; change
PR101 from 17.4K to 27.4K
3.Pop PR98 with 69.8K_0603_1% resistor. Connect
PR98.2 to PQ61.1 instead of to ground.
4.Change PR108 from 42.2K to 45.3K.
5.Change PC105 from 1000p to 4700p;change PR102
from 20K to 10K.
6.Change PR104 from 100K_5% to 90.9K_1%.
Solution Description Rev.
X00-B
X00-B
X00-B
X00-D3/05/2003 DELL
X00-E
X00-F
X00-H
X00-H
9 42 Battery CONN. 3/25/2003 DELL Dell's EMC engineer recommended that we add an L-C filer to
10 48 Charger 3/26/2003 DELL
A A
5
4
the for the
Subwoofer out /- next to battery connector
Dell's Power engineer recommended that we modified
Charger schematic to add some functions.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Reserved R,C ; Populate PR237,PR238(0_0603_5%) depop
PC226,PC227 [BOM update]
Add PU21, PC228, PR239 to reserved for ACAV.
Reserve PQ63.
DELL CONFIDENTIAL/PROPRIETARY
Title
Power_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
X00-L
X00-M
61 65Wednesday, January 28, 2004
A00-B
Page 62
5
4
POWER Version Change List ( P. I. R. List )
3
2
1
Request
Page#
Item Issue DescriptionDate
D D
11 44 For H/W request to change RUNPWROK_1P5V pull high source
12 48 6/16/2003 Compal Fix a leakage path from PBATT+ to +SDC_IN through PQ37 Change PL22 pin1 net from +SDC_IN to +PWR_SRC
13
41 PWR_DCIN
Title
+1.5VRUNP/ +VTT_GMCHP
Charger
Owner
Compal6/16/2003
for TTL source
6/16/2003 Compal +RTC_PWR (+5VRTC) circuit elimination Delete PU1 PC2
Change PR68 pin1 net from +5VSUS to +3VSUS
43 PWR_3.3V/5V Delete PQ13 PR45 PD14 PC51 PC49
48 Charger
14
43 PWR_3.3V/5V 6/16/2003 Compal Top side PD10 and PD11 interfere Change PD10 and PD11 from EC10QS04 to EP10QY03 X01-A
Change PU21 pin 5 and PQ36 pin 3 from +RTC_PWR to
+3.3VRTC
15 43 PWR_3.3V/5V 6/16/2003 Compal Fix the Skip mode enable for the +3SUS/+5VSUS regulator Depop PR32 X01-A
C C
16 46 CPU_CORE_Controller 6/19/2003 Dell
Nimitz_PT_ISSUE_LIST_REV00 item20: Rename the signal VCORE_VTT to VCORE_PHOT#. X01-B
Pop PR37 with 0 Ohm resistor
Rename the signal VCORE_VTT to VCORE_PHOT#.
17 43 PWR_3.3V/5V 6/19/2003 Dell Nimitz_PT_ISSUE_LIST_REV00 item21:
Change PR18 package from 0603 to 0805. X01-B
Damaged resistor issue.
18 46
19 44 +1.5VRUNP/ +VTT_GMCHP 6/19/2003
B B
CPU_CORE_Controller 6/19/2003 Dell
Compal
Nimitz_PT_ISSUE_LIST_REV00 item16:
Core Regulator Deep Sleep fix:- Currently the PLD is
forcing the Core regulator to be in deep sleep mode
Input capacitors' voltage rating is not enough. Change PC63 and PC64 from 4.7U_1206_16V to
Change the resistor population option: Populate PR92
and PR95. No pop PR93 and PR94.
4.7U_1206_25V.
Solution Description Rev.
X01-A
X01-A
X01-A
X01-B
X01-B
20 48 Charger 6/19/2003 Compal MAX1535 change pin definition. Change Pin32 from ACOK to ACOK#. X01-D
21 44 +1.5VRUNP/ +VTT_GMCHP 6/26/2003 Compal
22 46 CPU_CORE_Controller 6/26/2003 Compal
23 49
24 4445+1.5VRUNP/ +VTT_GMCHP
A A
Battery Discharger
6/26/2003 Compal
6/26/2003 Dell Reduce the risk of highside fet falsely turns on when
1.25V/2.5V
5
4
Add auto detect function to change VTT_GMCHP for
Prescott or Northwood CPU.
Add auto detect function to control the Presott DT/MT load
line.
Add VCORE_BOOTSELECT level shift circuit and
DT/MT detect circuit.
PWR_SRC is applied.This issue is related to Semtech
controllers only.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Change PR60 to 15.8K and add PQ64 and PR240. X01-D
Add PR214 and PQ65 parallel with PR204. X01-D
Add a circuit to generate CPU_PSC_HI and DT/MT#
signal to detect CPU type.
Add a 100k resistor between highside gate to source of
every regulator.
DELL CONFIDENTIAL/PROPRIETARY
Title
Power_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
X01-D
X01-D
62 65Wednesday, January 28, 2004
A00-B
Page 63
5
4
POWER Version Change List ( P. I. R. List )
3
2
1
Page#
Item Issue DescriptionDate
D D
25 49 Fix leakage current from PWR_SRC to PBATT+. Change PD25 and PD26 to B540C and PR202 to 33K
26 Charger 6/27/2003 Compal
27 49 Battery Discharger 7/01/2003 Compal
C C
28 4448+1.5VRUNP/ +VTT_GMCHP 7/01/2003 Compal Add auto detect function to change VTT_GMCHP for
29 41 PWR_DCIN 7/03/2003 Compal Change bridge battery to 8/V18HRT for Beijing and 6/V
30 49 Battery Discharger 7/03/2003
31 41
43
32 43 PWR_3.3V/5V 7/18/2003
B B
Title
Battery Discharger
PWR_DCIN
PWR_3.3V/5V
7/18/2003
Owner
Compal6/27/2003
Dell
Dell
Dell
according to Kapalua.
For MAXIN suqqest to change some value about
MAX1535.
Modify item 25. For Nimitz,it only has single battery.
Prescott or Northwood CPU.
15H for Nimitz.
Nimitz_PT_ISSUE_LIST_REV00 item24:
Intel update spec.
For Dell request to reserve RTC_PWR soure and
+RTC_PWR to +5VALW circuit.
Update item 17: PR18 power rating is not enough. Change PR18 size from 0805 to 1206. And reserve PC232
1. Add PQ69.
2. Change PR169 to 365K Ohm and PR174 to 49.9K.No
pop PC172.
3. Change PR178 and PR179 to 0 Ohm, PR176 to 20K
Ohm.
4. Change PR166 and PR167 to 0 Ohm. And depop
PC169 and PC170.
5. Change PR183 and PR186 to 0 Ohm. And depop
PC194 and PC195.
PR202 still change to original value(470K) and delete
PD27.
Change PR58 to 30K.
Change PR1 to 16.9K and PR3 to 8.06K to meet trickle
charger current spec (0.5mA for Beijing)
PR245 change to 12K.
Add PU1 and PC2 , PQ13 PR45 PD14 PC51 PC49 but
don't pop these materials.
to reduce inrush pulse.
33 48 Charger 7/18/2003 Dell For Dell request to delete PD20. Delete PD20. X02-A
Solution Description Rev.
X01-E
X01-E
X01-G
X01-G
X02-A
X02-A
X02-A
X02-A
Request
34 41~49 Power schematic 7/18/2003 Compal
35
48
49
Charger
Battery Discharger
7/21/2003 Dell For Dell request to reserve MAX1535 AVAC circuit. Reserve MAX1535 pin30(PDL) and pin31(PDS) to control
35 41 PWR_DCIN 7/22/2003 Compal Change Bridge battery trickle charger current to
36
46
CPU_CORE_Controller
CPU_CORE_Power-Stage47 8/29/2003 Dell
49
A A
Battery Discharger
37 44 +1.5VRUNP/ +VTT_GMCHP 8/29/2003 Compal +VTT_GMCH power on OVP protect Populate PC73 (PT memo, BOM need update)
5
4
For Compal purchaser request to change resistor and
capacitor's size from 0603 to 0402.
meet battery spec for Nimitz.
Change one loadline for Prescott and Northwood
and output capacitors to SP cap.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Change some resistor and capacitor's size to 0402. X02-A
PQ44 and PQ41.
X02-B
Add PR1 19.1K and 13.3K for Nimitz. X02-B
Del PR241, PQ65, PQ68, PR244,PR110.
Change PR111 to 2.21K, PR220 to 681K, PR204 to 11.5K,
PR102 to 20K, PR130/PR139/PR148/PR157 to 30.1K
X02-E
X02-E
DELL CONFIDENTIAL/PROPRIETARY
Title
Power_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
63 65Wednesday, January 28, 2004
1
A00-B
Page 64
5
4
POWER Version Change List ( P. I. R. List )
3
2
1
Page#
38
D D
41 Fix the PS_ID gate drive surge issue. Change PQ4 pin2 net to ACAV.Add PS_ID pull high
TitleItem Issue DescriptionDate
PWR_DCIN
Owner
Dell9/25/2003
resistor(PR254) to +3VALW and PD33 ,PR256 to GND.
Delete PR13 and PR10.
39 48 PWR_Charger 9/25/2003 Dell Fix ACAV glitch issue. Change PR168 from 1M to 330K Ohm.
40 49 Battery Discharger 9/25/2003 Dell Cost Reduction: Bootselect circuit Reserve VCORE_BOOTSELECT circuit and add a
41 47 CPU_CORE_Power-Stage 9/25/2003 Compal CPU_CORE input capacitors' rating is not rnough. Change PC114, PC146,PC153 and PC160 to 25V rating
42 44 +1.5VRUNP/ +VTT_GMCHP 9/25/2003 Dell Fix SC1485 noise issue.
43 41 PWR_DCIN 9/29/2003 Dell Change bridge battery to cell battery
C C
44 42 Battery Conn. 9/29/2003 Compal Change PR237 and PR238 power rating at net SUB_OUT1
45 44 +1.5VRUNP/ +VTT_GMCHP 9/29/2003 For Semtech recommendation to modify layout. Change
Compal Change PC63 and PC64 size to 1210.
46 45 1.25V/2.5V 10/06/2003 Dell For Semtech recommendation to modify layout for
47 46 Battery Conn. 10/08/2003 Compal For Compal factory PE suggestion to add a resistor for
B B
48 44 +1.5VRUNP/ +VTT_GMCHP 10/09/2003 Dell Reserve a resistor to debug easily. Reserve PR263 to connect AGND1 and AGND3. X03-F
and SUB_OUT2
input capacitors size.
Fine tune some value to improve the function.
SC1486.
EOS.
resistor(PR255) to connect VCORE_BOOTSELECT and
CPU_PDC_HI.
voltage.
Separate analog ground to AGND1 and AGND2. And add
a resistor (PR257) to connect power ground and AGND3.
Add PR258 and PR259 for safety concerm. And depop
PD1,PD2,PD4,PR1,PR3,PC1,PQ1,PQ2,PFS1
Change PR237 and PR238 size to 0805 X03-C
Pop PC72(100pF) and PC73(10pF) and change PR54 to
5.11K.
Add PR260 to connect PGND and AGND4.
Reserve PR261 to connect AGND2 and AGND4.
Add PR262 at Net PBAT_ALARM# X03-E
Solution Description Rev.
X03-B
X03-B
X03-B
X03-B
X03-B
X03-C
X03-C
X03-D
Request
49 49 Battery Discharge 10/09/2003 Dell For schematic issue item 7, add a resistor to pull down
VCORE_BOOTSELECT.And pop Intel VCORE_BOOTSELECT crcuit.
50 48 Charger 10/13/2003 Dell To solve MAX1535 high side MOSFET damage issue.
51 +1.5VRUNP/ +VTT_GMCHP44
45 1.25V/2.5V
10/13/2003 Dell Instead of PR263 and PR261 to reserve jumper from
AGND1 to AGND3 and from AGND2 to AGND4.
Depop PR109, and add PR264(depop). Pop Intel BOOTSELECT
circuit( PC229, PR242, PR243, PQ66, PR245, PQ67,
PR246, PC230, PC231) and depop PR255.
Change PQ37, PQ69 to SI4835DY and PC183 to 1000pF,
PR176 to 10K. And add PR265 at PU6.24 and PR175
pin1/ PC174 pin2 node.
X03-F
X03-G
Delete PR263 and PR261. Add AGNDJMP1 and AGNDJMP2. X03-G
52 49 Battery Discharger 10/13/2003 Compal Fix PBATT+ leakage voltage issue. Depop PD26. X03-G
A A
4445+1.5VRUNP/ +VTT_GMCHP
53
1.25V/2.5V
5
10/13/2003 Dell Correct Power PIR item 51, Add jumper from AGND to
4
GND.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Add AGNDJMP1 from AGND1 to GND. AGNDJMP2
from AGND3 to GND. AGNDJMP3 from AGND2 to GND
.AGNDJMP4 from AGND4 to GND.
DELL CONFIDENTIAL/PROPRIETARY
Title
Power_P.I.R History
Size Document Number Rev
2
Date: Sheet of
LA-1711
X03-H
64 65Wednesday, January 28, 2004
1
A00-B
Page 65
5
4
POWER Version Change List ( P. I. R. List )
3
2
1
Page#
54
D D
C C
41 Protect keyboard controller NB_PSID pin. Add PR267, PD33, PQ4, PD34, PR254, PR256, PR266,
55 48 Charger 10/14/2003 Dell Update PIR item 50. For MAXIM recommendation to add
56 46 CPU_CORE_Controller 10/14/2003 Dell For Dell request to add a capacitor at controller VCC pin.
57 41 PWR_DCIN 10/17/2003 Dell
58 44
45
47
TitleItem Issue DescriptionDate
PWR_DCIN
+1.5VRUNP & +VTT_GMCHP
1.25V/2.5V
CPU_CORE_Power-Stage
Owner
Dell10/14/2003
a 0603 capacitor between low side MOSFET gate to source.
For Dell request to reserve PS_ID protect function Reserve PR267, PR254,PR256 and PQ70. X03-I
10/17/2003 Compal EMI request to add EMI solution for system power broad
band issue.
PQ70, PR224 ,PR268
Reserve PC234 at PQ38 gate to source. X03-H
Add PC233 at PU9 pin32.
1.Change PQ14 to SI4392
2.Change PQ17 to SI4392
3.Change PQ20,PQ21,PQ24,PQ25,PQ28,PQ29,PQ32,
PQ33 to SI4392.
4.Change PQ22,PQ23,PQ26,PQ27,PQ30,PQ31,PQ34,
PQ35 to IRF7831
5.Change PQ22,PQ23,PQ26,PQ27,PQ30,PQ31,PQ34,
PQ35 to IRF7831
6.Change PC133,PC149,PC157,PC164 to 470P.
7.Change PR125,PR134,PR143,PR152 to 3 Ohm.
59 43 PWR_3.3V/5V 12/09/2003 Dell To solve PR18 pulse current issue Pop PC232 X04-A
60 48 Charger 12/09/2003 Compal
For EE request to change ACOK# pull high voltage
(because the pin is as EC input pin that should be 3V level)
61 48 Charger 12/09/2003 Dell For Dell request to add input current monitor circuit. 1.Add PU23 and PC239 to detect input current.
B B
Change PR172 pin 2 net to +3.3VRTC
2. Add PU22, PQ71, PR269, PR270, PR271, PR272,
PR273, PR274, PC235, PC236, PC237, PC238 to
throttling.
62 41 PWR_DCIN 12/09/2003 Dell For Dell request to add a resistor. Add PR276(0_0805_5%)
Solution Description Rev.
X03-H
X03-H
X03-I
X04-A
X04-A
X04-A
Request
63 46 CPU_CORE_Controller 12/09/2003 Dell For Dell request to fix the Load line Slope. Change PR111 to 2.43KOhm 1% resistor.
64 46 CPU_CORE_Controller 12/09/2003 Dell For Dell request to change the core regulator switching
frequency to 250KHz
change PR104 to 115K 1% part.
65 46 CPU_CORE_Controller 12/09/2003 Dell Update item 36. PQ60 is unused. Depop PQ60
X04-A
X04-A
X04-A
X04-A66 12/20/2003 CompalCharger48 Change PR270 pullup power source Change PR270 pullup from +3VALW to +3VRUN
A A
67 48 Charger 12/24/2003 Dell To solve can't charge at system on and pulg into over
5
4
dischargerd battery.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Add PD35 and PR277 to pull high PBATT+ to +5VSUS.
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet of
Power_P.I.R History
LA-1711
1
A00-A
64 64Wednesday, January 28, 2004
A00-B
Page 66
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