Compal LA-1711, Inspiron 9100 Schematic
5
D D
4
3
2
1
Prescott & Springdale Schematic with Capture CIS
and Function field
C C
uFCPGA Prescott
REV: A00-B
Cature library ball out check document
Prescott : Prescott processor Electrial,Mechanical and
Thermal Specification Rev0.5 [Check by HW:Henry,Steve]
B B
Springdale(GMCH): Springdale GMCH External Design
Specification (EDS) REV1.0 [Check by HW: Henry,Rita]
ICH5: N/A
2004-01-28
@ : Depop Component
1@ : Depop on Nimitz(Inspiron)
2@ : Depop on Alcatraz
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
Cover Sheet
LA-1711
1
1 65
A00-B
5
4
3
2
1
Block Diagram
D D
ADT7460 Thermal sensor
page 19
HA#(3..31)
VGA
Board
AGP CONN.
[CRT CONN. & TV-OUT]
C C
AGP4X/8X(1.5V)
page 18
Prescott
478 uFCPGA CPU
page 7,8,9
System Bus
533/800MHz
Springdale
GMCH
932 FC-BGA
page
10,11,12,13
HD#(0..63)
Memory
BUS(DDR)
2.5V
266/333/400MHz
2.5V
266/333/400MHz
Channel A SO-DIMM
BANK 0, 1, 2,3
Channel B SO-DIMM
BANK 0, 1, 2,3
page 15
page 16
Fan Control
page 14
Clock Generator
CK409
page 6
HUB Link
MINI PCI
page 32
PCI BUS
IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)
B B
LAN
BCM5705M
BCM4401
page 28
Transformer
page 29
RJ45
page 29
CardBus Controller
PCI4510
1394 Conn.
page31
3.3V 33MHz
page 30
Slot 0
page31
X BUS
LPC BUS
3.3V 33MHz
SST39VF080
A A
5
page 35
Touch Pad
page 35
4
1.5V
66Mhz
266MB/S
Macallen
LPC to X-BUS
& Super I/O
SATA
ATA100
3.3V 24.576MHz
3.3V ATA100
ATA100
HDD
page 21
ICH5
460 BGA
Page
20,21,22
CDROM
USB
FDD
Page
33,34
USB2.0
Int.KBD
page 35
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
USBPORT 4
page 23
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
page 26
page 27
USBPORT 6
AMP& Phone
Jack Interface
BT
BACK
DOG
MOD
BACKUSBPORT 5
BACK
2
AC-LINK
AC97
Codec
STAC9750
page 24
page 25
MDC
page 27
Subwoofer
page 50
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DC IN
BATT
IN
3.3V/5V
1.5V/+VTT_GMCH
1.25V/2.5V
VCORE
VCORE_CTRL
CHARGER
Block Diagram
LA-1711
1
2 65Wednesday, January 28, 2004
page 41
page 42
page 43
page 44
page 45
page 47
page 46
page 48
A00-B
5
PM TABLE
power
plane
State
D D
S0
S1
+3VALW
+5VALW
ON
ON
+3VSUS
+5VSUS
+2.5V_MEM
+3.3VRTC
+RTC_PWR
V_1P25V_DDR_VTT
ON
ON
+3VRUN
+5VRUN
+1.5VRUN
+VCC_CORE
+12V
+VCCVID
ON
ON
4
Bring up
SST-Build
PT-Build
ST-Build
QT-Build
Pilot-Build
3
MCH Rev. ICH5 Rev.
RG828SDGES FW82801EB
RG828SDGP
A2(QE45)
RG82865PE
A2(SL722)
RG82865PE
A2(SL722)
RG82865PE
A2(SL722)
A1(QE16ES)A1(QE18)
FW82801EB
A3(QE51ES)
FW82801EB
A3(SL73Z)
FW82801EB
A3(SL73Z)
FW82801EB
A3(SL73Z)
2
1
IDSEL
Reserved
BT
BACK
DOG
MOD
BACK
BACK
Reserved
ON
ON
ON
OFF
OFF
REQ#/GNT#
AD17
AD16
AD19
Note : "@" means all model depop
1
4
3
"1@" means Nimitz depoped only
"2@" means Alcatraz depoped only
Model
Function
Smart Card
LAN
Dog House
OFF
OFF
OFFOFF
PIRQ
D,C
C
D,B(NP)
A,B(NP)
Nimitz Alcatraz
No
10/100
(4401)
YES YES
No
1000
(5705M)
Configuration List
BOM Structure
Function
Bridge/Cell battery circuit options Table
No.
1
2
3
4
Bridge battery
Pop D3 and R158 ; Depop R623
Pop R232 ; Depop R624 Pop R624 ; Depop R623 33
Pop PD1,PD2,PD3,PD4,PQ1,PQ2,PFS1,
PR1,PR3,PR4 and PC1; Depop PR258,PR259
Cell battery
Pop R623 ; Depop D3 and R158
Pop D23Depop D23 39
Depop PD1,PD2,PD4,PQ1,PQ2,PFS1,PR1
PR3,PR4 and PC1; Pop PR258,PR259,PD3
Page
21
41
S3
S5 S4/AC
S5 S4/AC don't exist
TABLE
PCI
C C
PCI DEVICE
CARD BUS
LAN
MINI PCI
VGA
B B
TABLE
USB
USB PORT#
0
1
2
3
4
5
A A
6
7
DESTINATION
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Wednesday, January 28, 2004
Index and Config.
LA-1711
1
3 65
A00-B
5
4
3
2
1
RBAT
D D
ADAPTER
+RTCSRC
+RTC_PWR
+5VALW
+5VSUS
PWR_SRC
+3VALW+3.3VRTC
+3VSUS
BATTERY
SUSPWROK
DOCK _PWR_SRC
C C
+5VSUS
B B
+5VHDD
+5VMOD
+5VRUN
VDDA
+3VRUN +3VSUS+1.5VRUN
+3VSRC
+2.5VMEMP
+2.5V_MEM
+VCCP
V_1P25V_DDR_VTTV3P3LAN
+VCC_CORE
+12V
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Power Rail
LA-1711
1
4 65Wednesday, January 28, 2004
A00-B
5
4
3
2
1
ICH_SMBCLK
D D
ICH5
ICH_SMBDATA
+3VSUS
7002
+3VRUN
CK_SCLK
CK_SDATA
CLK GEN.
7002
V_3P3_LAN
DIMM1
7002
7002
7002
7002
7002
CLK_SMB
DIMM0
+3VALW
DAT_SMB
7002
C C
24C05
SIO
Macallen
SBAT_SMBCLK
SBAT_SMBDAT
B B
ADT7460
AD7414 PCA9561
+5VALW
DH PORT
EC SMBus Address
CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)
DDR Temp.(AD7414ART-0) : 90h/91h (P.15)
CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)
EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)
VID Select(PCA9561PW) : 9Ch/9Dh (P.38)
VGA
LAN_SMBCLK
LAN_SMBDATA
NIC
MPCI
PBAT_SMBCLK
1'nd
PBAT_SMBDAT
+5VALW
BATTERY
CHARGER
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
SMBUS TOPOLOGY
Wednesday, January 28, 2004
LA-1711
1
65
5
A00-B
+3VRUN
5
4
3
2
1
12
R529
D D
1K_0603_1%~D
12
R530
2K_0603_1%~D
12
R214
2.49K_0603_1%~D
SL0 SL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot
0 0 100 66 14.3 14.3 100/200
C C
0 MID REF REF REF REF REF
0 1 200
1 0 133 66 14.3
1 1 166
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
B B
ICH_SMBDATA
A A
ICH_SMBCLK
+3VRUN
12
R518
1K_0603_1%~D
CLKSEL0
CLKSEL1
12
R519
2K_0603_1%~D
12
R208
2.49K_0603_1%~D
66 14.3 100/200 48
R215 0_0402_5%~D@
12
R206 0_0402_5%~D
12
R508 0_0402_5%~D
12
R509 0_0402_5%~D@
12
14.3
14.3
66 14.3 100/2004848
ICH_SMBDATA
+3VRUN
12
R192
1K_0603_1%~D
H_STP_PCI#
+3VRUN
12
R218
1K_0603_1%~D@
ICH_SLP_S1#
+3VRUN
100K_0402_5%~D
D
1 3
2
2
1 3
D
D
1
14.3
12
R524
S
Q68
2N7002_SOT23~D
G
G
Q69
2N7002_SOT23~D
S
3G
S2
MCH_CLKSEL0
MCH_CLKSEL1
100/200
12
48
REF
R536
100K_0402_5%~D
CK_SDATA
CK_SCLKICH_SMBCLK
CPU_CLKSEL0
CPU_CLKSEL1
Bring Up: Populate R509 (Because CPU
is Northwood-MT, Frequency 533MHz)
CK_14M_ICH
CK_14M_SIO
CK_14M_CODEC
Close to X'tal pin
Place near CK409
CK_100M_ICH#
CK_100M_ICH
Check SPEC (250mA,300 ohm)
+3VRUN
CK_XTAL_IN and CK_XTAL_OUT equal length traces,
Please place R_J between Pins 4,5 of CK409 Pins
before X'tal
R538
12
33_0402_5%~D
R539
12
33_0402_5%~D
R611
12
24_0402_5%
C597
22P_0402_50V8J~D
12
X6
14.31818MHz_20P_1BX14318CC1A~D
12
C598
22P_0402_50V8J~D
R479
1 2
49.9_0402_1%~D
1 2
49.9_0402_1%~D
CK_48M_ICH
CK_48M_SCR
L45
BLM11A601S_0603~D
1 2
12
R478
CK_XTAL_OUT
Place crystal within
500 mils of CK409
ICH_SLP_S1#
CLK_STP_CPU#
CK_VTT_PG#
R485
1 2
33_0402_5%~D
R484
1 2
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
CLK_VDD_PLL
1
C166
10U_1206_6.3V7K~D
2
ICH_SLP_S1#
CLK_STP_CPU#
CK_VTT_PG#
R501
R500
1
C550
0.1U_0402_16V4Z~D
2
BLM21PG600SN1D_0805~D
CLKREF1
CLKREF0
CK_XTAL_IN
R548
2M_0603_5%~D @
1 2
R629 0_0402_5%~D
CLKSEL0
CLKSEL1
CK_SCLK
CK_SDATA
CK_SATA#
CK_SATA
CLK48M_OUT0
12
CLK48M_OUT1
12
R199
1 2
475_0603_1%~D
L17
1 2
10U_1206_6.3V7K~D
12
R_J
2N7002
5
4
CK_VDD_MAIN+3VRUN
2
1
C586
0.1U_0402_10V6K~D
1
2
24
16
3
VDD_PCI10VDD_PCI
VDD_REF
VDD_3V66
CK409
VSS_REF
VSS_PCI11VSS_PCI
VSS_3V66
6
17
25
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
2
4
5
51
56
21
49
50
35
28
30
37
38
31
32
52
55
54
3
C204
U39
REF_1
REF_0
XTAL_IN
XTAL_OUT
SEL0
SEL1
PWRDWN#
PCI_STP#
CPU_STP#
VTT_PWRGD#
SCLK
SDATA
SRCLKN_100MHZ
SRCLKP_100MHZ
USB_48MHZ
DOT_48MHZ
IREF
VDD_PLL
VSS_PLL
Place near each pin
W>40 mil
1
C587
0.1U_0402_10V6K~D
2
36
42
48
34
VDD_48
VSS_CPU
VDD_SRC
VDD_CPU
VDD_CPU
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
48/66MHZ_OUT/3V66_4
66MHZ_OUT3/3V66_3
66MHZ_OUT2/3V66_2
66MHZ_OUT1/3V66_1
66MHZ_OUT0/3V66_0
PCICLK_F2
PCICLK_F1
PCICLK_F0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
VSS_48
VSS_SRC
VSS_IREF
CY28409ZCT_TSSOP56~D
33
39
53
1
C553
2
45
47
46
44
43
41
40
29
27
26
23
22
9
8
7
20
19
18
15
14
13
12
1
C585
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
CK_CPU2
CK_CPU2#
CK_CPU1
CK_CPU1#
CK_CPU0H_STP_PCI#
CK_CPU0#
CLK66M_OUT3
CLK66M_OUT1
CLK66M_OUT0
PCICLK_F2
PCICLK6
PCICLK5
PCICLK2
PCICLK1
PCICLK0
1
C554
0.1U_0402_10V6K~D
2
1
C193
4.7U_0805_6.3V6K~D
2
1 2
1 2
1 2
1 2
1 2
1 2
R543
1 2
33_0402_5%~D
R547
1 2
33_0402_5%~D
R546
1 2
33_0402_5%~D
R540
1 2
33_0402_5%~D
R545
1 2
33_0402_5%~D
R542
1 2
33_0402_5%~D
R541
1 2
33_0402_5%~D
R544
1 2
33_0402_5%~D
1 2
R587 33_0402_5%~D
2
Trace wide=20 mils
1
C552
0.1U_0402_10V6K~D
2
R488
33_0402_5%~D
R472
1 2
49.9_0402_1%~D
R473
1 2
49.9_0402_1%~D
R489
33_0402_5%~D
R490
33_0402_5%~D
R474
1 2
49.9_0402_1%~D
R475
1 2
49.9_0402_1%~D
R491
33_0402_5%~D
R492
33_0402_5%~D
R476
1 2
49.9_0402_1%~D
R477
1 2
49.9_0402_1%~D
R493
33_0402_5%~D
1
C551
0.1U_0402_10V6K~D
2
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CK_HCLK
1
C588
0.1U_0402_10V6K~D
2
CK_BCLK
CK_BCLK#
CK_ITP
CK_ITP#
CK_HCLK
Place near CK409
CK_HCLK#
Title
Size Document Number Rev
Date: Sheet of
CK_HCLK#
CK_66M_AGP
CK_66M_MCH
CK_66M_ICH
CK_33M_ICHPCI
CK_33M_MINIPCI
CK_33M_CBPCI
CK_33M_LANPCI
CK_33M_SIOPCI
CK_33M_CPLD
DELL CONFIDENTIAL/PROPRIETARY
Clock Generator
LA-1711
1
6 65Wednesday, January 28, 2004
A00-B
5
4
+VCC_CORE
3
2
1
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C C
H_REQ#[0..4]
H_ADS#
R339
62_0402_5%@
R371
1 2
1 2
H_BR0#
H_BPRI#
H_BNR#
H_LOCK#
CK_BCLK
CK_BCLK#
H_HIT#
H_HITM#
H_DEFER#
+VCC_CORE
+VCC_CORE
B B
200_0402_5%
CK_BCLK
CK_BCLK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
AMP_3-1565030-1_Prescott~D
AF22
AF23
A10
A12
JCPUA
VCC_0
VCC_1
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
BCLK0
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
A14
A16
A18
VCC_2
VCC_3
VSS_0H1VSS_1H4VSS_2
H23
A20
VCC_4
H26
VCC_5
VSS_3
A11
AA10
AA12
VCC_6A8VCC_7
VSS_4
VSS_5
A13
A15
AA14
VCC_8
VSS_6
A17
AA16
VCC_9
VSS_7
A19
AA18
VCC_10
VCC_11
VSS_8
VSS_9
A21
AA8
VCC_12
VSS_10
A24
AB11
AB13
VCC_13
VCC_14
VSS_11
VSS_12A3VSS_13A9VSS_14
A26
AB15
VCC_15
AB17
AB19
VCC_16
AA1
AA11
AB7
VCC_17
VCC_18
VSS_15
VSS_16
AA13
AB9
VCC_19
VSS_17
AA15
AC10
VCC_20
VSS_18
AA17
AC12
VCC_21
VSS_19
AA19
AC14
VCC_22
VSS_20
AA23
AC16
AC18
VCC_23
VSS_21
AA4
AA26
AC8
VCC_24
VCC_25
VSS_22
VSS_23
AA7
AD11
VCC_26
VSS_24
AA9
AD13
VCC_27
VSS_25
AB10
AD15
VCC_28
VSS_26
AB12
AD17
VCC_29
VSS_27
AB14
AD19
AB16
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
Prescott
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
AB3
AB6
AB8
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AF15
VCC_42
VCC_43
VSS_40
VSS_41
AC2
AF17
VCC_44
VSS_42
AC22
AF19
VCC_45
VSS_43
AC25
AF2
VCC_46
VSS_44
AC5
AF21
VCC_47
VSS_45
AC7
AF5
VCC_48
VSS_46
AC9
AF7
VCC_49
VSS_47
AD10
AF9
VCC_50
VSS_48
AD12
B11
VCC_51
VSS_49
AD14
B13
VCC_52
VSS_50
AD16
B15
VCC_53
VSS_51
AD18
B17
B19
VCC_54
VSS_52
AD21
AD23
VCC_55
VCC_56B7VCC_57B9VCC_58
VSS_53
VSS_54
VSS_55
AD4
AD8
C10
C12
C14
VCC_59
VCC_61
BOOTSELECT
AD1
C16
VCC_62
VCC_81
F13
C18
VCC_63
VCC_82
F15
C20
VCC_64
VCC_83
F17
F19
D11
D13
VCC_65C8VCC_66
VCC_67
VCC_84
VCC_85
F9
F11
D15
VCC_68
VCC_79E8VCC_80
D17
VCC_69
VCC_78
E20
D19
VCC_70
VCC_77
E18
D9
VCC_71D7VCC_72
VCC_75
VCC_76
E14
E16
E10
VCC_73
VCC_74
E12
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
H_D#0
B21
D#0
H_D#1
B22
D#1
H_D#2
A23
D#2
H_D#3
A25
D#3
H_D#4
C21
D#4
H_D#5
D22
D#5
H_D#6
B24
D#6
H_D#7
C23
D#7
H_D#8
C24
D#8
H_D#9
B25
D#9
H_D#10
G22
H_D#11
H21
H_D#12
C26
H_D#13
D23
H_D#14
J21
H_D#15
D25
H_D#16
H22
H_D#17
E24
H_D#18
G23
H_D#19
F23
H_D#20
F24
H_D#21
E25
H_D#22
F26
H_D#23
D26
H_D#24
L21
H_D#25
G26
H_D#26
H24
H_D#27
M21
H_D#28
L22
H_D#29
J24
H_D#30
K23
H_D#31
H25
H_D#32
M23
H_D#33
N22
H_D#34
P21
H_D#35
M24
H_D#36
N23
H_D#37
M26
H_D#38
N26
H_D#39
N25
H_D#40
R21
H_D#41
P24
H_D#42
R25
H_D#43
R24
H_D#44
T26
H_D#45
T25
H_D#46
T22
H_D#47
T23
H_D#48
U26
H_D#49
U24
H_D#50
U23
H_D#51
V25
H_D#52
U21
H_D#53
V22
H_D#54
V24
H_D#55
W26
H_D#56
Y26
H_D#57
W25
H_D#58
Y23
H_D#59
Y24
H_D#60
Y21
H_D#61
AA25
H_D#62
AA22
H_D#63
AA24
H_D#[0..63]H_A#[3..31]
+VCC_CORE
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
AD20 VCCA VCCIOPLLConnect to CPU
AF23 Connect to CPU
VCCIOPLL VCCA VCCIOPLL
TESTHI12 TESTHI12AD25 DPSLP
Comment Comment
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Filter
Pull-up 200ohm
to +VCC_CORE
5
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
to +VCC_CORE
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
float
COMPAT#
Pull-up 62ohm
to +VCC_CORE
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VSSAE26 VSS Connect to GND OPTIMIZED/
Comment
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
float
float
float
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to PLD
through 0ohm
4
Northwood
Prescott
Northwood
MT
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
DepopPop
Pop Pop
Pop
Pop
Pop
Pop
Depop
Note: AD2,AD3 pop(bring up)
Depop
Depop
Pop
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCORE_BOOTSELECT
DELL CONFIDENTIAL/PROPRIETARY
Title
Prescott Processor in uFCPGA478
Size Document Number Rev
2
Date: Sheet of
LA-1711
1
A00-B
7 65Wednesday, January 28, 2004
5
+VCC_CORE
+VCC_CORE
CK_ITP_CPU
14
CK_ITP_CPU#
23
CK_ITP_JITP#
14
CK_ITP_JITP
23
Place near ICH
Place near CPU
1
+
2
ITP_TDO
+VCC_CORE
Pop: Prescott
Depop: Northwood
H_RS#[0..2]
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PWRGOOD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
CPU_CLKSEL0
CPU_CLKSEL1
H_THERMDA
H_THERMDC
H_THERMTRIP#
R338 62_0402_5%
1 2
R341 62_0402_5%
1 2
R337 62_0402_5%
1 2
R346 62_0402_5%
1 2
R343 62_0402_5%
1 2
R342 62_0402_5%
1 2
C368
33U_D2_8M_R35~D
H_RESET#
47_0402_5%~D
R370 27.4_0603_1%~D
0.1U_0402_10V6K~D
150_0402_5%~D
1 2
R364
1 2
1 2
1 2
R376
39.2_0603_1%~D
+VCCVID
R361
Close to the ITP
H_VCCA
H_VSSA
C386
VCCSENSE
VSSSENSE
R_D
R97
61.9_0603_1%
+VCC_CORE
1
2
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CK_ITP_JITP
CK_ITP_JITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
R131 62_0402_5%
R129 62_0402_5%
D D
R84 62_0402_5%@
C C
B B
+VCC_CORE
H_FERR#
1 2
H_THERMTRIP#
1 2
R111 130_0402_5%
H_PROCHOT#
1 2
R87 300_0402_5%~D
H_PWRGOOD
1 2
H_RESET#
1 2
10uH, DC current of 100mA parts
and close to cap
+VCC_CORE
L40 10U_LQH31MN100K01_100mA_10%_1206~D
1 2
1 2
L41 10U_LQH31MN100K01_100mA_10%_1206~D
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
CK_ITP
CK_ITP#
0_4P2R_0404_5%~D
CK_ITP#
CK_ITP#
CK_ITP
CK_ITP
R363
54.9_0603_1%~D
1 2
R358
54.9_0603_1%~D
1 2
0_4P2R_0404_5%~D @
ITP_TDO
H_RESET#
RN9
RN8
Close to the ITP
+VCC_CORE
R377
47_0402_5%~D@
R108 150_0402_5%~D
A A
1 2
R379 47_0402_5%~D @
680_0402_5%~D
1 2
Between the CPU and ITP
12
12
Close to the CPU
R381
ITP_TMS
ITP_TDI
ITP_TCK
ITP_TRST#
5
R333
H_FERR#
H_PWRGOOD
H_RESET#
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
1 2
CK_ITP_CPU
CK_ITP_CPU#
12
4
H_RS#0
H_RS#1
H_RS#2
F1
G5
F4
AB2
J6
C6
B6
B2
B5
AB23
Y4
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
AE23
A5
A4
AF3
0_0402_5%~D
AD22
AC26
AD26
L24
P1
12
R349
61.9_0603_1%
AMP_3-1565030-1_Prescott~D
29
JITP
28
VTT1
27
GND6
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
GND7
30
4
JCPUB
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
MOLEX_52435-2891_28P~D@
AE11
VSS_57
VSS_129F8VSS_130
+3VSUS
VID_PWRGD
AE13
VSS_58
G21
AE15
AE17
VSS_59
VSS_131
G24
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_132G3VSS_133G6VSS_134J2VSS_135
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
J22
J25
K21
K24
R152
1 2
10K_0402_5%~D
3
Level shift
+CPU_GMCH_GTLREF trace
wide 12mils(min),Space
15mils
AF18
AF20
AF6
AF8
B10
B12
B14
B16
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
L23
L26
N21
M22
M25
+3VSUS
5
U6A
P
1
G
SN74LVC2G07DBVR_SOT23-6~D
2
+3VSUS
5
U6B
P
O4I
G
SN74LVC2G07DBVR_SOT23-6~D
2
+CPU_GMCH_GTLREF
B18
B20
B23
VSS_80
VSS_81
VSS_82
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
N24
1 2
O6I
3
B26
C11
C13
C15
C17
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
Prescott
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
P22
P25
R23
R26
C131
0.1U_0402_16V4Z~D
H_VID_PWRGD
R155 8.2K_0402_5%~D
1 2
3
2
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
F10
F12
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
VSS_121
VID0
VID1
VID2
VID3
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
T21
T24
V23
V26
U22
U25
+3VSUS
C121
1 2
1U_0603_6.3V6M~D
+VCC_CORE
R_A
R_B
VCORE_ENLL
12
R357
200_0603_1%~D
12
R356
169_0603_1%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Y5
Y22
Y25
W21
W24
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
GTL Reference Voltage
Layout note :
2
C369
0.1U_0402_16V4Z~D
1
VID4
VSS_181
VID5
AE5
AE4
AE3
AE2
AE1
AD3
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
12
R340
0_0603_5%~D
1
2
F14
F16
F18
F22
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VIDPWRGD
AD2
C372
220P_0402_50V7K
AF26
F25
F5
VSS_127
VSS_128
SKTOCC#
GTLREF0
GTLREF1
GTLREF2
GTLREF3
OPTIMIZED/COMPAT#
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
PROCHOT#
VCCVID
AF4
+VCCVID
H_VID_PWRGD
2
DP#0
DP#1
DP#2
DP#3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
MCERR#
SLP#
R71
1 2
0_0402_5%~D
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
R_E
R336
681_0603_1%
1 2
2
2
1
1
@
T1
PAD@
R70 0_0402_5%~D@
1 2
H_TESTHI0
H_TESTHI1
H_TESTHI2_7
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
RE
Pop: Prescott
Depop: Northwood
+VCCVID
VID5
VID4
VID3
VID2
VID1
VID0
B_VID5
OPEN
@
1
+VCC_CORE
R76
200_0402_5%@
R78 0_0402_5%~D@
1 2
+VCC_CORE
RH
Pop: Prescott
Depop: Northwood MT
CPLD Enable
Pop R380
Closely Pin AE25
C660
12
1000P_0402_50V7K~D@
+VCC_CORE
R37 1K_0402_5%~D
R35 1K_0402_5%~D
B_VID2
OPEN
2
1
@
LA-1711
1
CPLD Enable
Pop R76, R78
H_DPSLP#
CPUPREF#
H_PROCHOT#
1 2
1 2
45
36
27
18
RN7 1K_8P4R_1206_5%~D
B_VID0
B_VID1
OPEN
OPEN
2
2
2
1
1
1
@
8 65Wednesday, January 28, 2004
12
DPSLP#
+CPU_GTLREF
Pop: Northwood
R_G
R77 62_0402_5%
R344 62_0402_5%
R82 62_0402_5%
R354 62_0402_5%
R350 62_0402_5%
R347 62_0402_5%
R382 62_0402_5%
R79 62_0402_5%
ITP_DBRESET#
H_CPUSLP#
R83 62_0402_5%@
1 2
B_VID4
OPEN
2
2
1
1
@
Title
Size Document Number Rev
Date: Sheet of
Depop: Prescott
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R_H
R380 0_0402_5%~D@
1 2
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
VID5
VID4
VID3
VID2
VID1
VID0
B_VID3
OPEN
2
2
2
2
1
1
1
1
@
DELL CONFIDENTIAL/PROPRIETARY
Prescott Processor in uFCPGA478
+3VRUN
A00-B
5
4
3
2
1
+VCC_CORE
1
C31
22U_1206_6.3VAM~D
2
D D
+VCC_CORE
1
C46
22U_1206_6.3VAM~D
@
2
+VCC_CORE
1
C381
22U_1206_6.3VAM~D
2
C C
+VCC_CORE
1
C76
22U_1206_6.3VAM~D
@
2
1
C27
22U_1206_6.3VAM~D
@
2
1
C56
22U_1206_6.3VAM~D
@
2
1
C411
22U_1206_6.3VAM~D
2
1
C71
22U_1206_6.3VAM~D
2
1
C28
22U_1206_6.3VAM~D
2
1
C55
22U_1206_6.3VAM~D
@
2
1
C72
22U_1206_6.3VAM~D
2
Place 11 North of Socket(Stuff 6)
1
C29
22U_1206_6.3VAM~D
2
1
C32
22U_1206_6.3VAM~D @
2
Place 12 Inside Socket(Stuff all)
1
C45
22U_1206_6.3VAM~D
@
2
1
C394
22U_1206_6.3VAM~D
2
Place 9 South of Socket(Unstuff all)
1
C75
22U_1206_6.3VAM~D
@
2
1
C69
22U_1206_6.3VAM~D
@
2
1
C30
22U_1206_6.3VAM~D
2
1
C403
22U_1206_6.3VAM~D
2
1
C70
22U_1206_6.3VAM~D
@
2
1
C77
22U_1206_6.3VAM~D
2
1
C404
22U_1206_6.3VAM~D
2
1
C73
22U_1206_6.3VAM~D
@
2
1
C331
22U_1206_6.3VAM~D
2
22uF depop reference
Springdale Chipset Platform Design Guide Rev1.11(12474)
1
C412
22U_1206_6.3VAM~D
2
1
2
C74
22U_1206_6.3VAM~D
@
1
C395
22U_1206_6.3VAM~D
2
1
C382
22U_1206_6.3VAM~D
2
Note:For PT-phase
22uF depop reference
Springdale Chipset Platform Design Guide Rev1.2(12837)
Inside the socket cavity 12 pcs (all stuffed)
North side 12pcs (4 sites stuffed)
Delete south side
B B
+VCC_CORE
1
+
C303
@
330U_D_2VM~D
2
+VCC_CORE
1
+
C299
330U_D_2VM~D
@
2
+VCC_CORE
A A
1
+
C68
330U_D_2VM~D
2
1
+
2
1
+
2
1
+
C423
330U_D_2VM~D
@
2
5
470uF _ERS10m ohm* 15, ESR=0.5m ohm
330uF _ERS7m ohm* 8, ESR=0.875m ohm
1
C302
330U_D_2VM~D
C294
330U_D_2VM~D
+
2
1
+
2
1
+
C422
330U_D_2VM~D
2
C304
330U_D_2VM~D
C298
330U_D_2VM~D
1
+
C301
330U_D_2VM~D @
2
1
+
C296
330U_D_2VM~D
2
Per Dell power team test, used Panasonic 330U_2V ESR
7m ohm * 8 (Implement on PT phase X02)
1
+
C300
330U_D_2VM~D
2
1
+
C295
330U_D_2VM~D
@
2
4
1
+
C305
330U_D_2VM~D
@
2
1
+
C297
330U_D_2VM~D
@
2
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page239
Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
CPU Decoupling
LA-1711
1
9 65Wednesday, January 28, 2004
A00-B
5
4
3
2
1
H_A#[3..31]
D D
H_REQ#[0..4]
H_ADSTB#0
C C
H_RS#[0..2] MCH_CLKSEL0
B B
+VTT_GMCH
12
R331
301_0402_1%~D
12
R332
102_0402_1%~D
A A
12
R335
20_0603_1%~D
H_ADSTB#1
CK_HCLK
CK_HCLK#
H_DSTBP#0
H_DSTBN#0
H_DINV#0
H_DSTBP#1
H_DSTBN#1
H_DINV#1
H_DSTBP#2
H_DSTBN#2
H_DINV#2
H_DSTBP#3
H_DSTBN#3
H_DINV#3
H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
+GMCH_GTLREF
Follow Intel design guide R1.11(12474) page80
Trace width 12mils,Space
10mils
HD_SWING
HDRCOMP
1
C365
0.01U_0402_16V7K~D
2
Trace width 10mils,Space
7mils
H_RESET#
PWRGD_3V
HDRCOMP
HD_SWING
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
U3A
D26
HA3#
D30
HA4#
L23
HA5#
E29
HA6#
B32
HA7#
K23
HA8#
C30
HA9#
C31
HA10#
J25
HA11#
B31
HA12#
E30
HA13#
B33
HA14#
J24
HA15#
F25
HA16#
D34
HA17#
C32
HA18#
F28
HA19#
C34
HA20#
J27
HA21#
G27
HA22#
F29
HA23#
E28
HA24#
H27
HA25#
K24
HA26#
E32
HA27#
F31
HA28#
G30
HA29#
J26
HA30#
G26
HA31#
B29
HREQ0#
J23
HREQ1#
L22
HREQ2#
C29
HREQ3#
J21
HREQ4#
B30
HADSTB0#
D28
HADSTB1#
B7
HCLKP
C7
B19
C19
C17
L19
K19
L17
G9
F9
L14
D12
E12
C15
F27
D24
G24
L21
E23
K21
E25
B24
B28
B26
E27
G22
C27
B27
E8
AE14
E24
C25
F23
RG828SDGES_FCBGA932_SPRINGDALE~D
HCLKN
HDSTBP0#
HDSTBN0#
DINV0#
HDSTBP1#
HDSTBN1#
DINV1#
HDSTBP2#
HDSTBN2#
DINV2#
HDSTBP3#
HDSTBN3#
DINV3#
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS0#
RS1#
RS2#
CPURST#
PWROK#
HDRCOMP
HDSWING
HDVREF
FSB
PROCHOT#
+CPU_GMCH_GTLREF
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
BSEL0
BSEL1
B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8
L20
L13
L12
R329
0_0603_5%~D
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R608
1 2
0_0402_5%~D
+VTT_GMCH
12
12
R323
200_0603_1%~D
H_D#[0..63]
PROCHOT_GATE PROCHOT_GATE
H_PROCHOT#
MCH_CLKSEL1
GTL Reference Voltage
Layout note :
1. +GMCH_GTLREF Trace wide
12mils(min),Space 15mils.
2. Place decoupling cap 220PF near GMCH.
+GMCH_GTLREF
MMBT3904_SOT23~D@
1
C366
220P_0402_50V7K
2
Create
2
Q76
31
+3VRUN
12
Q24
MMBT3904_SOT23~D
3 1
OVP_AC_ADAPT#
R90
1.24K_0402_1%~D
2
H_PROCHOT#
R605
1 2
0_0402_5%~D@
H_PROCHOT_SIO#
R91 10K_0402_5%~D
1 2
C670
12
100P_0402_50V8J~D
H_PROCHOT#
VCORE_PHOT#
+VCC_CORE
U3F
AR32
VSS
AR29
VSS
AR27
VSS
AR25
VSS
AR23
VSS
AR20
VSS
AR16
VSS
AR13
VSS
AR11
VSS
AR9
VSS
AN32
VSS
AN30
VSS
AN28
VSS
AN26
VSS
AN24
VSS
AN22
VSS
AN20
VSS
AN18
VSS
AN16
VSS
AN14
VSS
AN12
VSS
AN10
VSS
AM35
VSS
AM29
VSS
AM27
VSS
AM25
VSS
AM23
VSS
AM21
VSS
AM19
VSS
AM17
VSS
AM15
VSS
AM13
VSS
AM11
VSS
AM9
VSS
AL32
VSS
AL1
VSS
AK28
VSS
AK26
VSS
AK24
VSS
AK22
VSS
AK20
VSS
AK18
VSS
AK16
VSS
AK14
VSS
AK12
VSS
AK10
VSS
AK8
VSS
AK3
VSS
AJ35
VSS
AJ32
VSS
AJ9
VSS
AJ4
VSS
AJ1
VSS
AH33
VSS
AH30
VSS
AH24
VSS
AH22
VSS
AH20
VSS
AH18
VSS
AH16
VSS
AH14
VSS
AH12
VSS
AH10
VSS
AH6
VSS
AH3
VSS
AG35
VSS
AG32
VSS
AG28
VSS
AG26
VSS
AG24
VSS
AG22
VSS
AG20
VSS
AG18
VSS
AG16
VSS
AG14
VSS
AG8
VSS
AG4
VSS
AF33
VSS
AF30
VSS
AF25
VSS
AF24
VSS
AF22
VSS
AF20
VSS
AF18
VSS
AF16
VSS
AF14
VSS
AF11
VSS
AF9
VSS
AF6
VSS
AF3
VSS
AE35
VSS
AE32
VSS
AE26
VSS
AE25
VSS
AE13
VSS
AE12
VSS
RG828SDGES_FCBGA932_SPRINGDALE~D
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE11
AE10
AE4
AE1
AD33
AD30
AD28
AD10
AD9
AD8
AD6
AD3
AC35
AC32
AC4
AC1
AB33
AB30
AB28
AB27
AB26
AB10
AB9
AB8
AB6
AB3
AA32
AA4
AA1
Y35
Y33
Y30
Y28
Y27
Y26
Y10
Y9
Y8
Y6
Y3
W32
W18
W17
W4
V33
V30
V28
V27
V26
V19
V17
V10
V9
V8
V6
V3
U32
U19
U18
U4
T35
T33
T30
T28
T27
T26
T10
T9
T8
T6
T3
T1
R32
R4
R1
P33
P30
P28
P27
P26
P9
P8
P6
P3
N35
N32
N4
N1
M33
M30
M28
M27
M26
M6
M3
L35
U3G
L31
VSS
L26
VSS
L25
VSS
L24
VSS
K33
VSS
K29
VSS
K27
VSS
K25
VSS
K22
VSS
K20
VSS
K18
VSS
K16
VSS
K14
VSS
K12
VSS
K11
VSS
J35
VSS
J32
VSS
J28
VSS
J22
VSS
J20
VSS
J18
VSS
J16
VSS
J14
VSS
J12
VSS
J10
VSS
H33
VSS
H30
VSS
H26
VSS
H24
VSS
H22
VSS
H20
VSS
H18
VSS
H16
VSS
H14
VSS
H12
VSS
H9
VSS
H8
VSS
H5
VSS
H2
VSS
G35
VSS
G31
VSS
G28
VSS
F26
VSS
F24
VSS
F22
VSS
F20
VSS
F18
VSS
RG828SDGES_FCBGA932_SPRINGDALE~D
GND
F16
VSS
F14
VSS
F12
VSS
F10
VSS
F8
VSS
F5
VSS
F3
VSS
F1
VSS
E3
VSS
E1
VSS
D35
VSS
D33
VSS
D31
VSS
D29
VSS
D27
VSS
D25
VSS
D23
VSS
D21
VSS
D19
VSS
D17
VSS
D15
VSS
D13
VSS
D11
VSS
D9
VSS
D1
VSS
C28
VSS
C26
VSS
C24
VSS
C22
VSS
C20
VSS
C18
VSS
C16
VSS
C14
VSS
C12
VSS
C10
VSS
C8
VSS
C4
VSS
A32
VSS
A29
VSS
A27
VSS
A25
VSS
A23
VSS
A20
VSS
A16
VSS
A13
VSS
A11
VSS
A9
VSS
A7
VSS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
Springdale-Host/GND
LA-1711
1
10 65Wednesday, January 28, 2004
A00-B
5
4
3
2
1
DDRA_SDQ[0..63]
DDRA_SMA[0..12]
D D
C C
SM_VREF_A
SM_VREF_A trace width of 12mils and space
12mils(min)
2
C48
2.2U_0805_16VFZ~D
1
2
C47
0.1U_0402_16V4Z~D
1
Close to GMCH
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
B B
2
C64
2.2U_0805_16VFZ~D
1
A A
Follow Intel design guide
R1.11(12474) page124,125
12
R372
42.2_0603_1%~D
SMXRCOMP
12
R367
42.2_0603_1%~D
2
C65
2.2U_0805_16VFZ~D
1
5
DDRA_SMA[0..12]
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS0
DDRA_SBS1
DDRA_SCS#0
DDRA_SCS#1
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK2
DDRA_CLK2#
1
C637
0.01U_0402_16V7K~D
2
1
C406
1U_0603_6.3V6M~D
2
U3B
AJ34
SMAA_A0
AL33
SMAA_A1
AK29
SMAA_A2
AN31
SMAA_A3
AL30
SMAA_A4
AL26
SMAA_A5
AL28
SMAA_A6
AN25
SMAA_A7
AP26
SMAA_A8
AP24
SMAA_A9
AJ33
SMAA_A10
AN23
SMAA_A11
AN21
SMAA_A12
AL34
SMAB_A1
AM34
SMAB_A2
AP32
SMAB_A3
AP31
SMAB_A4
AM26
SMAB_A5
AB34
SWE_A#
Y34
SCAS_A#
AC33
SRAS_A#
AE33
SBA_A0
AH34
SBA_A1
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AL20
AN19
AM20
AP20
AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32
E34
AK9
AN9
AL9
Trace width of 12mils and space
10mils(min)
1
2
DDR Channel A
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCMDCLK_A0
SCMDCLK_A0#
SCMDCLK_A1
SCMDCLK_A1#
SCMDCLK_A2
SCMDCLK_A2#
SCMDCLK_A3
SCMDCLK_A3#
SCMDCLK_A4
SCMDCLK_A4#
SCMDCLK_A5
SCMDCLK_A5#
SMVREF_A
SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL
RG828SDGES_FCBGA932_SPRINGDALE~D
C400
0.01U_0402_16V7K~D
SDQS_A0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQS_A1
SDM_A1
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQS_A2
SDM_A2
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQS_A3
SDM_A3
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQS_A4
SDM_A4
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQS_A5
SDM_A5
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQS_A6
SDM_A6
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQS_A7
SDM_A7
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13
AP15
AP16
AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18
AP23
AM24
AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27
AM30
AP30
AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34
AF34
AF31
AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34
V34
W33
AC34
AB31
V32
V31
AD31
AB32
U34
U33
M32
M34
T34
T32
K34
K32
T31
P34
L34
L33
H31
H32
J33
H34
E33
F33
K31
J34
G34
F34
2
C63
2.2U_0805_16VFZ~D
1
1
C407
1U_0603_6.3V6M~D
2
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
SMXRCOMP
SMXRCOMPVOH
SMXRCOMPVOL
+2.5V_MEM
12
12
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SCS#0
DDRA_SCS#1
DDRA_CKE0
DDRA_CKE1
R374
10K_0603_1%~D
SMXRCOMPVOH
R369
30.9K_0603_1%~D
*
Close to GMCH <1" Close to GMCH <1"
Note: Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K
4
DDRA_SDQ[0..63]
DDRA_SDQS0
DDRA_SDM0
DDRA_SDQS1
DDRA_SDM1
DDRA_SDQS2
DDRA_SDM2
DDRA_SDQS3
DDRA_SDM3
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQS6
DDRA_SDM6
DDRA_SDQS7
DDRA_SDM7
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R373
30.9K_0603_1%~D
*
SMXRCOMPVOL
12
R368
10K_0603_1%~D
1
2
C401
0.01U_0402_16V7K~D
DDRB_SMA[0..12]
DDRB_SWE#
DDRB_SCAS#
DDRB_SRAS#
DDRB_SBS0
DDRB_SBS1
DDRB_SCS#0
DDRB_SCS#1
DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CLK2
DDRB_CLK2#
SM_VREF_B
SM_VREF_B trace width of
12mils and space
12mils(min)
2
C50
0.1U_0402_16V4Z~D
1
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SCS#0
DDRB_SCS#1
DDRB_CKE0
DDRB_CKE1
SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL
+2.5V_MEM
12
12
R104
300_0603_1%~D
R100
300_0603_1%~D
DDRB_SMA[0..12]
2
C62
2.2U_0805_16VFZ~D
1
2
C52
2.2U_0805_16VFZ~D
1
Close to GMCH
+2.5V_MEM
2
12
R110
42.2_0603_1%~D
SMYRCOMP
12
R109
42.2_0603_1%~D
2
C53
2.2U_0805_16VFZ~D
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C66
2.2U_0805_16VFZ~D
1
Trace width of 12mils
and space 10mils(min)
1
C636
0.01U_0402_16V7K~D
2
1
C57
1U_0603_6.3V6M~D
2
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R102
10K_0603_1%~D
SMYRCOMPVOH
12
R101
30.9K_0603_1%~D
*
2
U3C
AG31
SMAA_B0
AJ31
SMAA_B1
AD27
SMAA_B2
AE24
SMAA_B3
AK27
SMAA_B4
AG25
SMAA_B5
AL25
SMAA_B6
AF21
SMAA_B7
AL23
SMAA_B8
AJ22
SMAA_B9
AF29
SMAA_B10
AL21
SMAA_B11
AJ20
SMAA_B12
AE27
SMAB_B1
AD26
SMAB_B2
AL29
SMAB_B3
AL27
SMAB_B4
AE23
SMAB_B5
W27
SWE_B#
W31
SCAS_B#
W26
SRAS_B#
Y25
SBA_B0
AA25
SBA_B1
U26
SCS_B0#
T29
SCS_B1#
V25
SCS_B2#
W25
AK19
AF19
AG19
AE18
AG29
AG30
AF17
AG17
AJ30
AH29
AK15
AL15
AA33
N27
N26
N31
N30
AP9
R34
R33
DDR Channel B
SCS_B3#
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMVREF_B
SMYRCOMP
SMYRCOMPVOH
SMYRCOMPVOL
RG828SDGES_FCBGA932_SPRINGDALE~D
1
C54
0.01U_0402_16V7K~D
2
SDQS_B0
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7
SDQS_B1
SDM_B1
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQS_B2
SDM_B2
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQS_B3
SDM_B3
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQS_B5
SDM_B5
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQS_B6
SDM_B6
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQS_B7
SDM_B7
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
DDRB_SDQ[0..63]
AF15
AG11
AJ10
AE15
AL11
AE16
AL8
AF12
AK11
AG12
AG13
AG15
AE17
AL13
AK17
AL17
AK13
AJ14
AJ16
AJ18
AG21
AE21
AE19
AE20
AG23
AK23
AL19
AK21
AJ24
AE22
AH27
AJ28
AK25
AH26
AG27
AF27
AJ26
AJ27
AD25
AF28
AD29
AC31
AE30
AC27
AC30
Y29
AE31
AB29
AA26
AA27
U30
U31
AA30
W30
U27
T25
AA31
V29
U25
R27
L27
M29
P29
R30
K28
L30
R31
R26
P25
L32
J30
J31
K30
H29
F32
G33
N25
M25
J29
G32
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
2
C59
2.2U_0805_16VFZ~D
1
1
C61
1U_0603_6.3V6M~D
2
DDRB_SDQ[0..63]
DDRB_SDQS0
DDRB_SDM0
DDRB_SDQS1
DDRB_SDM1
DDRB_SDQS2
DDRB_SDM2
DDRB_SDQS3
DDRB_SDM3
DDRB_SDQS4
DDRB_SDM4
DDRB_SDQS5
DDRB_SDM5
DDRB_SDQS6
DDRB_SDM6
DDRB_SDQS7
DDRB_SDM7
+2.5V_MEM
Trace width of 12mils and space
10mils(min)
12
R106
30.9K_0603_1%~D
*
SMYRCOMPVOL
12
R105
10K_0603_1%~D
1
2
Close to GMCH <1" Close to GMCH <1"
DELL CONFIDENTIAL/PROPRIETARY
Title
Springdale-DDR Interface
Size Document Number Rev
Date: Sheet of
LA-1711
1
C58
0.01U_0402_16V7K~D
11 65Wednesday, January 28, 2004
A00-B
5
+1.5VRUN
12
R64
43.2_0603_1%~D
GRCOMP
+1.5VRUN
D D
12
R328
52.3_0603_1%~D
HI_RCOMP_MCH
+1.5VRUN
12
R330
226_0603_1%~D
HI_SWING_MCH
12
R68
C C
B B
147_0603_1%~D
12
R69
113_0603_1%
2
C43
0.1U_0402_16V4Z~D
1
2
C360
0.1U_0402_16V4Z~D
1
+1.5VRUN
HI_VREF_MCH
Note:
HI_SWING_MCH, trace width of
12mils and space 10mils
2
C355
0.1U_0402_16V4Z~D
1
2
C41
0.1U_0402_16V4Z~D
1
+1.5VRUN
12
R74
226_0603_1%~D
CI_SWING_GMCH
12
R75
147_0603_1%~D
CI_VREF_GMCH
12
R334
113_0603_1%
AGP8X_DET_GC
1
C364
0.01U_0402_16V7K~D
2
Close to GMCH ball <250mils
1
C42
0.01U_0402_16V7K~D
2
Close to GMCH ball <250mils
Note:
HI_VREF_MCH trace width of
10mils and space 7mils
Note:
CI_SWING_MCH, CI_VREF_MCH
trace width of 12mils and
space 20mils
0.8V
1
C44
0.01U_0402_16V7K~D
2
0.35V
1
C363
0.01U_0402_16V7K~D
2
+1.5VRUN
12
R45
8.2K_0402_5%~D
+12V
2
4
12
R48
8.2K_0402_5%~D
Q10
MMBT3904_SOT23~D
3 1
HUB_HL[0..10]
+1.5VRUN
PCI_PCIRST#
G_C/BE#[0..3]
G_PIPE#_DBI_HI
G_ST[0..2]
HUB_HLSTRF
HUB_HLSTRS
CK_66M_MCH
G_FRAME#
CK_66M_MCH
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_RBF#
G_WBF#
G_DBI_LO
Trace 10mils, space 7mils
52.3_0603_1%~D
R81
1 2
R40
ICH_SYNC#
12
1
@
2
3
GC_DET_REF
13
D
2
G
Q13
2N7002_SOT23~D
S
R55
1 2
39.2_0603_1%~D
Close to VGA Conn.
G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3
CK_66M_MCH G_AD3
G_PAR
GRCOMP
AGP_SWING
VREFGC
G_ST0
G_ST1
G_ST2
HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10
HI_RCOMP_MCH
HI_SWING_MCH
HI_VREF_MCH
CI_SWING_GMCH
CI_VREF_GMCH
0_0402_5%~D
12
1
C680
10P_0402_50V8J~D
@
2
R320
22_0402_5%~D @
C324
10P_0402_50V8J~D
U3D
Y7
GCBE0
W5
GCBE1
AA3
GCBE2
U2
GCBE3
U6
GFRAME
H4
GCLKIN
AB4
GDEVSEL
V11
GIRDY
AD11
AC10
AG10
AN35
AP34
AB5
W11
AB2
AC2
AC3
AD2
R10
AF5
AG3
AK2
AG5
AK5
AL3
AL2
AL4
AJ2
AH2
AJ3
AH5
AH4
AD4
AE3
AE2
AK7
AH7
AF7
AD7
AF8
AG7
AE9
AH9
AG6
AJ6
AJ5
AG2
AF2
AF4
AP8
AJ8
AK4
AG9
AR1
AGP
GTRDY
GSTOP
GPAR/ADD_DETECT
N6
GREQ
M7
GGNT
GRCOMP/DVOBCGCOMP
GVSWING
GVREF
GRBF
R9
GWBF
M4
DBI_HI
M5
DBI_LO
N3
GST0
N5
GST1
N2
GST2
HI0
HI1
HI2
HUB
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HISTRF
HISTRS
HI_RCOMP
HI_SWING
HI_VREF
CI0
CI1
CI2
CI3
CI4
CSA
CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
G4
DREFCLK
EXTTS#
ICH_SYNC#
RSTIN#
RESERVED_1
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5
RG828SDGES_FCBGA932_SPRINGDALE~D
GADSTBF0
GADSTBS0#
GADSTBF1
GADSTBS1#
GSBSTBF
GSBSTBS#
DDCA_DATA
DDCA_CLK
VGA
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#
RED#
GREEN
GREEN#
BLUE
BLUE#
HSYNC
VSYNC
REFSET
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
RED
+1.5VRUN
12
R59
60.4_0603_1%
AGP_SWING
12
R58
39.2_0603_1%~D
1 2
R57 100_0603_1%~D
C385 0.1U_0402_16V4Z~D
AC6
AC5
G_AD0
AE6
G_AD1
AC11
G_AD2
AD5
AE5
G_AD4
AA10
G_AD5
AC9
G_AD6
AB11
G_AD7
AB7
G_AD8
AA9
G_AD9
AA6
G_AD10
AA5
G_AD11
W10
G_AD12
AA11
G_AD13
W6
G_AD14
W9
G_AD15
V7
V4
V5
G_AD16
AA2
G_AD17
Y4
G_AD18
Y2
G_AD19
W2
G_AD20
Y5
G_AD21
V2
G_AD22
W3
G_AD23
U3
G_AD24
T2
G_AD25
T4
G_AD26
T5
G_AD27
R2
G_AD28
P2
G_AD29
P5
G_AD30
P4
G_AD31
M2
U11
T11
G_SBA#0
R6
G_SBA#1
P7
G_SBA#2
R3
G_SBA#3
R5
G_SBA#4
U9
G_SBA#5
U10
G_SBA#6
U5
G_SBA#7
T7
H3
F2
F4
E4
H6
G5
H7
G6
G3
E2
R38
D2
A3
A33
A35
AF13
AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25
Note:
AGP_SWING_MCH, trace width of
12mils and space 10mils
2
C38
0.1U_0402_16V4Z~D
1
VREFCG
12
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
R42
12
R41
12
R39
12
R43
12
R44
12
0_0402_5%~D
12
2
Close GMCH ball less than 250mils
1
C362
0.01U_0402_16V7K~D
2
R66
0_0402_5%~D
12
VREFCG
2
C361
0.01U_0402_16V7K~D
G_AD[0..31]
G_AD[0..31]
G_SBA#[0..7]
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
1
Close GMCH ball
less than
250mils
1
VREFGC
Follow Springdale Chipset Platform Design guide Rev1.11(12474)
Note:
Springdale Customer Schematic R1.2 page18
AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design
guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.
Analog RGB/CRT guidelines for Springdale-P
R61
A A
10K_0402_5%~D@
1 2
G_PAR
1: External AGP
0: Internal Graphics
5
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Springdale-AGP/HUB/VGA/CSA
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
12 65Wednesday, January 28, 2004
A00-B
5
D D
0.82uH, DC current of 30mA
+1.5VRUN
C C
B B
parts and close to cap
0.82U_LQM21NNR82K10_150mA_10%_0805~D
VCCA_FSB1 VCCA_FSB
1 2
12
R301
Trace 14mils
0_0603_5%~D
1uH(0.54uH-D-IN), DC current of
1000mA parts and close to cap
+1.5VRUN
1U_LQH32CN1R0M11_1A_20%_1210~D
VCCA_DDR
12
R351
0_0603_5%~D
L34
1 2
Trace 14mils
L42
1
+
C276
100U_D_10VM~D
2
2
1
Trace 50mils, min:35mils on ball field
VCCA1P5_DDR_SM
1
+
C398
100U_D_10VM~D
2
C280
0.1U_0402_16V4Z~D
Close to GMCH
2
C402
0.1U_0402_16V4Z~D
1
Close to GMCH
4
Note:
Placed less than 100 mils from ball
1
C348
0.47U_0603_16V7K~D
2
+VTT_GMCH
2
C414
0.1U_0402_10V6K~D
1
C405 0.1U_0402_10V6K~D
1 2
1 2
C419
0.22U_0603_10V7M~D
C49 0.47U_0603_16V7K~D
1 2
R314
R315
C410
C367 0.1U_0402_10V6K~D
C371 0.1U_0402_10V6K~D
1 2
0.22U_0603_10V7M~D
VCC_AGP_DCAP2
1 2
1 2
0_0402_5%~D
12
0_0402_5%~D
12
1 2
C421 0.1U_0402_10V6K~D
+3VRUN
Trace 14mils
Note:
Placed less than 100 mils from ball
VTT_DCAP1
VTT_DCAP2
1
C356
0.47U_0603_16V7K~D
2
+2.5V_MEM
VCC_DDR_DCAP5
VCC_DDR_DCAP4
VCC_DDR_DCAP1
VTT_DCAP3
VCCA_FSB
VCCA_DPLL
VCCA_DAC
VCC_DDR_DCAP2
VCCA1P5_DDR_SM
3
U3E
A15
VTT
A21
VTT
A4
VTT
A5
VTT
A6
VTT
B5
VTT
B6
VTT
C5
VTT
C6
VTT
D5
VTT
D6
VTT
D7
VTT
E6
VTT
E7
VTT
F7
VTT
AA35
VCC_DDR
AL6
VCC_DDR
AL7
VCC_DDR
AM1
VCC_DDR
AM2
VCC_DDR
AM3
VCC_DDR
AM5
VCC_DDR
AM6
VCC_DDR
AM7
VCC_DDR
AM8
VCC_DDR
AN2
VCC_DDR
AN4
VCC_DDR
AN5
VCC_DDR
AN6
VCC_DDR
AN7
VCC_DDR
AN8
VCC_DDR
AP3
VCC_DDR
AP4
VCC_DDR
AP5
VCC_DDR
AP6
VCC_DDR
AP7
VCC_DDR
AR15
VCC_DDR
AR21
VCC_DDR
AR31
VCC_DDR
AR4
VCC_DDR
AR5
VCC_DDR
AR7
VCC_DDR
E35
VCC_DDR
R35
VCC_DDR
G1
VCC_DAC
G2
VCC_DAC
AG1
VCCA_AGP
+1.5VRUN
Y11
VCCA_AGP
A31
VCCA_FSB
B4
VCCA_FSB
B3
VCCA_DPLL
C2
VCCA_DAC
AL35
VCCA_DDR
AB25
VCCA_DDR
AC25
VCCA_DDR
AC26
VCCA_DDR
RG828SDGES_FCBGA932_SPRINGDALE~D
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page84
POWER
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSSA_DAC
J6
VCC
J7
VCC
J8
VCC
J9
VCC
K6
VCC
K7
VCC
K8
VCC
K9
VCC
L6
VCC
L7
VCC
L9
VCC
L10
VCC
L11
VCC
M8
VCC
M9
VCC
M10
VCC
M11
VCC
N9
VCC
N10
VCC
N11
VCC
P10
VCC
P11
VCC
R11
VCC
T16
VCC
T17
VCC
T18
VCC
T19
VCC
T20
VCC
U16
VCC
U17
VCC
U20
VCC
V16
VCC
V18
VCC
V20
VCC
W16
VCC
W19
VCC
W20
VCC
Y16
VCC
Y17
VCC
Y18
VCC
Y19
VCC
Y20
VCC
J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5
Y1
D3
+1.5VRUN
VCC_AGP_DCAP1
2
1
C391
0.1U_0402_10V6K~D@
2
1
C378
0.1U_0402_10V6K~D@
2
+1.5VRUN
1
C358
0.1U_0402_10V6K~D
2
Place near ball
Y11,routing trace
from cap to ball
+1.5VRUN
1
2
+1.5VRUN
1
2
+1.5VRUN
1
2
1
C390
0.1U_0402_10V6K~D@
2
1
C373
0.1U_0402_10V6K~D@
2
C387
0.1U_0402_10V6K~D@
C319
0.1U_0402_10V6K~D@
C380
0.1U_0402_10V6K~D@
1
2
1
2
1
2
+VTT_GMCH
1
C337
0.1U_0402_10V6K~D
2
Place near GMCH Place near GMCH
+2.5V_MEM
1
C374
0.1U_0402_10V6K~D@
2
+2.5V_MEM
1
C389
0.1U_0402_10V6K~D@
2
C354
1 2
0.1U_0402_10V6K~D
C379
0.1U_0402_10V6K~D@
C359
0.1U_0402_10V6K~D@
C347
0.1U_0402_10V6K~D@
+2.5V_MEM
1
2
1
C377
0.1U_0402_10V6K~D@
2
1
C393
0.1U_0402_10V6K~D@
2
C396
0.1U_0402_10V6K~D
1
C338
0.1U_0402_10V6K~D@
2
1
C346
0.1U_0402_10V6K~D@
2
1
C345
0.1U_0402_10V6K~D@
2
1
1
C376
0.1U_0402_10V6K~D@
2
1
C375
0.1U_0402_10V6K~D@
2
1
C353
0.1U_0402_10V6K~D@
2
1
C351
0.1U_0402_10V6K~D@
2
+VTT_GMCH
Bulk Decopuling
1
+
C308
470U_D4_2.5V_R10M~D
2
A A
+2.5V_MEM
1
2
C384
22U_1206_10V4Z~D
5
2
C327
0.1U_0402_16V4Z~D
1
2
C370
4.7U_0805_6.3V6K~D
1
2
C288
4.7U_0805_6.3V6K~D
1
+1.5VRUN
2
C322
10U_0805_10V4M~D
1
2
C287
4.7U_0805_6.3V6K~D
1
1
C289
1U_0603_6.3V6M~D
2
+1.5VRUN
1
+
C329
470U_D4_2.5V_R10M~D
2
2
C284
4.7U_0805_6.3V6K~D
1
Place at the output of the 1.5V VR
4
1
C290
0.47U_0603_16V7K~D
2
Place between the VR and GMCH
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Springdale-Decoupling
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
13 65Wednesday, January 28, 2004
A00-B
5
4
3
2
1
C
E 3
FAN1 Control and Tachometer
D D
R286
100K_0402_5%~D
FAN1_PWM
C C
1 2
1U_0805_10V6K~D
FAN1VREF
C254
1
2
FAN1_VFB
12
U30B
LM358M_SO8~D
5
6
2200P_0603_50V7K~D @
R150
100K_0402_5%~D
+12V
8
P
IN+
IN-
G
4
C108
1 2
R151
300K_0402_5%
1 2
1
C117
0.1U_0402_16V4Z~D
2
SI3457DV-T1_TSOP6~D
FAN1_ON
7
O
D2
RB751V_SOD323~D
+12V
2
+3VRUN
12
R133
10K_0402_5%~D
Q30
PMBT2222_SOT23~D
3 1
SI3457DV P channel
Vds max: +/- 30V
Vgs max: +/- 20V
Id max: 4.3A @ Vgs = -10V
65mohm @ Vgs = -10V
FAN1_TACH
+5VRUN
Q31
S
3
G
D
6
2451
FAN1_VOUT
1
+
C110
47U_D_16VM_R70~D
2
2 1
1
C102
0.47U_0603_16V7K~D
2
R136
10K_0402_5%~D
1 2
1 2
R137
1K_0402_5%~D
FAN1_TACH_FB
FAN1TACH_ON
FAN1
FAN1_VOUT
FAN1_TACH_FB
B
2222 SYMBOL(SOT23-NEW)
1
2
FAN2 Control and Tachometer
2
FAN2
JFAN2
4
4
3
3
2
2
1
1
MOLEX_53398-0490~D
+3VRUN+12V
12
Q61
PMBT2222_SOT23~D
3 1
R287
10K_0402_5%~D
FAN2_TACH
+12V
U30A
3
2
2200P_0603_50V7K~D@
IN+
IN-
C625
1 2
1 2
8
P
O
G
4
R580
300K_0402_5%
RB751V_SOD323~D
1
R291
B B
FAN2_PWM
100K_0402_5%~D
1 2
1U_0805_10V6K~D
FAN2VREF
C255
LM358M_SO8~D
1
2
FAN2_VFB
12
R288
100K_0402_5%~D
Q72
SI3457DV-T1_TSOP6~D
FAN2_ON
3
D17
2 1
G
S
D
6
2451
FAN2_VOUT
1
+
C622
47U_D_16VM_R70~D
2
+5VRUN
R289
10K_0402_5%~D
1 2
1
C256
0.47U_0603_16V7K~D
2
R290
1K_0402_5%~D
1 2
FAN2_TACH_FB
FAN2TACH_ON
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
FAN CONTROL
LA-1711
1
14 65Wednesday, January 28, 2004
A00-B
5
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
D D
C C
B B
+2.5V_MEM
1
C111
22U_1206_10V4Z~D
2
A A
+2.5V_MEM
1
C103
0.1U_0402_10V6K~D
2
System Memory Decoupling caps
1
C107
0.1U_0402_10V6K~D
2
1
C134
0.1U_0402_10V6K~D
2
1
C113
0.1U_0402_10V6K~D
2
1
C124
0.1U_0402_10V6K~D
2
5
1
C106
0.1U_0402_10V6K~D
2
1
C132
0.1U_0402_10V6K~D
2
1
C109
0.1U_0402_10V6K~D
2
1
C129
0.1U_0402_10V6K~D
2
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
1
C114
0.1U_0402_10V6K~D
2
1
C123
0.1U_0402_10V6K~D
2
4
1
C112
0.1U_0402_10V6K~D
2
1
C128
0.1U_0402_10V6K~D
2
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE1
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
ICH_SMBDATA
ICH_SMBCLK
1
C101
2
1
C126
0.1U_0402_10V6K~D
2
+2.5V_MEM
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDQS0
DDRA_SDQ7
DDRA_SDQ6
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ27
DDRA_CKE1
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQS4
DDRA_SDQ33
DDRA_SDQ35
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5
DDRA_SDQ43
DDRA_SDQ42
DDRA_SDQ52
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ51
DDRA_SDQ54
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ59
+3VSUS
0.1U_0402_10V6K~D
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
C79
0.1U_0402_10V6K~D
2
1
C92
0.1U_0402_10V6K~D
2
3
+2.5V_MEM
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
AMP_1565917-1~D
DIMM0
STANDARD
3
2
VREF
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
DQ12
22
VDD
24
DQ13
26
DM1
28
VSS
30
DQ14
32
DQ15
34
VDD
36
VDD
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VDD
48
DM2
50
DQ22
52
VSS
54
DQ23
56
DQ28
58
VDD
60
DQ29
62
DM3
64
VSS
66
DQ30
68
DQ31
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
DU/RESET#
88
VSS
90
VSS
92
VDD
94
VDD
96
CKE0
98
DU/BA2
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
RAS#
120
CAS#
122
S1#
124
DU
126
VSS
128
DQ36
130
DQ37
132
VDD
134
DM4
136
DQ38
138
VSS
140
DQ39
142
DQ44
144
VDD
146
DQ45
148
DM5
150
VSS
152
DQ46
154
DQ47
156
VDD
158
CK1#
160
CK1
162
VSS
164
DQ52
166
DQ53
168
VDD
170
DM6
172
DQ54
174
VSS
176
DQ55
178
DQ60
180
VDD
182
DQ61
184
DM7
186
VSS
188
DQ62
190
DQ63
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
1
C104
0.1U_0402_10V6K~D
2
1
C133
0.1U_0402_10V6K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDRA_SDQ1
DDRA_SDQ4
DDRA_SDM0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ9
DDRA_SDQ12
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ18
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ31
DDRA_CKE0
DDRA_SMA11
DDRA_SMA8
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1
DDRA_SDQ37
DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ47
DDRA_SDQ46
DDRA_SDQ48
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ55
DDRA_SDQ50
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ63
DDRA_SDQ58
1
C81
0.1U_0402_10V6K~D
2
1
C105
0.1U_0402_10V6K~D
2
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
2
DDRA_VREF trace width of
12mils and space 12mils(min)
DDRA_VREF
2
C507
0.1U_0402_16V4Z~D
1
DDRA_CKE0
DDRA_SCS#1
DDRA_CLK2#
DDRA_CLK2
2
1
+2.5V_MEM
12
R442
150_0603_1%~D
12
R440
150_0603_1%~D
Follow
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21
Decoupling Reference Document:
Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DDR-SODIMM SLOT1
LA-1711
1
A00-B
15 65Wednesday, January 28, 2004
5
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
D D
C C
B B
System Memory Decoupling caps
+2.5V_MEM
1
C116
0.1U_0402_10V6K~D
2
+2.5V_MEM
1
2
C94
0.1U_0402_10V6K~D
A A
1
C100
0.1U_0402_10V6K~D
2
1
C86
0.1U_0402_10V6K~D
2
5
1
C82
0.1U_0402_10V6K~D
2
1
C97
0.1U_0402_10V6K~D
2
1
C84
0.1U_0402_10V6K~D
2
1
C80
0.1U_0402_10V6K~D
2
1
C98
0.1U_0402_10V6K~D
2
1
C90
0.1U_0402_10V6K~D
2
4
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
4
1
C95
0.1U_0402_10V6K~D
2
1
C78
0.1U_0402_10V6K~D
2
DDRB_CLK1
DDRB_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE1
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
ICH_SMBDATA
ICH_SMBCLK
1
C87
0.1U_0402_10V6K~D
2
1
C91
0.1U_0402_10V6K~D
2
DDRB_SDQ5
DDRB_SDQ4
DDRB_SDQS0
DDRB_SDQ6
DDRB_SDQ1
DDRB_SDQ9
DDRB_SDQ13
DDRB_SDQS1
DDRB_SDQ14
DDRB_SDQ10
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQS2
DDRB_SDQ19
DDRB_SDQ22
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQS3
DDRB_SDQ30
DDRB_SDQ26
DDRB_CKE1
DDRB_SMA12
DDRB_SMA9
DDRB_SMA7
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQS4
DDRB_SDQ33
DDRB_SDQ37
DDRB_SDQ46
DDRB_SDQ44
DDRB_SDQS5
DDRB_SDQ41
DDRB_SDQ45
DDRB_SDQ52
DDRB_SDQ49
DDRB_SDQS6
DDRB_SDQ48
DDRB_SDQ51
DDRB_SDQ60
DDRB_SDQ59
DDRB_SDQS7
DDRB_SDQ57
DDRB_SDQ56
+3VSUS
1
C125
0.1U_0402_10V6K~D
2
1
C83
0.1U_0402_10V6K~D
2
3
1
C85
0.1U_0402_10V6K~D
2
1
C127
0.1U_0402_10V6K~D
2
3
2
JDIM2
1
VREF
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
AMP_1565918-1~D
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DIMM1
REVERSE
1
C93
0.1U_0402_10V6K~D
2
1
C99
0.1U_0402_10V6K~D
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
+2.5V_MEM+2.5V_MEM
1
C96
0.1U_0402_10V6K~D
2
1
C122
0.1U_0402_10V6K~D
2
DDRB_SDQ7
DDRB_SDQ0
DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ12
DDRB_SDQ11
DDRB_SDM1
DDRB_SDQ8
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDM2
DDRB_SDQ23
DDRB_SDQ18
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDM3
DDRB_SDQ27
DDRB_SDQ31
DDRB_CKE0
DDRB_SMA11
DDRB_SMA8
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1
DDRB_SDQ32
DDRB_SDQ36
DDRB_SDM4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ43
DDRB_SDQ40
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDM6
DDRB_SDQ55
DDRB_SDQ50
DDRB_SDQ61
DDRB_SDQ63
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ62
+3VSUS
1
2
1
2
DDRB_VREF trace width of
12mils and space 12mils(min)
2
C458
0.1U_0402_16V4Z~D
1
DDRB_CKE0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1
DDRB_CLK2#
DDRB_CLK2
C130
0.1U_0402_10V6K~D
C115
0.1U_0402_10V6K~D
DDRB_VREF
2
+2.5V_MEM
12
R418
150_0603_1%~D
12
R415
150_0603_1%~D
Follow
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 0.1uF*24
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
DDR-SODIMM SLOT2
LA-1711
1
A00-B
1
16 65Wednesday, January 28, 2004
5
Channel A(DIMM0) Termination
resistors & Decoupling caps
RN97 56_4P2R_0404_5%~D
DDRA_SDQ1
1 4
DDRA_SDQ4
2 3
RN85 56_4P2R_0404_5%~D
DDRA_SDQ5
1 4
DDRA_SDQ0
D D
C C
2 3
RN84 56_4P2R_0404_5%~D
DDRA_SDQ7
1 4
DDRA_SDQS0
2 3
RN96 56_4P2R_0404_5%~D
DDRA_SDM0
1 4
DDRA_SDQ2
2 3
RN95 56_4P2R_0404_5%~D
DDRA_SDQ3
1 4
DDRA_SDQ9
2 3
RN83 56_4P2R_0404_5%~D
DDRA_SDQ8
1 4
DDRA_SDQ6
2 3
RN94 56_4P2R_0404_5%~D
DDRA_SDQ12
1 4
DDRA_SDM1
2 3
RN82 56_4P2R_0404_5%~D
DDRA_SDQS1
1 4
DDRA_SDQ13
2 3
RN81 56_4P2R_0404_5%~D
DDRA_SDQ15
1 4
DDRA_SDQ10
2 3
RN93 56_4P2R_0404_5%~D
DDRA_SDQ14
1 4
2 3
RN80 56_4P2R_0404_5%~D
DDRA_SDQ17
1 4
DDRA_SDQ20
2 3
RN109 56_4P2R_0404_5%~D
DDRA_SDQ16
1 4
DDRA_SDQ21
2 3
RN79 56_4P2R_0404_5%~D
DDRA_SDQ22
1 4
DDRA_SDQS2
2 3
RN108 56_4P2R_0404_5%~D
DDRA_SDM2
1 4
DDRA_SDQ18
2 3
RN78 56_4P2R_0404_5%~D
DDRA_SDQ28
1 4
DDRA_SDQ19
2 3
RN107 56_4P2R_0404_5%~D
DDRA_SDQ23
1 4
DDRA_SDQ24
2 3
RN77 56_4P2R_0404_5%~D
DDRA_SDQS3
14
DDRA_SDQ29
23
RN106 56_4P2R_0404_5%~D
DDRA_SDQ25
14
DDRA_SDM3
23
RN64 56_4P2R_0404_5%~D
DDRA_SDQ51 DDRA_SDQ49
14
DDRA_SDQS6
23
RN63 56_4P2R_0404_5%~D
DDRA_SDQ60
14
DDRA_SDQ54
23
RN87 56_4P2R_0404_5%~D
DDRA_SDQ50
14
DDRA_SDQ56
23
RN86 56_4P2R_0404_5%~D
DDRA_SDQ57
14
DDRA_SDM7
23
RN62 56_4P2R_0404_5%~D
DDRA_SDQS7
14
DDRA_SDQ61
23
RN92 56_4P2R_0404_5%~D
DDRA_SDQ37
14
DDRA_SDQ34
23
RN91 56_4P2R_0404_5%~D
DDRA_SDM4
14
DDRA_SDQ38
23
RN70 56_4P2R_0404_5%~D
DDRA_SDQ32
14
DDRA_SDQ36
23
RN69 56_4P2R_0404_5%~D
DDRA_SDQ33
14
DDRA_SDQS4
23
RN99 56_4P2R_0404_5%~D
DDRA_SDQ39
14
DDRA_SDQ40
23
RN68 56_4P2R_0404_5%~D
DDRA_SDQ44
14
DDRA_SDQ35
23
RN98 56_4P2R_0404_5%~D
DDRA_SDQ41
14
DDRA_SDM5
23
RN67 56_4P2R_0404_5%~D
DDRA_SDQS5
14
DDRA_SDQ45
23
RN90 56_4P2R_0404_5%~D
DDRA_SDQ47
14
DDRA_SDQ46
23
V_1P25V_DDR_VTTV_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTTV_1P25V_DDR_VTT
RN66 56_4P2R_0404_5%~D
RN89 56_4P2R_0404_5%~D
RN65 56_4P2R_0404_5%~D
RN88 56_4P2R_0404_5%~D
RN76 56_4P2R_0404_5%~D
RN105 56_4P2R_0404_5%~D
RN100 56_4P2R_0404_5%~D
RN61 56_4P2R_0404_5%~D
DDRA_CKE0
DDRA_CKE1
DDRA_SCS#0
DDRA_SCS#1
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
4
R433 56_0402_5%~D
DDRA_SCS#0
DDRA_SDQ42 DDRB_SDQS3
14
DDRA_SDQ43
23
DDRA_SDQ48
14
DDRA_SDQ53
23
14
DDRA_SDQ52
23
DDRA_SDM6
14
DDRA_SDQ55
23
DDRA_SDQ27
14
DDRA_SDQ30
23
DDRA_SDQ26
14
DDRA_SDQ31
23
DDRA_SDQ63
14
DDRA_SDQ58 DDRB_SDM7
23
DDRA_SDQ59
14
DDRA_SDQ62
23
DDRA_CKE0
DDRA_CKE1
DDRA_SCS#0
DDRA_SCS#1
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
1 2
RN103 56_4P2R_0404_5%~D
DDRA_SMA8
14
DDRA_SMA6
23
RN104 56_4P2R_0404_5%~D
DDRA_CKE0
14
DDRA_SMA11
23
RN73 56_4P2R_0404_5%~D
DDRA_SMA3
14
DDRA_SMA5
23
RN72 56_4P2R_0404_5%~D
DDRA_SMA10
14
DDRA_SMA1
23
RN110 56_4P2R_0404_5%~D
DDRA_SMA4
14
DDRA_SMA2
23
RN74 56_4P2R_0404_5%~D
DDRA_SMA7
14
DDRA_SMA9
23
RN102 56_4P2R_0404_5%~D
DDRA_SMA0
14
DDRA_SBS1
23
RN101 56_4P2R_0404_5%~D
14
DDRA_SCAS#
23
R443 56_0402_5%~D
DDRA_SCS#1
1 2
DDRA_SMA12
DDRA_CKE1
DDRA_SWE#
DDRA_SBS0
DDRA_SWE#
DDRA_SBS0
DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
V_1P25V_DDR_VTT
RN75
1 4
2 3
56_4P2R_0404_5%~D
RN71
1 4
2 3
56_4P2R_0404_5%~D
3
Channel B(DIMM1) Termination
resistors & Decoupling caps
RN38 56_4P2R_0404_5%~D
DDRB_SDQ7
1 4
DDRB_SDQ0
2 3
RN32 56_4P2R_0404_5%~D
DDRB_SDQ4
1 4
DDRB_SDQ5
2 3
RN31 56_4P2R_0404_5%~D
DDRB_SDQ6
1 4
DDRB_SDQS0
2 3
RN39 56_4P2R_0404_5%~D
DDRB_SDM0
1 4
DDRB_SDQ2
2 3
RN37 56_4P2R_0404_5%~D
DDRB_SDQ3
1 4
DDRB_SDQ12
2 3
RN30 56_4P2R_0404_5%~D
DDRB_SDQ9
1 4
DDRB_SDQ1
2 3
RN29 56_4P2R_0404_5%~D
DDRB_SDQS1
1 4
DDRB_SDQ13
2 3
RN36 56_4P2R_0404_5%~D
DDRB_SDQ11
1 4
DDRB_SDM1
2 3
RN28 56_4P2R_0404_5%~D
DDRB_SDQ10
1 4
DDRB_SDQ14
2 3
RN47 56_4P2R_0404_5%~D
DDRB_SDQ8
1 4
DDRB_SDQ15DDRA_SDQ11
2 3
RN27 56_4P2R_0404_5%~D
DDRB_SDQ21
1 4
DDRB_SDQ20
2 3
RN45 56_4P2R_0404_5%~D
DDRB_SDM2
1 4
DDRB_SDQ23
2 3
RN33 56_4P2R_0404_5%~D
DDRB_SDQ19
1 4
DDRB_SDQS2
2 3
RN44 56_4P2R_0404_5%~D
DDRB_SDQ18
1 4
DDRB_SDQ28
2 3
RN26 56_4P2R_0404_5%~D
DDRB_SDQ24
1 4
DDRB_SDQ22
2 3
RN46 56_4P2R_0404_5%~D
DDRB_SDQ16
1 4
DDRB_SDQ17
2 3
2
RN25 56_4P2R_0404_5%~D
14
DDRB_SDQ25
23
RN34 56_4P2R_0404_5%~D
RN58 56_4P2R_0404_5%~D
RN15 56_4P2R_0404_5%~D
RN52 56_4P2R_0404_5%~D
RN14 56_4P2R_0404_5%~D
RN51 56_4P2R_0404_5%~D
RN12 56_4P2R_0404_5%~D
RN41 56_4P2R_0404_5%~D
RN11 56_4P2R_0404_5%~D
RN40 56_4P2R_0404_5%~D
RN10 56_4P2R_0404_5%~D
RN49 56_4P2R_0404_5%~D
RN19 56_4P2R_0404_5%~D
RN48 56_4P2R_0404_5%~D
RN18 56_4P2R_0404_5%~D
DDRB_SDQ26
14
DDRB_SDQ30
23
DDRB_SDM6
14
DDRB_SDQ55
23
DDRB_SDQ60
14
DDRB_SDQ51
23
DDRB_SDQ50
14
DDRB_SDQ61
23
DDRB_SDQS7
14
DDRB_SDQ59
23
DDRB_SDQ63
14
23
DDRB_SDQ39
14
23
DDRB_SDQ32DDRA_SRAS#
14
DDRB_SDQ36
23
DDRB_SDQ33
14
DDRB_SDQS4
23
DDRB_SDM4
14
DDRB_SDQ34
23
DDRB_SDQ46
14
DDRB_SDQ37
23
DDRB_SDQ35
14
DDRB_SDQ43
23
DDRB_SDQS5
14
DDRB_SDQ44
23
DDRB_SDQ40
14
DDRB_SDM5
23
DDRB_SDQ45
14
DDRB_SDQ41
23
1
RN60 56_4P2R_0404_5%~D
DDRB_SDQ42
14
DDRB_SDQ47
23
RN17 56_4P2R_0404_5%~D
DDRB_SDQ49
14
DDRB_SDQ52
23
RN59 56_4P2R_0404_5%~D
DDRB_SDQ53
14
DDRB_SDQ54
23
RN16 56_4P2R_0404_5%~D
DDRB_SDQ48
14
DDRB_SDQS6
23
RN42 56_4P2R_0404_5%~D
DDRB_SDQ27
14
DDRB_SDQ31
23
RN43 56_4P2R_0404_5%~D
DDRB_SDQ29
14
DDRB_SDM3
23
RN13 56_4P2R_0404_5%~D
DDRB_SDQ56
14
DDRB_SDQ57
23
RN50 56_4P2R_0404_5%~D
DDRB_SDQ58
14
DDRB_SDQ62DDRB_SDQ38
23
RN55 56_4P2R_0404_5%~D
DDRB_SMA4
14
DDRB_SMA2
23
RN54 56_4P2R_0404_5%~D
DDRB_SMA0
14
DDRB_SBS1
23
RN53 56_4P2R_0404_5%~D
DDRB_SRAS#
14
DDRB_SCAS#
23
DDRB_SDQ[0..63] DDRB_CKE0
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
DDRB_SRAS#
DDRB_SCAS#
DDRB_SDQ[0..63]
DDRB_SDQS[0..7]
DDRB_SMA[0..12]
DDRB_SDM[0..7]
R405 56_0402_5%~D
1 2
RN24 56_4P2R_0404_5%~D
RN23 56_4P2R_0404_5%~D
RN56 56_4P2R_0404_5%~D
RN21 56_4P2R_0404_5%~D
R431 56_0402_5%~D
1 2
RN22 56_4P2R_0404_5%~D
DDRB_CKE0
DDRB_SMA11
DDRB_SWE#
DDRB_SBS0
DDRB_SCS#0
DDRB_SMA12
14
DDRB_CKE1
23
DDRB_SMA7
14
DDRB_SMA9
23
DDRB_SMA8
14
DDRB_SMA6
23
DDRB_SMA10
14
DDRB_SMA1
23
DDRB_SCS#1
DDRB_SMA3
14
DDRB_SMA5
23
1 4
2 3
56_4P2R_0404_5%~D
1 4
2 3
56_4P2R_0404_5%~D
DDRB_SWE#
DDRB_SBS0
DDRB_SBS1
DDRB_CKE1
DDRB_SCS#0
DDRB_SCS#1
V_1P25V_DDR_VTT
RN57
RN20
DDRB_SWE#
DDRB_SBS0
DDRB_SBS1
DDRB_CKE0
DDRB_CKE1
DDRB_SCS#0
DDRB_SCS#1
V_1P25V_DDR_VTT
B B
1
C519
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C504
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C492
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
A A
C499
0.1U_0402_10V6K~D
2
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*28
1
C514
0.1U_0402_10V6K~D
2
1
C512
0.1U_0402_10V6K~D
2
1
C498
0.1U_0402_10V6K~D
2
1
C494
0.1U_0402_10V6K~D
2
5
1
C515
0.1U_0402_10V6K~D
2
1
C518
0.1U_0402_10V6K~D
2
1
C501
0.1U_0402_10V6K~D
2
1
C486
0.1U_0402_10V6K~D
2
1
C516
0.1U_0402_10V6K~D
2
1
C513
0.1U_0402_10V6K~D
2
1
C500
0.1U_0402_10V6K~D
2
1
C495
0.1U_0402_10V6K~D
2
1
C517
0.1U_0402_10V6K~D
2
1
C503
0.1U_0402_10V6K~D
2
1
C438
0.1U_0402_10V6K~D
2
1
2
We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02')
1
C511
0.1U_0402_10V6K~D
2
1
C661
0.1U_0402_10V6K~D
2
@
1
C493
0.1U_0402_10V6K~D
2
C490
4.7U_1206_16V6K~D
1
C510
4.7U_1206_16V6K~D
2
4
1
C662
0.1U_0402_10V6K~D
2
@
1
C496
0.1U_0402_10V6K~D
2
1
C667
0.1U_0402_10V6K~D
2
@
1
2
@
1
C502
0.1U_0402_10V6K~D
2
1
2
@
C663
0.1U_0402_10V6K~D
C668
0.1U_0402_10V6K~D
V_1P25V_DDR_VTT
1
C488
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C484
0.1U_0402_10V6K~D
2
V_1P25V_DDR_VTT
1
C443
0.1U_0402_10V6K~D
2
Decoupling Reference Document:
Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*26
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C482
0.1U_0402_10V6K~D
2
1
C478
0.1U_0402_10V6K~D
2
1
C442
0.1U_0402_10V6K~D
2
1
C481
0.1U_0402_10V6K~D
2
1
C476
0.1U_0402_10V6K~D
2
1
C434
0.1U_0402_10V6K~D
2
2
1
C487
0.1U_0402_10V6K~D
2
1
C485
0.1U_0402_10V6K~D
2
1
C441
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
1
C437
0.1U_0402_10V6K~D
2
1
C440
0.1U_0402_10V6K~D
2
1
C666
0.1U_0402_10V6K~D
2
@
1
C477
0.1U_0402_10V6K~D
2
1
C479
0.1U_0402_10V6K~D
2
1
C505
4.7U_1206_16V6K~D
2
1
C483
0.1U_0402_10V6K~D
2
1
C480
0.1U_0402_10V6K~D
2
1
C664
0.1U_0402_10V6K~D
2
@
1
C436
0.1U_0402_10V6K~D
2
1
C439
0.1U_0402_10V6K~D
2
1
C665
2
@
We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')
Compal Electronics, Inc.
Title
DDR Termination Resistors
Size Document Number Rev
C
Date: Sheet of
LA-1711
1
17 65Wednesday, January 28, 2004
A00-B
5
G_ST[0..2]
G_AD[0..31]
G_C/BE#[0..3]
G_SBA#[0..7]
CK_66M_AGP
D D
G_REQ#
AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0
Note:
AGP8X_DET_GC :Pull low by an AGP3.0 graphics card
Floating by an AGP2.0 graphics card
C C
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO
B B
G_ST0
G_ST1
G_ST2
2
1
G_SBA#[0..7]
G_AD_STBF0
G_AD_STBS0#
G_AD_STBF1
G_AD_STBS1#
G_SB_STBF
G_SB_STBS#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
G_PIPE#_DBI_HI
G_DBI_LO
FPVCC
C317
0.1U_0402_10V6K~D
CK_66M_AGP
G_REQ#
G_ST0
G_ST1
G_ST2
AGP8X_DET_CG : low -->MB
support AGP3.0
VREFCG
R322
1
C388
0.1U_0402_16V4Z~D
2
GC_BL_SUSPEND
4
PCI_PIRQB#
+1.5VRUN
+1.5VRUN
RUNPWROK
FPVCC
+1.5VRUN
SP_DIF
ICH_SUS_STAT#
12
+5VSUS
+3VSUS
+3VRUN
0_0402_5%~D
+12V
G_PWR_SRC
CK_66M_AGP
AGP8X_DET_CG
PCI_PIRQB#
G_ST0
G_ST2
G_SBA#2
G_SBA#4
G_SB_STBF
G_SB_STBS#
AGP_RST#
G_IRDY#
G_TRDY#
RUNPWROK
G_STOP#
G_FRAME#
G_C/BE#3
G_AD31
G_AD29
G_AD_STBS1#
G_AD_STBF1
G_AD27
G_AD25
G_C/BE#2
G_AD21
G_AD19
VREFCG
G_AD15
G_AD13
G_AD11
G_AD9
G_AD_STBS0#
G_AD_STBF0
G_AD5
G_AD3
G_AD1
G_AD0
FPVCC
ICH_SUS_STAT#
GC_BL_SUSPEND
JVID
1
1
3
3
5
5
7
7
9
9
11
11
13
GND
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
GND
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
GND
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
GND
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
GND
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
GND
149
149
151
151
153
153
155
155
157
157
159
159
FOX_QT00160A-9120L~D
3
2
2
4
4
6
6
8
8
10
10
12
12
14
GND
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
GND
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
GND
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
GND
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
GND
124
124
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
142
142
144
144
146
146
148
GND
150
150
152
152
154
154
156
156
158
158
160
160
G_PWR_SRC
G_PWR_SRC
AGP8X_DET_GC
PCI_PIRQA#
G_REQ#
G_ST1
G_SBA#0
G_SBA#1
G_SBA#3
G_SBA#5
G_SBA#6
G_SBA#7
G_DEVSEL#
G_RBF#
G_WBF#
G_PIPE#_DBI_HI
G_AD30
G_AD28
G_AD26
G_AD24
G_AD22
G_AD20
G_AD18
G_AD23
G_AD17
G_AD16
G_DBI_LO
G_C/BE#1
VREFGC_R
G_AD14
G_AD12
G_AD10
G_AD8
G_AD7
G_AD6
G_AD4
G_AD2
G_C/BE#0
G_GNT#
G_PAR
SBAT_SMBDAT
SBAT_SMBCLK
STP_AGP_R#
+3VRUN
+1.5VRUN
2
C26
1
0.1U_0603_25V7M~D
R626 0_0402_5%~D
AGP8X_DET_GC
PCI_PIRQA#
G_RBF#
G_WBF#
+1.5VRUN
G_AGPBUSY#
SBAT_SMBCLK
+5VALW
+5VRUN
LID_CL#
+5VSUS
2
C23
1
0.1U_0603_25V7M~D
12
R88
1 2
0_0402_5%~D @
SBAT_SMBDAT
2
C24
1
0.1U_0603_25V7M~D
GC_THERMTRIP#
+3VRUN
2
C22
1
0.1U_0603_25V7M~D
VREFGC
+3VRUN
1 2
2
1
C21
2
0.1U_0603_25V7M~D
R96
10K_0402_5%~D
R98
0_0402_5%~D@
1 2
PWR_SRC
2
C19
1
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
CPLD Disable
Pop R96, Depop R98
STP_AGP#
+1.5VRUN
1
PWR_SRC G_PWR_SRC
2
C12
Q8
SI4435DY_SO8~D
1
2
3 6
4
8
7
5
1
R30
1 2
100K_0402_5%~D
Make R571
100K ohm
after 6th
August
RUN_ON
12
R28
100K_0402_5%~D
AGP_PWRON# GPWR_SRC_ON
13
D
Q7
2
G
2N7002_SOT23~D
S
FOXCONN QT00160A-9120L
Shielding Ground Pin
13,14
39,40
67,68
93,94
121,122
147,148
1
1
C325
C334
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
2
1
CLOSE
TO PIN
2
+5VALW
1
2
C415
0.1U_0402_16V4Z~D
1
+3VSUS
U7
TC7SH32FU_SSOP5~D@
5
SYS_SUSPEND
1
P
AGP_RST#
A A
5
4
O
R156
0_0402_5%~D
INB
PCIRST_AGP#
2
INA
G
3
12
4
SYS_SUSPEND
PCIRST_AGP#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C417
2
0.047U_0402_10V4M~D
+12V
1
C413
0.1U_0402_16V4Z~D
2
C418
2
0.047U_0402_10V4M~D
C339
2
0.047U_0402_10V4M~D
+5VRUN
1
C416
0.1U_0402_16V4Z~D
2
1
1
C342
C336
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1
2
1
1
C397
C409
2
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
1
1
C357
C352
2
2
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
VGA Daughter Board Conn.
LA-1711
1
18 65Wednesday, January 28, 2004
A00-B
5
+3VALW
4
3
2
1
CPU Temperature Sensor
D D
R378
R375
1 2
1 2
DAT_SMB
CLK_SMB
C C
DAT_SMB
CLK_SMB
6.8K_0402_5%~D
6.8K_0402_5%~D
FAN3 Control and Tachometer
+12V
12
8
U46A
P
O
G
LM358M_SO8~D
4
C672
R617
4
+12V
1 2
1
R609
10K_0402_5%~D@
+3VRUN
B B
A A
5
10K_0402_5%~D
FAN3_PWM
R117
R616
1M_0402_5%~D
1 2
C671
1U_0805_10V6K~D
12
2
G
1
2
13
D
S
2.7K_0402_5%@
Q75
2N7002_SOT23~D@
3
2
2200P_0603_50V7K~D @
12
R618
100K_0402_5%~D
R610
+12V
IN+
IN-
1 2
300K_0402_5%
1 2
C408
1 2
0.1U_0402_16V4Z~D
FAN3_TACH
0.47U_0603_16V7K~D
Q28
SI3457DV-T1_TSOP6~D
D
S
4 5
G
3
+3VRUN
6
2
1
U37
3
VCC
16
SDA
1
SCL
6
TACH1
7
TACH2
4
TACH3
9
TACH4
PWM2/ALERT#
2
GND
ADT7460ARQ_QSOP16~D
2.5VIN
PWM1
PWM3
14
13
D1+
D1-
D2+
D2-
H_THERMDC
12
MCH_THERMDA
11
MCH_THERMDC
10
FAN3_PWM
15
5
8
R365 10K_0402_5%~D
Address 0101 110X (X=1-->Read; X=0-->Write)
+5VRUN
R118
10K_0402_5%~D
1 2
R120
1K_0402_5%~D
1 2
1
C89
FAN3_ON
2
1
2
3
SUYIN_250019MR003G400ZL~D
Item101: Reserved Op amp circuit (NP) to the High side FET
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JFAN3
1
2
3
FAN3TACH_ON
FAN3
3
1 2
2 1
1 2
0_0402_5%~D
+3VRUN
12
R125
10K_0402_5%~D
Q29
2
PMBT2222_SOT23~D
3 1
D1
RB751V_SOD323~D
R366
FAN3_TACH
1
C420
2200P_0603_50V7K~D
2
+3VRUN
1
+
C88
47U_D_16VM_R70~D
2
ATF_INT#
H_THERMDA
H_THERMDC
2
MCH_THERMDAH_THERMDA
1
C657
2200P_0603_50V7K~D
2
MCH_THERMDC
Q73
2
MMBT3904_SOT23~D
Put 3904 between MCH and DDR
Put Cap near pin 10,11 of U37
DELL CONFIDENTIAL/PROPRIETARY
Title
CPU Thermal Sensor & FAN Control
Size Document Number Rev
Date: Sheet of
LA-1711
1
3 1
19 65Wednesday, January 28, 2004
A00-B
5
+3VRUN
RN3
182736
45
8.2K_8P4R_1206_5%~D
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
+3VRUN
D D
+3VRUN
+3VRUN
C C
+3VRUN
+3VRUN
B B
+3VSUS
PCI_PCIRST#
A A
182736
182736
182736
12
R386
10K_0402_5%~D
12
R401
10K_0402_5%~D
10
13
12
RN2
45
8.2K_8P4R_1206_5%~D
RN4
45
8.2K_8P4R_1206_5%~D
RN1
45
8.2K_8P4R_1206_5%~D
12
R113
10K_0402_5%~D
12
R426
10K_0402_5%~D
U8A
14
74VHC08MTC_TSSOP14~D
1
P
IN1
OUT
2
IN2
G
7
U8B
74VHC08MTC_TSSOP14~D
4
IN1
OUT
5
IN2
U8C
74VHC08MTC_TSSOP14~D
IN1
OUT
9
IN2
U8D
74VHC08MTC_TSSOP14~D
IN1
OUT
IN2
R387
10K_0402_5%~D
R139
10K_0402_5%~D
3
6
8
11
5
PCI_FRAME#
12
R398
8.2K_0402_5%~D
@
PCI_GNTA#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
12
R119
8.2K_0402_5%~D
PCI_PLOCK#
PCI_REQ0#
PCI_REQB#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_REQ2#
12
PCI_REQ4#
PCI_REQ1#
PCI_REQ3#
12
IDE_IRQ15
IDE_IRQ14
IRQ_SERIRQ
IDE_IRQ15
IDE_IRQ14
IRQ_SERIRQ
C118
0.1U_0402_16V4Z~D
R162
33_0402_5%~D
PCIRSTB1#
1 2
R159
33_0402_5%~D
PCIRSTB2#
1 2
33_0402_5%~D
1 2
R153
33_0402_5%~D
PCIRSTB3# PCIRST_1#
1 2
PCIRSTB4#
33_0402_5%~D
1 2
+3VRUN
R393
10K_0402_5%~D
1 2
PCI_REQA#
R414
CK_33M_ICHPCI
12
10_0402_5%~D@
CLK_ICH_TERM
1
C465
8.2P_0402_50V8J~D
@
2
+1.5VRUN
+1.5VRUN
12
R411
226_0603_1%~D
HI_SWING_ICH
12
R410
147_0603_1%~D
12
R409
113_0603_1%
12
PCIRST_AGP#
PCIRST_SIO#
R160
R157
PCIRST_2#
PCIRST_AGP#
PCIRST_SIO#
PCIRST_CB#
PCIRST_1#
PCIRST_2#
R124
1 2
52.3_0603_1%~D
HI_VREF_ICH
4
+3VRUN
RN35
182736
45
8.2K_8P4R_1206_5%~D
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
HI_RCOMP_ICH
Note:
HI_SWING_MCH, HI_VREF_MCH
trace width of 12mils and
space 10mils
2
C460
0.1U_0402_16V4Z~D
1
2
C456
0.1U_0402_16V4Z~D
1
4
+3VSUS
1
C455
0.01U_0402_16V7K~D
2
Close to ICH ball <250mils
1
C452
0.01U_0402_16V7K~D
2
Close to ICH ball <250mils
0.1"~6"
ICH_AC_RST_R#
ICH_AC_SYNC_R
ICH_AC_SDOUT_R
ICH_AC_SDOUT
ICH_AC_BITCLK
ICH_AC_SDIN0
ICH_AC_SDIN1
R389 33_0402_5%~D
R385 33_0402_5%~D
R390 33_0402_5%~D
R383
1K_0402_5%~D@
1 2
3
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
R425
10K_0402_5%~D@
12
ICH_PME#
PCI_PERR#
PCI_SERR#
PCI_PCIRST#
CK_33M_ICHPCI
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#
PCI_REQB#
PCI_GNT1#
PCI_GNT3#
PCI_GNT4#
PCI_GNTB#
HUB_HL[0..10]
R406 61.9_0603_1%
1 2
HUB_HLSTRF
HUB_HLSTRS
ICH_AC_SDIN0
ICH_AC_SDIN1
ICH_AC_BITCLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
ICH_PME#
PCI_PCIRST#
CK_33M_ICHPCI
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQA#
PCI_REQB#
PCI_GNT1#
PCI_GNT3#
PCI_GNT4#
PCI_GNTA#
PCI_GNTB#
R430 0_0402_5%~D
R392 1K_0402_5%~D@
1 2
LAN_RST#
12
NC_EE_DOUT
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDOUT_R
ICH_AC_SDIN0
ICH_AC_SDIN1
HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10
HI_RCOMP_ICH
HI_SWING_ICH
HI_VREF_ICH
CK_66M_ICH
U5A
D2
FRAME#
M3
IRDY#
E4
TRDY#
L3
DEVSEL#
E5
STOP#
F1
PAR
K2
PERR#
L2
PLOCK#
L4
SERR#
V2
PME#
V4
PCIRST#
N1
PCICLK
B3
PIRQA#
E1
PIRQB#
A2
PIRQC#
C2
PIRQD#
D7
PIRQE#/GPI2
A6
PIRQF#/GPI3
E2
PIRQG#/GPI4
B1
PIRQH#/GPI5
D5
REQ0#
C1
REQ1#
C5
REQ2#
B6
REQ3#
C6
REQ4#/GPI40
A5
REQA#/GPI0
E7
REQB#REQ5#/GPI1
D4
GNT0#
A3
GNT1#
B7
GNT2#
C7
GNT3#
A4
GNT4#/GPO48
E8
GNTA#/GPO16
B4
GNTB#/GNT5#/GPO17
FW82801EB_mBGA460_ICH5~D
H20
H21
J20
H23
M23
M21
N21
M20
L22
J22
K21
G22
K23
J24
N24
L20
L24
N22
C10
C9
C11
D9
E9
B12
D10
E10
AA1
B11
B10
A12
B9
B8
C12
A9
E12
D12
A13
D8
FW82801EB_mBGA460_ICH5~D
R396
10_0402_5%~D@
U5B
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11
HI_STBF
HI_STBS
HIRCOMP
HI_VSWING
HIREF
CLK66
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
LAN_CLK
LAN_RST#
EE_DIN
EE_CS
EE_SHCLK
EE_DOUT
AC_SYNC
AC_RST#
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_BIT_CLK
2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
C/BE3#
C/BE2#
C/BE1#
C/BE0#
USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
USBP6P
USBP6N
USBP7P
USBP7N
OC0#
OC1#
OC2#
OC3#
OC4#/GPI9
OC5#/GPI10
OC6#/GPI14
OC7#/GPI15
USBRBIAS
USBRBIAS#
CLK48
1
USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5USBP6+
USBP6-
PCI_AD[0..31]
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
12
R404
12
10_0402_5%~D@
Note:
USBRBIAS keep less than 500mils
CK_48M_ICH_TERM
2
C431
@
4.7P_0402_50V8C~D
1
RN111
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%~D
RN112
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
USB_OC6#
USB_OC IS 5V
TOLERANT
+3VSUS
PCI_AD31
P2
PCI_AD30
F4
PCI_AD29
P4
PCI_AD28
F5
PCI_AD27
N2
PCI_AD26
D3
PCI_AD25
P3
PCI_AD24
E6
PCI_AD23
N4
PCI_AD22
C4
PCI_AD21
N5
PCI_AD20
H3
PCI_AD19
P5
PCI_AD18
B2
PCI_AD17
L1
PCI_AD16
G4
PCI_AD15
G5
PCI_AD14
K1
PCI_AD13
G2
PCI_AD12
L5
PCI_AD11
H4
PCI_AD10
M4
PCI_AD9
F2
AD9
PCI_AD8
K5
AD8
PCI_AD7
J2
AD7
PCI_AD6
J3
AD6
PCI_AD5
H2
AD5
PCI_AD4
H5
AD4
PCI_AD3
K4
AD3
PCI_AD2
G3
AD2
PCI_AD1
J5
AD1
PCI_AD0
J4
AD0
M2
N3
J1
E3
C23
D23
A22
B22
C21
D21
A20
B20
C19
D19
A18
B18
C17
D17
A16
B16
USB_OC0#
C15
USB_OC1#
D15
USB_OC2#
D14
USB_OC3#
C14
USB_OC4#
B14
USB_OC5#
A14
USB_OC6#
D13
USB_OC7#
C13
A24
B24
F24
USBRBIAS
CK_48M_ICH
CK_48M_ICH
R394 22.6_0603_1%~D
1 2
CK_66M_ICH
12
12
12
R395
10K_0402_5%~D@
ICH_AC_RST#
ICH_AC_SYNC
ICH_AC_SDOUT
+3VRUN
12
12
12
R397
R402
10K_0402_5%~D@
10K_0402_5%~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
ICH_AC_BITCLK_TERM
2
C427
10P_0402_50V8J~D
@
1
2
CK_66M_ICH
R413
10_0402_5%~D
1 2
CK_66M_ICH_TERM
2
C464
10P_0402_50V8J~D
1
DELL CONFIDENTIAL/PROPRIETARY
Title
ICH5-PCI/HUB/USB/AC97
Size Document Number Rev
Date: Sheet of
LA-1711
1
A00-B
20 65Wednesday, January 28, 2004
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