Compal LA-1684 Ibiza, Inspiron 1150, Latitude 100L Schematic
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
MODEL NAME :
Ibiza
COMPAL P/N :
PCB NO :
Revision :
2 2
LA-1684
1.0
Ibiza Schematics Document
uFCBGA/uFCPGA NorthWood MT
2004-01-09
3 3
4 4
Dell-Compal Confidential
Com pal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Cover Sheet
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
E
of
148Friday, January 09, 2004
1.0
A
Compal confidential
B
C
D
E
Block Diagram
Model : Ibiza (Abacus MT for Ext. Gfx)
NorthWood-MT
1 1
Fan Control 1
+12V
Fan Control 2
+5VS
page 7
page 7
Mainstream
LVDS Connector
on VGA Board
TV OUT
CRT Connector
2 2
LVDS Connector
on M/B Board
page 19
page 19
page 18
CPU B ypass
AGP Conn
Value
page 7
PIRQE#
page 17
Internal LVDS
AGP4X(1.5V)
CRT Signal
+1.2VP
+CPU_CORE
+1.5VS
+2.5V
+1.25VS
+CPU_CORE
Prescott-MT
uFCPGA CPU
478pin
System Bus
400/533 MHz
INTEL
Montara-GMV
732 BGA
HUB LINK 1.5
+1.5VS
66MHz
Celeron 533
page 5,6
HD#(0..63)HA#( 3..31)
page 9,10,11,12
CPU ITP Port
and VID
page 8
Memory
BUS(DDR)
Therm al Sensor
ADM1032
+5VS +3VS
+2.5V 200/266/333MHz
page 6
Clock Generator
ICS950810
DDR-DIMM X2
BANK 0, 1, 2, 3
+2.5V
+1.25VS
page 13,14,15
page 16
+3VS 33MHz
IDSEL:AD18
(PIRQC,D#,GNT#1,REQ#1)
Debug
+5VS
page 35
3 3
Minipci CONN
WIRELESS
+3V
+3VS
+5VS
page 28
LAN
BCM -4401L
+3V +3V
Power On/Off
Reset & RTC
page 34
IDSEL:AD17
(PIRQB#,GNT#0,REQ#0)
page 24
RJ45
page 24
DC/DC Interface
Suspend
CardBus & 1394
Card Bus
SLOT CONN
page 26
page 35
PCI BUS
IDSEL:AD20
(PIRQA#,GNT#2,REQ#2)
PCI4510
PCI1510 for Ibiza
page 25,26,27
1394
page 25
+3VS
+3VALW
+1.5VS
+1.5VALW
+CPU_CORE
VCC5REF
VCC5REFSUS
LPC BUS
Touch Pad
LID Switch
+5VS
NS PC97551
Embedded
Controller
+3VS
+3VALW
page 31
INTEL
ICH4-M
421 BGA
page 20,21,22
+3VS
33MHz
page 32
Ext. IO
Int.KBD
page 33
page 33
48MHz
24.576M Hz /14.318M Hz
IDE HDD
+5VS
page 23
ATA100
CD-ROM
+5VS
PIDE IRQ14SIDE IRQ15
USB 2.0/1.1
AC-LINK
IDE
page 23
AMP & INT.
Speaker
+5VALW +5VDDA
AC97 Codec
STAC9750
+5VDDA
page 30
2X USB Ports
+3VALW
+5VALW
page 29
HeadPhone &
MIC Jack
page 30
page 34
MDC
+3VALW
+3V
RJ11
Cable
page 31
Cable
Power Circuit
4 4
DC/DC
page
36,37,38,39,40,41
A
LED Indicator
Connector
page 34
B
EC DEBUG
+3VALW
page 32
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
BIOS
+3VALW
page 33
Dell- C o m p a l C onfidential
Compa l Electronics, Inc.
Title
Block Di agram
Size Docu ment Number Re v
Ibiza LA - 1684
D
Date: Sheet
248Friday, January 09, 2004
E
1.0
of
5
4
3
2
1
Power Managment table
+3VS
Signal
ST2
D D
FSB
LH400
533
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
+1.5VALW
+3VALW
+5VALW
+12VALW
+3V
+2.5V
+12V_FAN
ON
ON ON
ON ON ON
ON ON
ON OFF
OFF OFF OFF
+5VS
+1.5VS
+1.2VP
+CPU_CORE
+1.25VS
OFF
OFF
SCHEMATICS VERSION LIST
VERSION ISSUE DATE REMARK
0.1
0.2
08/19/2003
10/06/2003
SST Release
PT Release
Seperate from Abacus-MT
0.1
1.0
11/19/2003
01/05/2004
ST Release
QT Release
Ceramic Capacitor Spec Guide:
C C
Temperature Characteristics:
Z5V
J
SL
1
Z5P
A
BJ
Symbol
CODE
0
Z5U
8
NP0 SH
H
UJ
9
C0G SJ
I
UK
3
2
Y5U X7R
C
B
CH
4
Y5V Y5P
CJ
5
E
D
CK
X5R
6
7
F
G
Item
Function Note
Ibiza
1@
Abacus-MT
2@
@ DEPOP
Montara GMV with no TV, 1394
Montara-PM
GMV supply 533 Celeron, and use the internal Gfx
Tolerance:
F
V
+20,-10%
K
A
+-0.05PF
M
+-20%
Symbol
CODE
B B
+-10%
B
+-0.1PF
N
+-30%
C
+-0.25PF
P
+100,-0%
D
+-0.5PF +-1PF
Q
+30,-10%
G
+-2%
X
+40,-20%
H
+-3%
Z
+80,-20%
J
+-5%
SMBUS Control Table
SOURCE
INVERTER BATT
SERIAL SENSOR
EEPROM
THERMAL
(CPU)
THERMAL
SENSOR
(LM75)
SODIMM CLK CHIP
MINI PCI
LCD
VGA Thermal
ADM1032
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CLK
SMB_CDATA
A A
LCD_DDCCLK
LCD_DDCDATA
PC87591L
PC87591L
ICH4-M
M-GT
5
Dell-Compal Confidential
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Note & Revision
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
1
of
348Friday, January 09, 2004
0.1
5
4
3
2
1
PU22
U66
FAN5234
page 39
+1.5VALW
SUSP#
+1.5VS
page 35
+5VALW
D D
+5VALW
SHDN#
PU8
MAX1632
page 38
U31
SUSP#
Q6
SIDEPWR
U26
SUSP#
+5VS
page 35
+5VSHDD
page 23
+5VDDA
page 29
U70
+3VALW
C C
page 36
PU21
+12VALW
SYSON
U20
SUSP#
+3V
page 35
+3VS
page 35
VR_ON
PU27
AC
Battery
page 36
B+
LM3485
page 38
ENLL
+12VFANP
PU23
Mobile
ISL6247
+CPU_CORE
LMS5258
page 41
+1.2VP
JP8
+5VS
page 41
B B
SUSP#
PU20
ISL6225
+1.25VS
+3VS
+1.5VS
+2.5V
VGA Conn.
180 pin
page 40
+2.5V
+3V
SYSON
+5VALW
+12VALW
B+
A A
Compa l Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Docu ment Number Re v
Date: Sheet
For External VGA
Dell- C o m p a l C onfidential
POWER DIAGRAM
Ibiza LA - 1684
page 17
1
1.0
of
448Friday, January 09, 2004
5
D D
A10
A12
A14
A16
A18
JCPU1A
HA#[3..31]<9> HD#[0..63] <9>
C C
H_REQ#[0..4]<9>
+CPU_CORE
B B
H_REQ#[0..4]
H_ADS#<9>
R284 56 _0402_1%
1 2
R301 220_0402_5%
1 2
H_BREQ0#<9>
H_BPRI#<9>
H_BNR#<9>
H_LOCK#<9>
CLK_CPU_BCLK<16>
CLK_CPU_BCLK#<16>
H_HIT#<9>
H_HITM#<9>
H_DEFER#<9>
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
CLK_CPU_BCLK
CLK_CPU_BCLK#
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
AF22
BCLK0
AF23
BCLK1
CON
F3
HIT#
TROL
E3
HITM#
E2
DEFER#
FOX_PZ47803-274A-42_Prescott
A20
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
HOST
ADDR
CONTROL
CLK
VSS_0H1VSS_1H4VSS_2
H23
H26
4
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AA10
AA12
AA14
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
AE18
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
POWER
Northwood-MT
Prescott-MT
GND
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
A11
A13
A15
A17
A19
A21
A24
A26
AA1
AA11
AA13
AA4
AA7
AA15
AA17
AA9
AA19
AA23
AA26
AB10
AB12
AB14
AB3
AB6
AB16
AB18
AB8
AB20
AB21
AB24
3
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
VCC_67
VCC_68
VCC_69
HOST
ADDR
POWER
VCC_78
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
AC2
AC5
AC7
AC11
AC13
AC15
AC17
AC19
AC9
AC22
AC25
AD10
AD12
AD14
AD16
AD18
BOOTSELECT
VSS_52
VSS_53
VSS_54
VSS_55
VCC_81
F13
AD1
AD4
AD8
AD21
AD23
VCC_79E8VCC_80
VCC_82
VCC_83
VCC_84
VCC_85
F9
F11
F15
F17
F19
E18
E20
VCC_70
VCC_77
E16
D9
VCC_71D7VCC_72
VCC_76
E14
E10
VCC_75
E12
2
+CPU_CORE
VCC_73
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
+CPU_CORE
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
1
HD#[0..63]HA#[3..31]
A A
NWD: L PSD: H
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
PSD Pull-up internal
BOOTSELECT <41>
2
Dell-Compal Confidential
Com pal Electronics, Inc.
Title
Prescott / P4 uFCPGA (1/2)
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
1
of
548Friday, January 09, 2004
1.0
5
+CPU_CORE
1 2
D D
C C
B B
R279 51_0402_5%
1 2
R262 51_0402_5%
1 2
R272 51_0402_5%
1 2
R268 51_0402_5%
1 2
R296 51_0402_5%
1 2
R278 51_0402_5%
1 2
R291 51_0402_5%
1 2
R288 300_0402_5%
+IOPLL
0_0603_5%
R207
1 2
R206 @0_0603_5%
1 2
L24
1 2
LQG21F4R7N00_0805
1 2
LQG21F4R7N00_0805
L25
@1U_0603_10V6K
CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>
CLK_ITP<8>
CLK_ITP#<8>
R572 49.9_0402_1%
1 2
R573 49.9_0402_1%
1 2
+CPU_CORE
H_RS#[0..2]<9>
H_RESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
H_PW RGD
+CPU_CORE
+CPU_CORE
+1.2VP
1
+
C644
2
C320
2
33U_D2_4VM
1
RP62
@0_4P2R_0402_5%
GTL Ref e r e n c e V o l tage
Layout note :
H_RS#[0..2]
H_TRDY#<9>
H_A20M#<20>
H_FERR#<20>
H_IGNNE#<20>
H_SMI#<20>
H_PWRGD<20>
H_STPCLK#<20>
H_INTR<20>
H_NMI<20>
H_INIT#<20>
H_RESET#<8,9>
H_DBSY#<9>
H_DRDY#<9>
H_BSEL0<16>
1 2
R315 56 _0402_1%
ITP_BPM#0<8>
ITP_BPM#1<8>
ITP_BPM#2<8>
ITP_BPM#3<8>
ITP_BPM#4<8>
ITP_BPM#5<8>
ITP_TCK<8>
ITP_TDI<8>
ITP_TDO<8>
ITP_TMS<8>
ITP_TRST#<8>
VCCIOPLL
VCCA
VCCSENSE<41>
VSSSENSE<41>
+1.2VP
VSSA
RP61
@0_4P2R_0402_5%
R302 61.9_0603_1%
1 2
R300 61.9_0603_1%
1 2
23
14
ITP_CLK0
ITP_CLK1
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_A20M#
H_FERR#
H_IGNNE#
H_SMI#
H_PW RGD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
H_BSEL0
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
VCCSENSE
VSSSENSE
ITP_CLK0
14
ITP_CLK1
23
FOX_PZ47803-274A-42_Prescott
1. Place R_A and R_B near CPU (With in 1. 5").
R265
60.4_0603_1%
+H_GTLREF
A A
12
R261
102_0603_1%
1
C319
1U_0603_6.3V6M
2
2200P_0603_50V7K
SMB_EC_CK2<8,32>
SMB_EC_DA2<8,32>
CPU Temperature Sensor
JCPU1B
F1
G5
F4
AB2
J6
C6
B6
B2
B5
AB23
Y4
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
AE23
A5
A4
AF3
AD22
AC26
AD26
L24
P1
H_THERMDA
C470
H_THERMDC
Intel change to 0.63VCC, then 60.4/102
5
GND
RS#0
RS#1
RS#2
RSP#
TRDY#
CON
TROL
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
LINT0
LEGACY
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1
1
2
4
AE11
AE13
AE15
AE17
VSS_57
VSS_58
VSS_59
VSS_60
MISC
THER
MAL
MISC
ITP
MISC
ITP
CLK
VSS_129F8VSS_130
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
G21
G24
8.2K_0402_5%
4
AE19
+5VS
3
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
E26
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
GROUND
Northwood-MT
Prescott-MT
GROUND MISC
VID0
VID1
S
G
VID2
AE5
AE4
AE3
AE2
CPU_VID2
CPU_VID0
CPU_VID1
CPU_VID3
+CPU_CORE
1 2
Q64
3 1
MMBT3904_SOT23
R334
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
VSS_181
1
Q62
Y22
Y25
3
D
1 3
Y5
D52
SM05_SOT23
2
J22
J25
12
K21
K24
12
R333
8.2K_0402_5%
L23
L26
+5VS
U57
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
T21
R23
R26
12
R337
@10K_0402_5%
T24
SHDN_1632#<36,38>
3
V23
V26
U22
U25
PCIRST#<10,17,20,24,25,27,28,32,35>
W21
W24
2
2N7002_SOT23
P22
N21
M22
M25
1
C174
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P25
N24
1
6
4
5
F10
F12
VSS_121
VID3
VID4
VID5
AE1
AD3
CPU_VID5
CPU_VID4
R316
470_0402_5%
2
2
F14
F16
F18
VSS_122
VSS_123
VSS_124
VIDPWRGD
AD2
R467
2.43K_0603_1%
Q59
MMBT3904_SOT23
3 1
2
AF26
F22
F25
F5
VSS_125F2VSS_126
VSS_127
VSS_128
SKTOCC#
REF
OPTIMIZED/COMPAT#
ITP
DATA
ADDR
DATA
MISC
VCCVID
AF4
12
CPU_VID[0..5] <8,41>
2
R320
470_0402_5%
1 2
2
1
H_SKTOCC#
R267
@33_0402_5%
DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
NC1
NC2
NC3
NC4
NC5
+1.2VP
H_VID_PWRGD <35>
1
3
H_THERMTRIP#
D54
SM05_SOT23
R269 and R317 depop for desktop CPU
J26
K25
K26
L25
AA21
AA6
F20
F6
AE26
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
A7
AF25
AF24
AE21
12
H_GHI#
H_DPSLPR#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DBR#
H_PROCHOT#
PROCHOT#<21,33>
R269 0_0402_5%
H_DPSLPR#
1 2
H_GHI#
1 2
R317 0_0402_5%
+H_GTLREF
1
C318
220P_0603_50V8J
2
R285
1 2
56_0402_5%
R275
1 2
56_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
R311
1 2
100K_0402_1%
H_SLP#
+1.2VP
1
C317
0.1U_0402_16V4Z
2
H_THERMTRIP# <21>
H_PROCHOT#<39>
+CPU_CORE
R293 56_0402_5%
R276 56_0402_5%
R294 56_0402_5%
R464 56_0402_5%
R465 56_0402_5%
R466 300_0402_5%
R318 @56_0402_5%
H_DBI#[0..3]
1 2
R266
@0_0402_5%
H_SLP# <20>
+3VS
R303
1K_0402_5%
R466 pop
56_0402_5% if
use DT CPU
and R318 pop
for DT
H_DSTBN#[0..3] <9>
H_DSTBP#[0..3] <9>
H_ADSTB#0 <9>
H_ADSTB#1 <9>
H_DBI#[0..3] <9>
+CPU_CORE
+CPU_CORE
1 2
2
Q26
MMBT3904_SOT23
3 1
H_PROCHOT#
Dell-Compal Confidential
Com pal Electronics, Inc.
Title
Prescott / P4 uFCPGA & Thermal sensor (2/2)
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
648Friday, January 09, 2004
1
H_DPSLP# <10,20>
PM_CPUPERF# <21>
SYSRST# <21>
H_DBR# <8>
R307
470_0402_5%
1 2
of
1.0
A
Layout n ote :
1 1
+CPU_CORE
2 2
+CPU_CORE
Place close to CPU, Use 2~3 vias per PAD.
Place 22uF caps x31 pcs, populated 14pcs.
1
C655
@22U_1210_6.3V6M
2
1
C666
@22U_1210_6.3V6M
2
3 3
+CPU_CORE
1
C673
22U_1210_6.3V6M
2
4 4
+CPU_CORE
1
2
C679
@22U_1210_6.3V6M
1
2
5 5
+CPU_CORE
6 6
+CPU_CORE
Please place these cap on the socket south side
1
C689
@22U_1210_6.3V6M
2
1
C694
@22U_1210_6.3V6M
2
7 7
8 8
A
B
C
Place on CPU inside
1
C656
22U_1210_6.3V6M
2
1
C667
22U_1210_6.3V6M
2
1
C657
22U_1210_6.3V6M
2
1
C668
22U_1210_6.3V6M
2
1
C658
@22U_1210_6.3V6M
2
1
C669
22U_1210_6.3V6M
2
Please place these cap on the socket north side
1
C682
@22U_1210_6.3V6M
2
1
2
1
2
C
1
C676
@22U_1210_6.3V6M
2
C692
22U_1210_6.3V6M
C697
22U_1210_6.3V6M
1
C674
@22U_1210_6.3V6M
2
C680
22U_1210_6.3V6M
1
C690
22U_1210_6.3V6M
2
1
C695
22U_1210_6.3V6M
2
B
1
2
1
C681
@22U_1210_6.3V6M
2
1
C691
@22U_1210_6.3V6M
2
1
C696
@22U_1210_6.3V6M
2
C675
22U_1210_6.3V6M
1
2
1
C683
22U_1210_6.3V6M
2
1
2
1
2
D
C670
22U_1210_6.3V6M
1
C677
22U_1210_6.3V6M
2
1
2
C693
@22U_1210_6.3V6M
C698
@22U_1210_6.3V6M
D
1
C671
22U_1210_6.3V6M
2
C684
@22U_1210_6.3V6M
E
Layout n ote :
Place close to CPU power and
ground pin as possible
(<1inch)
For Desktop's CPU:
330uFx7/7m ohm each
depop 8pcs
Fan1 Control circuit
EN_FAN1<32>
C686
1U_0603_10V4Z
F
+CPU_CORE
+CPU_CORE
+CPU_CORE
Note:When use +5V Fan,
the J2 must be opened. It
prevent the +5VS short to
+12V_FAN
+12VALW
3
+
1
2
R472
100K_0402_5%
2
-
1 2
C687 @2200P_0603_50V7K
R471
1 2
12
66.5K_0402_1%
84
1
+
2
1
+
2
1
+
2
U76A
LM358A
G
C645
@330U_D_2VM
C650
@330U_D_2VM
C661
330U_D_2VM
C678
2
0.1U_0402_16V4Z
1
FAN1_ON
1
D47
RB751V_SOD323
2 1
Note: R471 - 66.5K_1% for +5V Fan ; 300k_1% for +12V Fan
Fan2 Control circuit
U76B
LM358A
5
EN_FAN2<32>
1
C699
1U_0603_10V4Z
2
FAN2_VFB
12
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
E
F
+
6
-
C701 @2200P_0603_50V7K
1 2
1 2
R476 @100K_0402_5%
R477
150K_0603_5%
D48
@RB751V_SOD323
FAN2_ON
7
G
1
+
C646
330U_D_2VM
2
1
+
C651
@330U_D_2VM
2
1
+
C662
@330U_D_2VM
2
+12V_FAN +5VS
12
2@JOPEN
2
1
G
3
2
1
G
3
2 1
H
J2
L53
1@FBM-11-201209-300AT_0805
1 2
C672
1
0.1U_0402_16V4Z
2
6
Q65
D
SI3456DV-T1_TSOP6
S
4 5
0.47U_1206_16V4Z
1
+
C688
100U_D2_6.3VM
2
6
D
Q67
@SI3456DV-T1_TSOP6
S
4 5
FAN2_VOUT
1
C702
@10U_1206_10V4Z
2
H
I
1
+
C647
@330U_D_2VM
2
1
+
C652
330U_D_2VM
2
1
+
C663
330U_D_2VM
2
+5VS
1
C685
2
+5VS+5VS
1
C700
@0.47U_1206_16V4Z
2
12
R469
10K_0402_5%
R470
1 2
1K_0402_5%
3
2
FAN1_VOUT
FAN1_TACH_FB
1
2
12
R474
@10K_0402_5%
R475
1 2
@1K_0402_5%
FAN2_TACH_FB
1
C28
@1000P_0402_50V7K
2
1
+
C648
@330U_D_2VM
2
1
+
C653
330U_D_2VM
2
FAN1_TACH_ON
D55
1
SM05_SOT23
C22
1000P_0402_50V7K
FAN2_TACH_ON
1
+
2
1
+
2
+3VS
12
R468
10K_0402_5%
13
Q66
2
HMBT2222A_SOT23
JP28
4
4
3
3
2
2
1
1
C27
1
1000P_0402_50V7K
FAN1_VOUT
FAN1_TACH_FB
2
+3VS
12
13
Q68
2
@HMBT2222A_SOT23
JP29
1
2
3
1
@ACES_85205-0300
C29
@1000P_0402_50V7K
2
C649
330U_D_2VM
C654
330U_D_2VM
R473
@10K_0402_5%
Dell- C o m p a l C onfidential
Compa l Electronics, Inc.
Title
CPU Decoupling CAP . & Fan control
Size Docu ment Number Re v
Ibiza LA - 1684
Date: Sheet
I
J
FAN1_TACH <32>
2@ACES_85205-0400
JP34
1
2
3
1@MOLEX_53398-0390_3P
FAN2_TACH <32>
of
748Friday, January 09, 2004
J
1.0
10
9
8
7
6
5
4
3
2
1
H H
G G
F F
E E
H_RESET#<6,9>
D D
CPU_VID[0..5]<6,41>
VID [0..5]
+CPU_CORE
1
2
CLK_ITP<6>
CLK_ITP#<6>
C704
@2.2P_0402_16VCJ
C703
0.1U_0402_16V4Z
H_DBR#<6>
ITP_BPM#0<6>
ITP_BPM#1<6>
ITP_BPM#2<6>
ITP_BPM#3<6>
ITP_BPM#4<6>
ITP_BPM#5<6>
1 2
R483
150_0402_5%
ITP_TRST#<6>
1
1
C705
@2.2P_0402_16VCJ
2
2
ITP_TDO<6>
ITP_TCK<6>
ITP_TMS<6>
ITP_TDI<6>
+CPU_CORE
H_DBR#
ITP_RESET#
ITP_TCK
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
JP30
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
R260 1K_0402_5%
R259 1K_0402_5%
R258 1K_0402_5%
R257 1K_0402_5%
R256 1K_0402_5%
R478 1K_0402_5%
29
GND6
GND7
@MOLEX_52435-2891
30
+3VS
12
12
12
12
12
12
VID 5 for Prescott-MT
R479
H_DBR#
1 2
150_0402_5%
R480
75_0603_1%
ITP_TDO
1 2
R481
150_0402_5%
ITP_TDI
1 2
ITP_TMS
1 2
R482
39.2_0603_1%
ITP_TRST#
R484
1 2
680_0402_5%
ITP_TCKITP_TDO
R485
1 2
27.4_0603_1%
+3VALW
+CPU_CORE
VID
43210 V
1
0
0
01
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11
101
00
1
0
1
1
1
1111
0000
000
1
00
111
000
000
0
0
11
0
1
11110
00
10
00
1
00
1
1
0
111
1
00
1
0
1
11
1
1
1
1111
1
0
1
0
1
0
1.5750
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
off
ITP DEBUG POINT
C C
+5VS
1
C482
@0.1U_0402_16V4Z
ITP Debug Connector
SMB_EC_DA2<6,32>
SMB_EC_CK2<6,32>
SMB_EC_DA2
SMB_EC_CK2
B B
U25
1
SDA
2
3
4
VCC
SCL
OS#
GND
@LM75CIMMX-5_MSOP8
8
7
A0
6
A1
5
A2
2
1 2
R351 @1K_0402_5%
SMB_EC_DA2
SMB_EC_CK2
U23
1
SDA
VCC
2
SCL
3
OS#
4
GND
@LM75CIMMX-5_MSOP8
A0
A1
A2
8
1 2
7
R308 @10K_0402_5%
6
5
12
@0.1U_0402_16V4Z
C394
1 2
R486
@1K_0402_5%
+5VS
Address:1001_000X Address:1001_001X
Dell- C o m p a l C onfidential
A A
10
9
8
7
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
6
5
4
3
Compa l Electronics, Inc.
Title
CPU VID & ITP PORT
Size Docu ment Number Re v
Ibiza LA-1684
Date: Sheet
2
of
848Friday, January 09, 2004
1
1.0
5
4
3
2
1
HA#[3..31]
U77 use Montara-GMV
for Internal Gfx
D D
C C
H_ADSTB#0<6>
H_ADSTB#1<6>
CLK_MCH_BCLK#<16>
CLK_MCH_BCLK<16>
B B
A A
H_D S T B N # [0 ..3 ]<6>
H_DSTBP#[0..3]<6>
H_DBI#[0..3]<6> H_RESET#<6,8>
HI[0..10]<20>
HUB_PSTRB<20>
HUB_PSTRB#<20>
+1.5VS
R495 27.4_0402_1%
R496 27.4_0402_1%
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
HI[0..10]
1 2
48.7_0603_1%
1 2
1 2
R502
H_REQ#[0..4]
HD#[0..63]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
CLK_MCH_BCLK#
CLK_MCH_BCLK
+HYSWING
+HXSWING
+HYRCOMP
+HXRCOMP
+HVREF
+HCCVREF
+HAVREF
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HLRCOMP
+HUB_PSWING
+HUB_VREF
AA27
AA28
AB27
AB28
AA26
AD29
AE29
HA#[3..31] <5>
H_REQ#[0..4] <5>
HD#[0..63] <5>
U77A
Montara-GT
P23
HA#3
T25
HA#4
T28
HA#5
R27
HA#6
U23
HA7#
U24
HA#8
R24
HA#9
U28
HA#10
V28
HA#11
U27
HA#12
T27
HA#13
V27
HA#14
U25
HA#15
V26
HA#16
Y24
HA#17
V25
HA#18
V23
HA#19
W25
HA#20
Y25
HA#21
HA#22
W24
HA#23
W23
HA#24
W27
HA#25
Y27
HA#26
HA#27
W28
HA#28
HA#29
Y26
HA#30
HA#31
R28
HREQ#0
P25
HREQ#1
R23
HREQ#2
R25
HREQ#3
T23
HREQ#4
T26
HADSTB#0
HADSTB#1
BCLK#
BCLK
K28
HYSWING
B18
HXSWING
H28
HYRCOMP
B20
HXRCOMP
K21
HDVREF0
J21
HDVREF1
J17
HDVREF2
Y28
HCCVREF
Y22
HAVREF
J28
HDSTBN#0
C27
HDSTBN#1
E22
HDSTBN#2
D18
HDSTBN#3
K27
HDSTBP#0
D26
HDSTBP#1
E21
HDSTBP#2
E18
HDSTBP#3
J25
DINV0#
E25
DINV1#
B25
DINV2#
G19
DINV3#
F15
CPURST#
U7
HL_0
U4
HL_1
U3
HL_2
V3
HL_3
W2
HL_4
W6
HL_5
V6
HL_6
W7
HL_7
T3
HL_8
V5
HL_9
V4
HL_10
W3
HLSTB
V2
HLSTB#
T2
HLRCOMP
U2
PSWING
W1
HLVREF
RG82852GMV_uFCBGA732_MONTARA-GML+
HOST
HUB I/F
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS#0
RS#1
RS#2
K22
H27
K25
L24
J27
G28
L27
L23
L25
J24
H25
K23
G27
K26
J23
H26
F25
F26
B27
H23
E27
G25
F28
D27
G24
C28
B26
G22
C26
E26
G23
B28
B21
G21
C24
C23
D22
C25
E24
D24
G20
E23
B22
B23
F23
F21
C20
C21
G18
E19
E20
G17
D20
F19
C19
C17
F17
B19
G16
E16
C16
E17
D16
C18
L28
M25
N24
M28
N28
N27
P27
M23
N25
P28
M26
N23
P26
M27
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
H_RS#0
H_RS#1
H_RS#2
HXSWING and HYSWING Ref. Voltage
12
R487
301_0402_1%
+HYSWING +HXSWING
1
12
R490
150_0402_1%
C706
0.1U_0402_16V4Z
2
150_0402_1%
Host data Ref. Voltage
+CPU_CORE
12
R491
49.9_0603_1%
12
R492
100_0603_1%
1
C708
1U_0402_6.3V4Z
2
1
C709
0.1U_0402_10V6K
2
Host Address Ref. Voltage
+CPU_CORE
12
R493
49.9_0603_1%
C712
+HAVREF
1
C713
2
0.1U_0402_10V6K
R497
100_0603_1%
12
1U_0402_6.3V4Z
1
2
HUBLink reference Voltage
H_ADS# <5>
H_TRDY# <6>
H_DRDY# <6>
H_DEFER# <5>
H_HITM# <5>
H_HIT# <5>
H_LOCK# <5>
H_BREQ0# <5>
H_BNR# <5>
H_BPRI# <5>
H_DBSY# <6>
H_RS#[0..2]
H_RS#[0..2] <6>
+HUB_PSWING
C716
0.01U_0402_25V7Z
+HUB_VREF
C718
0.01U_0402_25V7Z
+CPU_CORE+CPU_CORE
R489
1.Place R491 and R492 within 0.5" of U77 pin K21 J21 J17
2.Place C708 C709 C710 C711 in order from U77 to divider
3.+HVREF 10mil trace, 20mil space.
R498
100_0603_1%
1
2
1
2
1.Place R487 and R490 within 0.5" of U77 pin K28
2.Place R488 and R489 within 0.5" of U77 pin B18
3.+HYSWING, +HXSWING 10mil trace, 20mil space.
12
R488
301_0402_1%
12
1
C707
0.1U_0402_16V4Z
2
+HVREF
C714
1
C711
@0.1U_0402_10V6K
2
+HCCVREF
1
C715
2
0.1U_0402_10V6K
1
C717
0.1U_0402_10V6K
2
1
C719
0.1U_0402_10V6K
2
1
C710
@0.1U_0402_10V6K
2
+CPU_CORE
12
R494
49.9_0603_1%
12
1
2
1U_0402_6.3V4Z
+1.5VS
12
R499
80.6_0402_1%
12
R500
51.1_0603_1%
12
R501
40.2_0603_1%
Dell-Compal Confidential
Com pal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Monta r a -GT (1/4 )
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
1
of
948Friday, January 09, 2004
1.0
5
4
3
2
1
check spec.
U77B
AGP_AD[0..31]<17>
12
D D
C C
B B
A A
0.1U_0402_10V6K
12
R503
100K_0402_5%
+1.5VS_DVO
R524
@33_0402_5%
C724
@10P_0402_25V8K
DREFSSCLK
RTCCLK<21>
+AGPREF
C720
R504
1@100K_0402_5%
1@100K_0402_5%
12
1
2
12
R526
@33_0402_5%
1
C726
@10P_0402_25V8K
2
AGP_PIPE#<17>
1
2
1@100K_0402_5%
R509
1 2
CLK_MCH_66MCLK_MCH_DISPLAY
AGP_AD[0..31]
AGP_AD14
AGP_AD13
AGP_AD31
12
R505
AGP_AD30
R525
@33_0402_5%
C725
@10P_0402_25V8K
+1.5VS
12
13
D
2
G
S
+1.5VS
12
1
2
AGP_SBA[0..7]<17>
R515
1@1K_0402_5%
Q69
1@BSN20_SOT23
40.2_0603_1%
AGP_PIPE#
AGP_BUSY#<17,21>
12
R518
R528
@1K_0402_5%
1 2
R529
2@1K_0402_5%
1 2
R530
1K_0402_5%
1 2
AGP_CBE#0<17>
AGP_ADSTB0<17>
AGP_ADSTB0#<17>
AGP_CBE#1<17>
AGP_ADSTB1<17>
AGP_ADSTB1#<17>
AGP_IRDY#<17>
AGP_DEVSEL#<17>
AGP_TRDY#<17>
AGP_FRAME#<17>
AGP_STOP#<17>
AGP_CBE#3<17>
AGP_SBA[0..7]
AGP_PAR<17>
R517 1@0_0402_5%
1 2
CLK_MCH_66M<16>
AGP_SBSTB<17>
AGP_SBSTB#<17>
AGP_GNT#<17>
AGP_REQ#<17>
AGP_ST2<17>
AGP_ST1<17>
AGP_ST0<17>
AGP_WBF#<17>
AGP_RBF#<17>
AGP_CBE#2<17>
AGP_ST0
AGP_ST1
R530 wait 533 Celeron
ST2 L : 400 H : 533
5
4
AGP_AD3
AGP_AD2
AGP_AD5
AGP_AD4
AGP_AD7
AGP_AD6
AGP_AD8
AGP_AD10
AGP_AD9
AGP_AD12
AGP_AD11
AGP_AD0
AGP_AD1
AGP_AD14
AGP_AD30
AGP_AD13
AGP_AD17
AGP_AD16
AGP_AD18
AGP_AD31
AGP_AD15
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD25
AGP_AD24
AGP_AD27
AGP_AD26
AGP_AD29
AGP_AD28
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
+AGPREF
CLK_MCH_66M
AGP_ST2
AGP_ST1
AGP_ST0
Q76
2
G
1@2N7002_SOT23
1 3
D
1 2
R583 2@0_0402_5%
AGP_ST2
S
H_BSEL0
<6>
Montara-GT
R3
DVOBD0/GAD3
R5
DVOBD1/GAD2
R6
DVOBD2/GAD5
R4
DVOBD3/GAD4
P6
DVOBD4/GAD7
P5
DVOBD5/GAD6
N5
DVOBD6/GAD8
P2
DVOBD7/GCBE0#
N2
DVOBD8/GAD10
N3
DVOBD9/GAD9
M1
DVOBD10/GAD12
M5
DVOBD11/GAD11
P3
DVOBCLK/GADSTB0
P4
DVOBCLK#/GADSTB0#
T6
DVOBHSYNC/GAD0
T5
DVOBVSYNC/GAD1
L2
DVOBBLANK#/GCBE1#
M2
DVOBFLDSTL/GAD14
G2
DVOBCINTR#/GAD30
M3
DVOBCCLKINT/GAD13
J3
DVOCCLK/GADSTB1
J2
DVOCCLK#/GADSTB1#
K6
DVOCHSYNC/GAD17
L5
DVOCVSYNC/GAD16
L3
DVOCBLANK#/GAD18
H5
DVOCFLDSTL/GAD31
K7
MI2CCLK/GIRDY#
N6
MI2CDATA/GDEVSEL#
N7
MDVICLK/GTRDY#
M6
MDVIDATA/GFRAME#
P7
MDDCCLK/GSTOP#
T7
MDDCDATA/GAD15
K5
DVOCD0/GAD19
K1
DVOCD1/GAD20
K3
DVOCD2/GAD21
K2
DVOCD3/GAD22
J6
DVOCD4/GAD23
J5
DVOCD5/GCBE3#
H2
DVOCD6/GAD25
H1
DVOCD7/GAD24
H3
DVOCD8/GAD27
H4
DVOCD9/GAD26
H6
DVOCD10/GAD29
G3
DVOCD11/GAD28
E5
ADDID0/GSBA0
F5
ADDID1/GSBA1
E3
ADDID2/GSBA2
E2
ADDID3/GSBA3
G5
ADDID4/GSBA4
F4
ADDID5/GSBA5
G6
ADDID6/GSBA6
F6
ADDID7/GSBA7
L7
DVODETECT/GPAR
D5
DPMS/GPIPE#
F1
GVREF
F7
AGPBUSY#
D1
DVO_GRCOMP
Y3
GCLKIN
F2
GSBSTB
F3
GSBSTB#
B2
GGNT#
B3
GREQ#
C2
GST2
C3
GST1
C4
GST0
D2
GWBF#
D3
GRBF#
L4
GCBE#2
D7
RSVD1
AA5
RSVD2
RG82852GMV_uFCBGA732_MONTARA-GML+
PANELBKLTCTL
PANELBKLTEN
PANELVDDEN
DVO
CLKS
MISCNC
DAC
DDCADATA
DDCPDATA
DREFSSCLK
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
HSYNC
VSYNC
REFSET
DDCACLK
IYAM0
IYAM1
IYAM2
IYAM3
IYAP0
IYAP1
IYAP2
IYAP3
IYBM0
IYBM1
IYBM2
IYBM3
IYBP0
IYBP1
IYBP2
IYBP3
LVDS
ICLKAM
ICLKAP
ICLKBM
ICLKBP
DDCPCLK
LIBG
RSVD3
RSVD4
RSVD5
DREFCLK
LCLKCTLA
LCLKCTLB
DPWR#
DPSLP#
RSTIN#
PWROK
EXTTS0
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
C9
D9
C8
D8
A7
A8
H10
J9
E8
B6
G9
G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
D14
E13
E10
F10
LCD_DDCCLK
B4
LCD_DDCDATA
C5
G8
PANEL_BKEN
F8
A5
A10
D12
F12
B12
CLK_M CH_DISPLAY
B7
DREFSSCLK
B17
H9
C6
AA22
Y23
AD28
J11
D6
B1
AH1
A2
AJ2
A28
AJ28
A29
B29
AH29
AJ29
AA9
AJ4
H_DPSLP#
CLK_VCH<16>
INTCRT_B <17>
INTCRT_G <17>
INTCRT_R <17>
INT_HSYNC <17>
INT_VSYNC <17>
INTDDCCK <17>
INTDDCDA <17>
LCD_A0- <18>
LCD_A1- <18>
LCD_A2- <18>
LCD_A0+ <18>
LCD_A1+ <18>
LCD_A2+ <18>
LCD_B0- <18>
LCD_B1- <18>
LCD_B2- <18>
LCD_B0+ <18>
LCD_B1+ <18>
LCD_B2+ <18>
LCD_ACLK- <18>
LCD_ACLK+ <18>
LCD_BCLK- <18>
LCD_BCLK+ <18>
LCD_DDCCLK <18>
LCD_DDCDATA <18>
R511 1@0_0402_5%
1 2
R512 1@1.5K_0603_1%
1 2
CLK_MCH_DISPLAY <16>
LCLKCTLB
PSB Voltage Select
H_DPSLP# <6,20>
PCIRST# <6,17,20,24,25,27,28,32,35>
PM_PWROK <21,32,34>
R516 10K_0603_1%
1 2
R521 @1K_0402_5%
1 2
R522 @1K_0402_5%
1 2
FS2 FS1
0 0
0 1
1 0
*
1 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
R506 pop 137_0603_1% for GML
p/n: SD014137000
pop 127_0603_1% for GMV
p/n: SD014127000
R506
1 2
1@127_0603_1%
LCD_DDCCLK
LCD_DDCDATA
H_DPSLP#
@56 _0402_1%
ENABKL <17,18,33>
ENVDD <18>
+3VS
R514
1K_0402_5%
1 2
LCLKCTLB H:1.2V
+3VS
1
7
8
R519 0_0402_5%
+SVDD
U78
X1/CLK
FS1
FS2
28< <38
38< <48
46< <60
58< <75
2
+3VS
R507
1 2
2.2K_0402_5%
R508
1 2
2.2K_0402_5%
R570
@0.1U_0402_10V6K
1 2
6
VDD
CLKOUT
GND
@W181G_SOIC8
3
+CPU_CORE
12
C721
pop R570 for
DT CPU
C722
@4.7U_0805_6.3V6K
1
2
1
2
11/12 EMI change to W181-51
R520 @22_0402_5%
1 2
R523
1 2
12
@1K_0402_5%
R527
@1K_0402_5%
SS% L : -0.625%< <0.625%
SS%
SSVCH_OUTCLK_VCH
5
2
X2
4
L41
@FCM2012C-800_0805
1 2
C723
1
@0.1U_0402_10V6K
2
DREFSSCLK
+SVDD
SS% H : -1.875%< <1.875%
Com pal Electronics, Inc.
Title
Monta r a -GT (2/4 )
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
1
+3VS+SVDD
1.0
of
10 48Friday, January 09, 2004
5
4
3
2
1
D D
DDR_SDQS[0..7]<13>
C C
B B
DDR_SDM[0..7]<13>
A A
DDR_SMA[0..12]
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SDQS[0..7]
DDR_SWE#<13,14>
DDR_SRAS#<13,14>
DDR_SCAS#<13,14>
DDR_CLK0<13>
DDR_CLK0#<13>
DDR_CLK1<13>
DDR_CLK1#<13>
DDR_CLK2<13>
DDR_CLK2#<13>
DDR_CLK3<14>
DDR_CLK3#<14>
DDR_CLK4<14>
DDR_CLK4#<14>
DDR_CLK5<14>
DDR_CLK5#<14>
DDR_CKE0<13>
DDR_CKE1<13>
DDR_CKE2<14>
DDR_CKE3<14>
DDR_SCS#0<13>
DDR_SCS#1<13>
DDR_SCS#2<14>
DDR_SCS#3<14>
DDR_SBS0<13,14>
DDR_SBS1<13,14>
DDR_SDM[0..7]
DDR_SMAB1<14>
DDR_SMAB2<14>
DDR_SMAB4<14>
DDR_SMAB5<14>
Need place Via as closed as pin.
+SMRCOMP
+SMVSWINGL
+SMVSWINGH
DDR_SMA12
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SWE#
DDR_SRAS#
DDR_SCAS#
DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK2
DDR_CLK2#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_CLK5
DDR_CLK5#
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_SBS0
DDR_SBS1
DDR_SDM0
DDR_SDM1
DDR_SDM2
DDR_SDM3
DDR_SDM4
DDR_SDM5
DDR_SDM6
DDR_SDM7
DDR_SMAB1
DDR_SMAB2
DDR_SMAB4
DDR_SMAB5
U77C
AC18
AD14
AD13
AD17
AD11
AC13
AD8
AD7
AC6
AC5
AC19
AD5
AB5
AG2
AH5
AH8
AE12
AH17
AE21
AH24
AH27
AD15
AD25
AC21
AC24
AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4
AC7
AB7
AC9
AC10
AD23
AD26
AC22
AC25
AD22
AD20
AE5
AE6
AE9
AH12
AD19
AD21
AD24
AH28
AH15
AD16
AC12
AF11
AD10
AC15
AC16
AB1
AJ22
AJ19
Montara-GT
SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SWE#
SRAS#
SCAS#
SCK0
SCK0#
SCK1
SCK1#
SCK2
SCK2#
SCK3
SCK3#
SCK4
SCK4#
SCK5
SCK5#
SCKE0
SCKE1
SCKE2
SCKE3
SCS#0
SCS#1
SCS#2
SCS#3
SBA0
SBA1
SDM0
SDM1
SDM2
SDM3
SDM4
SDM5
SDM6
SDM7
SDM8
SMAB1
SMAB2
SMAB4
SMAB5
RCVENOUT#
RCVENIN#
SMRCOMP
SMVSWINGL
SMVSWINGH
RG82852GMV_uFCBGA732_MONTARA-GML+
MEMORY
SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71
SMVREF0
DDR_SDQ0
AF2
DDR_SDQ1
AE3
DDR_SDQ2
AF4
DDR_SDQ3
AH2
DDR_SDQ4
AD3
DDR_SDQ5
AE2
DDR_SDQ6
AG4
DDR_SDQ7
AH3
DDR_SDQ8
AD6
DDR_SDQ9
AG5
DDR_SDQ10
AG7
DDR_SDQ11
AE8
DDR_SDQ12
AF5
DDR_SDQ13
AH4
DDR_SDQ14
AF7
DDR_SDQ15
AH6
DDR_SDQ16
AF8
DDR_SDQ17
AG8
DDR_SDQ18
AH9
DDR_SDQ19
AG10
DDR_SDQ20
AH7
DDR_SDQ21
AD9
DDR_SDQ22
AF10
DDR_SDQ23
AE11
DDR_SDQ24
AH10
DDR_SDQ25
AH11
DDR_SDQ26
AG13
DDR_SDQ27
AF14
DDR_SDQ28
AG11
DDR_SDQ29
AD12
DDR_SDQ30
AF13
DDR_SDQ31
AH13
DDR_SDQ32
AH16
DDR_SDQ33
AG17
DDR_SDQ34
AF19
DDR_SDQ35
AE20
DDR_SDQ36
AD18
DDR_SDQ37
AE18
DDR_SDQ38
AH18
DDR_SDQ39
AG19
DDR_SDQ40
AH20
DDR_SDQ41
AG20
DDR_SDQ42
AF22
DDR_SDQ43
AH22
DDR_SDQ44
AF20
DDR_SDQ45
AH19
DDR_SDQ46
AH21
DDR_SDQ47
AG22
DDR_SDQ48
AE23
DDR_SDQ49
AH23
DDR_SDQ50
AE24
DDR_SDQ51
AH25
DDR_SDQ52
AG23
DDR_SDQ53
AF23
DDR_SDQ54
AF25
DDR_SDQ55
AG25
DDR_SDQ56
AH26
DDR_SDQ57
AE26
DDR_SDQ58
AG28
DDR_SDQ59
AF28
DDR_SDQ60
AG26
DDR_SDQ61
AF26
DDR_SDQ62
AE27
DDR_SDQ63
AD27
AG14
AE14
AE17
AG16
AH14
AE15
AF16
AF17
SMVREF0
AJ24
C728
0.1U_0402_10V6K
+2.5V
TOPOLOGY 2 FOR DDR
SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
12
R537
@10K_0603_1%
12
1
2
DDR_SDQ[0..63]
R540
@10K_0603_1%
R539
1 2
0_0603_5%
DDR_SDQ[0..63] <13>DDR_SMA[0..12]<13,14>
+2.5V
12
R531
604_0603_1%
+SMVSWINGL
+SMRCOMP
60.4_0603_1%
+SMVSWINGH
SDREF
R534
12
R532
150_0603_1%
+2.5V
12
R533
60.4_0603_1%
12
0.1U_0402_10V6K
+2.5V
12
R535
150_0603_1%
12
R536
604_0603_1%
C727
1
2
Dell-Compal Confidential
Com pal Electronics, Inc.
Title
Monta r a -GT (3/4 )
Size Do cum e nt Number R e v
Ibiza LA-1684
2
Dat e : Sheet
11 48Friday, January 09, 2004
1
1.0
of
5
U77D
C1
VSS0
G1
VSS1
L1
VSS2
U1
VSS3
AA1
VSS4
AE1
VSS5
R2
VSS6
D D
C C
B B
A A
AG3
VSS7
AJ3
VSS8
D4
VSS9
G4
VSS10
K4
VSS11
N4
VSS12
T4
VSS13
W4
VSS14
AA4
VSS15
AC4
VSS16
AE4
VSS17
B5
VSS18
U5
VSS19
Y5
VSS20
Y6
VSS21
AG6
VSS22
C7
VSS23
E7
VSS24
G7
VSS25
J7
VSS26
M7
VSS27
R7
VSS28
AA7
VSS29
AE7
VSS30
AJ7
VSS31
H8
VSS32
K8
VSS33
P8
VSS34
T8
VSS35
V8
VSS36
Y8
VSS37
AC8
VSS38
E9
VSS39
L9
VSS40
N9
VSS41
R9
VSS42
U9
VSS43
W9
VSS44
AB9
VSS45
AG9
VSS46
C10
VSS47
J10
VSS48
AA10
VSS49
AE10
VSS50
D11
VSS51
F11
VSS52
H11
VSS53
AB11
VSS54
AC11
VSS55
AJ11
VSS56
J12
VSS57
AA12
VSS58
AG12
VSS59
A13
VSS60
D13
VSS61
F13
VSS62
H13
VSS63
N13
VSS64
R13
VSS65
U13
VSS66
AB13
VSS67
AE13
VSS68
J14
VSS69
P14
VSS70
T14
VSS71
AA14
VSS72
AC14
VSS73
D15
VSS74
H15
VSS75
N15
VSS76
R15
VSS77
U15
VSS78
AB15
VSS79
AG15
VSS80
F16
VSS81
J16
VSS82
P16
VSS83
T16
VSS84
AA16
VSS85
AE16
VSS86
A17
VSS87
D17
VSS88
H17
VSS89
N17
VSS90
RG82852GMV_uFCBGA732_MONTARA-GML+
Montara-GT
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
R17
U17
AB17
AC17
F18
J18
AA18
AG18
A19
D19
H19
AB19
AE19
F20
J20
AA20
AC20
A21
D21
H21
M21
P21
T21
V21
Y21
AA21
AB21
AG21
B24
F22
J22
L22
N22
R22
U22
W22
AE22
A23
D23
AA23
AC23
AJ23
F24
H24
K24
M24
P24
T24
V24
AA24
AG24
A25
D25
AA25
AE25
G26
J26
L26
N26
R26
U26
W26
AB26
A27
F27
AC27
AG27
AJ27
AC28
AE28
C29
E29
G29
J29
L29
N29
U29
W29
AA29
AJ10
AJ12
AJ18
AJ20
C22
D28
E28
L6
T9
AJ26
AJ1
4
C807
1
0.1U_0402_10V6K
+1.5VS
1
2
2
C808
0.1U_0402_10V6K
KC F BM-L11-201209-221LMAT_0805
L42
1 2
CLOSE TO PIN
C740
220U_D2_4VM
1 2
KC F BM-L11-201209-221LMAT_0805
C758
@220U_D2_4VM
1@22U_1210_6.3V6M
L43
+1.5VS
12
L44
FLM1608081R8K_0603
1
0.01U_0402_25V7Z
1
+
2
2
C759
0.1U_0402_10V6K
1
C769
2
L46
1 2
FLM1608081R8K_0603
C775
0.1U_0402_10V6K
L49
1 2
FLM1608081R8K_0603
1@22U_1210_6.3V6M
220U_D2_4VM
+1.5VS_DLVDS
C782
C730
1
150U_D2_6.3VM
+
2
C729
150U_D2_6.3VM
+VCCADPLLA
1
+
0.1U_0402_10V6K
2
+VCCADPLLB
1
+
C750
2
0.1U_0402_10V6K
C749
+1.5VS_DAC
C760
1
2
1
C770
1@22U_1210_6.3V6M
2
1
0.01U_0402_25V7Z
2
1
2
1
1
+
2
2
C731
10U_1206_6.3V7K
1
C741
2
1
2
C752
0.1U_0402_10V6K
+1.5VS
L45
BLM21A601SPT_0805
1 2
C814
0.1U_0402_10V6K
C817
0.1U_0402_10V6K
1 2
FLM1608081R8K_0603
1
C776
2
C783
1@10U_1206_6.3V7K
1
1
2
2
C784
0.1U_0402_10V6K
CLOSE TO VCC
C732
0.1U_0402_10V6K
+1.5VS
1
0.1U_0402_10V6K
2
1
C761
150U_D2_6.3VM
2
1
2
0.1U_0402_10V6K
L47
0.1U_0402_10V6K
1
2
C786
0.1U_0402_10V6K
1
2
C733
0.1U_0402_10V6K
C743
10U_1206_6.3V7K
1
C753
2
1
+
2
1
C818
2
C777
0.1U_0402_10V6K
C785
+2.5V_TXLVDS+2.5V
1
2
1
2
0.1U_0402_10V6K
1
2
10U_1206_6.3V7K
3
C734
0.1U_0402_10V6K
1
1
2
C735
2
0.1U_0402_10V6K
CLOSE TO VCCHL
C745
0.1U_0402_10V6K
C744
1
1
2
2
C811
0.1U_0402_10V6K
+1.5VS
+1.5VS_DVO
C763
1
1
0.1U_0402_10V6K
2
C762
C819
0.1U_0402_10V6K
+1.5VS_DLVDS+1.5VS+1.5VS_ALVDS+1.5VS
+3VS
2
0.1U_0402_10V6K
1
+1.5VS_DAC
2
+1.5VS_ALVDS
+1.5VS_DLVDS
1
2
+2.5V_TXLVDS
R541
0_0603_5%
1 2
C780
@10U_1206_6.3V7K
+1.5VS
1
2
+VCCADPLLA
+VCCADPLLB
1
2
C764
+VCC_GPIO
1
0.1U_0402_10V6K
2
2
+CPU_CORE
U77E
Montara-GT
J15
VCC0
P13
VCC1
T13
VCC2
N14
VCC3
R14
VCC4
U14
VCC5
P15
VCC6
T15
VCC7
AA15
VCC8
N16
VCC9
R16
VCC10
U16
VCC11
P17
VCC12
T17
VCC13
AA17
VCC14
AA19
VCC15
W21
VCC16
H14
VCC17
V1
VCCHL0
Y1
VCCHL1
W5
VCCHL2
U6
VCCHL3
U8
VCCHL4
W8
VCCHL5
V7
VCCHL6
V9
VCCHL7
D29
VCCAHPLL
Y2
VCCAGPLL
A6
VCCADPLLA
B16
VCCADPLLB
E1
VCCDVO_0
J1
VCCDVO_1
N1
VCCDVO_2
E4
VCCDVO_3
J4
VCCDVO_4
M4
VCCDVO_5
E6
VCCDVO_6
H7
VCCDVO_7
J8
VCCDVO_8
L8
VCCDVO_9
M8
VCCDVO_10
N8
VCCDVO_11
R8
VCCDVO_12
K9
VCCDVO_13
M9
VCCDVO_14
P9
VCCDVO_15
A9
VCCADAC0
B9
VCCADAC1
B8
VSSADAC
A11
VCCALVDS
B11
VSSALVDS
G13
VCCDLVDS0
B14
VCCDLVDS1
J13
VCCDLVDS2
B15
VCCDLVDS3
F9
VCCTXLVDS0
B10
VCCTXLVDS1
D10
VCCTXLVDS2
A12
VCCTXLVDS3
A3
VCCGPIO_0
A4
1
2
VCCGPIO_1
C781
RG82852GMV_uFCBGA732_MONTARA-GML+
POWER
VTTLF0
VTTLF1
VTTLF2
VTTLF3
VTTLF4
VTTLF5
VTTLF6
VTTLF7
VTTLF8
VTTLF9
VTTLF10
VTTLF11
VTTLF12
VTTLF13
VTTLF14
VTTLF15
VTTLF16
VTTLF17
VTTLF18
VTTLF19
VTTLF20
VTTHF0
VTTHF1
VTTHF2
VTTHF3
VTTHF4
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCQSM0
VCCQSM1
VCCASM0
VCCASM1
G15
H16
H18
J19
H20
L21
N21
R21
U21
H22
M22
P22
T22
V22
Y29
K29
F29
AB29
A26
A20
A18
A22
A24
H29
M29
V29
AC1
AG1
AB3
AF3
Y4
AJ5
AA6
AB6
AF6
Y7
AA8
AB8
Y9
AF9
AJ9
AB10
AA11
AB12
AF12
AA13
AJ13
AB14
AF15
AB16
AJ17
AB18
AF18
AB20
AF21
AJ21
AB22
AF24
AJ25
AF27
AC29
AF29
AG29
0.1U_0402_10V6K
AJ6
AJ8
VCC_ASM
AD1
AF1
C787
0.1U_0402_10V6K
C737
0.1U_0402_10V6K
+2.5V
C754
0.1U_0402_10V6K
C765
0.1U_0402_10V6K
100U_D2_6.3VM
C778
C738
0.1U_0402_10V6K
1
2
1
2
1
2
1
C771
2
1
2
1
2
1
2
10U_1206_6.3V7K
0.1U_0402_10V6K
1
C809
2
0.1U_0402_10V6K
C742 0.1U_0402_16V4Z
1 2
C746 0.1U_0402_16V4Z
1 2
C747 0.1U_0402_16V4Z
1 2
C748 0.1U_0402_16V4Z
1 2
C751 0.1U_0402_16V4Z
1 2
C755
0.1U_0402_10V6K
1
2
C756
0.1U_0402_10V6K
C766
0.1U_0402_10V6K
1
2
C767
0.1U_0402_10V6K
C771 & C772 change to 100u
next Reversion
1
+
C772
+
100U_D2_6.3VM
2
L48
1 2
1
KC F BM-L11-201209-221LMAT_0805
C779
4.7U_1206_10V7K
2
1
2
L50
1 2
KC F BM-L11-201209-221LMAT_0805
+
C788
100U_D2_6.3VM
1
2
C739
1
C810
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
2
1
C773
0.1U_0402_10V6K
2
1
1
+
C736
150U_D2_6.3VM
2
C757
0.1U_0402_10V6K
1
2
C768
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C774
2
0.1U_0402_10V6K
R16
0_0805_5%
1 2
1
C812
2
0.1U_0402_10V6K
1
C815
2
0.1U_0402_10V6K
1
C820
2
0.1U_0402_10V6K
+2.5V+2.5V_QSM
+1.5VS
1
C813
2
1
C816
2
1
C821
2
Dell-Compal Confidential
Com pal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Montara-GT(4/4)
Size Do cum e nt Number R e v
Ibiza LA-1684
Dat e : Sheet
1
of
12 48Friday, January 09, 2004
1.0
A
RP32 10_4P2R_0402_5%
DDR_SDQ1
DDR_SDQ4
DDR_SDQ2
DDR_SDQ5
DDR_SDQ6
1 1
2 2
3 3
4 4
DDR_SDQ0
DDR_SDQ7
DDR_SDQ3
DDR_SDQ12 DDR_DQ12
DDR_SDQ8
DDR_SDQ9 DDR_DQ9
DDR_SDQ13
DDR_SDQ11 DDR_DQ11
DDR_SDQ14 DDR_DQ14
DDR_SDQ15
DDR_SDQ10
DDR_SDQ21
DDR_SDQ20
DDR_SDQ16 DDR_DQ16
DDR_SDQ23 DDR_DQ23
DDR_SDQ18
DDR_SDQ29 DDR_DQ29
DDR_SDQ28
DDR_SDQ25 DDR_DQ25
DDR_SDQ24
DDR_SDQ57
DDR_SDQ61
DDR_SDQ60 DDR_DQ60
DDR_SDQ56
DDR_SDQ63
DDR_SDQ58 DDR_DQ58
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
1 4
2 3
RP42 10_4P2R_0402_5%
1 4
2 3
RP33 10_4P2R_0402_5%
1 4
2 3
RP43 10_4P2R_0402_5%
1 4
2 3
RP20 10_4P2R_0402_5%
1 4
2 3
RP31 10_4P2R_0402_5%
1 4
2 3
RP21 10_4P2R_0402_5%
1 4
2 3
RP40 10_4P2R_0402_5%
1 4
2 3
RP41 10_4P2R_0402_5%
1 4
2 3
RP35 10_4P2R_0402_5%
1 4
2 3
RP44 10_4P2R_0402_5%
1 4
2 3
RP34 10_4P2R_0402_5%
1 4
2 3
RP45 10_4P2R_0402_5%
1 4
2 3
RP38 10_4P2R_0402_5%
1 4
2 3
DDR_SDQ[0..63]<11>
DDR_SDQS[0..7]<11>
DDR_SMA[0..12]<11,14>
DDR_SDM[0..7]<11>
RP51 10_4P2R_0402_5%
1 4
2 3
RP50 10_4P2R_0402_5%
1 4
2 3
RP36 10_4P2R_0402_5%
1 4
2 3
R124 10_0402_5%
R109 10_0402_5%
R120 10_0402_5%
R121 10_0402_5%
A
DDR_DQ1
DDR_DQ4
DDR_DQ2
DDR_DQ5
DDR_DQ6
DDR_DQ0
DDR_DQ7
DDR_DQ3
DDR_DQ8
DDR_DQ13
DDR_DQ15
DDR_DQ10
DDR_DQ21
DDR_DQ20
DDR_DQ17DDR_SDQ17
DDR_DQ18
DDR_DQ19DDR_SDQ19
DDR_DQ22DDR_SDQ22
DDR_DQ28
DDR_DQ24
DDR_SDQ[0..63]
DDR _ S DQS[0..7]
DDR_SMA[0..12]
DDR_SDM[0..7]
DDR_DQ57
DDR_DQ61
DDR_DQ56
DDR_DQ63 DDR_SDQ62 DDR_DQ62
DDR_DQS0
12
DDR_DQS1
12
DDR_DQS2
12
DDR_DQS3
12
B
RP46 10_4P2R_0402_5%
DDR_SDQ26 DDR_DQ26
DDR_SDQ31 DDR_DQ31
DDR_SDQ27
DDR_SDQ30
DDR_SDM0
DDR_SDM1
DDR_SDM2 DDR_DM2
DDR_SDM3
DDR_SDM4 DDR_DM4
DDR_SDM5
DDR_SDM6 DDR_DM6
DDR_SDM7
DDR_SDQ32 DDR_DQ32
DDR_SDQ33
DDR_SDQ37 DDR_DQ37
DDR_SDQ36
DDR_SDQ39
DDR_SDQ34
DDR_SDQ35
DDR_SDQ38
DDR_SDQ45
DDR_SDQ44
DDR_SDQ40
DDR_SDQ41
DDR_SDQ47
DDR_SDQ46
DDR_SDQ42
DDR_SDQ43
DDR_SDQ49
DDR_SDQ52
DDR_SDQ48
DDR_SDQ53
DDR_SDQ51
DDR_SDQ50
DDR_SDQ54 DDR_DQ54
DDR_SDQ59
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
B
1 4
2 3
RP37 10_4P2R_0402_5%
1 4
2 3
R119 10_0402_5%
R117 10_0402_5%
R126 10_0402_5%
R127 10_0402_5%
R114 10_0402_5%
R113 10_0402_5%
R107 10_0402_5%
R118 10_0402_5%
RP16 10_4P2R_0402_5%
1 4
2 3
RP28 10_4P2R_0402_5%
1 4
2 3
RP26 10_4P2R_0402_5%
1 4
2 3
RP15 10_4P2R_0402_5%
1 4
2 3
RP27 10_4P2R_0402_5%
1 4
2 3
RP17 10_4P2R_0402_5%
1 4
2 3
RP29 10_4P2R_0402_5%
1 4
2 3
RP22 10_4P2R_0402_5%
1 4
2 3
RP30 10_4P2R_0402_5%
1 4
2 3
RP18 10_4P2R_0402_5%
1 4
2 3
RP25 10_4P2R_0402_5%
1 4
2 3
RP23 10_4P2R_0402_5%
1 4
2 3
RP39 10_4P2R_0402_5%
1 4
2 3
R108 10_0402_5%
R106 10_0402_5%
R115 10_0402_5%
R129 10_0402_5%
C
DDR_DQ27
DDR_DQ30
DDR_DM0
12
DDR_DM1
12
12
DDR_DM3
12
DDR_CLK0<11>
12
DDR_DM5
12
12
DDR_DM7
12
DDR_DQ33
DDR_DQ36
DDR_DQ39
DDR_DQ34
DDR_DQ35
DDR_DQ38
DDR_DQ45
DDR_DQ44
DDR_DQ40
DDR_DQ41
DDR_DQ47
DDR_DQ46
DDR_DQ42
DDR_DQ43
DDR_DQ49
DDR_DQ52
DDR_DQ48
DDR_DQ53
DDR_DQ51
DDR_DQ50
DDR_DQ55DDR_SDQ55
DDR_DQ59
DDR_DQS4
12
DDR_DQS5
12
DDR_DQS6
12
DDR_DQS7
12
C
DDR_CLK0#<11>
DDR_CLK2<11>
DDR_CLK2#<11>
DDR_CKE1<11> DDR_CKE0 <11>
DIMM_SMDATA<14,16,20,28>
Layout note
Place these resistors
close to DIMM0,
all trace length<500 mil
DDR TOPOLOGY 2 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
D
+2.5V
JP22
1
VREF
3
DDR_DQ5
DDR_DQ2
DDR_DQS0
DDR_DQ0
DDR_DQ6
DDR_DQ8
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ20 DDR_DQ16
DDR_DQ21 DDR_DQ17
DDR_DQS2
DDR_DQ18
DDR_DQ23 DDR_DQ19
DDR_DQ28
DDR_DQS3
DDR_DQ31
DDR_DQ26
DDR_CKE1 DDR_CKE0
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMA5
DDR_SMAA3
DDR_SMA1
DDR_SMAA10
DDR_BS0
DDR_WE#
DDR_SCS#0 DDR_SCS#1
DDR_DQ37
DDR_DQS4
DDR_DQ34
DDR_DQ44
DDR_DQ45
DDR_DQS5
DDR_DQ46
DDR_DQ47
DDR_DQ52
DDR_DQ49
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ56
DDR_DQ60
DDR_DQS7
DDR_DQ58
DDR_DQ63
DIMM_SMCLK<14,16,20,28>
+3VS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
JAE MM50-200B1-1R_200P_Reverse
E
E
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
BA1
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
SA0
196
SA1
198
SA2
200
DU
+2.5V
F
DDR_DQ4
DDR_DQ1
DDR_DM0
DDR_DQ3
DDR_DQ7
DDR_DQ13
DDR_DQ9DDR_DQ12
DDR_DM1
DDR_DQ10
DDR_DQ15
DDR_DM2
DDR_DQ22
DDR_DQ24
DDR_DQ25DDR_DQ29
DDR_DM3
DDR_DQ30
DDR_DQ27
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMA4
DDR_SMA2
DDR_SMAA0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_DQ33DDR_DQ36
DDR_DQ32
DDR_DM4
DDR_DQ38
DDR_DQ35DDR_DQ39
DDR_DQ41
DDR_DQ40
DDR_DM5
DDR_DQ43
DDR_DQ42
DDR_DQ53
DDR_DQ48
DDR_DM6
DDR_DQ55
DDR_DQ54
DDR_DQ61
DDR_DQ57
DDR_DM7
DDR_DQ59
DDR_DQ62
F
SDREF_DIMM
1
C413
0.1U_0402_16V4Z
2
DDR_SCS#1 <11>DDR_SCS#0<11>
DDR_CLK1# <11>
DDR_CLK1 <11>
R322
0_0402_5%
G
12
SDREF
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
R167 10_0402_5%
R149 10_0402_5%
R152 10_0402_5%
R116 10_0402_5%
R137 10_0402_5%
R148 10_0402_5%
R146 10_0402_5%
R151 10_0402_5%
R136 10_0402_5%
DDR_DQ[0..63] <14>
DDR_DQS[0..7] <14>
DDR_DM[0..7] <14>
DDR_SMAA0DDR_SMA0
12
DDR_SMAA3DDR_SMA3
12
DDR_SMAA6DDR_SMA6
12
DDR_SMAA7DDR_SMA7
12
DDR_SMAA8DDR_SMA8
12
DDR_SMAA9DDR_SMA9
12
DDR_SMAA10DDR_SMA10
12
DDR_SMAA11DDR_SMA11
12
DDR_SMAA12DDR_SMA12
12
Layout note
Place these resistor
close by DIMM0,
all trace length
Max=1.4"
+1.25VS
DDR_CKE0
DDR_CKE1
DDR_SCS#1
DDR_SCS#0
DDR_SBS0<11,14>
DDR_SBS1<11,14>
DDR_SRAS#<11,14>
DDR_SCAS#<11,14>
DDR_SWE#<11,14>
RP47
1 4
2 3
56_4P2R_0402_5%
RP49
1 4
2 3
56_4P2R_0402_5%
R139 10_0402_5%
R133 10_0402_5%
R141 10_0402_5%
R131 10_0402_5%
R138 10_0402_5%
12
12
12
12
12
Dell- C o m p a l C onfidential
Compa l Electronics, Inc.
Title
DDR-SODIMM SLOT0
Size Docu ment Number Re v
Ibiza LA - 1684
Date: Sheet
G
H
DDR_BS0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_WE#
13 48Friday, January 09, 2004
H
1.0
of
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