Compal LA-1521-REV Schematics
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SHANGHAI 100
BTK20 LA-1521 Schematics Document
2 2
REV 1.0A
PVT2
INTEL Mobile P4 uFCBGA/uFCPGA Northwood Celeron
3 3
4 4
A
MCH-M(845MZ) + ICH3-M + M6-C(16MB VRAM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Compal Electronics, inc.
Title
Size Docu ment Number Re v
Custom
Date: Sheet
401229
星期一 十一
SCHEM A T IC, M/B LA-1521
04, 2002
月
E
143,
of
1B
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SHANGHAI 100
BTK20 LA-1521 BLOCK DIAGRAM
4 4
Inte l Mobile
CRT
Connector
PAGE 19
Northwood
Celeron
(uFCBGA/uFCPGA)
PSB
PAGE 4,5,6
400MHz
Thermal S ensor
MAX6654MEE
NE1617
PAGE 5
Clock Generator
W320-04
ICS9508-05
PAGE13
CPU VID
PAGE 6
TFT LCD
3 3
2 2
Connector
RJ-45
PAGE 20
Slot 0/1
PAGE 26
PAGE 18
AGP
ATI M6-C
(VRAM DDR 16MB)
PAGE 14,15,16,17
TV-OUT
Connector
PAGE 19
LAN
RTL8100BL
CARDBUS
OZ6933B
PAGE 24
PAGE 25,26
AGP Bus
Super I/O
LPC47N227
REV B
33MHz (3.3V)
PAGE 27
PCI BUS
Brookdale-M
MCH-M 845MZ
593 FC-BGA
266MHz (1.8V)
ICH3-M
LPC BUS 3 3MHz (3.3V)
Embedded
Controller
NS PC87591S
REV B1
PAGE 7,8,9
HUB
421 BGA
REV B1
PAGE 20,21,22
PAGE 33
200MHz (2.5V)
Memory Bus
48MHz (3.3V)
ATA 66/100
AC-LINK24.576MHz (3.3V)
SO-DI M M x 2(DDR)
BANK 0,1,2,3
USB
Slot 0/1/3
PAGE 29
IDE HDD
PAGE 23
AC97 CODEC
ALC202
MDC
PAGE 30
PAGE 28
PAGE 10,11
CD-ROM/DVD
Aud i o A m p lifier
TPA0132
RJ-11
PAGE 20
PAGE 31
FANController
PAGE 34
DC/DC Interface
PAGE 37
BATTERY
Charger
PAGE 38
Power Interface &
TEMP. sensing circuit
PAGE 37,38,39,40,42
Parallel
1 1
A
PAGE 28
FDD
PAGE 19 PAGE 33
B
PAGE 34
BIOS & I/O PORTScan KB
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
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Title
Size Docu ment Number Re v
Custom
Date: Sheet
SCHEM A T IC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
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1B
of
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Voltage Rails
Power Plane Description
VIN
B+
1 1
+CPU_CORE
1.2VP
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2VP switched power rail for CPU VID
+1.25VS 1.25VS power rail ON OFF OFF
+1.5VS
AGP 4X ON OFF OFF
+1.8VALW 1.8V always power rail ON ON
+1.8VS
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW
+3V
+3VS
+5VALW
+5V
+5VS
+12VALW
+12V
2 2
+12VS
RTCVCC
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail ON
12V power rail
12V switched power rail
RTC power
+SDREF
Note : "ON*" means that this power plane is "ON" only with AC power available, otherwise it is "OFF".
S1 S3 S5
N/A N/A N/A
ON O F F
ON O F F
OFF1.8V switched power rail ON
ON+2.5V 2.5V power rail OFFON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
ON+SDREF power
N/AN/AN/A
OFF
OFF
ON*
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON
OFF
PIR
REV 0.1 (EVT/DVT PHASE)
Date Description
07/06 2002 ADD R441,R442 AND C622 FOR "+AGP_REF"
07/06 2002
07/06 2002 16
07/06 2002
07/06 2002
07/06 2002
07/12 2002
07/12 2002
07/12 2002 33 U pdate EC BOARD ID: 001 for PVT1.(Remove R331, Add R327)
REV 0.2 (PVT1 PHASE)
Date Page
07/26 2002
07/26 2002
Page
07
14
Change R137 Pin2 power name from "+AGP_NBREF" to "+AGP_VGAREF" for can't boot issue.
Change R181 Pin2 power plane from "+2.5V" to "+2.5V_VGA" for leakage.
DEL R43,R255,R40 and J1.07/06 2002 17
ADD Q4 7 FOR LAN POWER "+2.5VLAN".07/06 2002 24
ADD Q48 and Q49 FOR LAN Layout Rule.
JP8 Pin25 Create "FDD_READY#" for W/O FDD (GI BTO).2707/06 2002
3007/06 2002 Change R122 to 10K, R121 to 2.4K for MDC Noise.
Change R340 to 100K_1%, R347 to 33K_1% for Back-Grand Noise.
Change R159 to 0, C220 to 0 for Vendor(Realtek) Recommend.
3207/06 2002 ADD R443, JP22 FOR EC JTAG Connector.
34
Change JP5 form 20pins to 26pins type.
36 DEL R352,R277,R243,R287,R301 and R355.
37
Change PR 15 pin2 power name form " +2.5VREF" to "2.5REF"
ADD Q50,Q51,Q52,R445 and R446 for "H_THERMTRIP#" Function.
05
39 ADD PF3 for "NA" of Battery type.
Description
0507/26 2002
Improved Q50,Q51,Q52,R445 and R446 for "H_THERMTRIP#" Function.
Change R446 pin1 power from "+5VS" to "+CPU_CORE"
Change R445 pin1 power from "+5VS" to "+5V"
24
Update BOM by DEL Q47, ADD R106 for LAN unstable.
33
Update EC BOARD ID: 011 for PVT2.(Remove R325, Add R324)
REV 1.0
DescriptionDate
Update EC BOARD ID Description :EC_BID 2 < - > E C_BID0.3307/30 2002
DescriptionDate
Exter n al PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus
AD20
LAN AD17 3 PIRQB
2
Page
REV 1.0A (PVT 2 PHASE)
Page
PIRQ A/PIRQB
EC SM Bus1 address
3 3
Device
Smart Battery
EEPROM(24C16/02)
(24C04)
Address Address
1010 000Xb
1011 000Xb
EC SM Bus2 address
Device
MAX6654MEE
Smart Battery
DOT Board
1001 110Xb0001 011Xb
0001 011Xb
XXXX XXXXb
ICH3-M SM Bus address
Device
Clock Generator
W320-04 / ICS9508-05
Address
1101 0000
DDR SODIMM SM Bus address
4 4
DDR SLOT SA2 SA1 SA0
DDR SODIMM 0 (REVERSE)
DDR SODIMM 1 (NORMAL)
A
000
001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
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Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, inc.
SCHEM A T IC, M/B LA-1521
401229
星期一 十一
?04, 2002
343,
E
1B
of
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+CPU_CORE
1 1
AB1
AC1
AA3
AC3
AF22
AF23
U40A
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AP#0
V5
AP#1
BINIT#
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
BCLK0
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
HA#[3..31]7
2 2
HREQ#[0..4]7
HADS#7
+CPU_CORE
HBR0#7
3 3
HBPRI#7
HBNR#7
HLOCK#7
CLK_HCLK13
CLK_HCLK#13
HIT#7
HITM#7
HDEFER#7
HA#[3..31]
HREQ#[0..4]
1 2
R416 10K
1 2
R95 200_0603
CLK_HCLK
CLK_HCLK#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
B
A10
A12
A14
A16
A18
A20
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
NorthWood
VSS_0H1VSS_1H4VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
AA11
AA4
AA7
AA13
AA15
AA17
AA9
AA19
AA23
AA26
AB10
AB12
AB14
AB16
AB18
C
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
Mobile
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
AB3
AB6
AB8
AB20
AB21
AB24
AC11
AC13
AC15
D
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
E10
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71D7VCC_72
VCC_73
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VCC_81
AC2
AC5
AC7
AC9
AC17
AC19
AD1
AC22
AC25
AD10
AD12
AD14
AD16
AD18
AD21
F13
AD4
AD8
AD23
VCC_79E8VCC_80
VCC_82
VCC_83
VCC_84
VCC_85
F9
F11
F15
F17
F19
NorthWood
E12
E14
E16
E18
E20
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#[0..63]
E
HD#[0..63] 7
+CPU_CORE
4 4
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
期一 十一月
E
of
443¬P , 04, 2002
1B
A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF
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Size Doc u men t Numbe r R e v
Custom
Dat e : Sheet
A
hexainf@hotmail.com
+CPU_CORE
H_A20M#
12
R83 200
R91 200
R113 200
R414 200
1 1
2 2
3 3
R53 200
R408 200
R413 200
R118 200
R109 56
R56 300
R59 51.1_1%_0603
R87 200
Place resistor <100mils from
CPU pin
RP6
1 8
2 7
3 6
4 5
8P4R_1.5K
+CPU_CORE
12
R411 200_0603
12
R412 200_0603
12
R401 200_0603
12
R405 200_0603
Thermal Sensor
MAX6654MEE
C503
+5VS
2200PF_0603
R400 1K
12
4 4
Address:1001_110X
12
12
12
12
12
12
12
12
12
12
12
+1.2VP
ITP_TMS
ITP_TCK
ITP_TRST#
ITP_TDI
ITP_PREQ#
ITP_PRDY#
ITP_BPM0
ITP_BPM1
12
PM_CPUPERF#
1 2
1 2
H_THERMDA
H_THERMDC
A
H_SMI#
H_IGNNE#
H_STPCLK#
H_DPSLP#
H_NMI
H_INIT#
H_INTR
H_F_FERR#
H_PWRGD
H_RESET#
Murata
LQG21F4R7N00
L22
4.7UH_80mA_0805
4.7UH_80mA_0805
L21
W=15mil
1
2
3
4
5
6
7
8
+CPU_CORE
12
R111
56
12
C485
+
33UF_D2_16V
CLK_ITPP13
CLK_ITPP#13
C495
.1UF
1 2
U39
NC
VCC
DXP
DXN
NC
ADD1
GND
GND
NE1617/ MAX6654MEE
STBY
SMBCLK
SMBDATA
ALERT
ADD0
NC
NC
NC
16
15
14
13
12
11
10
9
H_RS#07
H_RS#17
H_RS#27
H_TRDY#7
H_A20M#20
H_F_FERR#20
H_IGNNE#20
H_SMI#20
H_PWRGD20
H_STPCLK#20
H_DPSLP#20
H_INTR20
H_INIT#20
H_RESET#7
H_DBSY#7
H_DRDY#7
H_BSEL013
H_BSEL113
12
C486
+
33UF_D2_16V
H_VSSA
CLK_ITPP
CLK_ITPP#
+5VS
1 2
R397
1K
H_NMI20
R395
10K
1 2
+5VS
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM0
ITP_BPM1
ITP_PRDY#
ITP_PREQ#
ITP_TCK
ITP_TDI
ITP_TMS
ITP_TRST#
51.1_1%_0603
R396
10K
1 2
R31
B
H_A20M#
H_F_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLP#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_VCCA
TP1
H_VCCIOPLL
1 2
1 2
EC_SMC2 32
EC_SMD2 32
B
F1
G5
F4
AB2
J6
C6
B6
B2
B5
AB23
Y4
AD25
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
A5
AE23
AF25
AF3
AC26
AD26
L24
P1
R115
51.1_1%_0603
AE11
AE13
AE15
AE17
AE19
AE22
AE24
VSS_57
VSS_58
VSS_59
VSS_129F8VSS_130
G21
VSS_60
VSS_61
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
G24
AE26
VSS_62
VSS_63
VSS_64
J22
U40B
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCA
VCCSENSE
VCCIOPLL
NC7
NC8
ITP_CLK0
ITP_CLK1
COMP0
COMP1
GTL Reference Vol tage
+CPU_CORE
12
R393
R_A
49.9_1%_0603
Trace width>=7mila
12
R394
100_1%_0603
R_B
C
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
AF26
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
SKTOCC#
B26
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
NorthWood
VSS_136
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
J25
L23
L26
K21
K24
Layout note :
1. Place R_A and R_B near CPU.
2. Place decoupling cap 220PF near CPU.(Within
500mils )
M22
M25
C487
C481
1UF_0603
220PF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
P22
P25
N21
N24
C
C11
C13
C15
C17
C19
C22
C25
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
Mobile
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
T21
T24
R23
R26
+H_GTLREF1
U22
D10
VSS_168
U25
D12
D14
VSS_99
VSS_100
VSS_169U5VSS_170V1VSS_171
V23
D
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
F10
F12
F14
F16
F18
F22
F25
F5
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VSS_127
VSS_128
J26
DP#0
K25
DP#1
K26
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
NC1
NC2
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
GHI#
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
VSSA
VSSSENSE
NC3
VID0
VID1
VID2
VID3
AE5
AE4
AE3
1 3
D
D
VID4
AE2
AE1
2
G
Q51
@2N7002
NC5
NC6
AF24
AE21
S
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
VSS_181
V26
W21
Y5
Y22
Y25
W24
CBRST#24,25,26
VR_ON32,43
EC_CPUPD#32
NC4
VCCVID
NorthWood
AF4
CPU_VR_VID4 6,43
CPU_VR_VID3 6,43
CPU_VR_VID2 6,43
CPU_VR_VID1 6,43
CPU_VR_VID0 6,43
+5V
12
***
Q52
3904
3 1
+H_GTLREF1
L25
AA21
AA6
F20
F6
A22
A7
TESTTHI0_1
AD24
AA2
TESTTHI2_7
AC21
AC20
AC24
AC23
AA20
AB22
TESTTHI8_10
U6
W4
Y3
A6
E22
K22
R22
W22
F21
J23
P23
W23
L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
AD22
A4
AD2
AD3
+1.2VP
C63
.1UF
R445
10K
2
Q50
3904
Title
Size Docu ment Number Re v
Date: Sheet
PM_CPUPERF#
H_DSTBN#[0..3]
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#[0..3]
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DBI#[0..3]
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_PROCHOT#
H_SLP#
H_VSSA
TP2
+CPU_CORE
12
3 1
R446
470
2
R415 56
R444 470
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
All of these pin
connected inside
1 2
R410 56
1 2
R62 56
1 2
R409 56
1 2
R54 200
H_THERMTRIP#
12
E
+CPU_CORE
PM_CPUPERF# 20
H_DSTBN#[0..3] 7
H_DSTBP#[0..3] 7
H_ADSTB#0 7
H_ADSTB#1 7
H_DBI#[0..3] 7
H_SLP# 20
12
+CPU_CORE
+CPU_CORE
543,
1B
of
A
B
C
D
E
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.
1 1
2 2
Please place these cap in the socket cavity area
+CPU_CORE
12
C134
10UF_6.3V_1206_X5R
+CPU_CORE
12
C112
10UF_6.3V_1206_X5R
Please place these cap on the socket north side
+CPU_CORE
12
C118
10UF_6.3V_1206_X5R
+CPU_CORE
12
C497
10UF_6.3V_1206_X5R
+CPU_CORE
12
C520
10UF_6.3V_1206_X5R
12
C127
10UF_6.3V_1206_X5R
12
C141
10UF_6.3V_1206_X5R
12
C123
10UF_6.3V_1206_X5R
12
C502
10UF_6.3V_1206_X5R
12
C83
10UF_6.3V_1206_X5R
12
C120
10UF_6.3V_1206_X5R
12
C136
10UF_6.3V_1206_X5R
12
C479
10UF_6.3V_1206_X5R
12
C505
10UF_6.3V_1206_X5R
12
C97
10UF_6.3V_1206_X5R
12
C111
10UF_6.3V_1206_X5R
12
C128
10UF_6.3V_1206_X5R
12
C483
10UF_6.3V_1206_X5R
12
C509
10UF_6.3V_1206_X5R
12
C107
10UF_6.3V_1206_X5R
12
C103
10UF_6.3V_1206_X5R
12
C121
10UF_6.3V_1206_X5R
12
C488
10UF_6.3V_1206_X5R
12
C512
10UF_6.3V_1206_X5R
Layout note :
Place close to CPU power and
ground pin as possible
(<1inch)
+CPU_CORE
12
C199
+
220UF_D2_4V_25m
+CPU_CORE
12
C561
+
220UF_D2_4V_25m
+CPU_CORE
12
12
C142
C143
.22UF_X7R
.22UF_X7R
Used ESR 25m ohm cap total ESR=2.5m ohm
+
12
C145
.22UF_X7R
12
C197
+
220UF_D2_4V_25m
12
C563
220UF_D2_4V_25m
12
C146
.22UF_X7R
12
C196
+
220UF_D2_4V_25m
12
C564
+
@220UF_D2_4V_25m
12
C105
.22UF_X7R
12
12
C198
+
@220UF_D2_4V_25m
12
C562
+
220UF_D2_4V_25m
12
C144
.22UF_X7R
CPU Voltage ID
C96
.22UF_X7R
12
C195
+
220UF_D2_4V_25m
12
C565
+
220UF_D2_4V_25m
12
C95
.22UF_X7R
12
C94
.22UF_X7R
12
C93
.22UF_X7R
R179
1K
+3VS
182736
45
12
RP15
8P4R_1K
CPU_VID1 5,43
CPU_VID2 5,43
CPU_VID3 5,43
CPU_VID4 5,43
Title
Size Docu ment Number Re v
D
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
1B
of
643,
Please place these cap on the socket south side
3 3
4 4
+CPU_CORE
12
C480
10UF_6.3V_1206_X5R
+CPU_CORE
12
C506
10UF_6.3V_1206_X5R
+CPU_CORE
12
C109
10UF_6.3V_1206_X5R
A
12
C484
10UF_6.3V_1206_X5R
12
C511
10UF_6.3V_1206_X5R
12
C119
10UF_6.3V_1206_X5R
12
C490
10UF_6.3V_1206_X5R
12
C513
10UF_6.3V_1206_X5R
12
C124
10UF_6.3V_1206_X5R
12
C498
10UF_6.3V_1206_X5R
12
C519
10UF_6.3V_1206_X5R
12
C130
10UF_6.3V_1206_X5R
12
12
B
C504
10UF_6.3V_1206_X5R
C98
10UF_6.3V_1206_X5R
CPU_VR_VID05,43 CPU_VID0 5,43
CPU_VR_VID15,43
CPU_VR_VID25,43
CPU_VR_VID35,43
CPU_VR_VID45,43
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
C
A
B
C
D
E
HD#[0..63]
+V_MCH_GTLREF
GTL Reference Vol tage
Layout note :
1. Place R_E and R_F near MCH
2. Place decoupling cap 220PF near MCH pin.(Within 500mils)
C518
.01UF
C514
.01UF
A
HA#[3..31]
HREQ#[0..4]
H_DBI#[0..3]
R417
24.9_0603_1%
+1.5VS
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
CLK_GHT
CLK_GHT#
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_SWNG0
H_SWNG1
12
R428 8.2K
R419 8.2K
R404 8.2K
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
AE17
AD15
AD13
AC13
12
R424
24.9_0603_1%
12
12
12
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7
R5
N6
U7
Y4
Y7
W5
J27
H26
V5
V4
Y5
Y3
V7
V3
W3
W2
W7
W6
U6
T7
R7
U5
U2
J8
K8
AD5
AG4
AH9
AA7
AC2
AGP_ADSTB0
AGP_ADSTB1
AGP_SBSTB
U7A
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB#0
HADSTB#1
CPURST#
HTRDY#
DEFER#
BPRI#
HLOCK#
RSTIN#
TESTIN#
DBSY#
DRDY#
HIT#
HITM#
BREQ#0
ADS#
BNR#
RS#0
RS#1
RS#2
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
BCLK
BCLK#
DBI#0
DBI#1
DBI#2
DBI#3
HSWNG0
HSWNG1
HRCOMP0
HRCOMP1
H_DSTBN#[0..3]
H_DSTBP#[0..3]
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
BROOKDALE(MCH-M)
H_DSTBN#[0..3] 5
H_DSTBP#[0..3] 5
R427 @8.2K
R418 @8.2K
R403 @8.2K
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4
AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16
AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16
M7
R8
Y8
AB11
AB17
12
12
12
B
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBSTB#
HA#[3..31]4
1 1
H_ADSTB#05
H_ADSTB#15
H_RESET#5
H_TRDY#5
HREQ#[0 ..4 ]4
+CPU_CORE
12
R420
12
R421
+CPU_CORE
12
R422
12
R423
HDEFER#4
HBPRI#4
HLOCK#4
PCIRST#14,20,23,24,25,26,27
H_DBSY#5
H_DRDY#5
HIT#4
HITM#4
HBR0#4
HADS#4
HBNR#4
H_RS#05
H_RS#15
H_RS#25
CLK_GHT13
CLK_GHT#13
H_DBI#[0..3]5
12
12
2 2
3 3
301_1%_0603
150_1%_0603
301_1%_0603
4 4
150_1%_0603
HD#[0 ..6 3 ] 4
AGP_AD[0..31]14
AGP_C/BE#[0..3]14
AGP_ST[0..2]14
+CPU_CORE
12
R426
R_E
49.9_1%_0603
12
R425
R_F
100_1%_0603
AGP_ST0
0=System memory is DDR
1=System memory is SDR
AGP_AD[0..31] HUB_PD[0..10]
AGP_ADSTB014
AGP_ADSTB0#14
AGP_ADSTB114
AGP_ADSTB1#14
AGP_SBSTB14
AGP_SBSTB#14
AGP_FRAME#14
AGP_DEVSEL#14
AGP_IRDY#14
AGP_TRDY#14
AGP_STOP#14
AGP_PAR14
AGP_REQ#14
AGP_GNT#14
Trace
width>=7mila
C523
C525
1UF_0603
220PF
AGP_ST0 AGP_ST1
R398 2K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
C
12
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_ST0
AGP_ST1
AGP_ST2
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#
AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#
U7B
R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
AA28
AB25
AB27
AA27
AB26
Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24
V25
V23
Y25
AA23
AG25
AF24
AG26
R24
R23
AC27
AC28
AF27
AF26
Y24
W28
W27
W24
W23
W25
AG24
AH25
AF22
N22
K27
K5
L24
M23
K7
J26
A3
A7
A11
A15
12
R406 @8.2K
G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31
G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3
ST0
ST1
ST2
AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#
G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AGP_FRAME#
AGP_TRDY#
AGP_PAR
AGP_STOP#
AGP_GNT#
AGP_REQ#
AGP_IRDY#
AGP_DEVSEL#
AGP_WBF#
AGP_PIPE#
AGP_RBF#
AGP_ST2
HUB
HLRCOMP
AGP
GRCOMP
BROOKDALE(MCH-M)
RP65 @8P4R_8.2K
1 8
2 7
3 6
4 5
RP63 @8P4R_8.2K
1 8
2 7
3 6
4 5
RP64 @8P4R_8.2K
1 8
2 7
3 6
4 5
12
R402 8.2K
12
R399 8.2K
HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10
HI_STB
HI_STB#
HI_REF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
AGPREF
66IN
RBF#
WBF#
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
+1.5VS
D
P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24
N25
N24
P27
P26
AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25
AA21
AD25
P22
AE22
AE23
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J29
AGP_ST1
0=533Mhz
1=400Mhz
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HLRCOMP
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
R407 36.5_1%_0603
CLK_AGP_MCH
AGP_RBF#
AGP_WBF#
+AGP_REF
HUB_PD[0..10] 20
HUB_PSTRB 20
HUB_PSTRB# 20
1 2
R430 36.5_1%_0603
AGP_SBA[0..7]
Place this cap near MCH
+AGP_REF
12
CLK_AGP_MCH 13
AGP_RBF# 14
**
301_1%_0603
301_1%_0603
Title
Size Docu ment Number Re v
Date: Sheet
星期一 十一
AGP_SBA[0..7] 14
12
C522
.1UF
+1.5VS
12
R441
1K_1%_0603
12
R442
1K_1%_0603
HUB Interface Reference
Layout note :
+1.8VS
1. Pla c e R_C and R_D in middle of Bus.
2. Place capacitors near MCH.
12
R116
R_C
12
R110
R_D
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
?04, 2002
+1.8VS
12
C622
.1UF
12
C170
@470PF_0603
12
R130
@56.2_1%_0603
12
R107
0
12
C166
.01UF
E
+VS_HUBREF
12
C530
.01UF
Place closely
ball P26
Place closely pin P22
CLK_AGP_MCH
R429
@33
1 2
C532
@10PF
+VS_HUBREF
of
743,
1B
A
B
C
D
E
U7D
M8
+CPU_CORE
1 1
+2.5V
2 2
3 3
4 4
VTT_0
U8
VTT_1
AA9
VTT_2
AB8
VTT_3
AB18
VTT_4
AB20
VTT_5
AC19
VTT_6
AD18
VTT_7
AD20
VTT_8
AE19
VTT_9
AE21
VTT_10
AF18
VTT_11
AF20
VTT_12
AG19
VTT_13
AG21
VTT_14
AG23
VTT_15
AJ19
VTT_16
AJ21
VTT_17
AJ23
VTT_18
A5
VCCSM1
A9
VCCSM2
A13
VCCSM3
A17
VCCSM4
A21
VCCSM5
A25
VCCSM6
C1
VCCSM7
C29
VCCSM8
D7
VCCSM9
D11
VCCSM10
D15
VCCSM11
D19
VCCSM12
D23
VCCSM13
D25
VCCSM14
F6
VCCSM15
F10
VCCSM16
F14
VCCSM17
F18
VCCSM18
F22
VCCSM19
G1
VCCSM20
G4
VCCSM21
G29
VCCSM22
H8
VCCSM23
H10
VCCSM24
H12
VCCSM25
H14
VCCSM26
H16
VCCSM27
H18
VCCSM28
H20
VCCSM29
H22
VCCSM30
H24
VCCSM31
K22
VCCSM32
K24
VCCSM33
K26
VCCSM34
L23
VCCSM35
K6
VCCSM36
J5
VCCSM37
J7
VCCSM38
L1
VSS41
L4
VSS42
L6
VSS43
L8
VSS44
L22
VSS45
L26
VSS46
N1
VSS47
N4
VSS48
N8
VSS49
N13
VSS50
N15
VSS51
N17
VSS52
N29
VSS53
P6
VSS54
P8
VSS55
P14
VSS56
P16
VSS57
R1
VSS58
R4
VSS59
R13
VSS60
R15
VSS61
R17
VSS62
R26
VSS63
T6
VSS64
T8
VSS65
T14
VSS66
T16
VSS67
T22
VSS68
U1
VSS69
U4
VSS70
U15
VSS71
U29
VSS72
V6
VSS73
V8
VSS74
V22
VSS75
W1
VSS76
W4
VSS77
W8
VSS78
W26
VSS79
Y6
VSS80
Y22
VSS81
AA1
VSS82
BROOKDALE(MCH-M)
POWER/GND
VCC1_5_0
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8
VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15
VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25
VCC1_8_0
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCCGA1
VCCHA1
VSSGA2
VSSHA2
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25
N14
N16
P13
P15
P17
R14
R16
T15
U14
U16
L29
N26
L25
M22
N23
T17
T13
U17
U13
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ27
VCC_MCH_PLL1
VCC_MCH_PLL0
VSS_MCH_PLL1
VSS_MCH_PLL0
+1.5VS
+1.5VS
+1.8VS
"Trace A"
"Trace A"
12
L43
4.7UH_30mA
"Trace A"
12
C527
+
33UF_D2_16V
"Trace A"
Layout note :
Trace width 5mil ; Spacing 10mil
Trace A to ball U7/T13 or U7/T7 =1.5" Max
12
L42
4.7UH_30mA
12
C541
+
33UF_D2_16V
Murata
LQG21N4R7K10
DDR_SDQ[0..63]10
DDR_CB[0..7]10
DDR_SDQ[0..63]
DDR_CB[0..7]
DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7
+SDREF
12
C547
.1UF_0402_X5R
Layout note
Please closely pinJ21 and J9
U7C
G28
SDQ0
F27
SDQ1
C28
SDQ2
E28
SDQ3
H25
SDQ4
G27
SDQ5
F25
SDQ6
B28
SDQ7
E27
SDQ8
C27
SDQ9
B25
SDQ10
C25
SDQ11
B27
SDQ12
D27
SDQ13
D26
SDQ14
E25
SDQ15
D24
SDQ16
E23
SDQ17
C22
SDQ18
E21
SDQ19
C24
SDQ20
B23
SDQ21
D22
SDQ22
B21
SDQ23
C21
SDQ24
D20
SDQ25
C19
SDQ26
D18
SDQ27
C20
SDQ28
E19
SDQ29
C18
SDQ30
E17
SDQ31
E13
SDQ32
C12
SDQ33
B11
SDQ34
C10
SDQ35
B13
SDQ36
C13
SDQ37
C11
SDQ38
D10
SDQ39
E10
SDQ40
C9
SDQ41
D8
SDQ42
E8
SDQ43
E11
SDQ44
B9
SDQ45
B7
SDQ46
C7
SDQ47
C6
SDQ48
D6
SDQ49
D4
SDQ50
B3
SDQ51
E6
SDQ52
B5
SDQ53
C4
SDQ54
E5
SDQ55
C3
SDQ56
D3
SDQ57
F4
SDQ58
F3
SDQ59
B2
SDQ60
C2
SDQ61
E2
SDQ62
G5
SDQ63
C16
SDQ64/CB0
D16
SDQ65/CB1
B15
SDQ66/CB2
C14
SDQ67/CB3
B17
SDQ68/CB4
C17
SDQ69/CB5
C15
SDQ70/CB6
D14
SDQ71/CB7
J21
SDREF0
J9
SDREF1
BROOKDALE(MCH-M)
MEMORY
SMA0/CS#11
SMA1/CS#10
SMA2/CS#6
SMA3/CS#9
SMA4/CS#5
SMA5/CS#8
SMA6/CS#7
SMA7/CS#4
SMA8/CS#3
SMA9/CS#0
SMA11/CS#2
SMA12/CS#1
SMRCOMP
RCVENIN#
RCVENOUT#
SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5
SCK6
SCK#6
SCK7
SCK#7
SCK8
SCK#8
SCS#0
SCS#1
SCS#2
SCS#3
SCS#4
SCS#5
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SMA10
SBS0
SBS1
SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5
SSI_ST
SRAS#
SWE#
SCAS#
NC0
NC1
E14
F15
J24
G25
G6
G7
G15
G14
E24
G24
H5
F5
K25
J25
G17
G16
H7
H6
DDR_SCS#0
E9
DDR_SCS#1
F7
DDR_SCS#2
F9
DDR_SCS#3
E7
G9
G10
DDR_SDQS0
F26
DDR_SDQS1
C26
DDR_SDQS2
C23
DDR_SDQS3
B19
DDR_SDQS4
D12
DDR_SDQS5
C8
DDR_SDQS6
C5
DDR_SDQS7
E3
DDR_SDQS8
E15
DDR_SMA0
E12
DDR_SMA1
F17
DDR_SMA2
E16
DDR_SMA3
G18
DDR_SMA4
G19
DDR_SMA5
E18
DDR_SMA6
F19
DDR_SMA7
G21
DDR_SMA8
G20
DDR_SMA9
F21
DDR_SMA10
F13
DDR_SMA11
E20
DDR_SMA12
G22
DDR_SBS0
G12
DDR_SBS1
G13
DDR_CKE0
G23
DDR_CKE1
E22
DDR_CKE2
H23
DDR_CKE3
F23
J23
K23
+SM_RCOMP
J28
RCVIN#
G3
RCVOUT#
H3
H27
F11
G11
G8
AD26
AD27
R432
DDR_SRAS#
DDR_SWE#
DDR_SCAS#
Layout note
Place R_J closely Ball H3<40mil,Ball H3 to G3 trace must
routing 1"
R431 30.1_1%
12
0_0402
R_J
DDR_CLK0 10
DDR_CLK0# 10
DDR_CLK1 10
DDR_CLK1# 10
DDR_CLK2 10
DDR_CLK2# 10
DDR_CLK3 11
DDR_CLK3# 11
DDR_CLK4 11
DDR_CLK4# 11
DDR_CLK5 11
DDR_CLK5# 11
DDR_SCS#0 10,11
DDR_SCS#1 10,11
DDR_SCS#2 11
DDR_SCS#3 11
DDR_SDQS0 10
DDR_SDQS1 10
DDR_SDQS2 10
DDR_SDQS3 10
DDR_SDQS4 10
DDR_SDQS5 10
DDR_SDQS6 10
DDR_SDQS7 10
DDR_SDQS8 10
DDR_SMA[0..12]
DDR_SBS0 10,11
DDR_SBS1 10,11
DDR_CKE0 10,11
DDR_CKE1 10,11
DDR_CKE2 11
DDR_CKE3 11
12
C553 .1UF_0402_X5R
C555 @47PF
DDR_SRAS# 10,11
DDR_SWE# 10,11
DDR_SCAS# 10,11
DDR_SMA[0..12] 10,11
+1.25VS
Layout note
Place R431 closely
pinJ28
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
A
B
C
D
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
1B
of
843,
5
4
3
2
1
Layout note :
Distr ib ute as cl ose as possib le
to M CH Processor Qu adrant.(b etween VTTFSB and VSS pin)
+CPU_CORE
D D
12
C533
.1UF_0402_X5R
+CPU_CORE
12
C510
.1UF_0402_X5R
+CPU_CORE
12
C494
10UF_6.3V_1206_X5R
C C
Layout note :
Distr ib ute as cl ose as possib le
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)
Processor system bus
12
C526
.1UF_0402_X5R
12
C501
.1UF_0402_X5R
12
C493
10UF_6.3V_1206_X5R
12
C515
.1UF_0402_X5R
12
C516
.1UF_0402_X5R
AGP/CORE
12
C507
.1UF_0402_X5R
12
C499
.1UF_0402_X5R
12
C492
10UF_6.3V_1206_X5R
12
C500
.1UF_0402_X5R
12
C508
.1UF_0402_X5R
Layout note :
Distr ib ute as cl ose as possib le
to MCH Processor Quadrant.(between VCCSM and VSS pin)
+2.5V
12
C550
.1UF_0402_X5R
+2.5V
12
C538
.1UF_0402_X5R
+2.5V
12
C543
.1UF_0402_X5R
+2.5V
12
C568
+
150UF_D2_6.3V
DDR Memory interface
12
C549
.1UF_0402_X5R
12
C546
.1UF_0402_X5R
12
C560
.1UF_0402_X5R
12
C548
.1UF_0402_X5R
12
C557
.1UF_0402_X5R
12
C552
.1UF_0402_X5R
12
C542
.1UF_0402_X5R
12
C558
.1UF_0402_X5R
12
C544
.1UF_0402_X5R
12
C545
.1UF_0402_X5R
12
C559
.1UF_0402_X5R
12
C551
.1UF_0402_X5R
12
C570
22UF_10V_1206
12
C567
22UF_10V_1206
+1.5VS
12
C529
.1UF_0402_X5R
B B
+1.5VS
12
C535
10UF_6.3V_1206_X5R
Layout note :
Distr ib ute as cl ose as possib le
to MC H P roce ssor Quadrant.(between VCCHL and VSS pin)
+1.8VS
A A
12
C537
10UF_6.3V_1206_X5R
12
C528
.1UF_0402_X5R
12
C536
10UF_6.3V_1206_X5R
Hub-Link
12
C534
.1UF_0402_X5R
5
12
C517
.1UF_0402_X5R
12
C539
.1UF_0402_X5R
12
C496
+
150UF_D2_6.3V
12
12
C524
.1UF_0402_X5R
C540
.1UF_0402_X5R
12
C521
.1UF_0402_X5R
4
12
C531
.1UF_0402_X5R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE
3
2
Title
Size Doc u men t Numbe r R e v
Dat e : Sheet
Compal Electronics, inc.
SCH E MATIC, M/B LA-1521
401229
期一 十一月
943¬P , 04, 2002
1
1B
of
A
DDR_SBS0
DDR_SWE#
RP86 4P2R_22
1 4
2 3
RP85 4P2R_22
1 4
2 3
RP84 4P2R_22
1 4
2 3
RP83 4P2R_22
1 4
2 3
RP82 4P2R_22
1 4
2 3
RP81 4P2R_22
1 4
2 3
RP80 4P2R_22
1 4
2 3
RP79 4P2R_22
1 4
2 3
RP78 4P2R_22
1 4
2 3
RP77 4P2R_22
1 4
2 3
RP76 4P2R_22
1 4
2 3
RP21 4P2R_10
1 4
2 3
RP23 4P2R_10
1 4
2 3
RP25 4P2R_10
1 4
2 3
RP75 4P2R_10
1 4
2 3
RP74 4P2R_22
1 4
2 3
RP73 4P2R_22
1 4
2 3
RP72 4P2R_22
1 4
2 3
RP71 4P2R_22
1 4
2 3
RP70 4P2R_22
1 4
2 3
RP69 4P2R_22
1 4
2 3
RP68 4P2R_22
1 4
2 3
RP67 4P2R_22
1 4
2 3
RP66 4P2R_22
1 4
2 3
DDR_SDQ0
DDR_SDQ6
DDR_SDQ3
DDR_SDQ2
DDR_SDQ8
1 1
2 2
DDR_SBS08,11
DDR_SWE#8,11
3 3
4 4
DDR_SDQ12
DDR_SDQS1
DDR_SDQ14
DDR_SDQ19
DDR_SDQ17
DDR_SDQS2
DDR_SDQ21
DDR_SDQ23
DDR_SDQ31
DDR_SDQ25
DDR_SDQ26
DDR_SDQS3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB3
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA6
DDR_SMA3
DDR_SMA1
DDR_SDQ36
DDR_SDQ37
DDR_SDQS4
DDR_SDQ33
DDR_SDQ34 DDR_DQ34
DDR_SDQ44 DDR_DQ44
DDR_SDQ41 DDR_DQ41
DDR_SDQ47
DDR_SDQ46
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ60 DDR_DQ60
DDR_SDQ62
DDR_SDQ59
A
DDR_DQ0
DDR_DQ6
DDR_DQ3
DDR_DQ2
DDR_DQ8
DDR_DQ12
DDR_DQS1
DDR_DQ14
DDR_DQ19
DDR_DQ17
DDR_DQS2
DDR_DQ21
DDR_DQ23
DDR_DQ31
DDR_DQ27DDR_SDQ27
DDR_DQ25
DDR_DQ26
DDR_DQS3
DDR_F_CB4
DDR_F_CB5
DDR_F_CB6
DDR_F_CB3
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SBS0
DDR_F_SWE#
DDR_DQ36
DDR_DQ37
DDR_DQS4
DDR_DQ33
DDR_DQ43DDR_SDQ43
DDR_DQ47
DDR_DQ46
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ54DDR_SDQ54
DDR_DQ57DDR_SDQ57
DDR_DQ62
DDR_DQ59
B
DDR_SDQ4
DDR_SDQ5
DDR_SDQ1
DDR_SDQS0
DDR_SDQ7
DDR_SDQ15
DDR_SDQ9
DDR_SDQ13
DDR_SDQ11
DDR_SDQ10
DDR_SDQ20
DDR_SDQ16
DDR_SDQ22
DDR_SDQ18
DDR_SDQ29
DDR_SDQ24
DDR_SDQ28
DDR_SDQ30
DDR_SDQS8
DDR_CB7
DDR_CB0
DDR_CB2
DDR_SMA7
DDR_SMA11
DDR_SMA4
DDR_SMA5
DDR_SMA10
DDR_SMA0
DDR_SCAS#8,11
DDR_SRAS#8,11
B
DDR_SCAS#
DDR_SRAS# DDR_F_SRAS#
DDR_SDQ32 DDR_DQ32
DDR_SDQ39
DDR_SDQ35 DDR_DQ35
DDR_SDQ42
DDR_SDQS5
DDR_SDQ40
DDR_SDQ45
DDR_SDQ55 DDR_DQ55
DDR_SDQ52
DDR_SDQS6
DDR_SDQ53
DDR_SDQ51
DDR_SDQ61
DDR_SDQS7
DDR_SDQ58
DDR_SDQ63
C
RP108 4P2R_22
1 4
2 3
RP107 4P2R_22
1 4
2 3
RP106 4P2R_22
1 4
2 3
RP105 4P2R_22
1 4
2 3
RP104 4P2R_22
1 4
2 3
RP103 4P2R_22
1 4
2 3
RP102 4P2R_22
1 4
2 3
RP101 4P2R_22
1 4
2 3
RP100 4P2R_22
1 4
2 3
RP99 4P2R_22
1 4
2 3
RP98 4P2R_22
1 4
2 3
RP97 4P2R_22
1 4
2 3
RP22 4P2R_10
1 4
2 3
RP24 4P2R_10
1 4
2 3
RP26 4P2R_10
1 4
2 3
RP96 4P2R_10
1 4
2 3
RP95 4P2R_22
1 4
2 3
RP94 4P2R_22
1 4
2 3
RP93 4P2R_22
1 4
2 3
RP92 4P2R_22
1 4
2 3
RP91 4P2R_22
1 4
2 3
RP90 4P2R_22
1 4
2 3
RP89 4P2R_22
1 4
2 3
RP88 4P2R_22
1 4
2 3
RP87 4P2R_22
1 4
2 3
C
DDR_DQ4
DDR_DQ5
DDR_DQ1
DDR_DQS0
DDR_DQ7
DDR_DQ15
DDR_DQ9
DDR_DQ13
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ16
DDR_DQ22
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQ28
DDR_DQ30
DDR_DQS8
DDR_F_CB7
DDR_F_CB1DDR_CB1
DDR_F_CB0
DDR_F_CB2
DDR_F_SMA7
DDR_F_SMA11
DDR_F_SMA4
DDR_F_SMA5
DDR_F_SMA10
DDR_F_SMA0
DDR_F_SCAS#
DDR_DQ39
DDR_DQ38DDR_SDQ38
DDR_DQ42
DDR_DQS5
DDR_DQ40
DDR_DQ45
DDR_DQ52
DDR_DQS6
DDR_DQ53
DDR_DQ51
DDR_DQ56DDR_SDQ56
DDR_DQ61
DDR_DQS7
DDR_DQ58
DDR_DQ63
D
DDR_DQ4
DDR_DQ0 DDR_DQ6
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ8
DDR_DQS1
DDR_DQ9
DDR_DQ14
DDR_CLK18
DDR_CLK1#8
DDR_DQ19
DDR_DQ20
DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQS3
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
DDR_DQS8
DDR_F_CB1
DDR_CLK08
DDR_CLK0#8
DDR_CKE18,11
DIMM_SMDATA11,13
DDR_CKE1 DDR_CKE0
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE# DDR_F_SCAS#
DDR_SCS#0
DDR_DQ36
DDR_DQ32
DDR_DQS4
DDR_DQ35
DDR_DQ34
DDR_DQ42
DDR_DQ41
DDR_DQS5
DDR_DQ40
DDR_DQ47
DDR_DQ55
DDR_DQ48
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQS7
DDR_DQ62
DDR_DQ58
DIMM_SMCLK11,13
+3VS
E
+2.5V +2.5V
JP18
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_REVERSE
DU/RESET#
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
F
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDR_DQ5
DDR_DQ1
DDR_DQ2
DDR_DQ12DDR_DQ15
DDR_DQ13
DDR_DQ11
DDR_DQ10
DDR_DQ17
DDR_DQ16
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_F_CB0
DDR_F_CB2DDR_F_CB3
DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SRAS#
DDR_DQ37
DDR_DQ39
DDR_DQ33
DDR_DQ38
DDR_DQ44
DDR_DQ43
DDR_DQ45
DDR_DQ46
DDR_DQ52
DDR_DQ49
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQ59
DDR_DQ63
+SDREF
12
C74
.1UF
DDR_CKE0 8,11
R241 10
R436 10
DDR_SCS#1 8,11DDR_SCS#08,11
DDR_CLK2# 8
DDR_CLK2 8
G
12
12
DDR_SMA2
DDR_SBS1DDR_F_SBS1
DDR_DQ[0..63]
DDR_F_CB[0..7]
DDR_DQS[0..8]
DDR_SMA[0..12]
DDR_SDQ[0..63]
DDR_CB[0..7]
DDR _ S DQS[0..8]
DDR_SBS1 8,11
H
DDR_DQ[0..63] 11
DDR_F_CB[0..7] 11
DDR_DQS[0..8] 11
DDR_SMA[0..12] 8,11
DDR_SDQ[0..63] 8
DDR_CB[0..7] 8
DDR_SDQS[0..8] 8
DIMM0 REVERSE H:5.2mm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
D
E
F
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
G
?04, 2002
1B
of
10 43,
H
A
DDR_F_CB[0..7]10
DDR_DQS[0..8]10
DDR_DQ[0..63]10
DDR_SMA[0..12]8,10
1 1
2 2
DDR_CKE08,10
DDR_CKE18,10
3 3
4 4
DDR_F_CB[0..7]
DDR_DQS[0..8]
DDR_DQ[0..63]
DDR_SMA[0..12]
DDR_DQ4
DDR_DQ0
DDR_DQ3
DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQ9
DDR_DQ14
DDR_DQ19
DDR_DQ20
DDR_DQ22
DDR_DQ23
DDR_DQ27
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
DDR_F_CB1
DDR_F_CB3
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
RP131 4P2R_56
1 4
2 3
RP130 4P2R_56
1 4
2 3
RP129 4P2R_56
1 4
2 3
RP128 4P2R_56
1 4
2 3
RP127 4P2R_56
1 4
2 3
RP126 4P2R_56
1 4
2 3
RP125 4P2R_56
1 4
2 3
RP124 4P2R_56
1 4
2 3
RP123 4P2R_56
1 4
2 3
RP122 4P2R_56
1 4
2 3
RP41 4P2R_56
1 4
2 3
RP42 4P2R_56
1 4
2 3
RP121 4P2R_56
1 4
2 3
RP120 4P2R_56
1 4
2 3
RP119 4P2R_56
1 4
2 3
+1.25VS +1.25VS
RP28 4P2R_56
14
23
RP29 4P2R_56
14
23
RP30 4P2R_56
RP31 4P2R_56
RP32 4P2R_56
RP33 4P2R_56
RP34 4P2R_56
RP35 4P2R_56
RP36 4P2R_56
RP37 4P2R_56
RP38 4P2R_56
RP39 4P2R_56
RP40 4P2R_56
RP43 4P2R_56
RP44 4P2R_56
1 2
R291 56
1 2
R292 56
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
14
23
DDR_DQ2
DDR_DQ5
DDR_DQ6
DDR_DQS0
DDR_DQ1
DDR_DQ12
DDR_DQ13
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ17
DDR_DQ16
DDR_DQS2DDR_DQ29
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQS3
DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_DQS8
DDR_F_CB0
DDR_SMA12
DDR_F_CB2
DDR_SMA7
DDR_SMA9
DDR_SMA3
DDR_SMA5
DDR_SMA1
DDR_SMA10
B
DDR_SBS18,10
DDR_SRAS#8,10
DDR_SCS#08,10
DDR_SCS#18,10
DDR_SCAS#8,10
DDR_SBS1
DDR_SRAS#
DDR_SCS#0
DDR_SCS#1
DDR_SCAS#
DDR_SCS#3
DDR_DQ36
DDR_DQ32
DDR_DQ35
DDR_DQ34
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ47
DDR_DQ55
DDR_DQ48
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQ62
DDR_DQ58
DDR_DQ63
RP118 4P2R_56
1 4
2 3
RP47 4P2R_56
1 4
2 3
RP117 4P2R_56
1 4
2 3
RP116 4P2R_56
1 4
2 3
RP115 4P2R_56
1 4
2 3
RP114 4P2R_56
1 4
2 3
RP113 4P2R_56
1 4
2 3
RP112 4P2R_56
1 4
2 3
RP111 4P2R_56
1 4
2 3
RP110 4P2R_56
1 4
2 3
RP109 4P2R_56
1 4
2 3
RP57 4P2R_56
1 4
2 3
C
RP45 4P2R_56
14
23
RP46 4P2R_56
14
23
RP48 4P2R_56
14
23
RP49 4P2R_56
14
23
RP50 4P2R_56
14
23
RP51 4P2R_56
14
23
RP52 4P2R_56
14
23
RP53 4P2R_56
14
23
RP54 4P2R_56
14
23
RP55 4P2R_56
14
23
RP56 4P2R_56
14
23
DDR_SWE#
DDR_SBS0
DDR_SCS#2
DDR_DQ37
DDR_DQ39
DDR_DQS4
DDR_DQ33
DDR_DQ38
DDR_DQ44
DDR_DQ43
DDR_DQS5
DDR_DQ45
DDR_DQ46
DDR_DQ52
DDR_DQ49
DDR_DQS6
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ59
DDR_SWE# 8,10
DDR_SBS0 8,10
DDR_CLK48
DDR_CLK4#8
DDR_CLK38
DDR_CLK3#8
DIMM_SMDATA10,13
DIMM_SMCLK10,13
D
+2.5V +2.5V
JP19
1
VREF
3
DDR_DQ5
DDR_DQ6
DDR_DQS0
DDR_DQ1
DDR_DQ2
DDR_DQ12
DDR_DQ13
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ17
DDR_DQ16
DDR_DQS2
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQS3
DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_DQS8
DDR_F_CB0
DDR_F_CB2
DDR_CKE3 DDR_CKE2
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_DQ37
DDR_DQ39
DDR_DQS4
DDR_DQ33
DDR_DQ38
DDR_DQ44
DDR_DQ43
DDR_DQS5
DDR_DQ45
DDR_DQ46
DDR_DQ52
DDR_DQ49
DDR_DQS6
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ59
DDR_DQ63
+3VS
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_NORMAL
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
E
DDR_DQ4
DDR_DQ0
DDR_DQ3
DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQ9
DDR_DQ14
DDR_DQ19
DDR_DQ20
DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
DDR_F_CB1
DDR_F_CB3
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3
DDR_DQ36
DDR_DQ32
DDR_DQ35
DDR_DQ34
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ47
DDR_DQ55
DDR_DQ48
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQ62
DDR_DQ58
+3VS
+SDREF
DDR_CKE2 8DDR_CKE38
DDR_SCS#3 8DDR_SCS#28
DDR_CLK5# 8
DDR_CLK5 8
12
C573
.1UF
DIMM1 NORMAL H:9.2mm
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
A
B
C
D
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
1B
of
11 43,
A
B
C
D
E
Layout note :
Distribute as close as possible
to DDR-SODIMM.
+2.5V
12
C574
150UF_D2_6.3V
12
C594
.1UF_0402_X5R
1 1
12
C601
.1UF_0402_X5R
+2.5V +2.5V
12
C592
.1UF_0402_X5R
12
C600
.1UF_0402_X5R
12
C603
.1UF_0402_X5R
12
C599
.1UF_0402_X5R
12
C591
.1UF_0402_X5R
12
C598
.1UF_0402_X5R
12
C590
.1UF_0402_X5R
12
C597
.1UF_0402_X5R
12
C589
.1UF_0402_X5R
12
C602
.1UF_0402_X5R
12
C588
.1UF_0402_X5R
12
C596
.1UF_0402_X5R
12
+
12
C577
150UF_D2_6.3V
C595
.1UF_0402_X5R
+
12
C593
.1UF_0402_X5R
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2 2
+1.25VS
12
C363
.1UF_0402_X5R
+1.25VS
12
C373
.1UF_0402_X5R
12
C364
.1UF_0402_X5R
12
C374
.1UF_0402_X5R
12
C365
.1UF_0402_X5R
12
C375
.1UF_0402_X5R
12
C366
.1UF_0402_X5R
12
C376
.1UF_0402_X5R
12
C367
.1UF_0402_X5R
12
C377
.1UF_0402_X5R
12
C368
.1UF_0402_X5R
12
C378
.1UF_0402_X5R
12
C369
.1UF_0402_X5R
12
C379
.1UF_0402_X5R
12
C370
.1UF_0402_X5R
12
C380
.1UF_0402_X5R
12
C371
.1UF_0402_X5R
12
C381
.1UF_0402_X5R
12
C372
.1UF_0402_X5R
12
C382
.1UF_0402_X5R
+1.25VS
12
C383
3 3
4 4
.1UF_0402_X5R
+1.25VS
12
C392
.1UF_0402_X5R
+1.25VS
12
C401
.1UF_0402_X5R
+1.25VS
12
C409
.1UF_0402_X5R
12
C384
.1UF_0402_X5R
12
C359
.1UF_0402_X5R
12
C402
.1UF_0402_X5R
12
C410
.1UF_0402_X5R
A
12
C385
.1UF_0402_X5R
12
C393
.1UF_0402_X5R
12
C403
.1UF_0402_X5R
12
C411
.1UF_0402_X5R
12
C386
.1UF_0402_X5R
12
C394
.1UF_0402_X5R
12
C605
.1UF_0402_X5R
12
C412
.1UF_0402_X5R
12
C387
.1UF_0402_X5R
12
C395
.1UF_0402_X5R
12
C604
.1UF_0402_X5R
12
C388
.1UF_0402_X5R
12
C396
.1UF_0402_X5R
12
C408
.1UF_0402_X5R
B
12
C389
.1UF_0402_X5R
12
C397
.1UF_0402_X5R
12
C404
.1UF_0402_X5R
12
C390
.1UF_0402_X5R
12
C398
.1UF_0402_X5R
12
C405
.1UF_0402_X5R
12
C391
.1UF_0402_X5R
12
C399
.1UF_0402_X5R
12
C406
.1UF_0402_X5R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
12
12
12
C
C358
.1UF_0402_X5R
C400
.1UF_0402_X5R
C407
.1UF_0402_X5R
Title
Size Docu ment Number Re v
D
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
?04, 2002
E
1B
of
12 43,
A
B
C
+3VS
L30
BLM21A601SPT
1 2
L35
BLM21A601SPT
1 2
D
+3V_CLK
+3V_CLK
+
12
C235
22UF_10V_1206
E
C245
.1UF
12
12
C253
.1UF
12
C258
.1UF
12
C263
.1UF
F
12
C249
.1UF
12
C280
.1UF
12
C279
.1UF
G
H
1 1
SEL0SEL1
00
01
*
1
11
2 2
100Mhz Host CLK
0
200Mhz Host CLK
133Mhz Host CLK
H_BSEL05
H_BSEL15
Function
66Mhz Host CLK
R216
1K
1 2
R171 @0
12
R167
@1K
H_BSEL2
H_BSEL0
R175
+3VS +3VS
12
12
1K
MULT0
0
1 2.32mA
Place Crystal within 500 mils of CK_Titan
C237 10PF
CK408_PWRGD#32,35
+3VS
BSEL0
PM_STPCPU#20,43
PM_SLP_S1#20,32
PM_SLP_S3#20,32
PM_STPPCI#20
caps are i nternal
to CK_TITAN
C238 10PF
R213 10K
R218 @ 10K
12
R170
1K
12
R177
@1K
Iref
5.00mA
12
12
1 2
1 2
DIMM_SMDATA
DIMM_SMCLK
1 2
R226 0
1 2
R233 @0
1 2
R166 0
Please closely pin42
1 2
R223 475_1%
CLK_ICH48M CLKPCI_F2
1 2
R164 33
1 2
R178 33
1 2
R169 @33
CLK_ICH14
CLK_SIO14
CLK_DAC14
1 2
R221 33
CLK_ICH4820
3 3
CLK_ICH1420
CLK_SIO1427
CLK_DAC1430
12
CLK_14M
Y3
14.318MHZ
+3V_CLK = 40mils
U12
2
XTAL_IN
3
XTAL_OUT
40
SEL2
55
SEL1
54
SEL0
25
PWR_DWN#
34
PCI_STOP#
53
CPU_STOP#
28
VTT_PWRGD#
43
MULT0
29
SDATA
30
SCLK
33
3V66_0/DRCG
35
3V66_1/VCH_CLK
42
IREF
39
48MHZ_USB
38
48MHZ_DOT
56
REF
W320-04
or ICS 9508-05
+3V_CLK
1
32
37
14
VDD_PCI8VDD_PCI
VDD_REF
VDD_3V6619VDD_3V66
VDD_48MHZ
66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2
GND_REF4GND_PCI9GND_PCI15GND_3V6620GND_3V6631GND_48MHZ36GND_IREF41GND_CPU
+3VS_VDD48M = 10mils
50
26
VDD_CORE
VDD_CPU46VDD_CPU
27
GND_CORE
45
CPUCLKT2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
PCICLK_F2
PCICLK_F1
PCICLK_F0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
44
49
48
52
51
24
23
22
21
7
6
5
18
17
16
13
12
11
10
CPU_CLKC2
66MHZ_IN/3V66_5
47
+3VS_CLKVDD
12
C281
.1UF
CLK66MCH
CLK66AGP
CLKICHHUB
CLKPCI_SIO
CLKPCI_LAN
CLKPCI_CB
CLKPCI_LPC
CLKPCI_DBC
+3VS_VDD48M
L33
BLM21A601SPT
1 2
12
C300
10UF_10V_1206
CLK_BCLK
CLK_BCLK#
CLK_HT
CLK_HT#
CLK_ITP
CLK_ITP#
1 2
R222 33
1 2
R215 33
1 2
R188 33
R214 33
1 2
R209 33
1 2
1 2
R205 33
R202 33
1 2
1 2
R196 33
+3VS_VDD48M
12
+3VS
1 2
R204 33
RD1
RD2
1 2
R208 33
1 2
R195 33
RD3
RD4
1 2
R201 33
1 2
R180 33
RD5
RD6
1 2
R185 33
Place caps. near
CK_Titan (U10)
L34
12
C274
.1UF
R219 33
C301
10UF_10V_1206
1 2
R206 49.9_1%_0603
1 2
R211 49.9_1%_0603
1 2
R190 49.9_1%_0603
1 2
R200 49.9_1%_0603
1 2
R176 49.9_1%_0603
1 2
R184 49.9_1%_0603
1 2
12
12
C268
C270
@10PF
@10PF
1 2
BLM21A601SPT
12
C275
@10PF
+3VS
CLK_HCLK 4
Place resistor near RD1,RD2
;Trace<=400mils
CLK_HCLK# 4
CLK_GHT 7
Place resistor near RD3, RD4
;Trace<=400mils
CLK_GHT# 7
CLK_ITPP 5
Place resistor near RD5, RD6
;Trace<=400mils
CLK_ITPP# 5
CLK_AGP_MCH 7
CLK_AGP 14
CLK_ICHHUB 20
CLK_ICHPCI 20
CLK_LPC_SIO 27
CLK_PCI_LAN 24
CLK_PCI_CB 25
CLK_LPC_EC 32
CLK_PCI_DBC 27
+5VS
2
G
1 3
D
4 4
SMB_CLK20,22
A
S
Q19 2N7002
+5VS
2
G
1 3
D
S
Q20 2N7002
B
DIMM_SMDATA 10,11SMB_DATA20,22
DIMM_SMCLK 10,11
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE
C
D
E
F
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-1521
401229
星期一 十一
G
?04, 2002
1B
of
13 43,
H
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