Compal LA-1441 ATW05, Satellite 1200 Schematic

A B C

1 1

D

E

ATW05

2 2

LA-1441 REV0.2 Schematics Document

uFCBGA/uFCPGA Coppermine-T or
Tualatin CPU

with Almador-MG
chipset

3 3

4 4

Compal Electronics, Ltd.

Title

Cover Sheet

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

1 43Wednesday, March 06, 2002

E

0.2

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

A B C

BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

4 4

CRT CONN.

PAGE 16

Mobile Tualatin
or
Coppermine-T

(uFCBGA/uFCPGA)

PAGE 4,5,6

PSB

Thermal Sensor
MAX1617MEE

PAGE 5

CK TITAN
ICS9250-38

PAGE12

CPU VID & All
reference voltage

PAGE 7

Almador-M

LVDS CONN.

PAGE 16

3 3

USB Port

HDD Connector

VCH
CONN.

PAGE 27

PAGE 20

GM Bus Interface

PAGE 15

USB

ATA 66/100

CD-ROM Connector

PAGE 20

2 2

LPC

GMCH-M

625 BGA

PAGE 8,9,10,11

HUB Interface

ICH3-M

421 BGA

PAGE 17,18,19

Memory Bus

PCI BUS

SO-DIMM * 2

BANK 2,3,4,5

LAN

RTL8100-L

PAGE 21

Mini PCI
Socket

PAGE 28

CardBus
TI

PCI1420

PAGE 23

PAGE 13,14

Slot 0/1

PAGE 24

FAN on controller &
TEMP. sensing circuit

PAGE 35

DC/DC Interface
RTC Battery

PAGE 37

BATTERY

Super I/O

LPC47N227

PAGE 25

1 1

Parallel

PAGE 26

FIR

PAGE 26

FDD

PAGE 20

Embedded
Controller

NS PC87591

PAGE 33

Scan KB

PAGE 15

BIOS & I/O
PORT

PAGE 34

C

AC'97
CODEC
CS4299

PAGE 31

Audio Jack

PAGE 32

Audio Amplifier

PAGE 32

D

Compal Electronics, Ltd.

Title

Block Digram

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

Charger

POWER
Interface

PAGE 40,42,43,44

PAGE 41

E

2 43Wednesday, March 06, 2002

0.2

檔

A B C

Voltage Rails

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

PIR

Power Plane Description

1 1

B+
+VCC_H_CORE
+VTT

VIN

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus
+1.5V 1.5V power rail ON ON OFF
+1.5VS

AGP 4X ON OFF OFF
+1.8V 1.8V power rail ON ON OFF
+1.8VS
+2.5V
+3VALW
+3V
+3VS
+5VALW
+5V ON
+5VS

2 2

+12VALW
+12VS
RTCVCC

1.8V switched power rail

2.5V power rail

3.3V always on power rail ON*

3.3V power rail

3.3V switched power rail

5V always on power rail

5V power rail

5V switched power rail

12V always on power rail

12V switched power rail

RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

S1 S3 S5

N/A N/A N/A

N/AN/AN/A
ON OFF
ON OFF

ON
ON
ON
ON
ON
ON ON

ON
ON
ON
ON

OFF
ON
ON
ON
OFF

ON
OFF
ON
OFF
ON

OFF

OFF

OFF

OFF

OFF

OFF

ON*

OFF

OFF

ON*

OFF

ON

REV 0.1

Date Page Description

0201 10 R229 change 225 to 255
0204 31 Add R564 @2.2K on pin 3 of MicPhone Jack

42 Modify PU10 pin 11 error

REV 0.2

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

LAN

Mini-PCI

AD20

AD17

AD18

2

PIRQA/PIRQB

3 PIRQB

1/4

PIRQC/PIRQD

3 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

0001 011X b
1010 000X b
1011 000Xb

EC SM Bus2 address

Device

MAX1617MEE
Smart Battery
Docking
DOT Board

1001 110X b
0001 011X b
0011 011X b
XXXX XXXXb

ICH3-M SM Bus address

Device

4 4

Clock Generator ( ICS9238-50)
SDRAM Select ( 74HC4052 )
CPU Voltage VID select ( F3565 )

Address

1101 0000
1010 0000
0110 111Xb

Compal Electronics, Ltd.

Title

Notes & PIR

Size Document Number Rev
Custom

LA-1441

C

D

Date: Sheet of

3 43Wednesday, March 06, 2002

E

0.2

檔

A

1 1

AF23

AD23

B11

A10
A13

C12
C10

A15
A14
B13
A12

AA3

W2

AB3
C14
AF4

C22

AA2

K1

J1
G2
K3

J2
H3
G1
A3

J3
H1
D3
F3
G3
C2
B5

C6
B9
B7
C8
A8

B3
A9

C3

A6

R1
L3
T1
U1
L1
T4

P3

A7
C4

R2
L2
V3

U2
T3

U9A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

TUALATIN

H_A#[3..31]<8>

2 2

H_REQ#[0..4]<8>

H_ADS#<8>

3 3

H_BPRI#<8>

H_BNR#<8>

H_LOCK#<8>

H_HIT#<8>

H_HITM#<8>

H_DEFER#<8>

H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#[0..4] H_D#33

+1.5VS

R331 1.5K

1 2

R87 10

1 2

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

+VCC_H_CORE

D22

F22

VCC_0

VCC_1

Request

Interface

Arbitration

B

E21

H22

G21

K22

VCC_2

VCC_3

VCC_4

Address

Lines

Signals

Error

Signals

Snoop

Signals

VSS_0

VSS_1

VSS_2

E16R4E25

G25

C

J21

M22

L21

P22

N21

T22

R21

V22

U21

Y22

W21

AB22

AA21

AC21

D20

F20

E19

AB20

AA19

AC19

D18

F18

E17

AB18

AA17

AC17

D16

F16

E15

AB16

AA15

AC15

D14

F14

E13

AB14

AA13

AC13

D12

F12

E11

AB12

AA11

AC11

D10

F10E9AB10

AA9

AC9D8F8E7AB8

AA7

VCC_5

VCC_6

VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_61

VCC

Mobile

Tualatin

VSS VCC

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

J25

L25

N25

R25

U25

W25

AA25

AC25

AF25

AE26

C23

F23

H23

K23

M23

P23

T23

V23

Y23

AB23

AE23

B22

D21

F21

E22

H21

G22

K21

J22

M21

L22

P21

N22

T21

R22

V21

U22

Y21

W22

AB21

AA22

AC22

AE21

B20

D19

AB19

AA20

AC20

AE19

B18

D17

F17

E18

AB17

D

AC7D6F6E5H6G5K6J5N5T6V6

VCC_62

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_69

VCC_70

Data

Signals

VCC_80

VCC_79

VCC_78

VCC_77

VCC_76

VCC_75

VCC_74

VCC_73

U5Y6W5

AB6

AA5

AC5M6P6

E

H_D#[0..63]

H_D#0

A16

VCC_71

VCC_72

D#0

H_D#1

B17

D#1

H_D#2

A17

D#2

H_D#3

D23

D#3

H_D#4

B19

D#4

H_D#5

C20

D#5

H_D#6

C16

D#6

H_D#7

A20

D#7

H_D#8

A22

D#8

H_D#9

A19

D#9

H_D#10

A23

D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32

H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] <8>

+VCC_H_CORE

4 4

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Mobile Tualatin Micro-FCPGA

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

4 43Wednesday, March 06, 2002

E

0.2

檔

A

B

C

D

E

+VTT

+1.8VS

+1.5VS

+1.5VS

12

1 1

2 2

3 3

4 4

Place H_RESET#
R3<0.1" from U1

H_FERR#<17>

H_PWRGD<17>

H_RESET#<8>

H_PICD0<17>
H_PICD1<17>

C70

2200PF

12

+5VALW

R61

56.2_1%

R53 @0
1 2
1 2

R64 @0

1 2

A

12

R325

1.5K

+1.5VS

R62
150

H_THERMDA
H_THERMDC

R80

1K

R335

12

+VS_CMOSREF

C40
.1UF

1 2

12

12

R336

3K

1.5K

+1.5VS

12

R55
150

CLK_CPU_APIC<12>

PM_CPUPERF#<17,19>

1 2

U8

1

NC

2

VCC
DXP

SMBCLK
DXN
NC

SMBDATA

ADD1

ALERT
GND
GND NC

MAX6654

STBY

ADD0

3
4
5
6
7
8 9

Thermal Sensor

H_IGNNE#<17>

H_STPCLK#<17>

H_DPSLP#<17,43>

+1.5VS

R44

200

NC

NC

H_TRDY#<8>

H_A20M#<17>

H_DBSY#<8>

H_DRDY#<8>

H_BSEL0<10,12>
H_BSEL1<12>

H_RS#0<8>
H_RS#1<8>
H_RS#2<8>

H_SMI#<17>

H_INTR<17>

H_NMI<17>

H_INIT#<17>

C39

@10PF

16
15
14
13
12
11
10

1 2

@33_0402

R482 1.5K

1 2

1 2

R517 200

1 2

R68 56.2_1%

Note :
GHI# Pull-Up internally

+5VALW

12

R50
1K

+5VALW

H_A20M#

H_IGNNE#

H_INTR
H_NMI

H_THERMDA
H_THERMDC

1 2

R280

110_1%

R41

ITP_TRST#

12

R49
10K

AC3
AF6
AF5
AD9
AD3
AB4
AE4

AF8
AD15
AE14

AE6

B15

AF13
AF14

AE12
AF10
AF16

AD19
AD17
AF20

AF22
AE20
AD22
AD21

AD10

AD7
AD11

AF7
AF15
AF19
AE22

AF12

AD5
AE16

B

AA18

AC18

AE17

B16

D15

F15

AB15

AA16

AC16

AE15

B14

D13

F13

E14

AB13

AA14

AC14

AE13

B12

D11

F11

E12

U9B

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

Y3

RS#0

V1

RS#1

U3

RS#2

M5

Request

RSP#

W1

Signals GND

TRDY#

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#

Compatibility

DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#

W3

DBSY#

Y1

DRDY#

THERMDA
THERMDC

SELFSB0
SELFSB1
EDGECTRLP

PICD0

L5

+VTT

PICD1
PICCLK

RP2#
RP3#
BPM0#
BPM1#

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

CMOSREF_1
CMOSREF_0
RTTIMPDEP

GHI#

VCCT_1

A26

G23

APIC

Debug
Break

Point

Test

Access

PORT
( ITP )

VCCT_3

VCCT_2

J23

L23

VCCT_4

N23

VCCT_8

VCCT_7

VCCT_6

VCCT_5

R23

U23

W23

AA23

EC_SMC2 <32,40>

VSS_73

VCCT_10

VCCT_11

VCCT_12

VCCT_13

VCCT_14

VCCT_15

VCCT_9

C21

C19

AD20

C17

AD18

C15

AB11

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VCCT VID

VCCT_16

VCCT_17

VCCT_18

VCCT_19

VCCT_20

VCCT_21

VCCT_22

C13

AD14

C11

AD12C9C7

AD8C5AD6

From 87591

EC_SMD2 <32,40>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AA12

AC12

AE11

B10D9F9

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VCCT_23

VCCT_24

VCCT_25

VCCT_26

VCCT_27

AC23

AA4E4G4J4L4

C

E10

AB9

AA10

AC10

AE9B8D7F7E8

AB7

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

Mobile

Tualatin

VCCT_28

VCCT_29

VCCT_30

VCCT_31

VCCT_32

VCCT_33

VCCT_34

VCCT_35

VCCT_36

VCCT_37

AC4V4AE3

AF2

AF1

AE18D5E6

AA8

AC8

AE7B6F5H5G6K5J6N6L6T5R6V5U6Y5W6

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VCCT_38

VID0

VID1

VID2

VID3

VID4

VSS

AB1

AC2

AE2

AF3R3B26M4AF26C1AF17

AB5

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS

VSSNCNC

NC

N4

CPU_VR_VID4 <7>
CPU_VR_VID3 <7>
CPU_VR_VID2 <7>
CPU_VR_VID1 <7>
CPU_VR_VID0 <7>

D

AA6

AC6

AE5B4D4F4H4K4M3U4W4B2D2F2H2

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

AD2

AE1

A25

C25

E20

F19

+3VS

12

R100
10K

12

C105
.1UF

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

AE24

DEP#0

AD25

DEP#1

AE25

DEP#2

AC24

DEP#3

AF24

DEP#4

AD26

DEP#5

Data

Signals

VTT Ref

Analog

NCHCTRLP

VTTPWRGOOD

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

+3V

147

U36F

Title

Size Document Number Rev
Custom

Date: Sheet of

AC26

DEP#6

AD24

DEP#7

AF21

VREF_1

AB26

VREF_2

H26

VREF_3

A21

VREF_4

AF9

VREF_5

A4

VREF_6

N1

VREF_7

AA1

VREF_8

Y4

TESTLO

R5

VCC

N3

PLL1

N2

PLL2

P1

NC

P5

NC

E1

NC

F1

NC

AC1

CLK0

AD1

CLK0#

M1

TESTLO

AF18

NC

AD16
AF11

TESTHI

AE8

NC

N24

NC

AE10

NC

E2

TESTHI

P4

NC

AD4

NC_1

A5

NC_2

D1

NC_3

AD13

NC_4

B1

NC_5

P26

NC_6

A11

NC_7

E3

D26

NC

VSS_130

TUALATIN

K2M2P2T2V2Y2AB2

1213

74LVC14

Compal Electronics, Ltd.

Mobile Tualatin Micro-FCPGA

LA-1441

TESTHI1
TESTHI2

+V_AGTLREF

TESTLO1

+

CLK_HCLK
CLK_HCLK#
TESTLO2

TESTHI1

TESTHI2

CPUVTT_PWRGD

2

+VCC_H_CORE

C520
33UF_16V_D2

R76 14_1%

1 2

+VTT

12

R99
10K

13

VTT_PWRGD# <12,32>VTT_PWRGD<44>

E

RP23
1 8
2 7
3 6
4 5

8P4R_1K

1 2

L30 4.7UH

CLK_HCLK <12>
CLK_HCLK# <12>

CPUVTT_PWRGD

Q6

2N7002

5 43Wednesday, March 06, 2002

+VTT

TESTLO1
TESTLO2

+VTT

+VTT

0.2

檔

A B C

D

E

Layout note :

Place close to CPU, Use 2~3 vias per PAD.

1 1

Place .47uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Layout note :

Place close to CPU,
Use 2 vias per PAD.

+VCC_H_CORE

12

12

12

12

12

12

12

12

12

12

12

C388

C389

C391

C392

C393

C394

C395

C396

C397

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

+VCC_H_CORE

12

12

12

12

12

12

12

12

C434

C425

C411

C433

C424

C421

.47UF

.47UF

.47UF

.47UF

12

C448
10UF_10V_1206

12

C30
10UF_10V_1206

12

C519

+

150UF_6.3V_D2

.47UF

2 2

+VCC_H_CORE

12

C450
10UF_10V_1206

+VCC_H_CORE

12

C445
10UF_10V_1206

3 3

+VCC_H_CORE

12

C536

+

150UF_6.3V_D2

+VCC_H_CORE

12

C449
10UF_10V_1206

12

C117
10UF_10V_1206

12

C537

+

150UF_6.3V_D2

.47UF

12

C447
10UF_10V_1206

12

C38
10UF_10V_1206

12

C549

+

150UF_6.3V_D2

.47UF

C525

C432

.47UF

12

C446
10UF_10V_1206

12

C33
10UF_10V_1206

12

C538

+

150UF_6.3V_D2

12

.47UF

.47UF

C409

C398

.47UF

12

C420

.47UF

12

C390

C412

.47UF

.47UF

12

12

C408

C431

.47UF

.47UF

+VTT

12

+

+VTT

12

1UF_10V_0603

C45
220UF_4V_D2

1UF_10V_0603

12

C32

C34

12

C513

+

220UF_4V_D2

1UF_10V_0603

12

C37

1UF_10V_0603

12

C41

1UF_10V_0603

1UF_10V_0603

12

C43

12

C48

12

C59

1UF_10V_0603

1UF_10V_0603

12

C67

12

C72

1UF_10V_0603

12

C79
1UF_10V_0603

12

C310

+

150UF_6.3V_D2

4 4

12

C309

+

150UF_6.3V_D2

12

C308

+

150UF_6.3V_D2

12

C314

+

150UF_6.3V_D2

12

C313

+

150UF_6.3V_D2

12

C297

+

150UF_6.3V_D2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Ltd.

Title

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

6 43Wednesday, March 06, 2002

E

0.2

檔

A

B

C

D

E

Tualatin

D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)

CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

1 1

CPU Voltege ID

Default for Resistors Should
be +VCC_CPU = 0.7V, for
Deeper Sleep Only.

SMB_CLK<12,14,17>

SMB_DATA<12,14,17>

CPU_VR_VID0<5>
CPU_VR_VID1<5>

From Tualatin CPU

2 2

PM_GMUXSEL = 1 : for Performance mode

PM_DPRSLPVR = 1: for Deeper Sleep mode

3 3

SpeedStep function Note for SMT

CPU_VR_VID2<5>
CPU_VR_VID3<5>
CPU_VR_VID4<5>

PM_DPRSLPVR<17,43>

PM_GMUXSEL<17,43>

1 2

R173

@10K

+3VS

0 : for CPU default power

0 : for Performance mode

R321
@10K

182736

12

1
2

U49
NC7SZ02

45

RP30
@8P4R_10K

+3V

1 2

3 5

.1UF

+3V

C647

12

R172
@100K

4

1
1

Override#

1

Address 0110 111X

U17

1

SCL

2

ASEL

SDA

3

Override#

4

I_0

5

MUX_SEL

I_1

6

I_2

7

I_3

8

I_4

9

A/B#

10

GND

FM3565

MUX_SEL

MUX_SEL

1
0

0

VCC

+3V

C213

1 2

.1UF

R460 0

20
19

1 2
1 2

18

WP

NC

Y_0
Y_1
Y_2
Y_3
Y_4

A/B#

17
16
15
14
13
12
11

X
0

1

R461 0

CPU_VID0 <43>
CPU_VID1 <43>
CPU_VID2 <43>
CPU_VID3 <43>
CPU_VID4 <43>

MUX_outputs Mode
MUX_inputs

From
Non-volatile
register(SOPRB)
From
Non-volatile
register(SOPRA)

Battery

Performance

Deeper sleep

Support SpeedStep :

Stuffed : U17, U49, R460, R461
Not Stuffed : RP30, R321

-------------------------------------------------------­0 0 1 1 1 1.40V (Performance)
0 1 1 0 0 1.15V (Battery)
1 0 1 0 1 0.85V (Deeper Sleep)

+3V

System Memory Reference

12

R302

249_1%

49.9_1%

301_1%

249.9_1%

Place capacitor close to GMCH.

12

12

R297

R308

+1.8VS

12

12

C467
.1UF

HUB Interface Reference

Layout note :

1. Place R308 and R296 in middle of Bus.

2. Place capacitors near GMCH.

12

C453

R296

.1UF

301_1%

+V_SMREF

+VS_HUBREF

+VTT

12

12

+1.5VS

12

12

+VAGP_BRDREF

GTL Reference Voltage

R303

Layout note :

1K_1%

1. Place R303 and R322 between and GMCH and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

R322
2K_1%

12

C514
.1UF

12

C35
.1UF

12

C27
.1UF

12

C71
.1UF

CMOS Reference Voltage

R288

Layout note :

1K_1%

1. Place R288 and R291 between and GMCH and CPU.

2. Place decoupling caps near CPU.

12

R291
2K_1%

Place Reference Circuit near GMCH

C439
.1UF

+1.5VS

12

12

12

C440
.1UF

R376
1K_1%

R370
1K_1%

C578

1 2

C555

1 2

470PF

470PF

+V_AGTLREF

+VS_CMOSREF

12

R373

82.5_1%

12

R365

82.5_1%

Without Support SpeedStep :

R93

301_1%

R94

301_1%

+1.8VS

HUB Interface VSwing Voltage

12

1. Place R93 and R94 in middle of Bus.

12

C97
.1UF

+VS_HUBVSWING

12

D

Stuffed : RP30, R321
Not Stuffed : U17, U49, R460, R461

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

+1.8VS

12

R275

576_1%

1. Place R275 and R274 near GMCH.

12

R274

2K_1%

Compal Electronics, Ltd.

Title

CPU VID & All Reference Voltage

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

+VS_RIMMREF

7 43Wednesday, March 06, 2002

E

0.2

檔

A B C

M12

M13

M17

M18

N12

N13

N14

N15

N16

N17

N18

P13

P14

P15

P16

P17

R13

R14

R15

R16

R17

T13

T14

T15

T16

T17

U12

U13

U14

U15

U16

U17

U18

V12

V13

V17

V18

1 1

2 2

3 3

4 4

H_D#[0..63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

HUB_PD[0..10]<17>

HUB_PSTRB<17>

HUB_PSTRB#<17>

U7A

U4

H_D#0

P1

H_D#1

W6

H_D#2

U2

H_D#3

U6

H_D#4

R1

H_D#5

N3

H_D#6

W5

H_D#7

V4

H_D#8

P3

H_D#9

R3

H_D#10

U1

H_D#11

V6

H_D#12

W4

H_D#13

T3

H_D#14

P2

H_D#15

V3

H_D#16

R2

H_D#17

T1

H_D#18

W3

H_D#19

U3

H_D#20

Y4

H_D#21

AA3

H_D#22

W1

H_D#23

V1

H_D#24

Y1

H_D#25

Y6

H_D#26

AD3

H_D#27

AB4

H_D#28

AB5

H_D#29

V2

H_D#30

Y3

H_D#31

Y2

H_D#32

AA4

H_D#33

AA1

H_D#34

AA6

H_D#35

AB1

H_D#36

AC4

H_D#37

AA2

H_D#38

AB3

H_D#39

AD2

H_D#40

AD1

H_D#41

AC2

H_D#42

AB6

H_D#43

AC6

H_D#44

AC1

H_D#45

AF3

H_D#46

AD4

H_D#47

AD6

H_D#48

AC3

H_D#49

AH3

H_D#50

AE5

H_D#51

AE3

H_D#52

AG2

H_D#53

AF4

H_D#54

AF2

H_D#55

AJ3

H_D#56

AE4

H_D#57

AG1

H_D#58

AE1

H_D#59

AG4

H_D#60

AH4

H_D#61

AG3

H_D#62

AF1

H_D#63

ALMADOR-M

+VS_HUBREF

12

.01UF

C476

VSS0

VSS1

VSS2

VSS3

VSS4

Host

Interface

HUB_PD5

HUB_PD4

HUB_PD3

HUB_PD2

HUB_PD1

HUB_PD0

G26

H28

H29

H27

F29

F27

HUB_PD5

HUB_PD4

HUB_PD3

HUB_PD2

HUB_PD1

HUB_PD0

R246 54.9_1%
R92 27.4_1%

1 2

R83 54.9_1%

1 2

VSS5

VSS6

VSS7

VSS8

VSS9

VSS11

VSS10

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS

Almador-M
GMCH

A3

AGP_RCOMP/DVOBC_RCOMP

RESET#

H_GTLREF1

H_GTLREF0

AB24

AA7J7C2

H_GTLRCOMP

12

C469
.1UF

R78 54.9_1%

12

C470
.1UF

12

SM_RCOMP

HUB_RCOMP

DVO_RCOMP

HUB_REF

AC22F6J23

+VAGP_CRDREF

AGP_REF

J25

K24

C

HUB_PSTRB#

HUB_PD10

HUB_PSTRB

HUB_PD9

HUB_PD8

HUB_PD7

HUB_PD6

E29

E28

G25

G27

H26

G29

H24

F28

HUB_PD10

HUB_PD9

HUB_PD8

HUB_PD6

HUB_PD7

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

VSSPCMOS_LM0

VSS

VSS

AB23

AC23

AH19

1 2

R91 80.6_1%

+V_AGTLREF

C471
.1UF

12

AJ5D2AC5Y5U5P5L5H5AH2

VSS36

VSS35

VSS34

VSS33

VSSPCMOS_LM1

VSSPCMOS_LM2

VSSP_HUB0

AH20

AF5

G28

H25

VSS_H5

VSS_H4

VSS_H3

VSS_H2

VSS_H1

VSS_H0

VSSP_HUB1

VSSP_IO0

VSSP_IO1

VSSP_IO2

AC26

AD22

AE28

PCIRST# <15,17,19,20,21,22,23,24,25,28,29,34>

10 mils wide,length <=500 mils.

VSS_H7

VSS_H6

VSSP_DVO0

AH24

AE2

AB2W2T2N2K2G2AC7

VSS_H9

VSS_H8

VSS_H10

VSSP_DVO1

VSSP_DVO2

AF25

AF27

D

VSS_H11

VSS_H12

VSS_H13

Interface

VSSA_DAC

AH26G8AD7

D

VSS_H14

Host

VSS_H15

VSS_H16

VSSA_CPLL

VSSA_HPLL

E

H_A#[3..31]

H_A#3

H2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_CPURST#

H_ADS#
H_BNR#

H_BPRI#

H_DBSY#

H_DEFER#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

CLK_HT

CLK_HT#

CLK_DREF

CLK_GBIN

CLK_GBOUT

H_A#4

E3

H_A#5

G3

H_A#6

N4

H_A#7

M6

H_A#8

F1

H_A#9

F2

H_A#10

J3

H_A#11

F3

H_A#12

P6

H_A#13

G1

H_A#14

N5

H_A#15

H1

H_A#16

P4

H_A#17

T4

H_A#18

M2

H_A#19

J2

H_A#20

L2

H_A#21

R4

H_A#22

K1

H_A#23

L3

H_A#24

L1

H_A#25

J1

H_A#26

N1

H_A#27

T5

H_A#28

H3

H_A#29

M3

H_A#30

M1

H_A#31

K3

1 2

R290 @0

R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4

H_REQ#0

K6

H_REQ#1

M4

H_REQ#2

K5

H_REQ#3

K4

H_REQ#4

L6

H_RS#0

H6

H_RS#1

H4

H_RS#2

G6

AJ4
AH5

AC19
AG26
AD24

R242

@33_0402

1 2

1 2

C322

@10PF

Compal Electronics, Ltd.

Title

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

1 2

R26047

R276
@33_0402

C381
@10PF

Close to Ball R6.

H_REQ#[0..4]

H_RS#[0..2]

.01UF
C373

1 2

CLK_GHT <12>
CLK_GHT# <12>

R158
240K

Closely to C.G

E

H_A#[3..31] <4>H_D#[0..63]<4>

H_RESETX#
H_RESET# <5>
H_ADS# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <5>
H_DEFER# <4>
H_DRDY# <5>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <5>
H_REQ#[0..4] <4>

H_RS#[0..2] <5>

CLK_DREF <12>
CLK_GBIN <12>
CLK_GBOUT <12>

8 43Wednesday, March 06, 2002

0.2

檔

A

AD8

AD9

AD10

AJ21

AE8

AE9

AE10

AE11

AE12

AE13

AE17

AE19

AH21

AF8

AF9

AF10

AF11

AF12

VSS_LM

VSS_LM

VSSP_SM14

VSSP_SM15

E22

E25G9G21E4D28

VSS_LM

VSSP_SM16

+VTT

AF13

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_SM17

VSSP_SM18

VSSP_SM19

U7B

SM_DQ0
SM_DQ1
SM_DQ2

1 1

SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30

2 2

SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

3 3

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_DQ[0..63]

4 4

D29

SM_DQ0

C29

SM_DQ1

D27

SM_DQ2

C27

SM_DQ3

A27

SM_DQ4

B26

SM_DQ5

E24

SM_DQ6

C25

SM_DQ7

E23

SM_DQ8

B25

SM_DQ9

C23

SM_DQ10

F22

SM_DQ11

B23

SM_DQ12

C22

SM_DQ13

E21

SM_DQ14

B22

SM_DQ15

C12

SM_DQ16

D10

SM_DQ17

C11

SM_DQ18

A10

SM_DQ19

C10

SM_DQ20

C8

SM_DQ21

A7

SM_DQ22

E9

SM_DQ23

C7

SM_DQ24

E8

SM_DQ25

A5

SM_DQ26

F8

SM_DQ27

C5

SM_DQ28

D6

SM_DQ29

B4

SM_DQ30

C4

SM_DQ31

E27

SM_DQ32

C28

SM_DQ33

B28

SM_DQ34

E26

SM_DQ35

C26

SM_DQ36

D25

SM_DQ37

A26

SM_DQ38

D24

SM_DQ39

F23

SM_DQ40

A25

SM_DQ41

G22

SM_DQ42

D22

SM_DQ43

A23

SM_DQ44

F21

SM_DQ45

D21

SM_DQ46

A22

SM_DQ47

F11

SM_DQ48

A11

SM_DQ49

B11

SM_DQ50

F10

SM_DQ51

B10

SM_DQ52

B8

SM_DQ53

D9

SM_DQ54

B7

SM_DQ55

F9

SM_DQ56

A6

SM_DQ57

C6

SM_DQ58

D7

SM_DQ59

B5

SM_DQ60

E6

SM_DQ61

A4

SM_DQ62

D4

SM_DQ63

ALMADOR-M

SM_DQ[0..63] <14>

VSS_LM

SDRAM
System
Memory

VSSP_SM0

VSSP_SM1

VSSP_SM2

B3B6B9

B12

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS Power

VSSP_SM3

VSSP_SM4

VSSP_SM5

VSSP_SM6

VSSP_SM7

VSSP_SM8

VSSP_SM9

VSSP_SM10

VSSP_SM11

VSSP_SM12

VSSP_SM13

B15

B18

B21

B24

B27E7E10

E13

E16

E19

B

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AG7

AG15

AG16

AG21

AH6

AH8

AH9

AH11

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS

Almador-M
GMCH

A3

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

H7

H23K7K23L7N6T6W7Y7AB7

M24

P24

T24

V24

C

VSSA_DPLL0 <10>
VSSA_DPLL1 <10>

AH12

AH14

AH17

AH18

K28

N28

T28

W28

AB28

L25

P25

U25

Y25

AE20

G24

SM_D_MA0

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_AGP0

VSSP_AGP1

VSSP_AGP2

VSSP_AGP3

VSSP_AGP4

VSSP_AGP5

VSSP_AGP6

VSSP_AGP7

VSSP_AGP8

VSSA_DPLL0

VSSA_DPLL1

SDRAM
System
Memory

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8

SM_MA9
SM_MA10
SM_MA11
SM_MA12

VCC_SM
VCC_SM

SM_BA0
SM_BA1

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

VCCQ_SM

SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

VCC_SM

VSS
VSS

VSS

VSS
VSS

VSS

A20

SM_D_MA1

B20

SM_D_MA2

B19

SM_D_MA3

C19

SM_D_MA4

A18

SM_D_MA5

A19

SM_D_MA6

C17

SM_D_MA7

C18

SM_D_MA8

B17

SM_D_MA9

A17

SM_D_MA10

A16

SM_D_MA11

C15

SM_D_MA12

C14

F20

NC

E20

NC

F12

NC

E11

NC

C21
F19
E12
A12

B16
C16

SM_DQM0

F18

SM_DQM1

D18

SM_DQM2

D13

SM_DQM3

D12

SM_DQM4

E18

SM_DQM5

F17

SM_DQM6

F14

SM_DQM7

F13

SM_CS#0

E17

SM_CS#1

F16

SM_CS#2

D16

SM_CS#3

D15
E15
E14

SM_D_CLK0

A15

SM_D_CLK1

B2

SM_D_CLK2

B14

SM_D_CLK3

A3
A14
C3

SM_CKE0

A13

SM_CKE1

C9

SM_CKE2

C13

SM_CKE3

A9
B13
A8

SM_D_MA[0..12]

XOR layout note:
F20,E20,F12,E11 add
testpoint for
factory

R319 10

1 2

R310 10

1 2

C452 .1UF

1 2

1 2

C512 .1UF

+3V

+3V

D

SM_D_MA[0..12] <13>

+3V

SM_BA0 <14>
SM_BA1 <14>
SM_DQM[0..7] <14>

SM_CS#0 <14>
SM_CS#1 <14>
SM_CS#2 <14>
SM_CS#3 <14>

SM_D_CLK0
SM_D_CLK1
SM_D_CLK2
SM_D_CLK3

SM_CKE0 <14>
SM_CKE1 <14>
SM_CKE2 <14>
SM_CKE3 <14>

R254 0

1 2

R306 0

1 2

*
*

VSSA_DPLL0
VSSA_DPLL1

Layout note :

Place resistors & capacitors near GMCH

R318 10

1 2

R313 10

1 2

R317 10

1 2

R315 10

1 2

12

12

C506
@33PF

C516
@33PF

12

E

C515
@33PF

12

C517
@33PF

SMD_CLK0 <14>
SMD_CLK1 <14>
SMD_CLK2 <14>
SMD_CLK3 <14>

Layout note :

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SM_VREF0

SM_VREF1

C24

E5

Y23

M14

M15

M16

P12

R12

F24

T12

P18

R18

T18

Line length 0.15 inches +- 50mils

12

C494
.1UF

SM_OCLK

SM_RCLK

A24

12

C493
.1UF

SM_RAS#

SM_CAS#

SM_W E#

C20

D19

A21

SM_OCLK

SM_RCLK

Layout note :

+V_SMREF

Close to Ball E5 and F24

1.Placement TP6 for Almador-M A2 stepping die.

2.The 0.1uF capacitor and connection to +3V
must be implanted for Almador-M A3 stepping
die.

R312 10

1 2

R311 10

1 2

R316 10

1 2

1 2

C507 @22PF

Layout note :

SM_RAS# <14>
SM_CAS# <14>
SM_WE# <14>

near pin C24

A

檔

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

9 43Wednesday, March 06, 2002

E

0.2

A

Layout note :

Place close to AE16,
AE15 of GMCH

1 1

AGP_SBA[0..7]<15>

AGP_CBE#[0..3]<15>

AGP_ADSTB0<15>

AGP_ADSTB#0<15>

AGP_ADSTB1<15>

2 2

3 3

4 4

AGP_ADSTB#1<15>

AGP_SBSTB<15>
AGP_SBSTB#<15>
AGP_FRAME#<15>

AGP_IRDY#<15>
AGP_TRDY#<15>
AGP_STOP#<15>

AGP_DEVSEL#<15>

AGP_REQ#<15>

AGP_GNT#<15>

AGP_PAR<15>

AGP_AD[0..31]<15>

AGP_PAR : Strapping option for SW detection of
AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device

+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_AD[0..31]

AGP_PAR

R272

1 2

@8.2K

A

AGP_ADSTB0
AGP_ADSTB#0
AGP_ADSTB1
AGP_ADSTB#1
AGP_SBSTB
AGP_SBSTB#
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_DEVSEL#
AGP_REQ#
AGP_GNT#
AGP_PAR

1 2

R279

330

12

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

C413
68PF

U7C

AA29

AGP_SBA0/ZV_D8

AA24

AGP_SBA1/ZV_D7

AA25

AGP_SBA2/ZV_D6

Y24

AGP_SBA3/ZV_D5

Y27

AGP_SBA4/ZV_D2

Y26

AGP_SBA5/ZV_D1

W24

AGP_SBA6/ZV_D0

Y28

AGP_SBA7/ZV_HREF

L27

AGP_CBE#0/DVOB_D7

P29

AGP_CBE#1/DVOB_BLANK#

R27

AGP_CBE#2/ZV_VSYNC

T25

AGP_CBE#3/DVOC_D5

L29

AGP_ADSTB0/DVOB_CLK

L28

AGP_ADSTB#0/DVOB_CLK#

U29

AGP_ADSTB1/DVOC_CLK

U28

AGP_ADSTB#1/DVOC_CLK#

AA27

AGP_SBSTB/ZV_D4

AA28

AGP_SBSTB#/ZV_D3

R29

AGP_FRAME#/M_DDC1_DATA

P26

AGP_IRDY#/M_I2C_CLK

P27

AGP_TRDY#/M_DDC1_CLK

N25

AGP_STOP#/M_DDC2_DATA

R28

AGP_DEVSEL#/M_I2C_DATA

AC27

AGP_REQ#/ZV_CLK

AD29

AGP_GNT#/ZV_D15

P28

AGP_PAR/DVO_DETECT

J29

AGP_AD0/DVOB_HSYNC

J28

AGP_AD1/DVOB_VSYNC

K26

AGP_AD2/DVOB_D1

K25

AGP_AD3/DVOB_D0

L26

AGP_AD4/DVOB_D3

J27

AGP_AD5/DVOB_D2

K29

AGP_AD6/DVOB_D5

K27

AGP_AD7/DVOB_D4

M29

AGP_AD8/DVOB_D6

M28

AGP_AD9/DVOB_D9

L24

AGP_AD10/DVOB_D8

M27

AGP_AD11/DVOB_D11

N29

AGP_AD12/DVOB_D10

M25

AGP_AD13/DVOBC_CLKINT#

N26

AGP_AD14/DVOB_FLD/STL

N27

AGP_AD15/M_DDC2_CLK

R25

AGP_AD16/DVOC_VSYNC

R24

AGP_AD17/DVOC_HSYNC

T29

AGP_AD18/DVOC_BLANK#

T27

AGP_AD19/DVOC_D0

T26

AGP_AD20/DVOC_D1

U27

AGP_AD21/DVOC_D2

V27

AGP_AD22/DVOC_D3

V28

AGP_AD23/DVOC_D4

U26

AGP_AD24/DVOC_D7

V29

AGP_AD25/DVOC_D6

W29

AGP_AD26/DVOC_D9

V25

AGP_AD27/DVOC_D8

W26

AGP_AD28/DVOC_D11

W25

AGP_AD29/DVOC_D10

W27

AGP_AD30/DVOBC_INTR#/DPMS_CLK

Y29

AGP_AD31/DVOC_FLD/STL

ALMADOR-M

AGP_PIPE#<15>
AGP_WBF#<15>

AGP_RBF#<15>

AGP_ST[0..2]<15>

B

+VTT

V14

V15

V16

AE16

AE15

AD15

AD16

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

AGP

Interface

(DVOB/DVOC & ZV port)

AGP_PIPE#/ZV_D10

AGP_WBF#/ZV_D9

AGP_RBF#/ZV_D11

AGP_ST0/ZV_D14

AGP_ST1/ZV_D13

AB26

AB29

AB25

AC28

AC29

AB27

AGP_PIPE#
AGP_WBF#
AGP_RBF#

AGP_ST[0..2]

B

AGP_ST2

AGP_ST0

AGP_ST1

C

+1.5VS

+1.8VS

+3V

AE25

AD23

J24

VDD_LM

VCCP_IO

VCCP_IO

VCCP_HUB

C330 .1UF

C483 .1UF

F26

N24

W23

J26

M26

VCCP_HUB

VCCP_AGP

VCCP_AGP

VCCQ _A GP

VCCQ _A GP

+VTT

+3V

12
12

R26

V26

AA26

L23

AA23

U24

AE6G7G10

G20

AF6

VCCQ _S M

VCCP_AGP

Interface

VCCA_CPLL

VCCA_HPLL

Power

VCCQ _S M

VCCPCM OS _L M

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

+1.8VS

AE7

AC9

VCCPCM OS _L M

AC8

VCCPCM OS _L M

VCCPCM OS _L M

0_0805

1 2

R277

12

C383
.01UF

+VTT

AF26

AG27F5J5M5R5V5AA5

VCC_H

VCC_H

VCCA_DAC

VCCA_DAC

+1.8VS

12

12

C384
.1UF

C283
@.1UF

+1.5VS

AD5

AG5

E2

AC20

F25

AC21

AF21

VCC_H

VCC_H

VCC_H

VCC_H

VCCP_DVO

VCCP_DVO

VCCA_DPLL0

VCCA_DPLL1

Display

Interface

12

VCC_H

VCC_H

VCC_H

(DVOA port)

Almador-M
GMCH

A3

Local Memory
Interface

Local Memory
Interface

LM_CMD

LM_SCK

LM_SIO

LM_RQ0

LM_RQ1

LM_RQ2

LM_RQ3

LM_RQ4

LM_RQ5

LM_RQ6

AGP_ST2/ZV_D12

AH7

AF7

AJ7

AG11

AJ12

LM_RQ7

AG12

AH13

AG13

AJ13

AG14

AJ14

AJ6

LM_CTM

LM_RCLK

AG6

LM_CTM #

LM_GCLK

LM_RAMREF0

LM_RAMREF1

LM_CFM

LM_CFM #

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCQ _S M

VCCQ _S M

VCCP_SM

VCCQ _S M

VCCP_SM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

AD14

AE14

AH15

AJ15

AJ16

AH16

D5D8D11

D14

D17

D20

D23

D26F7F15

G11

G19

G23

AC10

AC11

AD11

AD12

AD13

AE18

AD17

AD18

R234 10K

1 2

R239 10K

1 2

12

C340
.1UF

C

12

C328
.1UF

**

C282
@.1UF

@220UF_4V_D2

AF24

DAC_VSYNC

DAC_HSYNC

VCCP_DVO

DAC_RED#

DAC_GREEN#

DAC_BLUE#

DAC_RED

DAC_GREEN

DAC_BLUE

IO_DDC1CLK

IO_DDC1DATA

DAC_REFSET

DVO_CLKIN

DVO_BLANK#

DVO_VSYNC
DVO_HSYNC

IO_I2CCLK

IO_I2CDATA

DVO_CLK#

DVO_CLK

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

IO_DDC2DATA

IO_DDC2CLK

DVO_INTR#
DVO_FIELD

LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
LM_DQA5
LM_DQA6
LM_DQA7

LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7

AGP_BUSY#

VCC_LM

AD19

+3V

+VS_RIMMREF

C286

D

D

**

@220UF_4V_D2

*

AE29
AD28
AF28
AG28
AH27
AF29
AG29
AH28
AE27
AD27
AJ27

AD20
AD21
AF23
AF22
AD25
AC25
AG24
AJ24

AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26

AD26
AE26
AE21
AE22

AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20

AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8

AC24

+1.8VS

E

VSSA_DPLL0 <9>
VSSA_DPLL1 <9>

C285

L3 0_0805
1 2
1 2

L4 0_0805

IO_DDC1CLK

IO_DDC1DATA

AGP_BUSY#

12

R301 0
1 2
1 2

R299 0

R269 @2.2K

+1.5VS

R226 2.2K

R240 @2.2K

1 2

R229 255_1%
DVOA_CLKIN

R261 10K
R263 10K

DVOA_D0
DVOA_D1

DVOA_D4
DVOA_D5
DVOA_D6

DVOA_INTR#

DVOA_FIELD

XOR layout note: AE24,AJ25
add testpoint for factory

R251 10K
R250 10K

C354
68PF

Title

Size Document Number Rev
Custom

Date: Sheet of

Strap Name Low High
DVOA_D0 Reserved 133MHz
DVOA_D1 IOQD=2 IOQD=8

+VTT

DVOA_D5 Desktop Mobile

*

DVOA_D6 Dual Ended Term Single Ended Term

**

1 2
1 2

1 2

DAC_VSYNC <16>
DAC_HSYNC <16>
DAC_RED# <16>
DAC_GREEN# <16>
DAC_BLUE# <16>
DAC_RED <16>
DAC_GREEN <16>
DAC_BLUE <16>

VCH_I2CDATA <15>
VCH_I2CCLK <15>

1 2
1 2

TV_OUT_DDC2DATA<15>
TV_OUT_DDC2CLK <15>

1 2
1 2

R257

1 2

@10K

AGP_BUSY# <15,17>

DVOA_D6
DVOA_D5

DVOA_D0

R252 10K

1 2

R262 10K

1 2

R551 0

1 2

R552 0

1 2

+3VS

DVOA_CLKIN
DVOA_INTR#

DVOA_FIELD

+3VS

+3VS

*

1 2

R232@2.2K

R551,R552: No stuff in AGP mode,
Stuff in VCH mode

Compal Electronics, Ltd.

Almador-M GMCH

LA-1441

E

H_BSEL0 <5,12>

+3VS

AGP_DDCCLK <15,16>
AGP_DDCDATA <15,16>

+1.5VS

R259 100K

1 2

R255 100K

1 2

R256 10K

1 2

10 43Wednesday, March 06, 2002

0.2

檔

A B C

D

E

Layout note :

Distribute as close as possible
to GMCH Processor Quadrant .

+VTT

1 1

2 2

3 3

+VTT

+VTT

+

+VTT

+

+VTT

+

+VTT

12

12

12

12

12

12

12

C353
.1UF

12

C437
.1UF

C127
220UF_4V_D2

C80
220UF_4V_D2

C36
220UF_4V_D2

12

C475
.1UF

C327
.1UF

C454
.1UF

C484
.1UF

12

C350
.1UF

12

C466
.1UF

12

12

C405
.1UF

12

12

C410
.1UF

12

12

C380
.1UF

12

C490
.1UF

12

C404
.1UF

C463
.1UF

C401
.1UF

12

C357
.1UF

C474
.1UF

C504
.1UF

C358
.1UF

12

C427
.1UF

12

C403
.1UF

12

C473
.1UF

12

C422
.1UF

12

C402
.1UF

12

12

12

12

C343
.1UF

12

C435
.1UF

12

C418
.1UF

12

C81
.1UF

12

C441
.1UF

12

C414
.1UF

12

12

C344

C387

.1UF

.1UF

12

12

C460

C438

.1UF

.1UF

12

12

C436

C429

.1UF

.1UF

12

12

C74

C28

.1UF

.1UF

12

12

C456

C451

.1UF

.1UF

12

12

C417

C464

.1UF

.1UF

12

C407

C419

.1UF

.1UF

12

12

C459

C462

.1UF

.1UF

12

12

12

C386

C372

.1UF

.1UF

12

12

C88

C31

.1UF

.1UF

12

12

C465

C458

.1UF

.1UF

12

C399

C423

.1UF

.1UF

12

12

C78

C83

.1UF

.1UF

12

12

C468

C472

.1UF

.1UF

Layout note :

Distribute as close as possible
to VCCPCMOS_LM .

+1.8VS

12

C302

+

22UF_16V_1206

12

C363
.1UF

Layout note :

Distribute as close as possible
to GMCH Local Memory Quadrant .

+1.8VS

12

C345
82PF

12

+

22UF_16V_1206

C301

12

Layout note :

Distribute as close as possible
to GMCH AGP/DVO Quadrant .

+1.5VS

12

+

22UF_16V_1206

C287

12

12

C336
.1UF

Layout note :

Distribute as close as possible
to GMCH System Memory Quadrant .

+3V

12

+

22UF_16V_1206

C523

12

12

C477
.1UF

C359
.1UF

C335
.1UF

C482
.1UF

12

C364
.1UF

12

12

C360

C361

.1UF

82PF

12

12

C379

C382
.1UF

82PF

12

12

C481

C503
.1UF

82PF

12

C365
.01UF

12

12

C355

C356

.1UF

.1UF

12

12

C415
C400
.1UF

82PF

12

12

C501
C502
.1UF

82PF

12

+

12

12

C298
68UF_4V_B2

12

C366
.1UF

12

C500
.1UF

12

C406
.1UF

C489
.1UF

C334
.01UF

+

12

C299
68UF_4V_B2

12

C428
82PF

12

C496
82PF

12

12

+

C442
.1UF

C498
.1UF

12

C319
68UF_4V_B2

12

C244
.1UF

12

C495
.1UF

12

C320

+

@68UF_4V_B2

12

C457
82PF

12

C497
82PF

12

C300

+

@68UF_4V_B2

12

C443
.1UF

12

12

12

C480
.1UF

C479
.1UF

C491
.1UF

12

C505
.1UF

Layout note :

+VTT

12

C62

+

220UF_4V_D2

4 4

12

C106

+

220UF_4V_D2

Distribute as close as possible
to IO Quadrant .

+3V

12

C524

+

22UF_16V_1206

12

C499
.1UF

12

C511
.1UF

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Ltd.

Title

GMCH-M Decoupling

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

11 43Wednesday, March 06, 2002

E

0.2

A B C

D

E

+3VS

Check Bead Value
should be 19.6K

1 1

+3VS

+3VS

+3VS

12

12

12

R146
10K

H_BSEL1<5>
H_BSEL0<5,10>

2 2

CLK_ICH48<17>

3 3

CLK_DREF<8>

CLK_ICH14<17>
CLK_SIO14<25>

12

R145
@0

12

12

R110
1K

R112
@0

C135
@10PF

12

12

R111
1K

SEL2
SEL1
SEL0

R114
@0

VTT_PWRGD#<5,32>

C148
@10PF

Place Crystal within 500 mils of CK_Titan

C118 5PF

1 2

caps are internal
to CK_TITAN

1 2

C129 5PF

PM_SLP_S1#<17,32>
PM_SLP_S3#<17,32>

PM_STPPCI#<17>

PM_STPCPU#<17>

+3V

SMB_DATA<7,14,17>

SMB_CLK<7,14,17>

+3V

CLK_VCH<15>

R137 220_1%

R141 22

R149 22

R108 33
R109 33

Place caps. near
CK Titan (U5)

R528 0

R529 @0

R116 0
R562 10K

+3VS

D47

RB751V

R138 10K

R157 4.7K

1 2

1 2

R154 4.7K
R151 33

1 2

R151: No stuff in AGP mode
Stuff in VCH mode

1 2

* 221_1%

1 2

* 33

1 2

* 33

1 2
1 2

12

1 2

1 2

1 2
1 2
21

1 2

Y1

14.318MHZ

L6
CHB2012U170

1 2

2

40
55
54

25
34
53

28

43

29
30

33
35

42

39

38

56

U10

XTAL_IN

SEL2
SEL1
SEL0

PWR_DWN#
PCI_STOP#
CPU_STOP#

VTT_PWRGD#

MULT0

SDATA
SCLK

3V66_0/DRCG
3V66_1/VCH_CLK

IREF

48MHZ_USB

48MHZ_DOT

REF

ICS950805

+3V_CLK

181419323746

VDD_REF

GND_REF

491520313641

Width=40 mils

VDD_PCI

VDD_PCI

VDD_3V66

VDD_3V66

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

GND_3V66

GND_PCI

GND_3V66

GND_PCI

12

+

C115

22UF_16V_1206

50

VDD_CORE

VDD_CPU

VDD_CPU

VDD_48MHZ

GND_COREXTAL_OUT

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1
CPUCLKT0

CPUCLKC0

66MHZ_IN/3V66_5

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

GND_CPU

GND_48MHZ

GND_IREF

47

12

C130
.01UF

26

273
45

44
49

48
52

51
24

23
22
21

7
6
5

18
17
16
13
12
11
10

C152

C133

.01UF

.01UF

12

12

+

C128

C120

22UF_16V_1206

.01UF

R153 33

1 2

R150 33

1 2

R147 33

1 2

R119: Stuff in AGP mode
No stuff in VCH mode

R119 33

1 2

R118 33

1 2

R115 @33

1 2

R143 33

1 2

R144 33

1 2

R140 33

1 2

R136 @33

1 2

R125 @33

1 2

R121 33

1 2

R122 33

1 2

12

12

12

C121
.01UF

L5
CHB2012U170

1 2

CLK_BCLK

CLK_BCLK#
CLK_GCLK

CLK_GCLK#

12

12

C122
.01UF

PCIF1
PCIF0

12

C124

C155

.01UF

.01UF

+3VS

Place all these Block's
Components near CK_Titan(U5)

1 2

R324 33

12

12

R334
475_1%

R34
475_1%

1 2

R329 61.9_1%

R328 61.9_1%

1 2
1 2

R323

1 2

R32 33

1 2

R33 61.9_1%

R31 61.9_1%

1 2

R30 33

1 2

12

C147
@10PF

12

12

C156
.01UF

C149
@10PF

12

C123
.01UF

CLK_HCLK <5>

Place all these Block's
Components near CPU (U1)

33

12

C150
@10PF

CLK_HCLK# <5>
CLK_GHT <8>

CLK_GHT# <8>

CLK_GBOUT <8>

CLK_AGPCONN <15>
CLK_GBIN <8>
CLK_ICHHUB <17>

CLK_ICHPCI <17>

CLK_PCI_CB <23>
CLK_PCI_LAN <21>
CLK_LPC_SIO <25>
CLK_PCI_1394 <22>
CLK_PCI_SD/SM <29>
CLK_LPC_EC <32>
CLK_MINIPCI <28>

Place caps. near
CK_Titan (U5)

Place all these Block's
Components near GMCH (U6)

12

@33_0402

@10PF

C154

R155

Place near CPU

R36 26.7_1%

PCIF1

1 2

SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]

1 0 0 66.67 66.67
1 0 1 100.00 100.00
1 1 0 200.00 200.00
1 1 1 133.33 133.33

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

PCIF0

12

R35

137_1%

D

1 2
R351
@51.1_1%

Title

Size Document Number Rev
Custom

Date: Sheet of

12

R352
0_0603
0 ohm resistor for ICH3 doesn't
need to support APIC function.

Compal Electronics, Ltd.

Almador-M GMCH CLOCK GENERATOR

LA-1441

348_1%

CLK_CPU_APIC <5>
CLK_ICHAPIC <17>

12 43Wednesday, March 06, 2002

E

0.2

檔

A

SM_DQ[0..63]<9,14> MD[0..63] <9,14>

B

C

D

E

SM_DQ1 MD1

1 1

2 2

3 3

SM_DQ3 MD3

SM_DQ18 MD18

SM_DQ20 MD20
SM_DQ21 MD21

SM_DQ23 MD23

SM_DQ24 MD24
SM_DQ26 MD26

SM_DQ28 MD28
SM_DQ29 MD29
SM_DQ30 MD30

MD0SM_DQ0
MD2SM_DQ2

MD4SM_DQ4
MD5SM_DQ5
MD6SM_DQ6
MD7SM_DQ7

MD8SM_DQ8
MD9SM_DQ9
MD10SM_DQ10
MD11SM_DQ11

MD12SM_DQ12
MD13SM_DQ13
MD14SM_DQ14
MD15SM_DQ15

MD16SM_DQ16
MD17SM_DQ17

MD19SM_DQ19

MD22SM_DQ22

MD25SM_DQ25 MD57SM_DQ57
MD27SM_DQ27

SM_DQ38 MD38
SM_DQ39 MD39

SM_DQ40 MD40
SM_DQ41 MD41

SM_DQ44 MD44

SM_DQ56 MD56

SM_DQ59 MD59

SM_DQ60 MD60
SM_DQ61 MD61
SM_DQ62 MD62

MD32SM_DQ32
MD33SM_DQ33
MD34SM_DQ34
MD35SM_DQ35

MD36SM_DQ36
MD37SM_DQ37

MD42SM_DQ42
MD43SM_DQ43

MD45SM_DQ45
MD46SM_DQ46
MD47SM_DQ47

MD48SM_DQ48
MD49SM_DQ49
MD50SM_DQ50
MD51SM_DQ51

MD52SM_DQ52
MD53SM_DQ53
MD54SM_DQ54
MD55SM_DQ55

MD58SM_DQ58

MD63SM_DQ63MD31SM_DQ31

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .

+3V

12

C192
.1UF

+3V

12

C119

+

22UF_16V_1206

C167

1000PF

12

C168
.1UF

C184

1000PF

12

C164
.1UF

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .

+3V

12

C212
.1UF

+3V

12

C126

+

22UF_16V_1206

C211

1000PF

12

C205
.1UF

C210

1000PF

12

C206
.1UF

C169

1000PF

C207

1000PF

C199

1000PF

C166

1000PF

12

C196
.1UF

12

C215
.1UF

12

C170
.1UF

12

C222
.1UF

C195

1000PF

C221

1000PF

12

C194
.1UF

12

C220
.1UF

C190

1000PF

C219

1000PF

12

C189
.1UF

12

C218
.1UF

C188

1000PF

C217

1000PF

12

C209
.1UF

12

C160
.1UF

C216

1000PF

C165

1000PF

12

C203

C202

1000PF

.1UF

12

C214

C187

1000PF

.1UF

SM_D_MA[0..12]<9> MAA[0..12] <14>

SM_D_MA0
SM_D_MA1
SM_D_MA2
SM_D_MA3

SM_D_MA4
SM_D_MA5
SM_D_MA6
SM_D_MA7

SM_D_MA8
SM_D_MA9
SM_D_MA10

4 4

SM_D_MA11

SM_D_MA12

A

RP22
1 8
2 7
3 6
4 5

8P4R_10

RP21
1 8
2 7
3 6
4 5

8P4R_10

RP20
1 8
2 7
3 6
4 5

8P4R_10
1 2

R176 10

MAA0
MAA1
MAA2
MAA3

MAA4
MAA5
MAA6
MAA7

MAA8
MAA9
MAA10
MAA11

MAA12

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SODIMM Damping & Decoupling

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

13 43Wednesday, March 06, 2002

E

0.2

檔

A

SO-DIM 144 PINS
RAM MODULE CONN.

MD0

1 1

MAA[0..12]<13>

MD[0..63]<9>

SM_DQM[0..7]<9>

2 2

3 3

MAA[0..12]

MD[0..63]
SM_DQM[0..7]

SMD_CLK0<9>

SM_RAS#<9>
SM_WE#<9>
SM_CS#0<9>
SM_CS#1<9>

MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

R174

C204

10PF

22

SM_RAS# SM_CAS#
SM_WE# SM_CKE1
SM_CS#0 MAA12
SM_CS#1

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM0 SCKDIMM0

BANK 0/1

+3V +3V

JP26

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144-STANDRD

DIMM0

4 4

+3V

RP4

SCKDIMM1

1 8

SCKDIMM0

2 7

SDADIMM1

3 6

SDADIMM0

4 5

8P4R_10K

A

B

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0
A12/BA1

A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

B

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
SCL

A3
A4
A5

A7

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

PROPRIETARY NOTE

C

+3V+3V

C142

+

10UF_10V_1206

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

SM_DQM1
SM_DQM5

MAA3
MAA4
MAA5

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

SM_CKE0

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

SM_BA0
SM_BA1

SM_DQM3
SM_DQM7

MD56
MD57
MD58
MD59

MD60
MD61
MD62
MD63

SM_CKE0 <9>

SM_CKE1 <9>

R175
22

C223
10PF

SM_BA0 <9>
SM_BA1 <9>

SM_SEL0<17>

SMB_CLK<7,12,17>

SMB_DATA<7,12,17>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C143

+

10UF_10V_1206

SMD_CLK1 <9>

C230

6

INH

10

A

9

B

3

X

13

Y

.1UF

+3V

7

C

16

GND

8

+3V

X0
X1

VCC

X2
X3

GND

C132

+

10UF_10V_1206

SMD_CLK2<9>

U18

1
5
2
4

12

Y0

14

Y1

15

Y2

11

Y3

74HC4052

SM_CS#2<9>
SM_CS#3<9>

SCKDIMM0
SCKDIMM1

SDADIMM0
SDADIMM1

BANK 2/3

+3V +3V

MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

C163

R162

10PF

22

SM_RAS# SM_CAS#

SM_WE# SM_CKE3
SM_CS#2 MAA12
SM_CS#3

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM1

SM_SEL0 X/Y

0 SCKDIMM0

SCKDIMM11

JP27

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144 REVERSE

D

DIMM1

D

E

2

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

DQ40
DQ41
DQ42
DQ43

DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

RFU/CKE1

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

A11/BA0
A12/BA1

A13/A11

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC
RFU

RFU
RFU

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS
SCL

VCC

A3
A4
A5

A7

MD8

4

MD9

6

MD10

8

MD11

10
12

MD12

14

MD13

16

MD14

18

MD15

20
22

SM_DQM1

24

SM_DQM5

26
28

MAA3

30

MAA4

32

MAA5

34
36

MD40

38

MD41

40

MD42

42

MD43

44
46

MD44

48

MD45

50

MD46

52

MD47

54
56
58
60

SM_CKE2

62
64
66
68
70
72
74
76
78
80
82

MD24

84

MD25

86

MD26

88

MD27

90
92

MD28

94

MD29

96

MD30

98

MD31

100
102
104

SM_BA0

106
108

SM_BA1

110
112
114

SM_DQM3

116

SM_DQM7

118
120

MD56

122

MD57

124

MD58

126

MD59

128
130

MD60

132

MD61

134

MD62

136

MD63

138
140

SCKDIMM1

142
144

SM_CKE2 <9>
SM_CAS# <9>

SM_CKE3 <9>

R170
22

C193
10PF

SMD_CLK3 <9>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

S.O. DIMM CONNECTOR

B

LA-1441

E

14 43Wednesday, March 06, 2002

0.2

檔