Compal LA-1391 ATR11, Satellite 1905 Schematic

COMPAL CONFIDENTIAL

MODEL NAME :ATR11 LA-1391

REV:1.0

CRT & TV-OUT
LCD

PAGE 18

Pentium4/Northwood
mPGA478 CPU

PAGE 2,3

PSB

CLOCK

ICS950805

PAGE 11

INTERNAL IDE

IDE/CD
/FDD

PAGE 25

USB/BlueTooth

LPT PORT
MDC

ATI
M6P

16MB DD R SDRAM

PIRQA#

Direct CD
Play

PAGE 24

PAGE 27

LPC 47 N227

PAGE 26

PAGE 1 4, 15,16,17

HUB Link

ICH2

FUNC 0: LAN, HUB-TO-PCI ,
PCI-TO-LPC BRIDGE
FUNC 1: IDE Controller

FUNC 2: USB Controller #1
FUNC 3: SM BUS Controller
FUNC 4: USB Controller #2
FUNC 5: AC97 Audio Controller
FUNC 5: AC97 Modem Controller

LPC

SIO

PAGE 27

PAGE 1 0,11,12

EC/KBC

PC87591

EC BUFFER

PCI BUS

LPC

PAGE 31

BIOS

PAGE 31 PAGE 30

PROPRIETARY NOTE

Brookdale
MCH

Host-AGP Bridge
DRAM controller
Hub interface

1394 Controller

TAB43AB22

AC LINK

AC97 Codec

PAGE 29 PAGE 30

PAGE 4,5,6

IDSEL: AD26
MASTER 2
PIRQC#

PAGE 19

MDC
Connector

PAGE 25

MEMORY BUSAGP BUS

AMP &
Audio
Jack

IDSEL: AD16
MASTER 3
PIRQA#, PIRQB#
SIRQ

CARDBUS

OZ6933

PCMCIA
SOCKET

DDR DIMM*2

PAGE 7,8

LAN Controller

INTEL PHY

PAGE 20

PAGE 20

Switchs &
Connectors

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

POWER
INTERFACE

PAGE 35

IDSEL: AD27
MASTER 0
PIRQA#,
PIRQD#

Mini PCI
Connector

PAGE 22

PAGE 23

DC/DC POWER

+1.5V POWER
+1.8V POWER
+2.5V POWER
+3VA L W POWER
+5VA L W POWER
+12VALW POWER
CPU_VCC POWER

PAGE 36,37,38,39,40,41

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size Do cum e nt Number R e v

B

401211

Dat e : Sheet

期二 十一月

of

144¬P , 26, 2002

1B

A

CPU_VCC

1 2

R274 51_1%

1 2

R91 56

1 2

R280 300_1%

1 2

R290 51_1%

4 4

RP5

1 8
2 7
3 6
4 5

8P4R-1K

3 3

CPU_VCC

2 2

1 1

SELPSB[1:0] STSEM BUS FREQUENCY

CPURST#

FERR#

CPU_PW RGD

ITP_TMS
ITP_TRST#
ITP_TCK
ITP_TDI

1 2

R250 51_1%

1 2

R251 51_1%

1 2

R262 51_1%

1 2

R253 51_1%

1 2

R254 51_1%

1 2

R263 51_1%

00
01
10
11

BREQ0#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

A

100MHZ
RESERVED
RESERVED
RESERVED

CPU_PWRGD10

HREQ#04
HREQ#14
HREQ#24
HREQ#34
HREQ#44

ADSTB0#4
ADSTB1#4

BREQ0#4

BPRI#4
HLOCK#4
HIT#4
HITM#4
DEFER#4
DRDY#4

CPURST#4

HTRDY#4

CPU_VCC

BSEL013
BSEL113

DBSY#4

CPUSLP#10

HA#[3..31]4

ADS#4

BNR#4

RS#04
RS#14
RS#24

HA#[3..31]

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

BREQ0#

CPURST#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK

1 2

R82 @62_1%

BSEL0
BSEL1

CPU_PW RGD
CPUSLP#

THERMDA
THERMDC
THERMTRIP#

AB1

AC1
AA3
AC3

K25
K26
L25

AB25

AB2
AC6

AB5
AC4

AA5
AB4

AF26

AD6

AD5
AE25
AB23

AB26

W1

W2

J26

K2
K4
L6
K1
L3

M6

L2
M3
M4
N1
M1
N2
N4
N5

T1
R2

P3

P4
R3

T2
U1

P6
U3

T4

V2
R6

T5
U4

V3

Y1

J1

K5

J4
J3

H3

L5
R5

G1

V5

G2

H6

D2

G4

F3

E3

E2
H2

V6

J6
F1
G5
F4

Y6

D5
C1
F7
E6
D4
C3

H5

B3
C4
A2

U23A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADSTB0#
ADSTB1#

ADS#
AP0#
AP1#
BINIT#
BNR#
IERR#
DP0#
DP1#
DP2#
DP3#
BREQ0#
BPRI#
LOCK#
HIT#
HITM#
DEFER#
DRDY#
MCERR#
RESET#
TRDY#
RS0#
RS1#
RS2#
RSP#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

SKTOCC#
TDO
TDI
TMS
TRST#
TCK
PROCHOT#

BSEL0
BSEL1
DBSY#
DBR#

PWRGOOD
SLP#

THERMDA
THERMDC
THERMTRIP#

mPGA478

B

ADDR GROUP

CONTROL GROUP

THERMAL DIODE

B

Northwood

MISC

PROPRIETARY NOTE

C

HD#[0..63]

HD#0

B21

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#

DATA GROUP

HOST CLK

LEGACY CPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DBI0#
DBI1#
DBI2#
DBI3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

BCLK0
BCLK1

ITPCLK0
ITPCLK1

A20M#
FERR#

IGNNE#

INTR/LINT0

NMI/LINT1

INIT#

STPCLK#

SMI#

B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

E21
G25
P26
V21

E22
K22
R22
W22
F21
J23
P23
W23

AF22
AF23

AC26
AD26

C6
B6
B2
D1
E5

W5
Y4
B5

HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

A20M#
FERR#
IGNNE#
INTR
NMI

C

HD#[0..63] 4

SB_A20M#

SB_IGNNE#

SB_INTR

SB_NMI NMI

DBI0# 4
DBI1# 4
DBI2# 4
DBI3# 4

DSTBN0# 4
DSTBN1# 4
DSTBN2# 4
DSTBN3# 4
DSTBP0# 4
DSTBP1# 4
DSTBP2# 4
DSTBP3# 4

HCLK_CPU 13
HCLK_CPU# 13

FERR# 10

CPUINIT# 10
STPCLK# 10
SMI# 10

2200PF

+5VS

1 2

1 2

1 2

1 2

CPU_VCC

CPU_VCC

12

C104

R67 1K

R95
0

R97
0

R66
0

R65
0

1 2

A20M#

IGNNE#

INTR

R92
@0

1 2

R142 56

1 2

R98 56

12

THERMDA
THERMDC

R93

C71
.1UF

@0

D

1
2
3
4
5
6
7
8

1 8

2 7

3 6

4 5

12

12

12

12

2

THERMTRIP#

D

1617VCC

U5

NC
VCC

STBY

DXP

SMBCLK
DXN
NC

SMBDATA

ADD1

ALERT

GND

ADD0

GND

MAX1617/MAX6654

CPU_VCC

RP7

@8P4R_1K

SB_A20M#10

SB_IGNNE#10

SB_INTR10

SB_NMI10

CPURST#4

R96

R94

@0

@0

+3V

R144
1K

1 2

1 2

1

C

Q8

B

2SC2411K

E

3

16

NC

15
14
13

NC

12
11
10
9

NC

SB_A20M#

SB_IGNNE#

SB_INTR

SB_NMI

1 2

R497
@1K

R145
@0

Compal Electronics, Inc.

Title

Size Do cum e nt Number R e v

Dat e : Sheet

+5VS

12

R38
200

EC_SMC2 24,31

12

R39
1K

2
3

5
6

11
10

14
13

1

C604

@0.22UF

EC_SMD2 24,31

U7

IOA
IOA

IOB
IOB

I1C
I1C

I1D
I1D

S

@QS3257

A20M#
IGNNE#
INTR
NMI

ATF#

+5VS

1 2

SW1 RA TI O SELECT

RATIO
15X
16X
17X
18X
19X
20X
21X
22X
23X
24X

SCHEMATIC, M/B LA-1391

B

401211

NM I A 20M# IGNNE# I N TR

H
L
L
L
L
L
L
L
H
L

THERTRIP# 31
VR_ON 31,41

期二 十一月

VCC

GND

YA

YB

YC

YD

E#

16
4

7

9

12
8

15

1 2

RP6
@8P4R_330

L
H
H
H
H
L
L
L
H
L

E

+3VS

C96

1 2

@.1UF

A20M#

IGNNE#

INTR

NMI

R61 @1K

45
36
27
18

L
H
H
L
L
H
H
L
H
L

E

244¬P , 26, 2002

CPU_VCC

L
H
L
H
L
H
L
H
L
L

1B

of

A

10
9
8
7
6

10
9
8
7
6

+

TESTHI7
TESTHI6
TESTHI5
TESTHI4

1 2

CPUVID

VCCA

C368

+

150U_D

VSSA

VCCIOPLL

CPU_VCC

CPU_VCC

CPU_VCC

TESTHI12

CPU_GTLREF
H_GTLREF

R294

51.1_1%

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

COMP0
COMP1

R59

51.1_1%

1 2

R492
@0

12

C365
1UF

U23B

AD20

VCCA

AD22

VSSA

AE23

VCCIOPLL

A5

VCCSENSE

A4

VSSSENSE

A10

VCC

A12

VCC

A14

VCC

A16

VCC

A18

VCC

A20

VCC

A8

VCC

AA10

VCC

AA12

VCC

AA14

VCC

AA16

VCC

AA18

VCC

AA8

VCC

AB11

VCC

AB13

VCC

AB15

VCC

AB17

VCC

AB19

VCC

AB7

VCC

AB9

VCC

AC10

VCC

AC12

VCC

AC14

VCC

AC16

VCC

AC18

VCC

AC8

VCC

AD11

VCC

AD13

VCC

AD15

VCC

AD17

VCC

AD19

VCC

AD7

VCC

AD9

VCC

AE10

VCC

AE12

VCC

AE14

VCC

AE16

VCC

AE18

VCC

AE20

VCC

AE6

VCC

AE8

VCC

AF11

VCC

AF13

VCC

AF15

VCC

AF17

VCC

AF19

VCC

AF2

VCC

AF21

VCC

AF5

VCC

AF7

VCC

AD24

TESTHI0

AA2

TESTHI1

AC21

TESTHI2

AC20

TESTHI3

AC24

TESTHI4

AC23

TESTHI5

AA20

TESTHI6

AB22

TESTHI7

U6

TESTHI8

W4

TESTHI9

Y3

TESTHI10

A6

TESTHI11

AD25

TESTHI12

AA21

GTLREF

AA6

GTLREF

F20

GTLREF

F6

GTLREF

L24

COMP0

P1

COMP1

A22

RSVD

A7

RSVD

AD2

RSVD

AD3

RSVD

AE21

RSVD

AF3

12

RSVD

AF24

RSVD

AF25

RSVD

mPGA478

12

C379
220PF

12

C72
@220PF

1 2

L6

4.7UH_0805

1 2

L7

4.7UH_0805

RP25

1
2
3
4
5

10P8R-4.7K
RP4

1
2
3
4
5

10P8R-4.7K

12

C392
220PF

12

C65

@220PF

A

C28
150U_D

CPU_VCC

4 4

3 3

TESTHI0
TESTHI1
TESTHI2
TESTHI3

CPU_VCC

TESTHI8
TESTHI9
TESTHI10
TESTHI11

CPU_VCC

CPU_VCC

2 2

R291

49.9_1%

1 2

CPU_GTLREF

12

R287

C388
1UF

100_1%

1 2

CPU_VCC

R62
@49.9_1%

1 2

H_GTLREF

12

R60
@100_1%

1 2

C76
@1UF

1 1

B

PLL ANALOG VOLTAGE

Northwood

POWER,
GROUND,
RESERVED
SIGNALS

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D10
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D12
D14
D16
D18
D20
D21
D24
D3

CPU_VCC

CPU_VCC

CPU_VCC

CPU_VCC

CPU_VCC

CPU_VCC

CPU_VCC

CPU_VCC

12

.1UF

12

1UF

12

C35

10UF_1206

12

C32

10UF_1206

12

C372
10UF_1206

12

C445

10UF_1206

12

C450

10UF_1206

12

C145

10UF_1206

+

C167
470U_E

2.5V

+

C163
470U_E

2.5V

C70

C107

12

C66

.1UF

12

C98
1UF

12

C34

10UF_1206

12

C31

10UF_1206

12

C373

10UF_1206

12

C369

10UF_1206

12

C451

10UF_1206

12

C135

10UF_1206

+

C168

470U_E

2.5V

+

C166
470U_E

2.5V

C

12

C73

.1UF

12

C88

1UF

12

C33

10UF_1206

12

C30

10UF_1206

12

C374

10UF_1206

12

C413

10UF_1206

12

C452

10UF_1206

12

C130

10UF_1206

C

12

C77

.1UF

12

C85

1UF

+

+

C164

470U_E

2.5V

C160

470U_E

2.5V

12

12

C84
.1UF

12

12

C78

1UF

1UF

12

C29

10UF_1206

12

C367

10UF_1206

12

C446

10UF_1206

12

C423

10UF_1206

12

C118

10UF_1206

PROPRIETARY NOTE

12

C87

C97

.1UF

.1UF

CPU_VCC

12

C74

C67

1UF

12

C366

10UF_1206

12

C442

10UF_1206

12

C447

10UF_1206

12

C148

10UF_1206

12

C428

10UF_1206

+

C19

470U_E

2.5V

+

C18

470U_E

2.5V

12

C106

.1UF

12

C370

10UF_1206

12

C443

10UF_1206

12

C448

10UF_1206

12

C147

10UF_1206

12

C418

10UF_1206

+

C359

330U_E

2.5V

+

C105
470U_E

2.5V

CPU_VCC

+

C159

470U_E

2.5V

D

CPU_VID0
CPU_VID1

CPU_VID2
CPU_VID3
CPU_VID4

CPUVID

12

C40
1UF

+

C161

470U_E

2.5V

AF9
B11
B13
B15
B17
B19

B7

B9
C10
C12
C14
C16
C18
C20

C8
D11
D13
D15
D17
D19

D7

D9
E10
E12
E14
E16
E18
E20

E8

F11
F13
F15
F17
F19

AE5
AE4
AE3
AE2
AE1

AF4

Y5
Y25
Y22

Y2

W6

W3
W24
W21

V4
V26
V23

V1

U5
U25
U22

+

C162

470U_E

2.5V

F9

U23C

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VID0
VID1
VID2
VID3
VID4

VCCVID

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

mPGA478

VID[0..4]41

Northwood

POWER, GROUND AND NC

+

C360

330U_E

2.5V

CPU_VID[0..4]

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

CPU_VID4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_VCC

12

12

C103

C41

.1UF

.1UF

12

C371

10UF_1206

12

C444

10UF_1206

CPUVID41

12

C449

10UF_1206

12

C146

10UF_1206

12

C410

10UF_1206

+

C165

470U_E

2.5V

+

C468
330U_E

2.5V

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RP3

1 8
2 7
3 6
4 5

8P4R-1K

R17
1K

E

D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
G6
H1
H23
H26
H4
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2

+3V

12

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size Do cum e nt Number R e v

B

401211

期二 十一月

D

Dat e : Sheet

344¬P , 26, 2002

E

1B

of

A

B

C

D

E

MC-1/3(GTL+,AGP,HUB)

HD#[0 ..6 3 ]2

1 1

2 2

DSTBN0#2
DSTBN1#2
DSTBN2#2

DSTBN3#2

3 3

DSTBP0#2
DSTBP1#2
DSTBP2#2
DSTBP3#2
DBI0#2
DBI1#2

DBI2#2

DBI3#2

CPU_VCC

4 4

HD#[0..63] HA#[3..31]

C81
.1UF

AC11
AC12

AE10

AC10
AE12

AF10
AG11
AG10

AH11
AG12

AE13

AF12
AG13

AH13

AC14

AF14
AG14

AE14
AG15
AG16
AG17

AH15

AC17

AF16

AE15

AH17

AD17

AE16

AE11

AC15

AD11

AC16

AD15

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5

AE9
AC9

AD9
AG9

AD4
AE6

AD3
AE7

AD5
AG4
AH9

BROOKDALE

A

U22A

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBI0#
DBI1#
DBI2#
DBI3#

C82
.1UF

HOST

MCH_GTLREF

ADSTB0#
ADSTB1#

CPURST#

12

12

R63

49.9_1%

R56
100_1%

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8

HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0

RS#1

RS#2

BCLK#

BCLK

HLOCK#
DEFER#

ADS#

BNR#

BPRI#

DBSY#

DRDY#

HIT#

HITM#

HTRDY#

BR0#

RCOMP0
RCOMP1

SWNG0
SWNG1

HVREF
HVREF
HVREF
HVREF
HVREF

SWNG

T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7

U6
T7
R7
U5
U2

W2
W7
W6

R5
N6

K8
J8

AE17
W5
Y4
V3
W3
Y7
V5
V4
Y5
Y3
U7
V7

AC2
AC13
AA7
AD13

M7
R8
Y8
AB11
AB17

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

RCOMP0
RCOMP1

CPU_VCC

HA#[3..31] 2

HREQ#[0..4]

RS#[0..2]

ADSTB0# 2
ADSTB1# 2

CLK_HMCH# 13
CLK_HMCH 13

CPURST# 2
HLOCK# 2
DEFER# 2
ADS# 2
BNR# 2
BPRI# 2
DBSY# 2
DRDY# 2
HIT# 2
HITM# 2
HTRDY# 2
BREQ0# 2

R270 22

1 2

R20 22

1 2

SWNG

MCH_GTLREF

12

R18
300_1%

12

R19
150_1%

B

C43

0.01UF

HREQ#[0 ..4 ] 2

RS#[0..2] 2

PROPRIETARY NOTE

R273 40.2_1%

C83

0.1UF

GAD[0..31]

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
SBSTB
SBSTB#

RBF#
WBF#

AGPREF

1 2

CLK_66M_MCH

C116

0.1UF

GRCOMP

1 2

C109

0.1UF

R27
R28

R25

U27
U28

U23
U24

U25

AA28
AB25
AB27
AA27
AB26

AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

AA23

W28
W27
W24
W23

W25
AG24
AH25
AF22

R24

R23
AC27
AC28
AF27
AF26

AE22
AE23

AA21
AD25
AD26
AD27

12

12

T25
T26

T27

V26
V27
T23

T24

V24
Y27
Y26

Y23

V25
V23
Y25

Y24

P22

R347
10

C473
10PF

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

RBF#
WBF#

AGPREF
GRCOMP
NC
NC

66IN

HUBREF

C110

0.1UF

1 2

U22C

BROOKDALE

+1_8VS

1 2

12

12

R73
150_1%

R69

150_1%

AGP

HUB

1 2

D

TESTIN#

HIREF
HISTB

HISTB#

HLRCOMP

RSTIN#

C117

0.01UF

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

HI10

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9

ST0
ST1
ST2

H26
G9
G10
G16
G17
H6
H7
J23
H27
K23
K25
J25

AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24
P26
N25
N24

+GMCH_HLCOMP

P27

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

AG25
AF24
AG26
J27

R315
0

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HUBREF
HL_STB
HL_STB#

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

ST0
ST1
ST2

1 2

ST0
ST1CLK_66M_MCH
GPAR
AD_STB0#
AD_STB1#
SBSTB#

GAD[0..31]14

GC/BE#014
GC/BE#114
GC/BE#214
GC/BE#314

GFRAME#14

GDEVSEL#14

GIRDY#14

GTRDY#14

GSTOP#14

GPAR14
GREQ#14
GGNT#14

AD_STB014

AD_STB0#14

AD_STB114

AD_STB1#14

SBSTB14

SBSTB#14

RBF#14

AGPREF14

CLK_66M_MCH13

+1_5VS

12

R57
1K

AGPREF

12

R58
1K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HUBREF 10
HL_STB 10

1 2

R304

40.2_1%

R523 2K
R25 @2K
R285 100K
R299 6.8K
R277 6.8K
R275 6.8K

Title

Size Docu ment Number Re v

B

Date: Sheet

HL_STB# 10

+1_8VS

SBA[0..7]

HL[0..10 ]

ST0 14
ST1 14
ST2 14
PCIRST# 10,14,19,20,21,23,25,27,31,34

GTRDY#

R289 6.8K

GIRDY#

R281 6.8K

GDEVSEL#

12
12
12
12
12
12

GSTOP#
GFRAME#
GREQ#
GGNT#
SBSTB
RBF#
PIPE#

WBF#
AD_STB0
AD_STB1
SBSTB
ST1

R279 6.8K
R292 6.8K
R278 6.8K
R269 6.8K
R268 6.8K
R272 @6.8K
R22 6.8K
R21 6.8K
R23 6.8K
R297 @6.8K
R276 @6.8K
R271 @6.8K
R24 @10K

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1391
401211

星期二 十一

?26, 2002

E

SBA[0..7] 14
HL[0..10] 10

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

of

444, 

+1_5VS

1B

A

B

C

D

E

MCH-2/3(SDRAM)

1 1

2 2

3 3

DDR_SMA[0..12]7

DDR_CB[0..7]7

DDR_SMA[0..12]

DDR_SBS07
DDR_SBS17

DDR_CLK07
DDR_CLK0#7
DDR_CLK17
DDR_CLK1#7
DDR_CLK27
DDR_CLK2#7
DDR_CLK38
DDR_CLK3#8
DDR_CLK48
DDR_CLK4#8
DDR_CLK58
DDR_CLK5#8

DDR_SRAS#7
DDR_SCAS#7
DDR_SWE#7

DDR_CKE07
DDR_CKE17
DDR_CKE28
DDR_CKE38

DDR_SCS#07
DDR_SCS#17
DDR_SCS#28
DDR_SCS#38

DDR_SDQS07
DDR_SDQS17
DDR_SDQS27
DDR_SDQS37
DDR_SDQS47
DDR_SDQS57
DDR_SDQS67
DDR_SDQS77
DDR_SDQS87

DDR_CB[0..7]

Length
must equal

1.0"

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

DDR_SBS0
DDR_SBS1

DDR_SRAS#
DDR_SCAS#
DDR_SWE#

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

RDCLK

C631

1 2

@10P_0402

E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

G12
G13

E14
F15

J24

G25

G6

G7
G15
G14
E24
G24

H5

F5
F11

G8
G11

G23
E22
H23
F23

E9

F7

F9

E7
F26

C26
C23
B19
D12

C8

C5

E3
E15

C16
D16
B15
C14
B17
C17
C15
D14

G3

H3

U22B

SMAA0
SMAA1
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAA10
SMAA11
SMAA12

SBS0
SBS1

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

SRAS#
SCAS#
SWE#

SCKE0
SCKE1
SCKE2
SCKE3

SCS#0
SCS#1
SCS#2
SCS#3

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7

RCVENIN#
RCVENOUT#

BROOKDALE

DDR-MEMORY

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8

SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63

SRCOMP

SDREF
SDREF

DDR_SDQ0

G28

DDR_SDQ1

F27

DDR_SDQ2

C28

DDR_SDQ3

E28

DDR_SDQ4

H25

DDR_SDQ5

G27

DDR_SDQ6

F25

DDR_SDQ7

B28

DDR_SDQ8

E27

DDR_SDQ9

C27

DDR_SDQ10

B25

DDR_SDQ11

C25

DDR_SDQ12

B27

DDR_SDQ13

D27

DDR_SDQ14

D26

DDR_SDQ15

E25

DDR_SDQ16

D24

DDR_SDQ17

E23

DDR_SDQ18

C22

DDR_SDQ19

E21

DDR_SDQ20

C24

DDR_SDQ21

B23

DDR_SDQ22

D22

DDR_SDQ23

B21

DDR_SDQ24

C21

DDR_SDQ25

D20

DDR_SDQ26

C19

DDR_SDQ27

D18

DDR_SDQ28

C20

DDR_SDQ29

E19

DDR_SDQ30

C18

DDR_SDQ31

E17

DDR_SDQ32

E13

DDR_SDQ33

C12

DDR_SDQ34

B11

DDR_SDQ35

C10

DDR_SDQ36

B13

DDR_SDQ37

C13

DDR_SDQ38

C11

DDR_SDQ39

D10

DDR_SDQ40

E10

DDR_SDQ41

C9

DDR_SDQ42

D8

DDR_SDQ43

E8

DDR_SDQ44

E11

DDR_SDQ45

B9

DDR_SDQ46

B7

DDR_SDQ47

C7

DDR_SDQ48

C6

DDR_SDQ49

D6

DDR_SDQ50

D4

DDR_SDQ51

B3

DDR_SDQ52

E6

DDR_SDQ53

B5

DDR_SDQ54

C4

DDR_SDQ55

E5

DDR_SDQ56

C3

DDR_SDQ57

D3

DDR_SDQ58

F4

DDR_SDQ59

F3

DDR_SDQ60

B2

DDR_SDQ61

C2

DDR_SDQ62

E2

DDR_SDQ63

G5

SRCOMP

J28
J9

1 2

J21

R525 0_0603

DDR _ S DQ[0..63]

12mil

1 2

R524 30_0603_1%

SDREF

15mil

12

C7220.1U_0402_X7R

DDR_SDQ[0..63] 7

C630

1 2

0.1U_0402_X7R

+1.25VS

C735

10UF_1206_6.3V

SDREF

+2.5V

VS

15mil

12

84

5

+

7

6

-

LM358
U60B

84

3

+

1

2

-

LM358
U60A

C731

R562

R563

0.1UF_16V

0

0

12
12

12

R560

100K_0.5%

12

R561

100K_0.5%

C732

0.01UF

4 4

Compa l E l e c t r onics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

A

B

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

星期二 十一

?26, 2002

E

of

544, 

1B

A

B

C

D

E

MCH-3/3(Power)

U22D

R22

W22

W29
AA22
AA26
AB21

AC29
AD21
AD23
AE26
AF23
AG29

AJ25

M22

AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23

AJ19
AJ21
AJ23

AB19
AB22

AC1

AC4

AF21
AF25

AG1

AG18
AG20
AG22
AH19
AH21
AH23

AJ27
AJ17

R29
U22
U26

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16

L25
L29

N23
N26

A13
A17
A21
A25

C29
D11

D15
D19
D23
D25

F10
F14
F18
F22

G1
G4

G29
H10

H12
H14
H16
H18
H20
H22
H24

K22
K24
K26

L23

M8

AA9
AB8

AJ3
AJ5
AJ7

A5
A9

C1
D7

F6

H8

J5
J7

K6

U8

BROOKDALE

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+1_5VS

1 1

+1_8VS

+2.5V

2 2

3 3

CPU_VCC

4 4

A

VCC1_5
VCC1_5

VSS
VSS

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

POWER/GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

B

T13
T17

U13
U17

A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AJ9
AJ11
AJ13
AJ15

VCCA0
VCCA1

VSSA0
VSSA1

PROPRIETARY NOTE

VCCA0

C391
33U_D

VSSA0

VCCA1

C378
33U_D

VSSA1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+

+

1 2

L31 4.7UH_0805

1 2

L26 4.7UH_0805

12

C86

+

150UF_E

6.3V

C

+1_5VS

+1_5VS

CPU_VCC

C42

+

22UF_10V_1206

+2.5V

12

+

+1_5VS

C92

+

22UF_10V_1206

C425

150UF_E

6.3V

.1UF_0402

C123

4.7UF_0805

.1UF_0402

C47

C101

.1UF_0402

C153

.1UF_0402

.1UF_0402

C46

C95

+1_8VS

+

.1UF_0402

C152

.1UF_0402

.1UF_0402

C94
22UF_10V_1206

C48

C68

.1UF_0402

C126

.1UF_0402

C91

C108

.1UF_0402

.1UF_0402

D

C120
.1UF_0402

C57

.1UF_0402

C149

C112

.1UF_0402

C114
.1UF_0402

.1UF_0402

C125

.1UF_0402

.1UF_0402

C56

C111

C113
.1UF_0402

C59

.1UF_0402

C151

.1UF_0402

C100

.1UF_0402

.1UF_0402

.1UF_0402

C69

.1UF_0402

C154

C122

.1UF_0402

星期二 十一

C124

.1UF_0402

?26, 2002

.1UF_0402

C90
.1UF_0402

Compa l E l e c t r onics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

C127

.1UF_0402

C150

.1UF_0402

E

C115

C121

C134

.1UF_0402

644, 

C144

.1UF_0402

1B

of

A

DDR_SDQ0
DDR_SDQ4

DDR_SDQ5
DDR_SDQ1

DDR_SDQS0

1 1

Layout note

Place these resistor
closely DIMM0,
all trace length<750mil

2 2

3 3

DDR_SDQ[0..63]5
DDR_SD QS [0 ..8 ]5

4 4

A

DDR_SDQ6

DDR_SDQ3
DDR_SDQ2

DDR_SDQ7
DDR_SDQ8

DDR_SDQ13
DDR_SDQ12

DDR_SDQ15
DDR_SDQS1

DDR_SDQ9
DDR_SDQ11

DDR_SDQ14
DDR_SDQ10

DDR_SDQ16
DDR_SDQ20

DDR_SDQ21
DDR_SDQ17

DDR_SDQS2
DDR_SDQ18

DDR_SDQ23
DDR_SDQ22

DDR_SDQ19
DDR_SDQ24

DDR_SDQ29
DDR_SDQ25

DDR_SDQ28
DDR_SDQS3

DDR_SDQ[0..63]

DDR_CB[0..7]5

DDR_CB[0..7]
DDR _ S DQS[0..8]

DDR_SDQ51
DDR_SDQ59

DDR_SDQ63
DDR_SDQ58

DDR_SDQ62
DDR_SDQS7

DDR_SDQ57
DDR_SDQ61

DDR_SDQ60 DDR_DQ60
DDR_SDQ56 DDR_DQ56

B

RP53 4P2R_33
1 4
2 3

RP55 4P2R_33
1 4
2 3

RP57 4P2R_33
1 4
2 3

RP60 4P2R_33
1 4
2 3

RP63 4P2R_33
1 4
2 3

RP66 4P2R_33
1 4
2 3

RP69 4P2R_33
1 4
2 3

RP72 4P2R_33
1 4
2 3

RP75 4P2R_33
1 4
2 3

RP77 4P2R_33
1 4
2 3

RP79 4P2R_33
1 4
2 3

RP81 4P2R_33
1 4
2 3

RP83 4P2R_33
1 4
2 3

RP85 4P2R_33
1 4
2 3

RP87 4P2R_33
1 4
2 3

RP90 4P2R_33
1 4
2 3

RP95 4P2R_33
1 4
2 3

RP97 4P2R_33
1 4
2 3

RP99 4P2R_33
1 4
2 3

RP101 4P2R_33
1 4
2 3

RP103 4P2R_33
1 4
2 3

B

DDR_DQ0
DDR_DQ4

DDR_DQ5
DDR_DQ1

DDR_DQS0
DDR_DQ6

DDR_DQ3
DDR_DQ2

DDR_DQ7
DDR_DQ8

DDR_DQ13
DDR_DQ12

DDR_DQ15
DDR_DQS1

DDR_DQ9
DDR_DQ11

DDR_DQ14
DDR_DQ10

DDR_DQ16
DDR_DQ20

DDR_DQ21
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ23
DDR_DQ22

DDR_DQ19
DDR_DQ24

DDR_DQ29
DDR_DQ25

DDR_DQ28
DDR_DQS3

DDR_DQ51
DDR_DQ59

DDR_DQ63
DDR_DQ58

DDR_DQ62
DDR_DQS7

DDR_DQ57
DDR_DQ61

DDR_SDQ26
DDR_SDQ27

DDR_SDQ30
DDR_SDQ31

DDR_CB5
DDR_CB4

DDR_CB0
DDR_CB2

DDR_SDQS8
DDR_CB6

DDR_CB1
DDR_CB7

DDR_CB3

DDR_SDQ32
DDR_SDQ36

DDR_SDQ37
DDR_SDQ33

DDR_SDQS4
DDR_SDQ39

DDR_SDQ38
DDR_SDQ34

DDR_SDQ44
DDR_SDQ35

DDR_SDQ40
DDR_SDQ41

DDR_SDQ45
DDR_SDQS5

DDR_SDQ42
DDR_SDQ43

DDR_SDQ47
DDR_SDQ46

DDR_SDQ52
DDR_SDQ49

DDR_SDQ48
DDR_SDQ53

DDR_SDQS6
DDR_SDQ55

DDR_SDQ50
DDR_SDQ54

C

RP54 4P2R_33
1 4
2 3

RP56 4P2R_33
1 4
2 3

RP58 4P2R_33
1 4
2 3

RP61 4P2R_33
1 4
2 3

RP64 4P2R_33
1 4
2 3

RP67 4P2R_33
1 4
2 3

RP70 4P2R_33
1 4
2 3

RP73 4P2R_33
1 4
2 3

RP76 4P2R_33
1 4
2 3

RP78 4P2R_33
1 4
2 3

RP80 4P2R_33
1 4
2 3

RP82 4P2R_33
1 4
2 3

RP84 4P2R_33
1 4
2 3

RP86 4P2R_33
1 4
2 3

RP88 4P2R_33
1 4
2 3

RP91 4P2R_33
1 4
2 3

RP93 4P2R_33
1 4
2 3

RP94 4P2R_33
1 4
2 3

RP96 4P2R_33
1 4
2 3

RP98 4P2R_33
1 4
2 3

C

DDR_DQ26
DDR_DQ27

DDR_DQ30
DDR_DQ31

DDR_F_CB5
DDR_F_CB4

DDR_F_CB0
DDR_F_CB2

DDR_DQS8
DDR_F_CB6

DDR_F_CB1
DDR_F_CB7

DDR_F_CB3

DDR_DQ32
DDR_DQ36

DDR_DQ37
DDR_DQ33

DDR_DQS4
DDR_DQ39

DDR_DQ38
DDR_DQ34

DDR_DQ44
DDR_DQ35

DDR_DQ40
DDR_DQ41

DDR_DQ45
DDR_DQS5

DDR_DQ42
DDR_DQ43

DDR_DQ47
DDR_DQ46

DDR_DQ52
DDR_DQ49

DDR_DQ48
DDR_DQ53

DDR_DQS6
DDR_DQ55

DDR_DQ50
DDR_DQ54

PROPRIETARY NOTE

D

DDR_DQ4
DDR_DQ5

DDR_DQS0
DDR_DQ3

DDR_DQ7
DDR_DQ12

DDR_DQ15
DDR_DQS1

DDR_DQ11
DDR_DQ10

DDR_CLK15
DDR_CLK1#5

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ22

DDR_DQ19
DDR_DQ25

DDR_DQ28
DDR_DQS3

DDR_DQ27
DDR_DQ31

DDR_F_CB4
DDR_F_CB2

DDR_DQS8
DDR_F_CB7

DDR_F_CB3

DDR_CLK05
DDR_CLK0#5

DDR_CKE15

DDR_SCS#05

DIMM_SMDATA8,13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

DDR_CKE1

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#

DDR_SCS#0

DDR_DQ36
DDR_DQ33

DDR_DQS4
DDR_DQ39

DDR_DQ38
DDR_DQ44

DDR_DQ40
DDR_DQS5

DDR_DQ43
DDR_DQ47

DDR_DQ52
DDR_DQ48

DDR_DQS6
DDR_DQ55

DDR_DQ50
DDR_DQ59

DDR_DQ63
DDR_DQS7

DDR_DQ57
DDR_DQ60

DIMM_SMCLK8,13

E

+2.5V +2.5V

JP29

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

+3VS

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

DDR-SODIMM_200_Normal

DU/RESET#

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

F

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DIMM0(STD)

Top side

E

F

DDR_DQ0
DDR_DQ1

DDR_DQ6
DDR_DQ2

DDR_DQ8
DDR_DQ13

DDR_DQ9
DDR_DQ14

DDR_DQ16
DDR_DQ21

DDR_DQ18
DDR_DQ23

DDR_DQ24
DDR_DQ29

DDR_DQ26
DDR_DQ30

DDR_F_CB5
DDR_F_CB0

DDR_F_CB6
DDR_F_CB1

DDR_CKE0

DDR_F_SMA11
DDR_F_SMA8

DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#

DDR_SCS#1

DDR_DQ32
DDR_DQ37

DDR_DQ34
DDR_DQ35

DDR_DQ41
DDR_DQ45

DDR_DQ42
DDR_DQ46

DDR_DQ49
DDR_DQ53

DDR_DQ54
DDR_DQ51

DDR_DQ58
DDR_DQ62

DDR_DQ61
DDR_DQ56

DDR_SBS15

DDR_SBS05
DDR_SWE#5

DDR_SCAS#5
DDR_SRAS#5

SDREF_DIMM

12

C632
.1UF_0402

G

R526

DDR_DQ[0..63]
DDR_F_CB [0..7]
DDR_DQS[0..8]

12

SDREF

0_0402

DDR_SMA[0..12] 5

DDR_SMA12
DDR_SMA9

DDR_SMA8
DDR_SMA11

DDR_SMA7
DDR_SMA5

DDR_SMA4
DDR_SMA6

DDR_SMA3
DDR_SMA1

DDR_SMA0
DDR_SMA2

DDR_SMA10 DDR_F_SMA10

H

DDR_DQ[0..63] 8
DDR_F_CB[0..7] 8
DDR_DQS[0..8] 8

RP59 4P2R_0
1 4
2 3

RP62 4P2R_0
1 4
2 3

RP65 4P2R_0
1 4
2 3

RP68 4P2R_0
1 4
2 3

RP71 4P2R_0
1 4
2 3

RP74 4P2R_0
1 4
2 3

R527 0_0402

1 2

DDR_F_SMA[0..12]8

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA8
DDR_F_SMA11

DDR_F_SMA7
DDR_F_SMA5

DDR_F_SMA4
DDR_F_SMA6

DDR_F_SMA3
DDR_F_SMA1

DDR_F_SMA0
DDR_F_SMA2

Layout note

DDR_CKE0 5

Place these resistor
closely DIMM0,
all trace length<=750mil

Layout note
Place these resistor

closely DIMM0,

DDR_SCS#1 5

DDR_CLK2# 5
DDR_CLK2 5

R528 0_0402

DDR_SBS1 DDR_F_SBS1

DDR_SBS0
DDR_SWE#

DDR_SCAS#
DDR_SRAS# DDR_F_SRAS#

Title

Size Docu ment Number Re v

Date: Sheet

1 2

RP100 4P2R_0

1 4
2 3

RP102 4P2R_0

1 4
2 3

SCHEM AT IC , M/ B LA- 1391

401211

星期二 十一

G

all trace length Max=1.3"

RP89 4P2R_47

DDR_CKE1

1 4

DDR_CKE0

2 3

RP92 4P2R_47

DDR_SCS#0

1 4

DDR_SCS#1

2 3

Layout note

Place these resistor
closely DIMM0,
all trace
length<=750mil

DDR_F_SBS1 8

DDR_F_SBS0
DDR_F_SWE#

DDR_F_SCAS#

DDR_F_SBS0 8
DDR_F_SWE# 8

DDR_F_SCAS# 8
DDR_F_SRAS# 8

Compa l E l e c t r onics, Inc.

?26, 2002

+1.25VS

of

744, 

H

1B

A

+1.25VS +1.25VS

RP104 4P2R_47

DDR_DQ4

1 4

DDR_DQ0

2 3

RP107 4P2R_47

DDR_DQ5

1 4

DDR_DQ1

2 3

DDR_DQS0
DDR_DQ6

DDR_DQ3
DDR_DQ2

DDR_DQ7
DDR_DQ8

DDR_DQ12
DDR_DQ13

DDR_DQS1
DDR_DQ15

DDR_DQ11
DDR_DQ9

DDR_DQ10
DDR_DQ14

DDR_DQ20
DDR_DQ16

DDR_DQ17
DDR_DQ21

DDR_DQ18
DDR_DQS2

DDR_DQ22
DDR_DQ23

DDR_DQ19
DDR_DQ24

DDR_DQ25
DDR_DQ29

DDR_DQS3
DDR_DQ28

RP110 4P2R_47
1 4
2 3

RP114 4P2R_47
1 4
2 3

RP118 4P2R_47
1 4
2 3

RP122 4P2R_47
1 4
2 3

RP126 4P2R_47
1 4
2 3

RP130 4P2R_47
1 4
2 3

RP134 4P2R_47
1 4
2 3

RP137 4P2R_47
1 4
2 3

RP140 4P2R_47
1 4
2 3

RP143 4P2R_47
1 4
2 3

RP145 4P2R_47
1 4
2 3

RP147 4P2R_47
1 4
2 3

RP149 4P2R_47
1 4
2 3

RP151 4P2R_47
1 4
2 3

1 1

2 2

3 3

RP105 4P2R_47

14
23

RP108 4P2R_47

14
23

RP111 4P2R_47

14
23

RP115 4P2R_47

14
23

RP119 4P2R_47

14
23

RP123 4P2R_47

14
23

RP127 4P2R_47

14
23

RP131 4P2R_47

14
23

RP135 4P2R_47

14
23

RP138 4P2R_47

14
23

RP141 4P2R_47

14
23

RP144 4P2R_47

14
23

RP146 4P2R_47

14
23

RP148 4P2R_47

14
23

RP150 4P2R_47

14
23

RP152 4P2R_47

14
23

DDR_DQ27
DDR_DQ26

DDR_DQ31
DDR_DQ30

DDR_F_CB4
DDR_F_CB5

DDR_F_CB2
DDR_F_CB0

DDR_F_CB6
DDR_DQS8

DDR_F_CB1
DDR_F_CB7

DDR_F_CB3

DDR_DQ36
DDR_DQ32

DDR_DQ37
DDR_DQ33

DDR_DQ39
DDR_DQS4

DDR_DQ38
DDR_DQ34

DDR_DQ35
DDR_DQ44

DDR_DQ41
DDR_DQ40

DDR_DQS5
DDR_DQ45

DDR_DQ42
DDR_DQ43

DDR_DQ46
DDR_DQ47

RP106 4P2R_47

14
23

RP109 4P2R_47

14
23

RP112 4P2R_47

14
23

RP116 4P2R_47

14
23

RP120 4P2R_47

14
23

RP124 4P2R_47

14
23

RP128 4P2R_47

14
23

RP132 4P2R_47

14
23

RP136 4P2R_47

14
23

DDR_DQ49
DDR_DQ52

DDR_DQ53
DDR_DQ48

DDR_DQ55
DDR_DQS6

DDR_DQ54
DDR_DQ50

DDR_DQ51
DDR_DQ59

DDR_DQ58
DDR_DQ63

DDR_DQ62
DDR_DQS7

DDR_DQ61
DDR_DQ57

DDR_DQ56
DDR_DQ60

Layout note
Place these resistor

closely DIMM1,
all trace
length<=800mil

4 4

B

DDR_F_CB[0..7] 7

DDR_DQ[0..63]

DDR_DQS[0..8] 7
DDR_DQ[0..63] 7
DDR_F_SMA[0..12] 7

C

DDR_CLK45
DDR_CLK4#5

DDR_CLK35
DDR_CLK3#5

DDR_F_SBS07
DDR_F_SWE#7

DIMM_SMDATA7,13
DIMM_SMCLK7,13

+2.5V +2.5V

JP30

1

VREF

3
DDR_DQ0 DDR_DQ4
DDR_DQ1

DDR_DQS0
DDR_DQ6

DDR_DQ2
DDR_DQ8

DDR_DQ13
DDR_DQS1

DDR_DQ9
DDR_DQ14

DDR_DQ16
DDR_DQ21

DDR_DQS2
DDR_DQ18

DDR_DQ23
DDR_DQ24

DDR_DQ29
DDR_DQS3

DDR_DQ26
DDR_DQ30

DDR_F_CB5
DDR_F_CB0 DDR_F_CB2

DDR_DQS8
DDR_F_CB6

DDR_F_CB1

DDR_CKE3 DDR_CKE2

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#2 DDR_SCS#3

DDR_DQ32
DDR_DQ37

DDR_DQS4
DDR_DQ34

DDR_DQ35
DDR_DQ41

DDR_DQ45
DDR_DQS5

DDR_DQ42
DDR_DQ46

DDR_DQ49
DDR_DQ53

DDR_DQS6
DDR_DQ54

DDR_DQ51
DDR_DQ58

DDR_DQ62
DDR_DQS7

DDR_DQ61
DDR_DQ56

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

DDR-SODIMM_200_Reverse

DIMM1(REV)

D

DU/RESET#

DU/BA2

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

VSS

DM8

VDD

VSS

VSS

VDD

VDD

CKE0

VSS

VDD

RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD
CK1#

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

E

SDREF_DIMM

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CB4

74

CB5

76
78
80

CB6

82
84

CB7

86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116

BA1

118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

CK1

162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194

SA0

196

SA1

198

SA2

200

DU

DDR_DQ5

DDR_DQ3
DDR_DQ7

DDR_DQ12
DDR_DQ15

DDR_DQ11
DDR_DQ10

DDR_DQ20
DDR_DQ17

DDR_DQ22
DDR_DQ19

DDR_DQ25
DDR_DQ28

DDR_DQ27
DDR_DQ31

DDR_F_CB4

DDR_F_CB7
DDR_F_CB3

DDR_F_SMA11
DDR_F_SMA8

DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#

DDR_DQ36
DDR_DQ33

DDR_DQ39
DDR_DQ38

DDR_DQ44
DDR_DQ40

DDR_DQ43
DDR_DQ47

DDR_DQ52
DDR_DQ48

DDR_DQ55
DDR_DQ50

DDR_DQ59
DDR_DQ63

DDR_DQ57
DDR_DQ60

+3VS

12

C633
.1UF_0402

DDR_CKE2 5DDR_CKE35

DDR_F_SBS1 7
DDR_F_SRAS# 7
DDR_F_SCAS# 7
DDR_SCS#3 5DDR_SCS#25

DDR_CLK5# 5
DDR_CLK5 5

+1.25VS

RP113 4P2R_56

DDR_F_SMA9

14

DDR_F_SMA12

23

RP117 4P2R_56

DDR_F_SMA8

14

DDR_F_SMA11

23

RP121 4P2R_56

DDR_F_SMA5

14

DDR_F_SMA7

23

RP125 4P2R_56

DDR_F_SMA6

14

DDR_F_SMA4

23

RP129 4P2R_56

DDR_F_SMA1

14

DDR_F_SMA3

23

RP133 4P2R_56

DDR_F_SMA2

14

DDR_F_SMA0

23

R529 56_0402

R530 56_0402

DDR_CKE2
DDR_CKE3

DDR_SCS#2
DDR_SCS#3

1 2

RP139 4P2R_56

14
23

RP142 4P2R_56

14
23

1 2

RP153 4P2R_47
1 4
2 3

RP154 4P2R_47
1 4
2 3

DDR_F_SMA10

DDR_F_SWE#
DDR_F_SBS0

DDR_F_SRAS#
DDR_F_SCAS#

DDR_F_SBS1

Layout note
Place these resistor

closely DIMM1,
all trace length
Max=1.3"

+1.25VS

Bottem side

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

A

B

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Docu ment Number Re v

Date: Sheet

Compa l E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1391

401211

星期二 十一

?26, 2002

1B

of

844, 

E

A

B

C

D

E

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

1 1

+2.5V +2.5V

12

C660
.1UF_0402_X5R

12

C651
.1UF_0402_X5R

12

C661
.1UF_0402_X5R

12

C652
.1UF_0402_X5R

12

C662
.1UF_0402_X5R

12

C653
.1UF_0402_X5R

12

C663
.1UF_0402_X5R

12

C654
.1UF_0402_X5R

12

C664
.1UF_0402_X5R

12

C655
.1UF_0402_X5R

12

C665
.1UF_0402_X5R

12

C656
.1UF_0402_X5R

12

+

12

C666
150UF_D2_6.3V

C657
.1UF_0402_X5R

12

C667

+

150UF_D2_6.3V

12

C658
.1UF_0402_X5R

12

C659
.1UF_0402_X5R

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

+1.25VS

12

C668
.1UF_0402_X5R

+1.25VS

12

C678
.1UF_0402_X5R

12

C669
.1UF_0402_X5R

12

C679
.1UF_0402_X5R

12

C670
.1UF_0402_X5R

12

C680
.1UF_0402_X5R

12

C671
.1UF_0402_X5R

12

C681
.1UF_0402_X5R

12

C672
.1UF_0402_X5R

12

C682
.1UF_0402_X5R

12

C673
.1UF_0402_X5R

12

C683
.1UF_0402_X5R

12

C674
.1UF_0402_X5R

12

C684
.1UF_0402_X5R

12

C675
.1UF_0402_X5R

12

C685
.1UF_0402_X5R

12

C676
.1UF_0402_X5R

12

C686
.1UF_0402_X5R

12

C677
.1UF_0402_X5R

12

C687
.1UF_0402_X5R

+1.25VS

12

C688

3 3

4 4

.1UF_0402_X5R

+1.25VS

12

C698
.1UF_0402_X5R

+1.25VS

12

C708
.1UF_0402_X5R

+1.25VS

12

C718

4.7UF_10V_0805

12

C689
.1UF_0402_X5R

12

C699
.1UF_0402_X5R

12

C709
.1UF_0402_X5R

12

C719

4.7UF_10V_0805

A

12

C690
.1UF_0402_X5R

12

C700
.1UF_0402_X5R

12

C710
.1UF_0402_X5R

12

C720

+

150UF_D2_6.3V

12

C691
.1UF_0402_X5R

12

C701
.1UF_0402_X5R

12

C711
.1UF_0402_X5R

12

C721
.1UF_0402_X5R

12

C692
.1UF_0402_X5R

12

C702
.1UF_0402_X5R

12

C712
.1UF_0402_X5R

12

C693
.1UF_0402_X5R

12

C703
.1UF_0402_X5R

12

C713
.1UF_0402_X5R

B

12

C694
.1UF_0402_X5R

12

C704
.1UF_0402_X5R

12

C714
.1UF_0402_X5R

12

C695
.1UF_0402_X5R

12

C705
.1UF_0402_X5R

12

C715
.1UF_0402_X5R

PROPRIETARY NOTE

12

C696
.1UF_0402_X5R

12

C706
.1UF_0402_X5R

12

C716
.1UF_0402_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

12

12

C

C697
.1UF_0402_X5R

C707
.1UF_0402_X5R

C717
.1UF_0402_X5R

D

Title

Size Docu ment Number Re v

Date: Sheet

Compa l E l e c t r onics, Inc.

SCHEM AT IC , M/ B LA- 1391

401211

星期二 十一

?26, 2002

of

944, 

E

1B

A

1 1

B

C

D

AD[0..31]19,20,23

2 2

C/BE#019,20,23
C/BE#119,20,23
C/BE#219,20,23
C/BE#319,20,23

DEVSEL#19,20,23

FRAME#19,20,23

IRDY#19,20,23
TRDY#19,20,23
STOP#19,20,23

PCIRST#4,14,19,20,21,23,25,27,31,34

PLOCK#20
SERR#19,20,23

PCI Pullups

3 3

+3VS

+3VS

PERR#
REQA#
STOP#
SERR#

IRDY#
TRDY#

FRAME#

RP35
1
2
3
4
5

10P8R-8.2K

RP34
1
2
3
4
5

10P8R-8.2K

10

PIRQA#

9

PIRQB#

8

REQ#4

7
6

10

PIRQC#

9

PIRQD#DEVSEL#

8

SIRQ

7

PLOCK#

6

+3VS

+3VS

PERR#19,20,23

PME# ha s i n te rnal PU

PIDERST#25
PCLK_ICH13

REQ#023
REQ#219

REQ#320

PCI REQ ASSIGMENT
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

+3VS

RP37

1 8

4 4

2 7
3 6
4 5

8P4R-8.2K

1 2

R350 8.2K

1 2

R349 @1K

REQ#0
REQ#1
REQ#2
REQ#3

GPI1
GNTA#

GNTA# Strapping for "A16 swap override" : "0" -> Enable

A

AD[0..3 1 ]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

DEVSEL#
FRAME#
IRDY#
TRDY#

PAR19,20,23

STOP#

PCIRST#
PLOCK#

SERR#
PERR#

REQA#
GNTA#

PCLK_ICH
REQ#0

REQ#1
REQ#2
REQ#3
REQ#4
GPI1

WLAN
NC
1394

PCMC IA CONTROLLER

NC

PROPRIETARY NOTE

B

W10

AA10

AA15

W11

AB10

ICH-2

(FW82801BA)

U33A

AA4

AD0

AB4

AD1

Y4

AD2

W5

AD3

W4

AD4

Y5

AD5

AB3

AD6

AA5

AD7

AB5

AD8

Y3

AD9

W6

AD10

W3

AD11

Y6

AD12

Y2

AD13

AA6

AD14

Y1

AD15

V2

AD16

AA8

AD17

V1

AD18

AB8

AD19

U4

AD20

W9

AD21

U3

AD22

Y9

AD23

U2

AD24

AB9

AD25

U1

AD26
AD27

T4

AD28

Y10

AD29

T3

AD30
AD31

AA3

C/BE0#

AB6

C/BE1#

Y8

C/BE2#

AA9

C/BE3#

AB7

DEVSEL#

V3

FRAME#

W8

IRDY#

V4

TRDY#

W1

STOP#

W2

PAR
PCIRST#

AA7

PLOCK#

W7

SERR#

Y7

PERR#

Y15

PME#

M3

GPI0/REQA#

L2

GPO16/GNTA#
PCICLK

R2

REQ0#

R3

REQ1#

T1

REQ2#
REQ3#

P4

REQ4#

L3

GPI1/REQB#/REQ5#

ICH-2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI

PCLK_ICH

CPU

CPUPWRGD

HUB

IRQ

GPI2/PIRQE#

GPI3/PIRQF#
GPI4/PIRQG#
GPI5/PIRQH#

GPO17/GNTB#/GNT5#

12

12

CPUSLP#

IGNNE#

STPCLK#
A20GATE

HL_STB
HL_STB#
HLCOMP
HUBREF

PIRQA#

PIRQB#
PIRQC#
PIRQD#

APICCLK

APICD0

APICD1
SERIRQ

R154

@33

C222

@22PF

A20M#
FERR#

INIT#

INTR
SMI#

RCIN#

HL10
HL11

IRQ14
IRQ15

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#

D11
A12

FERR#

R22
A11

CPUINIT#

C12
C11
B11

NMI

SMI#

B12

STPCLK#

C10

RC#

B13

GATEA20

C13

CPU_PWRGD

A13

HL0

A4

HL0

HL1

B5

HL1

HL2

A5

HL2

HL3

B6

HL3

HL4

B7

HL4

HL5

A8

HL5

HL6

B8

HL6

HL7

A9

HL7

HL8

C8

HL8

HL9

C6

HL9

HL10

C7

HL11

C5

HL_STB

A6

HL_STB#

A7

+ICH_HLCOMP

A3

HUBREF

B4

PIRQA#

P1

PIRQB#

P2

PIRQC#

P3

PIRQD#

N4

IRQ14

F21

IRQ15

C16

CLK_APIC_ICH

N20

PICD0

P22

PICD1

N19

SIRQ

N21

GPI2

N3

GPI3

N2

GPI4

N1

GPI5

M4

PIN N3, M4 can not use GPIO.

GNT#0

M2
M1

GNT#2

R4

GNT#3

T2
R1

SIDERST#

L4

1 2

R383 0

C484 .1UF

C

HL[0..10]

HL_STB 4
HL_STB# 4

12

HUBREF 4
PIRQA# 14,20,23
PIRQB# 20
PIRQC# 19
PIRQD# 23

IRQ14 25
IRQ15 24

SIRQ 20,27,31

GNT#0 23
GNT#2 19

GNT#3 20

SIDERST# 25

SB_A20M# 2
CPUSLP# 2
FERR# 2
SB_IGNNE# 2
CPUINIT# 2
SB_INTR 2
SB_NMI 2
SMI# 2
STPCLK# 2
RC# 31
GATEA20 31
CPU_PWRGD 2

HL[0..10] 4

+1_8VS

HL11
+ICH_HLCOMP

SIDERST#
IRQ14
IRQ15

GPI4
GPI3
GPI2
GPI5

PICD0
PICD1
CLK_APIC_ICH

Compa l E l e c t r onics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

星期二 十一

?26, 2002

D

1 2

R357 @10K

1 2

R354 40.2_1%

1 2

R351 @8.2K

1 2

R410 10K

1 2

R390 10K

RP36

1 8
2 7
3 6
4 5

8P4R-100K

12

R414 10K

12

R409 10K

1 2

R415 0

+3VS

of

10 44, 

1B

A

1 2

+3V

+3V

+3V

ACIN31,34,36,37,39

+3V

+3V

+3V

+RTCVCC

1 2

INTRUDER#

SMLINK0
SMLINK1
OVCUR#2
OVCUR#0

VGATE

CLKRUN#

LDRQ#1

DSCACHE#
ICH_AC_SDOUT

RSMRST#

IAC_BITCLK
IAC_SDATAI
IAC_SDATAI1
SPKR

R403 10K
D38 RB751V

1 2

R380 10K
D34 RB751V

D22 RB751V

D21 @RB751V

1 2

R388 10K
D36 RB751V

1 2

R370 10K
D33 RB751V

1 2

R362 10K
D32 RB751V

1 2

R384 10K
D35 RB751V

R190

1 2

15K

1UF_25V_0805

R191

1K

LLBATT#31

EC_LID_OUT#31

PBTN_OUT#31

ON/OFF31,34

1 1

ECSMI#31

ECSCI#31

EC_RIOUT#31

2 2

+RTCVCC

1 2

R183 10K

+3V

3 3

1 2

R175 10K

1 2

R184 10K

1 2

R178 10K

1 2

R548 10K

+3VS

1 2

R386 100K

1 2

R436 10K

1 2

R356 @10K

12

R355 10K

1 2

R179 @10K

AC_SDOUT Strapping: "1" -> Safe Mode Boot

4 4

R168 100K

R169 10K
R404 10K
R405 10K
R407 1K

12

12
12
12
12

SPKR Strapping: "0" -> No Reboot

A

BATTLOW#

21

LID#

21

PBTN#

21

21

ICH_ACIN

21

EXT_SMI#

21

SCI#

21

ICH_RI#

21

12

C303

+R_VBAIS

1 2

C282
.047UF

12

1 2

R479
22M

R480

2.4M

1 2

CLKRUN# 19,20,23,27,31

R392

1 2

1K

R181

10M

C538
12PF

J1

JOPEN

1 2

R406 10M

32.768KHZ

12

IAC_BITCLK

USBP2­USBP2+
USBP0­USBP0+

CP5

8P4C-22PF

1 8

2 7

3 6

4 5

12

X3

12

C539
12PF

1 2

R158 @10K

12

R170

@33

C543

@33PF

RP41
1 8
2 7
3 6
4 5

8P4R-15

SYS_PWROK35

RSMRST#12,35

SUS_STAT#14,27,34

B

182736

45

RP40
8P4R-15K

C293
22PF

AA13

D14
W16

AB18

R20
W21

AA17

R21
W15

AA18

Y11
A15

C14

V21
Y17
T19

AA16
AB16
AB17

U19

V20
T20

T21

U22

T22

V22
P19

R19

P21

Y22
W22
N22

Y14

AA11

W14

AB15

L1
AB14
AA14

Y12

W12
AB13
AB12

Y13

W13
AB11
AA12

W17

Y18
AB19
AA19

W18

Y19
AB20
AA20

W19

Y20

Y21

W20

R408 22
R180 22

12

1 2
1 2

U33B

THRM#
GPO19
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
GPIO25
SUSCLK
GPI6
GPO18
GPO20
GPIO24
SUSSTAT#
INTRUDER#

SMBDATA
SMBCLK
SMBALERT#/GPI11
SMLINK0
SMLINK1

RTCRST#
VBIAS
RTCX1
RTCX2

AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
SPKR

GPI8
GPI7
GPI12
GPI13
GPO21
GPIO27
GPIO28

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LDRQ1#
LFRAME#/FWH4
FSO

USBP0+
USBP0­USBP1+
USBP1­USBP2+
USBP2­USBP3+

ICH-2

USBP3­OC0#

OC1#
OC2#
OC3#

SYSTEM

AC97

GPIO

LPC

USB

ICH_AC_SYNC
ICH_AC_SDOUT

ATF_INT#31

SLP_S3#31
SLP_S5#31

FLASH#32
RTCCLK20,21

SDAP413
SCKP413

IAC_RST#26,29 PDD[0..15] 25
IAC_BITCLK26,29
IAC_SDATAI29

IAC_SDATAI126

SPKR30

USB_EN#28

LAD027,31
LAD127,31
LAD227,31

LAD327,31
LDRQ#031
LDRQ#127

LFRAME#27,31

OVCUR#128
OVCUR#328

IAC_SYNC26,29

IAC_SDATAO26,29

PROPRIETARY NOTE

B

ATF_INT#
SLP_S3#

SLP_S5#
SYS_PWROK
PBTN#
ICH_RI#
RSMRST#

BATTLOW#

INTRUDER#
SDAP4

SCKP4
ICH_ACIN
SMLINK0
SMLINK1

+RTCRST#
+VBIAS
RTCX1
RTCX2

ICH_AC_SYNC
IAC_BITCLK
ICH_AC_SDOUT
IAC_SDATAI
IAC_SDATAI1
SPKR

EXT_SMI#
DSCACHE#
SCI#
LID#

LAD0
LAD1
LAD2
LAD3
LDRQ#0
LDRQ#1
LFRAME#

USBP0+
USBP0­USBP1+
USBP1­USBP2+
USBP2­USBP3+
USBP3-

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3

12

C544
22PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

USBP3­USBP3+
USBP1­USBP1+

8P4C-22PF

GPO22
GPO23

VGATE/VRMPWRGD

CLK48
CLK14
CLK66

PDA0
PDA1

PDA2
PDCS1#
PDCS3#

PDREQ

PDDACK#

PDIOR#
PDIOW#
PIORDY

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

IDE

PDD6

PDD7

PDD8

PDD9

PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDA0

SDA1

SDA2
SDCS1#
SDCS3#

SDDREQ

SDDACK#

SDIOR#
SDIOW#
SIORDY

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9

SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

C

RP44
1 8
2 7
3 6
4 5

U20
B14
A14
B15

P20
M19
D4

F20
F19
E22
E21
E19

G22
F22
G19
G21
G20

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

A16
D16
B16
C15
D15

B18
B17
D17
C17
A17

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

1 8

2 7

3 6

VGATE
CLK_USB_ICH

CLK_14M_ICH
CLK_HUB_ICH

8P4R-15

8P4R-15K

4 5

1 2

R478 0

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

PDDREQ
PDDACK#
PDIOR#
PDIOW#
PDIORDY

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SDIORDY

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

R400 1K

1 2

CP6

TP0

RP43

182736

45

+3V

CLK_USB_ICH 13
CLK_14M_ICH 13
CLK_66M_ICH 13

PDA0 25
PDA1 25
PDA2 25
PDCS1# 25
PDCS3# 25

PDDREQ 25
PDDACK# 25
PDIOR# 25
PDIOW# 25
PDIORDY 25

PDD[0..15]

SDA0 24
SDA1 24
SDA2 24
SDCS1# 24
SDCS3# 24

SDDREQ 24
SDDACK# 24
SDIOR# 24
SDIOW# 24
SDIORDY 24

SDD[0..15]

V_GATE 41

CLK_USB_ICH CLK_14M_ICH CLK_HUB_ICH

D

ICH2-B(IDE,LPC,GPIO)

USB3_D- 28
USB3_D+ 28
USB1_D- 28
USB1_D+ 28

SDD[0..15] 24

PDIORDY

1 2

R416 4.7K

SDIORDY

1 2

R394 4.7K

?26, 2002

12

R162
10

12

C245
10PF_0402

D

12

R149
10

12

C198
10PF

11 44, 

12

R166
22

12

C270
10PF_0402

Compa l E l e c t r onics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

星期二 十一

+5VS

1B

of

A

B

C

D

ICH2-C(LAN,Power)

+1_8VS

AA21
AA22

AB21
AB22

U33C

D10

VCC1_8_1

E5

VCC1_8_2

K19

VCC1_8_3

L19

VCC1_8_4

P5

VCC1_8_5

V9

VCC1_8_6

D2

VCC1_8_7

A1

GND1

A2

GND2

A10

GND3

B1

GND4

B2

GND5

B3

GND6

B9

GND7

B10

GND8

C2

GND9

C3

GND10

C4

GND11

C9

GND12

D5

GND13

D6

GND14

D7

GND15

D8

GND16

D9

GND17

E6

GND18

E7

GND19

E8

GND20

E9

GND21

J10

GND22

J11

GND23

J12

GND24

J13

GND25

J14

GND26

J9

GND27

K10

GND28

K11

GND29

K12

GND30

K13

GND31

K14

GND32

K9

GND33

L10

GND34

L11

GND35

L12

GND36

L13

GND37

L14

GND38

L9

GND39

M10

GND40

M11

GND41

M12

GND42

M13

GND43

M14

GND44

M9

GND45

N10

GND46

N11

GND47

N12

GND48

P9

GND49

P14

GND50

P13

GND51

P12

GND52

P11

GND53

P10

GND54

N9

GND55

N14

GND56

N13

GND57

A21

GND58

A22

GND59

B21

GND60

B22

GND61

AA1

GND62

AA2

GND63
GND64
GND65

AB1

GND66

AB2

GND67
GND68
GND69

K1

GND70

D3

GND71

ICH-2

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8

VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18

V5REF1
V5REF2

VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS1_8_4
VCCSUS1_8_5

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6

V_CPU_IO_1
V_CPU_IO_2

VCCRTC

V5REF_SUS

EEPROM

EE_CS

EE_SHCLK

EE_DOUT

EE_DIN

LAN

LAN_CLK
LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

LAN_RSTSYNC

RSM_PWROK

1 1

2 2

+3V

12

C250
.1UF_0402

+1_8V

12

+

12

12

C251
.1UF_0402

12

C238
.1UF_0402

C208

4.7UF_10V_0805

C227
.1UF_0402

12

12

C244
.1UF_0402

12

C209
.1UF_0402

CPU_VCC

12

C242
.1UF_0402

C229
.1UF_0402

12

12

C221
.1UF_0402

12

C212
.1UF_0402

C243
.1UF_0402

12

C253
.1UF_0402

12

C213
.1UF_0402

12

C252
.1UF_0402

12

C249
.1UF_0402

12

C224
.1UF_0402

12

C214
1000PF_0402

12

C246
1000PF_0402

+3VS

+1_8VS

12

C215
1000PF_0402

12

C225
1000PF_0402

12

C216
.1UF_0402

12

C247

+

4.7UF_10V_0805

3 3

12

C230
.1UF_0402

12

C231
.1UF_0402

+3VS

E14
E15
E16
E17
E18
F18
G18
H18
J18
P18
R18
R5
T5
U5
V5
V6
V7
V8

+VCC5REF

K2
M20

V14
V15
V16
H5
J5

T18
U18
F5
G5
V17
V18

D12
D13

U21
V19

K4
J3
J4
K3

R353 @10K

G3
G2
G1
H1

LANTXD0

F3

LANTXD1

F2

LANTXD2

F1
H2
Y16

1 2

+1_8V

+3V

CPU_VCC

VCCRTC

+3V

LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

LAN_CLK

R100 33

1 2

R101 33

1 2

R102 33

1 2

R99 33

1 2
1 2

R167 0

LAN_CLK

1
2
3
4

1 2

R182 1K

C540 .1UF

U29

CS
SK
DI
DO

9346

D12

1SS355

12

C197
1UF_0805

1 2

8

VCC

7

NC

6

NC

5

GND

LAN_CLK 22
LAN_RXD0 22
LAN_RXD1 22
LAN_RXD2 22
LAN_TXD0 22
LAN_TXD1 22

LAN_TXD2 22
LAN_RST 22
RSMRST# 11,35

12

R86

@33

12

C136

@22PF

+3VS

21

12

C292
.1UF

+RTCVCC

+5VS

12

R140
1K

+3V

12

C476
.1UF

4 4

Compa l E l e c t r onics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

A

B

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

星期二 十一

?26, 2002

D

of

12 44, 

1B

A

B

C

D

E

F

G

H

Clock Generator

+3VS

SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]

0 0 0 66.67 66.67
0 0 1 100.00 100.00
0 1 0 200.00 200.00
0 1 1 133.33 133.33

1 1

+3VS +3VS

12

12

R326

R328

1K

@1K

BSEL02
BSEL12

2 2

1 2

R547 @0

CPU_VCC

12

12

R545

R546

@1K

1K

+3VS

1 2

1 2

R338 10K

R346 220

+3VS

1

C

Q40

2SC2411K

2

B

E

3

R324 220

CLK_USB_ICH11

R107 33

C169 10PF

1 2

R323 1K

R339 1K

1 2

R317 1K

1 2

R327 1K

1 2

+3VS

1 2

1 2

1 2

12

1 2

C176
10PF

R325 10K

1 2

DIMM_SMDATA
DIMM_SMCLK

XTALIN

Y2

14.318MHZ

XTALOUT

L11
CHB2012U121

1 2

L12
CHB2012U121

1 2

2

3

40
55
54

25
34
53

28

43

29
30

33
35

42

39

38

R109 33

CLK_14M_ICH11

14.3M_SIO27

3 3

12

C133

1 2
1 2

R110 33

56

@10PF

U9

XTAL_IN

XTAL_OUT

SEL2
SEL1
SEL0

PWR_DWN#
PCI_STOP#
CPU_STOP#

VTT_PWRGD#

MULT0

SDATA
SCLK

3V66_0/DRCG
3V66_1/VCH_CLK

IREF

48MHZ_USB

48MHZ_DOT

REF

ICS950805

+3V_CLK

Width=40 mils

1

14

VDD_PCI8VDD_PCI

VDD_REF

GND_REF4GND_PCI9GND_PCI15GND_3V6620GND_3V6631GND_48MHZ36GND_IREF41GND_CPU

12

+

C139

22UF_16V_1206

50

32

37

VDD_CPU46VDD_CPU

VDD_3V6619VDD_3V66

VDD_48MHZ

CPU_CLKC2

66MHZ_IN/3V66_5

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

47

VDD_CORE

GND_CORE

CPUCLKT2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

26

27
45

44
49

48
52

51
24

23
22
21

7
6
5

18
17
16
13
12
11
10

12

12

C140
.01UF_0402

+3V_VDD

12

+

C175

.01UF_0402

CLK_BCLK

CLK_BCLK#

CLK_MCH

CLK_MCH#

66M_MCH

R131 33

1 2

R134 33

1 2

R521 33

1 2

R133 33

1 2

R132 33

1 2

R122 33

1 2

12

C141

C142

.01UF_0402

.01UF_0402

L14
CHB2012U121
1 2

12

C177
22UF_16V_1206

R105 27

1 2

R106 27

1 2

R103 27

1 2

R104 27

1 2

R125 33

1 2

R124 33

1 2

R123 33

1 2

12

12

C143

C172

.01UF_0402

.01UF_0402

+3VS

1 2

R87 49.9_1%

R88 49.9_1%

1 2

1 2

R89 49.9_1%

R90 49.9_1%

1 2

12

C157
.01UF_0402

12

C182
@10PF

12

C174
.01UF_0402

12

C183
@10PF

12

C171
.01UF_0402

HCLK_CPU 2

HCLK_CPU# 2
CLK_HMCH 4

CLK_HMCH# 4

12

C184
@10PF

CLK_66M_AGP 14
CLK_66M_ICH 11
CLK_66M_MCH 4

PCLK_ICH 10

PCLK_PCM 20
PCLK_1394 19
PCLK_SIO 27

PCLK_EC 31
PCLK_MINI 23

+3V

R321

4.7K

1 2

+3V

R322

4.7K

4 4

SCKP411

1 2

+5VS

2

G

1 3

D

Q61 2N7002

+5VS

2

G

1 3

D

DIMM_SMDATA

S

DIMM_SMCLK

S

DIMM_SMDATA 7,8SDAP411

DIMM_SMCLK 7,8

Q62 2N7002

Compa l E l e c t r onics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

A

B

C

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

E

F

SCHEMATIC, M/B LA-1391

Size Docu ment Number Re v

B

401211

Date: Sheet

星期二 十一

G

?26, 2002

of

13 44, 

H

1B

1

2

3

4

5

6

7

8

GAD[0:31]4

A A

GC/BE#[0:3 ]4

CLK_66M_AGP13

R40
@0

R41
0

FREQOUT

GREQ#4
GGNT#4

PIRQA#10,20,23

GPAR4

GSTOP#4

GDEVSEL#4

GTRDY#4
GIRDY#4

GFRAME#4

PCIRST#4,10,19,20,21,23,25,27,31,34

RBF#4

AD_STB04

AD_STB0#4

AD_STB14

AD_STB1#4

ST04
ST14
ST24

SBA[0:7]4

SBSTB4

SBSTB#4

AGPREF4

1 2

R494 22

1 2

R46 120

B B

+3V_VGA

L47
BLM21P300S_0805

12

C602

10UF_1206

C C

D D

C102
.1UF

CLK

PD#

LEE

MK1709

X1

VDD
ST

OSC_27MHz

12

12

R550
@0

4

8
5

OUT
GND

12

3
2

12

12

R43

R44

0

@0

12

12

R42

R45

@0

@0

+3V_VGA

2

U6

VDD

1

X1/CLK

7

S0

6

S1

GND

3

12

R64
10K

4

C93
.1UF

1

12

Divide r circuit for 1.8Vdc XTALIN from 3.3Vdc OSC out

1

2

GAD[0:31]

GC/BE#[0:3]

+3VS
+3VS

SBA[0:7]

(10 mil)

C158 .1UF

12

R54
@20K

12

R47
150

3

1 2

R4910

1 2

C393 10PF

1 2
1 2

R115 47_1%

1 2

1 2

R53 10

1 2

12

R37
@20K

12

C75
@15PF

COMPS18

LCD_CLK18

LCD_DATA18

R52

1 2

845_1%

PROPRIETARY NOTE

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

GREQ#
GGNT#
GINTA#
GPAR
GSTOP#
GDEVSEL#
GTRDY#
GIRDY#
GFRAME#

1 2

R30110

R7220K

RBF#

R6820K

ADSTBA
ADSTBA#
ADSTBB
ADSTBB#

ST0
ST1
ST2

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SBSTB
SBSTB#

OSCLIN

1 2

R55 1K

CRMA18
LUMA18

R2SET

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G23
G25
G24
G26

M26
M24

M25

AA25
AA24

AA23
AA26

W24

AB25
AB26

W26

W25

AE6
AE7

AF25
AF26

AC6

AF16
AF15
AF14
AE14
AF13

AE16

4

AF6
AF7

D24
C26
D25
D26
E23
E25
E24
E26
F26

H24
H26
H25
L23
L26
L24

N25
N26

P23
P26
P24
R25
R24
R26
T23
T25

F23
J25
L25
N23

Y24
J23

J24
J26
K24
K26
K25

F25
F24
P25
N24

Y26
Y23
Y25

V24
V26
V23
U26
U24
T26
T24

V25
U25

C25
B26

Y3

U8A

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

REQ#
GNT#
INTA#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
RST#
PCICLK

SERR#
STP_AGP#

AGP_BUSY#
RBF#
AD_STB0
ADSTRB0#
AD_STB1
ADSTRB1#

ST0
ST1
ST2

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SB_STB
SB_STB#

AGPTEST
AGPREF

SSIN
SSOUT

XTALIN
XTALOUT

TESTEN
ROMCS#
C_R

Y_G
COMP_B
H2SYNC
V2SYNC

CRT2DDCCLK
CRT2DDCDATA

R2SET

M6-P

PCI/AGP HOST BUS INTERFACECLK

SSCDAC2

GPIO / ROM

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8

ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23

ZV PORT / EXT TMDSLVDSTMDSDAC

ZV_LCDCNTL0

ZV_LCDCNTL1

ZV_LCDCNTL2

ZV_LCDCNTL3

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

DVIDDCCLK

DVIDDCDATA

VGADDCCLK

VGADDCDATA

SUS_STAT#

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

LTGIO0
LTGIO1
LTGIO2

DIGON
BLON#

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TXCM

TXCP

HPD

HSYNC
VSYNC

MONID0
MONID1

AUXWIN

RSET

5

Y2
Y1
W3
W2
W1
V4
V3
V2
V1
U3
U2
U1
T4
T3

AA4
AB1
AB2
AB3
AB4
AC1
AC2
AC3
AD1
AD2
AD3
AE1
AE2
AF1
AF2
AF3
AE3
AF4
AE4
AD4
AF5
AE5
AD5
AC5

Y4
AA1
AA2
AA3

AC8
AD8
AC9
AD9
AE8
AF8
AC10
AD10
AE9
AF9
AD11
AC11
AE11
AF11
AD12
AC12
AD13
AE13
AE12
AF12

AD7
AD6
AC7

AB10
AB9

AE19
AF19
AE20
AF20
AE21
AF21
AE18
AF18

AD20
AC20

AD21

AF24

R

AF23

G

AF22

B

AE24
AE23

AC25
AC26

AD24
AD25

AE25
AC22
AE22

Option Stra p Pins

GPIO0

R71 @10K
GPIO1
GPIO2
GPIO3

M_SEN#

R51 10K

RSET

1 2

R70 @10K

1 2

R74 @10K

1 2

R75 @10K

1 2

ENVDD
BLON#

DDCSCL
DDCSDA

R49 0

1 2

1 2

1 2

(10 mil)(10 mil)

TXOUT0- 18
TXOUT0+ 18
TXOUT1- 18
TXOUT1+ 18
TXOUT2- 18
TXOUT2+ 18

TXCLKO- 18
TXCLKO+ 18
TZOUT0- 18
TZOUT0+ 18
TZOUT1- 18
TZOUT1+ 18
TZOUT2- 18
TZOUT2+ 18

TZCLKO- 18
TZCLKO+ 18

R18
G18
B18
HSYNC1 18
VSYNC1 18

SUS_STAT#

499_1%
R50

6

Strap-G
Strap-H
Strap-J
Strap-K

M_SEN# 18
DDC_MD2 18

+3V_VGA

+3V_VGA

ENVDD 18
BLON# 18

DDC_CLK 18
DDC_DATA 18

SUS_STAT# 11,27,34

HOST INTERFACE

SUS_STAT#

1 2

R48 10K

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1391

Size D ocume nt Number R e v
Custom

401211

Date: Sheet

星期二 十一月

, 2002

7

+3V

14 44, 26

of

8

1B