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LA-1381 REV0.5 Schematics Document
uFCBGA/uFCPGA Northwood with
5 5
6 6
BOM 記號
DT@ SKU W/Desktop CPU 要打
M@ SKU W/Mobile CPU 要打
7 7
LAN@ SKU W/LAN 要打
1394@ SKU W/1394 controller 要打
S@ SKU W/TVOUT 要打
FIR@ SKU W/FIR module 要打
MDC@ SKU W/MODEM module 要打
DK@ SKU W/DOCKING 要打
SD@ SKU W/SD CARD 要打
8 8
BT@ SKU W/Bluetooth module 要打
MLED@ SKU Media LED supper 要打
SUB@ SKU W/SUBWOOFER要打
A
Brookdale chipset(845MP/MZ+ICH3-M)
PCB Layer
Structure:
TOP
GND1
IN1
IN2
VCC
IN3
GND2
BOT
B
C
D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
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H
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
146,
J
2B
Page 2
A
B
C
D
E
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H
I
J
Compal confidential
Model Name :APL11
File Name : LA-1381
1 1
Mobil e Nort hwood
uFCBGA/ uFC PGA CPU
2 2
3 3
Fan Cont rol
CRT Connector
page 6
page 15
VGA
Board
& CPUVID
LM75 thermal
sensor
AGP Conn
page 15
page 6
AGP4X(1.5V)
System Bus
400MHz
Brookdale-M
MCH-M
625 BGA
USB2.0 conn X 2
page 32
HUB Link
CPU B ypass
4 4
Mini PCI
Conn.
page 36
VIA_ VT 6202
USB2.0
page 26
PCI BUS
IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)
5 5
TI TSB43AB22
1394
page 25
DC/DC Interface
Suspend
6 6
page 37
CardBus Controller
PCI 1410
Slot 0
page 24
14M_5V
Power Circuit
DC/DC
page
38,39,40,41,42,43,44,45
7 7
Touch Pad
EC Ext. I/O
3.3V 33MHz
page 23
EC 87591
page 30
page 29
page 31
1.8V 266MHz
LPC BUS
3.3V 33MHz
Int.KBD
ICH3-M
421 BGA
SD/MS CARD
page 27
page 33
page 4,5
HD#(0..63)HA#( 3..31)
page 8,9
page 16,17
LPT
Port.
page 29
Memory
BUS(DDR)
2.5V 200MHz
LAN interface
USB interface
3.3V 48MHz
3.3V 24.57 6MHz
3.3V ATA100
SMsC
LPC47N227
page 28
Therm al Sensor
MAX6654 W320-04
page 5
SO-DIMM X2
BANK 0, 1, 2, 3
LAN
Kinnereth
Blu etooth
USB conn X1
IDE Connector
(HDD/CR-ROM)
page 19
Clock Generator
page 11,12
page 20
page 32
page 32
page 14
RJ45
page 20
AC-LINK
AC97
Codec
ALC202
page 21
AMP& Phone
Jack
page 22
SUB WOOFER
page 37
MDC
page 32
BIOS
page 31 page 29
8 8
A
B
C
D
PS/2 conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
FIR
page 29
F
FDD
page 19
G
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
H
Date: Sheet
?30, 2002
I
246,
2B
of
J
Page 3
10
9
8
7
6
5
4
3
2
1
Power Managment table
H H
State
Signal
+3VALW
+5VALW
+1.8VALW
+3V
+5V
+2.5V
+12VALW
G G
S0
S1
ON
ON ON ON
ON ON
+3VS
+5VS
+1.8VS
+1.5VS
+1.2VP
+CPU_CORE
+1.25V
NB Chip Rev SB Chip Rev
S3
S5 S4/AC
F F
E E
D D
C C
S5 S4/AC don't exist
ON ON
ON OFF
OFF OFF OFF
OFF
OFF
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
346,
1
2B
Page 4
A
B
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1 1
+CPU_CORE
2 2
HA#[3..31]<8>
3 3
4 4
HREQ#[0 ..4 ]<8>
HADS#<8>
5 5
R148 not plant
for DT CPU.
HBR0#<8>
HBPRI#<8>
HBNR#<8>
HLOCK#<8>
CLK_HCLK<14>
CLK_HCLK#<14>
+CPU_CORE
HA#[3..31]
HREQ#[0..4]
R148 M@10K_0402
1 2
R96 200_0402
1 2
CLK_HCLK
CLK_HCLK#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
AF22
AF23
6 6
HIT#<8>
HITM#<8>
HDEFER#<8>
A10
A12
A14
A16
U41A
VCC_0
VCC_1
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
VCC_2
VSS_0H1VSS_1H4VSS_2
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
J1
K5
J4
J3
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
F3
E3
E2
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
D9
A18
A20
AA10
AA12
AA14
VCC_3
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56B7VCC_57B9VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
Mobile
NorthWood
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VCC_81
VCC_82
VCC_83
VCC_84
F9
F13
F15
F17
A11
A13
A15
A17
A19
A21
A24
H23
H26
A26
AA1
AA11
AA4
AA7
AA13
AA15
AA9
AA17
AA19
AA23
AA26
AB10
AB12
AB3
AB6
AB8
AC2
AC5
AC7
AC9
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AD1
AC22
AC25
AD10
AD4
AD12
AD14
AD16
AD18
AD21
AD23
AD8
F19
E10
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71D7VCC_72
VCC_73
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79E8VCC_80
VCC_85
F11
NorthWood
E12
E14
E16
E18
E20
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#[0..63]
HD#[0 ..6 3 ] <8>
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
+CPU_CORE
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
H
Date: Sheet
?30, 2002
I
446,
2B
of
J
Page 5
A
+CPU_CORE
R116
1 1
2 2
3 3
R119
R120
R100
R26
R99
R101
R146
R115
R28 300_0402
R30
R114
Place resistor <100mils from
CPU pin
+CPU_CORE
200_0402
12
200_0402
12
200_0402
12
200_0402
12
200_0402
12
200_0402
12
200_0402
12
200_0402
12
56_0402
12
12
H_DPSLP#<16>
51.1_1%
12
200_0402
12
+CPU_CORE
PM_CPUPERF#
4 4
+1.2VP
Murata LQG21F4R7N00
If used ITP port must depop
RP6 8P4R_1.5K
1 8
2 7
5 5
6 6
3 6
4 5
+CPU_CORE
R147 51.1_1%
R87
R88
R89 51.1_1%
R158 51.1_1%
R159 51.1_1%
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
12
12
51.1_1%
51.1_1%
12
12
12
12
7 7
C155
2200PF
+5VALW
R197 1K_0402
8 8
Address:1001_110X
A
H_A20M#
H_SMI#
H_IGNNE#
H_STPCLK#
H_DPSLPR#
H_NMI
H_INIT#
H_INTR
H_F_FERR#
H_PWRGD
H_RESET#
DT : INSTALL
L50
DT@4.7UH_80mA
1 2
DT@4.7UH_80mA
L19
1 2
DT : REMOVE
L51
M@4.7UH_80mA
1 2
M@4.7UH_80mA
L12
1 2
ITP_PREQ#
ITP_PRDY#
ITP_BPM0
ITP_BPM1
ITP_BPM2
ITP_BPM3
12
H_THERMDA
H_THERMDC
12
B
DT : REMOVE
M@0_0402
R20
R19
DT@56_0402
12
C67
+
22U_1206_10V4Z
CLK_ITPP<14>
CLK_ITPP#<14>
B
H_TRDY#<8>
H_F_FERR#<16>
H_IGNNE#<16>
H_PWRGD<16>
H_STPCLK#<16>
12
12
H_RESET#<8>
H_DBSY#<8>
H_DRDY#<8>
+1.2VP
1 2
R124 56_0402
12
+
H_VSSA
Thermal Sensor
MAX6654MEE
W=15mil
1 2
U11
1
NC
2
VCC
3
DXP
SMBCLK
4
DXN
5
NC
SMBDATA
6
ADD1
GND
GND
MAX6654MEE
ALERT
7
8
C
H_RS#0<8>
H_RS#1<8>
H_RS#2<8>
H_A20M#<16>
H_SMI#<16>
H_INTR<16>
H_NMI<16>
H_INIT#<16>
H_BSEL0<14>
H_BSEL1<14>
H_THERMTRIP#
TP1
1
C94
22U_1206_10V4Z
+5VALW
C198
.1UF_0402
16
NC
15
STBY
14
13
NC
12
11
10
ADD0
9
NC
R199
1K_0402
C
12
R34 M@0_0402
DT : REMOVE
F1
G5
F4
AB2
J6
H_A20M#
H_F_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLPR#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_THERMDA
H_THERMDC
ITP_BPM0
ITP_BPM1
ITP_BPM2
ITP_BPM3
ITP_PRDY#
ITP_PREQ#
ITP_TCK
ITP_TDI
ITP_TMS
ITP_TRST#
H_VCCA
H_VCCIOPLL
R56
51.1_1%
R190
1 2
1 2
+5VALW
C6
B6
B2
B5
AB23
Y4
AD25
D1
E5
W5
AB25
H5
H2
AD6
AD5
B3
C4
A2
AC6
AB5
AC4
Y6
AA5
AB4
D4
C1
D5
F7
E6
AD20
A5
AE23
AF25
AF3
AC26
AD26
L24
P1
R142
51.1_1%
1 2
1 2
10K_0402
CPU_THRM# PROCHOT#
R195
10K_0402
1 2
D
AE11
AE13
AE15
U41B
VSS_57
VSS_58
VSS_59
RS#0
RS#1
RS#2
RSP#
TRDY#
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC
THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCA
VCCSENSE
VCCIOPLL
NC7
NC8
ITP_CLK0
ITP_CLK1
COMP0
COMP1
VSS_129F8VSS_130
G21
EC_SMC2 <30,39>
EC_SMD2 <30,39>
12
R172
@0_0402
D
AE17
AE19
VSS_60
VSS_61
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
G24
H_SKTOCC#
AE22
AE24
AE26
AE7
VSS_62
VSS_63
VSS_64
VSS_65
VSS_136
J22
J25
+CPU_CORE
12
R_A
12
R_B
E
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
AF26
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
SKTOCC#
B26
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
NorthWood
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
L23
L26
K21
K24
GTL Reference Vol tage
Layout note :
1. Place R_A and R_B near CPU.
2. Place decoupling cap 220PF near CPU.(Within
500mils )
R57
49.9_1%
Trace width>=7mila
R58
100_1%
M22
M25
C443
1UF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
P22
P25
N21
N24
C442
220PF
F
C11
C13
C15
C17
C19
C22
C25
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
Mobile
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
T21
T24
R23
R26
+H_GTLREF1
F
G
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
H
F10
F12
F14
F16
F18
F22
F25
F5
I
R125 DT@56_0402
1 2
PM_CPUPERF#H_GHI#
1 2
R123 M@0_0402
J
+CPU_CORE
PM_CPUPERF# <16>
DT : REMOVE
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VSS_127
VSS_128
J26
DP#0
K25
DP#1
K26
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
NC1
NC2
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
ITPCLKOUT0
ITPCLKOUT1
TESTHI8
TESTHI9
TESTHI10
GHI#
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
VSSA
VSSSENSE
NC3
VID0
VID1
VID2
VID3
G
S
AE5
AE4
AE3
AE2
+5VS
R632
@301_1%_0402
1 2
Q13
2
@3904
3 1
VID4
NC5
AE1
AE21
@470_0402
1 2
Q76
@3904
3 1
4/29 update
Johnny
NC6
AF24
R153
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
VSS_181
V23
V26
U22
U25
W21
PCIRST#<8,15,16,19,23,25,26,28,34>
MAINPWON<37,40,41>
Y5
Y22
Y25
W24
2
1 3
D
Q15
@2N7002
G
NC4
VCCVID
NorthWood
AF4
CPU_VR_VID4 <7>
CPU_VR_VID3 <7>
CPU_VR_VID2 <7>
CPU_VR_VID1 <7>
CPU_VR_VID0 <7>
PROCHOT#<30>
R144
2
1 2
@470_0402
H
H_THERMTRIP#
+H_GTLREF1
L25
AA21
AA6
F20
F6
A22
A7
TESTTHI0_1
AD24
AA2
TESTTHI2_7
AC21
AC20
AC24
AC23
ITPCLKOUT0
AA20
ITPCLKOUT1
AB22
TESTTHI8_10
U6
W4
Y3
H_GHI#
A6
H_DSTBN#0
E22
H_DSTBN#1
K22
H_DSTBN#2
R22
H_DSTBN#3
W22
H_DSTBP#0
F21
H_DSTBP#1
J23
H_DSTBP#2
P23
H_DSTBP#3
W23
L5
R5
H_DBI#0
E21
H_DBI#1
G25
H_DBI#2
P26
H_DBI#3
V21
H_DBR#
AE25
H_PROCHOT#
C3
V6
H_SLP#
AB26
H_VSSA
AD22
A4
AD2
AD3
+1.2VP
C145
.1UF_0402
R171
1K_0402
PROCHOT#
Q14
3904
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
All of these pin
connected inside
R25 56_0402
1 2
R27 56_0402
1 2
R49 56_0402
1 2
R50 56_0402
1 2
R102 56_0402
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
1 2
R210 @0_0402
1 2
R145 56_0402
TP2
1 2
3 1
?30, 2002
I
R29 200_0402
1 2
2
Q12
3 1
1
+3VALW
R176
470_0402
2
3904
+CPU_CORE
H_DSTBN#[0..3] <8>
H_DSTBP#[0..3] <8>
H_ADSTB#0 <8>
H_ADSTB#1 <8>
H_DBI#[0..3] <8>
+CPU_CORE
ITP_DBR# <33>
H_SLP# <16>
12
+CPU_CORE
R143
1 2
470_0402
546,
J
H_PROCHOT#
of
2B
Page 6
A
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
1 1
Use 2~3 vias per PAD.
B
C
D
E
Layout note :
Place close to CPU power and
ground pin as possible
(<1inch)
F
+CPU_CORE
G
12
C462
+
DT@470UF_D4_2.5V_10m
12
C449
+
DT@470UF_D4_2.5V_10m
H
12
C441
+
DT@470UF_D4_2.5V_10m
I
12
C492
+
DT@470UF_D4_2.5V_10m
12
C419
+
DT@470UF_D4_2.5V_10m
J
Please place these cap in the socket cavity area
+CPU_CORE
12
2 2
3 3
4 4
5 5
C95
10UF_6.3V_1206_X5R
+CPU_CORE
12
C107
10UF_6.3V_1206_X5R
Please place these cap on the socket north side
+CPU_CORE
12
C80
10UF_6.3V_1206_X5R
+CPU_CORE
12
C128
10UF_6.3V_1206_X5R
+CPU_CORE
12
C429
10UF_6.3V_1206_X5R
12
C122
10UF_6.3V_1206_X5R
12
C106
10UF_6.3V_1206_X5R
12
C92
10UF_6.3V_1206_X5R
12
C61
10UF_6.3V_1206_X5R
12
C430
10UF_6.3V_1206_X5R
12
C89
10UF_6.3V_1206_X5R
12
C465
10UF_6.3V_1206_X5R
12
C104
10UF_6.3V_1206_X5R
12
C59
10UF_6.3V_1206_X5R
12
C423
10UF_6.3V_1206_X5R
12
C113
10UF_6.3V_1206_X5R
12
C461
10UF_6.3V_1206_X5R
12
C428
10UF_6.3V_1206_X5R
12
C57
10UF_6.3V_1206_X5R
12
C53
10UF_6.3V_1206_X5R
12
C98
10UF_6.3V_1206_X5R
12
C445
10UF_6.3V_1206_X5R
12
C118
10UF_6.3V_1206_X5R
12
C56
10UF_6.3V_1206_X5R
Please place these cap on the socket south side
+CPU_CORE
12
C123
10UF_6.3V_1206_X5R
6 6
7 7
+CPU_CORE
12
C447
10UF_6.3V_1206_X5R
+CPU_CORE
12
C176
10UF_6.3V_1206_X5R
12
C115
10UF_6.3V_1206_X5R
12
C83
10UF_6.3V_1206_X5R
12
C426
10UF_6.3V_1206_X5R
12
C159
10UF_6.3V_1206_X5R
12
C495
10UF_6.3V_1206_X5R
12
C427
10UF_6.3V_1206_X5R
12
C116
10UF_6.3V_1206_X5R
12
C174
10UF_6.3V_1206_X5R
12
C55
10UF_6.3V_1206_X5R
12
C448
10UF_6.3V_1206_X5R
12
C175
10UF_6.3V_1206_X5R
EN_FAN2<30>
EMI Clip PAD for CPU
PAD1
PAD-2.5X3
1
A
B
C
D
8 8
For Desktop's CPU:
ESR total=0.75m ohm
C total=6350uF
For Mo b i l e 's CPU:
ESR total=1.875m ohm
C total=2590uF
.1UF_0402
12
R295
13K_1%
+12VS
84
U27A
+
-
R293
7.32K_1%
+12VS
5
6
1
LM358
12
F
C190
EN_FAN1<30>
3
2
12
R296
13K_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
+CPU_CORE
12
C485
+
470UF_D4_2.5V_10m
+CPU_CORE
12
C149
+
330UF_D2_2.5V_15m
+CPU_CORE
12
C456
.22UF_X7R
+12VS
R292
3.48K_1%
84
U27B
+
7
-
LM358
R294
7.32K_1%
3.48K_1%
2
R434
2
12
+12VS
1 2
21
D40
1N4148
31
Q51
2SA1036K
G
12
C455
.22UF_X7R
1 2
21
D27
1N4148
31
Q32
2SA1036K
Q24
FMMT619
C225
2.2UF_16V_0805
1 2
12
C420
+
470UF_D4_2.5V_10m
12
C99
+
330UF_D2_2.5V_15m
12
C480
.22UF_X7R
Q23
FMMT619
C367
2.2UF_16V_0805
1 2
2
3 1
D12
1N4148
2 1
12
C479
.22UF_X7R
2
3 1
D15
1N4148
2 1
New add
5/15 Johnny
D13
1SS355
2 1
C754
33PF_0402
New add
5/15 Johnny
C747
220PF_0402
H
12
C474
+
DT@470UF_D4_2.5V_10m
12
C50
+
330UF_D2_2.5V_15m
12
C478
.22UF_X7R
12
C477
.22UF_X7R
12
C421
+
DT@470UF_D4_2.5V_10m
12
C49
+
330UF_D2_2.5V_15m
12
12
C476
.22UF_X7R
C475
.22UF_X7R
12
C434
+
DT@470UF_D4_2.5V_10m
12
C48
+
330UF_D2_2.5V_15m
12
C450
.22UF_X7R
Fan1 Control circuit
New add
5/15 Johnny
+5VS
D16
C234
1SS355
1000PF_0402
2 1
+5VFAN1
C752
33PF_0402
New add
5/15 Johnny
C746
220PF_0402
+5VS
C222
1000PF_0402
+5VFAN2
C753
.1uF_0402
+3VS
12
Title
Size Docu ment Number Re v
Custom
Date: Sheet
JP22
C751
1
.1uF_0402
2
3
53398-0310
+3VS
12
R433
10K_0402
FAN_SPEED <30>
Fan2 Control circuit
JP23
1
2
3
53398-0310
R220
10K_0402
FAN_SPEED2 <30>
Compal Electronics, Inc.
SCHEM AT IC , M/ B LA- 1381
401212
星期一 十二
?30, 2002
I
12
C451
.22UF_X7R
646,
2B
of
J
Page 7
10
H H
9
8
7
6
5
4
3
2
1
For Mobile CPU
G G
1K_0402
CPU_VR_VID0<5>
CPU_VR_VID1<5>
CPU_VR_VID2<5>
F F
E E
CPU_VR_VID3<5>
CPU_VR_VID4<5>
CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4
For Desktop CPU
D D
C C
CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4 CPU_VID4
1 2
R399 DT@0_0402
RP89
4 5
3 6
2 7
1 8
DT@8P4R_0
R173
+3VS
12
182736
45
RP8
8P4R_1K
CPU_ECVID0 <31>
CPU_ECVID1 <31>
CPU_ECVID2 <31>
CPU_ECVID3 <31>
CPU_ECVID4 <31>
RP90 M@8P4R_0
4 5
3 6
2 7
1 8
R178 M@0_0402
1 2
+3VALW
R390
DT : REMOVE
M@100K_0402
1 2
1 2
R389
DT@100K_0402
NB/DT#_CPU <31,43>
EC_CPUVID0<31>
EC_CPUVID1<31>
EC_CPUVID2<31>
EC_CPUVID3<31>
EC_CPUVID4<31>
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
1 2
R403 DT@0_0402
RP87
4 5
3 6
2 7
1 8
DT@8P4R_0
CPU_VID0 <43>
CPU_VID1 <43>
CPU_VID2 <43>
CPU_VID3 <43>
CPU_VID4 <43>
@10K_0402
R404
+5VS
12
182736
45
RP86
@8P4R_10K
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
NB/DT_CPU
VID
VCC
1.750V
1.700V
1.650V
1.600V
1.550V
1.500V
1.450V
1.400V
1.350V
1.300V
1.250V
1.200V
1.150V
1.100V
1.050V
1.000V
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V
0.775V
0.750V
0.725V
0.700V
0.675V
0.650V
0.625V
0.600V
Mobil CPU Destop CPU
10
00 01
00000
1
0000
1
000
00 0
00
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000
1
1
1
1
1
1
0000
1
00
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
000
0
000
1
1
00
1
1
00
1
1
0
1
00
1
1
1
00
1
1
00
1
1
0
1
1
1
1
0
1
1
1
00011
1
0000
1
1
000
1
1
0
1
00
1
0
0
0
0
0
11
0
1
11
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
XXXXX
1
X
1
XXX
000
1
XXXXX
000
1
0
1
XXXXX
00
1
XXXXX
1
XXXXX
00
1
XXXXX
0
11111
VRM output off 1 1 1 1
0412134023
0
0
0
0
0
11
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
XXXXX
X
XXXXXXX
X
XX
X
XXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
746,
1
2B
Page 8
A
B
C
D
E
F
G
H
I
J
1 1
HA#[3..31]<4>
2 2
3 3
H_ADSTB#0<5>
H_ADSTB#1<5>
H_RESET#<5>
H_TRDY#<5>
HDEFER#<4>
HBPRI#<4>
HLOCK#<4>
H_DBSY#<5>
H_DRDY#<5>
HIT#<4>
4 4
5 5
+CPU_CORE
R68
301_1%
6 6
R72
150_1%
+CPU_CORE
7 7
R63
301_1%
R64
150_1%
HITM#<4>
HBR0#<4>
HADS#<4>
HBNR#<4>
H_RS#0<5>
H_RS#1<5>
H_RS#2<5>
HREQ#[0 ..4 ]<4>
CLK_GHT<14>
CLK_GHT#<14>
H_DBI#[0..3]<5>
12
12
C88
.01UF_0402
12
12
12
C90
.01UF_0402
12
8 8
A
HA#[3..31]
PCIRST#<5,15,16,19,23,25,26,28,34>
HREQ#[0..4]
H_DBI#[0..3]
24.9_0603_1%
CLK_GHT
CLK_GHT#
12
R48
+1.5VS
R90 8.2K_0402
R45 8.2K_0402
R41 8.2K_0402
B
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_SWNG0
H_SWNG1
12
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7
R5
N6
AE17
U7
Y4
Y7
W5
J27
H26
V5
V4
Y5
Y3
V7
V3
W3
W2
W7
W6
U6
T7
R7
U5
U2
J8
K8
AD5
AG4
AH9
AD15
AA7
AD13
AC2
AC13
R75
24.9_0603_1%
AGP_ADSTB0
12
AGP_ADSTB1
12
AGP_SBSTB
12
U43A
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB#0
HADSTB#1
CPURST#
HTRDY#
DEFER#
BPRI#
HLOCK#
RSTIN#
TESTIN#
DBSY#
DRDY#
HIT#
HITM#
BREQ#0
ADS#
BNR#
RS#0
RS#1
RS#2
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
BCLK
BCLK#
DBI#0
DBI#1
DBI#2
DBI#3
HSWNG0
HSWNG1
HRCOMP0
HRCOMP1
H_DSTBN#[0..3]
H_DSTBP#[0..3]
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
BROOKDALE(MCH-M)
H_DSTBN#[0..3] <5>
H_DSTBP#[0..3] <5>
R83 @8.2K_0402
R44 @8.2K_0402
R40 @8.2K_0402
C
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4
AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16
AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16
M7
R8
Y8
AB11
AB17
12
12
12
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBSTB#
HD#[0..63]
+V_MCH_GTLREF
AGP_ST0
0=System memory is DDR
1=System memory is SDR
D
HD#[0..63] <4>
AGP_AD[0..31]<15>
AGP_C/BE#[0..3]<15>
AGP_ST[0..2]<15>
+CPU_CORE
12
R66
R_E
49.9_1%
12
R65
R_F
100_1%
GTL Reference Vol tage
Layout note :
1. Place R_E and R_F near MCH
2. Place decoupling cap 220PF near MCH pin.(Within
500mils )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
AGP_AD[0..31] HUB_PD[0..10]
AGP_ADSTB0<15>
AGP_ADSTB0#<15>
AGP_ADSTB1<15>
AGP_ADSTB1#<15>
AGP_SBSTB<15>
AGP_SBSTB#<15>
AGP_FRAME#<15>
AGP_DEVSEL#<15>
AGP_IRDY#<15>
AGP_TRDY#<15>
AGP_STOP#<15>
AGP_PAR<15>
AGP_REQ#<15>
AGP_GNT#<15>
Trace
width>=7mila
C103
C102
220PF
1UF
R337 2K_0402
AGP_ST0 AGP_ST1
12
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_ST0
AGP_ST1
AGP_ST2
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#
AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#
F
U43B
R27
G_AD0
R28
G_AD1
T25
G_AD2
R25
G_AD3
T26
G_AD4
T27
G_AD5
U27
G_AD6
U28
G_AD7
V26
G_AD8
V27
G_AD9
T23
G_AD10
U23
G_AD11
T24
G_AD12
U24
G_AD13
U25
G_AD14
V24
G_AD15
Y27
G_AD16
Y26
G_AD17
AA28
G_AD18
AB25
G_AD19
AB27
G_AD20
AA27
G_AD21
AB26
G_AD22
Y23
G_AD23
AB23
G_AD24
AA24
G_AD25
AA25
G_AD26
AB24
G_AD27
AC25
G_AD28
AC24
G_AD29
AC22
G_AD30
AD24
G_AD31
V25
G_C/BE#0
V23
G_C/BE#1
Y25
G_C/BE#2
AA23
G_C/BE#3
AG25
ST0
AF24
ST1
AG26
ST2
R24
AD_STB0
R23
AD_STB#0
AC27
AD_STB1
AC28
AD_STB#1
AF27
SB_STB
AF26
SB_STB#
Y24
G_FRAME#
W28
G_DEVSEL#
W27
G_IRDY#
W24
G_TRDY#
W23
G_STOP#
W25
G_PAR
AG24
G_REQ#
AH25
G_GNT#
AF22
PIPE#
N22
VSS0
K27
VSS1
K5
VSS2
L24
VSS3
M23
VSS4
K7
VSS5
J26
VSS6
A3
VSS7
A7
VSS8
A11
VSS9
A15
VSS10
R336 @1K_0402
12
AGP_FRAME#
AGP_TRDY#
AGP_PAR
AGP_STOP#
AGP_GNT#
AGP_REQ#
AGP_IRDY#
AGP_DEVSEL#
AGP_WBF#
AGP_PIPE#
AGP_RBF#
AGP_ST2
G
HUB
HI_STB#
HLRCOMP
AGP
AGPREF
GRCOMP
BROOKDALE(MCH-M)
+1.5VS
RP4 @8P4R_8.2K
1 8
2 7
3 6
4 5
RP83 @8P4R_8.2K
1 8
2 7
3 6
4 5
RP3 @8P4R_8.2K
1 8
2 7
3 6
4 5
R62 6.2K_0402
12
6.2K_0402
R39
12
HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10
HI_STB
HI_REF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
66IN
RBF#
WBF#
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24
N25
N24
P27
P26
AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25
AA21
AD25
P22
AE22
AE23
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J29
AGP_ST1
0=533Mhz
1=400Mhz
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HLRCOMP
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
CLK_AGP_MCH
AGP_RBF#
AGP_WBF#
H
HUB_PD[0..10] <16>
HUB_PSTRB <16>
HUB_PSTRB# <16>
R85
1 2
AGP_SBA[0..7]
36.5_1%
AGP_SBA[0..7] <15>
Place this cap near MCH
+AGPREF
12
C84
.1UF_0402
R53
36.5_1%
12
CLK_AGP_MCH <14>
AGP_RBF# <15>
AGP_WBF# <15>
+1.5VS
12
Place this cap near AGP
R22
1K_1%
AGP_NBREF
Title
Size Docu ment Number Re v
Custom
Date: Sheet
12
R23
1K_1%
HUB Interface Reference
Layout note :
+1.8VS
1. Pla c e R_C and R_D in middle of Bus.
2. Place capacitors near MCH.
12
12
R69
301_1%
12
12
12
12
R78
301_1%
R_C
R_D
Compal Electronics, Inc.
SCHEM AT IC , M/ B LA- 1381
401212
星期一 十二
?30, 2002
I
+VS_HUBREF
+1.8VS
Place closely
ball P26
Place closely pin P22
CLK_AGP_MCH
R94
@33_0402
1 2
C121
@10PF_0402
12
C47
.1UF_0402
C108
@470PF
R84
@56.2_1%
+VS_HUBREF
R71
0_0402
C100
.01UF_0402
846,
12
C120
.01UF_0402
of
J
2B
Page 9
A
B
C
D
E
F
G
H
I
J
U43D
M8
+CPU_CORE
1 1
2 2
+2.5V
3 3
4 4
5 5
6 6
7 7
VTT_0
U8
VTT_1
AA9
VTT_2
AB8
VTT_3
AB18
VTT_4
AB20
VTT_5
AC19
VTT_6
AD18
VTT_7
AD20
VTT_8
AE19
VTT_9
AE21
VTT_10
AF18
VTT_11
AF20
VTT_12
AG19
VTT_13
AG21
VTT_14
AG23
VTT_15
AJ19
VTT_16
AJ21
VTT_17
AJ23
VTT_18
A5
VCCSM1
A9
VCCSM2
A13
VCCSM3
A17
VCCSM4
A21
VCCSM5
A25
VCCSM6
C1
VCCSM7
C29
VCCSM8
D7
VCCSM9
D11
VCCSM10
D15
VCCSM11
D19
VCCSM12
D23
VCCSM13
D25
VCCSM14
F6
VCCSM15
F10
VCCSM16
F14
VCCSM17
F18
VCCSM18
F22
VCCSM19
G1
VCCSM20
G4
VCCSM21
G29
VCCSM22
H8
VCCSM23
H10
VCCSM24
H12
VCCSM25
H14
VCCSM26
H16
VCCSM27
H18
VCCSM28
H20
VCCSM29
H22
VCCSM30
H24
VCCSM31
K22
VCCSM32
K24
VCCSM33
K26
VCCSM34
L23
VCCSM35
K6
VCCSM36
J5
VCCSM37
J7
VCCSM38
L1
VSS41
L4
VSS42
L6
VSS43
L8
VSS44
L22
VSS45
L26
VSS46
N1
VSS47
N4
VSS48
N8
VSS49
N13
VSS50
N15
VSS51
N17
VSS52
N29
VSS53
P6
VSS54
P8
VSS55
P14
VSS56
P16
VSS57
R1
VSS58
R4
VSS59
R13
VSS60
R15
VSS61
R17
VSS62
R26
VSS63
T6
VSS64
T8
VSS65
T14
VSS66
T16
VSS67
T22
VSS68
U1
VSS69
U4
VSS70
U15
VSS71
U29
VSS72
V6
VSS73
V8
VSS74
V22
VSS75
W1
VSS76
W4
VSS77
W8
VSS78
W26
VSS79
Y6
VSS80
Y22
VSS81
AA1
VSS82
BROOKDALE(MCH-M)
POWER/GND
VCC1_5_0
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8
VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15
VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25
VCC1_8_0
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCCGA1
VCCHA1
VSSGA2
VSSHA2
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25
N14
N16
P13
P15
P17
R14
R16
T15
U14
U16
L29
N26
L25
M22
N23
T17
T13
U17
U13
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ27
VCC_MCH_PLL1
VCC_MCH_PLL0
VSS_MCH_PLL1
VSS_MCH_PLL0
+1.5VS
Layout note :
Trace width 5mil ; Spacing
10mil
Trace A to ball U13/T13 or
U17/T7 =1.5" Max
+1.5VS
+1.8VS
12
"Trace A"
12
+
"Trace A"
"Trace A"
L22
4.7UH_30mA
"Trace A"
C169
33UF_D2_16V
Murata LQG21N4R7K10
12
L21
4.7UH_30mA
12
C168
+
33UF_D2_16V
DDR_SDQ[0..63]<11>
DDR_CB[0..7]<11>
SDREF
DDR_SDQ[0..63]
DDR_CB[0..7]
12
0_0402
R108
.1UF_0402_X5R
Layout note
Please closely
pin J21 and J9
DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7
SDREF_M
12
C141
U43C
G28
SDQ0
F27
SDQ1
C28
SDQ2
E28
SDQ3
H25
SDQ4
G27
SDQ5
F25
SDQ6
B28
SDQ7
E27
SDQ8
C27
SDQ9
B25
SDQ10
C25
SDQ11
B27
SDQ12
D27
SDQ13
D26
SDQ14
E25
SDQ15
D24
SDQ16
E23
SDQ17
C22
SDQ18
E21
SDQ19
C24
SDQ20
B23
SDQ21
D22
SDQ22
B21
SDQ23
C21
SDQ24
D20
SDQ25
C19
SDQ26
D18
SDQ27
C20
SDQ28
E19
SDQ29
C18
SDQ30
E17
SDQ31
E13
SDQ32
C12
SDQ33
B11
SDQ34
C10
SDQ35
B13
SDQ36
C13
SDQ37
C11
SDQ38
D10
SDQ39
E10
SDQ40
C9
SDQ41
D8
SDQ42
E8
SDQ43
E11
SDQ44
B9
SDQ45
B7
SDQ46
C7
SDQ47
C6
SDQ48
D6
SDQ49
D4
SDQ50
B3
SDQ51
E6
SDQ52
B5
SDQ53
C4
SDQ54
E5
SDQ55
C3
SDQ56
D3
SDQ57
F4
SDQ58
F3
SDQ59
B2
SDQ60
C2
SDQ61
E2
SDQ62
G5
SDQ63
C16
SDQ64/CB0
D16
SDQ65/CB1
B15
SDQ66/CB2
C14
SDQ67/CB3
B17
SDQ68/CB4
C17
SDQ69/CB5
C15
SDQ70/CB6
D14
SDQ71/CB7
J21
SDREF0
J9
SDREF1
12
C134
.1UF_0402_X5R
SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5
SCK6
SCK#6
SCK7
SCK#7
SCK8
SCK#8
SCS#0
SCS#1
SCS#2
SCS#3
SCS#4
MEMORY
SCS#5
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SMA0/CS#11
SMA1/CS#10
SMA2/CS#6
SMA3/CS#9
SMA4/CS#5
SMA5/CS#8
SMA6/CS#7
SMA7/CS#4
SMA8/CS#3
SMA9/CS#0
SMA10
SMA11/CS#2
SMA12/CS#1
SBS0
SBS1
SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5
SMRCOMP
RCVENIN#
RCVENOUT#
SSI_ST
SRAS#
SWE#
SCAS#
NC0
NC1
BROOKDALE(MCH-M)
E14
F15
J24
G25
G6
G7
G15
G14
E24
G24
H5
F5
K25
J25
G17
G16
H7
H6
E9
F7
F9
E7
G9
G10
F26
C26
C23
B19
D12
C8
C5
E3
E15
E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22
G12
G13
G23
E22
H23
F23
J23
K23
J28
G3
H3
H27
F11
G11
G8
AD26
AD27
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SBS0
DDR_SBS1
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
SM_RCOMP
RCVIN#
RCVOUT#
DDR_SRAS#
DDR_SWE#
DDR_SCAS#
DDR_CLK0 <11>
DDR_CLK0# <11>
DDR_CLK1 <11>
DDR_CLK1# <11>
DDR_CLK2 <11>
DDR_CLK2# <11>
DDR_CLK3 <12>
DDR_CLK3# <12>
DDR_CLK4 <12>
DDR_CLK4# <12>
DDR_CLK5 <12>
DDR_CLK5# <12>
DDR_SCS#0 <11>
DDR_SCS#1 <11>
DDR_SCS#2 <12>
DDR_SCS#3 <12>
DDR_SDQS0 <11>
DDR_SDQS1 <11>
DDR_SDQS2 <11>
DDR_SDQS3 <11>
DDR_SDQS4 <11>
DDR_SDQS5 <11>
DDR_SDQS6 <11>
DDR_SDQS7 <11>
DDR_SDQS8 <11>
DDR_SMA[0..12]
DDR_SBS0 <11>
DDR_SBS1 <11>
DDR_CKE0 <11>
DDR_CKE1 <11>
DDR_CKE2 <12>
DDR_CKE3 <12>
R113 27.4_1%
12
0_0402
R112
R_J
DDR_SRAS# <11>
DDR_SWE# <11>
DDR_SCAS# <11>
Layout note
Place R_J closely Ball
H3<40mil,Ball H3 to G3
trace must
routing 1"
DDR_SMA[0..12] <11>
12
C142 .1UF_0402_X5R
C143 @47PF_0402
+1.25VS
Layout note
Place R113
closely ball
J28
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
946,
J
2B
Page 10
10
9
8
7
6
5
4
3
2
1
Layout note :
Distribute as close as possible
H H
G G
F F
to MCH Processor Quadrant.(between VTTFSB and VSS pin)
+CPU_CORE
12
C63
.1UF_0402_X5R
+CPU_CORE
12
C109
.1UF_0402_X5R
+CPU_CORE
12
C52
10UF_6.3V_1206_X5R
Layout note :
E E
Distribute as close as possible
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)
+1.5VS
12
C114
.1UF_0402_X5R
Processor system bus
12
C62
.1UF_0402_X5R
12
C82
.1UF_0402_X5R
12
10UF_6.3V_1206_X5R
12
C66
.1UF_0402_X5R
12
C70
.1UF_0402_X5R
C54
AGP/CORE
12
C96
.1UF_0402_X5R
12
C105
.1UF_0402_X5R
12
C78
.1UF_0402_X5R
12
C69
.1UF_0402_X5R
12
C425
10UF_6.3V_1206_X5R
12
C85
.1UF_0402_X5R
12
C125
.1UF_0402_X5R
12
C81
.1UF_0402_X5R
12
C97
.1UF_0402_X5R
12
C119
.1UF_0402_X5R
Layout note :
Distribute as close as possible
to MCH P rocessor Quadrant.(bet ween VCCSM and VSS pin)
+2.5V
12
C136
.1UF_0402_X5R
+2.5V
12
C146
.1UF_0402_X5R
+2.5V
12
C163
.1UF_0402_X5R
+2.5V
12
C167
+
220UF_D2_4V
DDR Memory interface
12
C137
.1UF_0402_X5R
12
C160
.1UF_0402_X5R
12
C157
.1UF_0402_X5R
12
C139
.1UF_0402_X5R
12
C164
.1UF_0402_X5R
12
C158
.1UF_0402_X5R
12
C140
.1UF_0402_X5R
12
C165
.1UF_0402_X5R
12
C152
.1UF_0402_X5R
12
C135
.1UF_0402_X5R
12
C162
.1UF_0402_X5R
12
C144
.1UF_0402_X5R
12
C150
22UF_10V_1206
12
C166
22UF_10V_1206
D D
+1.5VS
12
C126
10UF_6.3V_1206_X5R
12
C86
10UF_6.3V_1206_X5R
12
C75
+
100UF_D_16V
C C
Layout note :
Distribute as close as possible
to MCH Processor Quadr ant.(between VCCHL and VSS pin)
+1.8VS
12
B B
C130
10UF_6.3V_1206_X5R
A A
Hub-Link
12
C127
.1UF_0402_X5R
10
12
C132
.1UF_0402_X5R
9
12
C133
.1UF_0402_X5R
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
8
7
6
5
4
3
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
10 46,
1
2B
Page 11
A
Layout note
Place these resistor
closely DIMM0,
all trace length<750mil
1 1
2 2
3 3
4 4
5 5
DDR_SDQ[0..63]<9>
6 6
DDR_CB[0..7]<9>
DDR_SD QS [0 ..8 ]<9>
7 7
8 8
A
B
DDR_SDQ0
DDR_SDQ4
DDR_SDQ1
DDR_SDQ5
DDR_SDQ6
DDR_SDQS0
DDR_SDQ2
DDR_SDQ3
DDR_SDQ8
DDR_SDQ7
DDR_SDQ9
DDR_SDQ12
DDR_SDQS1
DDR_SDQ13
DDR_SDQ10
DDR_SDQ14
DDR_SDQ15
DDR_SDQ11
DDR_SDQ16
DDR_SDQ20
DDR_SDQ21
DDR_SDQ17
DDR_SDQ18
DDR_SDQS2
DDR_SDQ19
DDR_SDQ22
DDR_SDQ24
DDR_SDQ23
DDR_SDQ25
DDR_SDQ28
DDR_SDQS3
DDR_SDQ29
DDR_SDQ56
DDR_SDQ51
DDR_SDQ60
DDR_SDQ57
DDR_SDQS7
DDR_SDQ61
DDR_SDQ62
DDR_SDQ58
DDR_SDQ63 DDR_DQ63
DDR_SDQ59 DDR_DQ59
RP109 4P2R_22
1 4
2 3
RP130 4P2R_22
1 4
2 3
RP131 4P2R_22
1 4
2 3
RP110 4P2R_22
1 4
2 3
RP132 4P2R_22
1 4
2 3
RP92 4P2R_22
1 4
2 3
RP111 4P2R_22
1 4
2 3
RP93 4P2R_22
1 4
2 3
RP112 4P2R_22
1 4
2 3
RP94 4P2R_22
1 4
2 3
RP113 4P2R_22
1 4
2 3
RP95 4P2R_22
1 4
2 3
RP120 4P2R_22
1 4
2 3
RP96 4P2R_22
1 4
2 3
RP114 4P2R_22
1 4
2 3
RP97 4P2R_22
1 4
2 3
DDR_SDQ[0..63]
DDR_CB[0..7]
DDR _ S DQS[0..8]
RP127 4P2R_22
1 4
2 3
RP106 4P2R_22
1 4
2 3
RP128 4P2R_22
1 4
2 3
RP108 4P2R_22
1 4
2 3
RP129 4P2R_22
1 4
2 3
DDR_DQ0
DDR_DQ4
DDR_DQ1
DDR_DQ5
DDR_DQ6
DDR_DQS0
DDR_DQ2
DDR_DQ3
DDR_DQ8
DDR_DQ7
DDR_DQ9
DDR_DQ12
DDR_DQS1
DDR_DQ13
DDR_DQ10
DDR_DQ14
DDR_DQ15
DDR_DQ11
DDR_DQ16
DDR_DQ20
DDR_DQ21
DDR_DQ17
DDR_DQ18
DDR_DQS2
DDR_DQ19
DDR_DQ22
DDR_DQ24
DDR_DQ23
DDR_DQ25
DDR_DQ28
DDR_DQS3
DDR_DQ29
DDR_DQ56
DDR_DQ51
DDR_DQ60
DDR_DQ57
DDR_DQS7
DDR_DQ61
DDR_DQ62
DDR_DQ58
B
C
DDR_SDQ30
DDR_SDQ26
DDR_SDQ31
DDR_SDQ27
DDR_CB5
DDR_CB4
DDR_CB1
DDR_CB0
DDR_CB2
DDR_SDQS8
DDR_CB3
DDR_CB6
DDR_CB7
DDR_SDQ36
DDR_SDQ32
DDR_SDQ33
DDR_SDQ37
DDR_SDQ38
DDR_SDQS4
DDR_SDQ39
DDR_SDQ34
DDR_SDQ44
DDR_SDQ35
DDR_SDQ45
DDR_SDQ40
DDR_SDQS5
DDR_SDQ41
DDR_SDQ43
DDR_SDQ42
DDR_SDQ47
DDR_SDQ46
DDR_SDQ49
DDR_SDQ48
DDR_SDQ53
DDR_SDQ52
DDR_SDQ54
DDR_SDQS6
DDR_SDQ55
DDR_SDQ50
C
D
RP115 4P2R_22
1 4
2 3
RP98 4P2R_22
1 4
2 3
RP116 4P2R_22
1 4
2 3
RP99 4P2R_22
1 4
2 3
RP121 4P2R_22
1 4
2 3
RP100 4P2R_22
1 4
2 3
RP117 4P2R_22
1 4
2 3
RP122 4P2R_22
1 4
2 3
RP102 4P2R_22
1 4
2 3
RP123 4P2R_22
1 4
2 3
RP103 4P2R_22
1 4
2 3
RP118 4P2R_22
1 4
2 3
RP119 4P2R_22
1 4
2 3
RP101 4P2R_22
1 4
2 3
RP104 4P2R_22
1 4
2 3
RP124 4P2R_22
1 4
2 3
RP125 4P2R_22
1 4
2 3
RP105 4P2R_22
1 4
2 3
RP126 4P2R_22
1 4
2 3
RP107 4P2R_22
1 4
2 3
D
DDR_DQ30
DDR_DQ26
DDR_DQ31
DDR_DQ27
DDR_F_CB5
DDR_F_CB4
DDR_F_CB1
DDR_F_CB0
DDR_F_CB2
DDR_DQS8
DDR_F_CB3
DDR_F_CB6
DDR_F_CB7
DDR_DQ36
DDR_DQ32
DDR_DQ33
DDR_DQ37
DDR_DQ38
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ44
DDR_DQ35
DDR_DQ45
DDR_DQ40
DDR_DQS5
DDR_DQ41
DDR_DQ43
DDR_DQ42
DDR_DQ47
DDR_DQ46
DDR_DQ49
DDR_DQ48
DDR_DQ53
DDR_DQ52
DDR_DQ54
DDR_DQS6
DDR_DQ55
DDR_DQ50
E
DDR_DQ4
DDR_DQ5
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ12
DDR_DQ13
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_CLK1<9>
DDR_CLK1#<9>
DDR_DQ20
DDR_DQ17
DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ28
DDR_DQ29
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_F_CB4
DDR_F_CB0 DDR_F_CB1
DDR_DQS8
DDR_F_CB6
DDR_F_CB7
DDR_CLK0<9>
DDR_CLK0#<9>
DDR_CKE1<9>
DDR_SCS#0<9>
DIMM_SMDATA<12,14>
DIMM_SMCLK<12,14>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_CKE1 DDR_CKE0
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#0 DDR_SCS#1
DDR_DQ36
DDR_DQ33
DDR_DQS4
DDR_DQ38
DDR_DQ39
DDR_DQ44
DDR_DQ45
DDR_DQS5
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ60
DDR_DQS7
DDR_DQ62
DDR_DQ63
E
F
+2.5V +2.5V
JP25
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
+3VS
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Normal
Front side / H=5.2mm
F
DIMM0
G
DU/RESET#
DU/BA2
G
VREF
VDD
DM0
DQ12
VDD
DQ13
DM1
DQ14
DQ15
VDD
VDD
DQ20
DQ21
VDD
DM2
DQ22
DQ23
DQ28
VDD
DQ29
DM3
DQ30
DQ31
VDD
DM8
VDD
VDD
VDD
CKE0
VDD
RAS#
CAS#
DQ36
DQ37
VDD
DM4
DQ38
DQ39
DQ44
VDD
DQ45
DM5
DQ46
DQ47
VDD
CK1#
DQ52
DQ53
VDD
DM6
DQ54
DQ55
DQ60
VDD
DQ61
DM7
DQ62
DQ63
VDD
VSS
DQ4
DQ5
DQ6
VSS
DQ7
VSS
VSS
VSS
VSS
VSS
CB4
CB5
VSS
CB6
CB7
VSS
VSS
VSS
BA1
VSS
VSS
VSS
CK1
VSS
VSS
VSS
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
H
DDR_DQ0
DDR_DQ1
DDR_DQ6
DDR_DQ2
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ15
DDR_DQ16
DDR_DQ21
DDR_DQ18
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DQ30
DDR_DQ31
DDR_F_CB5
DDR_F_CB2
DDR_F_CB3
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_DQ32
DDR_DQ37
DDR_DQ34
DDR_DQ35
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ52
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ61
DDR_DQ58
DDR_DQ59
DDR_SBS0<9>
DDR_SWE#<9>
DDR_SCAS#<9>
DDR_SRAS#<9>
DDR_SBS1<9>
H
SDREF_DIMM
12
C254
.1UF_0402
R229
I
DDR_DQ[0..63]
DDR_F_CB [0..7]
DDR_DQS[0..8]
12
SDREF
0_0402
DDR_SMA[0..12] <9>
DDR_SMA12
1 4
DDR_SMA9
2 3
DDR_SMA8
1 4
DDR_SMA11
2 3
DDR_SMA7
1 4
DDR_SMA5
2 3
DDR_SMA4
1 4
DDR_SMA6
2 3
DDR_SMA3
1 4
DDR_SMA1
2 3
DDR_SMA0
1 4
DDR_SMA2
2 3
R224 10_0402
DDR_SMA10 DDR_F_SMA10
1 2
DDR_F_SMA[0..12]<12>
DDR_DQ[0..63] <12>
DDR_F_CB[0..7] <12>
DDR_DQS[0..8] <12>
RP18 4P2R_10
RP16 4P2R_10
RP14 4P2R_10
RP19 4P2R_10
RP13 4P2R_10
RP12 4P2R_10
J
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA8
DDR_F_SMA11
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA4
DDR_F_SMA6
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA0
DDR_F_SMA2
Layout note
DDR_CKE0 <9>
Place these resistor
closely DIMM0,
all trace length<=750mil
Layout note
Place these resistor
closely DIMM0,
DDR_SCS#1 <9>
DDR_CLK2# <9>
DDR_CLK2 <9>
all trace length
Max=1.3"
RP28 4P2R_56
DDR_CKE1
1 4
DDR_CKE0
2 3
RP24 4P2R_56
DDR_SCS#0
1 4
DDR_SCS#1
2 3
+1.25VS
Layout note
Place these resistor
closely DIMM0,
all trace
length<=750mil
DDR_SBS0
DDR_SWE#
DDR_SCAS#
DDR_SRAS#
DDR_SBS1
Title
Size Docu ment Number Re v
Custom
Date: Sheet
RP15 4P2R_10
DDR_F_SBS0
1 4
2 3
RP17 4P2R_10
1 4
2 3
R223 10_0402
1 2
DDR_F_SWE#
DDR_F_SCAS#
DDR_F_SRAS#
DDR_F_SBS1
DDR_F_SBS0 <12>
DDR_F_SWE# <12>
DDR_F_SCAS# <12>
DDR_F_SRAS# <12>
DDR_F_SBS1 <12>
Compal Electronics, Inc.
SCHEM AT IC , M/ B LA- 1381
401212
星期一 十二
?30, 2002
I
11 46,
of
J
2B
Page 12
A
+1.25VS
RP78 4P2R_56
DDR_DQ4
1 4
DDR_DQ0
1 1
2 2
3 3
4 4
5 5
6 6
2 3
RP77 4P2R_56
DDR_DQ5
1 4
DDR_DQ1
2 3
RP76 4P2R_56
DDR_DQS0
1 4
DDR_DQ6
2 3
RP75 4P2R_56
DDR_DQ3
1 4
DDR_DQ2
2 3
RP74 4P2R_56
DDR_DQ7
1 4
DDR_DQ8
2 3
RP73 4P2R_56
DDR_DQ12
1 4
DDR_DQ9
2 3
RP72 4P2R_56
DDR_DQS1
1 4
DDR_DQ13
2 3
RP71 4P2R_56
DDR_DQ14
1 4
DDR_DQ10
2 3
RP70 4P2R_56
DDR_DQ11
1 4
DDR_DQ15
2 3
RP69 4P2R_56
DDR_DQ20
1 4
DDR_DQ16
2 3
RP68 4P2R_56
DDR_DQ17
1 4
DDR_DQ21
2 3
RP66 4P2R_56
DDR_DQS2
1 4
DDR_DQ18
2 3
RP67 4P2R_56
DDR_DQ22
1 4
DDR_DQ19
2 3
RP65 4P2R_56
DDR_DQ23
1 4
DDR_DQ24
2 3
RP64 4P2R_56
DDR_DQ28
1 4
DDR_DQ25
2 3
RP63 4P2R_56
DDR_DQS3
1 4
DDR_DQ29
2 3
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
7 7
EMI Clip PAD for Memory Door
B
RP62 4P2R_56
14
23
RP61 4P2R_56
14
23
RP60 4P2R_56
14
23
RP59 4P2R_56
14
23
RP58 4P2R_56
14
23
RP57 4P2R_56
14
23
RP29 4P2R_56
14
23
RP55 4P2R_56
14
23
RP54 4P2R_56
14
23
RP53 4P2R_56
14
23
RP52 4P2R_56
14
23
RP50 4P2R_56
14
23
RP51 4P2R_56
14
23
RP49 4P2R_56
14
23
RP48 4P2R_56
14
23
RP47 4P2R_56
14
23
DDR_DQ26
DDR_DQ30
DDR_DQ27
DDR_DQ31
DDR_F_CB4
DDR_F_CB5
DDR_F_CB0
DDR_F_CB1
DDR_F_CB2
DDR_DQS8
DDR_F_CB3
DDR_F_CB6
DDR_F_CB7
DDR_DQ36
DDR_DQ32
DDR_DQ37
DDR_DQ33
DDR_DQ38
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ35
DDR_DQ44
DDR_DQ40
DDR_DQ45
DDR_DQ41
DDR_DQS5
DDR_DQ42
DDR_DQ43
DDR_DQ46
DDR_DQ47
+1.25VS
RP46 4P2R_56
RP45 4P2R_56
RP44 4P2R_56
RP43 4P2R_56
RP42 4P2R_56
RP41 4P2R_56
RP40 4P2R_56
RP39 4P2R_56
RP38 4P2R_56
DDR_DQ48
14
DDR_DQ49
23
DDR_DQ52
14
DDR_DQ53
23
DDR_DQ54
14
DDR_DQS6
23
DDR_DQ50
14
DDR_DQ55
23
DDR_DQ51
14
DDR_DQ56
23
DDR_DQ57
14
DDR_DQ60
23
DDR_DQ61
14
DDR_DQS7
23
DDR_DQ58
14
DDR_DQ62
23
DDR_DQ59
14
DDR_DQ63
23
C
D
DDR_F_CB [0..7]
DDR_DQS[0..8]
DDR_DQ[0..63]
DDR_F_SMA[0..12]
E
DDR_F_CB[0..7] <11>
DDR_DQS[0..8] <11>
DDR_DQ[0..63] <11>
DDR_F_SMA[0..12] <11>
F
+2.5V +2.5V
DDR_DQ0
DDR_DQ1
DDR_DQS0
DDR_DQ6
DDR_DQ2
DDR_DQ8
DDR_DQ9
DDR_DQS1
DDR_DQ10
DDR_DQ15
DDR_CLK4<9>
DDR_CLK4#<9>
DDR_DQ16
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DQS3
DDR_DQ30
DDR_DQ31
DDR_F_CB5
DDR_F_CB1 DDR_F_CB0
DDR_DQS8
DDR_F_CB2
DDR_F_CB3
DDR_CLK3<9>
DDR_CLK3#<9>
DDR_CKE3<9>
DDR_F_SBS0<11>
DDR_F_SWE#<11>
DDR_SCS#2<9>
DIMM_SMDATA<11,14>
DIMM_SMCLK<11,14>
DDR_CKE3 DDR_CKE2
DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1
DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#2 DDR_SCS#3
DDR_DQ32
DDR_DQ37
DDR_DQS4
DDR_DQ34
DDR_DQ35
DDR_DQ40
DDR_DQ41
DDR_DQS5
DDR_DQ42
DDR_DQ46
DDR_DQ48
DDR_DQ52
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ61
DDR_DQS7
DDR_DQ58
DDR_DQ59
+3VS
G
JP28
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_Normal
DIMM1
Back side / H=9.2mm
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
CK1#
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
VSS
VDD
BA1
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
H
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
DDR_DQ4
DDR_DQ5
DDR_DQ3
DDR_DQ7
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ11
DDR_DQ20
DDR_DQ17
DDR_DQ22
DDR_DQ23
DDR_DQ28
DDR_DQ29
DDR_DQ26
DDR_DQ27
DDR_F_CB4
DDR_F_CB6
DDR_F_CB7
DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_DQ36
DDR_DQ33
DDR_DQ38
DDR_DQ39
DDR_DQ44
DDR_DQ45
DDR_DQ43
DDR_DQ47
DDR_DQ49
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ60
DDR_DQ62
DDR_DQ63
+3VS
I
SDREF_DIMM
12
C253
.1UF_0402
DDR_CKE2 <9>
DDR_F_SBS1 <11>
DDR_F_SRAS# <11>
DDR_F_SCAS# <11>
DDR_SCS#3 <9>
DDR_CLK5# <9>
DDR_CLK5 <9>
J
+1.25VS
RP27 4P2R_56
DDR_F_SMA9
14
DDR_F_SMA12
23
RP23 4P2R_56
DDR_F_SMA11
14
DDR_F_SMA8
23
RP26 4P2R_56
DDR_F_SMA5
14
DDR_F_SMA7
23
RP22 4P2R_56
DDR_F_SMA6
14
DDR_F_SMA4
23
RP25 4P2R_56
DDR_F_SMA1
14
DDR_F_SMA3
23
RP21 4P2R_56
DDR_F_SMA2
14
DDR_F_SMA0
23
R242 56_0402
R230 56_0402
DDR_CKE2
DDR_CKE3
DDR_SCS#2
DDR_SCS#3
1 2
RP37 4P2R_56
14
23
RP20 4P2R_56
14
23
1 2
RP56 4P2R_56
1 4
2 3
RP36 4P2R_56
1 4
2 3
DDR_F_SMA10
DDR_F_SWE#
DDR_F_SBS0
DDR_F_SRAS#
DDR_F_SCAS#
DDR_F_SBS1
Layout note
Place these resistor
closely DIMM1,
all trace length
Max=1.3"
+1.25VS
8 8
A
B
PAD10
PAD-2.5X3
PAD11
1
PAD-2.5X3
C
PAD12
1
PAD-2.5X3
1
D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
12 46,
J
2B
Page 13
A
B
C
D
E
F
G
H
I
J
Layout note :
Distribute as close as possible
to DDR-SODIMM.
1 1
+2.5V
12
C559
.1UF_0402_X5R
12
C577
.1UF_0402_X5R
12
C560
.1UF_0402_X5R
12
C562
.1UF_0402_X5R
12
C571
.1UF_0402_X5R
12
C558
.1UF_0402_X5R
12
C576
.1UF_0402_X5R
12
C555
.1UF_0402_X5R
12
C575
.1UF_0402_X5R
12
C557
.1UF_0402_X5R
2 2
3 3
4 4
5 5
6 6
+2.5V +2.5V
12
C574
.1UF_0402_X5R
12
C556
.1UF_0402_X5R
12
C570
.1UF_0402_X5R
12
C561
.1UF_0402_X5R
12
C573
.1UF_0402_X5R
12
C572
.1UF_0402_X5R
+
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
+1.25VS
12
C259
.1UF_0402_X5R
+1.25VS
12
C323
.1UF_0402_X5R
+1.25VS
12
C336
.1UF_0402_X5R
+1.25VS
12
C344
.1UF_0402_X5R
12
C324
.1UF_0402_X5R
12
C325
.1UF_0402_X5R
12
C316
.1UF_0402_X5R
12
C328
.1UF_0402_X5R
12
C271
.1UF_0402_X5R
12
C319
.1UF_0402_X5R
12
C317
.1UF_0402_X5R
12
C330
.1UF_0402_X5R
12
C260
.1UF_0402_X5R
12
C309
.1UF_0402_X5R
12
C305
.1UF_0402_X5R
12
C318
.1UF_0402_X5R
12
C347
.1UF_0402_X5R
12
C312
.1UF_0402_X5R
12
C306
.1UF_0402_X5R
12
C331
.1UF_0402_X5R
12
C326
.1UF_0402_X5R
12
C313
.1UF_0402_X5R
12
C346
.1UF_0402_X5R
12
C322
.1UF_0402_X5R
12
C310
.1UF_0402_X5R
12
C314
.1UF_0402_X5R
12
C333
.1UF_0402_X5R
12
C270
.1UF_0402_X5R
12
C255
220UF_D2_6.3V
12
+
12
C311
.1UF_0402_X5R
12
C332
.1UF_0402_X5R
12
C334
.1UF_0402_X5R
12
C329
.1UF_0402_X5R
C273
220UF_D2_6.3V
12
12
12
12
C307
.1UF_0402_X5R
C315
.1UF_0402_X5R
C320
.1UF_0402_X5R
C345
.1UF_0402_X5R
12
C308
.1UF_0402_X5R
12
C335
.1UF_0402_X5R
12
C327
.1UF_0402_X5R
12
C343
.1UF_0402_X5R
+1.25VS
12
C268
7 7
.1UF_0402_X5R
+1.25VS
12
C258
.1UF_0402_X5R
12
C269
.1UF_0402_X5R
12
C257
.1UF_0402_X5R
12
C266
.1UF_0402_X5R
12
C337
.1UF_0402_X5R
12
C267
.1UF_0402_X5R
12
C321
.1UF_0402_X5R
12
C272
.1UF_0402_X5R
12
C342
.1UF_0402_X5R
8 8
A
B
C
12
C338
.1UF_0402_X5R
D
12
C339
.1UF_0402_X5R
12
C340
.1UF_0402_X5R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
12
C341
.1UF_0402_X5R
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
13 46,
J
2B
Page 14
A
B
C
D
E
F
G
H
I
J
1 1
+3VS
SEL0SEL1 Function
00
01
10
2 2
3 3
H_BSEL0<5>
H_BSEL1<5>
SLP_S1#<16,30>
PM_STPPCI#<16>
PM_STPCPU#<16,43>
11
R350
1K_0402
4 4
5 5
CLK_ICH48<16>
CLK_SD48<27>
CLK_ICH14<16>
CLK_14M_SIO<28>
CLK_14M_AUD<21>
66Mhz Host CLK
100Mhz Host CLK
200Mhz Host CLK
133Mhz Host CLK
@1K_0402
1 2
R127 @0_0402
12
1K_0402
R130
R134
+3VS +3VS
12
12
R128
1K_0402
12
12
R129
@1K_0402
R67 M@0_0402
1 2
R672 M@0_0402
1 2
R126 M@0_0402
1 2
Please closely pin42
Place Crystal within 500 mils of CK_Titan
12
R70 DT@1K_0402
+3VS
R671 DT@1K_0402
+3VS
R365 DT@1K_0402
+3VS
+3VS
R76 475_1%
R77 22_0402
R73 22_0402
R131 10_0402
R133 10_0402
R132 10_0402
C154 @10PF_0402
caps are i nternal
to CK_TITAN
C147 @10PF_0402
1 2
1 2
1 2
CK408_PWRGD#<33>
R360 10K_0402
1 2
R351 @10K_0402
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
H_BSEL2
H_BSEL0
BSEL0
DIMM_SMDATA
DIMM_SMCLK
CLK_ICH48M
CLK_SD48M
CLK_ICH14M
Y1
14.318MHZ
L23
BLM21A601SPT
1 2
L52
BLM21A601SPT
1 2
2
3
40
55
54
25
34
53
28
43
29
30
33
35
42
39
38
56
6 6
Note:
or ICS 9508-05
U6
XTAL_IN
XTAL_OUT
SEL2
SEL1
SEL0
PWR_DWN#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
MULT0
SDATA
SCLK
3V66_0/DRCG
3V66_1/VCH_CLK
IREF
48MHZ_USB
48MHZ_DOT
REF
W320-04
+3V_CLK
1
14
VDD_PCI8VDD_PCI
VDD_REF
GND_REF4GND_PCI9GND_PCI15GND_3V6620GND_3V6631GND_48MHZ36GND_IREF41GND_CPU
Width=40 mils
12
+
C507
22UF_10V_1206
50
32
37
VDD_CORE
VDD_CPU46VDD_CPU
VDD_3V6619VDD_3V66
VDD_48MHZ
GND_CORE
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
66MHZ_IN/3V66_5
66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2
PCICLK_F2
PCICLK_F1
PCICLK_F0
47
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
12
C151
.1UF_0402
26
27
45
44
49
48
52
51
24
23
22
21
7
6
5
18
17
16
13
12
11
10
12
C483
.1UF_0402
+3VS_CLKVDD
Width=15 mils
12
C93
.1UF_0402
CLK_BCLK
CLK_BCLK#
CLK_HT
CLK_HT#
CLK_ITP
CLK_ITP#
CLK66_MCH
CLK66_AGP
CLKICH_HUB
CLKPCI_F2
CLKPCI_F0
CLKPCI_MIN
CLKPCI_SD
CLKPCI_LPC
CLKPCI_SIO
CLKPCI_PCM_F
CLKPCI_1394_F
12
12
C458
.1UF_0402
R74 33.2_1%
R80 33.2_1%
R79 33.2_1%
R117 33.2_1%
R521
R86 33.2_1%
R95 33.2_1%
R103 33.2_1%
R104 33.2_1%
R107 33.2_1%
R110 33.2_1%
C488
.1UF_0402
L20
BLM21A601SPT
1 2
12
C87
10UF_10V_1206
1 2
R92 33.2_1%
R82 33.2_1%
1 2
1 2
R105 33.2_1%
R98 33.2_1%
1 2
1 2
R118 @33.2_1%
R109 @33.2_1%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
C138
.1UF_0402
+3VS
USB20@33.2_1%
12
C124
.1UF_0402
1 2
R91 49.9_1%
R_1
R_2
R81 49.9_1%
1 2
1 2
R106 49.9_1%
R_3
R_4
R97 49.9_1%
1 2
1 2
R121 @49.9_1%
R_5
R_6
R111 @49.9_1%
1 2
12
12
12
12
C464
.1UF_0402
CLK_HCLK <4>
Place resistor near R_1,R_2 ;Trace
<=400mils
CLK_HCLK# <4>
CLK_GHT <8>
Place resistor near R_3,R_4 ;Trace
<=400mils
CLK_GHT# <8>
CLK_ITPP <5>
Place resistor near R_5,R_6 ;Trace
<=500mils
CLK_ITPP# <5>
12
C486
470PF_0402
12
C489
47PF_0402
CLK_AGP_MCH <8>
CLK_AGP <15>
CLK_ICHHUB <16>
CLK_ICHPCI <16>
CLK_PCI_USB20 <26>
CLK_PCI_MIN <34>
CLK_PCI_SD <27>
CLK_PCI_LPC <30>
CLK_PCI_SIO <28>
CLK_PCI_PCM <23>
CLK_PCI_1394 <25>
CPU_CLK[2:0] needs to be running in C3, C4.
C112
+12VS
12
7 7
SMB_CLK<16,18>
8 8
A
R154
22_0402
2
G
1 3
D
Q47 2N7002
B
S
2
1 3
D
Q11 2N7002
DIMM_SMDATA
G
DIMM_SMCLK
S
C
DIMM_SMDATA <11,12>SMB_DATA<16,18>
DIMM_SMCLK <11,12>
D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
G
C101
@10PF_0402
H
C117
@10PF_0402
@10PF_0402
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
2B
of
14 46,
J
Page 15
A
1 1
R634
SCRLE D @0_0402
SCROLLED#<30>
MEDI A _LED #<27>
2 2
1 2
New add 5/3
JOHNNY
3 3
4 4
12
C46
.1UF _ 0 402
12
C35
.1UF _ 0 402
12
C406
22UF_10V_1206
5 5
6 6
TV_SYNC
TV_LUMA
1 2
@FBM-11-160808-121
7 7
TV_CRMA
TV_COMPS
12
12
12
R10
S@75_0402
12
C26
S@270PF_0402
R11
R12
S@75_0402
8 8
S@75_0402
A
B
NUMLED#<30>
CAPSLED#<30>
MAIL_LED #<30>
INT_MIC<22>
PID0<28>
PID1<28>
PID2<28>
PID3<28>
PID4<28>
AGP_NBREF
+1.8VS
+1.5VS
+1.8VS+AGPREF
+5VS
12
C129
.1UF _ 0 402
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT _VSYNC
3VDDCDA
3VDDCCL
PID0
PID1
PID2
PID3
PID4
12
C431
.1UF _ 0 402
GNDA
+3VS+2.5VS
12
TV_OUT CONNECTOR
L5
12
C25
S@270PF_0402
D6
@DAN217
2
S@FBM -11-160808-121
S@FBM -11-160808-121
S@FBM -11-160808-121
12
C24
S@270PF_0402
B
D5
@DAN217
1
3
2
1 2
C15 S@22PF_0402
L6
1 2
1 2
C14 S@22PF_0402
L9
1 2
1 2
C21 S@22PF_0402
L7
1 2
C19
S@330PF_0402
C432
.1UF _ 0 402
1
3
12
C
JP3
1
GND
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
GND
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
GND
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
GND
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
GND
83
83
85
85
87
87
89
89
919192
939394
959596
979798
GND99GND
FOXCONN-100P
12
C22
.1UF _ 0 402
12
C16
S@330PF_0402
C
GND
10
12
14
16
18
20
GND
24
26
28
30
32
34
36
38
40
GND
44
46
48
50
52
54
56
58
60
GND
64
66
68
70
72
74
76
78
80
GND
84
86
88
90
+5VALW
D3
@DAN217
2
12
C17
S@330PF_0402
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
12
C65
.1UF _ 0 402
1
3
12
C20
@470PF_0402
+12VALW+1.5VS +5VS
12
C64
.1UF _ 0 402
TV_VCC
1 2
R13 S@0_0402
1 2
R14 @0_0402
TV_SYNCL
TV_LUMAL
TV_CRMAL
TV_COMPSL
D
E
AGP 100X2 Pin connector
Width=60 mils
12
C440
.1UF _ 0 402
M_SEN#<30,31>
AGP_C/BE#[0..3]<8>
AGP_ST[0..2]<8>
AGP_SBA[0..7]<8>
AGP_AD[0..31]<8>
12
R344
100K_0402
M_SEN#
CRT_R
CRT_G
CRT_B
E
FBM-L11-201209-221
R9
75_0402
TV_SYNC
TV_LUMA
TV_CRMA
TV_COMPS
+3VS
+1.25VS_VGA
Change 1.25VS to 1.25VS_VGA
5/3 JOHNNY
+3VS
+5VS
JP13
1
2
3
4
5
6
7
S@S CONN.
D
EC_SMC 1 <30,31, 39>
EC_SMD 1 <30,31, 39>
SUS_STAT# <16,28>
KSO16 <30>
KSI0 <30,33>
KSI1 <30,33>
KSI2 <30,33>
KSI3 <30,33>
KSI4 <30,33>
LID_S W # <30,31>
DRV 0 # <19,28>
ON/OFFBTN# <33>
B++
INV_B+
F
L10
AGP_ST[0..2]
AGP_SBA[0..7]
AGP_AD[0..31]
AGP_C/B#[0..3]
AGP_ADSTB1#<8>
AGP_ADSTB1<8>
AGP_ADSTB0<8>
AGP_ADSTB0#<8>
CLK_AGP<14>
AGP_PAR<8>
AGP_IRDY#<8>
AGP_TRDY#<8>
AGP_GNT#<8>
AGP_REQ#<8>
AGP_BUSY#< 16>
AGP_WBF#<8>
1
2
3 6
+12VALW
+AGPREF
+2.5VS
Q42
FDS4435
4
R342
1 2
75K
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0
8
7
5
FDS4435: P CHANNAL
CRT CONNECTOR
C32
12
10PF_0402
1 2
C33
12
10PF_0402
R7
75_0402
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R8
75_0402
12
1 2
F
Width=60 mils
+5V
13
D
Q41
2
G
S
2N7002
L3
1 2
FCM2012C80_0805
L2
1 2
FCM2012C80_0805
L4
1 2
FCM2012C80_0805
C34
10PF_ 0402
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
INVPWR_B+
D1
@DAN217
2
CRTL_R
CRTL_G
CRTL_B
12
C10
22PF_ 0402
CRT_HSYNC
CRT _VSYNC
G
JP2
GND
GND
3
5
7
9
11
13
15
17
19
GND
GND
23
25
27
29
31
33
35
37
39
GND
GND
43
45
47
49
51
53
55
57
59
GND
GND
63
65
67
69
71
73
75
77
79
GND
GND
83
85
87
89
919192
939394
959596
979798
GND99GND
FOXCONN-100P
1
D4
3
12
C11
22PF_0402
L8
1 2
CHB1608B121
L1
1 2
CHB1608B121
G
4
6
8
10
12
14
16
18
20
24
26
28
30
32
34
36
38
40
44
46
48
50
52
54
56
58
60
64
66
68
70
72
74
76
78
80
84
86
88
90
@DAN217
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
1
3
CRT_ HSYNCRFL
CRT_VSYNCRFL
D2
12
C12
22PF_0402
1
@DAN217
2
H
VGA_DECT
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_C/BE#3
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_C/BE#2
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#1
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1
AGP_RST#
M_SEN#
LVDS_BLON#
+3VS
3
C6
22PF_ 0402
+12VS
H
+5VS
12
2 1
C7
22PF_0402
AGP_SBSTB <8>
AGP_SBSTB# <8>
PM_C3_STAT# <16>
AGP_DEVSEL# <8>
AGP_STOP# <8>
AGP_FRAME# <8>
PIRQA # <16, 18,23,25,26>
AGP_RBF# <8>
+2.5VS
LVDS_BLON#
D33
FUSE_1A
RB411D
12
12
C13
220PF_0402
R661 100K_0402
I
INVPWR_B+
INVT_PWM<30>
DAC_BRIG<30>
R339 0_0402
1 2
1 2
R338 @0_0402
BKOFF#<30>
ENABLT<30>
+3VS
12
R514
10K_0402_5%
13
Q62
2
2N7002
CRT_VCCR_CRT_VCC
F4
21
12
C4
.1UF _ 0 402
R359
2.2K_0402
1 2
CRT_VCC
12
12
C3
220PF_0402
C9
220PF_0402
Compal El ectroni cs, In c.
Title
SCHEMATIC , M/B LA-1381
Size Document Number Re v
401212
C
Date: Sheet
I
R358
2.2K_0402
1 2
1 3
Q85
2N7002
十二月
2
1 3
PCIR ST# <5, 8,16, 19, 23,25, 26, 28,34>
G_RST# <23,24,25, 30>
D42
RB751V
D43
RB751V
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
Q86
2
2N7002
INVT_PWM
DISPOFF#
DAC_BRIG
21
21
JP14
CRT CONN.
+3VS
4.7K_ 0402_5%
1 2
J
1
2
3
4
5
6
7
R513
DISPOFF#
3VDDCDA
3VDDCCL
R667
4.7K_0402
R668
4.7K_0402
15 46星期@, 30, 2002
J
JP33
1
2
3
4
5
6
7
HEADER 7
12
12
of
+3VS
2B
Page 16
A
R226 10K_0402
D17 1SS355
0_0402
PM_PWROK
1 2
R162 10K_0402
1 2
R378 10K_0402
SDATA_IN1
R385 10K_0402
1 2
R376 @10K_0402
IAC_S D ATAO
12
C515
@27PF
1 2
R377 33_0402
12
21
PM_AU XPWRO K
IAC_BITCLK
SDATA_IN0
12
IAC_SYNC
+3VALW
1 1
VLBA#<30>
RSMRST#
C202 .1UF_0402
R200
1 2
1 2
2 2
IAC_BITCLK<21,32,34>
SDATA_IN0<21>
3 3
SDATA_IN1<32,34>
+3VS
IAC_S D ATAO<21,32,34>
4 4
IAC_SYNC<21,32,34>
AC97_RST#<21,32,34>
5 5
Place closely to
ICH3-M
CLK_ICH14
12
R421
@10_0402
12
6 6
C540
@10PF_0402
CLK_ICH48
12
R411
@10_0402
12
C532
@10PF_0402
+RTCVCC
1 2
R248 1K_0402
7 7
+1.8VS
HUB Interface VSwing Voltage
12
R211
301_1%
R_G
301_1%
8 8
R_H
1. Place R_G and R_H in middle of Bus.
12
R216
12
C544
.1UF_0402
+VS_HUBVSWING
A
B
BATTLOW#
1 2
R221 @0_0402
AD[0..31]<23,25,26,34>
SDATAO
R165
12
22_0402
12
C516
@27PF
AC_RST#
C/BE#0<23,25,26,34>
C/BE#1<23,25,26,34>
C/BE#2<23,25,26,34>
C/BE#3<23,25,26,34>
GNT#0<18,25>
GNT#1<18,34>
GNT#2<18,23>
GNT#3<18,26>
GNT#4<18,34>
REQ#0<18,25>
REQ#1<18,34>
REQ#2<18,23>
REQ#3<18,26>
REQ#4<18,34>
+R_VBAIS
C276
1 2
.047UF
1 2
R245 @22M
B
ICH_VGATE<33>
PM_CPUPERF#<5>
PM_GMUXSEL<43>
EC_THRM#<30>
SUS_STAT#<15,28>
PM_STPPCI#<14>
PM_STPCPU#<14,43>
RSMRST#<20,33>
ICH_SWI#<18,30>
PM_PWROK<33>
PBTN_OUT#<30>
PM_DPRSLPVR<43>
PM_CLKRUN#<18,23,25,28,30,34>
PM_C3_STAT#<15>
PM_AU XPWRO K
AGP_BUSY#<15>
1 2
+3VS
R208
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
1 2
EC_SMI#<30>
EC_SCI#<30>
LID_OUT#<30>
SLP_S5#<30>
SLP_S3#<30>
SLP_S1#<14,30>
1 2
R247 10M
R246
@2.4M_1%
J2
K1
J4
K3
H5
K4
H3
L1
L2
G2
L4
H4
M4
J3
M5
J1
F5
N2
G4
P2
G1
P1
F2
P3
F3
R1
E2
N4
D1
P4
E1
P5
K2
K5
N1
R2
A4
E3
D2
D5
B4
D3
F4
A3
R4
E4
C566
12PF
C
10K_0402
U52A
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
ICH3-M
1 2
R441 10M
12
32.768KHZ
C
EC_SMI#
EC_SCI#
LID_OUT#
PM_STPPCI#
RSMRST#
PM_PWROK
BATTLOW#
PCI
Interface
X4
VSS0A1VSS1
12
Y5
V4
AB3
PM_AUXPWROK
PM_AGPBUSY#/GPIO6
VSS2
A13
A16
A17
RTC_VBIAS
RTC_X1
RTC_X2
C582
12PF
V5
PM_BATLOW#
VSS3
A20
AC2
PM_C3_STAT#/GPIO21
VSS4
A23
AB21
PM_CLKRUN#/GPIO24
VSS5
R_K
R_L
AB1
PM_PWRBTN#
PM_DPRSLPVR
VSS6B8VSS7
B10
AA1
AA6
PM_RI#
PM_PWROK
VSS8
VSS9
B13
B14
R205
301_1%
R202
301_1%
D
AA5
W20
AA7
PM_RSMRST#
PM_SLP_S1#/GPIO19
VSS10
VSS11
B15
B18
B19
+RTCVCC
+1.8VS
12
12
D
PM_SLP_S3#
VSS12
C519 @33PF_0402
1 2
1 2
IAC_BITCLK
AA2
AB4
U5
V21
AA4
U21
PM_SLP_S5#
PM_STPPCI#/GPIO18
PM_STPCPU#/GPIO20
V19
Y20
U20
B7
PM_THRM#
PM_SUS_CLK
PM_SUS_STAT#
PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
PM_VGATE/VRMPWRGD
GeyservillePower Ma n a gement
Interface
ICH3-M (1/2)
VSS
VSS13
VSS14
VSS15C3VSS16C6VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
F19
B20
B22
C14
C15
C16
C17
C18
C19
C20
C21
C22
R185 15K
+ICH _HUBREF
CLK_ICH14
CLK_ICH48
CLK_ICH14<14>
CLK_ICH48<14>
1 2
HUB Reference Voltage
Place R_K and R_L
Closely ICH3
E
R383
@22_0402
IAC_SYNC
R382
33_0402
AC_RST#
SDATA_IN1
SDATAO
SDATA_IN0
1 2
A7
D11
AC_RST#
AC_BITCLK
AC'97
C7
B11
C11
AC_SDATAIN0
AC_SDATAIN1
U2
LPC_AD0V1LPC_AD1U3LPC_AD2T3LPC_AD3
AC_SYNC
AC_SDATAOUT
LPC
Interface
LPC_DRQ#0T2LPC_DRQ#1
Clocks EE PROM
VSS26
VSS27D9VSS28
VSS29
VSS30
D13
D16
D17
C189
1UF
CLK_14
VSS31
VSS32
VSS33
VSS34
E5
J23
D20
12
F20
D21
D22
RTC_RST#
R_RTC
Layout note:
Locate J1 and R_RTC on bottom side and with
easy access through memory door
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
U4
CLK_RTEST#Y7CLK_48
RTC_X1
12
12
U1
LPC_FRAME#
CLK_RTCX2
CLK_RTCX1
AC6
AC7
RTC_VBIAS
RTC_X2
J1
JOPEN
R192
1K_0402
AB7
IDE_PATADET
CLK_VBIAS
EC_SCI#
EC_SMI#
W2
GPIO_7V2GPIO_8
unMUX
GPIO
D7
F
GPIO_12Y4GPIO_13Y2GPIO_25W3GPIO_27W4GPIO_28
F
R222 10K_0402
LID_OUT#
LAN_DET#
Y3
J19
LAN
Interface
LAN_TXD2
LAN_JCLKC9LAN_RSTSYNC
A10
C10
LAN_CLK_ICH
R164 22_0402
1 2
1 2
PIRQA#
J21
J20
B1
INT_APICD1
INT_APICD0
INT_APICCLK
Interrupt
Interface
Interface
LAN_RXD0C8LAN_RXD1A8LAN_RXD2A9LAN_TXD0B9LAN_TXD1
D10
G
+3VS
1 2
R417 10K_0402
IRQ14 <18,19>
IRQ15 <18,19>
GPIO5
PIRQC#
GPIO4
PIRQD#
USB20_SMI#
GPIO3
PIRQB#
A6
B2
B5
A5
AB14
C5
INT_PIRQB#C1INT_PIRQA#
INT_IRQ14
INT_PIRQD#A2INT_PIRQC#
INT_PIRQF#/GPIO3
INT_PIRQE#/GPIO2
INT_PIRQH#/GPIO5
INT_PIRQG#/GPIO4
HUB_RCOMP
HUB_VREF
HUB_VSWING
EEP_CSE9EEP_DIND8EEP_DOUTE8EEP_SHCLK
L20
L19
K19
SIRQ <18,23,27,28,30>
H22
W19
INT_IRQ15
INT_SERIRQ
PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB#/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB#/GNT5#
Interface
Managment
Interface
Interface
P23
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI
PCI_PME#
PCI_RST#
PCI_SERR#
PCI_TRDY#
SM_INTRUDER#
SMLINK0
System
SMLINK1
SMB_CLK
Interface
SMB_DATA
SMB_ALERT#/GPIO11
CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU
CPU_INTR
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
STPCLK#
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PAR
HUB_PSTRB
T19
R19
N22
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_CLK
CLK_ICHHUB
HubLink
HUB_PSTRB#
HUB_ICH_RCOMP
LAN_RXD0 <20>
LAN_RXD1 <20>
LAN_RXD2 <20>
LAN_TXD0 <20>
LAN_TXD1 <20>
LAN_TXD2 <20>
LAN_JCLK <20>
LA N_RSTSYNC <20>
STOP#
G
H
LAD0 <27,28,30>
LAD1 <27,28,30>
LAD2 <27,28,30>
LAD3 <27,28,30>
LDRQ#1 <28>
LFRAME# <27,28,30>
SIDEPWR <19>
CLK_ICHPCI
T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1
ICH_WAKE_UP#
W1
Y1
L5
H2
H1
Y6
AC3
AB2
AC4
AB5
AC5
Y22
V23
AB22
H_FERR#
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23
HUB_PD0
L22
HUB_PD1
M21
HUB_PD2
M23
HUB_PD3
N20
HUB_PD4
P21
HUB_PD5
R22
HUB_PD6
R20
HUB_PD7
T23
HUB_PD8
M19
HUB_PD9
P19
HUB_PD10
N19
CLK_ICHHUB <14>
HUB_PSTRB <8>
HUB_PSTRB# <8>
EEP_CS <20>
EEP_DIN <20>
EEP_DOUT <20>
EEP_SHCLK <20>
R161
@1K_0402
1 2
H
I
LAN_DET#
1 2
R167 100K_0402
R381 L AN@0_0402
1 2
R_LAN
LAN enable: Mount R_LAN.
LAN disable: Delete R_LAN.
GPIO4
1 2
R310 @0_0402
USB20_SMI#
USB20_SMI#<26>
PIRQA#<15,18,23,25,26>
PIRQB#<18,26>
PIRQC#<18,26,34>
PIRQD#<18,34>
CLK_ICHPCI <14>
DEVSEL# <18,23,25,26,34>
FRAME# <18,23,25,26,34>
PCI_REQ A# <18>
PCI_REQ B# <18>
IR D Y# <18,23,25,26,34>
PAR <18,23,25,26,34>
PERR # <18,23,25,34>
R264 33_0402
PLOCK# <18,23>
12
SERR # <18,23,25,34>
STOP# <18,23,25,26,34>
TRDY # <18,23,25,26,34>
SM_INTRUDER# <18>
SMLINK0 <18>
SMLINK1 <18>
SMB_CLK <14,18>
SMB_DATA <14,18>
SMB_ALERT# <18>
GATEA20 <30>
H_A20M# <5>
H_IGNNE# <5>
H_INIT# <5>
H_ INTR <5>
H_NMI <5>
H_PWRGD <5>
KBRST# <30>
H_SLP# <5>
H_SMI# <5>
H_STPCLK# <5>
HUB_PD[0..10]
+ICH _HUBREF
Title
Size Document Number Re v
Custom
Date: Sheet
1 2
R384 8.2K_0402
GPIO3
1 2
R380 8.2K_0402
GPIO4
1 2
R379 8.2K_0402
GPIO5
1 2
R166 8.2K_0402
EC_WAKEUP#<31>
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCIRST# <5,8,15,19,23,25,26,28,34>
R233 0_0402
H_FERR#
H_F_FERR#<5>
HUB_PD[0..10] <8>
+VS_HUBVSWING
12
12
C219
.01UF_0402
1 2
+3VS
12
R201
300_0402
Q21
2
3 1
3904
1 2
R209 36.5_1%
C215
.01UF_0402
+3VS
H_DPSLP#<5>
Close to ICH3-M.
Comp al E l e c t ro n i c s , Inc.
SCHEMATIC, M/ B LA-1381
401212
薑 十二月
I
J
+3VS
GAIN_SEL# <22>
+3VALW
12
D14
21
RB751V
Place closely to
ICH3-M
CLK_ICHPCI
12
R225
@10_0402
12
C224
@15PF_0402
+CPU_CORE
12
R228
@10K_0402
(for us e if CPU unable
to support DPSLP#)
12
R204
470_0402
Q19
2
3 1
3904
R194
1 2
470_0402
CLK_ICHHUB
R227
@10_0402
1 2
C252
@10PF_0402
of
16 46星@, 30, 2002
J
R219
@10K_0402
ICH_WAKE_UP#
2B
Page 17
A
B
C
D
E
F
G
H
I
J
1 2
1 2
1 2
1 2
USBP0+
USBP0-
USBP1+
USBP1-
USBP2+
USBP2-
USBP3+
USBP3-
OVCUR_R#0
12
OVCUR_R#1
12
PIDERST#<19>
ICH_IDE_SRST#<19>
VCC1.8SUS : Width=40 mils
+1.8_ICHLAN : Width=20 mils
+3V
OVCUR#2
12
R630 100K_0402
R169 100K_0402
R157 100K_0402
R160 100K_0402
R623 USB20@100K_0402
R624 USB20@100K_0402
R207 0_0402
1 2
EC_FLASH#<31>
OVCUR#4
12
OVCUR#5
12
OVCUR#3
12
OVCUR_R#0
12
OVCUR_R#1
12
USBP0+
USBP1+
USBP2+
USBP3+
USBP4+
USBP5+
USBP0USBP1USBP2USBP3USBP4USBP5-
OVCUR_R#0
OVCUR_R#1
OVCUR#2<32>
BT_DET#<18>
MDC_DET#<18,32>
FIR_DET#<18>
MS_DET#<18>
SD_DET#<18>
OVCUR#2
OVCUR#3
OVCUR#4
OVCUR#5
ICH_IDE_SRST#
ICH_ACIN
Cancel 5/16 JOHNNY
12
*
R394
18.2_1%
+3VALW
ICH_SPKR<21>
+1.8VS
1 2
R400
0_0805
ICH_ SPKR
VCCPSUS
+5VS +3VS
R163
1K_0402
+1.8VAL W
1 2
0_0805
U52B
D19
USB_PP0
A19
USB_PP1
E17
USB_PP2
B17
USB_PP3
D15
USB_PP4
A15
USB_PP5
D18
USB_PN#0
A18
USB_PN#1
E16
USB_PN#2
B16
USB_PN#3
D14
USB_PN#4
A14
USB_PN#5
E12
USB_OC#0
D12
USB_OC#1
C12
USB_OC#2
B12
USB_OC#3
A12
USB_OC#4
A11
USB_OC#5
H20
USB_LEDA#0/GPIO32
G22
USB_LEDA#1/GPIO33
F21
USB_LEDA#2/GPIO34
G19
USB_LEDA#3/GPIO35
E22
USB_LEDA#4/GPIO36
E21
USB_LEDA#5/GPIO37
H21
USB_LEDG#0/GPIO38
G23
USB_LEDG#1/GPIO39
F23
USB_LEDG#2/GPIO40
G21
USB_LEDG#3/GPIO41
D23
USB_LEDG#4/GPIO42
E23
USB_LEDG#5/GPIO43
B21
USB_RBIAS
H23
SPKR
U19
VCCA
F17
VCCPSUS3/VCCPUSB0
F18
VCCPSUS4/VCCPUSB1
K14
VCCPSUS5/VCCPUSB2
E10
VCCPSUS0
V8
VCCPSUS1
V9
VCCPSUS2
12
VCC1.8SUS
R217
21
D11
1SS355
12
C229
.1UF_0402
L25
1 2
BLM21A601SPT
VCC1.8SUS
E13
F14
K12
VCC_SUS0
VCC_SUS1
VCC_SUS2
USB
Interface
Misc
Power
P10
Width=15 mils
VCC5REF
12
C208
1UF
+V1.8_ICHLAN
F15
F16
V7
VCC_SUS3
VCC_SUS4V6VCC_SUS5
VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7
VCC_AUX0/VCCLAN1_8F7VCC_AUX1/VCCLAN1_8F8VCC_AUX2/VCCLAN1_8
+VCC_RTC
K10
AB6
+5VALW
12
R188
0_0402
12
C185
.1UF_0402
+CPU_CORE
12
R186
0_0805
VCC PAU
F10
VCCPAUX0/VCCLAN3_3F9VCCPAUX1/VCCLAN3_3
P14
U18
V22
VCCPCPU0
VCCPCPU1
VCCPCPU2
+1.8VALW
12
VCC1.8SUS
C23
B23
VCCUSBBG/VCC_SUS8
VCCUSBPLL/VCC_SUS9
R181
0_0805
Power
N/C0E7N/C1
A21
T21
C2
N/C2D6N/C3T1N/C4
+3VALW
VCCREFSUS
C13
W5
W8
VCC_RTC
VCC5REF1E6VCC5REF2
VCC5REFSUS1
VCC5REFSUS2
12
C565
.1UF_0402
A22
VSS102
VSS103
VCCPPCI0F6VCCPPCI1G6VCCPPCI2H6VCCPPCI3J6VCCPPCI4
G18
M10
U6
VCCPPCI5R6VCCPPCI6T6VCCPPCI7
ICH3-M (2/2)
VSS
R437
1 2
1K_0402
Closely Pin AB6
+3VS
H18
P12
V15
V16
VCCP0
VCCP1
VCCPIDE0
VCCPIDE1
VCCPIDE2
+RTCVCC+VCC_RTC
+1.8VS
E11
K18
P18
V10
VCCCORE0
VCCCORE1K6VCCCORE2
IDE
Interface
VCCCORE3P6VCCCORE4
V14
IDE_PDCS1#
IDE_PDCS3#
VCCCORE5
VCCCORE6
IDE_SDCS1#
IDE_SDCS3#
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY
AC15
AB15
AC21
AC22
AA14
AC14
AA15
AC20
AA19
AB20
W12
AB11
AA10
AC10
W11
Y9
AB9
AA9
AC9
Y10
W9
Y11
AB10
AC11
AA11
AC12
Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18
Y13
Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
PDCS1# <19>
PDCS3# <19>
SDCS1# <19>
SDCS3# <19>
PDA0 <19>
PDA1 <19>
PDA2 <19>
SDA0 <19>
SDA1 <19>
SDA2 <19>
PDD[0..15] <19>
SDD[0..15] <19>
PD DACK# <19>
SD DACK# <19>
PDDRE Q <19>
SDDRE Q <19>
PDIOR# <19>
SDIOR# <19>
PD IOW# <19>
SD IOW# <19>
PD IO RDY <19>
SD IO RDY <19>
V17
V18
J18
M14
R18
T18
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3
VCCPIDE3
VCCPIDE4
USBP0+<32>
1 1
2 2
USBP0-<32>
C171 5PF_0402
USBP1+<32>
USBP1-<32>
C172 5PF_0402
USBP2+<32>
USBP2-<32>
C173 5PF_0402
USBP3+<32,34>
USBP3-<32,34>
C170 5PF_0402
3 3
Layout note The Cap close to
4 4
ICH3-M(< 1 inch)
OVCUR#0<26>
OVCUR#1<26>
R625 USB11@100K_0402
R626 USB11@100K_0402
5 5
6 6
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41G3VSS42
VSS43
VSS44
VSS45J5VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52L3VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65N5VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77R3VSS78R5VSS79
VSS80
VSS81T4VSS82
VSS83
VSS84V3VSS85
VSS86
VSS87W6VSS88W7VSS89
VSS90
VSS91
VSS92
VSS93Y8VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
ICH3-M
7 7
8 8
100K_0402
ACIN<30,37,40>
D38 RB751V
A
Note:
R376=22.6_1% for B0(QB63 part)
R376=18.2_1% for B0(QB62 & SL5LF part)
+3VS
12
R180
ICH_ACIN
21
B
R414
1 2
+3VS
@1K_0402
Disable Timeout feature
C
D
E14
E15
E18
E19
ICH_ SPKR
F22
E20
K11
H19
G20
AA22
L10
L11
L12
L13
L14
L21
K13
K20
K21
K22
K23
E
L23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
N10
M11
M12
M13
M20
M22
P11
P13
N11
N12
P20
N13
N14
N21
N23
F
T20
P22
T22
R21
V20
R23
AC23
AA3
W10
W14
W18
W22
G
VSS101
AA8
AB8
AC1
AC8
AA12
AA16
AA20
Comp al E l e c t ro n i c s , Inc.
Title
SCHEMATIC, M/ B LA-1381
Size Document Number Re v
401212
Custom
薑 十二月
H
Date: Sheet
I
17 46星@, 30, 2002
2B
of
J
Page 18
A
B
C
D
E
F
G
H
I
J
1 1
+3VS +3VS
RP11
FRAME#<16,23,25,26,34>
IRDY#<16,23,25,26,34> SERR# <16,23,25,34>
TRDY#<16,23,25,26,34>
2 2
STOP#<16,23,25,26,34>
PCI_REQA#<16>
PCI_REQB#<16>
REQ#0<16,25>
REQ#1<16,34>
3 3
GNT#1<16,34>
GNT#2<16,23>
PIRQD#<16,34>
IRQ14<16,19>
4 4
GNT#0<16,25>
GNT#3<16,26>
GNT#4<16,34>
PM_CLKRUN#<16,23,25,28,30,34>
SMB_DATA<14,16>
SMB_CLK<14,16>
1
2
3
4
5
10P8R_8.2K
+3VS
RP10
1
2
3
4
5
10P8R_8.2K
+3VS +3VS
RP9
1
2
3
4
5
10P8R_8.2K
R168 8.2K_0402
1 2
R152 8.2K_0402
1 2
R151 8.2K_0402
1 2
R150 10K_0402
1 2
R155 4.7K_0402
1 2
R156 4.7K_0402
1 2
5 5
R187 8.2K_0402
ICH_SWI#<16,30>
SMB_ALERT#<16>
SMLINK0<16>
6 6
SMLINK1<16>
SM_INTRUDER#<16>
1 2
R397 10K_0402
1 2
R395 4.7K_0402
1 2
R398 4.7K_0402
1 2
R218 100K_0402
1 2
10
9
8
7
6
10
9
8
7
6
10
9
8
7
6
+3VS
+3VS
+3VALW
+3VALW
+3VALW
+RTCVCC
DEVSEL# <16,23,25,26,34>
PERR# <16,23,25,34>
PLOCK# <16,23>
REQ#2 <16,23>
REQ#3 <16,26>
REQ#4 <16,34>
SIRQ <16,23,27,28,30>
IRQ15 <16,19>
PIRQA# <15,16,23,25,26>
PIRQB# <16,26>
PIRQC # <16,26,34>
+CPU_CORE
12
+
+3VS
12
+
+3VS
12
VCCPSUS
12
+
22UF_10V_1206
+1.8VS
12
+
VCC1.8SUS
12
12
C235
C217
.1UF_0402
1UF
C529
22UF_10V_1206
C242
47PF_0402
C218
C513
100UF_D2_6.3V
C228
10UF_6.3V_P
12
+
C523
22UF_10V_1206
12
C203
.1UF_0402
12
C247
.1UF_0402
12
C210
.1UF_0402
12
C248
.1UF_0402
12
C244
.1UF_0402
12
12
C243
.1UF_0402
12
C245
.1UF_0402
12
C214
33PF_0402
12
C246
.1UF_0402
C204
.1UF_0402
12
C238
47PF_0402
12
C211
.1UF_0402
12
C221
.1UF_0402
12
C196
.1UF_0402
12
C199
.1UF_0402
12
C239
.1UF_0402
12
C194
.1UF_0402
12
C226
.1UF_0402
12
C236
47PF_0402
12
C216
.1UF_0402
12
12
C232
33PF_0402
C250
.1UF_0402
12
12
C241
.1UF_0402
C240
.1UF_0402
12
C249
.1UF_0402
12
C200
47PF_0402
12
C205
.1UF_0402
12
12
C212
.1UF_0402
SD_DET#<17>
C251
47PF_0402
12
C213
.1UF_0402
SD_DET#
SD enable: Mount R_SD
SD disable: Delete R_SD.
MS_DET#<17>
MS_DET#
MS enable: Mount R_MS
MS disable: Delete R_MS.
12
12
1 2
R621 100K_0402
R622 S D@10K_0402
1 2
C237
.1UF_0402
C227
.1UF_0402
+3VS
R_SD
1 2
R611 100K_0402
R612 MS@10K_0402
1 2
+3VS
R_MS
R170 100_0402
PAR<16,23,25,26,34>
1 2
7 7
BT_DET#<17>
BT_DET# MDC_DET# FIR_DET#
1 2
R531 100K_0402
R533 L AN@10K_0402
1 2
+3VS +3VS +3VS
MDC_DET#<17,32> FIR_DET#<17>
R_BT
Blue Tooth enable: Mount R_BT
Blue Tooth disable: Delete R_BT.
8 8
A
B
MDC enable: Mount R_MDC
MDC disable: Delete R_MDC.
C
1 2
R532 100K_0402
R534 @10K_0402
1 2
R_MDC
D
1 2
R527 100K_0402
R529 FI R @1 0K_0402
1 2
R_FIR
FIR enable: Mount R_FIR
FIR disable: Delete R_FIR.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
G
H
Comp al E l e c t ro n i c s , Inc.
Title
SCHEMATIC, M/ B LA-1381
Size Document Number Re v
401212
Custom
薑 十二月
Date: Sheet
I
of
18 46星@, 30, 2002
J
2B
Page 19
A
B
C
D
E
F
G
H
I
J
PDD[0..15]<17>
1 1
PCIRST#<5,8,15,16,23,25,26,28,34>
PIDERST#<17>
Place closely to
JP31
2 2
PDIOW# PDIOR#
12
R517
10_0402
12
C675
15PF_0402
3 3
12
R518
10_0402
12
C676
15PF_0402
R304 4.7K_0402
+3VS
PDIORDY<17>
PDDACK#<17>
IRQ14<16,18>
1 2
R305 0_0402
1 2
1 2
R306 0_0402
1 2
+5VS
R301 100K_0402
4 4
SDD[0..15]<17>
5 5
INT_CD_L<21>
CD_AGND<21>
ICH_IDE_SRST#<17>
6 6
R260
1 2
+3VS
SDIORDY<17>
IRQ15<16,18>
7 7
1 2
R259 0_0402
1 2
+5VS
R257 100K_0402
R446 470_0402
PDD[0..15]
C369
12
.1UF_0402
PCIRST#
1
2
12
R297 @10K_0402
SDD[0..15]
C282
.1UF_0402
PCIRST#
1 2
C587 @47PF_0402
1 2
C588 @47PF_0402
12
R263 @10K_0402
4.7K_0402
12
+3VS
12
1
2
DISKCHG#<28>
5
3
PDDREQ<17>
PDIOW#<17>
PDIOR#<17>
PDCS1#<17>
+3VS
+5VSCD
SDIOW#<17>
SDCS1#<17>
RDATA#<28>
TRACK0#<28>
WDATA#<28>
HDD Connector
U28
PIDE_RST#
4
7SH08FU
Correct HDD pin define ,pls update layout
PIDE_RST#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDDREQ
PDIOW#
PDIOR#
PDIORDY
RPD DACK#
+5VS
RIRQ14
PHDD_LED#
PDA1<17>
PDA0<17>
JP31
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
HDD_CONN_44P
CD-ROM Connector
U22
5
SIDERST#
4
3
7SH08FU
JP29
CD_AGND
SIDERST#
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
SDIORDY
SDA1<17>
SDA0<17>
STEP#<28>
MTR0#<28>
DRV0#<15,28>
RIRQ15
SHDD_LED#
SEC_CSEL
RDATA#
WP#
WP#<28>
TRACK0#
WDATA#
STEP#
MTR0#
DISKCHG#
DRV0#
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
HEADER 2X30
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PCSEL
CD_AGND
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDDREQ
RSD DACK#
EXTID0
EXTID1
EXTID2
HDSEL#
R298
1 2
470_0402
PDA2 <17>
PDCS3# <17>
+5VS
@.1UF_0402
PHDD_LED#
SHDD_LED#
1 2
C589 @47PF_0402
WGATE#
FDDIR#
INDEX#
+5VSCD
C717
12
1
2
SDDRE Q <17>
SDIOR# <17>
SDA2 <17>
SDCS3# <17>
EXTID0 <31>
EXTID1 <31>
EXTID2 <31>
HDSEL# <28>
WGATE# <28>
FDDIR # <28>
3MODE# <28>
INDEX# <28>
+5VS
5
3
IN T_CD_R <21>
+5VS
Placea caps. near HDD CONN.
12
C370
1000PF_0402
PDDREQ
R627 0_0402
1 2
U71
4
@7SH08FU
1 2
R258 0_0402
12
C363
10UF_16V_1206
1 2
R302 @5.6K_0402
1 2
C374 33PF_0402
ACT_LED#
SD DACK# <17>
12
C373
10UF_16V_1206
ACT_LED# <29>
12
C371
1UF_25V_0805
12
C375
.1UF_0402
+5VS
R444
10K_0402
13
SIDEPWR<16>
2
Extend Module ID list
FDD
CD-ROM
LS-120
2'nd HDD
NONE
0
00
00
00
0
SDDREQ
1
11
1 2
R262 @5.6K_0402
SI3456DV: N CHANNEL
VGS: 4.5V, R D S: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V
+5VS
+12VALW
R436
100K_0402
2
Q54
2N7002
EXTID0EXTID1EXTID2DEVICE
1
111
1 2
C585 33PF_0402
6
5
2
1
47K
Q30
SI3456DV
12
47K
3
1
3
+5VSCD
WITH: 100 mils
4
12
+
C581
4.7UF_10V_0805
<1st Part Field>
Q55
DTC144EKA
12
Placea caps. nea r CDROM
CONN.
+5VSCD
12
C285
1000PF_0402
+5VSCD
12
C281
1000PF_0402
12
R443
1K_0402
13
Q56
2N7002
C568
.01UF_0402
W=100 mils
12
C283
.1UF_0402
12
C284
.1UF_0402
SIDE_PWR#
2
12
C586
1UF_25V_0805
12
C578
1UF_25V_0805
12
C580
10UF_16V_1206
12
C579
10UF_16V_1206
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Comp al E l e c t ro n i c s , Inc.
Title
SCHEMATIC, M/ B LA-1381
Size Document Number Re v
401212
Custom
薑 十二月
Date: Sheet
I
of
19 46星@, 30, 2002
J
2B
Page 20
10
9
8
7
6
5
4
3
2
1
H H
+
12
LAN@4.7UF_10V_0805
C473
G G
F F
E E
RSMRST#<16,33>
= LAN_RST#
2
G
+3VALW
12
13
D
S
12
C508
LAN@4.7UF_10V_0805
LAN_JCLK<16>
LAN_RSTSYNC<16>
LAN_TXD2<16>
LAN_TXD1<16>
LAN_TXD0<16>
LAN_RXD2<16>
LAN_RXD1<16>
LAN_RXD0<16>
1 2
R372 @0_0402
R370
LAN@100K_0402
LAN_TCK
LAN_TI
LAN_EX
LAN_TESTEN
Q48
LAN@2N7002
+
LAN@.1UF_0402
12
C511
12
@10PF_0402
12
C505
C471
LAN@.1UF_0402
R371
12
@33_0402
LAN_JCLK
LAN_RSTSYNC
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0
TP_LAN_ADV
LAN_TCK
LAN_TI
LAN_EX
TP_LAN_TOUT
LAN_TESTEN
D D
LAN_ACTLED# ORE_LED_N
C C
LAN_LILED#
B B
LED1_GRNN
LED2_YELN
+3VALW
LAN@.1UF_0402
12
12
C468
C469
LAN@.1UF_0402
39
JCLK
42
JRSTSYNC
45
JTXD[2]
44
JTXD[1]
43
JTXD[0]
37
JRXD[2]
35
JRXD[1]
34
JRXD[0]
41
ADV10
30
ISOL_TCK
28
ISOL_TI
29
ISOL_TEX
26
TOUT
21
TESTEN
EEP_CS<16>
EEP_SHCLK<16>
EEP_DOUT<16>
EEP_DIN<16>
R60 LAN@0_0402
R16 LAN@0_0402
R24 @100K_0402
R59 @100K_0402
1 2
L54 LAN@4.7UH
7
2
25
VCC1VCC
VCCP36VCCP40VCCA
VCCT9VCCT12VCCT14VCCT
VCCA2
17
Kinnereth
VSS8VSS13VSS18VSS24VSS48VSSP33VSSP38VSSA3VSSA26VSSR20VSSR
EEPROM for ICH3-m LAN
(Atmel AT93C46-10PC-2.7)
U40
1
CS
VCC
2
SK
3
DI
ORG
4
DO
GND
LAN@AT93C46-10SC-2.7
GRN_LED_N
+3VALW
VCCR_LAN
LAN@.1UF_0402
23
VCCR19VCCR
TDP
TDN
RDP
RDN
RBIAS100
RBIAS10
ACTLED#
SPDLED#
LILED#
U46LAN@82562ET
22
8
7
DC
6
R345 LAN@10K_0402
5
2
2
12
12
+
C466
C470
LAN@4.7UF_10V_0805
LAN_TX+
10
LAN_TX-
11
LAN_RX+
15
LAN_RX-
16
R355 LAN@619_1%_0402
5
1 2
R356 LAN@549_1%_0402
4
1 2
LAN_ACTLED#
32
31
LAN_LILED#
27
LAN_X2
47
X2
LAN_X1
46
X1
+3VALW
1 2
ORE_LED_1
C
10K
B
47K
Q8
E
LAN@DTA114YKA
3 1
+3V
GRN_LED_1
C
10K
B
47K
E
Q4
LAN@DTA114YKA
3 1
+3V
LAN_TX+
LAN_RX+
X3
LAN@25MHZ
12
C501
LAN@22PF_0402
1 2
R36 LAN@510_0603
12
C60
LAN@47PF_0402
1 2
R6 LAN@510_0603
12
C36
LAN@47PF_0402
1 2
R354 LAN@100_1%_0402
1 2
R357 LAN@100_1%_0402
12
C502
LAN@22PF_0402
ORE_LED_2
LAN_RJ45R-
LAN_RJ45R+
LAN_RJ45TLAN_RJ45T+
GRN_LED_2
LAN_TX-
LAN_RX-
12
R32
LAN@75_0402
12
R31
LAN@75_0402
LAN_GND
Layout note :
Cassis LAN_GND
should cover part
of U15.
LAN_RX+
LAN_RX-
LAN_TX+
LAN_TX-
Layout Note:
H0022 Pls closely to
RJ45 Conn.
JP18
12
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
LAN@AMP R J45 with LED
U39
1
RD+
2
RD-
3
CT
6
CT
7
TD+
TD-8TX-
LAN@Pulse-H0022
16
SHLD4
15
SHLD3
14
SHLD2
13
SHLD1
RX+
RX-
CT
CT
TX+
LAN@75_1%
16
15
14
11
10
9
R341
12
LAN_RJ45R+
LAN_RJ45R-
LAN_RJ45T+
LAN_RJ45T-
12
R340
LAN@75_1%
LAN_GND
C436
LAN@1000PF_1206_2KV
1 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Comp al E l e c t ro n i c s , Inc.
Title
SCHEMATIC, M/B LA-13 81
Size Document Number Re v
401212
Custom
薑 十二月
Date: Sheet
2
of
20 46星@, 30, 2002
1
2B
Page 21
A
1 1
BEEP#<30>
13
U21D
12 11
74LVC125
2 2
New update
5/16 JOHNNY
+3VALW
B
12
R449
100K_0402
R318
1 2
10K_0402
.22UF_0603
C605
12
PCM_SPK#<23>
13 12
7 14
C
+3VALW
U12F
74LVC14
1 2
1UF_0603
C613
1 2
1UF_0603
C609
1 2
.1UF_0402
C387
R452
1 2
560_0402
R464
1 2
560_0402
D
+5VS
12
R319
@100K_0402
2
VDDA
12
12
3 1
E
R463
10K_0402
R462
10K_0402
R488 0_0402
Q60
2SC2411EK
12
C607
10UF_16V_1206
MONO_IN_R MONO_IN
12
12
R489
2.4K_0402
F
Close to AC97 CODEC
C615
1 2
1UF_10_0603
+5VS
+5VALW
G
New add
5/16 JOHNNY
1 2
@0_0805
1 2
0_0805
C592
4.7UF_10V_0805
SUSP#<30,36,42>
L91
L92
W=40Mil
12
H
reserve for AC97 coedc using only
U55
5VDDA
12
C594
.1UF_0402
4
VIN
2
DELAY
ERROR7CNOISE
8
ON/OFF#
SI9182DH-AD
VOUT
SENSE
GND
5
6
1
3
12
C593
.01UF_0402
I
R309
1 2
12
28.7K_1%
10K_1%
R308
VDDA
12
4.7UF_10V_0805
C598
J
12
C597
.1UF_0402
C388
1 2
1UF_0603
CDL
CDR
12
12
12
12
ICH_SPKR<17>
6.8K_0402
6.8K_0402
3 3
INT_CD_L<19>
INT_CD_R<19>
R493
R494 6.8K_0402
R495
R496 6.8K_0402
4 4
R492
CLK_14M_AUD<14>
1 2
@0_0402
5 5
C644 15PF_0402
AC97_RST#<16,32,34>
IAC_BITCLK<16,32,34>
IAC_SYNC<16,32,34>
IAC_SDATAO<16,32,34>
SDATA_IN0<16>
6 6
MD_SPK<32,34>
MD_MON<34>
R470 20K_0402
R469 33K_0402
7 7
CD_AGND<19>
R465
MD_SPKR
12
12
12
R466 10K_0402
12
R467 1K_0402
6.8K_0402
12
R468
12
6.8K_0402
MD_MONR
CD_AGNDR
MICIN<22>
MONO_IN
CDL
CDR
1 2
C624
1 2
1 2
C626 1UF_10V
1 2
C625 1UF_10V
1UF_10V
C110
.1UF_0402
.1UF_0402
1 2
1 2
C617 .1UF_0402
8 8
A
B
C
1 2
C648
22PF_0402
12
C620
.1UF_0402
C111
R454
560_0402
@10K_0402
C616
.1UF_0402
1 2
CD_AGNDRC
12
R320
1M_0402
R475
Y2
24.576MHz
1 2
R473 22_0402
1 2
R472 22_0402
MD_SPKRC
MD_MONRC
LINEL_IN_C
C622
.1UF_0402
1 2
1 2
D
2 1
C649
22PF_0402
LINER_IN_C
C627
.1UF_0402
D31
1SS355
12
VDDC
12
C634
.1UF_0402
AVDD_AC97
38
9
2
XTL-IN
3
XTL-OUT
11
RESET#
6
BIT-CLK
10
SYNC
5
SDATA-OUT
8
SDATA-IN
12
PC-BEEP
13
PHONE
14
AUX-L
15
AUX-R
16
VIDEO-L
17
VIDEO-R
18
CD-L
20
CD-R
21
MIC1
22
MIC2
23
LINE-L
24
LINE-R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
VDD1VDD
VSS4VSS7AVSS26AVSS
CD-GND
42
19
AVDD25AVDD
F
LINE-OUTL
LINE-OUTR
MONO-OUT
HP-OUT-R
12
C629
.1UF_0402
VREF
VREFOUT
AFILT1
AFILT2
VRAD
VRDA
CAP1
JD/SDIN1
TEST1
ID0#
ID1#
EAPD
SPDIFO
HP-OUT-L
ALC202
R471 0_0805
12
10UF_10V_1206
U62
35
36
37
27
28
29
30
31
32
33
34
NC
43
44
45
46
47
48
39
40
NC
41
1 2
C630
HB-1M2012-121JT
12
C614
10UF_10V_1206
1000PF_0402
LINEL
LINER
MDMIC
C642
12
R480
@0_0402
L62
C647
AUD_REF
+AUD_VREF
C637
1000PF_0402
C640
@1000PF_0402
G
+3VS
12
1 2
1000PF_0402
12
R476
@0_0402
VDDA
C645
1000PF_0402
1 2
C651 4.7UF_10V_0805
1 2
C628
+
1UF_10V
C643
1UF_10V
C633
.1UF_0402
ID1# ID0# FREQ. SEL
NC
NC
0
NC
C646 4.7UF_10V_0805
12
C631
.1UF_0402
C641
1UF_10V
+AUD_VREF
12
H
24.576MHZ
NC
14.318MHZ
0
48MHZ
1 2
C657 1UF_25V_0805
C653 1000PF_0402
C636
1UF_10V
12
C635
@10UF_10V_1206
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
1 2
1 2
I
?30, 2002
L63
1 2
0_0805
L66
1 2
0_0805
L60
1 2
0_0805
L56
1 2
0_0805
L65
1 2
0_0805
LEFT <22,35>
RIGHT <22,35>
MD_MIC <32,34>
GNDA
AGNDDGND
of
21 46,
J
2B
Page 22
A
B
C
D
E
F
G
H
I
J
New update
8
VDD13VDD2
1
13
5/24 JOHNNY
L33
1 2
BLM21A05_0805
W=40mils
U59
18
VDD4
VDD3
ROUT+
ROUT-
LOUT+
LOUT-
R_UP/DOWN#
L_UP/DOWN#
GAINSEL
SVR
GND420GND311GND210GND1
TDA8552TS
VDDA
C389
.1UF_0402
+
R461
1K_0402
30dB/20dB#
C604
2.2UF_16V_0805
C386
100UF_10V_D2
2N7002
Q37
+
13
D
S
Q35
2N7002
Q59
2N7002
C382
10UF_16V_1206
16V
1 2
C384
1000PF_0402
SPK_R+ SPKF_R+
12
19
SPK_L+
2
9
6
1 2
7
14
16
C603
.1UF_0402
G
S
S
G
R317
100K_0402
LINE_OUT_PLUG
2
G
2
2
EC_MUTEO
13
D
D
13
+5V_AMP
SPKF_L+
S
G
2
D
1 3
2
G
Q57
1 3
D
Q58 2N7002
D
1 3
G
2
Q34
2N7002
R456
1 2
100K_0402
2N7002
S
S
+5VALW
135
+12VALW
INTSPK_R+
INTSPK_R-
INTSPK_L+
INTSPK_L-
U61
24
74AHCT1G125GW
INTSPK_R+
INTSPK_L+
DIS_ADJVOL <30>
ADJVOL_UP/DW# <31>
GAIN_SEL# <16>
C618 150UF_63V_D2
+
LINEC_OUT_R
1 2
+
LINEC_OUT_L
1 2
C638 150UF_63V_D2
1 2
L58 BLM11A121S
1 2
L59 BLM11A121S
INTSPK_R+
INTSPK_R-
INTSPK_L+
INTSPK_L-
LINE_OUT_PLUG
LINECL_OUT_R
LINECL_OUT_L
47PF_0402
1 1
+5V_AMP
2 2
RIGHT<21,35>
LEFT<21,35>
R455
RIGHT
LEFT LEFT_R
1 2
0_0402
R313
1 2
0_0402
RIGHT_R
R312
@100K_0402
17
RLINEIN
15
12
12
LLINEIN
R453
@100K_0402
3 3
LINE_OUT_PLUG
R458
EC_MUTEO
1 2
100K_0402
R459
1 2
100K_0402
+5VALW
EC_MUTEO<31,33,35>
4 4
12
R460
100K_0402
4
HPS
5
MODE
5 5
Layout note:
Trace width=15 mils.
1.SPK_R+,SPK_L+,SPKF_R+,SPKF_L+
2.INTSPK_R+/-,INTSPK_L+/-
3.LINEOUT_L,LINEOUT_R
15 mils trace
12
C42
@220PF_0402
@220PF_0402
12
C45
12
C44
@220PF_0402
12
HEADPHONE OUT
JP9
5
4
3
6
2
C639
12
12
C632
1
LINE OUT
JP4
1
1
2
2
R-SPK CONN.
JP1
1
1
2
2
L-SPK CONN
C43
@220PF_0402
7
8
47PF_0402
VDDA
6 6
VDDA
84
3
+AUD_VREF
12
12
C719
@1UF
7 7
C723
MICIN
MICIN<21>
1 2
1UF
AFOPMIC_IN
8 8
A
+
2
-
C720
@.1UF_0402
VDDA
84
+
7
-
1 2
R609 @18K_1%
1 2
C725 @15PF_NPO_0402
1 2
0_0402
B
U72A
@TDA1308
1
U72B
@TDA1308
5
6
R610
+AUD_VREF
R605
@100_0402
1 2
@4.7UF_10V_0805
BFOPMIC_IN
C721
R608
1 2
@10K_1%
C
L84
1 2
@0_0805
C722
@.1UF_0402
MIC_PWR
C724
1 2
@.22UF
12
12
BFOPRMIC_IN MIC_IN
INT_MIC<15>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
F
R615
9.09K_1%_0603
1 2
VDDA
1 2
R616
@0_0603
100K_1%_0402
INT_MIC INT_MICL
MIC_IN EXT_MICL
12
R617
L64 BLM11A121S
1 2
1 2
L61 BLM11A121S
G
2SC2411K
12
C734
1UF_10V_0603
H
Q75
2
MIC_PWR
3 1
EXT. MIC
12
12
2.2K_0402
12
C654
47PF_0402
Title
Size Docu ment Number Re v
Custom
Date: Sheet
R619
R618
12
@2.2K_0402
C664
47PF_0402
JP10
5
4
3
6
2
1
EXT. MIC
Compal Electronics, Inc.
SCHEM AT IC , M/ B LA- 1381
401212
星期一 十二
?30, 2002
I
22 46,
7
8
2B
of
J
Page 23
A
8 8
7 7
6 6
5 5
4 4
1 2
+3V
R174 22K_0402
3 3
PCM_SUSP#<30>
+3VALW
R261 10K_0402
CLK_PCI_PCM
2 2
+3V
R392 10K_0402
1 2
1 2
12
R373
@10_0402
12
C510
@15PF_0402
PCM_RI#
D39
RB751V
B
VPPD0<24>
VPPD1<24>
VCCD0#<24>
VCCD1#<24>
New update
5/16 JOHNNY
1 2
21
R568 6912@0_0402
C
AD[0..31]<16,25,26,34>
PCM_RI#<29>
SIRQ<16,18,27,28,30>
PLOCK#<16,18>
AD[0..3 1 ]
C/BE#0<16,25,26,34>
C/BE#1<16,25,26,34>
C/BE#2<16,25,26,34>
C/BE#3<16,25,26,34>
PCIRST#<5,8,15,16,19,25,26,28,34>
FRAME#<16,18,25,26,34>
IRDY#<16,18,25,26,34>
TRDY#<16,18,25,26,34>
DEVSEL#<16,18,25,26,34>
STOP#<16,18,25,26,34>
PERR#<16,18,25,34>
SERR#<16,18,25,34>
PAR<16,18,25,26,34>
REQ#2<16,18>
GNT#2<16,18>
CLK_PCI_PCM<14>
PCM_PME#<31>
PIRQA#<15,16,18,25,26>
PCM_RI#
1 2
R571 6912@0_0402
PM_CLKRUN#<16,18,25,28,30,34>
G_RST#<15,24,25,30>
AD20
D
4.7UF_10V_0805
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCIRST#
CLK_PCI_PCM
1 2
R391 0_0402
1 2
R367 100_0402
1 2
R5706912@0_0402
C472
12
U47
57
AD0
56
AD1
55
AD2
54
AD3
53
AD4
52
AD5
51
AD6
49
AD7
47
AD8
46
AD9
45
AD10
43
AD11
41
AD12
40
AD13
39
AD14
38
AD15
26
AD16
25
AD17
24
AD18
23
AD19
19
AD20
17
AD21
16
AD22
15
AD23
11
AD24
10
AD25
9
AD26
8
AD27
7
AD28
5
AD29
4
AD30
3
AD31
48
C/BE0#
37
C/BE1#
27
C/BE2#
12
C/BE3#
20
PCIRST#
28
PCIFRAME#
29
PCIIRDY#
31
PCITRDY#
32
PCIDEVSEL#
33
PCISTOP#
34
PCIPERR#
35
PCISERR#
36
PCIPAR
1
PCIREQ#
2
PCIGNT#
21
PCIPCLK
59
RI_OUT#/PME#
70
SUSPEND#
13
IDSEL
60
MF0
61
MF1
64
MF2
65
MF3
67
MF4
68
MF5
69
MF6
66
G_RST#
12
C482
.1UF_0402
74
VCCD0#73VCCD1#
E
3V_CB
R566
1 2
6912@0_0402
72
18
44
VCCP
VCCP
VPPD071VPPD1
PCI1410
GND
GND
GND
GND
GND
GND
6
22
42
58
78
94
90
126
VCCCB
GND
114
130
12
C481
.1UF_0402
3V_CB
VCCCB
GND
S1_VCC
86
102
122
138
VCC
VCC
VCC
RSVD/D14
RSVD/A18
84
100
143
F
12
C503
.1UF_0402
R_OZ
1 2
R393 0_1206
R_TI/ENE
1 2
R396 @0_1206
+3V
.1UF_0402
63
30
50
14
VCC
VCC
VCCI
VCCP
VCCP
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#
CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCCLK/A16
CSTSCHNG/BVD1
CCLKRUN#/WP
CBLOCK#/A19
CINT#/READY
SPKROUT
CAUDIO#/BVD2
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#
RSVD/D2
C522
1 2
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76
125
112
99
88
119
111
110
109
107
105
104
133
101
123
106
108
135
136
103
132
62
134
137
75
117
131
G
3V_CB
+3VS
+3V
3V_CB
C504
.1UF_0402
12
C499
.1UF_0402
12
C517
.1UF_0402
12
Stuff R_OZ for OZ6912.
Stuff R_TI/ENE for TI/ENE CB1410.
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
S1_REG#
S1_A12
S1_A8
S1_CE1#
S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
1 2
R362 33_0402
S1_BVD1
S1_WP
S1_A19
S1_RDY#
PCM_SPK#
S1_BVD2
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14
S1_IOWR# <24>
S1_IORD# <24>
S1_OE# <24>
S1_CE2# <24>
S1_REG# <24>
S1_CE1# <24>
S1_RST <24>
S1_WAIT# <24>
S1_INPACK# <24>
S1_WE# <24>
S1_BVD1 <24>
S1_WP <24>
S1_RDY# <24>
PCM_SPK# <21>
S1_BVD2 <24>
S1_CD2# <24>
S1_CD1# <24>
S1_VS2 <24>
S1_VS1 <24>
S1_A[0..25]
S1_D[0..15]
S1_A23
1 2
R412 22K_0402
S1_WP
1 2
R410 @22K_0402
S1_OE#
Stuff this resistor
for ENE CB1410 only.
S1_A16
H
C524
.1UF_0402
R206
@47K_0402
12
C525
.1UF_0402
S1_A[0..25] <24>
S1_D[0..15] <24>
12
S1_VCC
S1_VCC
S1_VCC
12
C509
.1UF_0402
I
12
C496
.1UF_0402
J
1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCH EMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
23 46,
J
2B
Page 24
A
B
C
D
E
F
G
H
I
J
1 1
PCMCIA Power Controller
+12VALW
U51
+5VALW
+3VALW
6912@TPS2211
9
12V
5
5V
6
5V
3
3.3V
4
3.3V
VCC
VCC
VCC
VPP
VCCD0
VCCD1
VPPD0
VPPD1
OC
GND
SHDN
7
16
G_RST#
C547
.1UF_0402
2 2
C539
.1UF_0402
3 3
C535
.1UF_0402
4 4
5 5
6 6
+3VALW +5VALW
12
C528
10UF_10V_1206
12
S1_VPP
C545
10UF_10V_1206
S1_VCC
13
12
11
10
1
2
15
14
8
G_RST# <15,23,25,30>
12
C153
.01UF_0402
12
C536
4.7UF_10V_0805
S1_VPP
+
C541
.1UF_0402
VCCD0# <23>
VCCD1# <23>
VPPD0 <23>
VPPD1 <23>
C494
4.7UF_10V_0805
S1_VCC
L24
1 2
FBM-11-160808-800LMT
12
C498
.1UF_0402
CardBus Socket
S1_A[0..25]<23>
S1_D[0..15]<23>
S1_D3 S1_CD1#
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#<23>
S1_OE#<23>
S1_WE#<23>
S1_RDY#<23>
12
S1_VPP S1_VPP
C506
10UF_10V_1206
S1_WP<23>
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP
S1_A[0..25]
S1_D[0..15]
JP21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
FOXCONN_1CA415M1-TA_68P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
72
74
76
78
80
82
84
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_VCCLS1_VCCL
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#
1 2
12
C91
1000PF_0402
C191
1000PF_0402
S1_CD1# <23>
S1_CE2# <23>
S1_VS1 <23>
S1_IORD# <23>
S1_IOWR# <23>
S1_VS2 <23>
S1_RST <23>
S1_WAIT# <23>
S1_INPACK# <23>
S1_REG# <23>
S1_BVD2 <23>
S1_BVD1 <23>
S1_CD2# <23>
JP21AS1
CARDBUS HOUSI NG
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
24 46,
J
2B
Page 25
10
9
8
7
6
5
4
3
2
1
H H
+3VALW
22
24
25
26
28
29
31
32
37
38
40
41
42
43
45
46
61
63
65
66
67
69
70
71
74
76
77
79
80
81
82
84
34
47
60
73
16
18
19
36
49
50
52
53
54
56
13
21
57
58
12
85
14
89
90
U26
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
PCI_CLK
PCI_GNT
PCI_REQ
PCI_IDSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_INTA
PCI_PME
PCI_SERR
PCI_PAR
PCI_CLKRUN
PCI_RST
G_RST
GPIO3
GPIO2
REG_EN#
REG18
REG18
9
93
30
VDDP20VDDP35VDDP48VDDP62VDDP
TSB43AB22
PCI BUS I NTERF ACE
AGND
AGND
AGND
AGND
AGND
PLLGND1
8
109
110
111
117
126
127
G G
F F
E E
AD16
D D
C C
CLK_PCI_1394
12
R270
@10_0402
12
C291
@15PF_0402
CLK_PCI_1394<14>
1394_PME#<31>
PM_CLKRUN#<16,18,23,28,30,34>
AD[0..31]<16,23,26,34>
C/BE#3<16,23,26,34>
C/BE#2<16,23,26,34>
C/BE#1<16,23,26,34>
C/BE#0<16,23,26,34>
GNT#0<16,18>
REQ#0<16,18>
FRAME#<16,18,23,26,34>
IRDY#<16,18,23,26,34>
TRDY#<16,18,23,26,34>
DEVSEL#<16,18,23,26,34>
STOP#<16,18,23,26,34>
PERR#<16,18,23,34>
PIRQA#<15,16,18,23,26>
SERR#<16,18,23,34>
PAR<16,18,23,26,34>
PCIRST#<5,8,15,16,19,23,26,28,34>
G_RST#<15,23,24,30>
CLK_PCI_1394
R275 1394@100_0402
R287
R288
1 2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1394@220_0402
12
12
1394@220_0402
1394@100K_0402
12
R286
1394@100K_0402
78
87
CYCLEIN
PHY PORT 2
BIA S C URRENT
OSCILLATOR
FILTER
EEPROM 2 WIRE BUS
POWER CL ASS
PHY PORT 1
AGND
DGND44DGND55DGND64DGND
AGND
DGND17DGND
DGND
23
33
128
R285
12
86
CYCLEOUT
68
R272
1394@100K_0402
12
12
R291
1394@100K_0402
11
96
DVDD
CNA
DVDD
TEST1710TEST16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD
CPS
TPBIAS1
TPA1+
TPA1-
TPB1+
TPB1-
R0
R1
X0
X1
FILTER0
FILTER1
SDA
SCL
PC0
PC1
PC2
TPBIAS0
TPA0+
TPA0-
TPB0 +
TPB0 -
TEST9
TEST8
TEST3
TEST2
TEST1
TEST0
DGND75DGND
DGND
83
103
12
R269
1394@100K_0402
+3VALW
15
27
39
51
59
72
88
100
7
1
2
107
108
120
106
125
124
123
122
121
118
119
6
5
3
4
92
91
99
98
97
116
115
114
113
112
94
95
101
102
104
105
1 2
1394@0_0805
R283 1394@1K_0402
1 2
C298 1394@.1UF_0402
1 2
R273 1394@1K_0402
1 2
R274 1394@1K_0402
1 2
R276
1 2
X2
1394@24.576MHz
C295 1394@.1UF_0402
1 2
SDA_1395
SCL_1394
XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-
L28
VPLL_1394
12
C292
1394@.01UF_0402
1394@6.34K_1%_0402
Near 1394 IC
C293 1394@15PF_0402
1 2
C294 1394@15PF_0402
1 2
R290 1394@220_0402
1 2
R289 1394@220_0402
1 2
12
C288
1394@4.7UF_10V_0805
XTPBIAS0
XTPA0+ PA0+_C
XTPA0XTPB0+
XTPB0-
1394@220PF_0402
R281
1394@56.2_1%
C354
+3VALW
12
R278
1394@56.2_1%
12
12
1394@.1UF_0402
1394@.1UF_0402
12
12
C296
C289
1394@.1UF_0402
1394@.1UF_0402
12
12
C349
C350
1394@1000PF_0402
1394@1000PF_0402
12
12
C359
C362
1394@1000PF_0402
12
12
C356
C302
12
R279
1394@56.2_1%
12
R280
1394@56.2_1%
12
R284
1394@5.11K_1%
1394@.1UF_0402
12
C297
1394@.1UF_0402
12
C351
12
C360
1394@1000PF_0402
1394@1000PF_0402
12
C303
1394@1UF_25V_0805
12
C301
1394@.1UF_0402
12
C353
1394@.1UF_0402
L72 1394@0_0603
L71 1394@0_0603
L70 1394@0_0603
L69 1394@0_0603
1 2
1 2
1 2
1 2
JP30
4
PA0-_C
3
PB0+_C
2
PB0-_C
1
1394@1394_CONN 4PIN
12
C290
B B
1394@.1UF_0402
A A
10
9
8
12
C361
1394@.1UF_0402
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
7
6
5
4
3
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
25 46,
1
2B
Page 26
10
9
8
7
6
5
4
3
2
1
+3VS +2.5VS
H H
10
U66
AD[0..31]<16,23,25,34>
G G
CLK_PCI_USB20
12
F F
E E
AD27
D D
R552
@10_0402
12
C689
@15PF_0402
CLK_PCI_USB20<14>
PIRQA#<15,16,18,23,25>
PIRQB#<16,18>
PIRQC#<16,18,34>
USB20_PME#<31>
USB20_SMI#<16>
C/BE#3<16,23,25,34>
C/BE#2<16,23,25,34>
C/BE#1<16,23,25,34>
C/BE#0<16,23,25,34>
GNT#3<16,18>
REQ#3<16,18>
FRAME#<16,18,23,25,34>
IRDY#<16,18,23,25,34>
TRDY#<16,18,23,25,34>
DEVSEL#<16,18,23,25,34>
STOP#<16,18,23,25,34>
PAR<16,18,23,25,34>
PCIRST#<5,8,15,16,19,23,25,28,34>
CLK_PCI_USB20
New update 5/16 JOHNNY
R556 USB20@100_0402
1 2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
USB20@VT6202
116
AD31
117
AD30
118
AD29
121
AD28
122
AD27
123
AD26
124
AD25
125
AD24
126
AD23
1
AD22
2
AD21
7
AD20
8
AD19
11
AD18
12
AD17
13
AD16
14
AD15
15
AD14
16
AD13
29
AD12
30
AD11
31
AD10
32
AD9
37
AD8
38
AD7
39
AD6
40
AD5
42
AD4
45
AD3
46
AD2
47
AD1
48
AD0
3
-CBE3
19
-CBE2
28
-CBE1
41
-CBE0
109
PCICLK
112
-GNT
113
-REQ
6
IDSEL
20
-FRAME
21
-IRDY
22
-TRDY
23
-DEVSEL
24
-STOP
27
PAR
105
-INTA
106
-INTB
107
-INTC
111
PCIRST
67
-PME
64
-SMI
5
VCC33
VCC3318VCC3326VCC3334VCC3344VCC3352VCC3362VCC33
GND
GND17GND25GND33GND43GND51GND61GND
GND
9
101
GND36GND
110
120
VCC33
54
+3V_USB20
C688
12
USB20@.1UF_0402
128
115
70
108
GND
119
VCC254VCC2535VCC2553VCC25
GND
GND
127
114
VSUS
USBP1-
USBP1+
USBP2-
USBP2+
USBP3-
USBP3+
USBP4-
USBP4+
-USBOC0
-USBOC1
VCCUSB
VCCUSB
VCCUSB
VCCUSB
REXT
GNDUSB
GNDUSB
GNDUSB
GNDUSB
VCCPLLA
VCCOSC
VCCPLL
GNDPLLA
GNDOSC
GNDPLL
WAKEUP_EN
EECS
EESK
EEDO
ATPGEN
TESTMODE
TEST1
TEST2
TEST3
TEST4
XOUT
GND
GNDSUS
69
EEDI
NC
NC
NC
NC
NC
NC
XIN
USB20P1-
85
USB20P1+
86
81
82
USB20P3-
77
USB20P3+
78
73
74
OVCUR#0
71
OVCUR#1
68
84
80
76
72
R553
88
USB20@2.2K_0603_1%
87
83
79
75
89
96
91
90
93
92
60
63
97
103
104
102
98
49
50
55
56
USB20ATPGEN
65
USB20TESTMODE
66
USB20TEST1
57
USB20TEST2
58
59
99
USB20XIN
94
USB20XOUT
95
1 2
USB20@24MHz
C690
1 2
R554
USB20@3.92K_0603_1%
+2.5VS_USB20
R555 USB20@4.7K_0402
1 2
R557 @4.7K_0402
1 2
R620 USB20@4.7K_0402
1 2
R558 USB20@4.7K_0402
1 2
R559 USB20@4.7K_0402
1 2
X5
1 2
VCC33
VCC33
100
+3V_USB20
R628 USB20@100K_0402
R629 USB20@100K_0402
1 2
1 2
L81
USB20@BLM21A601SPT_0805
C691
12
12
OVCUR#0 <17>
OVCUR#1 <17>
+2.5VS
+3V_USB20
OVCUR#0
OVCUR#1
+3V_USB20
USB20TEST1
USB20TEST2
USB20ATPGENUSB20ATPGEN
USB20TESTMODE
L78
USB20@BLM21A601SPT_0805
1 2
1 2
L80
@BLM21A601SPT_0805
SUSON<36>
RP138 USB20@8P4R_4.7K
4 5
3 6
2 7
1 8
+3V
+3VS
+5V
R662
12
USB20@3M_0402
12
L73
USB20@0_0603
1 2
1
L74 @DLW21SN900SQ2
4
1 2
USB20@0_0603
L75
L76
USB20@0_0603
1 2
1
L77 @DLW21SN900SQ2
4
1 2
USB20@0_0603
L79
12
R663
USB20@100K_0402
13
D
Q87
2
G
USB20@2N7002
S
C748
USB20@.22UF_0603
12
C755
USB20@.1UF_0402
2
3
2
3
U67
1
GND
IN
EN1#
EN2#4OC2#
TPS2042
New update
5/16 JOHNNY
OC1#
OUT1
OUT2
2
3
12
R664
USB11@0_0402
Close to USB Port
8
7
6
5
USB0D- <32>
USB0D+ <32>
USB1D- <32>
USB1D+ <32>
OVCUR#0
OVCUR#1
USB_VCCA
USB_VCCB
C C
USB20@20PF_0603
USB20@20PF_0603
+3VS +2.5VS
B B
C692
USB20@.01UF_0402
C693
USB20@.1UF_0402
12
12
C694
USB20@.01UF_0402
C695
USB20@.1UF_0402
12
12
C696
C697
USB20@.1UF_0402
12
USB20@.01UF_0402
12
C698
USB20@.01UF_0402
C699
USB20@.1UF_0402
12
12
C701
USB20@.1UF_0402
12
C700
USB20@.01UF_0402
12
C702
USB20@.01UF_0402
C703
USB20@.1UF_0402
12
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
12
+3V_USB20
12
C704
USB20@.1UF_0402
5
C705
USB20@.1UF_0402
12
12
C706
USB20@.1UF_0402
C707
USB20@.1UF_0402
12
4
+2.5VS_USB20
12
C708
USB20@.1UF_0402
C709
USB20@.1UF_0402
12
C710
USB20@.1UF_0402
3
12
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
26 46,
1
2B
Page 27
New add 5/3 JOHNNY
5
4
3
2
1
+3VS
37
38
39
40
41
42
43
44
45
46
47
48
CLK_PCI_SD
WR_PT
SDPWCTL#
SDCLK
SD1
SD2
VDD3V
SD3
SD4
SD5
LAD3
LAD2
LAD1
LAD0
SERIRQ
SD@8P4R_4.7K_0804
MMC_DET#
SD4
SD3
SD_CLK
SD2
SD1
SD5
35
34
33
30
31
29
32
36
SDPWCTL#
28
VSS
SCC4
SCC8
SDLED
MSCLK
MSLED
MSPWCTL#
W83L518D (LPC)
VSS6SCBC88SCBC4
PME#5lESET#
LFRAME#3RESERVED
PCICLK
2
1
RP5
9
7
4
+3VS
1 8
2 7
3 6
4 5
12
12
D D
SD_CLK
R136
@10_0402
1 2
C C
C156
@10PF_0402
SD@10K_0402
B B
SDPWCTL#
CLK_PCI_SD
R175
@10_0402
1 2
C181
@15PF_0402
+3VS
12
R122
13
D
Q10
2
SD@2N7002
G
S
SD@.1UF_0402
LAD[0 ..3 ]<16,28,30>
U7
3
VIN
4
VIN/CE
2
GND
SD@RT9701-CB
SD_CLK
VOUT
VOUT
C207
C197
SD@10UF_10V_0805
R137 SD@10_0402
1 2
LAD[0 ..3 ]
CLK_PCI_SD<14>
LFRAME#<16,28,30>
LPC_RST#<28,30>
SD_3VCC+3VS
1
5
12
C148
SDOR711@4.7UF_10V_0805
SIRQ<16,18,23,28,30>
+3VS
SD1
SD2
SD3
SD4
SD5
LAD3
LAD2
LAD1
LAD0
MSLED
MSPWCTL#
MSCLK
25
MS4
MS326MS227MS1
SCPWCTL#
SCBPWCTL#
SCBCLK11SCBIO10SCBRST#
SCBPSNT
SD@W 83L518D (LPC)
12
R549
12
SD@10K_0402
R149
SD@1M
MS1
MS2
MS3
MS4
U8
24
MS5
23
XIN
22
XOUT
21
SCRST#
20
SCIO
19
SCCLK
18
SCPSNT
17
16
SCLED
15
VDD
14
SCBLED
13
MMC_DET#10Wr_Pt_Vss
8
SD4
7
SD3
6
Vss2
5
SDCLK
4
Vdd
3
Vss1
2
SD2
1
SD1
9
SD5
SDOR711@SD_SOCKET
MS5
CLK_SD48
MMC_DET#
12
R666
SD@4.7K_0402
JP6
Vss3
Vss4
Wr_Pt
11
12
13
14
CLK_SD48 <14>
C417
SD@.1UF_0402
12
R138
SD@4.7K_0402
499_1% change to 4.7K
2002/4/16 Johnny
WR_P
12
R631 SD@1K_0402
1 2
Add 1K
2002/4/16 Johnny
MS@10K_0402
MSPWCTL#
+5VS
12
C418
SD@10UF_10V_0805
MLED@10K_0402
+3VS
12
R579
13
D
Q66
2
MS@2N7002
G
S
WR_PT
WR_PT
MSLED
R645
12
3
4
2
CLK_SD48
R141
@10_0402
1 2
C161
@10PF_0402
R646
MLED@10K_0402
U69
VIN
VOUT
VIN/CE
VOUT
GND
MS@RT9701-CB
MS@4.7UF_10V_0805
12
+5VS
2
1
1
5
U76
MLED@7SH32FU
3 5
MS_3VCC+3VS
12
C714
MEDIALED
4
MEDIALED
New add 5/3 JOHNNY
MS1
MS2
MS3
MS5
MSCLK
MS@200K_0402
MLED@10K_0402
MS@4.7K_0402
MS4
12
R584
+5VS
12
R654
13
D
2
G
S
+3VS
R578
12
C716
MS@.1UF_0402
Q79
MLED@2N7002
12
MEDIA_LED# <15>
JP35
1
GND
2
BS
3
VCC
4
SDIO
5
RSVD
6
INS
7
RSVD
8
SCLK
9
VCC
10
GND
11
GND
12
GND
13
GND
14
GND
MS@HRS_CB1EBB
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
SCHEM AT IC , M/ B LA-1381
Size Docu ment Number Re v
401212
Custom
Date: Sheet
星期一 十二
?30, 2002
27 46,
1
of
2B
Page 28
A
B
C
D
E
F
G
H
I
J
1 1
SUPER I/O S MsC FDC47N227
LAD[0..3]<16,27,30>
2 2
CLK_PCI_SIO
3 3
CLK_14M_SIO
4 4
R368
@10_0402
1 2
C500
@15PF_0402
1 2
R375
@10_0402
1 2
C514
@15PF_0402
1 2
R374 10K
R388 10K
+3VS
PM_CLKRUN#<16,18,23,25,30,34>
CLK_PCI_SIO<14>
+3VS
R387 100K_0402
1 2
1 2
LFRAME#<16,27,30>
LDRQ#1<16>
SUS_STAT#<15,16>
+3VS
1 8
2 7
3 6
4 5
1 2
SIRQ<16,18,23,27,30>
RP84
8P4R-100K
R369 10K
PID0<15>
PID1<15>
PID2<15>
PID3<15>
PID4<15>
LAD0
LAD1
LAD2
LAD3
LPC_RST#
1 2
1 2
R386 10K
CLK_PCI_SIO
CLK_14M_SIO
PID0
PID1
PID2
PID3
PID4
PID0
PID1
PID2
PID3
PID4
5 5
C521
4.7UF_10V_0805
10V
12
C534
.1UF_0402
12
C512
.1UF_0402
12
C518
.1UF_0402
U48
20
LAD0
21
LAD1
22
LAD2
23
LAD3
24
LFRAME#
25
LDRQ#
26
PCIRST#
27
LPCPD#
50
GPIO12/IO_SMI#
17
IO_PME#
30
SIRQ
28
CLKRUN#
29
PCICLK
19
CLK14
48
GPIO10
54
GPIO15
55
GPIO16
56
GPIO17
57
GPIO20
58
GPIO21
59
GPIO22
6
GPIO24
32
GPIO30
33
GPIO31
34
GPIO32
35
GPIO33
36
GPIO34
37
GPIO35
38
GPIO36
39
GPIO37
40
GPIO40
41
GPIO41
42
GPIO42
43
GPIO43
44
GPIO44
45
GPIO45
46
GPIO46
47
GPIO47
51
GPIO13/IRQIN1
52
GPIO14/IRQIN2
64
GPIO23/FDC_PP
18
VTR
53
VCC
65
VCC
93
VCC
7
VSS
31
VSS
60
VSS
76
VSS
SMsC LPC47N227
PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7
BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#
DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#
DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#
IRMODE/IRRX3
IRRX2
IRTX2
RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0
DRVDEN1
GPIO11/SYSOPT
6 6
LPD[0 ..7 ]LAD[0 ..3 ]
LPD0
68
LPD1
69
LPD2
70
LPD3
71
LPD4
72
LPD5
73
LPD6
74
LPD7
75
LPTBUSY
79
LPTPE
78
LPTSLCT
77
LPTERR#
81
LPTACK#
80
LPTINIT#
66
LPTAFD#
82
LPTSTB#
83
LPTSLCTIN#
67
100
CTS#2
99
98
DSR#2
97
96
95
DCD#2
94
RI#2
92
89
CTSA#
88
87
DSRA#
86
85
RXDA
84
DCDA#
91
RIA#
90
IRMODE
63
IRRX
61
IRTXOUT
62
RDATA#
16
WDATA#
10
WGATE#
11
HDSEL#
12
FDDIR#
8
STEP#
9
5
INDEX#
13
DISKCHG#
4
WP#
15
TRACK0#
14
MTR0#
3
3MODE#
1
2
49
1 2
R491 @10K_0402
1 2
R135 10K_0402
Base I/O Address
0 = 02Eh
1 = 04Eh*
LPD[0..7] <29>
1 2
R415 1K
R405 10K
LPTBUSY <29>
LPTPE <29>
LPTSLCT <29>
LPTERR# <29>
LPTACK# <29>
LPTINIT# <29>
LPTAFD# <29>
LPTSTB# <29>
LPTSLCTIN# <29>CLK_14M_SIO<14>
IRMODE <29>
IRRX <29>
IRTXOUT <29>
RDATA# <19>
WDATA# <19>
WGATE# <19>
HDSEL# <19>
FDDIR# <19>
STEP# <19>
DRV0# <15,19>
INDEX# <19>
DISKCHG# <19>
WP# <19>
TRACK0# <19>
MTR0# <19>
3MODE# <19>
12
+3VS
12
R633
1K_0402
New add
5/16 JOHNNY
+5VS
CTSA#
DSRA#
DCDA#
RIA#
New add
5/16 JOHNNY
CTS#2
DSR#2
DCD#2
RI#2
TRACK0#
WP#
INDEX#
DISKCHG#
HDSEL#
WGATE#
WDATA#
FDDIR#
+5VS
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
RP88
6
7
8
9
10
10P8R_1K
RP141
8P4R_4.7K
RP91
8P4R_4.7K
RP85
1 8
2 7
3 6
4 5
8P4R_1K
+5VS
+3VS
+3VS
5
4
3
2
1
BOARD ID
+3VS
12
R408
@10K_0402
12
R409
10K_0402
SST
PT 0
QT
+5VS
STEP#
MTR0#
RDATA#
DRV0#
R407
@10K_0402
R402
10K_0402
BD_ID2
0
12
R315
@10K_0402
12
R316
10K_0402
BD_ID1
BD_ID2 <31>
BD_ID1 <31>
BD_ID0 <31>
BD_ID0
0
0
12
12
01
0
0
+3VS
1
1
0ST
1
.1UF_0402
C180
1 2
LPCRST
+3V
1 2
R299
10K_0402
PCIRST#<5,8,15,16,19,23,25,26,34>
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
12
C372
.1UF_0402
U29
1
3
NC7WZ14
VCC5Y1
A1
A2
GND
LPCRST
6
4
Y2
2
Title
Size Docu ment Number Re v
Custom
H
Date: Sheet
R303
10K_0402
1 2
LPC_RST#
D29
RB751V
21
LPC_RST# <27,30>
Compal Electronics, Inc.
SCHEM AT IC , M/ B LA- 1381
401212
星期一 十二
?30, 2002
I
28 46,
2B
of
J
Page 29
A
B
C
D
E
F
G
H
I
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Touch P a d & Stat us LED Conn.
+5VS
1 1
TPAD_ON/OFF#<31>
TPAD_LED#<30>
ACT_LED#<19>
PMLED_0#<31>
PMLED_1#<31>
BATLED_0#<31>
BATLED_1#<31>
TP_DATA<30>
TP_CLK<30>
2 2
22PF_0402
C583
+5VALW
12
12
C584
22PF_0402
3 3
1 2
L18
4.7UF_25V_0805
L85 FBM-11-160808-121
1 2
L86 FBM-11-160808-121
1 2
KB_ASPS2KB_VCC
12
L87 FBM-11-160808-121
L88 FBM-11-160808-121
C728
1 2
1 2
12
1000PF_0402
C729
PS2_CLK<30>
PS2_DATA<30>
+5VS
F2
POLYSWITCH_1.1A
4 4
W=40mils
4516
KBD_DATA<30>
KBD_CLK<30>
PS2_CLK
PS2_DATA
FBM-11-451616-800T
KBD_DATA
KBD_CLK
5 5
3
1
1
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
96212-1411S
Q72
@SM05
2
W=40mils
12
C730
220PF_0402
2
Q73
@SM05
JP7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10
9
8
7
6
10
9
8
7
6
+5V_PRN
+5V_PRN
12
C726
220PF_0402
12
C731
220PF_0402
JP17
4
2
1
563
KBD/PS2_6
KBD-35136S
12
12
C727
220PF_0402
C732
220PF_0402
+5V_PRN
+5V_PRN
FD0
FD1
FD2
FD3
SLCTIN#
PRNINIT#
ERR#
AFD/3M#
RP1
1
2
3
4
5
10P8R_2.7K
RP2
1
2
3
4
5
10P8R_2.7K
FD7
FD6
FD5
FD4
ACK#
BUSY
PE
SLCT
LPD[0..7]<28>
AFD/3M#
ERR#
PRNINIT#
SLCTIN#
ACK#
BUSY
PE
SLCT
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
LPD[0 ..7 ]
CP10
1 8
2 7
3 6
4 5
8P4C_220PF
CP3
1 8
2 7
3 6
4 5
8P4C_220PF
CP11
1 8
2 7
3 6
4 5
8P4C_220PF
CP12
1 8
2 7
3 6
4 5
8P4C_220PF
C39
4.7UF_10V_0805
+5V_PRN
12
12
C38
.1UF_0402
LPTSTB#<28>
LPTAFD#<28>
LPTERR#<28>
LPTINIT#<28>
LPTSLCTIN#<28>
LPTACK#<28>
LPTBUSY<28>
LPTPE<28>
LPTSLCT<28>
EXTFDD must connect
to docking.
+5VS
LPTSTB#
LPD0
L47 68
L46 68
LPD1
L45 68
L44 68
LPD2
L43 68
L42 68
LPD3
L41 68
L40 68
LPD4
L39 68
LPD5
L38 68
LPD6
L37 68
LPD7
L13 68
L16 68
L15 68
L14 68
L17 68
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Parallel Port
D7
w=10mils
2 1
1SS355
R4
33_0402
1 2
AFD/3M#
FD0
ERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3
FD4
FD5
FD6
FD7
ACK#
BUSY
PE
SLCT
+5V_PRN
12
R5
2.7K_0402
PWRPRN
w=10mils
14
15
16
17
18
19
20
21
22
10
23
11
24
12
25
13
1
2
3
4
5
6
7
8
9
C18
1 2
47PF_0402
JP15
LPTCN-25-SUYIN
+3VS
FIR Module
D34
RB751V
D35
RB751V
+3V
21
21
12
R335
100K_0402
C402
FIR@10UF_10V_1206
6 6
PCM_RI#<23>
7 7
MD_RI#<34>
RING#<30>
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
12
+
C404
FIR@.1UF_0402
F
T = 40mil
12
C403
+
FIR@22UF_10V_1206
U64
2
LED_C
4
RXD
6
VCC
8
GND
FIR@TFDU6101E
G
LED_A
TXD
MODE
+5VS
12
R332
FIR@10_1206
1
3
5
SD
7
T = 40mil
T = 12mil
T = 12mil
T = 12mil
H
12
R490
FIR@10_1206
IRTXOUT
IRMODE
IRRX
+
C400
FIR@10UF_10V_1206
+5VS_IR
IRTXOUT <28>
IRMODE <28>
IRRX <28>
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
C670
FIR@.1UF_0402
2B
of
29 46,
J
Page 30
A
B
C
D
E
123
136
157
VCC4
PORTB
PORTD-1
166
VCC5
VCC6
AD Input
DA output
PWM
or PORTA
PORTE
EC_AVCC
95
IOPB7/RING/PFAIL/LRESET2
PORTC
IOPD2/EXWINT24/LRESET2
IOPE7/CLKRUN/EXWINT46
PORTH
PORTI
PORTJ-1
PORTD-2
PORTK
PORTL
161
AVCC
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPJ1/WR0
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD
IOPL4/WR1
VBAT
IOPE0AD4
DP/AD8
DN/AD9
IOPC0
IOPH6/A6
IOPH7/A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
IOPJ0/RD
SELIO
IOPD4
IOPD5
IOPD6
IOPD7
IOPK0/A8
IOPK1/A9
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
+RTCVCC
C277
1UF_0603
1 2
U24
BATT_TEMPA
81
AD0
AD1
AD2
AD3
DA0
DA1
DA2
DA3
BATT_TEMPB
82
83
ADI_PR ADI_P
84
87
88
VOL_IN_UP#
89
VOL_IN_DN#
90
93
94
99
100
101
102
32
33
36
37
38
39
40
43
KSO16
153
KSO17
154
MAIL_LED#
162
EC_SMC1
163
EC_SMD1
164
LPC_RST#
165
168
EC_SMC2
169
EC_SMD2
170
171
PME_EC#
172
175
D24 RB751V
176
1
26
29
30
2
44
EC_MUTEI#
24
25
KBA0
124
KBA1
125
KBA2
126
KBA3
127
KBA4
128
KBA5
131
KBA6
132
KBA7
133
ADB0
138
ADB1
139
ADB2
140
ADB3
141
ADB4
144
ADB5
145
ADB6
146
ADB7
147
FRD#
150
FWR#
151
SELIO#
152
41
42
54
55
KBA8
143
KBA9
142
KBA10
135
KBA11
134
KBA12
130
KBA13
129
KBA14
121
KBA15
120
KBA16
113
KBA17
112
KBA18
104
KBA19
103
48
BATT_TEMPA <39>
BATT_TEMPB <39>
PROCHOT# <5>
ALI/NIMH# <39>
BLI/NIMH# <39>
VOL_IN_UP# <33>
VOL_IN_DN# <33>
DAC_BRIG <15>
EN_FAN1 <6>
EN_FAN2 <6>
IREF <38>
INVT_PWM <15>
BEEP# <21>
M_SEN# <15,31>
ACOFF <38>
VLBA# <16>
EC_ON <33>
LID_OUT# <16>
CONA# <31>
KSO16 <15>
MAIL_LED# <15>
EC_SMC1 <15,31,39>
EC_SMD1 <15,31,39>
LPC_RST# <27,28>
PBTN_OUT# <16>
EC_SMC2 <5,39>
EC_SMD2 <5,39>
FAN_SPEED <6>
PME_EC# <31>
21
FAN_SPEED2 <6>
WL_ON <32,34>
ACIN <17,37,40>
RING# <29>
SLP_S3# <16>
ON/OFF# <33>
SLP_S5# <16>
EC_MUTEI# <33>
PM_CLKRUN# <16,18,23,25,28,34>
FRD# <31>
FWR# <31>
SELIO# <31>
SCROLLED# <15>
NUMLED# <15>
CAPSLED# <15>
A/B#USE <39>
FSTCHG <39>
ADI_P
BATT_TEMPA
EC_THRM#
ADB[0..7]
KBA[0..19]
C366 @.01UF_0402
C364 .01UF_0402
1 2
1 2
R51910K_0402
C677
1 2
.22UF_0603
ECAGND
12
EEROM/BATTERY
THERMAL/DOCKING
EC_THRM# <16>
ADB[0..7] <31>
KBA[0..19] <31>
C365 .01UF_0402
12
*
BATT_TEMPB
ADI_P <38>
BADDR1-0
0 0
0 1
1 0
1 1
Index
(HCFGBAH, HCFGBAL)
I/O Address
2E
4E
Reserved
ENV0
0
IRE
OBD
*
SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the
signals for clip-on ISE use
KBA0
(ENV0)
KBA1
(ENV1)
KBA2
(BADDR0)
KBA3
(BADDR1)
KBA4
(TRIS)
KBA5
(SHBM)
EC_SMC1
EC_SMD1
EC_SMC2
EC_SMD2
JP27
1
1
EC_TINIT#
2
2
EC_TCK
3
3
EC_TDO
4
4
EC_TDI
5
5
EC_TMS
6
6
7
7
KSO16
8
8
KSO17
9
9
MAIL_LED#
10
10
@96212-1011S
0
1
DEV
PROG
1
R239 @10K_0402
R267 10K_0402
R254 @10K_0402
R252 10K_0402
R215 @10K_0402
R251 10K_0402
RP30
8P4R_10K_0804
+5VALW
Data
2F
4F
(HCFGBAH, HCFGBAL)+1
ENV1
TRIS
0
0
1
0
00
01
+3VALW
+5VALW
18
27
36
45
L31
L29
R401
12
C355
.1UF_0402
1 2
1
2
3
4
5
18
27
36
45
18
27
36
45
12
.1UF_0402
12
C300
C358
.1UF_0402
ECAGND
EC_RST#<33>
GATEA20
KBRST#
KBD_DATA
KBD_CLK
PS2_DATA
KBRST#
GATEA20
EC_THRM#
FSEL#
SELIO#
FRD#
EC_SMI#
VOL_IN_UP#
VOL_IN_DN#
EC_MUTEI#
D18
2 1
12
C280
1000PF_0402
12
C357
1000PF_0402
2 1
2 1
+5VS
RB751V
EC_AVCC
RB751V
D25
RB751V
D26
C279
10PF_0402
R249 20M
1 2
12
32.768KHZ
+3VALW
+3VS
LAD[0..3]<16,27,28>
X1
EC_SMI#<16>
EN_WOL#<34>
G_RST#<15,23,24,25>
ICH_SWI#<16,18>
TPAD_LED#<29>
SLP_S1#<14,16>
TRICKLE<39>
PCM_SUSP#<23>
EC_RSMRST#<33>
ENABLT<15>
BKOFF#<15>
CLK_PCI_LPC<14>
KSI[0..7]<15,33>
KSO[0..15]<33>
CLK_PCI_LPC
12
R277
@10_0402
12
C348
@15PF_0402
12
C278
10PF_0402
SYSON<36>
SUSP#<21,36,42>
FSEL#<31>
KBD_DATA<29>
DIS_ADJVOL<22>
R250
LFRAME#<16,27,28>
LAD[0 ..3 ]
KBD_CLK<29>
PS2_CLK<29>
PS2_DATA<29>
TP_CLK<29>
TP_DATA<29>
LID_SW#<15,31>
120K_0402
1 2
R268 0_0402
22UF_10V_1206
SIRQ<16,18,23,27,28>
EC_SCI#<16>
12
KSI[0 ..7 ]
KSO[0..15]
EC_SMI#
MMO_ON
FSEL#
C299
LAD0
LAD1
LAD2
LAD3
CLK_PCI_LPC
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA
LID_SW#
CRY1
CRY2
12
EC_SCI#
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
12
C304
.1UF_0402
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
EC_3VDD
7
SERIRQ
8
LDRQ
9
LFRAME
15
LAD0
14
LAD1
13
LAD2
10
LAD3
18
LCLK
19
LREST1
22
SMI
23
PWUREQ
31
IOPD3/ECSCI
5
GA20/IOPB5
6
KBRST/IOPB6
71
KBSIN0
72
KBSIN1
73
KBSIN2
74
KBSIN3
77
KBSIN4
78
KBSIN5
79
KBSIN6
80
KBSIN7
49
KBSOUT0
50
KBSOUT1
51
KBSOUT2
52
KBSOUT3
53
KBSOUT4
56
KBSOUT5
57
KBSOUT6
58
KBSOUT7
59
KBSOUT8
60
KBSOUT9
61
KBSOUT10
64
KBSOUT11
65
KBSOUT12
66
KBSOUT13
67
KBSOUT14
68
KBSOUT15
105
TINT
106
TCK
107
TDO
108
TDI
109
TMS
110
PSCLK1/IOPF0
111
PSDAT1/IOPF1
114
PSCLK2/IOPF2
115
PSDAT2/IOPF3
116
PSCLK3/IOPF4
117
PSDAT3/IOPF5
118
PSCLK4/IOPF6
119
PSDAT4/IOPF7
158
32KX1/32KCLKOUT
160
32KX2
62
IOPJ2/BST0
63
IOPJ3/BST1
69
IOPJ4/BST2
70
IOPJ5/PFS
75
IOPJ6/PLI
76
IOPJ7/BRKL_RSTO
148
IOPM0/D8
149
IOPM1/D9
155
IOPM2/D10
156
IOPM3/D11
3
IOPM4/D12
4
IOPM5/D13
27
IOPM6/D14
28
IOPM7/D15
173
SEL0
174
SEL1
47
CLK
16
VDD
Host interface
Key matrix scan
JTAG debug port
PS2 interface
PORTJ-2
PORTM
VCC134VCC245VCC3
+3VALW
+3VALW
1 1
+5VS
TP_CLK PS2_CLK
2 2
3 3
TP_DATA
22UF_10V_1206
1 2
1 2
GATEA20<16>
10
9
8
7
6
+3VS
1 8
2 7
3 6
4 5
+3VALW
+3VALW
+3VS
VR_ON<36,43>
12
C368
BLM11A20
BLM11A20
KBRST#<16>
RP35
10P8R_10K
RP32
8P4R_10K_0804
RP31
8P4R_10K_0804
RP79
8P4R_10K_0804
10K_0402
4 4
A
B
PC87591VPC
GND117GND235GND346GND4
AGND
GND5
GND6
GND7
122
159
167
137
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
96
C
NC212NC320NC421NC585NC686NC791NC892NC997NC10
NC1
11
ECAGND
98
L32
1 2
CHB1608U800
D
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
Date: Sheet
星期一 十二
?30, 2002
30 46,
E
of
2B
Page 31
A
B
C
D
E
11
INPUT
+3VALW
1A121Y1
1A241Y2
1A361Y3
1A481Y4
2A1112Y1
2A2132Y2
2A3152Y3
2A4172Y4
1
1G
19
2G
+3VALW
1A121Y1
1A241Y2
1A361Y3
1A481Y4
2A1112Y1
2A2132Y2
2A3152Y3
2A4172Y4
1
1G
19
2G
R450
1 2
20K_0402
OUTPUT
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
3
LARST#
C602
1 2
1UF_0603
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
8
LARST#
3
11
1
3
11
1
+5VALW
20
D0
D14Q1
VCC
D27Q2
D38Q3
D413Q4
D514Q5
D617Q6
D718Q7
CLK
CLR
+5VALW
20
D0
D14Q1
VCC
D27Q2
D38Q3
D413Q4
D514Q5
D617Q6
D718Q7
CLK
CLR
C599
1 2
.1UF_0402
U58
Q0
GND
74HCT273
10
1 2
U31
Q0
GND
74HCT273
10
C378
2
5
6
9
12
15
16
19
.1UF_0402
2
5
6
9
12
15
16
19
ADJVOL_UP/DW# <22>
BT_RST# <32,34>
BT_DETACH <32,34>
BT_ON# <32,34>
PMLED_0# <29>
PMLED_1# <29>
BATLED_0# <29>
BATLED_1# <29>
EC_WAKEUP# <16>
EC_GRST <33>
EC_MUTEO <22,33,35>
EC_CPUVID0 <7>
EC_CPUVID1 <7>
EC_CPUVID2 <7>
EC_CPUVID3 <7>
EC_CPUVID4 <7>
C601
1 2
.1UF_0402
20
U56
ADB0
18
ADB1
16
VCC
10
20
VCC
10
GND
1 2
U33
GND
14
12
9
7
5
3
74LVC244
C377
.1UF_0402
18
16
14
12
9
7
5
3
74LVC244
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
CONA#<30>
LID_SW#<15,30>
S_TSR
EXTID0
EXTID1
EXTID2
CONA#
BT_PRES#
1394_PME#
PCM_PME#
MDM_PME#
LAN_PME#
DS_PME#
DOCKINTR#
UNDOCK#
BT/WL_ON/OFF#
IN4
IN3
IN2
IN1
QVCC_OK
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 2
R46 100K_0402
RP133
8P4R_100K_0804
RP80
8P4R-100K
RP81
8P4R_100K_0804
RP82
8P4R_100K_0804
RP134
8P4R_100K_0804
+3VALW
+3VALW
+3VALW
+3VS
KBA2
SELIO#
KBA4
SELIO#
C379
1 2
.1UF_0402
+3VALW
C381
1 2
.1UF_0402
+3VALW
147
1
2
+3VALW
147
9
10
U17A
74LVC32
U17C
74LVC32
CPU_ECVID0<7>
CPU_ECVID1<7>
CPU_ECVID2<7>
CPU_ECVID3<7>
CPU_ECVID4<7>
NB/DT#_CPU<7,43>
TPAD_ON/OFF#<29>
BT/WL_ON/OFF#<32>
BT_WAKE_UP<32,34>
ADB[0 ..7 ]
KBA[0..19]
EXTID0<19>
EXTID1<19>
EXTID2<19>
KBA1
SELIO#
BD_ID0<28>
BD_ID1<28>
BD_ID2<28>
BT_PRES#<32,34>
KBA3
SELIO#
+3VALW
147
4
5
EXTID0
EXTID1
EXTID2
U17B
74LVC32
TPAD_ON/OFF#
BT/WL_ON/OFF#
BT_PRES#
BT_WAKE_UP
1 2
R311 100K_0402
+3VALW
U17D
147
74LVC32
12
13
6
ADB[0..7]<30>
KBA[0..19]<30>
1 1
SELIO#<30>
2 2
R509
M_SEN#
M_SEN#<15,30>
3 3
U18
KBA18
1
NC
KBA16
2
A16
KBA15 KBA17
3
A15
KBA12 KBA14
4
A12
KBA7 KBA13
5
A7
KBA6 KBA8
6
A6
KBA5 KBA9
7
A5
KBA4 KBA11
8
A4
KBA3 FRD#
9
A3
KBA2 KBA10
10
A2
KBA1 FSEL#
11
A1
KBA0
12
A0
ADB0 ADB6
13
DQ0
ADB1
14
DQ1
ADB2 ADB4
15
DQ2
16
VSS
29F040/SST39VF040_PLCC
U20
1
A11
KBA9
2
A9
KBA8
3
A8
KBA13
4
4 4
KBA14
KBA17
FWE#
KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
A13
5
A14
6
A17
7
WE#
8
VCC
9
A18
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
@SST39VF040_TSOP
A
VCC_FLASH
VCC
WE*
DQ7
DQ6
DQ5
DQ4
DQ3
32
FWE#
31
30
A17
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE*
23
A10
22
CE*
ADB7
21
20
ADB5
19
18
ADB3
17
FRD#KBA11
32
OE#
KBA10
31
A10
FSEL#
30
CE#
ADB7
29
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VSS
ADB6
28
ADB5
27
ADB4
26
ADB3
25
24
ADB2
23
ADB1
22
ADB0
21
KBA0
20
A0
KBA1
19
A1
KBA2
18
A2
KBA3
17
A3
12
+
C563
4.7UF_10V_0805
FRD# <30>
FSEL# <30>
C564
.1UF_0402
1 2
VCC_FLASHVCC_FLASH
1 2
R435 0_0402
TSOP 8x14 TSOP 8x20
FWE#
+3VALW
C220
1 2
.1UF_0402
4
7SH32FU
KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#
KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
B
+3VALW
3 5
U19
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE#
8
VCC
9
A18
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
@29F040_TSOP
+3VALW
12
U15
2
1
R238
100K_0402
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
+5VS
12
2
1 3
D
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R431
100K_0402
G
Q52
2N7002
S
FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3
EC_FLASH# <17>
FWR# <30>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
10K_0402
update from 100K to 10K
5/3 JOHNNY
PCM_PME#<23>
1394_PME#<25>
MDM_PME#<34>
LAN_PME#<34>
USB20_PME#<26>
C
+3V
12
R669
10K_0402
PCM_PME#
1394_PME#
MDM_PME#
LAN_PME#
USB20_PME#
12
2
3 1
Q88
D20
3904
RB751V
D21
RB751V
D22
RB751V
D44
RB751V
R670
22K_0402
21
21
21
21
+3VALW
12
R240
100K_0402
PEM_EC#
PME_EC# <30>
.1UF_0402
EC_SMC1<15,30,39>
EC_SMD1<15,30,39>
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
+3VALW +3VALW
12
C265
12
R237
100K_0402
U16
8
VCC
7
WC
6
SCL
5
SDA
NM24C16-27
GND
1
A0
2
A1
3
A2
4
Compal Electronics, Inc.
SCH EMATIC, M/B LA-1381
401212
星期一 十二
?30, 2002
31 46,
E
12
R430
100K_0402
12
R426
100K_0402
2B
of
Page 32
10
9
8
7
6
5
4
3
2
1
MDC Conn.
JP11
1
MONO_OUT/PC_BEEP
3
AGND
5
AUXA_RIGHT
7
AUXA_LEFT
9
CD_GND
11
CD_RIGHT
13
CD_LEFT
15
GND
17
3.3Vaux
19
GND
21
3.3Vmain
23
AC97_SDATA_OUT
25
AC97_RESET#
27
GND
29
AC97_MSTRCLK
MDC@AMP 3-1473290-0
12
C392
@1000PF_0402
AUDIO_PWDN
MONO_PHONE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0
AC97_BITCLK
C596
1 2
BT/WL@.1UF_0402
SW2
21
43
BT/WL@HCH_PTS-05
12
C393
@.1UF_0402
GND
+5V
GND
BT/WL_ON/OFF#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
+5VMDC
1 2
R329 @0_0805
@1000PF_0402
1 2
R326 MDC@10K_0402
R328
12
MDC@22_0402
R327
12
@22_0402
1 2
BT/WL_ON/OFF# <31>
C758
1 2
R325
15_0402
C391
22PF_0402
+5V
MD_SPK <21,34>
MDC_DET# <17,18>
+3V
IAC_SYNC <16,21,34>
SDATA_IN1 <16,34>
IAC_BITCLK <16,21,34>
+5VALW
0: Have primary CODEC on mother board
BLUE TOOTH
GREEN
D28
2 1
BT@12-215 SYGC
D45
2 1
12-215 UYOC
GREEN
WIRELESS LAN
R651
WL@330_0402
+5VS
12
1 2
JP34
1
1
3
224
RJ11 CONN.
2
B
10K
10K
E
BT@DTA114EKA
Q78
DTC144EKA
1
C
47K
2
3 1
Q33
R660
10K_0402
3
4
BT_ON#
R300
BT@330_0402
3
47K
New add 5/3 JOHNNY
12
WL_ON <30,34>
C666
MDC@.1UF_0402
+3VMDC
+3V
C759
1 2
@1000PF_0402
MDC Note
H H
G G
F F
USBP3+<17,34>
USBP3-<17,34>
E E
D D
Pin 1 is NC for Pctel and connexant MDC modem
Pin 2 is NC for Pctel and connexant MDC modem
+3VMDC
12
C667
MDC@.1UF_0402
1 2
+3V
+3VALW
1 2
R487 MDC@0_0805
1 2
R486 @0_0805
MDC@4.7UF_10V_0805
C668
BlueTooth Interface
BT_DETACH<31,34>
L26 BT@FBM-11-160808-121
1 2
1 2
L27 BT@FBM-11-160808-121
BT_WAKE_UP<31,34>
BT_RST#<31,34>
BT@.1UF_0402
+3VALW +5VALW
C444
BT_WAKE_UP
12
Bluetooth Connector
JP26
1 2
3 4
5 6
7 8
9 10
121411
13
15 16
171918
20
BT@AXK5S20035
USB CONNECTOR 2
W=40mils
USB_VCCB
USBP1-<17>
USBP1+<17>
C672
.1UF_0402
USBP1USBP1+
12
+
C671
100UF_16V_D2
L67
USB11@FBM-11-160808-121
1 2
1 2
USB11@FBM-11-160808-121
L68
12
C673
1000PF_0402
USB1DUSB1D+
12
C665
MDC@1000PF_0402
BT_ON#
12
C233
BT@.1UF_0402
JP32
1
2
3
4
USB2_CONN
12
MD_MIC<21,34>
IAC_SDATAO<16,21,34>
AC97_RST#<16,21,34>
BT_ON# <31,34>
BT_PRES# <31,34>
USB1D-<26>
USB1D+<26>
USB20@15K_0402
C C
+5V
12
C756
USB11-3@.1uF_0402
B B
U78
1
GND
2
IN
3
IN
EN#4OC#
USB11-3@TPS2041
OUT
OUT
OUT
USB_VCCC
USB_VCCC
8
7
6
5
OVCUR#2 <17>
12
12
R560
R561
USB20@15K_0402
USB CONNECTOR 3
W=40mils
12
C742
USB11-3@.1UF_0402
USBP2-<17>
USBP2+<17>
USBP2USBP2+
+
C741
USB11-3@100UF_16V_D2
L89
USB11-3@FBM-11-160808-121
1 2
1 2
USB11-3@FBM-11-160808-121
L90
12
USB2DUSB2D+
C743
USB11-3@1000PF_0402
JP37
1
2
3
4
USB3_CONN
USB CONNECTOR 1
W=40mils
USB_VCCA
USBP0-<17>
USBP0+<17>
USB0D-<26>
USB0D+<26>
C394
.1UF_0402
USBP0USBP0+
12
USB11@FBM-11-160808-121
USB11@FBM-11-160808-121
+
C396
100UF_16V_D2
L35
1 2
1 2
L34
12
C395
1000PF_0402
USB0DUSB0D+
R562
USB20@15K_0402
12
12
R563
USB20@15K_0402
JP12
1
2
3
4
USB1_CONN
New add 5/3 JOHNNY
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
32 46,
1
2B
Page 33
A
1 1
R271
EC_RST#<30> RSMRST# <16,20>
200K_0402
330K_0402
12
R184
2 2
R440 10K_0402
1 2
+3V
VGATE<43>
R665 10K_0402
1 2
3 3
4 4
5 5
6 6
+5V +3V
12
R419
12
+5VS
DT@47K_0402
C533
DT@.1UF_0402
1 2
R442
DT@240K_0402
DT@100K_0402
R416
7 7
1 2
DT@330K_0402
8 8
A
12
12
C757
1000PF_0402
R244 100K_0402
1 2
+3VALW
C590
12
DT@.01UF_0402
11 10
DT@.01UF_0402
12
R445
B
12
C188
.1UF_0402
ITP_DBR#<5>
RSM_RST#
7 14
12
B
Power ON Circuit
+3VALW
147
U12A
74LVC14
1 2
+3VALW
147
2 3
VR_ON#<36>
R451
+3VS
@240_0402
4
U21B
5 6
74LVC125
C287
100PF_0402
1 2
2
1
U12E
74LVC14
12
C569
C567
DT@.1UF_0402
1
U21A
74LVC125
ITP_PWROK
2
3 5
DT@7SH32FU
C
RSM_RST#
R182 M@20K_0402
1 2
2
G
1 2
R439 0_0402
1 2
R255 10K_0402
Q31
3904
3 1
C183
1 2
U13
DT@.1UF_0402
4
5
MR#
3
PFI
C
+3VALW
U12B
74LVC14
3 4
7 14
13
D
Q20
@2N7002
S
+3VS
C610 @.01UF_0402
1 2
53
U14
1
2
@7SH08
R422 M@0_0402
+3V
10K_0402
+3VS
C201
1 2
DT@.1UF_0402
1
U53
6
RST#
VCC
4
PFO#
GND
DT@MAX6342
2
C186
M@1UF_0805_X7R
1 2
4
R438
12
+3VS
D
R196
1 2
0_0402
+3VALW
5 6
7 14
10
U21C
9 8
74LVC125
D
1 2
12
R203
@100K_0402
U12C
74LVC14
12
R418
@10K_0402
ICH_VGATE <16>
CK408_PWRGD# <14>
1 2
12
R212
DT@10K_0402
R241
@0_0402
RSMRST#
+3VALW
9 8
7 14
PM_PWROK
R213 DT@0_0402
E
U12D
74LVC14
EC_RSMRST# <30>
DT : REMOVE
ITP_PWROK
PM_PWROK <16>
F
EC_MUTEO<22,31,35>
G
EC_GRST<31>
ON/OFFBTN#<15>
+3VALW
12
2
G
EC_ON
+5VS
12
R314
220_0402
New update
5/16 JOHNNY
21
D30
67-21SYGC
GREEN
13
D
Q36
2N7002
S
EC_ON<30>
SW3
1 2
3 4
RESET BTN
Power BTN
R51
100K_0402
1 2
R52
0_0402
D9
3
DAN202U
H
2
Q7
DTC124EK
VOL_IN_DN#<30>
EC_MUTEI#<30>
VOL_IN_UP#<30>
+3VALW
1
2
22K
B
22K
INT_KBD CONN.
KSI[0 ..7 ]
KSO[0..15]
JP5
KSI1
1
1
KSI7
DT : INSTALL
PM_PWROK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
F
G
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
INT_KB_CONN.
H
I
J
Reset Button
+3VALW
12
R447
10K_0402
1 2
13
C
KSI[0..7] <15,30>
KSO[0..15] <30>
C286 .01UF_0402
1 2
U23
2
1
3 5
R253
10K_0402
1 2
R47 100K_0402
ON/OFF#
12
C68
1000PF_0402
E
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
4
7SH32FU
12
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
C398
.1UF_0402
1 2
C399
.1UF_0402
1 2
C401
.1UF_0402
1 2
?30, 2002
I
EC_RST#
+3VALW
ON/OFF# <30>
EC_PWR_ON# <37>
D8
RLZ20A
SW1
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
3
4
5
6
7
1
2
a
GND
b
c
d
e
f
g
8
HSS115A
CP6
1 8
2 7
3 6
4 5
8P4C_100PF
CP7
1 8
2 7
3 6
4 5
8P4C_100PF
CP4
1 8
2 7
3 6
4 5
8P4C_100PF
CP5
1 8
2 7
3 6
4 5
8P4C_100PF
CP8
1 8
2 7
3 6
4 5
8P4C_100PF
CP9
1 8
2 7
3 6
4 5
8P4C_100PF
33 46,
J
of
2B
Page 34
A
B
C
D
E
F
G
H
I
J
1 1
Or use SI2305DS.
+3VALW +3VAUX
12
C275
2 2
3 3
+3VS
4 4
5 5
6 6
+3VALW +5VALW
12
C711
.1UF_0402
R425
+3VS_MINI_L
12
0_1206
12
C548
1000PF_0402
CLK_PCI_MIN
12
R428
@10_0402
12
C550
@15PF_0402
IAC_BITCLK
12
R432
@10_0402
12
C552
@15PF_0402
12
C712
12
C551
100PF_0402
.1UF_0402
101
103
105
107
109
111
113
115
117
119
121
123
127
JP24
KEY KEY
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
127
128
Mini-PCI SLOT
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
128
1 2
R510 10K_0402
TIP RING
+3VALW
+5VALW
BT_PRES#<31,32>
BT_ON#<31,32>
WL_ON<30,32>
BT_DETACH<31,32>
PIRQD#<16,18>
REQ#4<16,18> GNT#4 <16,18>
CLK_PCI_MIN<14>
REQ#1<16,18>
AD31<16,23,25,26>
AD29<16,23,25,26>
AD27<16,23,25,26>
AD25<16,23,25,26>
IDSEL : AD22
C/BE#3<16,23,25,26>
AD23<16,23,25,26>
AD21<16,23,25,26>
AD19<16,23,25,26>
AD17<16,23,25,26>
C/BE#2<16,23,25,26>
IRDY#<16,18,23,25,26>
PM_CLKRUN#<16,18,23,25,28,30>
SERR#<16,18,23,25>
PERR#<16,18,23,25>
C/BE#1<16,23,25,26>
AD14<16,23,25,26>
AD12<16,23,25,26>
AD10<16,23,25,26>
AD8<16,23,25,26>
AD7<16,23,25,26>
AD5<16,23,25,26>
AD3<16,23,25,26>
+5VS
AD1<16,23,25,26>
IAC_SYNC<16,21,32>
IAC_BITCLK<16,21,32>
MD_MON<21>
MD_MIC<21,32>
MD_RI#<29>
+5VS
W=40mils
CLK_PCI_MIN
REQ#1 GNT#1
AD22
W=30mils
IAC_BITCLK
MD_MON
12
C767
1000PF_0402
BT_ON#
WL_ON
1 2
R427 0_0402
1 2
R429 100_0402
W=30mils W=40mils
LAN RESERVEDLAN RESERVED
BT_WAKE_UP
W=30mils
1 2
R231 0_0402
W=40mils
W=40mils
1 2
R236 100_0402
MD_SPK
+3VS_MINI_R
MDM_PME#
LAN_PME#
AD18
12
C768
IDSEL : AD18
1000PF_0402
BT_WAKE_UP <31,32>
BT_RST# <31,32>
+5VS
PIRQC# <16,18,26>
+3VAUX
PCIRST# <5,8,15,16,19,23,25,26,28>
GNT#1 <16,18>
MDM_PME# <31>
LAN_PME# <31>
AD30 <16,23,25,26>
AD28 <16,23,25,26>
AD26 <16,23,25,26>
AD24 <16,23,25,26>
AD22 <16,23,25,26>
AD20 <16,23,25,26>
PAR <16,18,23,25,26>
AD18 <16,23,25,26>
AD16 <16,23,25,26>
FRAME# <16,18,23,25,26>
TRDY# <16,18,23,25,26>
STOP# <16,18,23,25,26>
DEVSEL# <16,18,23,25,26>
AD15 <16,23,25,26>
AD13 <16,23,25,26>
AD11 <16,23,25,26>
AD9 <16,23,25,26>
C/BE#0 <16,23,25,26>
AD6 <16,23,25,26>
AD4 <16,23,25,26>
AD2 <16,23,25,26>
AD0 <16,23,25,26>
IAC_SDATAO <16,21,32>SDATA_IN1<16,32>
AC97_RST# <16,21,32>
MD_SPK <21,32>
+3VAUX
12
C261
100PF_0402
L82 FBM-11-160808-121
12
12
L83 FBM-11-160808-121
R234
1 2
0_1206
12
C262
1000PF_0402
USBP3+ <17,32>
USBP3- <17,32>
+3VS
4.7UF_10V_0805
4.7UF_10V_0805
4.7UF_10V_0805
+5VS
C549
+3VS
C223
+3VAUX
C264
1UF_0603
EN_WOL#<30>
12
+
12
+
12
+
12
C553
.1UF_0402
12
12
C263
.1UF_0402
C230
.1UF_0402
12
C554
1000PF_0402
12
C231
.1UF_0402
12
C256
1000PF_0402
12
C542
1000PF_0402
Q28
SI2301DS
S
G
+
2
12
D
13
C543
4.7UF_10V_0805
12
C274
1UF_0603
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCH EMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
34 46,
J
2B
Page 35
A
B
C
D
E
F
G
H
I
J
1 1
R641 SUB@100K_0402
RIGHT
RIGHT<21,22>
LEFT<21,22>
1 2
R642 SUB@100K_0402
LEFT MIX_IN
1 2
C738
SUB@1UF_0402
R643 SUB@100K_0402
1 2
SUB_VREF
2 2
MIX_OUT
1
1OUT
2
1IN-
3
1IN+
4
GND
U75
R638 SUB@1K_0402
1 2
8
VDD+
7
2OUT
6
2IN-
5
2IN+
SUB@TLV2462
SUB@.1UF_0402
C749
+5V_AMP
12
R639 SUB@1K_0402
1 2
12
C737
SUB@@150PF_0402
LPF_OUT
LPF_IN
C739 SUB@.1UF_0402
SUB_IN
SUB_VREF
C740 SUB@100PF_0402
SUB_VREF
+5V_AMP
R655
12
@39.2K_0402_1%
12
R656
@39.2K_0402_1%
R657
1 2
SUB@0_0402
+AUD_VREF
3 3
S
EC_MUTEO<22,31,33>
EC_MUTEO
4 4
Q81
G
S
S
G
2
SUB@2N7002
13
D
D
13
Q83
SUB@2N7002
2
SUBSPKF-
SUBSPKF+
R659
SUB@100K_0402
1 2
+5VS
+5V_AMP
12
5 5
C750
SUB@.1UF_0402
C736
SUB@.47UF_0402
SUB_IN
SUB_SD#
12
U73
1
IN
2
SHUTDOWN#
3
VDD
4
BYPASS
GND
SE/BTL
SUB@TPA0211
SUB@100K_0402
VO+
8
VO-
7
6
5
12
R637
SUBSPKFF-
SUBSPKFF+
G
2
1 3
1 3
D
D
D
Q80
1 3
SUB@2N7002
2
G
Q82
SUB@2N7002
S
S
Q84
SUB@2N7002
G
2
R658
1 2
+12VALW
SUB@100K_0402
SUBSPK-
SUBSPK+
JP36
2
2
1
1
SUB@ W OOFER CONN
Layout note:
Trace width=15 mils.
1.SUBSPKFF-,SUBSPKFF+,SUBSPKF-,SUBSPKF+SUBSPK-,SUBSPK+
+
C745
SUB@10UF_16V_1206
16V
6 6
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
I
of
35 46,
J
2B
Page 36
A
+12VALW
12
R363
Q46
2N7002
100K_0402
12
13
D
R364
2
G
1M_0402
S
1 1
SYSON#
2 2
3 3
+3VALW
U49
8
7
6
R353
1M_0402
5
SI4800
12
C527
10UF_6.3V_P
12
12
C520
+
33UF_D2_16V
4 4
SUSP
+12VALW
R352
100K_0402
2
G
Q44
2N7002
12
13
D
S
5 5
6 6
B
+5VALW to +5V Transfer
+5VALW
12
C491
.01UF_0402
+5VALW +5VALW
12
C493
4.7UF_10V_0805
+3VALW to +3V Transfer
+3V
1
S
D
2
S
D
3
S
D
4
G
D
+5VALW to +5VS Transfer
+5VALW
12
C467
.01UF_0402
+5VALW
C463
4.7UF_10V_0805
U44
8
D
7
D
6
D
5
D
SI4800
SUSON
12
C526
10UF_10V_1206
SUSON
U42
8
D
7
D
6
D
5
D
RUNON
12
S
S
S
G
12
C490
+
33UF_D2_16V
SI4800
S
S
S
G
+5VALW
12
+
1
2
3
4
12
C538
.1UF_0402
SUSON <26>
+5VS
1
2
3
4
C452
100UF_D_16V
C
+5V
12
C487
10UF_10V_1206
D
S
12
C453
.1UF_0402
12
R420
470_0402
13
2
G
Q50
2N7002
12
C459
22UF_10V_1206
12
C484
.1UF_0402
SYSON#
D
S
12
R348
470_0805
Q43
13
2N7002
D
S
G
12
13
2
D
R361
470_0805
2
G
Q45
2N7002
SUSP
SYSON#
E
+3VALW
R232
@100K_0402
1 2
VR_ON#<33>
VR_ON<30,43>
+12VALW To +12VS Transfer +2.5V To +2.5VS Transfer
C187
1 2
@.1UF_25V_0805
R177
1 2
100K_0402
+12VALW
12
C184
1UF_25V_0805
U9
8
D
7
D
6
D
5
D
12
C195
10UF_6.3V_P
CF5
HOLEB
VR_ON#
13
VR_ON
+12VALW
4
6
SUSP# SUSP#
5
+1.8VS+1.8VALW
SI4800
1
S
2
S
3
S
4
G
CF8
HOLEB
H5
D
2
G
Q25
S
@2N7002
Q16
SI3861
D
S
2
G
3
C193
12
1
1UF_25V_0805
12
R189
0_0402
+1.8VALW to +1.8VS Transfer
12
C177
22UF_10V_1206
RUNON
CF7
CF6
HOLEB
HOLEB
H13
1
HOLEC
H3
F
+CPU_CORE
12
R235
@330
13
D
2
G
Q26
S
@2N7002
+12VS
12
R515
470_0402
13
D
SUSP SUSP
2
G
Q63
S
2N7002
C405
1 2
@.1UF_0402
R1
1 2
100K_0402
+2.5VS
12
+
C412
4.7UF_10V_0805
+1.25VS
D
S
12
R520
470_0402
13
Q65
2N7002
+2.5V
SUSP
2
G
Q39
SI3865
S
4
6
5
-+
12
12
C179
R179
470_0402
.1UF_0402
CF10
HOLEB
RTC Battery
CF13
HOLEB
H21
1
HOLEC
H7
HOLEC
Q18
13
D
2N7002
SUSP
2
G
S
CF14
CF9
HOLEB
HOLEB
H11
H12
H22
1
1
HOLEC
H29
G
SUSP<42>
SUSP#<21,30,42>
D
2
G
3
12
+
C413
1
4.7UF_10V_0805
12
R333
0_0402
BATT1
RTCBATT
+RTCVCC
CF16
HOLEB
H2
HOLEC
H9
CF18
HOLEB
1
D
S
12
R516
470_0402
13
Q64
2N7002
12
+2.5VS
2
G
RTCPWR
HOLEB
HOLEC
SUSP
CF11
H19
H10
2
G
RTCPWR
1
3
HSM126S
1
H
+12VALW
2
CF15
HOLEB
HOLEC
12
R424
10K_0402
13
D
Q53
2N7002
S
+1.5VALW to +1.5VS Transfer
+1.5VS
12
C424
22UF_10V_1206
12
C669
.1UF_0402
D41
CHGRTC
CF12
HOLEB
H15
1
H4
CF17
HOLEB
HOLEC
CF19
HOLEB
H23
1
H1
I
12
C27
.1UF_0402
SYSON#<42>
SYSON<30>
CF20
HOLEB
H27
HOLEC
H28
D
S
1
12
R214
470_0402
13
Q22
2N7002
2
G
CF1
HOLEB
HOLEC
CF3
SUSP
SYSON#
H18
CF2
HOLEB
1
2
G
HOLER
CF4
+12VALW
12
13
D
S
H31
J
R423
47K_0402
Q27
2N7002
HOLES
H32
HOLEB
HOLEB
7 7
12
+
8 8
A
C530
100UF_D_16V
+3VALW +3VS
U50
SI4800
8
7
6
5
12
C537
10UF_6.3V_P
1
S
D
2
S
D
3
S
D
4
G
D
B
+3VALW to +3VS Transfer
12
C546
22UF_10V_1206
RUNON
12
C531
.1UF_0402
C
12
R406
82_0402
13
D
S
New update 5/20 Johnny
Q49
2N7002
SUSP
2
G
D
1
HOLED
H25
1
HOLEH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HOLED
HOLEH
1
H24
1
E
HOLEL
HOLEI
1
H14
1
1
HOLEP
H16
1
HOLEI
F
HOLEE
H17
HOLEG
1
H20
HOLEG
1
HOLEE
G
H26
HOLEG
HOLEE
1
HOLEF
FD3
FD2
HOLEA
HOLEA
H
1
HOLEJ
FD1
FD4
HOLEA
HOLEA
Compal Electronics, Inc.
Title
SCHEM AT IC , M/ B LA- 1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
HOLEK
I
FD6
HOLEA
?30, 2002
1
FD5
HOLEA
H8
HOLET
H30
1
36 46,
1
HOLET
of
J
2B
Page 37
A
B
C
D
Vin Detector
High 1 8 . 78 4 17. 901 17.077 V
Low 1 7 . 8 77 17. 043 16.195 V
VIN VS
12
PR3
84.5K_1%
PC6
1000PF_50V
3
PZD3
RLZ6.2C
12
PR6
20K_1%
12
12
12
12
VS
PR13
10K_1%
0.1UF_16V
PC9
1000PF_50V
PR5
22K
1 2
PC7
7
PR1
1M_1%
1 2
VS
12
PC5
0.1UF_50V
84
3
+
1
2
12
-
PU1A
LM393M
12
PR9
10K
RTCVREF
(3.3V)
12
PR2
10K
12
PZD1
RLZ4.3B
12
1 2
PR7
10K
PR4
1K
ACIN <17,30,42>
PACIN <40,41>
ACIN
Precharge detector
16.6 15.9 15.2
13.48 12.93 12.09
PR14
1M_1%
12
PU1B
84
LM393M
5
+
6
-
12
0.1UF_16V
PC12
PR17
10K
12
RTCVREF
(3.3V)
PQ2
2N7002
12
PR20
215K_1%
13
2
PQ3
DTC115EUA
B++
12
12
PR15
499K_1%
PR18
499K_1%
13
100K
100K
12
PR22
47K
2
BAT ONLY
Precharge detector
8.597 8.247 7.904
6.310 6.101 5.683
PC8
1000PF_50V
PACIN
12
+5VALWP
12
EC10QS04
P1
PD1
PC1
1000PF_50V
B++
VIN
PD3
IN4148
PQ1
TP0610T
13
2
CHGRTCP
PR23
200_0805
CHGRTCP+
2
2
PC13
1UF_0805_25V
PCN1
3
3
1 1
4
4 2
SIN-2DC-S726B201
VIN
2 2
VMB_A<41>
VMB_B<41>
CHGRTCP
EC_PWR_ON#<33>
3 3
CHGRTC
1 2
*
*
1 2
PR21
22K
PR24
200
1
2 1
PD2
IN4148
1
2
PZD2
RLZ4.3B
RTCVREF
1
2
VIN+
PD4
RB715F
3
12
12
PR19
100K
3.3V
PC14
10UF_1206_10V
PR8 1K_1206
PR10 1K_1206
PR11 1K_1206
PR12 1K_1206
VS+
12
PC10
0.22UF_1206_25V
PU2
S-81233SG(SOT-23-5)
3
3
1
1
PL1
FBM-L18-453215-900LMA 90T_1812
1 2
PC2
100PF_50V
21
VIN++
PR16
33_1206
12
0.1UF_0805_25V
PC11
2 1
PZD4
RLZ16B
VS
PC3
1000PF_50V
VIN
PC4
100PF_50V
MAINPWON<5,42,43>
1
ACON<40,41>
2
PD5
RB715F
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SCHEM A T IC, M/B LA-1381
Size Document Nu mber Re v
B
401212 2B
Date: Sheet
星期一 十二
30, 2002
月
D
of
37 46,
Page 38
A
B
C
D
1 1
PQ4
SI4835DY
ACOFF#
8
7
5
PD6
1SS355
1 2
PR33
10K
1 2
VIN
12
PR26
10K
ACOFF#
PACIN<39,41>
2 2
ACON<39,41>
IREF=1.31 * Icharge
IREF=0(0.73)~3.3V
IREF<30>
P2 P3
PQ5
SI4835DY
1
1
2
2
3 6
36
12
4
PR27
200K
L_1
12
PR31
150K
13
D
PQ8
2N7002
2
G
S
PC20
0.1UF_16V
PR39
140K_1%
1 2
8
7
5
4
2.22V
12
12
PR35
19.1K_1%
PR43
100K_1%
ADI_P<30>
12
PR34
24K_1%
12
PC23
0.1UF_16V
12
12
PC27
0.1UF_16V
APL11 APL10
PR35
12.7K_1%19.1K_1%
(5.0V)
Iadp=0~4.5A
PR25
0.02_2512_1%
12
PR32 10K
PR36 10K
1 2
1 2
PC21 4700PF_50V
1 2
1 2
PC24 2200PF_50V
PR41 10K
12
PR37 10K
12
PU3 MB3878
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
FB2
6
VREF
7
FB1
8
-INE1
9
+INE1
10
OUTC1
11
OUTD
12
-INC1
B+
FBM-L18-453215-900LMA 90T_1812
1 2
PR30
0
1 2
24
+INC2
23
GND
22
CS
21
VCC(o)
20
OUT
VH
19
VH
18
VCC
1 2
17
RT
16
-INE3
1 2
15
FB3
14
CTL
13
+INC1
PL2
L_3
PC22
0.1UF_50V
1 2
PR38
68K
PR42
47K
0.1UF_0805_25V
1 2
PC26 1500PF_50V
1 2
1 2
PR203 1K
*
PC18
0.022UF_25V
1 2
1 2
PC19
0.1UF_0805_25V
PC25
PR210
0
12
12
PC15
10UF_1210_25V
CHR_G
ACON
12
PR44
100K
B++
PQ6
SI4835DY
1
L_2
ACOFF#
1 2
0.02_2512_1%
PR40
2
3 6
1 2
PR28
10K
13
100K
100K
12
PC16
0.1UF_0805_25V
13
2
G
PQ58
2N7002
FSTCHG_EN#<41>
578
LXCHRG
12
D
S
12
PC17
@1000PF_50V
36
241
PQ7
SI4835DY
PL3
22UH_SPC_1205P_220A
1 2
PD8
EC31QS04
8
7
5
4
PR29
47K
1 2
2
PQ9
DTC115EKA
ACOFF <30>
CC=2.7A +-10%
CV= 1 2 . 6 V(9 CE LLS)
12
PC28
PC29
10UF_1210_25V
4.7UF_1210_25V
VIN
BATT+
12
3 3
4 4
+INE2 2.22V 1.73V
10UF_1206_10V
A
PR48
0
PC32
12
PR45
51K_1%
VS
12
PC30
0.1UF_50V
PU4A
84
LM358A
3
+
1
2
PU4B
LM358A
7
-
L_L18
5
+
6
-
12
L_L19
+2.5VPSDREF
12
PR47
100K_0.5%
12
PR49
100K_0.5%
PC31
0.1UF_16V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
(4.2V)
C
12
PR46
102K_1%
CHARGE < 43>
Compal Electronics, Inc.
Title
SCHEM A T IC, M/B LA-1381
Size Document Nu mber Re v
B
401212 2B
Date: Sheet
星期一 十二
?30, 2002
D
of
38 46,
Page 39
A
VMB_A
ALI/NIMH#
AB/I
12
TS_A
@BAS40-04
PC33
1000PF_50V
PD9
3
FBM-L18-453215-900LMA 90T_1812
12
12
PR54
PR55
100
100
1
2
2
12
EC_SMD1
EC_SMC1
PD10
1
@BAS40-04
3
PL4
BAT_LA BAT_LB
12
PR50
1K
EC_SMD1 <15,30,31>
EC_SMC1 <15,30,31>
PCN2
1 1
*
@BTD-09JR1
1
2
3
4
5
6
7
8
9
VMB_A <39>
12
PC35
0.01UF_50V
8
7
5
B
PJP9
PAD-OPEN 4x4m
1 2
PQ10
@FDS4435
P5
1
2
36
4
L_4 L_5
1 2
PR58 @22K
13
2
PQ14
@HMBT2222A
PR60
@10K
12
13
PJP10
PAD-OPEN 4x4m
1 2
PQ11
@FDS4435
1
2
3 6
12
4
PR52
@39K
PD11
@IN4148
1 2
BATT+
8
7
5
C
VMB_B<39>
4
1 2
PR59 @22K
PQ15
@HMBT2222A
PR61
13
1
2
36
2
@10K
P4
13
12
PQ12
@FDS4435
8
7
5
PQ13
@FDS4435
1
2
3 6
12
4
@0.01UF_50V
PR53
@39K
PD12
@IN4148
1 2
VMB_B
PL5
8
7
5
PC36
EC_SMD2<5,30,35>
EC_SMC2<5,30,35>
@FBM-L18-453215-900LMA 90T_1812
PR51
12
@1K
EC_SMD2
PD13
@BAS40-04
12
12
12
PR56
@100
EC_SMC2
1
3
2
PR57
@100
12
PC34
@1000PF_50V
BLI/NIMH#
BB/I
TS_B
12
1
PD14
@BAS40-04
3
2
PCN3
1
2
3
4
5
6
7
8
9
@BTD-09JR1
D
2 2
PCN4
BTD-09JR1
ACON<39,40>
1
2
3
4
5
6
7
8
9
PR72
1 2
270K
+5VALWP
PU5
@74HC253
PC38
@0.1UF_16V
16
VL
12
9
1Y72Y
VCC
1C061C151C241C332C0102C1112C2122C313S014S121EN12EN
8
GND
15
2
1 2
VL
12
PR68
@100K
1 2
PR71 @4.7K
PR62
@10K
100K
100K
1
PQ16
@DTC115EKA
VS
PU6A
84
@LM393M
3
+
2
-
GB<43>
12
PC37
@0.01UF_50V
PR70
@100K_1%
1 2
FSTCHG_EN#<40>
100K
100K
S1
VL
12
PR78
@100K
S0
13
1 2
PR81 @4.7K
PQ18
3 3
DTC115EKA
FSTCHG<30>
4 4
13
100K
2
100K
A/B#USE<30>
PR75
@100K
1 2
1 2
PR79
@100K
2
PQ19
@DTC115EKA
PR74 @5.6M
7
1 2
PR84 @5.6M
1 2
+
-
@DTC115EKA
PU6B
@LM393M
5
6
PQ20
RTCVREF
12
PR76
@10K
12
PC41
@1000PF_50V
13
100K
2
100K
GB
1 2
3.3V
PR80
@100K_1%
PR88
@47K
PD19
@IN4148
100K
2
PR63
@10K
12
12
12
100K
VMB_B
12
PR67
@1M_0.5%
12
PR73
@499K_1%
VMB_A
12
PR77
@1M_0.5%
12
PR82
@499K_1%
PQ17
@DTC115EKA
12
PC39
@100PF_50V
12
PC40
@100PF_50V
PACIN <39,40>
TRICKLE <30>
ALI/NIMH#<30>
8 CELLS BATTERY UVP
H 8.0V L 7.2V
BLI/NIMH#<30>
ALI/NIMH#
BLI/NIMH#
PR69
1K
PR87
@1K
+5VALWP
+3VALWP
12
PR65
47K
PD15
1
1
@BAS40-04
PD17
@BAS40-04
3
2
+3VALWP
3
2
12
12
PR85
@47K
12
3
2
3
2
1 2
PD16
@BAS40-04
1 2
PD18
@BAS40-04
PR64
25.5K_1%
1
PR83
@25.5K_1%
1
TS_A
12
PR66
1K
BATT_TEMPA<30>
TS_B
12
PR86
@1K
BATT_TEMPB<30>
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SCHEM A T IC, M/B LA-1381
Size Document Nu mber Re v
B
401212 2B
Date: Sheet
星期一 十二
30, 2002
月
D
of
39 46,
Page 40
A
B++
1 1
12
PC45
0.1UF_0805_25V
12
PC46
PC47
2200PF_50V
10UF_1210_25V
D1
S1
D2
7
S2
8
+3.3V Ipeak = 6.66A ~ 10A
12
12
PL6
SLF12565T_100M
12
PC58
21
21
150UF_D_6.3V_FP
21
21
21
0.012_2512_1%
12
+
2 1
+3VALW
+5VALW
+12VALW
+1.2VP
+2.5V
+1.25VS
PR94
PD22
EP10QY03
1 2
10K
PR102
1 2
(5A,200mils ,Via NO.= 10)
(5A,200mils ,Via NO.= 10)
(120mA,20mils ,Via NO.= 1)
(100mA,20mils ,Via NO.= 1)
(3A,120mils ,Via NO.= 6)
(3A,120mils ,Via NO.= 6)
(3A,120mils ,Via NO.= 6)
(3A,120mils ,Via NO.= 6)
+1.25VS_VGA
(3A,120mils ,Via NO.= 6)
2 2
+3VALWP
3 3
+5VALWP
+12VALWP
+1.2VPP
+1.8VALWP +1.8VALW
+1.5VP +1.5VS
4 4
+2.5VP
+1.25VP
+1.25VS
+3VALWP
12
+
PC57
150UF_D_6.3V_FP
1 2
PJP1 PAD-OPEN 4x4m
1 2
PJP4 PAD-OPEN 4x4m
PJP6 JOPEN/2MMA
PJP8 JOPEN/2MMA
1 2
PJP2 JOPEN/3MMA
1 2
PJP3 JOPEN/3MMA
PJP5 JOPEN/3MMA
PJP7 JOPEN/3MMA
PJP11 JOPEN/3MMA
A
PC55
47PF_50V
PR95
1M
1 2
12
PC59
3.57K_1%
PR99
33PF_50V
FB3_L
PQ21
FDS6982S
45
G1
36
2
G2
1
ACIN<17,30,39>
B
PC44
0.1UF_0805_25V
1 2
DH3
1 2
LX3
DL3
B
PR90
0
CSH3
1 2
PR98
10K
PR100
@300K
VS
12
PR106
47K
12
PC65
0.047UF_50V
BST31
12
PD21
1
12
12OUT
VDD
BST5
PGND
CSH5
CSL5
SEQ
SYNC
RST#
DH5
DL5
FB5
REF
LX5
3
VL
PC49
4.7UF_1206_16V
4
5
18
16
17
19
20
14
13
12
15
9
6
11
C
BST51
VL
+12VALWP
12
PC54
4.7UF_1210_25V
BST51+
L_51
PR104
@0
1 2
PR107
0
MAINPWON <5,39,43>
2.5VREF
12
PC60
4.7UF_1206_16V
12
PC48
0.1UF_0805_25V
1 2
PR92
0
1 2
VL
PU17B
LM358AMX_SO8
7
+1.5VS
PC147
4.7U_1206_16V
+
-
1 2
FB5_L
5
6
VS
PD40
1SS355
1 2
DAP202U
2
VS_L+VS_L++
12
PR91
10_1206
12
PC53
0.1UF_0805_25V
22
12
V+
PU7
MAX1632
21
VL
GND
8
VL
25
BST3
L_6
27
DH3
26
LX3
24
DL3
1
CSH3
2
CSL3
3
FB3
10
SKIP#
23
SHDN#
7
TIME/ON5
28
RUN/ON3
12
PC63
680PF_50V
RUN
PR105
47K
MAINPWON
12
PC66
0.047UF_16V
M7C
+1.25VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
12
PC50
2200PF_50V
PR93
0
PQ60
SI3442DV_TSOP6
D
6
2
1
D
B++
PC51
S
G
3
D
1 2
PC43
470PF_0805_100V
12
PC52
0.1UF_0805_25V
DH5
LX5
DL5
CSH5
12
PC64
33PF_50V
45
PU17A
LM358AMX_SO8
1
PC151
68P_0603_50V8J
12VDD
10UF_1210_25V
PR103
10K
84
3
+
2
-
E
PC42
4.7UF_1210_25V
1 2
12
7
8
1 4
SDT-1205P-100
12
PC56
47PF_50V
12
PR96
2M
2 1
PD20
EC11FS2
PT1
12
3 2
12
PR97
0.012_2512_1%
12
+
+
PC61
150UF_D_6.3V_FP
PR89
22_1206
D1
4 5
G1
3 6
D2
2
G2
1
PQ22
FDS6982S
12
PR101
10.5K_1%
12
FLYBACKSNB
12
S1
S2
PD23
EP10QY03
+5V Ipeak = 6.66A ~ 10A
+5VALWP
PR217
PR216
1 2
12
PC148
.1U_0603_50V4Z
1 2
PR220 5.1K_0603_5%
Title
Size Docu ment Number Re v
B
Date: Sheet
1 2
0_0603_5%
5.1K_0603_5%
PC149
220P_0603_50V8J
1 2
PC150
1000P_0603_50V7K
Compal Electronics, Inc.
SCHEM A T I C , M /B LA-1381
401212
星期一 十二
?30, 2002
97.6K_0603_1%
PR219
33K_0603_1%
+
PR218
E
*
47UF_D_6.3V_PC
PC62
+1.25V+-5%
PC146
47U_6.3V_M
12
VL
40 46,
+5VALWP
+1.25VS_VGA
of
2B
Page 41
A
B
C
D
PTH1 under CPU botten side :
CPU thermal protection at 84(85)+-3 degree C
Recovery at 36(37)+-3 degree C
1 1
PTH2 near main Battery CONN :
BAT. thermal protection at 90(91)+-3 degree C
Recovery at 39(40)+-3 degree C
3.3V
RTCVREF
*
PC139
0.1UF_50V
CPU
PR111
3.65K_1%
L_L1
2 2
0.1UF_16V
PC70
L_7
PTH1
10K_1%
PR117
19.1K_1%
PR108
100K_1%
PR115
1K_1%
1000PF_50V
PC71
L_L2
PC69
L_L4
RTCVREF
L_8
PR114
3.65K_1%
PTH2
10K_1%
PR118
18.2K_1%
PR116
1K_1%
PC67
0.1UF_16V
REV
L_L5
PR113
47K_1%
5
6
<40>
CHARGE
VS
PR109
10K
84
+
7
-
PU8B
LM393M
PR120
470K
L_L6
PZD6
RLZ3.6B
21
1SS355
PD25
PC74
0.1UF_16V
12
OTP
CHARGE
13
100K
PQ56
DTC115EKA
100K
2
PQ23
DTC115EKA
<5,39,42>
Battery
0.1UF_16V
MAINPWON
VS
PC68
21
PZD5
RLZ3.6B
0.1UF_50V
PD24
1SS355
PC72
0.1UF_16V
12
100K
OTP
2
PC73
@1000PF_50V
MAINPWON
13
100K
PR110
47K_1%
84
3
REV
PR121
249K_1%
+
2
-
PU8A
LM393M
1
PR119
PR112
10K
L_L3
470K
APL10 PR117 18.7K
PTH1 under CPU botten side :
Please refer to Page. 45
CPU thermal protection at 87(88)+-3 degree C
BATTER Y Char ger OVP : 13. 56V
PR122
36K_1%
L_L8
PC76
VIN
1
ACOFF#
3 3
GB<41>
13
@2N7002
13
@2N7002
2
PQ24
2
PQ25
PR129
100K_1%
L_L7
PR125
309K 1%
1UF_1206_25V
Recovery at 37(38)+-3 degree C
APL10 PR118 19.1K
PTH2 near main Battery CONN :
BAT. thermal protection at 84(85)+-3 degree C
Recovery at 36(37)+-3 degree C
VS
12
PC75
0.1UF_50V
84
3
+
2
-
PU11A
LM393M
PR124 0
L_L9 L_L10
PR126
100K
2.5VREF
PC77
1UF_0805_16V
BATT+
PR123
1M_0.5%
PR127
@100K_0.5%
PR128
226K_1%
APL10 nonpop components for cpu_core
PU15;PQ51;PQ52;PQ54;PQ55;PD39;PD38;PL14;PC130;
PC132;PC133;PC131;PC134;PC135;PC129;PC128;
PR193;PR194;PR196;PR199;PR197;PR192;PR195;
PR200;PR198,PR223
APL11 nonpop components for mobile
PR171,PR172,PQ42,PR177,PQ43,PQ44,PR207,PR184,
PQ49,PR204,PQ59,PR205,PQ50
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SCHEM A T IC, M/B LA-1381
Size Document Nu mber Re v
B
401212 2B
Date: Sheet
星期一 十二
30, 2002
月
D
of
41 46,
Page 42
A
D
S
+5VALWP
12
PR132
PC84
+3VALWP
12
12
0_1206
2.5VDD
PD26
RB751V
1 2
1 2
PR136
12
31
PR142
0_1206
PD29
RB751V
PC96
2200PF_50V
PQ36
2SA1036K
1K
2
PQ28
HMBT2222A
2
1.8VDD
1 2
1 2
PR147
12
1K
31
2
13
L_L11
PQ33
HMBT2222A
2
12
PR135
10K
PU9B
LM393M
13
L_L15
1 1
12
PC82
10UF_1210_25V
2200PF_50V
PQ29
2SA1036K
2 2
PC94
10UF_1206_10V
3 3
4 4
4 5
G
3
D
S
4 5
G
PQ27
3
SI3445DV
L_9
7
12
PR146
10K
PU9A
LM393M
6
PQ26
2
@SI3445DV
1
6
2
1
5
+
6
-
PQ32
SI3445DV
D
S
4 5
G
3
EC31QS04
L_10
84
+
1
-
12
PD27
EC31QS04
L_L13
4700PF_50V
6
2
1
PD30
VS
3
2
PR153
43K_1%
LX2.5
L_L12
PC88
LX1.8
12
0.1UF_50V
12
PC99
1 2
1 2
4.7UH SPC-1205P-4R7A
12
PR133
@2M
12
PC85
@0.1UF_16V
12
PL9
5UH SPC-06704-5R0
1 2
12
PR143
@2M
12
PC95
@0.1UF_16V
1.8V
12
PR154
215K_1%
PL7
13
100K
PR144
191K_1%
L_L16
PC103
0.01UF_50V
12
PR134
191K_1%
1 2
PR137
47K
100K
2
PQ30
DTC115EKA
12
1 2
PR152
100K
PR208
@47K
*
B
(+2.5V +-5%)
+2.5VP
+2.5VP
12
12
12
+
PC80
470PF_0805_100V
2.5VREF
VS
12
SYSON# <38>
L_L14
(+1.8V+-5%)
+1.8VALWP
12
PC92
2200PF_50V
2.5VREF
12
+
PC81
220UF_D_4V_FP
PC93
150UF_D_6.3V_FP
+2.5VP
SUSP#<21,30,35,38>
PR130
0_1206
+2.5VP
12
1 2
PR138 100K
2
PQ31
DTC115EUA
PC100
1 2
0.1UF_0805_25V
12
4.7UF_1206_16V
100K
100K
+3VALWP
12
PR145
0_1206
12
10UF_1206_10V
PC102
2200PF_50V
PQ37
2SA1036K
PR131
10_1206
PC78
PC83
13
+2.5VDD
PR141 @0
1.5VDD
PD31
RB751V
1 2
1 2
PR151
12
1K
31
2
12
12
12
PC91 1000PF_50V
PQ35
HMBT2222A
2
C
+2.5VCC
PU10
CM8500IT
1
VCC1
2
PVDD1
3
VL1
4
PGND1
5
AGND1
6
SD
7
VIN/2
8
AGSEN
VCC2
PVDD2
PGND2
AGND2
VFB
VCCQ
AGND
16
15
14
VL2
13
12
11
10
9
PC79
1 2
0.1UF_0805_25V
LX1.25
12
PC86
4.7UF_1206_16V
+2.5VP
12
PC90
0.1UF_0805_25V
1 2
PC89
1000PF_50V
PL8
5UH SPC-06704-5R0
12
PR139
100K
12
12
PR140
1K
Layout : "Compensation network close to FB pin"
PC152
PC97
2200PF_50V
PR221
100K_1%
0.01UF_50V
(+1.5V+-5%)
+1.5VP
12
12
12
13
SUSP
L_L17
12
SUSP
PR150
10K
7
PQ34
SI3445DV
D
S
4 5
G
3
L_11
84
+
-
PU11B
100K
2
PQ61
DTC115EKA
6
2
1
PD32
EC31QS04
5
6
LM393M
100K
PL10
5UH SPC-06704-5R0
LX1.5
1 2
12
12
PR148
@2M
12
PC101
@0.1UF_16V
L_LTT
13
PR222
162K_1%
191K_1%
1 2
12
PR149
12
D
(+1.25V+-5%)
+1.25VP
12
+
+
PC98
150UF_D_6.3V_FP
2.5VREF
PC87
220UF_D_4V_FP
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SCHEM A T IC, M/B LA-1381
Size Document Nu mber Re v
B
401212 2B
Date: Sheet
星期一 十二
30, 2002
月
D
of
42 46,
Page 43
A
VID_VCC
+3VALWP
1 1
VR_ON<30,38>
PR155
0
PC104
4.7UF_1206_16V
CPU_ON
VR_ON
1.2VDD +1.2VPP
12
PC105
0.068UF_16V
PR158
0
SWC13V<16>
CPU_VID4<7>
CPU_VID3<7>
CPU_VID2<7>
CPU_VID1<7>
PR176
PC132
0
10
0
CPU_VID0<7>
VGATE<33>
CPU_ON
PC116
1UF_0805
PC122
4700PF_50V
PC127
4700PF_50V
PC130
4700PF_50V
DPRSLPVR
0
0
0
0
1
+3VALWP
PR175
150K_1%
0.1UF_0805_25V
PR185
200
1 2
1 2
1 2
1 2
PR193
200
1 2
1 2
PR196
200
1 2
PR199
200
1 2
PC121
PR187
200
PR189
200
PR191
200
PR194
200
180K_1%
4700PF_50V
+2VREF
2 2
+2VREF
*
PR179
48.7K_1%
PR181
20K_1%
3 3
4 4
GMUXSEL STPCPU# VCORE
PM
PM D-S
11
1
BM
BM D-S
Deeper
00
X
A
PC138
@1000PF_50V
CM1+
CM1+
PC133
470PF_50V
VCORE'
1.30V 0%
1.20V 2.0%
1.0V
B
PU12
4
2
8
SI91822DH-12-T1
PR161 0
PR163 100K
PR166 100K
PR167 100K
PR169 100K
PR170 0
PR173 120K
CPUVDD
PC115 47PF_50V
PC117
1UF_0805
+2VREF
*
PR178
100K_1%
PR180
*
53.6K_1%
PR201
@0
PC125
PR190
470PF_50V
1K_1%
PR197 1K_1%
Offset
4.62%
4.62%
B
VIN
VOUT
SENSE
DELAY
ERROR7CNOISE
ON/OFF#
GND
12
12
12
12
12
12
ILIM
PC118
1000PF_50V
1
ILIM
2
TRIG
3
CM+
4
CM-
5
CS-
6
CS+
7
COMP
8
GND
1
ILIM
2
TRIG
3
CM+
4
CM-
5
CS-
6
CS+
7
COMP
8
GND
0%
5
6
1
3
1 2
PR159 0
PU13 MAX1718
21
D4
22
D3
23
D2
24
D1
25
D0
14
VGATE
3
TIME
2
SDN/SKIP
17
VDD
6
CC
20
OVP
11
REF
12
ILIM
GND15TON
PU14
MAX1887
PR202 0
PU15
MAX1887
1.30V
1.2309V
1.176V
1.144V
1.0V
LIMIT
VDD
PGND
LIMIT
VDD
PGND
+5VALWP
ZMODE
V+
BST
LX
DH
DL
V+
BST
LX
DH
DL
C
12
LX
DH
BST
DL
V+
VCC
FB
POS
NEG
SUS
S1
S0
C
PC106
1000PF_50V
27
28
26
16
1
9
4
13
5
19
18
8
7
10
16
15
14
13
12
11
10
9
L_16
16
15
14
13
12
11
10
9
PR157
@10K_1%
2.2
L_12
1 2
L_19
PR164
CPUVCC
PR182 33K_1%
L_13
L_15
CPUVDD
2 1
PR192 33K_1%
L_17
CPUVDD
PC134
1UF_0805
PR156
0
PR160
20
1 2
*
PC113
4.7UF_0805_10V
PM_DPRSLPVR_R
L_14
PC123
0.1UF_0805_25V
PD37
1SS355
PC126
1UF_0805
ILIM
PC131
0.1UF_0805_25V
L_18
2 1
21
PD33
1SS355
0.1UF_0805_25V
PR223
0@DT
ILIM
PD38
1SS355
D
+1.2VPP
12
PC107
4.7UF_1206_16V
CPU_GH1
PQ38
IR7811A
CPU_LX1
PC110
0.1UF_0805_25V
CPU_B+
PC112
CPU_GL1
CPU_FB
POS
CPU_LX2
1 2
PR188
*
2.2
CPU_GL2
*
PR195
2.2
CPU_LX3
CPU_GL3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
12
CPU_GH2
SI4362DY
PQ45
IR7811A
IR7811A
CPU_GH3
PQ40
PQ51
PQ54
SI4362DY
CPU_B+
578
3 6
241
578
3 6
578
3 6
241
578
3 6
578
3 6
578
241
241
241
3 6
E
CPU_B+
IR7811A
SI4362DY
CPU_B+
IR7811A
PQ47
SI4362DY
241
E
PQ39
PQ41
PQ46
CPU_B+
PQ52
IR7811A
PQ55
SI4362DY
10UF_1210_25V
578
3 6
241
578
3 6
241
578
3 6
241
578
3 6
241
578
3 6
241
578
3 6
241
PC108
PR165
68_0805
1000PF_50V
PQ48
SI4362DY
4.7UF_1210_25V
PC109
4.7UF_1210_25V
PC140
@10UF_1210_25V
*
SSC-1255-0R5
PD34
EC31QS04
2 1
12
PC111
220PF_50V
PC114
PC119
4.7UF_1210_25V
PR186
68_0805
12
PC124
220PF_50V
PC128
@10UF_1210_25V
PM_DPRSLPVR<16>
PR200
68_0805
12
PC135
220PF_50V
F
*
PC141
@10UF_1210_25V
PL12
1 2
PR174
100
SSC-1255-0R5
2 1
PC143
CM1+
PR168
2.8K_1%
PC142
@10UF_1210_25V
*
PC120
10UF_1210_25V
PL13
PD36
EC31QS04
**
@10UF_1210_25V
PL14
SSC-1255-0R5
PD39
EC31QS04
2 1
F
12
+
PC136
@100UF_EC_25V
PR162
0.002_2512_1%
CM2+
PC144
PM_DPRSLPVR
CM3+
G
PL11
FBM-L18-453215-900LMA 90T_1812
12
+
PC137
@100UF_EC_25V
1 2
PR212
0_0603_5%
+CPU_CORE
12
PD35
EC31QS04
2 1
PR171
49.9K_1%
PM_STPCPU# <14,16>
PR183
0.002_2512_1%
+CPU_CORE
12
PM_GMUXSEL<16>
PC129
10UF_1210_25V
PR205
100K
PR198
0.002_2512_1%
+CPU_CORE
12
Compal Electronics, Inc.
Title
SCHEM A T IC, M/B LA-1381
Size Docu ment Number Re v
B
401212 2B
Date: Sheet
星期一 十二
G
+CPU_CORE
PR172
68K_1%
PQ43
13
D
2N7002
2
G
S
2
G
PR207
100K
2
G
PM_DPRSLPVR_R
NB/DT#_CPU<7,31>
?30, 2002
B++
PC145
0.1U
+5VALWP
PR204
100K
PR214
2K_0603_1%
PR215
1K_0603_1%
PR177
100K
13
D
S
13
D
PQ59
2N7002
S
2
G
PR206
@100K
+5VALWP
MAX4322EUK-T_SOT23-5
5
+
1
-
2
12
12
D
S
PQ44
2N7002
+5VALWP
13
D
2
G
S
13
D
PQ50
S
2N7002
PU16
3
4
1K for MB P4 CPU.
2K for DT P4 CPU.
PQ42
13
2N7002
2
G
PR184
100K
PQ49
2N7002
2
G
PQ53
@2N7002
PQ57
@2N7002
H
PR211
499_0603_1%
PR213
1K_0603_1%
13
D
S
13
D
2
G
S
of
43 46,
H
CM1+
12
+CPU_CORE
12
Page 44
10
9
8
7
6
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
H H
Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem
G G
F F
E E
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
30, 2002
Date: Sheet
月
2
of
44 46,
1
2B
Page 45
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Version change list (P.I.R. List) Page 1 of 2
H H
Reason for change PAGE Mod ify ListFixed IssueItem
1 Footprint error 4 Change R9 6 footprint to 0402
5 Change RP6 footprint to 0402
7 Change RP 8, RP86 , RP87 , R P89 and RP90 footprint to 0402
2 7 Change RP9 1 footprint to 0402
M.B. Ver.
0.2
G G
2
Power saving
6 Change C190.1, R292. 2, R434.2 and U27.8 connect from +12VALW to +12VS
0.2
Change D16.1, D13.1, Q23.1 and Q24.1 connect from +5VALW to +5VS
Change R433.1 and R220.1 connect from +3V to +3VS
3
No design requirement 7 Delet e U10 and C178 0.2
Delete RP717
F F
Delet e C6 21 and C62321
Delete J8, C611, C612, L55 and L5722
4
5
E E
6
7
No requiremen t for VGA board
Divid er c ir cuit for U62( AC97 CODEC ALC201 )
Lost connected net for L59
Modify B ase I/ O A ddr ess fo r U48( SU PER I/O SMsC LPC47N227 )
15
Change JP3. 48 net fr om EC_PWR_ON# to N.C.
21 0.2
Add R503, R504, R507 and R508 6.8K
22
Connect L59.2 to LINECL_OUT_L
27
Change R491 value from 10K_0402 to @10K_0402
0.2
0.2
0.2
Change R135 value from @10K_0402 to 10K_0402
8
9
D D
10
11
12
C C
13
Solve Touch Pad no function issue
Prevent power leakage
Modify bright of D28
Solve D28 can't work iss ue
Solv e USB2 no function issue
Solve powe r on fail issue
30
Change RP82.3 net from TPAD_ON/OFF# to N.C.
30
Change RP80.3 net from M_SEN# to N.C.
Add R509 100K pull-hi gh to +3VS for M_SEN#
31
Change Q33. 3 net from +3VALW to+5VALW
31
Relayout for D28
31
Relayout for JP19
32
Delet e R183
0.2
0.2
0.2
0.2
0.2
0.2
Change R271 from 0_0402 to 68K_0402
14
15
B B
16
Modify net name for SW1
BIOS request for MDC
Modify USB application
32
Exchan ge VO L_IN_UP# and VOL_IN_DN#
35
Add R510 10K pull-d own to GND for JP24.108
17
Change R157.1 net from OVCUR#0 to OVCUR#5
0.2
0.2
0.2
Change R160.1 net from OVCUR#1 to OVCUR#3
Change R169.1 net from OVCUR#2 to OVCUR#4
31
Change L26.1 net from USBP1+ to USBP3+
Change L27.1 net from USBP1- to USBP3Add F5, C671, C672, C673, C674, R511, R512, L67, L68 and JP32
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
45 46,
1
2B
Page 46
10
9
8
7
6
5
4
3
2
1
Version change list (P.I.R. List) Page 2 of 2
H H
17 For M.E . request Add JP33, R513, R514, D42, D43 and Q62
G G
18 Disc harge circuit for +12V S and +2.5VS 36 Add R 515, R516, Q63 and Q64 0.2
19 For USB2.0 can't fast speed 2 6 Ch ang e L7 3, L75, L7 6,L 79 to 0_0603 0. 3
20 Signal H_THERMTRIP# Design change 5 Add R632 and Q76 0.3
21 Remove serial port c onnector 0.3
F F
22 Change M_SEN# R509 from 100K_0402 to 10K_0402 31 Change R509 from 100K_0402 to 10K_0402 0 . 3
23 For s ch ematic R568 711@ error 2 3 Chan ge R568 711@0_0402 to 6912@0_04 02 0.3
24 Change D28 to new part32
25 Add sub-woofer soluction 22 Add SUB@ 0.3
26 Add USB1.1 port 32 Add USB3 port 0.3
E E
D D
C C
27 6 A dd C75 1/C752/C753/C754/C746/C747/C234 0. 3
28 3 0 Change U24_pin162 to MAIL_LED#
29 Chang e audio amp power source 2 2 Cha nge +5VALW to V DDA 0.3
30 Change CD_AGND connect to AGND 21 Chang e from GND to GNDA 0.3
31 711 option cancel 23, 27 Del 711@ 0.4
32 Add EMI request(FAN) 6 Add C222/ C754/C753/C747 and change C746 to 220P 0.4
33 Add EMI request(HDD) 19 A dd R517/R518/C675/C676 0.4
34 SD co ntrol vender recommend 27 R149 change to 1M/Add 4.7K pull-down 0. 4
35 circuit update 3 0 JP27 pin10 change to MAIL_LED# 0.4
36 Add capacitance for audio noise 32,35,36 Add C758/C759/ C760/C761/C762/C763/C764/C765/C766/C767/C768 0 .4
37 Add POWER VGATE recommend 33 Add R665/ C757 0.4
38 Change ACL201 to ACL202 21 Change CLK inpu t to 14MHZ 0.4
39 Add crystal for ALC202 21 0.5Add Y2,R475,C468,C469 Del R492,R480
40 Power nois e issue 30 Chan ge C366 to @ 0.5
41 Customer request 3 2 Cha ng e D45 to Green LED 0.5
Reason for change PAGE Modify ListFixed IssueItem
15
Chang e JP 3.8 , J P3. 10, J P3. 94, JP3.96, JP2.84 and JP2.86 net to N.C.
Change JP3 .98 net from INVPWR_B+ to LVDS_BLON#
Add JP34
31
32 Change JP5 for new connector
U66 pin112 connector change to GNT#3,pin113 connector change to REQ#3
Change VL to +5VS
28 Add R633 and RP141
29 Cancel U4,C40,C1,C414,C415,C416,CP1,CP2 ,JP16
35 Update JP20 pin151,152,101,102,103,104, 105,106 Name
Add net RIA0
BT LED SPEC update 0.3
Add Fan EMI soluction
EC add MAIL_LED#
Add WL_LED
Add U24_pin24 EC_MUTEI#
M.B. Ver.
0.2
0.3
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
9
8
7
6
5
4
3
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1381
Size Docu ment Number Re v
401212
Custom
星期一 十二
Date: Sheet
?30, 2002
2
of
46 46,
1
2B
Page 47
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