Compal LA-1361 ADQ00, LA-1361 ADQ10 Schematic

A

1 1

B

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D

E

2 2

Compal Confidential

Schematics Document

P4 uFCBGA/uFCPGA Northwood with SIS Core Logic

2001-5-30

3 3

REV:1.0A

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ACT10

Cover Sheet

E

145Thursday, May 30, 2002

1.0A

of

A

Compal confidential

B

C

D

E

Block Diagram

Model Name :CT10
File Name : LA-1361

CPU Bypass

1 1

Fan Control

VGA
Board

page 6

& CPUVID

LM75 thermal
sensor

CRT Connector

page 16

AGP Conn

page 16

page 5

page 6

AGP4X(1.5V)

Mobile Northwood

uFCBGA/uFCPGA CPU

478pin
System Bus

400MHz

page 3,4,5

HD#(0..63)HA#(3..31)

SIS 650

BGA-702

page 7,8,9,10,11

Memory
BUS(DDR)

2.5V 200MHz

Thermal Sensor

MAX6654

page 4

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

Clock Generator

page 15

page 12,13,14

2 2

PCI BUS

MINI
PCI I/F

3 3

1394
Controller

TI TSB43AB22

page 25page 26

1394
Connector

page 25

LED INDICATE

page 36

Power On/Off
Reset & RTC

page 35

DC/DC Interface
Suspend

4 4

Power Circuit
DC/DC

page 38, 39,
40, 41 42, 43

page 37

A

LAN

RTL 8100L

page 22

RJ45

page 22

Ext. Board

SERIAL

IO PC87391

Legacy I/O Option

B

3.3V 33MHz

CardBus

ENE CB1410

2Eh-2Fh

Slot 0

page 24

FDDFIR

PARALLEL

page
23

page 32

MULTIO

Ext. Board

SIS 961

BGA-371

LPC BUS

3.3V 33MHz

page 17,18,19,20

NS PC87591S

LPC to X-BUS
& KBC

page 33

USB port 0, 1, 2

3.3V 48MHz

3.3V 24.576MHz

3.3V ATA100

HDD

page 21

USBx3

USB conn

page 27

AC-LINK

O2
OZ165

CD Player

page 29

CDROM

C

Touch Pad

page 36

page 35

page 21

D

EC I/O Buffer

page 34

BIOS Int.KBD

page 33

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

SD/MS Slot

page 28

USB port 3 USB port 4

Winbond
W81386D

page 28

AC97
Codec

ALC202

AMP& Phone
Jack

Title

Size Document Number Rev

Date: Sheet

BlueTooth I/F

page 27

page 30

page 31

Compal Electronics, Inc.

Block Diagram

ACT10

E

245Thursday, May 30, 2002

1.0A

of

A

B

C

D

E

HD#[0..63]<7>
HA#[3..31]<7>

1 1

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20

2 2

+CPU_CORE

HREQ#[0..4]

R23 10K_0402

1 2
1 2

HREQ#[0..4]<7>

HADS#<7>

HBR0#<7>

3 3

HBPRI#<7>

HBNR#<7>

HLOCK#<7>

CLK_HCLK<15>
CLK_HCLK#<15>

HIT#<7>

HITM#<7>

HDEFER#<7>

HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

R42 200_0402

AF22
AF23

M6
M3

M4
N1
M1
N2
N4
N5

R2

R3
U1
U3

R6
W1

U4
W2

AB1

H3
G1

AC1
AA3

AC3

H6
D2
G2
G4

K2
K4
L6
K1
L3

L2

T1
P3

P4
T2
P6
T4

V2

T5
V3
Y1

J1
K5
J4
J3

V5

F3
E3
E2

+CPU_CORE

A10

U1A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#

AP#0
AP#1
BINIT#
IERR#

BR0#
BPRI#
BNR#
LOCK#

BCLK0
BCLK1

HIT#
HITM#
DEFER#

+CPU_CORE

A12

A14

A16

A18

A20A8AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19B7B9

C10

C12

C14

C16

C18

C20C8D11

D13

D15

D17

D19D7D9

E10

VCC_0

VCC_1

VCC_2

VCC_3

VCC_4

VCC_5

VCC_6

VCC_7

VCC_8

VSS_0

H1H4H23
GND

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_61

VCC_62

VCC_63

VCC_64

VCC_65

Mobile

NorthWood

32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

H26

A11

A13

A15

A17

A19

A21

A24

A26A3A9

AA1

AA11

AA13

AA15

VSS_24

AA17

AA19

AA23

AA26

AA4

AA7

AA9

AB10

VSS_

AB12

AB14

AB16

AB18

AB20

AB21

AB24

AB3

AB6

AB8

AC11

AC13

AC15

AC17

AC19

AC2

AC22

AC25

AC5

VSS_51

AC7

AC9

AD1

AD10

AD12

AD14

AD16

AD18

VCC_81

VCC_82

VCC_83

VSS_52

VSS_53

VSS_54

AD21

AD23

AD4

VCC_84

VSS_55

VSS_56

AD8

F13

F15

F17

F19

F9

VCC_73

VCC_66

VCC_67

VCC_68

VCC_69

VCC_70

VCC_71

VCC_72

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

VCC_85

VCC_74

VCC_75

VCC_76

VCC_77

VCC_78

VCC_79

VCC_80

E12

E14

E16

E18

E20E8F11

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

NorthWood

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#[0..63]
HA#[3..31]

+CPU_CORE

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Mobile NorthwooduFCPGA

ACT10

345Thursday, May 30, 2002

E

1.0A

of

200_0402

12

+CPU_CORE

R238
@10K_0402

R242
@10K_0402

1 8
2 7
3 6
4 5

C254

12

12
12

12
12

12

56_0402

12

56_0402

12

56_0402

12

56_0402

12

200_0402

12

56_0402

12

56_0402

12

56_0402

12

56_0402

12
12

51.1_1%

12

+1.2VP

A

H_A20M#
H_SMI#
H_IGNNE#
H_STPCLK#
H_DPSLP#
H_NMI
H_INIT#
H_INTR

H_FERR#
H_PWRGD

H_RESET#

PM_CPUPERF#

12

R237
@10K_0402

H_BSEL0
H_BSEL1

12

R241
@10K_0402

Murata LQG21F4R7N00

L15

1 2

L16

1 2

ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK

ITP_PREQ#
ITP_PRDY#

ITP_BPM0
ITP_BPM1

H_THERMDA
H_THERMDC

A

+1.2VP

BSEL0 BSEL1

0 0
0 1
1 0

MurataLQG21F4R7N00_80mA
MurataLQG21F4R7N00_80mA

12

C10

+

33UF_D2_16V

R246

+CPU_CORE

R245

W=15mil

C255

.1UF_16V_0402_Y5V

1 2

U2

1
2
3
4
5
6
7
8 9

MAX6654MEE

NC

STBY

VCC

SMBCLK

DXP
DXN

SMBDATA

NC
ADD1

ALERT

GND

ADD0

GND NC

NC

NC

H_RS#0<7>
H_RS#1<7>
H_RS#2<7>

H_TRDY#<7>

H_A20M#<18>

H_FERR#<18>

H_IGNNE#<18>

H_SMI#<18>

H_PWRGD<7>

H_STPCLK#<18>

H_DPSLP#<18>

H_INTR<18>

H_NMI<18>

H_INIT#<18>

H_RESET#<7>

H_DBSY#<7>

H_DRDY#<7>

1 2

R236 56_0402

100
Resvd
Resvd
Resvd1 1

12

C17

+

33UF_D2_16V

H_VSSA

4.7K_0402

12

4.7K_0402

12

+5VS

R213

10K_0402

1 2

16
15
14
13
12
11
10

R211

1K_0402

1 2

+5VS

R210

1 2

1 1

+CPU_CORE

1 1

2 2

R306
R304
R303
R268
R244
R299
R269
R300

R305

R251 51.1_1%

R258

R308

Place resistor <100mils from
CPU pin

12

12

If used ITP port must depop

RP70 8P4R_1.5K

+CPU_CORE

3 3

4 4

+5VS

R252 51.1_1%

R262 51.1_1%
R249 51.1_1%

R272 51.1_1%

Thermal Sensor
MAX6654MEE

2200PF_50V_0603

R212 1K_0402

Address:1001_110X

B

AE11

AE13

AE15

AE17

AE19

AE22

AE24

AE26

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF26

U1B

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_131

VSS_132

VSS_133

VSS_134

VSS_67

VSS_135

VSS_136

VSS_137

VSS_138

J25J5K21

+CPU_CORE

F1

RS#0

G5

RS#1

F4

RS#2

AB2

RSP#

J6

TRDY#

H_A20M#

C6

1 2

AB23
AD25

AB25

AD6
AD5

AC6
AB5
AC4

AA5
AB4

AD20
AE23
AF25

AF3

AC26
AD26

R34

51.1_1%

B6
B2
B5

Y4

D1

E5

W5

H5
H2

B3

C4

A2

Y6

D4
C1
D5

F7
E6

A5

L24

P1

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCA
VCCSENSE
VCCIOPLL

NC7
NC8

ITP_CLK0
ITP_CLK1

COMP0
COMP1

VSS_129

F8

VSS_130

G21

G24G3G6J2J22

H_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLP#
H_INTR
H_NMI
H_INIT#
H_RESET#

H_BSEL0 TESTTHI8_10
H_BSEL1

H_THERMDA
H_THERMDC

H_THERMTRIP#

ITP_BPM0
ITP_BPM1
ITP_PRDY#
ITP_PREQ#

ITP_TCK
ITP_TDI

ITP_TMS
ITP_TRST#

H_VCCA
VCCSENSE
H_VCCIOPLL

CLK_ITPP
CLK_ITPP#

R41

51.1_1%
1 2

R_A

EC_SMB_CK2 <6,16,29,33>
EC_SMB_DA2 <6,16,29,33>

R_B

10K_0402

B

AF6

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

SKTOCC#

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

K24K3K6L1L23

L26L4M2

GTL Reference Voltage

Layout note :

1. Place R_A and R_B near CPU.

2. Place decoupling cap 220PF near CPU.(Within

12

500mils)

R297

49.9_1%

Trace width>=7mila

12

R298
100_1%

C399

1UF_10V_0603_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

VSS_75

VSS_146

AF8

B10

VSS_76

VSS_147

M22

M25M5N21

VSS_77

VSS_148

B12

B14

VSS_78

VSS_79

VSS_149

VSS_150

C

B16

B18

B20

B23

B26B4B8

C11

C13

C15

C17

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

Mobile

NorthWood

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

N24N3N6P2P22

VSS_160

P25P5R1

R23

R26R4T21

C398
220PF_50V_0402_NPO

C

GND

VSS_90

VSS_161

C19C2C22

VSS_91

VSS_162

B_PCIRST#<16,17,28,29,33,34>

MAINPWON<38,41,42>

C25C5C7C9D10

VSS_92

VSS_93

VSS_94

VSS_163

VSS_164

VSS_165

T24T3T6U2U22

+H_GTLREF1

VSS_95

VSS_166

VSS_96

VSS_167

U25U5V1

VSS_97

VSS_168

VSS_98

VSS_169

D

D12

D14

D16

D18

D20

D21

D24D3D6D8E1

E11

E13

E15

E17

E19

E23

E26E4E7E9F10

F12

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VID0

VID1

VID2

VID3

VSS_170

VSS_171

V23

VSS_172

VSS_173

V26V4W21

1 3

D

Q24
@2N7002

VSS_174

VSS_175

VSS_176

W24W3W6Y2Y22

2

G

S

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

Y25

Y5

R226

@300_0402

VID4

AE5

AE4

AE3

AE2

AE1

VL

R10
1 2
Q25

1 2

1

2

3

@3904

Q26

1
3

@3904

D

F14

F16

F18F2F22

F25

F5

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

PROCHOT#

VSSSENSE

VCCVID

NC5

NC6

AF4

AE21

AF24

CPU_VR_VID4 <5,43>
CPU_VR_VID3 <5,43>
CPU_VR_VID2 <5,43>
CPU_VR_VID1 <5,43>
CPU_VR_VID0 <5,43>

@470_0402

R225

1 2

2

@470_0402

GND

VSS_128

DP#0
DP#1
DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

NC1
NC2

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9

TESTHI10

GHI#

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

MCERR#

SLP#

VSSA

NC3
NC4

NorthWood

PROCHOT#<33>

H_THERMTRIP#

E

J26
K25
K26

+H_GTLREF1

L25

AA21
AA6
F20
F6
A22
A7

TESTTHI0_1

AD24
AA2

TESTTHI2_7

AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6

H_DSTBN#0

E22

H_DSTBN#1

K22

H_DSTBN#2

R22

H_DSTBN#3

W22

H_DSTBP#0

F21

H_DSTBP#1

J23

H_DSTBP#2

P23

H_DSTBP#3

W23

L5
R5

H_DBI#0

E21

H_DBI#1

G25

H_DBI#2

P26

H_DBI#3

V21

DBR#

AE25

H_PROCHOT#

C3
V6

H_SLP#

AB26

H_VSSA

AD22

VSSSENSE

A4

AD2
AD3

+1.2VP

Title

Size Document Number Rev

ACT10

Date: Sheet

All of these pin
connected inside

+CPU_CORE

R243 1K_0402

1 2

R260 1K_0402

1 2

R267 1K_0402

1 2

PM_CPUPERF#

H_DSTBN#[0..3]

H_DSTBP#[0..3]

H_DBI#[0..3]

R302 56_0402

1 2

C287
.1UF_16V_0402_Y5V

+5VS

R206
1K_0402

1 2

R261 200_0402

R518
470_0402

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_ADSTB#0 <7>
H_ADSTB#1 <7>

H_DBI#[0..3] <7>

12

+CPU_CORE

1 2
2

31

Q60
3904

PM_CPUPERF# <18>

+CPU_CORE

H_SLP# <18>
+CPU_CORE

H_PROCHOT#

Compal Electronics, Inc.

Mobile Northwood uFCPGA & Thermal sensor

445Thursday, May 30, 2002

E

of

1.0A

A

B

C

D

E

Layout note :

Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

1 1

2 2

3 3

+CPU_CORE

C99
10UF_6.3V_1206_X7R

+CPU_CORE

C97
10UF_6.3V_1206_X7R

+CPU_CORE

C289
10UF_6.3V_1206_X7R

+CPU_CORE

C103
10UF_6.3V_1206_X7R

+CPU_CORE

C359
10UF_6.3V_1206_X7R

+CPU_CORE

C330
10UF_6.3V_1206_X7R

+CPU_CORE

Please place these cap in the socket cavity area

C98

10UF_6.3V_1206_X7R

C77

10UF_6.3V_1206_X7R

C100

10UF_6.3V_1206_X7R

C96

10UF_6.3V_1206_X7R

C101

10UF_6.3V_1206_X7R

C56

10UF_6.3V_1206_X7R

Please place these cap on the socket north side

C411

10UF_6.3V_1206_X7R

C424

10UF_6.3V_1206_X7R

C383

10UF_6.3V_1206_X7R

C339

10UF_6.3V_1206_X7R

C416

10UF_6.3V_1206_X7R

C302

10UF_6.3V_1206_X7R

C421

10UF_6.3V_1206_X7R

C387

10UF_6.3V_1206_X7R

C311

10UF_6.3V_1206_X7R

Please place these cap on the socket south side

C347

10UF_6.3V_1206_X7R

C364

10UF_6.3V_1206_X7R

C422

10UF_6.3V_1206_X7R

C102

10UF_6.3V_1206_X7R

C67

10UF_6.3V_1206_X7R

C400

10UF_6.3V_1206_X7R

C319

10UF_6.3V_1206_X7R

C60

10UF_6.3V_1206_X7R

CPU_VR_VID1<4,43>
CPU_VR_VID2<4,43>
CPU_VR_VID3<4,43>
CPU_VR_VID4<4,43>

Layout note :

Place close to CPU power and
ground pin as possible
(<1inch)

+CPU_CORE

12

C276

+

220UF_D2_4V_15m

+CPU_CORE

12

C274

+

220UF_D2_4V_15m

+CPU_CORE

12

C34

.22UF_10V_0603_X7R

R224

1K_0402

12

C35

.22UF_10V_0603_X7R

.22UF_10V_0603_X7R

+3VS

12

182736

45

RP69
8P4R_1K

Used ESR 15m ohm cap total ESR=1.875m
ohm

12

C420

+

220UF_D2_4V_15m

12

C273

+

220UF_D2_4V_15m

12

C32

.22UF_10V_0603_X7R

12

C33

12

+

+

12

C46

.22UF_10V_0603_X7R

.22UF_10V_0603_X7R

C271
220UF_D2_4V_15m

12

C272
220UF_D2_4V_15m

12

C47

.22UF_10V_0603_X7R

CPU Voltage ID

12

+

12

+

12

12

C30

.22UF_10V_0603_X7R

C269
220UF_D2_4V_15m

C270
220UF_D2_4V_15m

12

C48

C49

.22UF_10V_0603_X7R

CPU_VID0 <4,43>CPU_VR_VID0<4,43>
CPU_VID1 <4,43>
CPU_VID2 <4,43>
CPU_VID3 <4,43>
CPU_VID4 <4,43>

12

C50

.22UF_10V_0603_X7R

1

C385

10UF_6.3V_1206_X7R

C337

10UF_6.3V_1206_X7R

PAD4

PAD-5.0X3.5

C358

10UF_6.3V_1206_X7R

1

B

PAD5

PAD-5.0X3.5

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass & CPU VID

ACT10

545Thursday, May 30, 2002

E

1.0A

of

C423
10UF_6.3V_1206_X7R

+CPU_CORE

C317
10UF_6.3V_1206_X7R

4 4

EMI Clip PAD for CPU

PAD1

1

PAD-5.0X3.5

C384

10UF_6.3V_1206_X7R

C335

10UF_6.3V_1206_X7R

PAD2

PAD-5.0X3.5

A

1

C360

10UF_6.3V_1206_X7R

C318

10UF_6.3V_1206_X7R

PAD3

PAD-5.0X3.5

5

4

3

2

1

D D

ITP_PWROK<35>

+5VS

53

R583 @100K_0402

+5VS

EC_PWROFF<34>

C C

1 2

POWERCUT

U68

1
2

@7SH08

R620

+5VS

C173

R126

@10K_0402

+5VS

.1UF_16V_0402_Y5V

1 2

U4A

14

1
2

7

4

0_0402

+3V

74HCT08

+5VS
POWER

3

U69

1

VCC

GND

2

3

RST

@MAX809_2.93V

R128

5.6K_0402

R584 @100K_0402

POWERCUT

R129
10K_0402

1 2

PM_PWROK <9,18>

U5

EC_SMB_DA2<4,16,29,33>

EC_SMB_CK2<4,16,29,33>

1

SDA

2

SCL

3

OS#

4

GND

@LM75CIMMX-5

Dectect PCB Thermal

+5VS

8

VCC

7

A0

6

A1

5

A2

Address:1001_000X

12

C84

.1UF_16V_0402_Y5V

R37 1K_0402

1 2

Fan1 Control circuit

+12VALW

2

D9
1N4148

1
3

+5VALW

2 1

D10
1SS355

2 1

C4
@1000PF_0402

1000PF_0402_X7R

+5VFAN

12

12

C744

C743

.1UF_16V_0402_Y5V

JP1

1
2
3

53398-0390

+3V

12

R8
10K_0402

FAN1_TACH <33>

12

B B

U60

LMV321_SOT23-5

+5V

5

1

EC_EN_FAN<33>

R431
13K_1%

+

12

4

3

-

2

12

R430

7.32K_1%

R7
10K_0402

21

D7
1N4148

3

Q4

2

2SA1036K

1

Q5

FMMT619

C8

2.2UF_16V_0805

1 2

A A

COMPAL Electronics,Inc

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

3

2

Title

LM75 Thermal sensor & Fan control

Size Document Number Rev

ACT10

Date: Sheet

645Thursday, May 30, 2002

1

of

1.0A

A

B

C

D

E

H_DSTBP#[0..3]<4>
H_DSTBN#[0..3]<4>

H_DBI#[0..3]<4>

HD#[0..63]<3>

1 1

2 2

3 3

A4XAVDD

.1UF_0402_X5R

+CPU_CORE

4 4

HREQ#[0..4]<3>

MurataBLM21A601S

C9

R229

20_1%
R240

113_1%

HA#[3..31]<3>

L2

1 2

H_DSTBP#[0..3]
H_DSTBN#[0..3]
H_DBI#[0..3]

HA#[3..31]
HREQ#[0..4]

CLK_GHT<15>

CLK_GHT#<15>

HLOCK#<3>
HDEFER#<3>
H_TRDY#<4>

H_RESET#<4>
H_PWRGD<4>

HBPRI#<3>

HBR0#<3>

H_RS#2<4>
H_RS#1<4>
H_RS#0<4>

HADS#<3>

HITM#<3>

HIT#<3>

H_DRDY#<4>

H_DBSY#<4>

HBNR#<3>

H_ADSTB#1<4>
H_ADSTB#0<4>

+3VS

C5
10UF_10V_1206

HNCOMP

Rds-on(n) = 10 ohm
HNCVERF = 1/3 VCCP

HPCOMP

Rds-on(p) = 56 ohm
HPCVERF = 2/3 VCCP

A

+3VS

C1XAVDD

CLOSE CHIP

C415

.1UF_0402_X5R

C4XAVDD

HVREF

HNCVREF

HNCOMP

HPCOMP

C1XAVSS

AH25

AJ25

AH27

AJ27

U21

T21

P21

N21

J17

B20

B19

A19A7F9B7M6M5M4L3L6L4K6L2K3J3K4J2J6J4J1H6F4F1G6E3F5E2E4E1D3D4C2F7C3E6B2D5D6A3D7C5A5C6D8

CPU_GHT
CPU_GHT#

HLOCK#
HDEFER#
H_TRDY#
H_RESET#
H_PWRGD
HBPRI#
HBR0#

HRS#2
HRS#1
HRS#0

HADS#
HITM#
HIT#
H_DRDY#
H_DBSY#
HBNR#

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

H_ADSTB#1
H_ADSTB#0

HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3

+CPU_CORE +CPU_CORE

R274

75_1%

R271
150_1%

AJ26

CPUCLK

AH26

CPUCLK#

U24

HLOCK#

U26

DEFER#

V26

HTRDY#

C20

CPURST#

D19

CPUPWRGD

T27

BPRI#

U25

BREQ0#

T24

RS#2

T26

RS#1

U29

RS#0

V28

ADS#

T28

HITM#

U28

HIT#

W26

DRDY#

V24

DBSY#

V27

BNR#

W28

HREQ#4

W29

HREQ#3

W24

HREQ#2

W25

HREQ#1

Y27

HREQ#0

AD24

HASTB#1

AA24

HASTB#0

AF26

HA#31

AE25

HA#30

AH28

HA#29

AD26

HA#28

AG29

HA#27

AE26

HA#26

AF28

HA#25

AC24

HA#24

AG28

HA#23

AE29

HA#22

AD28

HA#21

AC25

HA#20

AD27

HA#19

AE28

HA#18

AF27

HA#17

AB24

HA#16

AB26

HA#15

AC28

HA#14

AC26

HA#13

AC29

HA#12

AA26

HA#11

AB28

HA#10

AB27

HA#9

AA25

HA#8

AA29

HA#7

AA28

HA#6

Y26

HA#5

Y24

HA#4

Y28

HA#3

C349
.01UF_25V_0402_X7R

C343

.01UF_25V_0402_X7R

place this capacitor
under 650 solder side

C1XAVSS

C4XAVSS

C1XAVDD

C4XAVDD

HOST

HD#63

HD#62

HD#61

HD#60

HD#59

HD#58

HD#57

F19

A21

HD#62

HD#61

E19

D22

D20

HD#58

HD#60

HD#59

HVREF

C355
.1UF_0402_X5R

B

HD#56

B22

C22

B23

HD#57

HD#55

HD#56

B21

HD#63

HVREF0

HVREF1

HVREF2

HVREF3

HVREF4

HPCOMP

HNCOMP

HNCOMPVREF

HD#55

HD#54

HD#53

HD#52

HD#51

HD#50

HD#49

HD#48

HD#47

A23

D21

HD#53

HD#54

HD#46

F22

D24

D23

C24

B24

E25

E23

HD#47

HD#49

HD#51

HD#52

HD#50

HD#48

HD#46

AGP_AD2

AGP_AD0

AGP_AD6

AGP_ST2

AGP_AD1

AGP_AD7

AGP_AD5

AGP_AD3

AGP_ST0

AGP_AD4

AGP_ST1

ST0

ST1

ST2

VBD7/AAD0

VBD6/AAD1

VBD5/AAD2

VBD4/AAD3

VBD3/AAD4

VBD2/AAD5

CBD1/AAD6

AGP_AD14

AGP_AD11

AGP_AD9

AGP_AD16

AGP_AD10

AGP_AD8

VAD6/AAD8

VAD5/AAD9

CBD0/AAD7

AGP_AD17

AGP_AD13

AGP_AD12

AGP_AD18

AGP_AD15

VAD4/AAD10

VAD7/AAD11

VAD8/AAD12

VAD9/AAD13

VADE/AAD16

VAD10/AAD14

VAD11/AAD15

VAVSYNC/AAD17

650-1

HD#45

HD#44

HD#43

HD#42

HD#41

HD#40

HD#39

HD#38

HD#37

HD#36

HD#35

HD#34

HD#33

HD#32

HD#31

HD#30

HD#29

HD#28

HD#27

HD#26

HD#25

D25

A25

C26

B26

B27

D26

B28

E26

F28

G25

F27

F26

G24

H24

G29

HD#36

HD#37

HD#41

HD#42

HD#45

HD#39

HD#38

HD#33

HD#35

HD#31

HD#32

HD#44

75_1%

HD#43

R230

150_1%

R228

HD#34

HD#40

C290
.01UF_25V_0402_X7R

HNCVREF

C285
.01UF_25V_0402_X7R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

HD#24

J26

G26

J25

H26

G28

H28

J24

K28

HD#26

HD#30

HD#27

HD#23

HD#25

HD#29

HD#24

HD#28

C

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R24 8.2K_0402

12

R17 8.2K_0402

12

R279

60.4_1%

R227

8.2K_0603
R21

8.2K_0603

AGP_ADSTB0#

12

AGP_ADSTB1#

12

AGP_SBSTB#

12

12

R239
@22_0402

12

C283
@10PF_0402

745Thursday, May 30, 2002

of

VDDQ

VDDQ

1.0A

AGP_ST[0..2]<16>

AGP_AD29

AGP_AD30

AGP_SBA6

AGP_AD28

AGP_AD31

AGP_SBA7

SBA7

SBA6

VBCTL0AAD28

VBCTL1/AAD29

VBVSYNCAAD31

VBHSYNC/AAD30

AGP

HD#13

HD#12

HD#11

HD#10

HD#9

HD#8

HD#7

P26

L29

N24

N26

M27

N28

P27

HD#8

HD#12

HD#7

HD#10

HD#9

HD#11

HD#13

AGP_SBA5

AGP_SBA3

AGP_SBA2

AGP_SBA4

SBA5

SBA4

SBA3

SBA2

VAGCLKN/AD_STB#0

VBGCLKN/AD_STB#1

HD#6

HD#5

HD#4

HD#3

N29

R24

R28

M28

HD#3

HD#5

HD#6

HD#4

AGP_SBA0

AGP_SBA1

C7

AC/BE#3

SBA1

AC/BE#2
AC/BE#1
AC/BE#0

VBCLK/SBA0

VBCAD/AREQ#

AGNT#

AFRAME#

AIRDY#

ATRDY#

ADEVSEL#

ASERR#
ASTOP#

VBHCLK/RBF#
VGPIO2/WBF#
VGPIO3/PIPE#

SB_STB

SB_STB#

VAGCLK/AD_STB0

VBGCLK/AD_STB1

AGPCLK

AGPRCOMP

A1XAVDD

A1XAVSS

A4XAVDD

A4XAVSS

AGPVREF

AGPVSSREF

HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0

HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0

DBI#3

DBI#2

HD#2

HD#1

HD#0

P28

R26

R29

E21

A27

HD#0

HD#1

HD#2

H_DBI#2

H_DBI#3

C4XAVDD

U6A

F6
F3
H4
K5

C9
A6
G2
G1
G3
G4
H5
H1

H3

APAR

E8
F8
D9

D10

NC

B3

NC

C4

NC

B5
A4

K1
L1

C1
D1

B10
M1
B9

A9
B8

A8
M3

M2

F20
F23
K24
P24

F21
F24
L24
N25

DBI#1

DBI#0

SIS650

H27

R25

H_DBI#0

H_DBI#1

.1UF_0402_X5R

AGP_AD[0..31]<16>

AGP_C/BE#[0..3]<16>

AGP_C/BE#3
AGP_C/BE#2
AGP_C/BE#1
AGP_C/BE#0

AGP_REQ#
AGP_GNT#
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_DEVSEL#
AGP_SERR#
AGP_STOP#

AGP_PAR
AGP_RBF#

AGP_WBF#
AGP_PIPE#

CLK_AGP0
AGPRCOMP

A4XAVDD

H_DSTBN#3
H_DSTBN#2
H_DSTBN#1
H_DSTBN#0

H_DSTBP#3
H_DSTBP#2
H_DSTBP#1
H_DSTBP#0

C419

C418

.01UF_25V_0402_X7R

D

1 2

AGP_AD25

AGP_AD21

AGP_AD24

AGP_AD26

AGP_AD20

AGP_AD19

AGP_AD22

AGP_AD27

AGP_AD23

VBD8/AAD21

VBD9/AAD22

VAD1/AAD23

VAD0/AAD24

VAD2/AAD25

VAD3/AAD26

VBD11/AAD19

VAHSYNC/AAD18

HD#23

HD#22

J29

K27

HD#22

HD#21

VBDE/AAD27

VBD10/AAD20

HD#21

HD#20

HD#19

HD#18

HD#17

HD#16

HD#15

HD#14

J28

M24

L26

K26

L25

L28

M26

HD#14

HD#16

HD#17

HD#20

HD#15

HD#18

HD#19

AGP_ST[0..2]

AGP_AD[0..31]HD#[0..63]
AGP_C/BE#[0..3]

AGP_SBSTB

AGP_SBSTB#

AGP_ADSTB0
AGP_ADSTB#0

AGP_ADSTB1
AGP_ADSTB#1

A1XAVDD
A1XAVSS

AGP_NBREF

L36

MurataBLM21A601S

RP4 8P4R_8.2K
AGP_FRAME#
AGP_TRDY#
AGP_PAR
AGP_STOP#

RP2 8P4R_8.2K
AGP_GNT#

AGP_IRDY#
AGP_DEVSEL#

RP3 8P4R_8.2K

AGP_WBF#

ENVDD

AGP_PIPE#

ENBLT

AGP_SBSTB

AGP_REQ# <16>
AGP_GNT# <16>
AGP_FRAME# <16>
AGP_IRDY# <16>
AGP_TRDY# <16>
AGP_DEVSEL# <16>

AGP_STOP# <16>
AGP_PAR <16>
AGP_RBF# <16>

AGP_WBF# <16>
AGP_PIPE# <16>

AGP_ADSTB0 <16>
AGP_ADSTB0# <16>

AGP_ADSTB1 <16>

CLK_AGP0 <15>

C41 .1UF_0402_X5R

AGP_ADSTB1# <16>

+3VS

C288

.1UF_0402_X5R

CLOSE CHIP

AGP_NBREF

25MIL

+3VS

C417
10UF_10V_1206

Title

Size Document Number Rev

ACT10

Date: Sheet

AGP_SERR#

AGP_ADSTB0

AGP_ADSTB1

AGPRCOMP

AGP_REQ#

AGP_RBF#

R28 8.2K_0402

R18 8.2K_0402

R11 8.2K_0402

VDDQ

R27

300_0603_1%

R35
300_0603_1%

CLK_AGP0

Compal Electronics, Inc.

SiS 645/650

E

A

1 1

2 2

+3VALW

12

12

R280

R162

4.7K_0402

4.7K_0402

PSON#<18> SLP_S5# <33>

S3AUXSW#

3 3

S0 S3 S5
S3AUXSW#
PSON#
SLP_S3#
SLP_S5#

1 0 1 0

0 1 1 0

1 0 1 0

0 1 1 0

R408

0_0402

1 2

R404
0_0402

1 2

B

DDR_SDQ61
DDR_SDQ58
DDR_SDQ57
DDR_SDQ56
DDR_SDQ63
DDR_SDQ59
DDR_SDQ62
DDR_SDQ60
DDR_DM7

DDR_SDQS7

DDR_SDQ55
DDR_SDQ50
DDR_SDQ52
DDR_SDQ48
DDR_SDQ51
DDR_SDQ54
DDR_SDQ49
DDR_SDQ53
DDR_DM6

DDR_SDQS6

DDR_SDQ46
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ47
DDR_SDQ45
DDR_SDQ40
DDR_SDQ41
DDR_DM5

DDR_SDQS5

DDR_SDQ38
DDR_SDQ35
DDR_SDQ33
DDR_SDQ32
DDR_SDQ39
DDR_SDQ34
DDR_SDQ36
DDR_SDQ37
DDR_DM4

DDR_SDQS4

DDR_SDQ31
DDR_SDQ26
DDR_SDQ29
DDR_SDQ25
DDR_SDQ30
DDR_SDQ27
DDR_SDQ28
DDR_SDQ24
DDR_DM3

DDR_SDQS3

DDR_SDQ21
DDR_SDQ17
DDR_SDQ19
DDR_SDQ20
DDR_SDQ22
DDR_SDQ23
DDR_SDQ18
DDR_SDQ16
DDR_DM2

DDR_SDQS2

DDR_SDQ10
DDR_SDQ15
DDR_SDQ12
DDR_SDQ14
DDR_SDQ9
DDR_SDQ8
DDR_SDQ13

SLP_S3# <33>

X

DDR_SDQ11
DDR_DM1

DDR_SDQS1

DDR_SDQ0
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ2
DDR_SDQ7
DDR_SDQ1
DDR_DM0

DDR_SDQS0

AJ23
AG22
AH21

AJ21
AD23
AE23
AF22
AF21
AD22
AH22
AD21
AG20
AE19
AF19
AE21
AD20
AD19
AH19
AF20
AH20
AF18
AG18
AH17
AD16
AD18
AD17
AF17

AJ17
AE17
AH18
AD14
AG14

AJ13
AE13

AJ15
AF14
AD13
AF13
AH13
AH14
AD10
AH10

AG10
AF10

AE9

AD8

AH9

AF9

AD9

AJ9
AH5
AG4

AE5
AH3
AG6

AF6

AF5

AF4
AH4

AJ3

AE4
AD6

AE2
AC5
AG2
AG1

AF3
AC6
AD4

AF2

AB6
AD3

AA6

AB3
AC4

AE1
AD2
AC1

AB4
AC2

C

U6B

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0/CSB#0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB#1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB#2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3/CSB#3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB#4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB#5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB#6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB#7

SIS650

650-2

MA10
MA11
MA12
MA13
MA14

SRAS#
SCAS#

SWE#

CS#0
CS#1
CS#2
CS#3
CS#4
CS#5

CKE0
CKE1
CKE2
CKE3
CKE4
CKE5

S3AUXSW#

SDCLK

FWDSDCLKO

SDRCLKI

SDAVDD
SDAVSS

DDRAVDD
DDRAVSS

DDRVREFA
DDRVREFB

DRAM_SEL

D

DDR_SMA[0..12]

DDRMA9
DDRMA12

DDRMA8
DDRMA11

DDRMA5
DDRMA7

DDRMA1

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9

AF12
AH12
AG12
AD12
AH15
AF15
AH16
AE15
AD15
AF11
AG8
AJ11
AG16
AF16

AH8
AJ7
AH7

AE7
AF7
AH6
AJ5
AF8
AD7

AB2
AA4
AB1
Y6
AA5
Y5
Y4

AA3
AD11
AE11

Y1
Y2

AA1
AA2

AJ19
AH2

W3

DDRMA1
DDRMA2
DDRMA3
DDRMA4
DDRMA5
DDRMA6
DDRMA7
DDRMA8
DDRMA9
DDRMA10

DDRMA11
DDRMA12

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

S3AUXSW#

SDCLK

B_CLOCK

SDAVDD

DDRAVDD

DDRVREFA
DDRVREFB

DDR_SBS0
DDR_SBS1

DDRCAS#
DDRRAS#

DDRWE#
DDRCS#0
DDRCS#1

DDRCS#2
DDRCS#3

R301

22_0402

R291 4.7K_0402

DDR_CKE0 <12>
DDR_CKE1 <12>
DDR_CKE2 <13>
DDR_CKE3 <13>

DDRMA0

AH11

DDRMA3
DDRMA0

DDRMA2
DDRMA4

DDRMA6

DDRMA10

1 4
2 3

R101 10_0402
R99 10_0402
R100 10_0402

1 4
2 3

SDCLK <15>

FW

DSDCLKO

C414

10PF_0402_NPO

+3VALW

DDR_SDQ[0..63]
DDR_SDQS[0..7]

DDR_DM[0..7]

RP424P2R_10

RP184P2R_10

DDR_SCAS#
DDR_SRAS#

DDR_SWE#
DDR_SCS#0
DDR_SCS#1

DDR_SCS#2
DDR_SCS#3

FWDSDCLKO <15>

DDR_SMA[0..12] <12,13>

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R112

10_0402

DDR_SBS0 <12>
DDR_SBS1 <12>

DDR_SCAS# <12,13>
DDR_SRAS# <12,13>

DDR_SWE# <12,13>

DDR_SDQ[0..63] <12>
DDR_SDQS[0..7] <12>
DDR_DM[0..7] <12>

E

DDR_SMA9

RP154P2R_10

DDR_SMA12
DDR_SMA8

RP404P2R_10

DDR_SMA11
DDR_SMA5

RP164P2R_10

DDR_SMA7
DDR_SMA1

RP294P2R_10

DDR_SMA3
DDR_SMA0

RP174P2R_10

DDR_SMA2
DDR_SMA4

RP414P2R_10

DDR_SMA6

DDR_SMA10

DDR_SCS#0 <12,13>
DDR_SCS#1 <12>

DDR_SCS#2 <13>
DDR_SCS#3 <13>

SDCLK

+2.5V+2.5V

.01UF_25V_0402_X7R

4 4

.01UF_25V_0402_X7R

C105

R72
150_1%

A

DDRVREFBDDRVREFA

.01UF_25V_0402_X7R

.01UF_25V_0402_X7R

R71
150_1%

C409

R74

150_1%

C95

SDAVDD

R73
150_1%

C82

.1UF_0402_X5R

B

1 2

C389

+3VS

L33

MurataBLM21A601S

DDRAVDD

C386

.01UF_25V_0402_X7R

.1UF_0402_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

L29

1 2

MurataBLM21A601S

C390

+3VS

C52
10UF_10V_1206

D

12

R295
@22_0402

12

C379
@10PF_0402

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SiS 645/650

ACT10

845Thursday, May 30, 2002

E

of

1.0A

A

B

C

D

E

NB Hardware Trap Table(For Mobil Only)

CLK_NB14M

1 1

+1.8VS

R39

C353
.1UF_0402_X5R

150_1%

R38

150_1%

2 2

+3VS

1 2

C45

10UF_10V_1206

3 3

C357
.1UF_0402_X5R

L28

MurataBLM21A601S

ZVREF

C372

Z4XAVDD

.01UF_25V_0402_X7R

.01UF_25V_0402_X7R

961_PCIRST#<17>

PM_PWROK<6,18>

RSMRST#<18,33,35>

12

R248
@22_0402

12

C299
@10PF_0402

ZAD[0..15]<17>

C382

PID0_OLD

ZCLK0

ZCLK0<15>

ZUREQ<17>
ZDREQ<17>

ZSTB0<17>

ZSTB#0<17>

ZSTB1<17>

ZSTB#1<17>

R294 0_0402
R292 0_0402

R257 1K_0402

12

R285
@22_0402

12

C361
@10PF_0402

ZAD[0..15]

Z4XAVDD

PWRGD
AUXOK

U6C

SIS650
ZCLK0
ZUREQ

ZDREQ
ZSTB0

ZSTB#0
ZSTB1

ZSTB#1
ZAD0

ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15

ZVREF
VDDZCMP
ZCMP_P

Z4XAVDD

TRAP0

V3

ZCLK

U6

ZUREQ

U1

ZDREQ

T3

ZSTB0

T1

ZSTB#0

P1

ZSTB1

P3

ZSTB#1

T4

ZAD0

R3

ZAD1

T5

ZAD2

T6

ZAD3

R2

ZAD4

R6

ZAD5

R1

ZAD6

R4

ZAD7

P4

ZAD8

N3

ZAD9

P5

ZAD10

P6

ZAD11

N1

ZAD12

N6

ZAD13

N2

ZAD14

N4

ZAD15

U3

ZVREF

V5

VDDZCMP

U4

ZCMP_N

U2

ZCMP_P

V6

VSSZCMP

W1

Z1XAVDD

W2

Z1XAVSS

V2

Z4XAVDD

V1

Z4XAVSS

Y3

PCIRST#

W4

PWROK

W6

AUXOK

D11

TRAP1

E10

TRAP0

DRAM_SEL
TRAP0

TRAP1 Panel ID0
CSYNC
RSYNC
LSYNC

0

enable PLL

normal

Panel ID1
enable VGA interface
Panel ID2

C15

VOSCI

A12

ROUT

B13

GOUT

A13

BOUT

F13

HSYNC

E13

VSYNC

D13

VGPIO0

D12

VGPIO1

B11

INT#A

E12

CSYNC

A11

RSYNC

F12

LSYNC

E14

VCOMP

D14

VRSET

F14

VVBWN

B12

DACAVDD1

C12

DACAVSS1

C13

DACAVDD2

C14

DACAVSS2

B15

DCLKAVDD

A15

DCLKAVSS

B14

ECLKAVDD

A14

ECLKAVSS

F10

ENTEST

E11

DLLEN#

C11

TESTMODE0

F11

TESTMODE1

A10

TESTMODE2

disable PLL
DDR
NB debug mode

ROUT
GOUT
BOUT

R263
R253

RP68 4P2R_100
1 4
2 3

PID1_OLD
RSYNC
PID2_OLD

VCOMP
VRSET
VVBWN

DACAVDD2

DACAVDD2ZCMP_N

DCLKAVDD

ECLKAVDD

ENTEST

DLLEN#

1

R259

R13
R12
R14

33_0402
33_0402

1K_0402

CLK_NB14M

DDCCL_SIS
DDCDA_SIS

HSYNC_SIS
VSYNC_SIS

R250 130_1%

embedded pull-low

Default

(30~50K Ohm)

yesDLLEN#

0

yes1(DDR)SDR
yes0

X
X
1
X

CLK_NB14M <15>

CRT_R_SIS

0_0402

CRT_G_SIS

0_0402

CRT_B_SIS

0_0402

HSYNC_SIS <16>
VSYNC_SIS <16>

DDCCL_SIS <16>
DDCDA_SIS <16>

SIS_PIRQA# <16>

Ap Note:
DACAVDD1 & DACAVDD2 connect together
DACAVSS1 & DACAVSS2 connect together

CRT_R_SIS <16>
CRT_G_SIS <16>
CRT_B_SIS <16>

for 650 only

RSYNC

PID0_OLD
PID1_OLD

PID2_OLD

ENTEST
PWRGD
AUXOK

R234 4.7K_0402

R254 @10K_0402
R265 @10K_0402

R264

1 2

@10K_0402

R266 4.7K_0402
C388 .1UF_0402_X5R
C374 @.1UF_0402_X5R

+3VS

L13

DCLKAVDD

+1.8VS

4 4

A

0_0603

R277

C366

.1UF_0402_X5R

C348

.01UF_25V_0402_X7R

R286 56_0402
R290 56_0402

VDDZCMP
ZCMP_N
ZCMP_P

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

.01UF_25V_0402_X7R

ECLKAVDD

.01UF_25V_0402_X7R

C292

C294

MurataBLM21A601S

C291

.1UF_0402_X5R

C293

.1UF_0402_X5R

1 2

L14

1 2

MurataBLM21A601S

D

+3VS

C275

10UF_10V_1206

+3VS

C268

10UF_10V_1206

C300

VVBWN

VCOMP

DACAVDD2

.1UF_0402_X5R

C301

.1UF_0402_X5R

C297

C286

.1UF_0402_X5R

Title

Size Document Number Rev

ACT10

Date: Sheet

+1.8VS

L17

1 2

MurataBLM21A601S

1UF_10V_0603_X5R

C341

10UF_10V_1206

Compal Electronics, Inc.

SiS 645/650

E

945Thursday, May 30, 2002

1.0A

of

A

+CPU_CORE

1 1

2 2

3 3

4 4

+CPU_CORE

+2.5V

VDDQ

+1.8VS

AE10
AE12
AE14
AE16
AE18
AE20
AE22

W18

AA10
AA13
AA14
AA15
AA16
AA17

AB13
AB17

H21

H22

J16

J20

J21

A16

VTT

A17

VTT

A18

VTT

B16

VTT

B17

VTT

B18

VTT

C16

VTT

C17

VTT

C18

VTT

D15

VTT

D16

VTT

D17

VTT

D18

VTT

E15

VTT

E16

VTT

E17

VTT

E18

VTT

F15

VTT

F16

VTT

F17

VTT

F18

VTT

AB5

VDDM

AD5

VDDM

AE6

VDDM

AE8

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

V10

VDDM

V11

VDDM
VDDM

Y9

VDDM

Y10

VDDM

Y12

VDDM

Y14

VDDM

Y16

VDDM

Y18

VDDM

Y19

VDDM

AA8

VDDM

AA9

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

AB8

VDDM

AB9

VDDM
VDDM
VDDM

E5

VDDQ

E7

VDDQ

E9

VDDQ

G5

VDDQ

J5

VDDQ

L5

VDDQ

H8

VDDQ

H9

VDDQ

J8

VDDQ

J9

VDDQ

J10

VDDQ

J13

VDDQ

K9

VDDQ

K11

VDDQ

K13

VDDQ

L10

VDDQ

N9

VDDQ

N10

VDDQ

N5

VDDZ

R5

VDDZ

U5

VDDZ

W5

VDDZ

P9

VDDZ

P10

VDDZ

R9

VDDZ

R10

VDDZ

T9

VDDZ

T10

VDDZ

T11

VDDZ

PVDDP

L17

J22

VTT

VTT

VTT

VTT

VTT

PVDDP

PVDDP

PVDDP

PVDDP

PVDDP

VSS

L19

N19

R19

U19

W19

M12

M13

B

K16

K17

K18

K19

K20

K21

L20

M20

N20

P20

R20

R21

T20

U20

V20

W20

Y20

Y21

AA20

AA21

AA22

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

650-4

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M14

M15

M16

M17

M18

N12

N13

N14

N15

N16

N17

N18

P12

P13

VSS

P14

P15

P16

P17

P18

R12

R13

C

+1.8VS +3VS

AB21

AB22

L12

L14

L15

L16

L18

M11

M19

N11

P19

R11

T19

U11

V19

W11

W13

W15

W17

VTT

VTT

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

IVDD

Power

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

R14

R15

R16

R17

R18

T12

T13

T14

T15

T16

T17

T18

VSS

U12

U13

U14

U15

U16

U17

U18

V12

D

+3VALW

12

R283

+PVDDM

0_0805

P11

J14

J15

K15

K10

K12

K14

M10

W10

Y11

Y13

Y15

Y17

IVDD

PVDD

PVDD

PVDD

PVDD

OVDD

OVDD

OVDD

PVDDZ

VSS

VSS

VSS

VSS

VSS

V13

V14

V15

V16

V17

PVDDM

PVDDM

PVDDM

PVDDM

PVDDM

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

V18

B25

C28

VSS

C29

D27

D28

E28

E29

AF23

AF24

AF25

VSS

AUX1.8
AUX3.3

VSS

AG24

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

AG26

AH23

NBAUX1.8V NBAUX3.3V

U6D

U10
U9

A20
A22
A24
A26
C19
C21
C23
C25
C27
E20
E22
E24
F25
H25
K25
M25
P25
T25
V25
Y25
AB25
AD25
E27
G27
J27
L27
N27
R27
U27
W27
AA27
AC27
AE27
D29
F29
H29
K29
M29
P29
T29
V29
Y29
AB29
AD29
AF29
AE24
AG25
B4
B6
C8
C10
D2
F2
H2
K2

P2
T2
V4
AD1
AF1
AC3
AE3
AG3
AG5
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AJ4
AJ6
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AG27

VSS

VSS

SIS650

AH24

E

+3VALW

+1.8VALW

12

12

R223

R220

0_0603

0_0603

+5VS VDDQ

R590

1 2

10K_0402

C730

.1UF_0402_X5R

1
2

5

F

U67

IN
IN

GND

MAX1857

OUT
OUT

SETSHDN
RST

8
7

64
3

R593

49.9K_1%_0603

12

R591

20K_1%_0603

12

.1UF_0402_X5R

G

12

R592

20K_1%_0603

12

R594

6.8K_1%

Q70

13

D

G

S

2N7002

C733

C731

.1UF_0402_X5R

+5VS

12

2

Internal AGP : H
External AGP : L

R595

100K_0402

12

C732

4.7UF_16V_1206

VDDQ_SW <16>

H

+1.8VS

A

B

C

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

F

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SiS 645/650

ACT10

G

10 45Thursday, May 30, 2002

H

1.0A

of

5

4

3

2

1

Layout note :

Distribute as close as possible
to ProcessorQuadrant.(betweenVTTFSB and VSS pin)

D D

+1.8VALW +3VALW

C C

10UF_6.3V_1206_X7R

10UF_6.3V_1206_X7R

B B

10UF_6.3V_1206_X7R

10UF_6.3V_1206_X7R

Processor system bus

C266

10UF_10V_1206

C265

1UF_10V_0603_X5R

C6

.1UF_0402_X5R

C391

C392

C325

C267

C262

10UF_10V_1206

C263

1UF_10V_0603_X5R

C260

.1UF_0402_X5R

C280

1UF_10V_0603_X5R

C329

1UF_10V_0603_X5R

C346

1UF_10V_0603_X5R

C332

1UF_10V_0603_X5R

+3VS

10UF_10V_1206

1UF_10V_0603_X5R

C279

.1UF_0402_X5R

C380

.1UF_0402_X5R

C351

.1UF_0402_X5R

C320

.1UF_0402_X5R

C278

C277

C321

.1UF_0402_X5R

C328

.1UF_0402_X5R

C281

.1UF_0402_X5R

C371

.1UF_0402_X5R

C367

.1UF_0402_X5R

C312

.1UF_0402_X5R

CHECK SiS 650 CAP.
IT NEED HOW MANY ESR

+1.8VS+CPU_CORE

C354

10UF_6.3V_1206_X7R

C370

1UF_10V_0603_X5R

C350

.1UF_0402_X5R

C334

.1UF_0402_X5R

C723

10UF_6.3V_1206_X7R

C724

1UF_10V_0603_X5R

C725

.1UF_0402_X5R

VDDQ +2.5V

C313

.1UF_0402_X5R

C323

.1UF_0402_X5R

C327

.1UF_0402_X5R

C310

.1UF_0402_X5R

Place these capacitors under 650 solder side

+CPU_CORE

C304

.1UF_0402_X5R

C308

.1UF_0402_X5R

C303

.1UF_0402_X5R

C307

.1UF_0402_X5R

+1.8VS

C336

.1UF_0402_X5R

C342

.1UF_0402_X5R

C338

.1UF_0402_X5R

C315

.1UF_0402_X5R

C333

.1UF_0402_X5R

C344

.1UF_0402_X5R

C352

.1UF_0402_X5R

C356

.1UF_0402_X5R

+2.5V

C393

10UF_10V_1206

C394

10UF_10V_1206

C395

10UF_10V_1206

C396

10UF_10V_1206

C407

.1UF_0402_X5R

C404

.1UF_0402_X5R

C405

.1UF_0402_X5R

C406

.1UF_0402_X5R

+1.8VS

.1UF_0402_X5R

+3VS

.1UF_0402_X5R

C365

1UF_10V_0603_X5R

C368

1UF_10V_0603_X5R

C408

.1UF_0402_X5R
C410

.1UF_0402_X5R

C381

C314

10UF_6.3V_1206_X7R

C397

.1UF_0402_X5R
C322

+3VS

.1UF_0402_X5R

.1UF_0402_X5R

C401

1UF_10V_0603_X5R

C362

1UF_10V_0603_X5R

C412

.1UF_0402_X5R

C373

.1UF_0402_X5R

C324

C282

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SiS 645/650 Decoupling
ACT10

1

11 45Thursday, May 30, 2002

1.0A

of

5

DDR SWAP NOW, SO DATA NOT CORRECT

DDR_SDQ1

!

DDR_SDQ5

DDR_SDQ2

!

DDR_SDQ7

DDR_DM0

!

D D

Layout note

Place these resistor
closely DIMM0,
all trace
length<750mil

C C

B B

A A

DDR_SDQS0

DDR_SDQ4

!

DDR_SDQ3

DDR_SDQ0

!

DDR_SDQ6

DDR_SDQ14

!

DDR_SDQ11

DDR_SDQ12 DDR_DQ41

!

DDR_SDQ15

DDR_DM1
DDR_SDQS1

!

DDR_SDQ9

!

DDR_SDQ8

DDR_SDQ10

!

DDR_SDQ13

DDR_SDQ20

!

DDR_SDQ19

DDR_SDQ17

!

DDR_SDQ16

DDR_SDQS2

!

DDR_DM2

DDR_SDQ18

!

DDR_SDQ21

DDR_SDQ23

!

DDR_SDQ22

DDR_SDQ31

!

DDR_SDQ25

DDR_SDQ28

!

DDR_SDQ29

!

DDR_DM3

DDR_SDQ26

!

DDR_SDQ24

DDR_SDQ30

!

DDR_SDQ27

5

RP5 4P2R_10
1 4
2 3

RP30 4P2R_10
1 4
2 3

RP6 4P2R_10
1 4
2 3

RP31 4P2R_10
1 4
2 3

RP7 4P2R_10
1 4
2 3

RP32 4P2R_10
1 4
2 3

RP8 4P2R_10
1 4
2 3

RP33 4P2R_10
1 4
2 3

RP9 4P2R_10
1 4
2 3

RP34 4P2R_10
1 4
2 3

RP10 4P2R_10
1 4
2 3

RP35 4P2R_10
1 4
2 3

RP11 4P2R_10
1 4
2 3

RP36 4P2R_10
1 4
2 3

RP12 4P2R_10
1 4
2 3

RP37 4P2R_10
1 4
2 3

RP13 4P2R_10
1 4
2 3

RP38 4P2R_10
1 4
2 3

RP14 4P2R_10
1 4
2 3

RP39 4P2R_10
1 4
2 3

DDR_DQ1
DDR_DQ5

DDR_DQ2
DDR_DQ7

DDR_F_DM0
DDR_DQS0

DDR_DQ4
DDR_DQ3

DDR_DQ0
DDR_DQ6

DDR_DQ14
DDR_DQ11

DDR_DQ12
DDR_DQ15

DDR_F_DM1
DDR_DQS1

DDR_DQ9
DDR_DQ8

DDR_DQ10
DDR_DQ13

DDR_DQ20
DDR_DQ19

DDR_DQ17
DDR_DQ16

DDR_DQS2
DDR_F_DM2

DDR_DQ18
DDR_DQ21

DDR_DQ23
DDR_DQ22

DDR_DQ31
DDR_DQ25

DDR_DQ28
DDR_DQ29

DDR_DQS3DDR_SDQS3
DDR_F_DM3

DDR_DQ26
DDR_DQ24

DDR_DQ30
DDR_DQ27

4

DDR_SDQ36

!

DDR_SDQ38

DDR_SDQ37

!

DDR_SDQ32

DDR_SDQS4

!

DDR_DM4

DDR_SDQ39

!

DDR_SDQ33

DDR_SDQ34

!

DDR_SDQ35

DDR_SDQ43

!

DDR_SDQ44

DDR_SDQ41

!

DDR_SDQ45

DDR_DM5
DDR_SDQS5

!

DDR_SDQ40

!

DDR_SDQ42

DDR_SDQ47

!

DDR_SDQ46

DDR_SDQ49

!

DDR_SDQ48

DDR_SDQ53

!

DDR_SDQ50

DDR_SDQS6

!

DDR_DM6

DDR_SDQ51

!

DDR_SDQ52 DDR_DQ52

DDR_SDQ55

!

DDR_SDQ54 DDR_CKE1

DDR_SDQ58

!

DDR_SDQ60

DDR_SDQ57

!

DDR_SDQ56

DDR_DM7

!

DDR_SDQS7

DDR_SDQ62

!

DDR_SDQ61

DDR_SDQ63

!

DDR_SDQ59

RP43 4P2R_10
1 4
2 3

RP20 4P2R_10
1 4
2 3

RP44 4P2R_10
1 4
2 3

RP21 4P2R_10
1 4
2 3

RP45 4P2R_10
1 4
2 3

RP22 4P2R_10
1 4
2 3

RP46 4P2R_10
1 4
2 3

RP23 4P2R_10
1 4
2 3

RP47 4P2R_10
1 4
2 3

RP24 4P2R_10
1 4
2 3

RP48 4P2R_10
1 4
2 3

RP25 4P2R_10
1 4
2 3

RP49 4P2R_10
1 4
2 3

RP26 4P2R_10
1 4
2 3

RP50 4P2R_10
1 4
2 3

RP27 4P2R_10
1 4
2 3

RP51 4P2R_10
1 4
2 3

RP28 4P2R_10
1 4
2 3

RP52 4P2R_10
1 4
2 3

RP71 4P2R_10
1 4
2 3

Layout note
Place these resistor closely DIMM0,

all trace length<=750mil

DDR_SDQ[0..63]<8>

DDR_DM[0..7]<8>

DDR_SDQS[0..7]<8>

4

DDR_DQ36
DDR_DQ38

DDR_DQ37
DDR_DQ32

DDR_DQS4
DDR_F_DM4

DDR_DQ39
DDR_DQ33

DDR_DQ34
DDR_DQ35

DDR_DQ43
DDR_DQ44

DDR_DQ45

DDR_F_DM5
DDR_DQS5

DDR_DQ40
DDR_DQ42

DDR_DQ47
DDR_DQ46

DDR_DQ49
DDR_DQ48

DDR_DQ50

DDR_DQS6
DDR_F_DM6

DDR_DQ51

DDR_DQ55
DDR_DQ54

DDR_DQ58
DDR_DQ60

DDR_DQ57
DDR_DQ56

DDR_F_DM7
DDR_DQS7

DDR_DQ62
DDR_DQ61

DDR_DQ63
DDR_DQ59

DDR_SDQ[0..63]
DDR_DM[0..7]
DDR_SDQS[0..7]

DDR_CLK1<15>

DDR_CLK1#<15>

DDR_CLK0<15>

DDR_CLK0#<15>

DDR_CKE1<8>

DDR_SWE#<8,13>

DDR_SCS#0<8,13>

SMB_DATA<13,15,18,20>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

3

+2.5V

JP2

1

VREF

3
DDR_DQ1
DDR_DQ2

DDR_DQS0
DDR_DQ4

DDR_DQ0
DDR_DQ14

DDR_DQ12
DDR_DQS1

DDR_DQ9
DDR_DQ10

DDR_DQ20
DDR_DQ17

DDR_DQS2
DDR_DQ18

DDR_DQ23
DDR_DQ31

DDR_DQ28
DDR_DQS3

DDR_DQ26
DDR_DQ30

DDR_CKE1
DDR_SMA12

DDR_SMA9
DDR_SMA7DDR_DQ53

DDR_SMA5
DDR_SMA3
DDR_SMA1

DDR_SMA10
DDR_F_SBS0
DDR_SW

E#

DDR_SCS#0

DDR_DQ36
DDR_DQ37

DDR_DQS4
DDR_DQ39

DDR_DQ34
DDR_DQ43

DDR_DQ41
DDR_DQS5

DDR_DQ40
DDR_DQ47

DDR_DQ49
DDR_DQ53

DDR_DQS6
DDR_DQ51

DDR_DQ55
DDR_DQ58

DDR_DQ57
DDR_DQS7

DDR_DQ62 DDR_DQ61
DDR_DQ63

SMB_CLK<13,15,18,20>

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

MOLEX 67589-2003 200P STD

VREF

DQ4

DQ5
VDD
DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14
DQ15

VDD
VDD

VSS

VSS

DQ20
DQ21

VDD
DM2

DQ22

VSS

DQ23
DQ28

VDD

DQ29

DM3

VSS

DQ30
DQ31

VDD

CB4

CB5

VSS
DM8

CB6
VDD

CB7

DU/RESET#

VSS

VSS
VDD
VDD

CKE0

DU/BA2

VSS

VDD

RAS#
CAS#

VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5

VSS

DQ46
DQ47

VDD

CK1#

CK1

VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

DQ61

DM7

VSS

DQ62
DQ63

VDD

VSS

A11

A8
A6

A4
A2
A0

BA1

S1#

DU

SA0
SA1
SA2

DU

DIMM0

top
side

3

2

+2.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQ5
DDR_DQ7

DDR_F_DM0
DDR_DQ3

DDR_DQ6
DDR_DQ11

DDR_DQ15
DDR_F_DM1

DDR_DQ8
DDR_DQ13

DDR_DQ19
DDR_DQ16

DDR_F_DM2
DDR_DQ21

DDR_DQ22
DDR_DQ25

DDR_DQ29
DDR_F_DM3

DDR_DQ24
DDR_DQ27

DDR_CKE0

DDR_SMA11
DDR_SMA8

DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0

DDR_F_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#1

DDR_DQ38
DDR_DQ32

DDR_F_DM4
DDR_DQ33

DDR_DQ35
DDR_DQ44

DDR_DQ45
DDR_F_DM5

DDR_DQ42
DDR_DQ46

DDR_DQ48
DDR_DQ50

DDR_F_DM6
DDR_DQ52

DDR_DQ54
DDR_DQ60

DDR_DQ56
DDR_F_DM7

DDR_DQ59

2

SDREF_R

12

DDR_CKE0 <8>

DDR_SRAS# <8,13>
DDR_SCAS# <8,13>
DDR_SCS#1 <8>

DDR_CLK2# <15>
DDR_CLK2 <15>

DDR_F_SBS1<13>

DDR_F_SBS0<13>

Title

Size Document Number Rev

Date: Sheet

L54

1 2

C451

MurataBLM21A601S

.1UF_16V_0402_Y5V

ACT10

1

SDREF

DDR_DQ[0..63]
DDR_F_DM[0..7]
DDR_DQS[0..7]

DDR_SMA[0..12]

Layout note
Place these resistor

closely DIMM0,
all trace length
Max=1.3"

DDR_CKE0

DDR_SCS#1

PULL -UP AT PAGE 13

DDR_F_SBS1

DDR_F_SBS0

DDR_DQ[0..63] <13>
DDR_F_DM[0..7] <13>
DDR_DQS[0..7] <13>

DDR_SMA[0..12] <8,13>

RP58 4P2R_470
1 4
2 3

R132

1 2

33_0402

RP194P2R_10

14
23

Compal Electronics, Inc.

DDR-SODIMM SLOT1

1

+2.5V

+1.25VS

DDR_SBS1 <8>
DDR_SBS0 <8>

12 45Thursday, May 30, 2002

1.0A

of

A

+1.25VS +1.25VS

RP116 4P2R_33

DDR_DQ5

1 4
2 3

RP115 4P2R_33

DDR_DQ1

1 4

DDR_DQ2

2 3

DDR_F_DM0
DDR_DQ3

DDR_DQS0
DDR_DQ4

DDR_DQ6
DDR_DQ11

DDR_DQ0
DDR_DQ14

DDR_DQ15
DDR_F_DM1

DDR_DQ12
DDR_DQS1

DDR_DQ8
DDR_DQ13

DDR_DQ9
DDR_DQ10

DDR_DQ19
DDR_DQ16

DDR_DQ20
DDR_DQ17

DDR_F_DM2
DDR_DQ21

DDR_DQS2
DDR_DQ18

DDR_DQ22
DDR_DQ25

DDR_DQ23
DDR_DQ31

RP114 4P2R_33
1 4
2 3

RP113 4P2R_33
1 4
2 3

RP111 4P2R_33
1 4
2 3

RP112 4P2R_33
1 4
2 3

RP110 4P2R_33
1 4
2 3

RP108 4P2R_33
1 4
2 3

RP107 4P2R_33
1 4
2 3

RP109 4P2R_33
1 4
2 3

RP106 4P2R_33
1 4
2 3

RP105 4P2R_33
1 4
2 3

RP104 4P2R_33
1 4
2 3

RP103 4P2R_33
1 4
2 3

RP98 4P2R_33
1 4
2 3

RP102 4P2R_33
1 4
2 3

1 1

2 2

3 3

RP100 4P2R_33

14
23

RP101 4P2R_33

14
23

RP97 4P2R_33

14
23

RP99 4P2R_33

14
23

RP95 4P2R_33

14
23

RP90 4P2R_33

14
23

RP94 4P2R_33

14
23

RP89 4P2R_33

14
23

RP93 4P2R_33

14
23

RP88 4P2R_33

14
23

RP91 4P2R_33

14
23

RP87 4P2R_33

14
23

RP92 4P2R_33

14
23

RP86 4P2R_33

14
23

RP85 4P2R_33

14
23

RP83 4P2R_33

14
23

DDR_DQ29
DDR_F_DM3

DDR_DQ28
DDR_DQS3

DDR_DQ24
DDR_DQ27

DDR_DQ26
DDR_DQ30

DDR_DQ38
DDR_DQ32

DDR_DQ36
DDR_DQ37

DDR_F_DM4
DDR_DQ33

DDR_DQS4
DDR_DQ39

DDR_DQ35
DDR_DQ44

DDR_DQ34
DDR_DQ43

DDR_DQ45
DDR_F_DM5

DDR_DQ41
DDR_DQS5

DDR_DQ42
DDR_DQ46

DDR_DQ40
DDR_DQ47

DDR_DQ48
DDR_DQ50

DDR_DQ49
DDR_DQ53

RP84 4P2R_33

DDR_F_DM6

14

DDR_DQ52

23

RP82 4P2R_33

DDR_DQS6

14

DDR_DQ51

23

RP81 4P2R_33

DDR_DQ54

14

DDR_DQ60

23

RP80 4P2R_33

DDR_DQ55

14

DDR_DQ58

23

RP78 4P2R_33

DDR_DQ56

14

DDR_F_DM7

23

RP79 4P2R_33

DDR_DQ57

14

DDR_DQS7

23

RP76 4P2R_33

DDR_DQ61

14

DDR_DQ59

23

RP77 4P2R_33

DDR_DQ62

14

DDR_DQ63

23

Layout note
Place these resistor

closely DIMM1,
all trace
length<=800mil

4 4

A

B

DDR_DQ[0..63]DDR_DQ7
DDR_SMA[0..12]

DDR_F_DM[0..7]
DDR_DQS[0..7]

DDR_SDQ[0..7]

B

DDR_DQ[0..63] <12>
DDR_SMA[0..12] <8,12>

DDR_F_DM[0..7] <12>
DDR_DQS[0..7] <12>

DDR_SDQ[0..7] <8,12>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

DDR_CLK4<15>
DDR_CLK4#<15>

DDR_CLK3<15>
DDR_CLK3#<15>

DDR_SWE#<8,12>

SMB_DATA<12,15,18,20>

SMB_CLK<12,15,18,20>

C

+2.5V +2.5V

JP3

1

VREF

3

DDR_DQ5
DDR_DQ7

DDR_DQS0
DDR_DQ3

DDR_DQ6
DDR_DQ11

DDR_DQ15
DDR_DQS1

DDR_DQ8
DDR_DQ13

DDR_DQ19
DDR_DQ16

DDR_DQS2
DDR_DQ21

DDR_DQ22
DDR_DQ25

DDR_DQ29
DDR_DQS3

DDR_DQ24
DDR_DQ27

DDR_CKE3
DDR_SMA12

DDR_SMA9
DDR_SMA7

DDR_SMA5
DDR_SMA3
DDR_SMA1

DDR_SMA10

DDR_F_SBS0

E#

DDR_SW
DDR_SCS#2 DDR_SCS#3

DDR_DQ38
DDR_DQ32

DDR_DQS4
DDR_DQ33

DDR_DQ35
DDR_DQ44

DDR_DQ45
DDR_DQS5

DDR_DQ42
DDR_DQ46

DDR_DQ48
DDR_DQ50

DDR_DQS6
DDR_DQ52

DDR_DQ54
DDR_DQ60

DDR_DQ56
DDR_DQS7

DDR_DQ61
DDR_DQ59

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

MOLEX 67625-2003 200P REV

DIMM1

bottom
side

D

DU/RESET#

DU/BA2

D

VREF

VDD
DM0

DQ12

VDD

DQ13

DM1

DQ14
DQ15

VDD
VDD

DQ20
DQ21

VDD
DM2

DQ22
DQ23

DQ28

VDD

DQ29

DM3

DQ30
DQ31

VDD

DM8
VDD

VDD
VDD

CKE0

VDD

RAS#
CAS#

DQ36
DQ37

VDD
DM4

DQ38
DQ39

DQ44

VDD

DQ45

DM5

DQ46
DQ47

VDD

CK1#

DQ52
DQ53

VDD
DM6

DQ54
DQ55

DQ60

VDD

DQ61

DM7

DQ62
DQ63

VDD

E

2
4

VSS

6

DQ4

8

DQ5

10
12
14

DQ6

16

VSS

18

DQ7

20
22
24
26
28

VSS

30
32
34
36
38

VSS

40

VSS

42
44
46
48
50
52

VSS

54
56
58
60
62
64

VSS

66
68
70
72

CB4

74

CB5

76

VSS

78
80

CB6

82
84

CB7

86
88

VSS

90

VSS

92
94
96
98
100

A11

102

A8

104

VSS

106

A6

108

A4

110

A2

112

A0

114
116

BA1

118
120
122

S1#

124

DU

126

VSS

128
130
132
134
136
138

VSS

140
142
144
146
148
150

VSS

152
154
156
158
160

CK1

162

VSS

164
166
168
170
172
174

VSS

176
178
180
182
184
186

VSS

188
190
192
194

SA0

196

SA1

198

SA2

200

DU

DDR_DQ1
DDR_DQ2

DDR_F_DM0
DDR_DQ4

DDR_DQ0
DDR_DQ14

DDR_DQ12
DDR_F_DM1

DDR_DQ9
DDR_DQ10

DDR_DQ20
DDR_DQ17

DDR_F_DM2
DDR_DQ18

DDR_DQ23
DDR_DQ31

DDR_DQ28
DDR_F_DM3

DDR_DQ26
DDR_DQ30

DDR_CKE2

DDR_SMA11
DDR_SMA8

DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0

DDR_F_SBS1
DDR_SRAS#
DDR_SCAS#

DDR_DQ36
DDR_DQ37

DDR_F_DM4
DDR_DQ39

DDR_DQ34
DDR_DQ43

DDR_DQ41
DDR_F_DM5

DDR_DQ40
DDR_DQ47

DDR_DQ49
DDR_DQ53

DDR_F_DM6
DDR_DQ51

DDR_DQ55
DDR_DQ58

DDR_DQ57
DDR_F_DM7

DDR_DQ62
DDR_DQ63

SDREF_R

12

C450
.1UF_16V_0402_Y5V

+1.25VS

RP604P2R_33

DDR_SMA8

1 4

DDR_SMA11

2 3

RP61 4P2R_33

DDR_SMA9

14

DDR_SMA12

23

RP54 4P2R_33

RP55 4P2R_33

R130 33_0402

DDR_CKE2 <8>DDR_CKE3<8>

R131 33_0402

DDR_SRAS# <8,12>
DDR_SCAS# <8,12>
DDR_SCS#3 <8>DDR_SCS#2<8>

DDR_F_SBS0
DDR_F_SBS1
DDR_SCS#0

DDR_CLK5# <15>
DDR_CLK5 <15>

+3VS

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDR-SODIMM SLOT1

ACT10

DDR_SMA4

1 4

DDR_SMA6

2 3

RP53 4P2R_33

DDR_SMA5

14

DDR_SMA7

23

DDR_SMA0

1 4

DDR_SMA2

2 3

RP56 4P2R_33

DDR_SMA1

14

DDR_SMA3

23

DDR_SMA10

1 2

RP96 4P2R_33

DDR_F_SBS1

14

DDR_F_SBS0

23

RP574P2R_33

DDR_SCAS#

1 4

DDR_SRAS#

2 3

DDR_SWE#

1 2

DDR_F_SBS0 <12>
DDR_F_SBS1 <12>
DDR_SCS#0 <8,12>

RP72 4P2R_470

DDR_CKE2

1 4

DDR_CKE3

2 3

RP59 4P2R_33

DDR_SCS#0

1 4

DDR_SCS#2

2 3

R133 33_0402

DDR_SCS#3

1 2

Layout note
Place these resistor

closely DIMM0,
all trace length
Max=1.3"

13 45Thursday, May 30, 2002

E

+2.5V

+1.25VS

of

1.0A

A

B

C

D

E

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

1 1

12

C146
.1UF_0402_X5R

+2.5V +2.5V

12

C156
.1UF_0402_X5R

12

C147
.1UF_0402_X5R

12

C161
.1UF_0402_X5R

12

C148
.1UF_0402_X5R

12

C157
.1UF_0402_X5R

12

C149
.1UF_0402_X5R

12

C158
.1UF_0402_X5R

12

C150
.1UF_0402_X5R

12

C159
.1UF_0402_X5R

12

C151
.1UF_0402_X5R

12

C160
.1UF_0402_X5R

12

C152
.1UF_0402_X5R

12

+

C170
150UF_D2_6.3V

12

C153
.1UF_0402_X5R

12

+

C144
150UF_D2_6.3V

12

C154
.1UF_0402_X5R

12

C155
.1UF_0402_X5R

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

+1.25VS

12

C504
.1UF_0402_X5R

+1.25VS

12

C495
.1UF_0402_X5R

12

C503
.1UF_0402_X5R

12

C494
.1UF_0402_X5R

12

C502
.1UF_0402_X5R

12

C493
.1UF_0402_X5R

12

C501
.1UF_0402_X5R

12

C492
.1UF_0402_X5R

12

C500
.1UF_0402_X5R

12

C491
.1UF_0402_X5R

12

C505
.1UF_0402_X5R

12

C490
.1UF_0402_X5R

12

C499
.1UF_0402_X5R

12

C489
.1UF_0402_X5R

12

C498
.1UF_0402_X5R

12

C488
.1UF_0402_X5R

12

C497
.1UF_0402_X5R

12

C487
.1UF_0402_X5R

12

C496
.1UF_0402_X5R

12

C486
.1UF_0402_X5R

+1.25VS

12

C485

3 3

4 4

.1UF_0402_X5R

+1.25VS

12

C475
.1UF_0402_X5R

+1.25VS

12

C465
.1UF_0402_X5R

+1.25VS

12

C455
.1UF_0402_X5R

12

C484
.1UF_0402_X5R

12

C474
.1UF_0402_X5R

12

C464
.1UF_0402_X5R

12

C454
.1UF_0402_X5R

A

12

C483
.1UF_0402_X5R

12

C473
.1UF_0402_X5R

12

C463
.1UF_0402_X5R

12

C453
.1UF_0402_X5R

12

C482
.1UF_0402_X5R

12

C472
.1UF_0402_X5R

12

C462
.1UF_0402_X5R

12

C452
.1UF_0402_X5R

12

C481
.1UF_0402_X5R

12

C471
.1UF_0402_X5R

12

C461
.1UF_0402_X5R

12

C480
.1UF_0402_X5R

12

C470
.1UF_0402_X5R

12

C460
.1UF_0402_X5R

B

12

C479
.1UF_0402_X5R

12

C469
.1UF_0402_X5R

12

C459
.1UF_0402_X5R

12

C478
.1UF_0402_X5R

12

C468
.1UF_0402_X5R

12

C458
.1UF_0402_X5R

12

C477
.1UF_0402_X5R

12

C467
.1UF_0402_X5R

12

C457
.1UF_0402_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

12

12

12

C

C476
.1UF_0402_X5R

C466
.1UF_0402_X5R

C456
.1UF_0402_X5R

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

DDR SODIMM Decoupling

ACT10

14 45Thursday, May 30, 2002

E

1.0A

of