Compal LA-1281 CY23 Schematic
A
B
C
D
E
Compal confidential
Block Diagram
Model Name : CY23 LA-1281 Rev1.0
1 1
CRT
Connector
page 14
TV_OUT
Connector
page 13
TFT Panel
Interface
2 2
page 14
INTEL FC-PGA370
Page 2,3
HD#(0..63)HA#(3..31)
Twister PN-133T
(VT8606)
page 4,5,6
Memory Damping
AD(0..31)
Resistor
PCIGNT#/PCIREQ#
MD(0..63)
page 6
PIRQA#
MA(0..13)
APICCLK
HCLK_CPU
HCLK_NB
PCLK_NB
DCLKWR
On Board
64/128MB
(Bank 0)
page 7
DCLKO
CLK_SDRAM0
SO-DIMM 0
(Bank 2,3)
page 8
Y1
14.318MHZ
Clock Generator
ICS 9248-195
page 11
CLK_SDRAM2,3
14MOSC
14MCRT/14.3M_TV
PCLK_1394
PCLK_PCM
PCLK_MINI
PCLK_SB
PCI BUS
USB Port 0,1
page 12
DIRECT
CD-PLAY
FUNCTION
page 18
134, 22, 2001
E
1B
of
BIOS
FIR
page 25
ISA BUS
KeyBoard
87570
page 20
SA(0..15)
SD(0..15)
KBD
page 21
Touch Pad
page 26page 21
VT686B
page 9,10
IDE Damping
Resistor
page 17
IDE Connector
(FDD/HDD/CR-ROM)
page 19
D
48MHZ
14MOSC
IDE CHANNEL 1
Pull Up/Down
Resistor
PIO
page 24
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1281
401202
!"# $%
Mini PCI
Socket
PIRQB#/PIRQD#
GNT#0/REQ#0
GNT#1/REQ#1
AD27/AD28
page 23 page 15
3 3
CardBus
OZ6933
PIRQA#/PIRQB#
GNT#3/REQ#3
AD15
Slot 0&1
page 16
IEEE 1394
GNT#2/REQ#2
page 29
Slot 0
page 29
PIRQC#
AD24
AC97
Interface
page 27
Power On/Off
Reset Circuit
page 28
DC/DC Interface
RTC Battery
page 22
I/O Buffer
page 21
4 4
Power Circuit
DC/DC
page
30,31,32,33
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
A
HA#[3..31]4
4 4
R64
1.5K
FERR#1.5
3 3
2 2
+3VS
C533 reserve for
Intel Celeron
1 1
,VIA recommend
SELPSB[1:0] STSEM BUS FREQUENCY
+3VSVCMOSVCMOS
R73
R67
10K
1.5K
1 2
1 2
1 2
2
13
Q5
FDV301N
HREQ#04
HREQ#14
HREQ#24
HREQ#34
HREQ#44
ADS#4
BSEL06
BSEL16,11
NMI3
00
01
10
11
R6 1K
12
R5 1K
12
R10 @1K
12
NMI
12
66MHZ
100MHZ
RESERVED
133MHZ
A
C139
1UF
FERR# 9
BREQ0#4
BPRI#4
BNR#4
HLOCK#4
HIT#4
HITM#4
DEFER#4
HTRDY#4
RS#04
RS#14
RS#24
A20M#3
IGNNE#3
SMI#9
1 8
2 7
3 6
4 5
RP98
8P4R-1K
INTR3
STPCLK#9
HA#[3..31]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
ADS#
BREQ0#
BPRI#
BNR#
LOCK#
HIT#
HITM#
DEFER#
HTRDY#
RS#0
RS#1
RS#2
A20M#
FERR#1.5
IGNNE#
PWRGD_CPU
SMI#
PWRGD_CPU
PREQ#
PRDY#
INTR
STPCLK#
SLP#
THERMDA
THERMDC
AK8
AH12
AH8
AN9
AL15
AH10
AL9
AH6
AK10
AN5
AL7
AK14
AL5
AN7
AE1
AG3
AC3
AE3
AB6
AB4
AF6
AA1
AK6
AA3
AD4
AC1
AF4
AK18
AH16
AH18
AL19
AL17
AN23
AN31
AK24
AL11
AN13
B36
AE35
AN29
AN17
AH14
AK20
AL25
AL23
AN19
G33
E37
C35
E35
AN25
AH26
AH22
AK28
AC37
AE33
AC35
AG37
AK26
AJ35
AN37
AN35
AK32
AN33
AL33
A35
AJ33
AJ31
M36
AG35
AH30
AL31
AL29
AJ1
W3
J37
L37
Z6
Y3
Z4
X6
V4
X2
U38A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RP#
ADS#
AERR#
AP0#
AP1#
BERR#
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BR1#/RSVD*
HIT#
HITM#
DEFER#
BP2#
BP3#
BPM0#
BPM1#
TRDY#
RS0#
RS1#
RS2#
RSP#
A20M#
FERR#
IGNNE#
PWRGOOD
SMI#
TDO
TDI
TMS
TRST#
TCK
PREQ#
PRDY#
BSEL0
BSEL1
INTR/LINT0
NMI/LINT1
STPCLK#
SLP#
THERMDA
THERMDC
FC-PGA2
B
B
FC-PGA2
REQUEST
PHASE
SIGNALS
ERROR
SIGNALS
ARBITRATION
PHASE
SIGNALS
SNOOP PHASE
SIGNALS
RESPONSE
PHASE
SIGNALS
PC
COMPATIBILITY
SIGNALS
DIAGNOSTIC
& TEST
SIGNALS
EXECUTION
CONTROL
SIGNALS
THERMAL DIODE
* For Intel New CPU
PROPRIETARY NOTE
C
HD#[0..63]
HD#0
W1
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
DATA
PHASE
SIGNALS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DBSY#
DRDY#
PICCLK
PICD1
PICD0
INIT#
FLUSH#
RESET#
RESET2#/VSS*
BCLK
EDGCTRL/VTT*
T4
N1
M6
U1
S3
T6
J1
S1
P6
Q3
M4
Q1
L1
N3
U3
H4
R4
P4
H6
L3
G1
F8
G3
K6
E3
E1
F12
A5
A3
J3
C5
F6
C1
C7
B2
C9
A9
D8
D10
C15
D14
D12
A7
A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16
C33
C31
A33
A31
E31
C29
E29
A29
AL27
AN27
J33
L35
J35
AG33
AE37
AH4
X4
W37
AG1
CPU_IO
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
DBSY#
DRDY#
R117 150
R131 150
CPUINIT#
FLUSH#
CPURST#
1 2
R396 1K
2
Q56
1 3
FDV301N
C
R94 1K
HD#[0..63] 4
12
C80
2200PF
PWRGD_CPU
VR_POK9,27,32
IGNNE#
A20M#
INTR
NMI
PRDY#
SLP#
CPUINIT#
STPCLK#
FLUSH#
SMI#
PREQ#
CPURST#
ADS# HD#19
DBSY# 4
DRDY# 4
APICCLK 11
VCMOS
CPUINIT# 9
R97 10
TUAL5 3,11,32
D7
RB751V
RP26
1 8
2 7
3 6
4 5
8P4R-150
1 2
R151 150
1 2
R54 150
1 2
R61 150
1 2
R53 150
1 2
R57 150
1 2
R47 150
1 2
R127 330
1 2
R26 56.2_1%
1 2
R7 @56.2_1%
CPURST# 4,9
HCLK_CPU 11SLP#9
C94
1 2
12
10PF
21
12
C79
.1UF
THERMDA
THERMDC
BREQ0#
RS#2
DBSY#
DRDY#
D
U6
1
NC
2
VCC
3
DXP
4
DXN
5
NC
6
ADD1
7
GND
8 9
GND NC
MAX1617
1 2
R27 180
1 2
R395 @1.8K
RP2
@8P4R-56
VCMOS
CPU_IO
D
1617VCC
SMBCLK
SMBDATA
ALERT
ADD0
18
27
36
45
HREQ#2
HREQ#0
HREQ#4
BPRI#
RS#1
HLOCK#
HREQ#3
DEFER#
RS#0
HIT#
HTRDY#
HITM#
HREQ#1
HA#7
BNR#
HA#14
E
+5VS
12
R90
200
NC
STBY
NC
+2.5V_CLK
HA#5
HA#13
HA#10
HA#12
HA#16
HA#15
HA#28
HA#31
HA#19
HA#25
HA#22
HA#17
HA#23
HA#24
HA#20
HA#27
HA#30
HA#29
HA#18
HA#26
16
15
14
13
12
11
10
R89
1K
12
+5VS
RP6
@8P4R-56
RP14
@8P4R-56
RP20
@8P4R-56
RP19
@8P4R-56
RP22
@8P4R-56
RP9
@8P4R-56
RP10
@8P4R-56
RP11
@8P4R-56
RP8
@8P4R-56
from 87570
SMC 18,20,24
SMD 18,20,24
ATF# 21
12
R96
1K
CPU_IO
HD#39
HD#36
HD#37
HD#38
HD#27
HD#42
HD#45
HD#44
HD#40
HD#41
HD#49
HD#51
HD#48
HD#63
HD#52
HD#47
HD#46
HD#55
HD#57
HD#59
HD#50
HD#58
HD#53
HD#54
HD#61
HD#56
HD#62
HD#60
HA#4
HA#8
HA#11
HA#9
HA#3
HA#6
HA#21
1 8
2 7
3 6
4 5
RP43
@8P4R-56
1 8
2 7
3 6
4 5
RP44
@8P4R-56
1 8
2 7
3 6
4 5
RP45
@8P4R-56
1 8
2 7
3 6
4 5
RP46
@8P4R-56
1 8
2 7
3 6
4 5
RP47
@8P4R-56
1 8
2 7
3 6
4 5
RP48
@8P4R-56
1 8
2 7
3 6
4 5
RP49
@8P4R-56
RP7
@8P4R-56
RP1
@8P4R-56
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
HD#1
HD#5
HD#8
HD#17
HD#0
HD#4
HD#15
HD#6
HD#12
HD#10
HD#9
HD#18
HD#14
HD#2
HD#3
HD#11
HD#13
HD#20
HD#7
HD#16
HD#24
HD#30
HD#22
HD#43
HD#34
HD#32
HD#28
HD#31
18
HD#25
27
HD#29
36
HD#35
45
HD#23
18
HD#21
27
HD#26
36
HD#33
45
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
234, 22, 2001
E
RP25
@8P4R-56
RP24
@8P4R-56
RP28
@8P4R-56
RP27
@8P4R-56
RP31
@8P4R-56
RP30
@8P4R-56
1 8
2 7
3 6
4 5
RP42
@8P4R-56
1 8
2 7
3 6
4 5
RP41
@8P4R-56
1 8
2 7
3 6
4 5
RP40
@8P4R-56
of
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
1B
A
U38B
R353
56_1%
R149
110_1%
12
12
12
C83
.1UF
AD36
Z36
E33
F18
AD6
AK12
AK22
AA37
AA5
AB2
AB34
AD32
AE5
F14
F22
F26
F30
F34
H32
H36
K32
K34
M32
P34
R32
R36
T34
V32
V36
X34
Y35
Z32
AF2
AF34
AH24
AH32
AH36
AJ13
AJ17
AJ21
AJ25
AJ29
AJ5
AK2
AK34
AM12
AM16
AM20
AM24
AM28
AM32
AM4
AM8
B10
B14
B18
B22
B26
B30
B34
D20
D24
D28
D32
D36
E13
E17
AJ9
S35
E27
AH28
Y33
K4
R6
V6
E5
E9
F2
F4
J5
K2
N5
P2
S5
T2
W5
B6
C3
D6
VCC1.5/VTT*
VCC2.5/RSVD*
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7/VCMOS_REF*
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33/VTT*
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
RTTCTRL
SLEWCTRL
THERMTRIP#
CLKREF/BCLK#*
FC-PGA370
CPU_IO
4 4
CPU_IO
VCMOS
3 3
TUALDET
2 2
1 1
R150
1 2
75_1%
R400
1 2
75_1%
12
R402
10K
2
B
Q58
FMMT3904
VCCTREF
12
R118
150_1%
VCMOSREF
12
R401
150_1%
+5V
12
R403
2.7K
2
1
C
E
3
+2.5V_CLK
VCCTREF
12
C166
.1UF
12
C501
.1UF
12
R404
2.7K
13
Q57
FDV301N
R91
150_1%
A
12
.1UF
VCCTREF
VCMOSREF
12
12
12
C110
C144
.1UF
.1UF
4.7UF_0805
CPU_CORE
CPU_IO
TUAL5 2,11,32
TUAL5# 11
12
R78
150_1%
1 2
C181
C60
CLKREF
12
C70
4.7UF_0805
B
VSS5/DYN_OE*
FC-PGA370
POWER,
GROUND,
RESERVED
SIGNALS
VSS46/DETECT*
VSS55/RESET2#*
VSS57/VID_25mV*
VSS58/VTT_PWRGD*
VSS59/RSVD*
VEDT/RSVD*
VCCCMOS/VTT*
* For Intel New CPU
B
VSS0
VSS1
VSS2
VSS3
VSS4
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS56
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
PLL1
PLL2
CPUPRES#
AM22
AM26
AM30
AM34
AM6
AN3
B12
B16
B20
B24
B28
B32
B4
B8
D18
D2
D22
D26
D30
D34
D4
E11
E15
E19
E7
F20
F24
F28
F32
F36
G5
H2
H34
K36
L5
M2
M34
P32
P36
A37
AB32
AC33
AC5
AD2
AD34
AF32
AF36
AG5
AH2
AH34
AJ11
AJ15
AJ19
AJ23
AJ27
AJ3
AJ7
AK36
AK4
AL1
AL3
AM10
AM14
AM18
Q5
R34
T32
T36
U5
V2
V34
X32
X36
Y37
Y5
Z2
Z34
W33
U33
E21
AB36
C37
DYN_OE
12
C186
.1UF
TUALDET
CPU_CORE
VID4
1 2
R405 1K
CPU_CORE
VCCT
VSST
12
C203
.1UF
R397
1K
1 2
12
C218
.1UF
12
C185
.1UF
CPU_CORE
CPU_CORE
+
C457
220UF_E
6.3V
12
C109
.1UF
CPU_IO
C
CPU_IO
12
12
C216
C217
.1UF
.1UF
12
12
C5
C141
.1UF
.1UF
12
12
C427
C429
1UF
12
12
C412
C421
1UF
12
12
C101
C88
.1UF
.1UF
VTTPWRGD 11,32
CPU_CORE
12
C160
.1UF
+
C178
220UF_E
6.3V
1 2
L18 4.7Uh_0805
+
C140
33UF_6.3X2.5
CPU_CORE
CPU_CORE
C
12
C215
.1UF
12
C119
.1UF
12
C434
1UF
1UF
12
C411
1UF
1UF
12
C425
.1UF
12
12
C164
C167
.1UF
.1UF
+
12
C417
4.7UF_1206
+
C422
220UF_E
6.3V
12
C214
.1UF
12
C111
.1UF
12
C445
1UF
12
C410
1UF
12
C76
.1UF
12
.1UF
C449
220UF_E
6.3V
12
C438
4.7U_1206
12
C213
.1UF
12
C9
.1UF
+
C6
220UF_E
12
C446
1UF
12
C414
1UF
12
C63
.1UF
C165
CPU_CORE
+
C458
220UF_E
6.3V
12
.1UF
PROPRIETARY NOTE
12
12
C211
C212
.1UF
.1UF
12
12
C47
C11
.1UF
.1UF
CPU_IO
12
C10
.1UF
12
12
C442
C441
1UF
1UF
12
12
C416
C415
1UF
1UF
12
12
C62
C61
.1UF
.1UF
12
C170
C168
.1UF
+
C116
220UF_E
6.3V
12
C418
4.7U_1206
+
C459
220UF_E
6.3V
AH20
AK16
AL13
AL21
AN11
AN15
G35
AA33
AA35
AN21
U35
U37
E23
S33
S37
U38C
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
D
FC-PGA370
POWER AND NC
RSVD/VTT*
RSVD
RSVD
RSVD
RSVD/NCHCTRL*
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD/KEY*
RSVD
VID0
VID1
VID2
VID3
G37
L33
N33
N35
N37
Q33
Q35
Q37
R2
W35
Y1
AK30
AM2
F10
AL35
AM36
AL37
AJ37
NCHCTRL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CPU_IO
CPU_IO CPU_IO
12
12
C210
C209
.1UF
.1UF
CPU_IO
12
C12
.1UF
VID0
VID1
VID2
VID3
CPU_IO
12
E
R398
14_1%
VID1
VID2
VID0
VID3
VID4
R399 10K
* For Intel New CPU
FC-PGA370
12
12
12
12
C443
C444
C428
1UF
12
C77
.1UF
12
C172
.1UF
+
C150
220UF_E
6.3V
12
C420
4.7U_1206
12
C173
.1UF
+
C134
220UF_E
6.3V
1UF
12
C151
1UF
12
C87
.1UF
12
C162
.1UF
+
C135
220UF_E
6.3V
12
C431
4.7U_1206
12
C142
1UF
12
C120
.1UF
C433
1UF
12
C156
.1UF
12
C437
4.7U_1206
+
C404
220UF_E
6.3V
12
C117
1UF
12
C149
.1UF
1UF
12
C169
.1UF
R166
SB_A20M#
SB_IGNNE#
VCMOS
RP58
@8P4R_1K
1 8
2 7
3 6
4 5
SB_A20M#9
SB_IGNNE#9
SB_INTR9
SB_NMI9
12
12
12
12
CRESET#4
R175
R165
@0
@0
@0
R162
@0
R168
0
R159
0
R157
0
R158
0
12
C430
4.7UF_1206
A20M#
IGNNE#
12
4.7UF_1206
1 2
1 2
SB_INTR
1 2
SB_NMI NMI
1 2
12
C426
4.7U_1206
+
C400
220UF_E
6.3V
D
VID[0..4]32
U18
2
IOA
SB_A20M#
SB_IGNNE#
SB_INTR
SB_NMI
CRESET#
11
10
14
13
VCC
3
IOA
5
IOB
6
IOB
I1C
I1C
I1D
I1D
1
S
GND
@QS3257
SW1 RATIO SELECT
INTR
C435
12
C439
4.7UF_1206
RATIO
3.5X
4.5X
5.5X
6.5X
7.5X
ON
3X
ON
OFF
4X
OFF
OFF
5X
OFF
ON
6X
ON
ON
7X
ON
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
VID[0..4]
+3VS
C266
1 2
16
4
YA
7
YB
9
YC
12
YD
8
15
E#
@.1UF
A20M#
IGNNE#
INTR
NMI
1 2
R172 @1K
1234
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
ON
ON
OFF
OFF
OFF
334, 22, 2001
E
RP13
1 8
2 7
3 6
4 5
8P4R-10K
1 2
A20M# 2
IGNNE# 2
INTR 2
NMI 2
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
of
+5V
1B
A
HD#[0..63]
4 4
3 3
2 2
HCLK_NB11
HD#[0..63]
HD#[0..63] 2
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
U14A
E19
HD0#
B18
HD1#
B16
HD2#
A16
HD3#
C18
HD4#
C17
HD5#
D18
HD6#
D15
HD7#
D17
HD8#
C16
HD9#
B17
HD10#
D16
HD11#
A17
HD12#
A15
HD13#
E16
HD14#
D19
HD15#
A14
HD16#
E18
HD17#
E17
HD18#
B14
HD19#
C15
HD20#
E14
HD21#
B11
HD22#
D14
HD23#
B15
HD24#
D13
HD25#
C13
HD26#
E9
HD27#
C12
HD28#
D12
HD29#
E15
HD30#
A13
HD31#
B12
HD32#
B13
HD33#
A12
HD34#
E13
HD35#
D11
HD36#
D10
HD37#
A11
HD38#
E10
HD39#
E8
HD40#
C9
HD41#
D9
HD42#
C11
HD43#
B10
HD44#
A10
HD45#
E7
HD46#
D8
HD47#
B8
HD48#
C10
HD49#
B6
HD50#
B9
HD51#
F8
HD52#
D6
HD53#
D7
HD54#
C7
HD55#
E5
HD56#
A7
HD57#
E6
HD58#
B7
HD59#
C6
HD60#
D5
HD61#
A6
HD62#
A8
HD63#
G22
HCLKIN
VT8606
R130
10
1 2
12
C182
10PF
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
ADS#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
BREQ0#
BPRI#
BNR#
HLOCK#
HIT#
HITM#
DEFER#
DBSY#
DRDY#
HTRDY#
RS#0
RS#1
RS#2
CPURST#
CPURSTD#
GTL_REFA
GTL_REFB
A25
D24
B25
B26
E23
C26
C24
A23
C25
D22
B24
D25
F22
C23
D21
A20
C22
A21
B23
A22
B21
E20
B22
B19
C20
A24
B20
D20
C21
J24
E24
F23
F24
F25
E25
J25
E26
D26
G23
G24
G26
F26
H26
J23
G25
H23
K23
H25
A19
E22
E12
E21
B
R111
@0
HA#[3..31]
12
HA#[3..31]
VCCT_REF
ADS# 2
HREQ#0 2
HREQ#1 2
HREQ#2 2
HREQ#3 2
HREQ#4 2
BREQ0# 2
BPRI# 2
BNR# 2
HLOCK# 2
HIT# 2
HITM# 2
DEFER# 2
DBSY# 2
DRDY# 2
HTRDY# 2
RS#0 2
RS#1 2
RS#2 2
CPURST# 2,9
CRESET# 3
HA#[3..31]2
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
C
+
C223
150UF_E_4V
12
C113
4.7UF_1206
12
C126
.1UF
12
C171
.1UF
12
C129
.1UF
12
C248
.1UF
12
C131
.1UF
12
C249
.1UF
12
C196
.1UF
12
C208
.1UF
12
C201
.1UF
12
C200
.01UF
12
C159
.1UF
12
C127
.01UF
12
C250
.01UF
12
C132
.01UF
12
C128
.01UF
D
12
C130
.01UF
+2.5VS
M18
R18
U18
AF26
AF18
AF9
AF1
AD19
AD13
AD8
AC23
AC4
AA15
AA14
AA13
AA21
AA6
W24
E
U14E
J9
VCC25
J10
VCC25
J11
VCC25
J12
VCC25
J15
VCC25
J16
VCC25
J17
VCC25
J18
VCC25
K9
VCC25
K18
VCC25
L9
VCC25
L18
VCC25
M9
VCC25
VCC25
R9
VCC25
VCC25
T9
VCC25
T18
VCC25
U9
VCC25
VCC25
V9
VCC25
V10
VCC25
V11
VCC25
V12
VCC25
V15
VCC25
V16
VCC25
V17
VCC25
V18
VCC25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V26
GND
V14
GND
V13
GND
T21
GND
T16
GND
T15
GND
T14
GND
T13
GND
T12
GND
VT8606
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A9
A18
A26
B2
C8
C14
C19
D4
D23
F6
F13
F14
F16
F21
H24
J13
J14
J26
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
M21
N3
N6
N9
N11
N12
N13
N14
N15
N16
N18
N21
P1
P6
P9
P11
P12
P13
P14
P15
P16
P18
P21
R11
R12
R13
R14
R15
R16
T11
VCCT_REF
CPU_IO
1 1
75_1%
12
R122
150_1%
R125
1 2
12
1UF
C158
VCCT_REF
12
C153
.1UF
12
C148
1000PF
12
C143
4.7UF_0805
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL
ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.
THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION
OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
A
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
E
of
434, 22, 2001
1B
A
+3VS
12
12
12
12
C133
C118
.1UF
4.7UF_1206
4 4
12
12
C92
C98
.1UF
4.7UF_1206
12
12
C503
C502
.1UF
3 3
2 2
1 1
4.7UF_1206
+3V
REQ#4
GNT#4
2 1
1 2
R212 10K
1 2
R211 10K
C232
.1UF
12
C95
.1UF
12
C504
.1UF
D42
1N4148
A
12
C267
.1UF
C96
.1UF
12
.1UF
C505
+3VS
12
.1UF
12
.1UF
12
C256
C154
12
.1UF
C506
C465
.1UF
CPU_IO
AA10
AA17
AA18
AA20
AA22
W22
AB22
R21
U21
V21
Y21
AA7
AA9
E11
F10
F12
F17
F18
F19
F20
G21
K21
V22
U14C
G6
VCC3
H6
VCC3
J6
VCC3
L4
VCC3
VCC3
T4
VCC3
VCC3
V6
VCC3
VCC3
W6
VCC3
VCC3
Y6
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VTT
F7
VTT
F9
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
J21
VTT
VTT
25VSUS
U6
NC1
NC2
NC3
NC4
VT8606
+3VS
PWRGOOD
REQ#3
GNT#0
REQ#0
REQ#1
CLKRUN#
PCI REQ ASSIGMENT
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
MiniPCI(Compal)
MINI PCI
1394
PCMCIA CONTROLLER
NO USED
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
PAR
STOP#
SERR#
LOCK#
WSC#
REQ0#
REQ1#
REQ2#
REQ3#
REQX#
PREQ#
GNT0#
GNT1#
GNT2#
GNT3#
GNTX#
PGNT#
SUSTAT#
PCIRST#
PCICLK
AF14
AE14
AE13
AF13
AC14
AB14
AC13
AB13
AE12
AD12
AB12
AC12
AF11
AE11
AD11
AC11
AA8
AC9
AF8
AE8
AE7
AB8
AF7
AC8
AC7
AB7
AF6
AE6
AD6
AC6
AB6
AF5
AF12
AB11
AD9
AD7
AE9
AC10
AD10
AB9
AB10
AE10
AF10
AE5
AA11
AC5
AD5
AE4
AD4
AF2
AC15
AB5
AF4
AF3
AE3
AE2
AD15
AC22
AD14
AE15
AF15
AB15
B
10
B
RP63
6
7
8
9
10P8R-10K
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
SERR#
1 2
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
GNT#0
GNT#1
GNT#2
GNT#3
GNT#4
SUS_STAT#
NBPWROK
R274
0
CLKRUN#
R210
1 2
12
C255
15PF
AD[0..31]
R221
4.7K
47
5
4
3
2
1
SUS_STAT#
STANDBY
AGP_BUSY#
SUSSTAT#
ZV8
ZV11
ZV10
ZV9
SUSPEND
C/BE#0 9,15,23,28
C/BE#1 9,15,23,28
C/BE#2 9,15,23,28
C/BE#3 9,15,23,28
FRAME# 9,12,15,23,28
IRDY# 9,12,15,23,28
TRDY# 9,12,15,23,28
DEVSEL# 9,12,15,23,28
PAR 9,12,15,23,28
STOP# 9,12,15,23,28
SERR# 9,12,15,23,28
PLOCK# 12,15
+3VS
REQ#0 23
REQ#1 23
REQ#2 28
REQ#3 15
PCIREQ# 9,12
GNT#0 23
GNT#1 23
GNT#2 28
GNT#3 15
PCIGNT# 9,12
12
PCIRST# 9,13,15,16,19,23,28
CLKRUN# 9,12,15,23,28
PCLK_NB 11
GNT#2
GNT#3
GNT#1
REQ#2
RP29
1 8
2 7
3 6
4 5
8P4R_4.7K
AD[0..31] 9,15,23,28
RP39
6
7
8
9
10
10P8R-100K
1 2
R392 @1K
SUS_STAT# 9
SPWROFF# 9,20,27
+3VS
+3VS
5
4
3
2
1
+3V POWER
C
PIRQA#9,12,15
+3VS
VGASUSP20
R391
@10K
1 2
SMDTV13
SMCTV13
TXOUT0-14
TXOUT0+14
TXOUT1-14
TXOUT1+14
TXOUT2-14
TXOUT2+14
TXCLKO-14
TXCLKO+14
TZOUT0-14
TZOUT0+14
TZOUT1-14
TZOUT1+14
TZOUT2-14
TZOUT2+14
TZCLKO-14
TZCLKO+14
+3VS
+2.5VS
ZV12
ZV15
ZV13
ZV14
SUS_STAT#
4
56
U28B
74LVC125
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL
ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.
THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION
OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
AGP_BUSY#
1 2
R119 0
1 2
R390
0
ZV8
ZV9
ZV10
ZV11
ZV12
ZV13
ZV14
ZV15
1 2
R147 100K
LVDD
PLLVDD
+LAVDD
R110
1K
14MCRT11
L19
1 2
CHB2012U121_0805
C123
.1UF
CHB2012U121_0805
SUSSTAT#SUS_STAT#
SUSPEND
STANDBY
12
12
R109
1K
L28
1 2
C219
.1UF
12
D
T=40iml
12
C124
.1UF
12
D
W5
B4
C4
F5
F4
R6
T2
T1
R5
R2
R4
R1
R3
P5
P2
P3
P4
N5
N2
N1
N4
T3
U1
U3
F2
F3
AB3
AA3
Y4
W4
AA5
Y5
AC1
AB1
AD2
AC2
AD3
AC3
AB4
AA4
AE1
AD1
W1
W2
AB2
Y2
Y1
AA1
Y3
AA2
F15
F11
A2
A3
T=20iml
U14D
INTA#
AGP_BUSY#
STP_AGP#
SUSPEND
STANDBY
ZVD0
ZVD1
ZVD2
ZVD3
ZVD4
ZVD5
ZVD6
ZVD7
ZVD8
ZVD9
ZVD10
ZVD11
ZVD12
ZVD13
ZVD14
ZVD15
ZVHS
ZVVS
ZVCLK
SPD1
SPCLK1
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
YCM
YCP
Z0M
Z0P
Z1M
Z1P
Z2M
Z2P
ZCM
ZCP
LVDSVCCA
LVDS1VCCA
PLLVCCA
VCCLVDS
LVDSGND
LVDS1GND
PLLGND
GNDLVDS
BISTIN
DFTIN
XTALI
XTALO
VT8606
12
C114
10UF_1206
12
E
12
C125
1000PF
+LAVDD+2.5VS
C227
10UF_1206
TVD11/PD0
TVD10/PD1
PD2
PD3
PD4
PD5
PD6
PD7
TVD9/PD8
TVD8/PD9
PD10
PD11
PD12
PD13
PD14
PD15
TVCLKR/PD16
TVBLANK/PD17
PD18
PD19
PD20
PD21
PD22
PD23
TVD6/PD24
TVD4/PD25
TVD5/PD26
TVD7/PD27
TVD0/PD28
TVD1/PD29
TVD3/PD30
TVVS/PD31
TVCLK/PD32
TVD2/PD33
TVHS/PD34
PD35
PANELDEN
PANELCLK
PANELVS
PANELHS
ENVDD
ENVEE
GOP0
FPGPIO
STRW/GPOUT
PANELDET
SPCLK2
SPD2
RED
GREEN
BLUE
HSYNC
VSYNC
RSET
COMP
VCCDAC
VCCRGB
GNDDAC
GNDRGB
VCCPLL1
VCCPLL2
GNDPLL1
GNDPLL2
+2.5VS
PLLVDD
G2
H2
H1
J2
J1
H4
K6
J4
J3
L5
K2
J5
K1
K3
L6
L2
K5
L1
L3
M6
K4
M4
M5
M1
T6
T5
U4
U2
V1
V2
V3
W3
V4
U5
V5
C5
H3
G4
G3
G5
F1
H5
C3
G1
AA12
AA16
M2
M3
C2
D3
D2
E2
E1
R121
140_1%
E3
E4
C1
D1
B1
A1
B3
A5
A4
B5
1 2
CHB2012U121_0805
CHB2012U121_0805
1 2
R222
4.7K
1 2
1 2
C161
.1UF
PLLVDD
L20
L35
1 2
TVD11 13
TVD10 13
TVD9 13
TVD8 13
R129
22
TVD6 13
TVD4 13
TVD5 13
TVD7 13
TVD0 13
TVD1 13
TVD3 13
TVVS 13
TVCLK 13
TVD2 13
TVHS 13
ENVDD 14
ENVEE 14,21
BLON# 14
DDC_CLK 14
DDC_DATA 14
R14
G14
B14
HSYNC1 14
VSYNC1 14
1 2
+DACVDD
+DACVDD
T=40iml
12
C155
.1UF
T=40iml
12
C234
.1UF
TVCLKR 13
12
C146
10UF_1206
12
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
E
12
C174
1000PF
C233
10UF_1206
of
534, 22, 2001
+DACVDD
LVDD+3VS
1B
A
B
C
D
E
MD[0..63]
4 4
U14B
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
M23
K25
L26
L25
M26
M24
N26
N24
P23
P25
R23
R25
P22
T23
T25
T22
AD22
AF22
AB21
AE21
AB20
AD20
AE20
AC19
AF19
AC18
AE18
AD17
AF17
AB17
AE16
AC16
K26
L23
M22
L24
M25
N23
N25
N22
P26
P24
R26
R24
R22
T26
T24
U23
AE22
AC21
AD21
AF21
AC20
AF20
AB19
AE19
AB18
AD18
AA19
AE17
AC17
AD16
AF16
AB16
MDD1
MDD2
MDD3
MDD4
MDD5
MDD6
MDD7
MDD8
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32
MDD33
MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58
MDD59
MDD60
MDD61
MDD62
MDD63
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
1 2
T=40iml
12
Y26
Y25
Y24
Y23
Y22
W21
V23
W23
AF24
AE23
W26
W25
AD23
AF23
U24
U25
U26
AA24
AA25
AA26
U22
V25
V24
AA23
AB23
AB26
AB25
AB24
AC26
AC25
AC24
AD26
AD25
AE26
AD24
AE24
AE25
AF25
K22
H21
H22
K24
R354
4.7K
C451
.1UF
J22
L21
L22
RAS0#/CS0#
RAS1#/CS1#
RAS2#/CS2#
RAS3#/CS3#
RAS4#/CS4#
RAS5#/CS5#
DQM0/CAS0#
DQM1/CAS1#
DQM2/CAS2#
DQM3/CAS3#
DQM4/CAS4#
DQM5/CAS5#
DQM6/CAS6#
DQM7/CAS7#
SWEA#
SWEB#/CKE2
SWEC#/CKE0
SRASA#
SRASB#/CKE5
SRASC#/CKE4
SCASA#
SCASB#/CKE3
SCASC#/CKE1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
DCLKO
DCLKI
VCCA
VCCA
GNDA
GNDA
PLLTEST
VT8606
12
C448
10UF_1210
VCCA
B
RRAS#07
RRAS#28
RRAS#38
RCAS#07,8
RCAS#17,8
RCAS#27,8
RCAS#37,8
RCAS#47,8
RCAS#57,8
RCAS#67,8
RCAS#77,8
RMWEA#7,8
CKE28
CKE07
3 3
2 2
1 1
DCLKO11
DCLKWR11
SRASA#7,8
SCASA#7,8
CKE38
C187
10PF
1 2
R134
33
VCCA
@15
@47PF
1 2
CHB2012U121_0805
DCLKO1
L23
1 2
R137
1 2
12
C189
+2.5VS
A
MDD0
MDD5
8 9
MDD0
7
MDD34
6
MDD6
5
MDD38
4
MDD7 MD7
3
MDD37
2
MDD39
1
MDD10
8 9
MDD44
7
MDD45
6
MDD14
5
MDD46
4
MDD13
3
MDD15
2
MDD47 MD47
1
MDD20
8 9
MDD52
7
MDD21
6
MDD22 MD22
5
MDD53
4
MDD58
3
MDD54
2
MDD23
1
MDD27
8 9
MDD59
7
MDD28
6
MDD62
5
MDD30
4
MDD61
3
MDD31
2
MDD63
1
MDD1
8 9
MDD32
7
MDD33
6
MDD35
5
MDD3
4
MDD2
3
MDD36
2
MDD4
1
MDD40
8 9
MDD9
7
MDD41
6
MDD8
5
MDD12
4
MDD42
3
MDD11
2
MDD43
1
MDD16
8 9
MDD48 MD48
7
MDD17
6
MDD18
5
MDD49 MD49
4
MDD50
3
MDD19
2
MDD51 MD51
1
MDD55
8 9
MDD24
7
MDD56
6
MDD25
5
MDD57
4
MDD26
3
MDD29
2
MDD60
1
MA0
8 9
MA1
7
MA2
6
MA3
5
MA4
4
MA5
3
MA6
2
MA7
1
MA8
8 9
MA9
7
MA11
6
MA10
5
MA12
4
MA13
3
MA14
2
1
MMA[0..14]7,8
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
MMA[0..14]
MD[0..63] 7,8
MD5
MD0
MD34
MD6
MD38
MD37
MD39
MD10
MD44
MD45
MD14
MD46
MD13
MD15
MD20
MD52
MD21
MD53
MD58
MD54
MD23
MD27
MD59
MD28
MD62
MD30
MD61
MD31
MD63
MD1
MD32
MD33
MD35
MD3
MD2
MD36
MD4
MD40
MD9
MD41
MD8
MD12
MD42
MD11
MD43
MD16
MD17
MD18
MD50
MD19
MD55
MD24
MD56
MD25
MD57
MD26
MD29
MD60
MMA0
MMA1
MMA2
MMA3
MMA4
MMA5
MMA6
MMA7
MMA8
MMA9
MMA11
MMA10
MMA12
MMA13
MMA14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL
ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.
THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION
OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
RP53
16P8R-22
RP56
16P8R-22
RP34
16P8R-22
RP50
16P8R-22
RP54
16P8R-22
RP62
16P8R-22
RP38
16P8R-22
RP33
16P8R-22
RP57
16P8R-22
RP61
16P8R-22
MA0
MA1
MA13
MA14
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA12
MA9
MA11
R170 10K
MA8
1 2
R185 10K
MA12
1 2
R362 @10K
1 2
R364 @10K
1 2
R370 @10K
1 2
R368 @10K
1 2
R366 @10K
1 2
R361 @10K
1 2
R363 @10K
1 2
R365 @10K
1 2
R164 10K
1 2
R167 @10K
1 2
R174 @10K
1 2
R369 @10K
1 2
R180 @10K
1 2
R367 @10K
1 2
D
+3VS
+3VS
+3VS
+3VS
BSEL0 2
BSEL1 2,11
Strap Description Setting
MA12,8 CPU Clcok Frequency
MA2 PCI Base Address Mapping
MA3 Graphic IO Enable/Disable
MA4 PCI Interrupt
MA7 Graphic Test Mode
MA9 VGA Clock Select
MA11 IOQ Level
MA0,1,13,14 Panel Type
01=100Mhz
11=133Mhz
00=66Mhz
0=Map0
1=Map1
0=Enable
1=Disable
0=Enable
1=Disable
0=Normal
1=Test
0=PLL
1= External
0=4Level
1=1Level
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
401202
Custom
!"# $%
Date: Sheet
634, 22, 2001
E
1B
of
A
+3V
B
C
+3V
D
E
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15DQML
CKE
RVD
RVD
CLK
U44
4
5
7
8
10
11
13
42
44
45
47
48
50
51
5315
37
38
36
40
8MX16S
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15DQML
CKE
CLK
RVD
RVD
U43
4
5
7
8
10
11
13
42
44
45
47
48
50
51
5315
37
38
36
40
8MX16S
BANK0
MD11 MMA10 MD42
MD13 MMA12 MD44
MD14
CKE0 6
MMA14
RMWEA#6,8
SCASA#6,8
SRASA#6,8
RRAS#06
CLK_SDRAM0 11
R286
@10
C330
@15PF
MMA0 MD16
MMA1 MD17
MMA2 MD18 MMA0 MD48
MMA3 MD19 MMA1 MD49
MMA4 MD20 MMA2 MD50
MMA5 MD21 MMA3 MD51
MMA6 MD22 MMA4 MD52
MMA7 MD23 MMA5 MD53
MMA8 MD24 MMA6 MD54
MMA9 MD25 MMA7 MD55
MMA10 MD26 MMA8 MD56
MMA13
MMA12 MD28 MMA10 MD58
MMA11
RCAS#2 MD31
RCAS#3 MD62
RMWEA# CKE0 RCAS#6 MD63
SCASA# CLK_SDRAM0 RCAS#7
SRASA# RMWEA# CKE0
RRAS#0 SCASA# CLK_SDRAM0
+3V
11427394349
23 2
A0 DQ0
24
25
26
29
30
31
32
33
34
22
35
21
20
39
16
17
18
19
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BA1
A13/BA0
DQMH
WE#
CAS#
RAS#
CS#
VCC
VCC
VCC
VCCQ
VCCQ
VCCQ
VSS
VSS
VSS
VSSQ
VSSQ
2841546124652
VCCQ
VSSQ
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15DQML
CKE
CLK
RVD
RVD
MMA13
MMA11
RRAS#0
U42
4
5
7
8
10
11
13
42
44
45
47
48
50
51
5315
37
38
36
40
8MX16S
MMA14
11427394349
23 2
A0 DQ0
24
25
26
29
30
31
32
33
34
22
35
21
20
39
16
17
18
19
MD27 MMA9 MD57
MD29
MD30 MMA12 MD60
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BA1
A13/BA0
DQMH
WE#
CAS#
RAS#
CS#
VCC
VCC
VCC
VCCQ
VCCQ
VSS
VSS
VSS
VSSQ
2841546124652
VCCQ
VCCQ
VSSQ
VSSQ
MD43
MD45
MMA14
MMA0 MD0
MMA1 MD1 MMA0 MD32
MMA2 MD2 MMA1 MD33
MMA3 MD3 MMA2 MD34
MMA4 MD4 MMA3 MD35
MMA5 MD5 MMA4 MD36
1 1
MMA6 MD6 MMA5 MD37
MMA7 MD7 MMA6 MD38
MMA8 MD8 MMA7 MD39
MMA9 MD9 MMA8 MD40
MMA10 MD10 MMA9 MD41
MMA13
MMA12 MD12
MMA11
RCAS#0 MD15 MD46
RCAS#1 RCAS#4 MD47
RMWEA# CKE0 RCAS#5
SCASA# CLK_SDRAM0 RMWEA# CKE0
SRASA# SCASA# CLK_SDRAM0
RRAS#0 SRASA#
2 2
MMA[0..14]6,8
11427394349
23 2
A0 DQ0
24
25
26
29
30
31
32
33
34
22
35
21
20
39
16
17
18
19
RCAS#[0..7]6,8
VCC
VCC
VCC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BA1
A13/BA0
DQMH
WE#
CAS#
RAS#
CS#
MD[0..63]6,8
VCCQ
VCCQ
VCCQ
VSS
VSS
VSS
VSSQ
VSSQ
2841546124652
MMA[0..14]
MD[0..63]
RCAS#[0..7]
VCCQ
VSSQ
64/128MB SDRAM
+3V
11427394349
23 2
A0 DQ0
MMA13
MMA11
SRASA#
RRAS#0
24
25
26
29
30
31
32
33
34
22
35
21
20
39
16
17
18
19
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BA1
A13/BA0
DQMH
WE#
CAS#
RAS#
CS#
VCC
VCC
VCC
VCCQ
VCCQ
VSS
VSS
VSS
VSSQ
2841546124652
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15DQML
CKE
CLK
RVD
RVD
U41
4
5
7
8
10
11
13
42
44
45
47
48
50
51
5315
37
38
36
40
8MX16S
MD59
MD61
MMA14
3 3
C339
.1UF
C329
1000PF
+3V
+3V
C335
.1UF
C350
1000PF
C365
.1UF
C392
1000PF
C362
.1UF
C343
1000PF
C338
.1UF
C482
1000PF
+3V
+3V
C485
.1UF
C384
1000PF
+3V
C351
C332
C368
C344
.1UF
.1UF
4 4
C352
1000PF
C393
1000PF
.1UF
C364
1000PF
+3V
C331
.1UF
C336
1000PF
.1UF
C367
1000PF
C389
.1UF
C363
1000PF
Compal Electronics, Inc.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
734, 22, 2001
E
of
1B
A
SO-DIM 144 PINS
B
C
D
E
RAM MODULE CONN.
MMA[0..14]6,7
1 1
2 2
3 3
4 4
MD[0..63]6,7
RCAS#[0..7]6,7
RRAS#[2..3]6
CLK_SDRAM211
SRASA#6,7
RMWEA#6,7
MMA[0..14]
MD[0..63]
RCAS#[0..7]
RRAS#[2..3]
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
RCAS#0
RCAS#4
MMA0 MMA3
MMA1 MMA4
MMA2 MMA5
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
R260
C298
33
22PF
RMWEA# CKE3
RRAS#2 MMA14
RRAS#3
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MMA6 MMA7
MMA8
MMA9 MMA12
MMA10
RCAS#2
RCAS#6
MD48
MD49
+3V +3V
MD50
MD51
R372
10K
SMBDATA9,11
MD52
MD53
MD54
MD55
BANK2/3
+3V +3V
JP20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65
RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
SO-DIMM144
RESVD/DQ68
RESVD/DQ69
RESVD/DQ70
RESVD/DQ71
CE6#/RESVD
CE7#/RESVD
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
CE4#
CE5#
VCC
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
RFU/CKE0
VCC
RFU
RFU/CKE1
RFU
RFU
RFU/CLK1
VSS
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A11/BA0
VSS
A12/BA1
A13/A11
VCC
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
A3
32
A4
34
A5
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
A7
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RCAS#1
RCAS#5
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
CKE2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MMA11
MMA13
RCAS#3
RCAS#7
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
CKE2 6
SCASA# 6,7
CKE3 6
R277
33
C319
22PF
R278
10K
CLK_SDRAM3 11
SMBCLK 9,11
+
C473
10UF_1206
6.3V
+3V
+
C483
.1UF
C472
10UF_1206
6.3V
C478
.01UF
C474
.1UF
+3V
1000PF
C479
C484
.1UF
C489
1000PF
C476
.1UF
C358
1000PF
C477
.01UF
1000PF
C487
C475
.01UF
C488
.01UF
DIMM1
Compal Electronics, Inc.
Title
PROPRIETARY NOTE
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
834, 22, 2001
E
of
1B
1
2
3
4
5
6
7
8
VT82C686A-A
12
R300 10K
12
R295 0
+3VS
SDA0 17
SDA1 17
SDA2 17
SDCS1# 17
SDCS3# 17
SDDACK# 17
SDDREQ 18
SDIOR# 17
SDIOW# 17
SDIORDY 18
SB_A20M# 3
FERR# 2
SB_IGNNE# 3
SB_INTR 3
SB_NMI 3
12
SMI# 2
STPCLK# 2
SMBCLK 8,11
SMBDATA 8,11
SPWROFF# 5,20,27
CPU_STP# 11
PCI_STP# 11
CLKRUN# 5,12,15,23,28
RSMRST# 27
12
R275 0
PX4_RI# 21
SPKR 26
EXTSMI# 20
ATF_INT# 20
IRQ8# 20
LID# 21
SCI# 20
SUSA# 11,20
SUSB# 20
SUSC# 20
RP83
18
27
36
45
8P4R_10K
12
R385 10K
C376
+
10UF_1210
+3VS
12
4
R306 @33
IAC_BITCLK 26
IAC_SDATAI 26
IAC_SYNC 26
IAC_SDATAO 26
IAC_RST# 26
+3VS
R247 0
R248 0
SLP# 2
RTCCLK 15,16
D25
RB751V
D28
2 1
RB751V
+5VS
FAN_SENSE 20,22
12
+3VS
1 2
12
C369 @22PF
Signals Pullup
+3V
RP92
1
2
3
4
5
10P8R-10K
12
12
21
VR_POK2,27,32
10
9
8
7
6
CPURST# 2,4
CPUINIT# 2
PCI_RST#
+3VS
SUS_STAT# 5
LLBATT# 21
+3VS
1
2
PBTN#
CLKRUN#
5
PCIRST#
4
U45
3
@7SH08FU
PCIRST#PCI_RST#
12
R394 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D29
2 1
@RB751V
D30
2 1
RB751V
R288 10K
R289 @1K
PCIRST# 5,13,15,16,19,23,28
ON/OFF 20,26
PBTN_OUT# 21
12
+3VS
12
+3VS
PBTN#
ATF_INT#
PX4_RI#
IRQ8#
LID#
SCI#
VLB#
SUSCLK
SUSA#
SPKR
NOTE:DISABLE INTERNAL
AUDIO CTRL
ACIN20,26,29
1 2
R319 10K
1 2
R318 @10K
Populate R318 and not
populate R319 When
100MHz SDRAM on board
Populate R319 and not
populate R318 When
133MHz SDRAM on board
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
5
6
Date: Sheet
7
RP86
1 8
2 7
3 6
4 5
8P4R_10K
1 8
2 7
3 6
4 5
RP82 8P4R_10K
R272 10K
R268 10K
R267 10K
12
R264 @10K
+3VS
12
13
2
12
+3V
12
12
R265
4.7K
ACIN_SYS#
Q40
2N7002
133M/100M#
934, 22, 2001
of
8
+3VS
1B
+3V
12
C279
.1UF
C311
.01UF
PCLK_SB
RTCX1
RTCX2
12
C360
.1UF
PDD[0..15]
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
PDDACK#
PDDREQ
PDIOR#
PDIOW#
PIORDY
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
SERR#
PAR
IDSEL
PCIREQ#
PCIGNT#
PCI_RST#
U30A
P16
PDD0
P18
PDD1
P20
PDD2
R17
PDD3
R19
PDD4
T16
PDD5
T18
PDD6
T20
PDD7
T19
PDD8
T17
PDD9
R20
PDD10
R18
PDD11
R16
PDD12
P19
PDD13
P17
PDD14
N20
PDD15
M17
PDA0
M19
PDA1
M18
PDA2
L20
PDCS1
M16
PDCS3
M20
PDDACK
N19
PDDREQ
N17
PDIOR
N18
PDIOW
N16
PDRDY
L17
AD0
L16
AD1
K20
AD2
K19
AD3
K18
AD4
K17
AD5
K16
AD6
J20
AD7
J18
AD8
J17
AD9
J16
AD10
H20
AD11
H19
AD12
H18
AD13
H17
AD14
H16
AD15
F16
AD16
E20
AD17
E19
AD18
E18
AD19
E17
AD20
D20
AD21
D19
AD22
D18
AD23
B20
AD24
A20
AD25
A19
AD26
B19
AD27
A18
AD28
B18
AD29
C18
AD30
A17
AD31
J19
C/BE0
G20
C/BE1
F17
C/BE2
C19
C/BE3
F18
FRAME
F19
IRDY
F20
TRDY
G17
STOP
G16
DEVSEL
G18
SERR
G19
PAR
C20
IDSEL
L18
REQ
L19
GNT
B16
PCIRST
A16
PINTA
D17
PINTB
C17
PINTC
B17
PINTD
E16
PCICLK
Y5
RTCX1
W5
RTCX2
R9
VCCSUS
R10
VCCSUS
Y6
VBAT
H15
VCC
J15
VCC
K15
VCC
M15
VCC
N15
VCC
R7
VCC
R8
VCC
R11
VCC
R14
VCC
VT82C686-B
2
SDD0/BITCLK
SDD3/SYNC
SDD4/SDOUT
SDD5/-ACRST
SDD10/JAB2
SDD11/JAB1
SDD12/JBB2
SDD13/JBB1
SDD14/MSO
CPUSTP/GPO4
PCISTP/GPO5
GPIOD/GPIO11
PME/GPI5/THRM
SUSST1/GPO6
BATLOW/GPI2
GPIOA/GPIO8
LID/APICREQ/GPI3
SMBALT/GPI6
SUSA/APICACK/GPO1
SUSB/APICCS/GPO2
VSENS4(12V)
VSENS3(5V)
VSENS1(2.0V)
VSENS2(2.2V)
FAN2/GPIOB/GPIO9
3
SDD1/SDIN
SDD2
SDD6/JBY
SDD7/JBX
SDD8/JAY
SDD9/JAX
SDD15/MSI
SDA0
SDA1
SDA2
SDCS1
SDCS3
SDDACK
SDDREQ
SDIOR
SDIOW
SDRDY
A20M
CPURST
FERR
IGNNE
INIT
INTR
NMI
SLP/GPO7
SMI
STPCLK
SMBCLK
SMBDATA
PWRGD
CLKRUN
PWRBTN
RSMRST
SUSCLK
RING/GPI7
SPKR
EXTSMI
GPI1/IRQ8
GPO0
SUSC
GND
GND
GND
GND
GND
TSEN1
VREF
TSEN2
FAN1
VCCHWM
GNDHWM
W18
V17
Y17
V16
Y16
U15
W15
U14
Y15
V15
T15
W16
U16
W17
Y18
Y19
U19
V18
U20
U17
U18
V19
Y20
W19
W20
V20
Y7
V8
V7
Y8
T6
W8
U7
T7
U6
W7
U9
T9
W6
Y12
V12
W12
Y11
V6
T10
V11
V5
U8
Y10
T11
V10
U11
W11
T14
T8
U10
W10
V9
W9
Y9
F15
G15
L15
P15
R15
Y14
W14
U13
V13
W13
T13
Y13
T12
U12
R12
R13
R312 0
R310 22
R313 22
SDA0
SDA1
SDA2
SDCS1#
SDCS3#
SDDACK#
SDDREQ
SDIOR#
SDIOW#
FERR#
R8 0
SB_SMC
SB_SMD
CLKRUN#
PBTN#
RSMRST#
SUSCLK
PX4_RI#
SPKR
ACIN_SYS#
ATF_INT#
VLB#
IRQ8#
133M/100M#
LID#
SCI#
SUSA#
SUSB#
SUSC#
R290 100K
R299 0
12
C383
.1UF
12
12
12
1 2
C359 .1UF
12
PDD[0..15]17
A A
PDA017
PDA117
PDA217
PDCS1#17
PDCS3#17
PDDACK#17
PDDREQ17
PDIOR#17
PDIOW#17
PDIORDY17
R315 100
X3
R386
@20M
+3VS
12
C263
4.7U_1206
1
AD[0..31]
12
12
C294
22PF
12
.1UF
C278
C/BE#05,15,23,28
C/BE#15,15,23,28
C/BE#25,15,23,28
C/BE#35,15,23,28
FRAME#5,12,15,23,28
IRDY#5,12,15,23,28
TRDY#5,12,15,23,28
STOP#5,12,15,23,28
DEVSEL#5,12,15,23,28
SERR#5,12,15,23,28
PAR5,12,15,23,28
PCIREQ#5,12
PCIGNT#5,12
PIRQA#5,12,15
PIRQB#12,15,23
PIRQC#12,28
PIRQD#12,23
PCLK_SB11
+RTCVCC
1 2
12
C277
.1UF
AD[0..31]5,15,23,28
B B
AD18 IDSEL
C C
PCLK_SB
12
R292
@22
C353
@10PF
As close as 686A
RTCX1 RTCX2
32.768KHZ
1 2
12
D D
C288
22PF
1
SDD[0..15]17
LPD[0..7]24
SD[0..15]12,20
A A
B B
C C
D D
SA[0..19]12,20
Populate R384 and not
populate R383 When 64M
SDRAM on board
Populate R383 and not
populate R384 When
128M SDRAM on board
14MOSC
12
R252
@10
12
C265
@10PF
R250 4.7K
1 2
+3VS
R239 4.7K
1 2
+3VS
SDD[0..15]
LPD[0..7]
SA[0..19]
SIRQ12,15
PHDRST#19
SHDRST#19
1 2
+3VS
R383 10K
1 2
R384 @10K
AEN20
IOR#12,20
IOW#12,20
MEMR#12,20
MEMW#12,20
1
TC
IOCHK#
MEMR#
MEMW#
12
C379
4.7UF_1206
RP72 8P4R_22
IOCHRDY12,20
IRQ312
IRQ412
IRQ512
IRQ612
IRQ712
IRQ912
IRQ1012
IRQ1112
IRQ1412,17
IRQ1512,18
12
C374
.1UF
PID014
PID114
PID214
PID314
+3VS
+3VS
1 8
2 7
3 6
4 5
+3VS
+3VS
14MOSC11
FLASH#21
12
C366
.1UF
2
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8SD[0..15]
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SA16
SA17
SA18
SA19
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
64M#/128M
R253 1K
1 2
R254 1K
1 2
PIOR#
PIOW#
PMEMR#
PMEMW#
R240 1K
1 2
R251 4.7K
1 2
IOCHK#
TC
14MOSC
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
+3VS
12
12
C375
C373
.1UF
.1UF
2
U30B
W1
SA0
V2
SA1
V1
SA2
U3
SA3
U2
SA4
U1
SA5
T4
SA6
T3
SA7
T2
SA8
T1
SA9
R5
SA10
R4
SA11
R3
SA12
R2
SA13
R1
SA14
P5
SA15
P4
SA16
P3
SA17
K2
SA18
K1
SA19
J5
LA20
J4
LA21
J3
LA22
J2
LA23
Y1
SD0
Y2
SD1
W2
SD2
Y3
SD3
W3
SD4
V3
SD5
Y4
SD6
W4
SD7
L5
SD8
M2
SD9
M4
SD10
N1
SD11
N3
SD12
N5
SD13
P1
SD14
P2
SD15
L2
DACK0/IDEIRQA/GPO16
E1
DACK1/IDEIRQB/GPO17
D2
DACK3/AC97IRQ/GPO18
L4
DACK5/MC97IRQ/GPO19/SERIRQ
M3
DACK6/USBIRQA/GPO20
N2
DACK7/USBIRQB/GPO21
L3
DRQ0/GPI16
E2
DRQ1/GPI17
D3
DRQ3/GPI18
M1
DRQ5/GPI19
M5
DRQ6/GPI20
N4
DRQ7/GPI21(CF/CG)
B2
AEN
H2
BALE
F2
SBHE
E3
REFRESH
D1
IOR
C2
IOW
U4
MEMR
V4
MEMW
A1
SMEMR
B1
SMEMW
F3
IOCS16
F1
MEMCS16
A2
IOCHRDY
F4
IOCHK/GPI0
H1
TC
J1
RSTDRV
E4
OSC
H5
BCLK
D12
IRRX/GPO15
E12
IRTX/GPO14
G4
IRQ3
G3
IRQ4
G2
IRQ5
G1
IRQ6/GPI4/SLPBTN#
F5
IRQ7
H4
IRQ9
K3
IRQ10
K4
IRQ11
L1
IRQ14
K5
IRQ15
T5
XDIR/GPO12
U5
SOE/GPO13
F7
VCC
F10
VCC
F12
VCC
F13
VCC
F14
VCC
H6
VCC
J6
VCC
K6
VCC
M6
VCC
N6
VCC
VT82C686-B
3
PRD0
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7
ACK
BUSY
SLCT
ERROR
PINIT
AUTOFD
SLCTIN
STROBE
TXD1
DTR1
RTS1
CTS1
DSR1
DCD1
RXD1
TXD2
DTR2
RTS2
CTS2
DSR2
DCD2
RXD2
VCCUSB
GNDUSB
USBCLK
USBP0+
USBP0-
USBP1+
DRQ2/OC1/SERIRQ/GPIOE
3
USBP1-
DACK2/OC0/GPIOF
CHAS/GPIOC/GPIO10
USBP2+
USBP2-
USBP3+
USBP3-
KBCK/KA20G
KBDT/KBRC
MSCK/IRQ1
MSDT/IRQ12
ROMCS/KBCS
DRVDEN0
DRVDEN1
INDEX
MTR0
DS1
DS0
MTR1
STEP
WDATA
WGATE
TRAK00
WRTPRT
RDATA
HDSEL
DSKCHG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
LPD0
B15
LPD1
D15
LPD2
A14
LPD3
B14
LPD4
C14
LPD5
D14
LPD6
E14
LPD7
A13
B13
C13
D13
PE
E13
A15
C15
C16
E15
D16
TXD1
A11
DTR#1
D11
RTS#1
B11
C11
DSR#1
C12
DCD#1
A12
E11
RI1
RI2
DIR
RXD1
B12
D10
B9
E10
A9
C10
A10
C9
B10
R28410K
VCCUSB
F9
GNDUSB
F8
C3
USBP0+
A3
USBP0-
B3
USBP1+
C4
USBP1-
D4
H3
G5
V14
RP80
A4
B4
B5
E6
E5
A5
IRQ1
D5
IRQ12
C5
C1
D9
D6
D7
E9
A8
B8
C8
D8
E8
A7
B7
E7
A6
B6
C7
C6
F6
F11
G6
J9
J10
J11
J12
K9
K10
K11
K12
L6
L9
L10
L11
L12
M9
M10
M11
M12
P6
R6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
CTS#1
DCD#1
DSR#1
RI#1
CTS2
DSR2
DCD2
RI2
1 2
1 8
2 7
3 6
4 5
BIOSCS#
4
LPTACK# 24
LPTBUSY 24
LPTPE 24
LPTSLCT 24
LPTERR# 24
INIT# 24
LPTAFD# 24
SLCTIN# 24
LPTSTB# 24
RP84
1 8
2 7
3 6
4 5
8P4R_10K
RI2
CTS2
DSR2
DCD2
OVCUR#1 25
OVCUR#0 25
8P4R_15K
GATEA20 20
RC# 20
IRQ1 12,20
IRQ12 12,20
3MODE# 19
INDEX# 19
MTR0# 19
DRV0# 19,21
FDDIR# 19
STEP# 19
WDATA# 19
WGATE# 19
TRACK0# 19
WP# 19
RDATA# 19
HDSEL# 19
DSKCHG# 19
1 2
R28510K
+3VS
RP81
1 8
2 7
3 6
4 5
8P4R_10K
48M
1 2
R255 4.7K
PH: SOCKET 370; SLOT 1,SOCKET-A
PL: SOCKET 7
+5V
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
12
R263
@33
12
C303
@10PF
VCCUSB
GNDUSB
5
RXD1
12
5
C333
.1UF
1
2
3
4
5
6
7
8
9
10
@96212-1011S
+3VS
48M 11
BIOSCS# 20
+3VS
12
+
JP1
1
2
3
4
5
6
7
8
9
10
L38
1 2
C325
10UF_1206
1 2
L37
0_0805
0_0805
+3VS
6
USBP1+
USBP1USBP0+
USBP0-
1 8
2 7
3 6
SDD0
SDD1
SDD2
SDD3
SDD4 SA4
SDD5
SDD6
SDD9
SDD14
SDD8
SDD13
SDD12
SDD11
SDD10
SDD15
6
7
The components most place cloely 686B
RP76
1 8
2 7
3 6
CP7
8P4C-47PF
4 5
4 5
8P4R-27
RP73
4 5
3 6
2 7
1 8
8P4R_0
RP71
4 5
3 6
2 7
1 8
8P4R_0
RP78
8P4R_0
RP79
8P4R_0
18
27
36
45
18
27
36
45
SA0
SA1
SA2
SA3
SA5
SA6
SA7SDD7
SA9
SA14
SA8
SA13
SA12
SA11
SA10
SA15
182736
45
RP77
8P4R-15K
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
B
401202
!"# $%
Date: Sheet
7
8
10 34, 22, 2001
8
USB1_D+ 25
USB1_D- 25
USB0_D+ 25
USB0_D- 25
of
1B
CLOCK GENERATOR & BUFFER
L32
1 2
CHB2012U170
+3VS
DCLKO
12
R196
@22
C237
@10PF
SUSA#9,20
CPU_IO
L34
1 2
CHB2012U170
C462
4.7UF_10V_0805
10V
C281
10PF
1 2
R407 10K
12
@RB751V
@RB751V
3
Q61
FMMT3904
C264
1 2
1000PF
Y3
1 2
14.318MHZ
1 2
R257 @2M
D45
21
D20
21
2
CBE
1
12
12
C280
10PF
1 2
R389 @10K
CPUSTP#
SUS_A#
1 2
R184
10K
W=40MILS
12
C469
C466
.1UF
1000PF
CPU_STP#9
+3VS
+3VS
12
DCLKO6
PCI_STP#9
+3VCLK_CORE
C463
.1UF
12
1 2
R388 0
+12VS
R169
10K
1 2
2
Q27
13
2N7002
Q28
2N7002
C464
.1UF
CLK_CPUIO
+3VCLK_CORE
+3VBUFF
+3VBUFF
+3VCLK_CORE
+3VCLK_CORE
+3VCLK_CORE
+3VCLK_CORE
XIN
XOUT
DCLKO
SUS_A#
CPUSTP#
2
13
+3V
+3VS
U22
47
VDDL
36
VDDSDR
30
VDDSDR
27
VDD48
14
VDDPCI
6
VDDPCI
1
VDDREF
4
XIN
5
XOUT
15
BUFIN
20
PCI_STP#
21
PWR_DWN#
41
CLK_STP#
23
SDATA
24
SCLK
3
VSS
9
VSS
16
VSS
22
VSS
33
VSS
40
VSS
44
VSS
ICS9248-195
SMBCLK 8,9
SMBDATA 8,9
CPU / PCI CLOCK
FS3 FS2 FS1 FS0 CPU / PCI
1 0 1 1 133 / 33 MHz
L30
1 2
@CHB2012U170
L31
1 2
CHB2012U170
4.7UF_10V_0805
10V
C225
12
C231
.1UF
24/48MHZ/FS1
48MHZ/FS0VDDCOR
CPUCLKF
CPUCLK0
CPUCLK1
CPUCLK2
PCIF
PCI0/FS3
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
SDRAMF
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
REF0
REF1/FS2
W=30MILS
12
C235
.01UF
25
2619
46
45
43
42
7
8
10
11
12
13
17
18
39
38
37
35
34
32
31
29
28
2
48
BSEL12,6
+3VBUFF
12
FS1
FS0
MODE
EARLY
SPECTRUM
FS2
C242
1000PF
1 2
1 2
+3VBUFF
12
1000PF
R176
@10K
R186
10K
C236
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R237 @10
1 2
R238 10
1 2
R243 10
R179
FS0
1 2
@10K
R177
FS1
1 2
@10K
R246
FS2
1 2
10K
+2.5V_CLK
R187 22
R387 22
R225 22
R219 @22
R213 22
R377 33
R216 33
R206 33
R202 33
R190 33
R214 22
R204 10
R198 10
R197 10
CHB2012U170
C254
@10PF
L36
1 2
C260
@10PF
C283
4.7UF_10V_0805
10V
C252
@15PF
0NO
1 EARLY CLOCK
W=30MILS
R378
150
1 2
13
Q60
FDV301N
R406
49.9_1%
1 2
13
2
0 3.3V CPU
1 2.5V CPU
0NO
1 SPREAD SPECTRUM
CLK_CPUIO
12
C270
.01UF
2
Q59
FDV301N
12
C276
1000PF
48M 10
HCLK_CPU 2
HCLK_NB 4
PCLK_SB 9
APICCLK 2
PCLK_PCM 15
PCLK_MINI 23
PCLK_1394 28
PCLK_NB 5
DCLKWR 6
CLK_SDRAM0 7
CLK_SDRAM2 8
CLK_SDRAM3 8
14.3M_TV 13
14MCRT 5
14MOSC 10
TUAL5 2,3,32VTTPWRGD3,32
TUAL5# 3
R220
1 2
10K
CLK_CPUIO
12
C262
.1UF
EARLY
MODE
SPECTRUM
R227
1 2
@10K
R218
1 2
10K
R226
1 2
10K
+3VS
1 0 0 0 100 / 33 MHz
1 1 1 0 66 / 33 MHz
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1281
Size Document Number Rev
401202
!"# $%
Date: Sheet
11 34, 22, 2001
of
1B
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