Compal LA-1121 888M3, V60 Schematic

A

4 4

B

C

3 3

ATL02 LA-1121 Schematic Document

Mobile Tualatin or Coppermine-T(uFCBGA/uFCPGA)

Almador-M GMCH-M/ICH3-M

2001-09-13

2 2

Rev: 1.0 (1A)

1 1

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

A

B

C D E

Date: Sheet

1

1A

87Thursday, September 13, 2001

of

A

Model Name: ATL02
PCB No: LA-1121

B

C

BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

Revision: 1.0

4 4

Mobile Tualatin
or
Coppermine -T

(uFCBGA/uFCPGA)

PAGE 4,5,6

Thermal Sensor
MAX1617MEE

PAGE 5

CK TITAN
ICS9250-38

PAGE12

CPU VID & All
reference vol t a g e

PAGE 7

PSB

Almador-M

CRT & TV-Out
CONN.

3 3

PAGE 16

USB & BlueTooth

HDD Connec tor

CD-ROM Connec to r

2 2

AGP 4X
CONN.

PAGE 27

PAGE 20

PAGE 20

PAGE 15

AGP Bus Interface

USB

ATA 66/100

Audio CD-DJ

OZ163
Rev.C

PAGE 30

LPC

GMCH-M

625 BGA

PAGE 8,9,10,11

HUB

Interface

ICH3-M

421 BGA

PAGE 17,18,19

Memory Bus

PCI BUS

IEEE 1394

TI TSB43AB22

LAN

RTL8100-L

Mini PCI
Socket

CardBus
TI

PCI1420

Super I/O

LPC47N227

PAGE 25

1 1

Parallel

PAGE 26

A

FIR

PAGE 26

FDD

PAGE 20

B

Embedded
Controller

NS PC87591

PAGE 33

Scan KB

PAGE 15

BIOS & I/O
PORT

PAGE 34

C

AC'97
CODEC

CS4299

Audio Jack

SO-DIMM * 2

BANK 2,3,4,5

PAGE 22

PAGE 21

PAGE 28

PAGE 23

PAGE 31

PAGE 32

PAGE 13,14

SmartMedia with SD

TC6371AF

Slot 0/1

PAGE 24

Audio Amplifier

PAGE 32

D

PAGE 29

FAN on controller &
TEMP. sensing circuit

PAGE 35

DC/DC Interface
RTC Battery

PAGE 37

BATTERY
Charger

PAGE 41

POWER
Interface

PAGE 40,42,43,44

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

287Thursday, September 13, 2001

E

1A

of

A

B

C

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

Voltage Rails

PIR

Power Plane Descripti on

1 1

B+
+VCC_H_CORE
+VTT

VIN

Adapter power supply (19V)
AC or battery power rail for po w er circuit.
Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus
+1.5V 1.5V pow er rail ON ON OFF
+1.5VS

AGP 4 X ON OFF OFF
+1.8V 1.8V pow er rail ON ON OFF
+1.8VS
+2.5V
+3VALW
+3V
+3VS
+5VALW
+5V ON
+5VS

2 2

+12VALW
+12VS
RTCVCC

1.8V switched power rail

2.5V power rail

3.3V always on power rail ON*

3.3V power rail

3.3V switched power rail

5V always on power rail

5V power rail

5V switched power rail

12V always on power r ail

12V switched power rail

RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL# REQ# / G NT # Interrupts

AGP 4X CONN.
IEEE 1394 AD16 0
CardBus

LAN

Mini-PCI

3 3

SD/SM

AD20

AD17

AD18

AD22

EC SM Bus1 address

Device

Smart Batte r y
EEPROM(24C16/0 2)

(24C04)

Address Address

0001 011X b
1010 000X b
1011 000Xb

2

3 PIRQB

1/4

EC SM Bus2 address

ICH3-M SM Bus address

Device

4 4

Clock Generator ( ICS9238-50)
SDRAM Select ( 74HC4052 )
CPU Voltage VID select ( F3565 )

A

Address

1101 0000
1010 0000
0110 111Xb

S1 S3 S5

N/A N/A N/A

ON OFF
ON OFF

ON
ON
ON
ON
ON
ON ON

ON
ON
ON
ON

Device

MAX1617MEE
OZ163
Smart Battery
Docking
DOT Board

B

OFF
ON
ON
ON
OFF

ON
OFF
ON
OFF
ON

PIRQA
PIRQA
PIRQA/PIRQB

PIRQC/PIRQD
PIRQC/PIRQD

1001 110X b
0011 0100 b
0001 011X b
0011 011X b
XXXX XXXXb

N/AN/AN/A
OFF
OFF

OFF
OFF

OFF
OFF
ON*
OFF
OFF
ON*
OFF
ON

REV 0.2

Date Page Description

5/8 29 Modification toshiba SM+SD function
5/8 32 Modification audio volume control function
5/8 42 ADD system thermal protection
5/14 DEL R244 ,Add D44

33

REV 0.3

Date Page Description

5/23

5/23 18 DEL R90,R89,R281

5/23 32 R448 change gnd to +5VCD, R479 change +5VCD to gnd.
5/23 37 U2.4 link to U20.8
5/23 30 Add R519.
5/23 5 U9.AF19 add R517 link to +1.5VS
5/23 25 Modifty LPC_RST# timing. Add U55,D45,R518.
5/31 27 JP15.8 connector to U29.57
5/31 25 ADD R520, Add net name BT_DET# to U29.57
5/31 34 Modifty net name ANT_SW to WL_OFF#, ADD R221
5/31 28 Modifty net name RFOFF# to WL_OFF#
5/31 35 DEL R19

REV 0.4

Date Page Description

7/3 16 Del L23,R14,R12,R10,R6,R8
7/3 27 ADD C720,C721,C722,C723,C724,C725
7/3 29 IDSEL0 change to PCI_AD26, INTA#/INTB# change to PIRQC#/PIRQD#
7/10 24 Add U58,U59,R531,R532,R533,R534,C718,C719
7/17 29 Del SD function
7/18 29 Change IDSEL to PCI_AD22
7/23 21 DEL C15

REV 0.5

Date Page Description

8/13 15 Add R544 reserve for sus_stat# and stp_agp#
8/13 29 Add R545 pull-up signal SM_LED to SMC_VCC,Add@ in
8/13 35 Change R543 pull-up form SMC_VCC to +5VS
8/13 29 Add R546,R547 signal PCIRST#,CBRST#
8/13 37 Del U2,Q4,R330
8/16 10 Add Signal TV_out_DDC2CCLK,TV_out_DDC2DATA

8/16 10 Add R551.R552. DEL R225,R235
8/16 15 Add RP38,RP39
8/16 16 Add R553,R554,R555
8/17 34 Del R29, Add R557, R558
8/17 20 Add R556

REV 1.0

Date Page Description

8/31 5 Q6 RESERVE

REV 1.A

Date DescriptionPage

9/6 12 Add D47 and R562

C

5

U8 Vcc plane modifty to +5VALW

U62,C729,R486

,VCH_I2CCLK,VCH_I2CDATA,AGP_DDCCLK,AGP_DDCDATA

D

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

387Thursday, September 13, 2001

E

of

1A

A

+VCC_H_CORE

1 1

AF23

AD23

B11

A10
A13

C12
C10

A15
A14
B13
A12

AA3

AB3
C14
AF4

C22

AA2

W2

K1

J1
G2
K3

J2
H3
G1
A3

J3
H1
D3
F3
G3
C2
B5

C6
B9
B7
C8
A8

B3
A9

C3

A6

R1
L3
T1
U1
L1
T4

P3

A7
C4

R2
L2
V3

U2
T3

U9A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

TUALATIN

H_A#[3..31]8

2 2

H_REQ#[0..4]8

H_ADS#8

+1.5VS

3 3

H_BPRI#8

H_BNR#8

H_LOCK#8

H_HIT#8

H_HITM#8

H_DEFER#8

H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#[0..4] H_D#33

R331 1.5K

1 2

R87 10

1 2

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

B

D22

F22

E21

H22

VCC_0

VCC_1

VCC_2

Address

Lines

Request

Signals

Error

Interface

Arbitration

Signals

Snoop

Signals

VSS_0

E16R4E25

C

G21

K22

J21

M22

L21

P22

N21

T22

R21

V22

U21

Y22

W21

AB22

AA21

AC21

D20

F20

E19

AB20

AA19

AC19

D18

F18

E17

AB18

AA17

AC17

D16

F16

E15

AB16

AA15

AC15

D14

F14

E13

AB14

AA13

AC13

D12

F12

E11

AB12

AA11

AC11

D10

F10E9AB10

AA9

AC9D8F8E7AB8

AA7

VCC_3

VCC_4

VCC_5

VCC_6

VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_61

VCC

Mobile

Tualatin

VSS VCC

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

G25

J25

L25

N25

R25

U25

W25

AA25

AC25

AF25

AE26

C23

F23

H23

K23

M23

P23

T23

V23

Y23

AB23

AE23

B22

D21

F21

E22

H21

G22

K21

J22

M21

L22

P21

N22

T21

R22

V21

U22

Y21

W22

AB21

AA22

AC22

AE21

B20

D19

AB19

AA20

AC20

AE19

B18

D17

F17

E18

AB17

D

AC7D6F6E5H6G5K6J5N5T6V6

VCC_62

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_69

VCC_70

VCC_71

Data

Signals

VCC_73

VCC_74

VCC_75

VCC_76

VCC_77

VCC_78

VCC_79

VCC_80

U5Y6W5

AB6

AA5

AC5M6P6

E

H_D#[0..63]

H_D#0

A16

VCC_72

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32

H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] 8

+VCC_H_CORE

4 4

Compal Electronics, inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

487Thursday, September 13, 2001

E

of

1A

A

B

C

D

E

+VTT

+1.8VS

+1.5VS

+1.5VS

1 1

2 2

3 3

4 4

Place H_RESET#
R3<0.1" from U1

H_FERR#17

H_PWRGD17

H_RESET#8

H_PICD017
H_PICD117

2200PF

C70

+5VALW

12

R61

56.2_1%

R53 @0
1 2
1 2

R64 @0

1 2

A

12

R325

1.5K

+1.5VS

R62
150

H_THERMDA
H_THERMDC

R80

1K

R335

+1.5VS

12

+VS_CMOSREF

C40
.1UF

1 2

12

12

12

R336

1.5K

3K

12

R55
150

CLK_CPU_APIC12

+1.5VS

PM_CPUPERF#17,19

1 2

U8

1

NC

2
3
4
5
6
7
8 9

VCC

SMBCLK

DXP
DXN

SMBDATA

NC
ADD1

ALERT
GND
GND NC

MAX6654

STBY

ADD0

Thermal Sensor

R44

200

NC

NC

H_IGNNE#17

H_STPCLK#17

H_DPSLP#17,43

H_TRDY#8

H_A20M#17

H_DBSY#8

H_DRDY#8

H_BSEL010,12
H_BSEL112

@10PF

H_RS#08
H_RS#18
H_RS#28

H_SMI#17

H_INTR17

H_NMI17

H_INIT#17

C39

16
15
14
13
12
11
10

1 2

@33_0402

R482 1.5K

1 2

1 2

R517 200

1 2
R68 56.2_1%

Note :
GHI# Pull-Up internally

+5VALW

12

R50
1K

+5VALW

H_A20M#

H_IGNNE#

H_INTR
H_NMI

H_THERMDA
H_THERMDC

1 2

R280

110_1%

R41

ITP_TRST#

12

R49
10K

AC3

AF6

AF5
AD9
AD3
AB4
AE4

AF8

AD15
AE14

AE6

B15

AF13
AF14

AE12
AF10
AF16

AD19
AD17
AF20

AF22
AE20
AD22
AD21

AD10

AD7

AD11

AF7

AF15
AF19
AE22

AF12

AD5

AE16

B

AA18

AC18

AE17

B16

D15

F15

AB15

AA16

AC16

AE15

B14

D13

F13

E14

AB13

AA14

AC14

AE13

B12

D11

F11

E12

AB11

U9B

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

Y3

RS#0

V1

RS#1

U3

RS#2

M5

Request

RSP#

W1

Signals GND

TRDY#

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#

Compatibilit y

DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#

W3

DBSY#

Y1

DRDY#

THERMDA
THERMDC

SELFSB0
SELFSB1
EDGECTRLP

PICD0

L5

+VTT

PICD1
PICCLK

RP2#
RP3#
BPM0#
BPM1#

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

CMOSREF_1
CMOSREF_0
RTTIMPDEP

GHI#

VCCT_1

VCCT_2

A26

G23

APIC

Debug
Break

Point

Test

Access

PORT
( ITP )

VCCT_3

VCCT_4

VCCT_5

VCCT_6

J23

L23

N23

R23

EC_SMC2 30,33,40

VCCT_7

VCCT_8

VCCT_9

VCCT_10

VCCT_11

VCCT_12

VCCT_13

VCCT_14

VCCT_15

VCCT_16

U23

W23

AA23

C21

C19

AD20

C17

AD18

C15

C13

AA12

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VCCT VID

VCCT_17

VCCT_18

VCCT_19

VCCT_20

VCCT_21

VCCT_22

AD14

C11

AD12C9C7

AD8C5AD6

From 87591

EC_SMD2 30,33,40

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

AC12

VSS_81

VCCT_23

AE11

B10D9F9

VSS_82

VSS_83

VCCT_24

VCCT_25

AC23

AA4E4G4J4L4

VSS_84

VSS_85

VSS_86

VCCT_26

VCCT_27

VCCT_28

E10

AB9

AA10

AC10

AE9B8D7F7E8

AB7

AA8

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

Mobile

Tualatin

VCCT_29

VCCT_30

VCCT_31

VCCT_32

VCCT_33

VCCT_34

VCCT_35

VCCT_36

VCCT_37

VCCT_38

AC4V4AE3

AF2

AF1

AE18D5E6

AC8

AE7B6F5H5G6K5J6N6L6T5R6V5U6Y5W6

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VID0

VID1

VID2

VID3

VID4

VSS

VSS

VSSNCNC

AB1

AC2

AE2

AF3R3B26M4AF26C1AF17

CPU_VR_VID4 7
CPU_VR_VID3 7
CPU_VR_VID2 7
CPU_VR_VID1 7
CPU_VR_VID0 7

AB5

AA6

AC6

AE5B4D4F4H4K4M3U4W4B2D2F2H2

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_141

VSS_142

NC

E20

F19

N4

+3VS

D

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

AE24

DEP#0

AD25

DEP#1

AE25

DEP#2

AC24

DEP#3

AF24

DEP#4

AD26

DEP#5

Data

Signals

VTT Ref

Analog

NCHCTRLP

VTTPWRGOOD

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

AD2

AE1

A25

C25

+3V

12

R100
10K

12

C105
.1UF

U36F

14

7

Title

Size Document Number Rev
Custom

Date: Sheet

AC26

DEP#6

AD24

DEP#7

AF21

VREF_1

AB26

VREF_2

H26

VREF_3

A21

VREF_4

AF9

VREF_5

A4

VREF_6

N1

VREF_7

AA1

VREF_8

Y4

TESTLO

R5

VCC

N3

PLL1

N2

PLL2

P1

NC

P5

NC

E1

NC

F1

NC

AC1

CLK0

AD1

CLK0#

M1

TESTLO

AF18

NC

AD16
AF11

TESTHI

AE8

NC

N24

NC

AE10

NC

E2

TESTHI

P4

NC

AD4

NC_1

A5

NC_2

D1

NC_3

AD13

NC_4

B1

NC_5

P26

NC_6

A11

NC_7

E3

D26

NC

VSS_130

TUALATIN

K2M2P2T2V2Y2AB2

1213

74LVC14

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121
401191 (FOR ATL02 / ACL00)

TESTHI1
TESTHI2

+V_AGTLREF

TESTLO1

+

CLK_HCLK
CLK_HCLK#
TESTLO2

TESTHI1

TESTHI2

CPUVTT_PWRGD

2

+VCC_H_CORE

C520
33UF_16V_D2

R76 14_1%

1 2

+VTT

12

R99
10K

13

VTT_PWRGD# 12,33VTT_PWRGD44

E

Q6

RP23
1 8
2 7
3 6
4 5

8P4R_1K

1 2

L30 4.7UH

CLK_HCLK 12
CLK_HCLK# 12

CPUVTT_PWRGD

2N7002

587Thursday, September 13, 2001

of

+VTT

+VTT

+VTT

TESTLO1
TESTLO2

1A

A

B

C

D

E

Layout note :

1 1

Place close to CPU, Use 2~3 vias per PAD.
Place .47uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Layout note :

Place close to CPU,
Use 2 vias per PAD.

+VCC_H_CORE

12

12

12

12

12

12

12

12

12

12

12

C388

C389

C391

C392

C393

C394

C395

C396

C397

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

+VCC_H_CORE

12

12

12

12

12

12

12

12

C434

C425

C411

C433

C424

C421

.47UF

.47UF

.47UF

.47UF

12

C448
10UF_10V_1206

12

C30
10UF_10V_1206

12

C519

+

150UF_6.3V_D2

.47UF

2 2

+VCC_H_CORE

12

C450
10UF_10V_1206

+VCC_H_CORE

12

C445
10UF_10V_1206

3 3

+VCC_H_CORE

12

C536

+

150UF_6.3V_D2

12

C449
10UF_10V_1206

12

C117
10UF_10V_1206

12

C537

+

150UF_6.3V_D2

.47UF

12

C447
10UF_10V_1206

12

C38
10UF_10V_1206

12

C549

+

150UF_6.3V_D2

.47UF

C525

C432

.47UF

12

C446
10UF_10V_1206

12

C33
10UF_10V_1206

12

C538

+

150UF_6.3V_D2

12

.47UF

C409

.47UF

C398

.47UF

12

C420

.47UF

12

C390

C412

.47UF

.47UF

12

12

C408

C431

.47UF

.47UF

+VTT

12

+

+VTT

12

1UF_10V_0603

C45
220UF_4V_D2

1UF_10V_0603

12

C32

C34

12

C513

+

220UF_4V_D2

1UF_10V_0603

12

C37

1UF_10V_0603

12

C41

1UF_10V_0603

1UF_10V_0603

12

C43

12

C48

12

C59

1UF_10V_0603

1UF_10V_0603

12

C67

12

C72

1UF_10V_0603

12

C79
1UF_10V_0603

+VCC_H_CORE

12

C310

+

150UF_6.3V_D2

4 4

A

12

C309

+

150UF_6.3V_D2

12

C308

+

150UF_6.3V_D2

12

C314

+

150UF_6.3V_D2

B

12

C313

+

150UF_6.3V_D2

12

C297

+

150UF_6.3V_D2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

687Thursday, September 13, 2001

E

of

1A

A

B

C

D

E

Tualatin

CPU Voltege ID

Default f o r R e s is t o r s S hould
be +VCC_CPU = 0.7V, for
Deeper Sleep Only.

1 1

SMB_CLK12,14,17

SMB_DATA12,14,17

CPU_VR_VID05
CPU_VR_VID15

From Tualatin CPU

PM_GMUXSEL = 1 : for Performance mode

PM_DPRSLPVR = 1: for Deeper Sleep mode

2 2

3 3

CPU_VR_VID25
CPU_VR_VID35
CPU_VR_VID45

+3VS

PM_DPRSLPVR17,43

PM_GMUXSEL17,43

0 : for CPU default power

0 : for Performance mode

1 2

R173

@10K

R321
@10K

182736

12

1
2

+3VS +3V

45

RP30
@8P4R_10K

+3V

C647

1 2

.1UF

3 5

U49
NC7SZ02

12

R172
@100K

4

Override# MUX_SEL A/B# MUX_outputs

1
1

1

Address 0110 111X

U17

1

SCL

2

SDA

3

Override#

4

I_0

5

MUX_SEL

I_1

6

I_2

7

I_3

8

I_4

9

A/B#

10

GND

FM3565

MUX_SEL

1 X MUX_inputs
0 0 From

01

VCC

ASEL

+3V

C213

1 2

.1UF

R460 0

20

1 2

19

1 2

18

WP

NC

Y_0
Y_1
Y_2
Y_3
Y_4

17
16
15
14
13
12
11

R461 0

Non-volatile
register(SOPRB)
From
Non-volatile
register(SOPRA)

CPU_VID0 43
CPU_VID1 43
CPU_VID2 43
CPU_VID3 43
CPU_VID4 43

Mode

Battery

Performance

Deeper sleep

D4 D3 D2 D1 D0 CPU_Core(V) ES(before MP)

-------------------------------------------------------­0 0 1 0 1 1.50V (Performance)
0 1 1 0 0 1.15V (Battery)
1 0 1 0 1 0.85V (Deeper Sleep)

D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)

-------------------------------------------------------­0 0 1 1 1 1.40V (Performance)
0 1 1 0 0 1.15V (Battery)
1 0 1 0 1 0.85V (Deeper Sleep)

+3V

System Memory Referenc e

12

R302

249_1%

49.9_1%

301_1%

249.9_1%

Place capacitor close to GMCH.

12

12

R297

+1.8VS

R308

12

12

C467
.1UF

HUB Interface Reference

Layout note :

1. Place R308 and R296 in middle of Bus.

2. Place capacitors near GMCH.

12

R296

C453

301_1%

.1UF

+V_SMREF

+VS_HUBREF

+VTT

12

R303
1K_1%

12

R322
2K_1%

+1.5VS

12

R288
1K_1%

12

R291
2K_1%

+VAGP_BRDREF

GTL Reference Voltage

Layout note :

1. Place R303 and R322 between and GMCH and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

12

C514
.1UF

12

12

C35

C71

.1UF

.1UF

12

C27
.1UF

+V_AGTLREF

CMOS Reference Vo l t a g e

Layout note :

1. Place R288 and R291 between and GMCH and CPU.

2. Place decoupling caps near CPU.

C578

1 2

C555

1 2

+VS_CMOSREF

470PF

470PF

12

12

R373

82.5_1%

R365

82.5_1%

12

Place Reference Ci rc u it n ea r GM CH

C439
.1UF

+1.5VS

12

12

12

C440
.1UF

R376
1K_1%

R370
1K_1%

+1.8VS

HUB Interface VSwing Voltage

12

R93

301_1%

1. Place R93 and R94 in middle of Bus.

12

C97
.1UF

+VS_HUBVSWING

D

12

R94

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

301_1%

C

+1.8VS

12

R275

576_1%

1. Place R275 and R274 near GMCH.

12

R274

2K_1%

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

+VS_RIMMREF

787Thursday, September 13, 2001

E

of

1A

A

1 1

2 2

3 3

4 4

A

H_D#[0..63]

HUB_PD[0..10]17

HUB_PSTRB17

HUB_PSTRB#17

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

B

AA3

AD3
AB4
AB5

AA4
AA1
AA6
AB1
AC4
AA2
AB3
AD2
AD1
AC2
AB6
AC6
AC1

AD4
AD6
AC3
AH3
AE5
AE3
AG2

AE4
AG1
AE1
AG4
AH4
AG3

+VS_HUBREF

B

AF3

AF4
AF2
AJ3

AF1

U4

P1
W6
U2
U6
R1
N3
W5

V4

P3
R3
U1

V6
W4

T3

P2

V3
R2

T1
W3
U3

Y4
W1

V1

Y1

Y6

V2

Y3

Y2

U7A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

ALMADOR-M

12

C476

.01UF

M12

M13

M17

M18

N12

VSS0

VSS1

VSS2

VSS3

VSS4

Host

Interface

HUB_PD0

HUB_PD1

HUB_PD2

HUB_PD3

HUB_PD4

HUB_PD5

G26

H28

H29

H27

F29

F27

HUB_PD0

HUB_PD1

HUB_PD2

HUB_PD3

HUB_PD4

HUB_PD5

R246 54.9_1%
R92 27.4_1%

1 2

R83 54.9_1%

1 2

C

N13

N14

N15

N16

N17

N18

P13

P14

P15

P16

P17

R13

R14

R15

R16

R17

T13

T14

T15

T16

T17

U12

U13

U14

U15

U16

U17

U18

V12

V13

V17

V18

AJ5D2AC5Y5U5P5L5H5AH2

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS_H0

VSS_H1

VSS_H2

VSS_H3

VSS_H4

VSS_H5

VSS

Almador-M
GMCH

A3

HUB_PD6

HUB_PD7

HUB_PD8

HUB_PD9

HUB_PD10

HUB_PSTRB

HUB_REF

HUB_PSTRB#

DVO_RCOMP

SM_RCOMP

HUB_RCOMP

AGP_REF

AGP_RCOMP/DVOBC_RCOMP

RESET#

H_GTLREF1

H_GTLREF0

H_GTLRCOMP

VSS

VSS

VSSPCMOS_LM0

VSSPCMOS_LM1

VSSPCMOS_LM2

VSSP_HUB0

VSSP_HUB1

VSSP_IO0

VSSP_IO1

VSSP_IO2

E29

E28

G25

G27

H26

G29

H24

F28

AC22F6J23

J25

K24

AB24

AA7J7C2

HUB_PD7

HUB_PD6

HUB_PD8

HUB_PD9

HUB_PD10

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+VAGP_CRDREF

C

12

C469
.1UF

R78 54.9_1%

12

C470
.1UF

AB23

AC23

1 2

R91 80.6_1%

+V_AGTLREF

12

C471
.1UF

12

AH19

AH20

AF5

G28

H25

AC26

AD22

AE28

PCIRST# 15,17,19,20,21,22,23,24,25,28,29,35

10 mils wide,length <=500 mils.

VSS_H6

VSS_H7

VSS_H8

VSSP_DVO0

VSSP_DVO1

AH24

AF25

D

AE2

AB2W2T2N2K2G2AC7

VSS_H9

VSS_H10

VSS_H11

VSS_H12

VSS_H13

Host

Interface

VSSP_DVO2

VSSA_DAC

AF27

AH26G8AD7

D

VSS_H14

VSS_H15

VSS_H16

VSSA_CPLL

VSSA_HPLL

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_CPURST#

H_ADS#

H_BNR#

H_BPRI#

H_DBSY#

H_DEFER#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

CLK_HT

CLK_HT#

CLK_DREF

CLK_GBIN

CLK_GBOUT

E

H_A#[3..31]

H_A#3

H2

H_A#4

E3

H_A#5

G3

H_A#6

N4

H_A#7

M6

H_A#8

F1

H_A#9

F2

H_A#10

J3

H_A#11

F3

H_A#12

P6

H_A#13

G1

H_A#14

N5

H_A#15

H1

H_A#16

P4

H_A#17

T4

H_A#18

M2

H_A#19

J2

H_A#20

L2

H_A#21

R4

H_A#22

K1

H_A#23

L3

H_A#24

L1

H_A#25

J1

H_A#26

N1

H_A#27

T5

H_A#28

H3

H_A#29

M3

H_A#30

M1

H_A#31

K3

1 2

R290 @0

R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4

H_REQ#0

K6

H_REQ#1

M4

H_REQ#2

K5

H_REQ#3

K4

H_REQ#4

L6

H_RS#0

H6

H_RS#1

H4

H_RS#2

G6

AJ4
AH5

AC19
AG26
AD24

@33_0402

@10PF

Title

Size Document Number Rev
Custom

Date: Sheet

1 2

R242

1 2

1 2

C322

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121
401191 (FOR ATL02 / ACL00)

R26047

R276
@33_0402

C381
@10PF

Close to Ball R6.

H_REQ#[0..4]

H_RS#[0..2]

.01UF
C373

H_A#[3..31] 4H_D#[0..63]4

H_RESETX#
H_RESET# 5
H_ADS# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 5
H_DEFER# 4
H_DRDY# 5
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 5
H_REQ#[0..4] 4

H_RS#[0..2] 5

CLK_GHT 12
CLK_GHT# 12

R158
240K

Closely to C.G

1 2

E

CLK_DREF 12
CLK_GBIN 12
CLK_GBOUT 12

887Thursday, September 13, 2001

of

1A

A

AD8

AD9

AD10

AJ21

AE8

AE9

AE10

AE11

AE12

AE13

AE17

AE19

AH21

AF8

AF9

AF10

AF11

AF12

AF13

U7B

SM_DQ0
SM_DQ1
SM_DQ2

1 1

SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30

2 2

SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

3 3

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_DQ[0..63]

D29

SM_DQ0

C29

SM_DQ1

D27

SM_DQ2

C27

SM_DQ3

A27

SM_DQ4

B26

SM_DQ5

E24

SM_DQ6

C25

SM_DQ7

E23

SM_DQ8

B25

SM_DQ9

C23

SM_DQ10

F22

SM_DQ11

B23

SM_DQ12

C22

SM_DQ13

E21

SM_DQ14

B22

SM_DQ15

C12

SM_DQ16

D10

SM_DQ17

C11

SM_DQ18

A10

SM_DQ19

C10

SM_DQ20

C8

SM_DQ21

A7

SM_DQ22

E9

SM_DQ23

C7

SM_DQ24

E8

SM_DQ25

A5

SM_DQ26

F8

SM_DQ27

C5

SM_DQ28

D6

SM_DQ29

B4

SM_DQ30

C4

SM_DQ31

E27

SM_DQ32

C28

SM_DQ33

B28

SM_DQ34

E26

SM_DQ35

C26

SM_DQ36

D25

SM_DQ37

A26

SM_DQ38

D24

SM_DQ39

F23

SM_DQ40

A25

SM_DQ41

G22

SM_DQ42

D22

SM_DQ43

A23

SM_DQ44

F21

SM_DQ45

D21

SM_DQ46

A22

SM_DQ47

F11

SM_DQ48

A11

SM_DQ49

B11

SM_DQ50

F10

SM_DQ51

B10

SM_DQ52

B8

SM_DQ53

D9

SM_DQ54

B7

SM_DQ55

F9

SM_DQ56

A6

SM_DQ57

C6

SM_DQ58

D7

SM_DQ59

B5

SM_DQ60

E6

SM_DQ61

A4

SM_DQ62

D4

SM_DQ63

ALMADOR-M

SM_DQ[0..63] 14

VSS_LM

SDRAM
System
Memory

VSSP_SM0

VSSP_SM1

VSSP_SM2

B3B6B9

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS Power

VSSP_SM3

VSSP_SM4

VSSP_SM5

VSSP_SM6

VSSP_SM7

VSSP_SM8

VSSP_SM9

VSSP_SM10

VSSP_SM11

VSSP_SM12

VSSP_SM13

VSSP_SM14

B12

B15

B18

B21

B24

B27E7E10

E13

E16

E19

E22

AF14

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

Almador-M
GMCH

VSSP_SM15

VSSP_SM16

VSSP_SM17

VSSP_SM18

VSSP_SM19

E25G9G21E4D28

+VTT

Layout note :

Place resistors & capacitors near GMCH

4 4

SM_D_CLK0
SM_D_CLK1
SM_D_CLK2
SM_D_CLK3

R318 10

1 2

R313 10

1 2

R317 10

1 2

R315 10

1 2

A

12

C506
@33PF

12

C516
@33PF

12

C515
@33PF

12

C517
@33PF

B

AF15

AF16

AF17

AF18

AF19

AF20

AG7

AG15

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS

A3

VCC

VCC

VCC

VCC

VCC

VCC

VCC

H7

H23K7K23L7N6T6W7Y7AB7

SMD_CLK0 14
SMD_CLK1 14
SMD_CLK2 14
SMD_CLK3 14

B

VSS_LM

VCC

C

VSSA_DPLL0 10
VSSA_DPLL1 10

AG16

AG21

AH6

AH8

AH9

AH11

AH12

AH14

AH17

AH18

K28

N28

T28

W28

AB28

L25

P25

U25

Y25

AE20

G24

SM_D_MA0

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_AGP0

VSSP_AGP1

VSSP_AGP2

VSSP_AGP3

VSSP_AGP4

VSSP_AGP5

VSSP_AGP6

VSSP_AGP7

VSSP_AGP8

VSSA_DPLL0

VSSA_DPLL1

SDRAM
System
Memory

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8

SM_MA9
SM_MA10
SM_MA11
SM_MA12

VSS

VSS
VCC_SM
VCC_SM

SM_BA0
SM_BA1

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

VCCQ_SM

VSS

SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3

VSS

VSS

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

VSS
VCC_SM

A20

SM_D_MA1

B20

SM_D_MA2

B19

SM_D_MA3

C19

SM_D_MA4

A18

SM_D_MA5

A19

SM_D_MA6

C17

SM_D_MA7

C18

SM_D_MA8

B17

SM_D_MA9

A17

SM_D_MA10

A16

SM_D_MA11

C15

SM_D_MA12

C14

F20

NC

E20

NC

F12

NC

E11

NC

C21
F19
E12
A12

B16
C16

SM_DQM0

F18

SM_DQM1

D18

SM_DQM2

D13

SM_DQM3

D12

SM_DQM4

E18

SM_DQM5

F17

SM_DQM6

F14

SM_DQM7

F13

SM_CS#0

E17

SM_CS#1

F16

SM_CS#2

D16

SM_CS#3

D15
E15
E14

SM_D_CLK0

A15

SM_D_CLK1

B2

SM_D_CLK2

B14

SM_D_CLK3

A3
A14
C3

SM_CKE0

A13

SM_CKE1

C9

SM_CKE2

C13

SM_CKE3

A9
B13
A8

SM_D_MA[0..12]

XOR layout note:
F20,E20,F12,E11 add
testpoint for factory

R319 10

1 2

R310 10

1 2

C452 .1UF

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

1 2

C512 .1UF

+3V

+3V

D

SM_D_MA[0..12] 13

+3V

SM_BA0 14
SM_BA1 14
SM_DQM[0..7] 14

SM_CS#0 14
SM_CS#1 14
SM_CS#2 14
SM_CS#3 14

SM_CKE0 14
SM_CKE1 14
SM_CKE2 14
SM_CKE3 14

VSSA_DPLL0
VSSA_DPLL1

R254 0

1 2

R306 0

1 2

*
*

For Al m a d o r-M A3 s t e pping r e quirement.

E

Layout note :

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SM_VREF0

SM_VREF1

C24

E5

M24

P24

T24

V24

Y23

M14

M15

M16

P12

R12

F24

T12

P18

R18

T18

Line length 0.15 inches +- 50mils

12

C494
.1UF

SM_OCLK

SM_RCLK

A24

12

SM_WE#

A21

SM_RCLK

C493
.1UF

SM_CAS#

D19

SM_OCLK

Layout note :

SM_RAS#

C20

+V_SMREF

Close to Ball E5 and F24

1.Placement TP6 for Almad or- M A 2 st epping die.

2.The 0.1uF capacitor and connection to +3V
must be implanted for Almador-M A3 stepping
die.

R312 10

1 2

R311 10

1 2

R316 10

1 2

1 2

C507 @22PF

Layout note :

near pin C24

C

SM_RAS# 14
SM_CAS# 14
SM_WE# 14

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

D

Date: Sheet

987Thursday, September 13, 2001

E

1A

of

A

Layout note :

Place close to AE16,
AE15 of GMCH

1 1

AGP_SBA[0..7]15

AGP_CBE#[0..3]15

AGP_ADSTB015

AGP_ADSTB#015

AGP_ADSTB115

2 2

3 3

4 4

AGP_ADSTB#115

AGP_SBSTB15
AGP_SBSTB#15
AGP_FRAME#15

AGP_IRDY#15
AGP_TRDY#15
AGP_STOP#15

AGP_DEVSEL#15

AGP_REQ#15

AGP_GNT#15

AGP_PAR15

AGP_AD[0..31]15

AGP_PAR : Strapping option for SW detection of
AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device

+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_AD[0..31]

AGP_PAR

R272

1 2

8.2K

A

AGP_ADSTB0
AGP_ADSTB#0
AGP_ADSTB1
AGP_ADSTB#1
AGP_SBSTB
AGP_SBSTB#
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_DEVSEL#
AGP_REQ#
AGP_GNT#
AGP_PAR

R279

1 2

@330

12

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

C413
68PF

U7C

AA29

AGP_SBA0/ZV_D8

AA24

AGP_SBA1/ZV_D7

AA25

AGP_SBA2/ZV_D6

Y24

AGP_SBA3/ZV_D5

Y27

AGP_SBA4/ZV_D2

Y26

AGP_SBA5/ZV_D1

W24

AGP_SBA6/ZV_D0

Y28

AGP_SBA7/ZV_HREF

L27

AGP_CBE#0/DVOB_D7

P29

AGP_CBE#1/DVOB_BLANK#

R27

AGP_CBE#2/ZV_VSYNC

T25

AGP_CBE#3/DVOC_D5

L29

AGP_ADSTB0/DVOB_CLK

L28

AGP_ADSTB#0/DVOB_CLK#

U29

AGP_ADSTB1/DVOC_CLK

U28

AGP_ADSTB#1/DVOC_CLK#

AA27

AGP_SBSTB/ZV_D4

AA28

AGP_SBSTB#/ZV_D3

R29

AGP_FRAME#/M_DDC1_DATA

P26

AGP_IRDY#/M_I2C_CLK

P27

AGP_TRDY#/M_DDC1_CLK

N25

AGP_STOP#/M_DDC2_DATA

R28

AGP_DEVSEL#/M_I2C_DATA

AC27

AGP_REQ#/ZV_CLK

AD29

AGP_GNT#/ZV_D15

P28

AGP_PAR/DVO_DETECT

J29

AGP_AD0/DVOB_HSYNC

J28

AGP_AD1/DVOB_VSYNC

K26

AGP_AD2/DVOB_D1

K25

AGP_AD3/DVOB_D0

L26

AGP_AD4/DVOB_D3

J27

AGP_AD5/DVOB_D2

K29

AGP_AD6/DVOB_D5

K27

AGP_AD7/DVOB_D4

M29

AGP_AD8/DVOB_D6

M28

AGP_AD9/DVOB_D9

L24

AGP_AD10/DVOB_D8

M27

AGP_AD11/DVOB_D11

N29

AGP_AD12/DVOB_D10

M25

AGP_AD13/DVOBC_CLKINT#

N26

AGP_AD14/DVOB_FLD/STL

N27

AGP_AD15/M_DDC2_CLK

R25

AGP_AD16/DVOC_VSYNC

R24

AGP_AD17/DVOC_HSYNC

T29

AGP_AD18/DVOC_BLANK#

T27

AGP_AD19/DVOC_D0

T26

AGP_AD20/DVOC_D1

U27

AGP_AD21/DVOC_D2

V27

AGP_AD22/DVOC_D3

V28

AGP_AD23/DVOC_D4

U26

AGP_AD24/DVOC_D7

V29

AGP_AD25/DVOC_D6

W29

AGP_AD26/DVOC_D9

V25

AGP_AD27/DVOC_D8

W26

AGP_AD28/DVOC_D11

W25

AGP_AD29/DVOC_D10

W27

AGP_AD30/DVOBC_INTR#/DPMS_CLK

Y29

AGP_AD31/DVOC_FLD/STL

ALMADOR-M

AGP_PIPE#15
AGP_WBF#15

AGP_RBF#15

AGP_ST[0..2]15

B

+VTT

V14

V15

V16

AE16

AE15

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

AGP

Interface

(DVOB/DVOC & ZV port)

AGP_PIPE#/ZV_D10

AGP_WBF#/ZV_D9

AGP_RBF#/ZV_D11

AGP_ST0/ZV_D14

AB26

AB29

AB25

AC28

AGP_PIPE#
AGP_WBF#
AGP_RBF#

AGP_ST[0..2]

B

AGP_ST0

C

0_0805

1 2

AE7

AC9

AC8

VCCPCMOS_LM

VCCPCMOS_LM

R277

+VTT

AF26

AG27F5J5M5R5V5AA5

VCCA_DAC

VCCA_DAC

VCCPCMOS_LM

+1.5VS

+1.8VS

+3V

AD15

AD16

AE25

AD23

J24

F26

VDD_LM

VDD_LM

VCCP_IO

VCCP_IO

VCCP_HUB

VCCP_HUB

N24

W23

VCCQ_AGP

C330 .1UF

C483 .1UF

J26

M26

VCCP_AGP

VCCQ_AGP

VCCP_AGP

+VTT

AA23

VCCP_AGP

U24

VCCP_AGP

+3V

AE6G7G10

VCCQ_SM

VCCA_HPLL

VCCA_CPLL

Power

Interface

+1.8VS

G20

AF6

VCCQ_SM

VCCPCMOS_LM

12
12

R26

V26

AA26

L23

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

+1.8VS

12

12

C384
.1UF

VCC_H

AD5

C283
@.1UF

+1.5VS

AG5

E2

AC20

F25

AC21

AF21

VCC_H

VCC_H

VCC_H

VCCP_DVO

VCCP_DVO

VCCA_DPLL0

VCCA_DPLL1

Display

Interface

12

12

C383
.01UF

VCC_H

VCC_H

VCC_H

VCC_H

VCC_H

(DVOA port)

Almador-M
GMCH

A3

Local Memory
Interface

Local Memor y
Interface

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCQ_SM

VCCQ_SM

VCCP_SM

VCCQ_SM

VCCP_SM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

AGP_ST1/ZV_D13

AGP_ST2/ZV_D12

LM_CMD

LM_SCK

LM_SIO

LM_RQ0

LM_RQ1

LM_RQ2

LM_RQ3

LM_RQ4

LM_RQ5

LM_RQ6

LM_RQ7

LM_RCLK

LM_GCLK

LM_RAMREF0

LM_RAMREF1

LM_CTM

LM_CTM#

LM_CFM

LM_CFM#

AC29

AB27

AH7

AF7

AJ7

AG11

AJ12

AG12

AH13

AG13

AJ13

AG14

AJ14

AJ6

AG6

AD14

AE14

AH15

AJ15

AJ16

AH16

D5D8D11

D14

D17

D20

D23

D26F7F15

G11

G19

G23

AC10

AC11

AGP_ST2

AGP_ST1

R234 10K

1 2

R239 10K

1 2

12

C340
.1UF

C

VCC_LM

AD11

AD12

AD13

AE18

AD17

AD18

12

C328
.1UF

**

C282
@.1UF

@220UF_4V_D2

AF24

DAC_VSYNC
DAC_HSYNC

VCCP_DVO

DAC_RED#

DAC_GREEN#

DAC_BLUE#

DAC_RED

DAC_GREEN

DAC_BLUE

IO_DDC1CLK

IO_DDC1DATA

DAC_REFSET

DVO_CLKIN

DVO_BLANK#

DVO_VSYNC
DVO_HSYNC

IO_I2CCLK

IO_I2CDATA

DVO_CLK#

DVO_CLK

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

IO_DDC2DATA

IO_DDC2CLK

DVO_INTR#
DVO_FIELD

LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
LM_DQA5
LM_DQA6
LM_DQA7

LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7

AGP_BUSY#

VCC_LM

AD19

+3V

+VS_RIMMREF

C286

D

D

**

C285

@220UF_4V_D2

*

1 2
1 2

AE29
AD28
AF28
AG28
AH27
AF29
AG29
AH28
AE27
AD27
AJ27

AD20
AD21
AF23
AF22
AD25
AC25
AG24
AJ24

AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26

AD26
AE26
AE21
AE22

AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20

AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8

AC24

+1.8VS

VSSA_DPLL0 9
VSSA_DPLL1 9

L3 0_0805

L4 0_0805

+1.5VS

IO_DDC1CLK
IO_DDC1DATA

1 2

R229 225_1%
DVOA_CLKIN

DVOA_D0
DVOA_D1

DVOA_D4
DVOA_D5
DVOA_D6

DVOA_INTR#

DVOA_FIELD

AGP_BUSY#

12

C354
68PF

E

Strap Name Low Hig h
DVOA_D0 Reserved 133MHz
DVOA_D1 IOQD=2 IOQD=8

+VTT

R301 0
1 2
1 2

R299 0

R269 @2.2K
R226 2.2K

R240 @2.2K

R261 10K
R263 10K

XOR layout note: AE24,AJ25
add testpoint for factory

R251 10K
R250 10K

Title

Size Document Number Rev
Custom

Date: Sheet

DVOA_D5 Desktop Mo b ile

*

DVOA_D6 Dual Ended Term Single Ended Term

**

1 2
1 2

1 2

DAC_VSYNC 16
DAC_HSYNC 16
DAC_RED# 16
DAC_GREEN# 16
DAC_BLUE# 16
DAC_RED 16
DAC_GREEN 16
DAC_BLUE 16

VCH_I2CDATA 15
VCH_I2CCLK 15

1 2
1 2

TV_OUT_DDC2DATA 15
TV_OUT_DDC2CLK 15

1 2
1 2

R257

1 2

@10K

AGP_BUSY# 15,17

DVOA_D6
DVOA_D5

DVOA_D0

R252 10K

1 2

R262 10K

1 2

R551 @0

1 2

R552 @0

1 2

+3VS

DVOA_CLKIN
DVOA_INTR#

DVOA_FIELD

+3VS

+3VS

*

1 2

R232@2.2K

+3VS

AGP_DDCCLK 15,16
AGP_DDCDATA 15,16

R551,R552: No stuff in AGP mode,
Stuff in VCH mode

R259 100K

1 2

R255 100K

1 2

R256 10K

1 2

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121
401191 (FOR ATL02 / ACL00)

10 87Thursday, September 13, 2001

E

H_BSEL0 5,12

+1.5VS

of

1A

A

B

C

D

E

Layout note :

Distri bute as close as possible
to GMCH Processor Quadrant .

+VTT

1 1

+VTT

2 2

3 3

+VTT

+VTT

+VTT

+VTT

12

C353
.1UF

12

C437
.1UF

12

C127

+

220UF_4V_D2

12

C80

+

220UF_4V_D2

12

C36

+

220UF_4V_D2

12

C475
.1UF

12

12

C327

C350

.1UF

.1UF

12

12

C454

C466

.1UF

.1UF

12

C405
.1UF

12

C410
.1UF

12

C380
.1UF

12

12

C484

C490

.1UF

.1UF

12

12

C358

C357

.1UF

.1UF

12

12

C474

C427

.1UF

.1UF

12

12

C404

C403

.1UF

.1UF

12

12

C463

C473

.1UF

.1UF

12

12

C401

C422

.1UF

.1UF

12

12

C402

C504

.1UF

.1UF

12

12

C429
.1UF

C28
.1UF

C451
.1UF

12

C344
.1UF

C438
.1UF

C417
.1UF

12

12

C387
.1UF

12

C460
.1UF

12

C436
.1UF

12

C74
.1UF

12

C456
.1UF

12

C464
.1UF

12

C407

C419

.1UF

.1UF

12

12

C459

C462

.1UF

.1UF

12

12

12

C386

C372

.1UF

.1UF

12

12

C31

C88

.1UF

.1UF

12

12

C465

C458

.1UF

.1UF

12

C399

C423

.1UF

.1UF

12

12

C78

C83

.1UF

.1UF

12

12

C472

C468

.1UF

.1UF

12

C343
.1UF

12

C435
.1UF

12

12

C418
.1UF

12

12

C81
.1UF

12

12

C441
.1UF

12

C414
.1UF

Layout note :

Distribute as close as possible
to VCCPCMOS_LM .

+1.8VS

12

C302

+

22UF_16V_1206

12

C363
.1UF

Layout note :

Distribute as close as possible
to GMCH Local Memory Quadrant .

+1.8VS

12

C345
82PF

12

+

22UF_16V_1206

C301

12

C359
.1UF

Layout note :

Distribute as close as possible
to GMCH AGP/DVO Quadrant .

+1.5VS

12

+

22UF_16V_1206

C287

12

12

C336

C335

.1UF

.1UF

Layout note :

Distribute as close as possible
to GMCH System Memory Quadrant .

+3V

12

+

22UF_16V_1206

C523

12

12

C477

C482

.1UF

.1UF

12

C364
.1UF

12

12

C361

C360

82PF

.1UF

12

12

C379

C382

82PF

.1UF

12

12

C481

C503

82PF

.1UF

12

C365
.01UF

12

12

C355

C356

.1UF

.1UF

12

12

C415

C400

82PF

.1UF

12

12

C501

C502

82PF

.1UF

12

+

12

12

C298
68UF_4V_B2

12

C366
.1UF

12

C500
.1UF

12

C406
.1UF

C489
.1UF

C334
.01UF

12

+

C299
68UF_4V_B2

12

C428
82PF

12

C496
82PF

12

12

+

C442
.1UF

C498
.1UF

12

C319
68UF_4V_B2

12

C244
.1UF

12

C495
.1UF

12

C320

+

@68UF_4V_B2

12

C457
82PF

12

C497
82PF

12

C300

+

@68UF_4V_B2

12

C443
.1UF

12

12

12

C480
.1UF

C479
.1UF

C491
.1UF

12

C505
.1UF

Layout note :

+VTT

12

C62

+

220UF_4V_D2

4 4

12

C106

+

220UF_4V_D2

Distribute as close as possible
to IO Quadrant .

+3V

12

C524

+

22UF_16V_1206

12

C499
.1UF

12

C511
.1UF

Compal Electronics, inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

11 87Thursday, September 13, 2001

E

of

1A

A

B

C

D

E

+3VS

Check Bead Value
should be 19.6K

1 1

+3VS

+3VS

+3VS

12

12

12

R146
10K

H_BSEL15
H_BSEL05,10

2 2

CLK_ICH4817

3 3

CLK_DREF8

CLK_ICH1417
CLK_SIO1425

12

R145
@0

12

12

R110
330

R112
@0

C135
@10PF

12

12

R111
330

SEL2
SEL1
SEL0

R114
@0

VTT_PWRGD#5,33

C148
@10PF

Place Crystal within 500 mils of CK_Titan

C118 5PF

1 2

caps are internal
to CK_TITAN

1 2

C129 5PF

R528 0

PM_SLP_S1#17,33
PM_SLP_S3#17,33

PM_STPPCI#17

PM_STPCPU#17

+3V

SMB_DATA7,14,17

SMB_CLK7,14,17

+3V

CLK_VCH15

R137 220_1%

1 2

R141 22

1 2

R149 22

1 2

R108 33

1 2
1 2

R109 33

Place caps. near
CK Titan (U5)

+3VS

R157 4.7K

1 2

R529 @0

1 2

R116 0

1 2

R562 10K

1 2
21

D47

RB751V

R138 10K

1 2

1 2

1 2

R154 4.7K
R151 @33

1 2

R151: No stuff in AGP mode
Stuff in VCH mode

* 221_1%

* 33

* 33

12

Y1

14.318MHZ

L6
CHB2012U170

1 2

U10

2

40
55
54

25
34
53

28

43

29
30

33
35

42

39

38

56

ICS950805

+3V_CLK

XTAL_IN

SEL2
SEL1
SEL0

PWR_DWN#
PCI_STOP#
CPU_STOP#

VTT_PWRGD#

MULT0

SDATA
SCLK

3V66_0/DRCG
3V66_1/VCH_CLK

IREF

48MHZ_USB

48MHZ_DOT

REF

Width=40 mils

181419323746

VDD_PCI

VDD_PCI

VDD_REF

VDD_3V66

VDD_3V66

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

GND_REF

GND_PCI

GND_PCI

GND_3V66

GND_3V66

491520313641

12

+

C115

22UF_16V_1206

50

VDD_CORE

VDD_CPU

VDD_CPU

VDD_48MHZ

GND_COREXTAL_OUT

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

66MHZ_IN/3V66_5

PCICLK_F2
PCICLK_F1
PCICLK_F0

GND_48MHZ

GND_IREF

GND_CPU

47

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

12

C152
.01UF

12

+

C128
22UF_16V_1206

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

C121
.01UF

L5
CHB2012U170

1 2

CLK_BCLK

CLK_BCLK#
CLK_GCLK

CLK_GCLK#

12

12

C122
.01UF

PCIF1
PCIF0

12

C124

C155

.01UF

.01UF

+3VS

Place all these Block's
Components near CK_Titan(U5)

1 2

R324 33

12

12

R334
475_1%

R34
475_1%

1 2

R329 61.9_1%

R328 61.9_1%

1 2
1 2

R323

1 2

R32 33

1 2

R33 61.9_1%

R31 61.9_1%

1 2

R30 33

1 2

12

C147
@10PF

12

12

C156
.01UF

C149
@10PF

12

C123
.01UF

CLK_HCLK 5

Place all these Block's
Components near CPU (U1)

33

12

C150
@10PF

CLK_HCLK# 5
CLK_GHT 8

CLK_GHT# 8

CLK_GBOUT 8

CLK_AGPCONN 15
CLK_GBIN 8
CLK_ICHHUB 17

CLK_ICHPCI 17

CLK_PCI_CB 23
CLK_PCI_LAN 21
CLK_LPC_SIO 25
CLK_PCI_1394 22
CLK_PCI_SD/SM 29
CLK_LPC_EC 33
CLK_MINIPCI 28

Place caps. near
CK_Titan (U5)

Place all these Block's
Components near GMCH (U6)

12

@33_0402

@10PF

C154

R155

12

12

C133

C130

.01UF

.01UF

26

12

C120

.01UF
273
45

44
49

48
52

51
24

R153 33

23

R150 33

22

R147 33

21

R119: Stuff in AGP mode

No stuff in VCH mode

R119 33

7

R118 33

6

R115 @33

5

R143 33

18

R144 33

17

R140 33

16

R136 33

13

R125 33

12

R121 33

11

R122 33

10

Place near CPU

R36 26.7_1%

PCIF1

1 2

SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]

1 0 0 66.67 66.67
1 0 1 100.00 100.00
1 1 0 200.00 200.00
1 1 1 133.33 133.33

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

PCIF0

12

R35

137_1%

D

1 2
R351
@51.1_1%

Title

Size Document Number Rev
Custom

Date: Sheet

12

R352

348_1%

0_0603
0 ohm resistor for ICH3 doesn't
need to support APIC function.

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121
401191 (FOR ATL02 / ACL00)

CLK_CPU_APIC 5
CLK_ICHAPIC 17

12 87Thursday, September 13, 2001

E

1A

of

A

SM_DQ[0..63]9,14 MD[0..63] 9,14

B

C

D

E

SM_DQ1 MD1

1 1

2 2

3 3

SM_DQ3 MD3

SM_DQ18 MD18

SM_DQ20 MD20
SM_DQ21 MD21

SM_DQ23 MD23

SM_DQ24 MD24
SM_DQ26 MD26

SM_DQ28 MD28
SM_DQ29 MD29
SM_DQ30 MD30

MD0SM_DQ0
MD2SM_DQ2

MD4SM_DQ4
MD5SM_DQ5
MD6SM_DQ6
MD7SM_DQ7

MD8SM_DQ8
MD9SM_DQ9
MD10SM_DQ10
MD11SM_DQ11

MD12SM_DQ12
MD13SM_DQ13
MD14SM_DQ14
MD15SM_DQ15

MD16SM_DQ16
MD17SM_DQ17

MD19SM_DQ19

MD22SM_DQ22

MD25SM_DQ25 MD57SM_DQ57
MD27SM_DQ27

SM_DQ38 MD38
SM_DQ39 MD39

SM_DQ40 MD40
SM_DQ41 MD41

SM_DQ44 MD44

SM_DQ56 MD56

SM_DQ59 MD59

SM_DQ60 MD60
SM_DQ61 MD61
SM_DQ62 MD62

MD32SM_DQ32
MD33SM_DQ33
MD34SM_DQ34
MD35SM_DQ35

MD36SM_DQ36
MD37SM_DQ37

MD42SM_DQ42
MD43SM_DQ43

MD45SM_DQ45
MD46SM_DQ46
MD47SM_DQ47

MD48SM_DQ48
MD49SM_DQ49
MD50SM_DQ50
MD51SM_DQ51

MD52SM_DQ52
MD53SM_DQ53
MD54SM_DQ54
MD55SM_DQ55

MD58SM_DQ58

MD63SM_DQ63MD31SM_DQ31

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .

+3V

12

C192
.1UF

+3V

12

C119

+

22UF_16V_1206

C167

1000PF

12

C168
.1UF

C184

1000PF

12

C164
.1UF

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .

+3V

C211

1000PF

12

C205
.1UF

C210

1000PF

12

C206
.1UF

12

C212
.1UF

+3V

12

C126

+

22UF_16V_1206

C169

1000PF

C207

1000PF

12

C170
.1UF

12

C222
.1UF

C199

1000PF

C166

1000PF

12

C196
.1UF

12

C215
.1UF

C195

1000PF

C221

1000PF

12

C194
.1UF

12

C220
.1UF

C190

1000PF

C219

1000PF

12

C189
.1UF

12

C218
.1UF

C188

1000PF

C217

1000PF

12

C209
.1UF

12

C160
.1UF

C216

1000PF

C165

1000PF

12

C203

C202

1000PF

.1UF

12

C214

C187

1000PF

.1UF

SM_D_MA[0..12]9 MAA[0..12] 14

SM_D_MA0
SM_D_MA1
SM_D_MA2
SM_D_MA3

SM_D_MA4
SM_D_MA5
SM_D_MA6
SM_D_MA7

SM_D_MA8
SM_D_MA9
SM_D_MA10

4 4

SM_D_MA11

SM_D_MA12

A

RP22
1 8
2 7
3 6
4 5

8P4R_10

RP21
1 8
2 7
3 6
4 5

8P4R_10

RP20
1 8
2 7
3 6
4 5

8P4R_10
1 2

R176 10

MAA0
MAA1
MAA2
MAA3

MAA4
MAA5
MAA6
MAA7

MAA8
MAA9
MAA10
MAA11

MAA12

Compal Electronics, inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

13 87Thursday, September 13, 2001

E

of

1A

A

B

C

+3V+3V

+3V

D

E

SO-DIM 144 PINS

C142

RAM MODULE CONN.

MD0

1 1

MAA[0..12]13

MD[0..63]9

SM_DQM[0..7]9

2 2

3 3

MAA[0..12]

MD[0..63]
SM_DQM[0..7]

SMD_CLK09

SM_RAS#9
SM_WE#9
SM_CS#09
SM_CS#19

MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

R174

C204

10PF

22

SM_RAS# SM_CAS#
SM_WE# SM_CKE1
SM_CS#0 MAA12
SM_CS#1

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM0 SCKDIMM0

BANK 0/1

+3V +3V

JP26

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144-STANDRD

RESVD/DQ68
RESVD/DQ69

RESVD/DQ70
RESVD/DQ71

CE6#/RESVD
CE7#/RESVD

VSS
DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

VSS
CE4#
CE5#

VCC

VSS

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

VSS

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

VSS

VCC
DQ48
DQ49
DQ50
DQ51

VSS
DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0

VSS

A12/BA1

A13/A11

VCC

VSS
DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VSS
SCL

VCC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

A3

32

A4

34

A5

36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104

A7

106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

SM_DQM1
SM_DQM5

MAA3
MAA4
MAA5

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

SM_CKE0

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

SM_BA0
SM_BA1

SM_DQM3
SM_DQM7

MD56
MD57
MD58
MD59

MD60
MD61
MD62
MD63

+

10UF_10V_1206

SM_CKE0 9

SM_CKE1 9

R175
22

C223
10PF

SM_BA0 9
SM_BA1 9

DIMM0

SM_SEL017

SMB_CLK7,12,17

4 4

+3V

RP4

8P4R_10K

SCKDIMM1
SCKDIMM0
SDADIMM1
SDADIMM0

A

B

1 8
2 7
3 6
4 5

SMB_DATA7,12,17

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C143

+

10UF_10V_1206

SMD_CLK1 9

C230

.1UF

6

INH

10

A

9

B

3

X

13

Y

+3V

7

C

16

GND

8

VCC

GND

C132

+

10UF_10V_1206

SMD_CLK29

U18

1

X0

5

X1

2

X2

4

X3

12

Y0

14

Y1

15

Y2

11

Y3

74HC4052

SM_CS#29
SM_CS#39

SCKDIMM0
SCKDIMM1

SDADIMM0
SDADIMM1

BANK 2/3

+3V +3V

JP27

1
MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

C163

R162

10PF

22

SM_RAS# SM_CAS#

SM_WE# SM_CKE3
SM_CS#2 MAA12
SM_CS#3

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144 REVERSE

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0
A12/BA1

A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
SCL

A3
A4
A5

A7

DIMM1

SM_SEL0 X/Y

0 SCKDIMM0

SCKDIMM11

Title

Size Document Number Rev

D

Date: Sheet

2

MD8

4

MD9

6

MD10

8

MD11

10
12

MD12

14

MD13

16

MD14

18

MD15

20
22

SM_DQM1

24

SM_DQM5

26
28

MAA3

30

MAA4

32

MAA5

34
36

MD40

38

MD41

40

MD42

42

MD43

44
46

MD44

48

MD45

50

MD46

52

MD47

54
56
58
60

SM_CKE2

62
64
66
68
70
72
74
76
78
80
82

MD24

84

MD25

86

MD26

88

MD27

90
92

MD28

94

MD29

96

MD30

98

MD31

100
102
104

SM_BA0

106
108

SM_BA1

110
112
114

SM_DQM3

116

SM_DQM7

118
120

MD56

122

MD57

124

MD58

126

MD59

128
130

MD60

132

MD61

134

MD62

136

MD63

138
140

SCKDIMM1

142
144

SM_CKE2 9
SM_CAS# 9

SM_CKE3 9

R170
22

C193
10PF

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121

B

401191 (FOR ATL02 / ACL00)

E

SMD_CLK3 9

14 87Thursday, September 13, 2001

1A

of

5

4

3

2

1

RTCCLK17,23,24,29

+2.5V

+3VS
+5VS

+1.5V

+

C101

22UF_16V_1206

JP13

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

AMP-108-5424

KSI[0..7]
KS0[0..15]

KSI0
KSI2
KSI4
KSI6
KSO0
KSO2
KSO4
KSO6
KSO8
KSO10
KSO12
KSO14

Int. Keyboard CONN.

JP11

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

HEADER 2X20

12

C146
1UF_25V_0805

GND

GND

+5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

AUDIO_PWDN

MONO_PHONE

RESERVED

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0

AC97_BITCLK

MDC CONN.

KSI1
KSI3
KSI5
KSI7
KSO1
KSO3
KSO5
KSO7
KSO9
KSO11
KSO13
KSO15

12

C145

1UF_25V_0805

+5VS_MDC

1 2

R378 22

+12V
+3V+3V

+5V

1 2

L41 CHB1608B121

1 2

R388 10K

1 2

R548 @22

1 2

R383 22

+5VS_MDC+3VS_MDC+3.3VAUX

12

C159

1UF_25V_0805

MDC_DN# 34MD_MIC31
MD_SPK 31

1 2

R381 @10K

IAC_BITCLK 17,31

+5VS

+3VS

IAC_SYNC 17,31

IAC_SDATAI1 17

KSI[0..7]33

KSO[0..15]33

AGP CONN.

JP8

D D

C C

AGP_IRDY#10

AGP_DEVSEL#10

B B

AGP_AD[0..31]10
AGP_SBA[0..7]10

AGP_R16
AGP_G16

AGP_B16
AGP_HSYNC116
AGP_VSYNC116

AGP_DDCDATA10,16

AGP_DDCCLK10,16

DDC_MD216

M_SEN#16,18

+5VALW

DAC_BRIG33

CBRST#21,22,23,24,28,29

+1.5VS +1.5VS

SUS_STAT#17,21,25,35

AGP_BUSY#10,17

AGP_REQ#10

AGP_ST010
AGP_ST210

AGP_RBF#10

AGP_SBSTB10

CLK_AGPCONN12

AGP_ADSTB110

AGP_CBE#210

CLK_VCH12

AGP_CBE#110

AGP_ADSTB010

+VAGP_BRDREF +VAGP_CRDREF

R104

AGP_CLK

1 2

@33
R120

CLK_VCH

1 2

@33

+1.5V

AGP_IRDY#
AGP_DEVSEL#

AGP_AD[0..31]
AGP_SBA[0..7]

DAC_BRIG

AGP_SBA0
AGP_SBA2

AGP_SBA4
AGP_SBA6
AGP_CLK

AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17

CLK_VCH

AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8

STP_AGP#
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1

C112

1 2

@15PF
C125

1 2

@15PF

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

HEADER 2X60

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

SUS_STAT#17,21,25,35

INVT_PWM

ENBKL
ENVEE

PCI_RST#

AGP_SBA1
AGP_SBA3

AGP_SBA5
AGP_SBA7

AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24

AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16

AGP_FRAME#

AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9

AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0

C3_STAT#17

CRMA 16
LUMA 16
COMPS 16
TV_SYNC 16

TVOUT_IO_DDC2CLK
TVOUT_IO_DDC2DATA
VCH_IO_I2CCLK
VCH_IO_I2CDATA

INVT_PWM 33

+5VALW

ENBKL 33
ENVEE 33

+1.5V

PIRQA# 17,19,22,23
PCIRST# 8,17,19,20,21,22,23,24,25,28,29,35
AGP_GNT# 10
AGP_ST1 10
AGP_PIPE# 10
AGP_WBF# 10

AGP_SBSTB# 10

AGP_CBE#3 10

AGP_ADSTB#1 10

AGP_FRAME# 10
AGP_TRDY# 10
AGP_STOP# 10
AGP_PAR 10

AGP_ADSTB#0 10
AGP_CBE#0 10

+3V

C727

1 2

.1UF

5

1
2

3

U60

4

@7SH08FU

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

STP_AGP#

RP38

In AGP mode : stuff RP38, no stuff RP39.

8P4R_0

In VCH mode: stuff RP39, no stuff RP38.

RP39

@8P4R_0

+3.3VAUX

+3VS

IAC_SDATAO17,31

IAC_RST#17,31

PID0 25
PID1 25
PID2 25
PID3 25

TV_OUT_DDC2CLK 10
TV_OUT_DDC2DATA 10
VCH_I2CCLK 10
VCH_I2CDATA 10

L39

1 2

+3VS_MDC

CHB1608B121

TP_DATA33 TP_CLK 33

1 2

A A

R544 0

Compal Electronics, inc.

Title

PROPRIETARY NOTE

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

15 87Thursday, September 13, 2001

1

of

1A

A

B

C

D

E

TV_OUT CONN.

D11

DAN217

12

C291
47PF

2

FBM-11-160808-121

1 2

FBM-11-160808-121

FBM-11-160808-121

12

C292

47PF

1 1

TV_SYNC15

LUMA15

CRMA15

COMPS15

12

12

R218

R220

75

TV_GND

R219

75

75

L17

1 2

@FBM-11-160808-121

12

12

C293

47PF

1

3

L21

1 2

L20

L22

1 2

D10

DAN217

C262

47PF

D9

1

DAN217

1

R559 For VCH (CH7011)

1 2

2

3

12

12

C261

47PF

12

C270

47PF

2

3

12

C269
@470PF

R559 @0

1 2

R560 0

JP2

S CONN._SUYIN

1
2
3
4
5
6
7

+3VS

+5VS

R560 For CH7007

2 2

3 3

In AGP mode: No stuff R6,R8,R10,R12,R14. Stuff R9,R11,R13,R549,R550
In VCH mode: Stuff R6,R8,R10,R12,R14. No stuff R9,R11,R13,R549,R550

DAC_RED10

AGP_R15

DAC_GREEN10

AGP_G15

DAC_BLUE10

AGP_B15

4 4

In AGP mode: No stuff C326,R245,C318,R231,C325,R230.
In VCH mode: Stuff C326,R245,C318,R231,C325,R230

DAC_RED#10

DAC_GREEN#10

DAC_BLUE#10

C326 @.1UF

1 2

R245 @37.5_1%

1 2

C318 @.1UF

1 2

R231 @37.5_1%

1 2

C325 @.1UF

1 2

R230 @37.5_1%

1 2

CRT Connector

DDC_MD215

M_SEN#15,18

R14 @0

1 2

R13 0

1 2

R12 @0

1 2

R11 0

1 2

R10 @0

1 2

R9 0

1 2

12

R199

@75

1 2

AGP_HSYNC115

FROM AGP CONN.

FROM GMCH

AGP_VSYNC115

+12VS

DAC_HSYNC10

DAC_VSYNC10

A

1 2
1 2

C265

R200

18PF

@75

0

R549

0

R550

R202 100K

R6 @33

*

R8 @33

*
*
*
*
*
*

+5VS

+5VS

12

R86
10K

L10

1 2

FCM2012C80_0805

L11

1 2

FCM2012C80_0805

L12

1 2

R201

@75

1 2

13

2N7002

2

B

FCM2012C80_0805

12

C266
18PF

Q18

13

Q17

2N7002

2

1 2

1 2

CHB1608B121

12

C264
18PF

1 2

D7

DAN217

2

12

C256
15PF

L1

CHB1608B121

L2

1

3

1

D6

DAN217

2

12

C255
15PF

12

C3
68PF

*10PF *10PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D5

DAN217

3

2

12

C254
15PF

12

C4
68PF

+5VS

1

3

12

C250
100PF

C

D8

2 1

RB491D

12

FUSE_1A

C253
100PF

220PF

CRT_VCCR_CRT_VCC

F1

21

12

C5
.1UF

CRT_VCC

12

12

C2

C252
220PF

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

5VDDCDA

5VDDCCL

JP3
CRT-15P

CRT_VCC

12

CRT_VCC

R553
@2.2K

In AGP mode: Stuff R16,R15,R7. No stuff R553,R554,R555.
In VCH mode: Stuff R553,R554,R555. No stuff R16,R15,R7

+5VS+5VS+12VS +3VS

12

12

R554
@2.2K

Q1

2N7002

1 3

12

2

R555
@2.2K

12

R15

2.2K

R16
100K

2

1 3

Q3
2N7002

12

R7

2.2K

AGP_DDCDATA 10,15

AGP_DDCCLK 10,15

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

401191 (FOR ATL02 / ACL00)

Custom

D

Date: Sheet

16 87Thursday, September 13, 2001

E

1A

of

A

PM_BATLOW#33

1 2

R295 10M

12

R522

2.4M

PM_CPUPERF#5,19

PM_DPRSLPVR7,43

J2

K1

J4

K3

H5

K4

H3

L1
L2

G2

L4
H4
M4

J3

M5

J1

F5
N2
G4

P2
G1

P1

F2

P3

F3
R1

E2
N4
D1

P4

E1

P5

K2

K5
N1
R2

A4

E3
D2
D5

B4

D3

F4

A3
R4

E4

C461
12PF

PM_GMUXSEL7,43

PM_STPCPU#12

PM_RSMRST#36
SYS_PWROK36

PM_CLKRUN#19,22,23,25,28,29,33

ICH_VGATE36

ATF_INT#33

SUS_STAT#15,21,25,35

PM_STPPCI#12
PM_SLP_S5#33

PM_SLP_S3#12,33
PM_SLP_S1#12,33

ICH_RI#19

C3_STAT#15

AGP_BUSY#10,15

U33A

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

ICH3-M

12

PBTN#19

PM_LANPWROK

1 2

R294 10M

X2

32.768KHZ

PM_RSMRST#

1 2

V4Y5AB3V5AC2

PM_AGPBUSY#/GPIO6

PCI

Interface

VSS0

VSS1

A1

A13

12

C444
12PF

R370

AB21

AB1

AA6

AA1

AA7

W20

AA5

AA2

PM_RI#

PM_PWROK

PM_SLP_S3#

PM_PWRBTN#

VSS7

B13

VSS8

B14

PM_RSMRST#

VSS9

VSS10

B15

B18

+RTCVCC

PM_SLP_S5#

PM_SLP_S1#/GPIO19

VSS11

VSS12

VSS13

B19

B20

PM_BATLOW#

PM_DPRSLPVR

PM_AUXPWROK

PM_CLKRUN#/GPIO24

PM_C3_STAT#/GPIO21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

VSS2

VSS3

VSS4

VSS5

VSS6

A16

A17

A20

A23B8B10

RTC_VBIAS
RTC_X1

RTC_X2

PCI_AD[0..31]21,22,23,28,29

ECSMI#
ECSCI#
LID#
IDE_PATADET
R60 0

R287 1K

1 2

PM_SUSCLK

12

IAC_BITCLK
IAC_RST#

IAC_SDATAI0
IAC_SDATAI1

IAC_SDATAO
IAC_SYNC

PCI_C/BE#021,22,23,28,29
PCI_C/BE#121,22,23,28,29
PCI_C/BE#221,22,23,28,29
PCI_C/BE#321,22,23,28,29

PCI_GNT#019,22
PCI_GNT#119,28
PCI_GNT#219,23
PCI_GNT#319,21
PCI_GNT#419,28

PCI_REQ#019,22
PCI_REQ#119,28
PCI_REQ#219,23
PCI_REQ#319,21
PCI_REQ#419,28

1 2

R521 22M

C426

1 2

.047UF

A

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ECSMI#19
ECSCI#19

LID#19

IDE_PATADET20

RTCCLK15,23,24,29

IAC_BITCLK15,31

IAC_RST#15,31
IAC_SDATAI031
IAC_SDATAI115

1 1

IAC_SDATAO15,31

IAC_SYNC15,31

2 2

Place closely to ICH3-M

CLK_ICH14

12

R337
@10

12

C541
@15PF

CLK_ICH48

12

3 3

R340
@10

12

C534
@15PF

+RTCVCC

4 4

V21

U21

PM_STPCPU#/GPIO20

VSS14

B22C3C6

CLK_ICH1412
CLK_ICH4812

PM_SUSCLK

AA4

PM_SUS_CLK

PM_STPPCI#/GPIO18

VSS15

VSS16

AB4U5U20

PM_THRM#

PM_SUS_STAT#

GeyservillePower Management

VSS

VSS17

VSS18

VSS19

F19

C14

C15

1 2

R286 15K

B

C60

10PF

IAC_SDATAO

IAC_SYNC

12

22

R72

1 2

1 2

IAC_SDATAI0

IAC_SDATAI1

IAC_BITCLK

IAC_RST#

R69 47

R70 47

Y20

V19B7D11

B11

C11C7A7V1U3T3U2T2U4U1V2W2Y4Y2W3W4Y3

AC_RST#

AC_SYNC

AC_BITCLK

AC_SDATAIN0

AC_SDATAIN1

AC_SDATAOUT

PM_GMUXSEL/GPIO23

PM_CPUPREF#/GPIO22

AC'97

PM_VGATE/VRMPWRGD

Interface

ICH3-M (1/2)

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

C16

C17

C18

C19

C20

C21

C22D9D13

D16

D17

D20

D21

CLK_ICH14
CLK_ICH48

12

C416

1UF_10V_0603

B

PIDEPWR

ECSCI#

LID#

ECSMI#

IDE_PATADET

GPIO_25

GPIO_7

GPIO_8

GPIO_12

GPIO_13

GPIO_25

CLK_VBIAS

unMUX

GPIO

Interface

LAN_RSTSYNC

LAN_JCLK

LAN

LAN_TXD2

A10C9D7

GPIO_27

LAN_TXD1

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_DRQ#0

LPC_DRQ#1

LPC_FRAME#

LPC

Interface

Clocks EEP R O M

VSS33

VSS34

D22

E5

CLK_RTCX2

CLK_RTCX1

CLK_RTEST#

CLK_48

CLK_14

AC6

AC7Y7F20

J23

AB7

RTC_VBIAS

RTC_X2

RTC_X1

RTC_RST#

12

J1
JOPEN

12

R278
1K

C

LPC_AD0 25,33
LPC_AD1 25,33
LPC_AD2 25,33
LPC_AD3 25,33
LPC_DRQ#0 19,33
LPC_DRQ#1 19,25
LPC_FRAME# 25,33

SM_SEL0 14
SIDEPWR 20
CLK_ICHAPIC 12
H_PICD0 5
H_PICD1 5

INT_IRQ14 19,20
INT_IRQ15 19,30

PCI_CLK

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_PERR#

PCI_LOCK#

PCI_PME#
PCI_RST#

PCI_SERR#

STOP#

PCI_TRDY#

SM_INTRUDER#

SMLINK0
SMLINK1

SMB_CLK

SMB_DATA

CPU_A20GATE

CPU_A20M#

CPU_DPSLP#

CPU_FERR#

CPU_IGNNE#

CPU_INIT#
CPU_INTR

CPU_NMI

CPU_RCIN#

CPU_SLP#
CPU_SMI#

STPCLK#

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9

HUB_PD10

PM_LANPWROK

C44

1 2

.1UF

INT_SERIRQ 19,23,25,33

CLK_ICHPCI

T5
M3
F1
C4
D4

GNTA#

B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

Y6
AC3
AB2
AC4
AB5
AC5

Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

HUB_PD0

L22

HUB_PD1

M21

HUB_PD2

M23

HUB_PD3

N20

HUB_PD4

P21

HUB_PD5

R22

HUB_PD6

R20

HUB_PD7

T23

HUB_PD8

M19

HUB_PD9

P19

HUB_PD10

N19

CLK_ICHHUB 12
HUB_PSTRB 8
HUB_PSTRB# 8

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHPCI 12
PCI_DEVSEL# 19,21,22,23,28,29
PCI_FRAME# 19,21,22,23,28,29
PCI_REQA# 19
PCI_REQB# 19

PCI_IRDY# 19,21,22,23,28,29
PCI_PAR 19,21,22,23,28,29
PCI_PERR# 19,21,22,23,28
PCI_LOCK# 19
ICH_WAKE_UP# 33
PCIRST# 8,15,19,20,21,22,23,24,25,28,29,35
PCI_SERR# 19,21,22,23,28
PCI_STOP# 19,21,22,23,28,29
PCI_TRDY# 19,21,22,23,28,29

SM_INTRUDER# 19
SMLINK0 19
SMLINK1 19
SMB_CLK 7,12,14
SMB_DATA 7,12,14
SMB_ALERT# 19

GATEA20 33
H_A20M# 5

H_FERR# 5
H_IGNNE# 5
H_INIT# 5
H_INTR 5
H_NMI 5
H_PWRGD 5
RC# 33

H_SMI# 5
H_STPCLK# 5

HUB_PD[0..10]

+VS_HUBREF

+VS_HUBVSWING

12

C530
.01UF

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

CLK_ICHAPIC

H_PICD0

H_PICD1

PIRQA#

J21

J20

J19

GPIO_28

INT_APICD1

INT_APICD0

INT_PIRQA#

INT_APICCLK

Interrupt
Interface

Interface

EEP_SHCLK

LAN_RXD0

LAN_RXD1

LAN_RXD2

LAN_TXD0

D10

C8A8A9B9C10

PIRQB#

ICH_PID1

ICH_PID0

PIRQD#

PIRQC#

INT_PIRQB#

INT_PIRQD#

INT_PIRQC#

INT_PIRQE#/GPIO2

EEP_CS

EEP_DIN

EEP_DOUT

E9D8E8

12

R77
@0

+3V

PM_RSMRST#

C

ICH_PID3

ICH_PID2

H22

W19

AB14A5C5B5A6A2B2C1B1

INT_IRQ15

INT_IRQ14

INT_SERIRQ

INT_PIRQF#/GPIO3

INT_PIRQH#/GPIO5

INT_PIRQG#/GPIO4

PCI_GPIO0/REQA#

PCI_GPIO1/REQB#/REQ5#

PCI_GPIO16/GNTA#

PCI_GPIO17/GNTB#/GNT5#

PCI

Interface

System

Managment

Interface

SMB_ALERT#/GPIO11

CPU

Interface

HubLink

Interface

HUB_PAR

HUB_PSTRB

HUB_PSTRB#

HUB_RCOMP

HUB_VREF

HUB_VSWING

T19

R19

N22

P23

K19

L20

L19

HUB_ICH_RCOMP

100K
R59

1 2

R67 10K

1 2

CPU_PWRGOOD

HUB_CLK

CLK_ICHHUB

D

+3VS

GNTA#
GPIO_25

PIRQA# 15,19,22,23
PIRQB# 19,21,23
PIRQC# 19,28,29
PIRQD# 19,28,29

+1.5VS

1 2

R332 0

H_PICD0
H_PICD1

HUB_PD[0..10] 8

1 2

R346

36.5_1%

12

C529
.01UF

Close to ICH3-M.

D

RP15
1 8
2 7
3 6
4 5

8P4R_4.7K

R65 @10K

1 2
1 2

R54 10K

Place closely to ICH3-M

CLK_ICHAPIC

R342
@33_0402

1 2

C540
@10PF

CLK_ICHPCI

12

R66
@10

12

C42
@15PF

12

(for use if CPU unable

R327
@10K

to support DPSLP#)

H_DPSLP# 5,43

12

12

R338

1K

17 87Thursday, September 13, 2001

ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

+3VS
+3V

R339

1K

CLK_ICHHUB

R344
10

1 2

C543
5PF

of

1A

A

B

C

D

E

CLOSE TO ICH3-M(< 1 inch)

C508 @5PF

1 2

USB_PP127
USB_PN127
USB_PP027
USB_PN027

1 1

USB_PP327
USB_PN327
USB_PP227
USB_PN227

USB_PP4
USB_PN4

+3V

RP19

2 2

3 3

4 4

8P4R_10K

1 8
2 7
3 6
4 5

Disable Timeout Feature

+3VS

C509 @5PF
C91 @5PF

C197 @5PF
C86 @5PF

12

1 2

R343
@1K

ACIN33,35,38,41

1 2

1 2

1 2

1 2

USB_OC#2
USB_OC#4

USB_OC#5

R314

18.2_1%

ICH_SPKR

A

USB_D_PP1
USB_D_PN1
USB_D_PP0
USB_D_PN0

USB_D_PP3
USB_D_PN3
USB_D_PP2
USB_D_PN2

USB_D_PP4
USB_D_PN4

USB_OC#027
USB_OC#127

USB_OC#327

ICH_IDE_PRST#20
ICH_IDE_SRST#20

FWH_WP#19

FWH_TBL#19

EC_FLASH#34

M_SEN#15,16

ICH_SPKR32

+1.8VS

+3V

R326
100K

21

D32 RB751V

1 2

USB_RBIAS

1 2

+V3A_ICH

+3VS

12

USB_D_PP0
USB_D_PP1
USB_D_PP2
USB_D_PP3
USB_D_PP4
USB_PP5
USB_D_PN0
USB_D_PN1
USB_D_PN2
USB_D_PN3
USB_D_PN4
USB_PN5

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

R98 @0

ICH_ACIN

ICH_SPKR

R309

0_0805

ICH_ACIN

+5VS +3VS

R73

1K

+1.8V

R320

1 2

0_0805

U33B

D19

USB_PP0

A19

USB_PP1

E17

USB_PP2

B17

USB_PP3

D15

USB_PP4

A15

USB_PP5

D18

USB_PN#0

A18

USB_PN#1

E16

USB_PN#2

B16

USB_PN#3

D14

USB_PN#4

A14

USB_PN#5

E12

USB_OC#0

D12

USB_OC#1

C12

USB_OC#2

B12

USB_OC#3

A12

USB_OC#4

A11

USB_OC#5

H20

USB_LEDA#0/GPIO32

G22

USB_LEDA#1/GPIO33

F21

USB_LEDA#2/GPIO34

G19

USB_LEDA#3/GPIO35

E22

USB_LEDA#4/GPIO36

E21

USB_LEDA#5/GPIO37

H21

USB_LEDG#0/GPIO38

G23

USB_LEDG#1/GPIO39

F23

USB_LEDG#2/GPIO40

G21

USB_LEDG#3/GPIO41

D23

USB_LEDG#4/GPIO42

E23

USB_LEDG#5/GPIO43

B21

USB_RBIAS

H23

SPKR

U19

VCCA

F17

VCCPSUS3/VCCPUSB0

F18

VCCPSUS4/VCCPUSB1

K14

VCCPSUS5/VCCPUSB2

E10

VCCPSUS0

V8

VCCPSUS1

V9

VCCPSUS2

ICH3-M

21

12

D26
1SS355

12

C58
.1UF

L33

1 2

CHB2012U170

E13

F14

K12

P10V6V7

VCC_SUS0

VCC_SUS1

VCC_SUS2

USB

Interface

VCC_SUS3

12

VCC_SUS4

VCC_SUS5

VCC5REF

C455
1UF_10V_0603

+V1.8_ICHLAN

F15

F16F7F8

VCC_USB0/VCC_SUS6

VCC_USB1/VCC_SUS7

VCC_AUX0/VCCLAN1_8

VCC_AUX1/VCCLAN1_8

+RTCVCC

K10

AB6E6W8

VCC_RTC

VCC_AUX2/VCCLAN1_8

+V5S_ICHREF

VCC5REF1

VCC5REF2

Misc

Power

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

E14

E15

E18

E19

E20

F22G3G20

H19

AA22J5K11

K13

K20

K21

K22

K23L3L10

B

+3V

12

R305
0

12

C492
.1UF

+3V

VCC5REFSUS

12

C13W5F9

F10

VCC5REFSUS1

VCC5REFSUS2

VCCPAUX0/VCCLAN3_3

VCCPAUX1/VCCLAN3_3

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

L11

L12

L13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+1.8V

+1.5VS

12

R341
0_0805

U18

V22

VCCPCPU1

VCCPCPU2

+1.8VA_ICH

C23

B23E7T21D6T1C2A21

N/C0

Power

VCCUSBBG/VCC_SUS8

VCCUSBPLL/VCC_SUS9

N/C1

N/C2

N/C3

N/C4

R298
0_0805

P14

VCCPCPU0

ICH3-M (2/2)

VSS

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

L14

L21

L23

M11

M12

M13

M20

M22N5N10

N11

N12

N13

N14

C

A22F6G6H6J6

VSS102

VSS71

VSS72

N21

N23

P11

VSS103

VSS73

P13

VCCPPCI0

VSS74

VSS75

P20

P22R3R5

M10R6T6U6G18

VCCPPCI1

VCCPPCI2

VCCPPCI3

VSS76

VSS77

VSS78

R21

VCCPPCI4

VCCPPCI5

VCCPPCI6

VSS79

VSS80

VSS81

R23T4T20

H18

VCCP0

VCCPPCI7

VSS82

VSS83

VSS84

T22V3AC23

+3VS +1.8VS

P12

V15

V16

V17

V18

J18

M14

R18

VCCP1

VSS85

VSS86

V20W6W7

VCCPIDE0

VCCPIDE1

VCCPIDE2

VSS87

VSS88

VSS89

W10

W14

VCCPIDE3

VCCPIDE4

VSS90

VSS91

VSS92

W18

W22Y8AA3

VCCPHL0

VCCPHL1

VSS93

VSS94

AA8

VCCPHL2

VSS95

T18

VCCPHL3

VSS96

AA12

E11K6K18P6P18

VCCCORE0

VSS97

VSS98

AA16

AA20

D

VCCCORE1

VCCCORE2

VCCCORE3

VCCCORE4

IDE

Interface

VSS99

VSS100

VSS101

AB8

AC1

AC8

V10

V14

IDE_PDCS1#
IDE_PDCS3#

VCCCORE5

VCCCORE6

IDE_SDCS1#
IDE_SDCS3#

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8

IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD0

IDE_SDD1

IDE_SDD2

IDE_SDD3

IDE_SDD4

IDE_SDD5

IDE_SDD6

IDE_SDD7

IDE_SDD8

IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDDACK#
IDE_SDDACK#

IDE_PDDREQ
IDE_SDDREQ

IDE_PDIOR#

IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#

IDE_PIORDY

IDE_SIORDY

AC15
AB15
AC21
AC22

AA14
AC14
AA15
AC20
AA19
AB20

IDE_PDD0

W12

IDE_PDD1

AB11

IDE_PDD2

AA10

IDE_PDD3

AC10

IDE_PDD4

W11

IDE_PDD5

Y9

IDE_PDD6

AB9

IDE_PDD7

AA9

IDE_PDD8

AC9

IDE_PDD9

Y10

IDE_PDD10

W9

IDE_PDD11

Y11

IDE_PDD12

AB10

IDE_PDD13

AC11

IDE_PDD14

AA11

IDE_PDD15

AC12

IDE_SDD0

Y17

IDE_SDD1

W17

IDE_SDD2

AC17

IDE_SDD3

AB16

IDE_SDD4

W16

IDE_SDD5

Y14

IDE_SDD6

AA13

IDE_SDD7

W15

IDE_SDD8

W13

IDE_SDD9

Y16

IDE_SDD10

Y15

IDE_SDD11

AC16

IDE_SDD12

AB17

IDE_SDD13

AA17

IDE_SDD14

Y18

IDE_SDD15

AC18
Y13

Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

IDE_PDCS1# 20
IDE_PDCS3# 20
IDE_SDCS1# 30
IDE_SDCS3# 30

IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20
IDE_SDA0 30
IDE_SDA1 30
IDE_SDA2 30
IDE_PDD[0..15] 20

IDE_SDD[0..15] 30

IDE_PDDACK# 20
IDE_SDDACK# 30
IDE_PDDREQ 20
IDE_SDDREQ 30
IDE_PDIOR# 20
IDE_SDIOR# 30
IDE_PDIOW# 20
IDE_SDIOW# 30
IDE_PIORDY 20
IDE_SIORDY 30

18 87Thursday, September 13, 2001

E

of

1A

A

+3VS +3VS

RP13

PCI_FRAME#17,21,22,23,28,29

PCI_IRDY#17,21,22,23,28,29

PCI_TRDY#17,21,22,23,28,29

PCI_STOP#17,21,22,23,28,29

1 1

PCI_REQA#17
PCI_REQB#17
PCI_REQ#017,22
PCI_REQ#117,28

PCI_GNT#117,28
PCI_GNT#217,23

PIRQD#17,28,29

INT_IRQ1417,20

PCI_GNT#017,22

2 2

3 3

EC_LID_OUT#33

4 4

PCI_GNT#317,21

PCI_GNT#417,28

PCIRST#8,15,17,20,21,22,23,24,25,28,29,35
SMLINK017
SMLINK117

SM_INTRUDER#17

PM_CPUPERF#5,17

PBTN_OUT#33 PBTN# 17

ON/OFF33,35

+3V

EC_RIOUT#33 ICH_RI# 17

+3V

EC_SMI#33

+3V

EC_SCI#33

+3V

1
2
3
4
5

10P8R_8.2K

+3VS +3VS

RP18
1
2
3
4
5

10P8R_8.2K

+3VS

D14 RB751V

D15 @RB751V

1 2

R38 10K
D13 RB751V

1 2

R47 10K
D16 RB751V

1 2

R42 10K
D17 RB751V

1 2

R40 10K
D18 RB751V

RP14
1
2
3
4
5

10P8R_8.2K

21

21

21

21

21

21

10
9
8
7
6

10
9
8
7
6

10
9
8
7
6

1 2

R57 8.2K

1 2

R63 8.2K

1 2

R58 8.2K

1 2

R39 @8.2K

1 2

R515 4.7K

1 2

R516 4.7K

1 2

R282 100K

R300 @10K

1 2

PBTN#

ICH_RI#

ECSMI#

ECSCI#

LID#

+3VS

ECSMI# 17

ECSCI# 17

LID# 17

B

PCI_SERR# 17,21,22,23,28
PCI_DEVSEL# 17,21,22,23,28,29
PCI_PERR# 17,21,22,23,28
PCI_LOCK# 17

PCI_REQ#2 17,23
PCI_REQ#3 17,21
PCI_REQ#4 17,28
INT_SERIRQ 17,23,25,33

INT_IRQ15 17,30
PIRQA# 15,17,22,23
PIRQB# 17,21,23
PIRQC# 17,28,29

+3VS

+3V

+RTCVCC

+VTT

+3VS

12

+

+3V

12

+

22UF_16V_1206

+1.8VS

12

+

+1.8VA_ICH

12

+

22UF_16V_1206

PM_CLKRUN#17,22,23,25,28,29,33

SMB_ALERT#17

LPC_DRQ#017,33

LPC_DRQ#117,25

C362
22UF_16V_1206

C341

C317
150UF_6.3V_D2

C527

C92

C82

.1UF

.1UF

FWH_WP#18
FWH_TBL#18

12

+

C385
22UF_16V_1206

12

C486
.1UF

12

C85
.1UF

12

C531
.1UF

C

R289 10K

R45 10K

R56 10K

12

12

12

C485

C488

.1UF

.1UF

12

C52
47PF

12

12

C533

C532

.1UF

.1UF

C61

C66

.1UF

.1UF

1 8
2 7
3 6
4 5

1 2

1 2

1 2

C51
.1UF

12

C95
.1UF

RP24

8P4R_10K

12

12

C487
47PF

C104
.01UF

C47
.1UF

12

C96
.1UF

+V3A_ICH

D

+3VS

R71 @100

PCI_PAR17,21,22,23,28,29

+3V

+V5S_ICHREF

+3VS

12

12

12

C46
47PF

12

C68
.01UF

C76
47PF

C55

C50

.1UF

.1UF

+V1.8_ICHLAN

C69
.1UF

12

12

C98
.1UF

C99
.1UF

12

+

C75

1UF_10V_0603

12

C57
.1UF

C54
.1UF

12

C65
.1UF

12

C56
47PF

C63
.1UF

1 2

+1.5VS

12

C49
.1UF

12

12

C77

C93

47PF

.1UF

12

12

+

C64

C84

.1UF

1UF_10V_0603

12

12

C87

C94

.1UF

.1UF

12

C102
.1UF

12

C100
.1UF

12

12

C89
47PF

C103
.1UF

E

12

C110
.1UF

12

12

12

C162
47PF

C161
.1UF

C73
.1UF

Compal Electronics, inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1121

Size Document Number Rev
Custom

401191 (FOR ATL02 / ACL00)

Date: Sheet

19 87Thursday, September 13, 2001

E

of

1A

+5VS

IDE,CD-ROM Module CONN.

12

C109

IDE_PDD[0..15]18

IDE_PDDREQ18

IDE_PDIOW#18

IDE_PDIOR#18
IDE_PIORDY18
IDE_PDDACK#18

INT_IRQ1417,19
IDE_PDA118
IDE_PDA018
IDE_PDCS1#18 IDE_PDCS3# 18
PHDD_LED#34

1 2

+5VS

R95 100K

1 2

+5VMOD

R167 100K

CD_RSTDRV#30

+5VS

RP2

DSKCHG#

18

INDEX#

27

WP#

36

TRACK0#

45

8P4R_1K

+5VS

DRV0#

6
7
8
9

10

EXTCSEL

1 2

R253 1K

WDATA#
WGATE#
HDSEL#
FDDIR#

1 2

R166 470

IDE_PDD[0..15]

PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

IDE_PDDREQ

IDE_PIORDY

INT_IRQ14

+5VS

SHDD_LED#

5
4
3
2
1

CDD[0..15]

CD_AGND
CD_RSTDRV#
CDD7
CDD6
CDD5
CDD4
CDD3
CDD2
CDD1
CDD0

CD_SIORDY
CD_IRQ

SHDD_LED#
EXTCSEL

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

STEP#
MTR0#
RDATA#

CDD[0..15]30

INT_CD_L31 INT_CD_R 31
CD_AGND31

CD_SIOW#30

CD_SIORDY30

CD_IRQ30
CD_SBA130
CD_SBA030

CD_SCS1#30

SHDD_LED#34

RDATA#25

WP#25

TRACK0#25

WDATA#25

STEP#25

MTR0#25

DSKCHG#25

DRV0#25,34

RP1

10P8R_1K

1000PF

Place component's closely IDE CONN.

JP7

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

HDD 44P SUYIN 20225A-44G5-A

JP17

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

HEADER 2X30

+3VALW

1 8
2 7
3 6
4 5

+5VS

C518
10UF_16V_1206

RP3

8P4R_100K

+5VMOD

12

C114

1UF_25V_0805

EXTID0
EXTID1
EXTID2

12

C107

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

PCSEL

1 2

R84 470

1 2

R556 @0

+5VS

CD_AGND
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
CD_DREQ

EXTID0
EXTID1
EXTID2
HDSEL#

WGATE#

FDDIR#
3MODE#

INDEX#

12

C186

C183

1000PF

10UF_16V_1206

Place component's closely CD-ROM CONN.

.1UF

+5VMOD

W=80mils

IDE_PDA2 18

CD_DREQ 30
CD_SIOR# 30
CD_DACK# 30
CD_SBA2 30
CD_SCS3# 30
EXTID0 34
EXTID1 34
EXTID2 34
HDSEL# 25

WGATE# 25

FDDIR# 25
3MODE# 25

INDEX# 25

12

C182
1UF_25V_0805

+5VS

12

12

+3VS

+5VMOD

12

C185
.1UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

HDD Manual ATA Ty p e S e le c t i o n:

ATA33 : populate R43, de-populate R46.
ATA66/100 : populate R46, de-populate R43.

R43

@10K

IDE_PATADET 17

R46

10K

R75 10K

1 2

R429 10K

1 2

R88 1K

1 2

R428 1K

1 2

IDE_PDD7

CDD7

IDE_PIORDY

CD_SIORDY

EXTIDEPWR#34

SIDEPWR17

R82 5.6K

1 2

R152 5.6K

1 2

R412 1K

IDE_PDDREQ

CD_DREQ

ICH_IDE_SRST#18

2

G1

PCIRST#8,15,17,19,21,22,23,24,25,28,29,35

ICH_IDE_PRST#18

D1 S1

61

+12VALW

Q41A

SI1906DL

C139

1 2

.1UF

PCIRST#

+5VCD

PCIRST#

+5VS

1
2

R165

100K

2

C140

1 2

.1UF

5

3

Q9

SI3456DV
6
5
2
1

12

47K

+5VS

1
2

U13

7SH08FU

47K

4

5

3

3

Q39

1

DTC144EKA

3

U12

7SH08FU

+5VMOD

4

4

12

+

{1st Part Field}

12

PIDE_RST#

12

C174

4.7UF_16V_1206

C176
.01UF

R161
1K

D2

34

5

Q41B
SI1906DL

S2

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

SIDE_RST# 30

EXTIDE_EN#

G2

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

20 87Thursday, September 13, 2001

1A

of

5

4

3

2

1

LAN_IDSEL

12

R271

100K

D D

Q24

EN_LAN#34

+12VALW

C C

B B

CLK_PCI_LAN

A A

2

R241

1 2

470K

Q23
FDV301

12

R238
@22

12

C324
@10PF

1 3

2

1 3

+3VLAN

12

5

2N7002

LAN_IDSELPCI_AD17

C370

.1UF

SUS_STAT#15,17,25,35

1 2

+3VS

R227 @1K

PIRQB#17,19,23

PCIRST#8,15,17,19,20,22,23,24,25,28,29,35

CBRST#15,22,23,24,28,29

CLK_PCI_LAN12

PCI_REQ#317,19

PCI_C/BE#317,22,23,28,29

PCI_AD[0..31]17,22,23,28,29

PCI_GNT#317,19

+2.5VLAN

LAN_IDSEL

1 2

1 2

CLK_PCI_LAN

PCI_AD31
PCI_AD30

PCI_AD29
PCI_AD28

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

R270 100

1 2

PCI_AD23

PCI_AD[0..31]

PCI_C/BE#217,22,23,28,29

PCI_FRAME#17,19,22,23,28,29

PCI_DEVSEL#17,19,22,23,28,29

PCI_C/BE#117,22,23,28,29

R22
50

PCI_TRDY#17,19,22,23,28,29

PCI_PERR#17,19,22,23,28
PCI_SERR#17,19,22,23,28

R222
@15K

R4850

PCI_IRDY#17,19,22,23,28,29

PCI_STOP#17,19,22,23,28,29

LAN_PME#33

LAN_RD­LAN_RD+

LAN_TD­LAN_TD+

12

ACTIVITY#

LINK10_100#

8079787776757473727170696867666564636261605958575655545352

LED1NCLED2

AVDD25

GND

AD21

AD20

AD19

PCI_AD20

PCI_AD21

PCI_AD19

12

R25
50

PROPRIETARY NOTE

AVDD

VDD

ISOLATEB

VDD25

PCI_AD18

GND

AD18

PCI_AD17

R484@0

PCI_PAR17,19,22,23,28,29

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

12

12

R21
50

12

C12
.1UF

LED0

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

AD22

1234567891011121314151617181920212223242526272829

+2.5VLAN

PCI_AD22

1 2

C11 .1UF

4

*BOM 16.9K_1%

12

GND

TXD-

TXD+

RXIN-

AVDD

RXIN+

RTSET

AVDD25

AD17

AD16

CBE2B

FRAMEB

IRDYB

TRDYB

DEVSELB

GND

PCI_AD16

PCI_C/BE#2

PCI_TRDY#

PCI_IRDY#

PCI_STOP#

PCI_FRAME#

PCI_DEVSEL#

LAN_RD+
LAN_RD-

LAN_TD+
LAN_TD-

12

R24
50

C19
.1UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R217

1.69K_1%

GND

RTT2

RTT3

STOPB

PERRB

SERRB

PCI_PERR#

PCI_SERR#

PCI_PAR

12

X1

PAR

X2

CBE1B

AVDD-1

AVDD-2

AVDD-3

AVDD

AVDD25

VDD

AD15

PCI_AD15

12

PCI_AD14

12

+2.5VLAN

51

NCNCNC

GND

PMEB

VCTRL

AD14

AD13

AD12

AD11

AD10

AD9

30

PCI_AD12

PCI_AD10

PCI_AD11

PCI_AD13

PCI_AD8

PCI_AD9

+3VLAN

C352

.1UF

U23

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7 10

TD+ TX+

Pulse H0013

+3V

C18
.1UF

3

12

C295
.1UF

LAN_X1
LAN_X2

U6

VDD25

50

AUX

49

EECS

48

EESK

47

EEDI

46

EEDO

45

AD0

44

AD1

43

GND

42

AD2

41

AD3

40

VDD25

39

VDD

38

AD4

37

AD5

36

AD6

35

VDD25

34

VDD

33

AD7

32

CBE0B

31

GND

AD8

RTL8100-L

Layout Note
H0013 pls close to
conn.

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

98

TX-TD-

AUX

PCI_AD0
PCI_AD1

PCI_AD2
PCI_AD3

PCI_AD4
PCI_AD5
PCI_AD6

PCI_AD7

R17

75

1 2

L28 4.7UH

1 2

L27 4.7UH

1 2

L25 4.7UH

12

12

C306

C304

.1UF

.1UF

Y2
25 MHz

LAN_X1 LAN_X2

12

C312

LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

+3VLAN

C333

4.7UF_10V_1206

ACTIVITY#

LINK10_100#

18PF

U5

1

CS

VCC

2

SK

3
4

PCI_C/BE#0 17,22,23,28,29

NC

DI

NC

DO

GND

9346

C

10K

2

B

3 1

+3V

10K

2

B

2

+3V

12

R224

5.6K

+2.5VLAN

12

C29
.1UF

RJ45_RX+
RJ45_RX-

RJ45_TX+
RJ45_TX-

12

12

R18
75

LAN_GND

+3V

C288

4.7UF_10V_1206

12

C311
18PF

+3V

8
7
6
5

47K

E

C

47K

E

3 1

+3V

Q20

DTA114YKA

Q21

DTA114YKA

12

RJ45_RX-

RJ45_RX+
RJ45_TX­RJ45_TX+

R186

1 2

510_0603

For 3V LAN only

+3VLAN

12

12

C348

C347

.1UF

+2.5VLAN

12

12

C368
.1UF

JP5

12

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

AMP RJ45/RJ11 with LED

C248

1000P_2KV_1206

1000PF

C351
1000PF

C21
.1UF

R187
510_0603

1 2

12

R184

75

12

R185
75

LAN_GND

Termination plane should be copled to chassis ground

R52

1 2

0_1206

12

C367
.1UF

12

C371
.1UF

SHLD4
SHLD3

SHLD2
SHLD1

LANGND
12

C249

.1UF

+3V+3VLAN

12

12

C369

1000PF

12

12

C329

1000PF

16
15

14
13

12

C257

4.7UF_10V_0805

C332
.1UF

C349
.1UF

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

21 87Thursday, September 13, 2001

1

1A

of

A

PCI_AD[0..31]17,21,23,28,29

PCI_AD[0..31]

B

8P4R_4.7K

1 8
2 7
3 6
4 5

+3V

RP31

C

+3V

D

+3V

12

C614

.01UF

12

C640

.01UF

12

C649

.01UF

12

C645

.01UF

E

12

12

C642

C631

.1UF

.01UF

12

C651
.1UF

12

C632
.1UF

12

C609
.1UF

1 1

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11

2 2

PCI_AD16

1 2

R475 100

3 3

1394_IDSEL

PCI_C/BE#317,21,23,28,29
PCI_C/BE#217,21,23,28,29
PCI_C/BE#117,21,23,28,29
PCI_C/BE#017,21,23,28,29

CLK_PCI_139412

PCI_GNT#017,19

PCI_REQ#017,19

PCI_FRAME#17,19,21,23,28,29

PCI_TRDY#17,19,21,23,28,29

PCI_DEVSEL#17,19,21,23,28,29

PCI_PERR#17,19,21,23,28

PCI_SERR#17,19,21,23,28

PM_CLKRUN#17,19,23,25,28,29,33

PCI_IRDY#17,19,21,23,28,29

PCI_STOP#17,19,21,23,28,29

PIRQA#15,17,19,23

1394_PME#33

PCI_PAR17,19,21,23,28,29
PCIRST#8,15,17,19,20,21,23,24,25,28,29,35

CBRST#15,21,23,24,28,29

PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1

PCI_AD0
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394

1394_IDSEL

1394_PME#
PCI_SERR#
PCI_PAR

PCIRST#

R411
220

1 2

U48

TSB43AB22

22

PCI_AD31

24

PCI_AD30

25

PCI_AD29

26

PCI_AD28

28

PCI_AD27

29

PCI_AD26

31

PCI_AD25

32

PCI_AD24

37

PCI_AD23

38

PCI_AD22

40

PCI_AD21

41

PCI_AD20

42

PCI_AD19

43

PCI_AD18

45

PCI_AD17

46

PCI_AD16

61

PCI_AD15

63

PCI_AD14

65

PCI_AD13

66

PCI_AD12

67

PCI_AD11

69

PCI_AD10

70

PCI_AD9

71

PCI_AD8

74

PCI_AD7

76

PCI_AD6

77

PCI_AD5

79

PCI_AD4

80

PCI_AD3

81

PCI_AD2

82

PCI_AD1

84

PCI_AD0

34

PCI_C/BE3

47

PCI_C/BE2

60

PCI_C/BE1

73

PCI_C/BE0

16

PCI_CLK

18

PCI_GNT

19

PCI_REQ

36

PCI_IDSEL

49

PCI_FRAME

50

PCI_IRDY

52

PCI_TRDY

53

PCI_DEVSEL

54

PCI_STOP

56

PCI_PERR

13

PCI_INTA

21

PCI_PME

57

PCI_SERR

58

PCI_PAR

12

PCI_CLKRUN

85

PCI_RST

14

G_RST

89

GPIO3

90

GPIO2

PLLGND1

R410

220

1 2

8

2035486278

PCI BUS INTERFACE

AGND

AGND

AGND

AGND

AGND

PLLGND2

109

110

111

117

126

127

9

VDDP

VDDP

VDDP

VDDP

VDDP

TSB43AB22

PHY PORT 2

BIAS CURRENT

OSCILLATOR

FILTER

EEPROM 2 WIRE BUS

POWER CLASS

PHY PORT 1

AGND

DGND

DGND

AGND

DGND

DGND

DGND

DGND

445564

128

172330

33

87

CYCLEIN

DGND

68

DGND

DGND

758393

CYCLEOUT

DGND

DGND

96

TEST7

DGND

103

101186

TEST17

DVDD
DVDD

TEST16

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD

PLLVDD

AVDD
AVDD
AVDD
AVDD
AVDD

TPBIAS1

TPA1+

TPA1-

TPB1+

TPB1-

FILTER0
FILTER1

TPBIAS0

TPA0+

TPA0-

TPB0 +

TPB0 -

TEST9
TEST8

TEST3
TEST2
TEST1
TEST0

CPS

SDA

SCL
PC0

PC1
PC2

15
27
39
51
59
72
88
100
7
1
2
107
108
120

106

R434 1K

125
124

R459 1K

123
122
121

R458 1K

118

R0

R453

6.34K_1%

119

R1

6

X0

5

X1

3

C650 .1UF

4
92

R424 220

91

R425 220
99
98
97

116
115
114
113
112

94
95

101
102
104
105

+3V

+3V

1 2

1 2

C646 .1UF

1 2
1 2

1 2

1 2
1 2

TPBIAS0

R423 220

1 2

R422 220

1 2

R437 220

1 2

R439 220

1 2

R441 220

1 2

R442 220

1 2

PLLVDD

Y4

24.576MHz

12

C652

.01UF

C656

1 2

15PF

C655

1 2

15PF

R394 56.2_1%

R399

56.2_1%

R400

56.2_1%

R395

56.2_1%

L45

1 2

0_0805

12

C653

4.7UF_10V_0805

TPA0+
TPA0­TPB0+
TPB0-

C585 220PF

+3V

R387

5.11K_1%

TPB0­TPB0+
TPA0-

12

C590
.33UF

TPA0+

JP12
1

1

2

2

3

3

4

4

Molex SD-54030-0411

CLK_PCI_1394

4 4

12

R462

@22

1 2

C657

@.1UF

1 2

C605

@.1UF

TSB43AB22 USE

C654

@10PF

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For TSB43AA22

C657,C605

change to 0

ohm to short

to GND

C

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

D

Date: Sheet

22 87Thursday, September 13, 2001

E

1A

of

A

RTCCLK15,17,24,29

PCI_GNT#217,19

PCI_REQ#217,19
PCI_C/BE#317,21,22,28,29
PCI_C/BE#217,21,22,28,29
PCI_C/BE#117,21,22,28,29
PCI_C/BE#017,21,22,28,29

CLK_PCI_CB12
PCI_FRAME#17,19,21,22,28,29

PCI_DEVSEL#17,19,21,22,28,29

PCIRST#8,15,17,19,20,21,22,24,25,28,29,35

PCI_TRDY#17,19,21,22,28,29

PCI_IRDY#17,19,21,22,28,29
PCI_STOP#17,19,21,22,28,29

PCI_PERR#17,19,21,22,28

PCI_PAR17,19,21,22,28,29

W10

B_D0/CAD27

U10

B_D1/CAD29

P10

B_D2/RSVD

H2

B_D3/CAD0

J1

B_D4/CAD1

J3

B_D5/CAD3

K1

B_D6/CAD5

K3

B_D7/CAD7

V10

B_D8/CAD28

R10

B_D9/CAD30

W11

B_D10/CAD31

H1

B_D11/CAD2

J2

B_D12/CAD4

J6

B_D13/CAD6

K2

B_D14/RSVD

K5

B_D15/CAD8

R8

B_A0/CAD26

W7

B_A1/CAD25

V7

B_A2/CAD24

W6

B_A3/CAD23

V6

B_A4/CAD22

U6

B_A5/CAD21

V5

B_A6/CAD20

U5

B_A7/CAD18

N1

B_A8/CC/BE1#

M3

B_A9/CAD14

L1

B_A10/CAD9

M1

B_A11/CAD12

T1

B_A12/CC/BE2#

N3

B_A13/CPAR

P1

B_A14/CPERR#

P5

B_A15/CIRDY#

P6

B_A16/CCLK

M6

B_A17/CAD16

N2

B_A18/RSVD

N6

B_A19/CBLOCK#

N5

B_A20/CSTOP#

R1

B_A21/CDEVSEL#

R2

B_A22/CTRDY#

R3

B_A23/CFRAME#

W4

B_A24/CAD17

R6

B_A25/CAD19

V9

B_BVD1/CSTSCHG

W9 J15

B_BVD2/CAUDIO A_BVD2/CAUDIO

H3

B_CD1#/CCD1#

R9

B_CD2#/CCD2#

V8

B_READY/CINT#

W8

B_WAIT#/CSERR#

U9

B_WP/CCLKRUN#

R7

B_INPACK/CREQ#

K6

B_CE1#/CC/BE0#

L2

B_CE2#/CAD10

P3

B_WE#/CGNT#

L5

B_IORD#/CAD13

M2

B_IOWR#/CAD15

L6

B_OE#/CAD11

U8

B_VS1#/CVS1

P7

B_VS2#/CVS2

P8

B_REG#/CC/BE3#

W5

B_RESET/CRST#

PCI_AD[0..31]

PCI_SERR#17,19,21,22,28

1 2

R478

1 2

100K

22K

2

13

Q60 2N7002

S1_D[0..15]

S1_A[0..25]
S2_D[0..15]

S2_A[0..25]

S2_A16 SB_A16 SA_A16 S1_A16

1 2

Placement near
to PCMCIA
controller

S2_BVD124
S2_BVD224
S2_CD1#24
S2_CD2#24
S2_RDY#24
S2_WAIT#24

S2_WP24

S2_INPACK#24

S2_CE1#24
S2_CE2#24
S2_WE#24

S2_IORD#24

S2_IOWR#24

S2_OE#24
S2_VS124

S2_VS224
S2_REG#24
S2_RST24

S2_VCC
S2_VCC

A

S2_D0 S1_D0
S2_D1 S1_D1
S2_D2 S1_D2
S2_D3 S1_D3
S2_D4 S1_D4
S2_D5 S1_D5
S2_D6 S1_D6
S2_D7 S1_D7
S2_D8 S1_D8
S2_D9 S1_D9
S2_D10 S1_D10
S2_D11 S1_D11
S2_D12 S1_D12
S2_D13 S1_D13
S2_D14 S1_D14
S2_D15 S1_D15

S2_A0 S1_A0
S2_A1 S1_A1
S2_A2 S1_A2
S2_A3 S1_A3
S2_A4 S1_A4
S2_A5 S1_A5
S2_A6 S1_A6
S2_A7 S1_A7
S2_A8 S1_A8
S2_A9 S1_A9
S2_A10 S1_A10
S2_A11 S1_A11
S2_A12 S1_A12
S2_A13 S1_A13
S2_A14 S1_A14
S2_A15 S1_A15

R463

S2_A17 S1_A17
S2_A18 S1_A18

47

S2_A19 S1_A19
S2_A20 S1_A20
S2_A21 S1_A21
S2_A22 S1_A22
S2_A23 S1_A23
S2_A24 S1_A24
S2_A25 S1_A25

S2_BVD1 S1_BVD1
S2_BVD2 S1_BVD2
S2_CD1# S1_CD1#
S2_CD2# S1_CD2#
S2_RDY# S1_RDY#
S2_WAIT# S1_WAIT#
S2_WP S1_WP
S2_INPACK# S1_INPACK#

S2_VS2
S2_RST

PCI_AD[0..31]17,21,22,28,29

1 1

2 2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

S2_WP

S2_A23

S1_D[0..15]24
S1_A[0..25]24

+12VS

S2_D[0..15]24
S2_A[0..25]24

R435 22K

R177

B

SLATCH24
SLDATA24

12

R473

33

12

C695
10PF

C6B6A6F7A7B7A14C7F8

PAR

IRDY#

STOP#

TRDY#

SERR#

PERR#

RSTIN#

DEVSEL#

FRAME#

A10E2A5C8A15

PCLK

B13

C13

GNT#

REQ#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

PCI

Interface

Slot

B

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD4

AD10

AD9

AD8

AD7

AD6

AD5

AD3

AD2

AD1

AD0

F2

G5

H6G3G1

H5

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD6

PCI_AD1

PCI_AD2

PCI_AD0

PCI_AD7

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD8

B

AD17

AD15

AD14

AD13

AD12

AD11

PCI_AD12

AD18

AD16

A12

B11

C11

E13

F11

E10

F10A9B9F9A8F1F6B5E6A4C12E3F5G6E1

E9

B8

PCI_AD29

PCI_AD28

PCI_AD27

PCI_AD25

PCI_AD16

PCI_AD18

PCI_AD13

PCI_AD17

PCI_AD14

PCI_AD20

PCI_AD15

PCI_AD19

PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

F14

B12

E19

DATA

AD29

E12

PCI_AD30

CLOCK

AD30

G15

F17

LATCH

AD31

A13

PCI_AD31

C

+3V

F18

VCCI

SPKOUT

IRQ/DMA

IDSEL

F15

C10

12

R474
100

PCI_AD20

C

PCM_SPK# 32

12

L3

E11

D1

F3

VCC

VCCP

VCCP

Power

IRQSER/MFUNC3

INTA#/MFUNC0

INTB#/MFUNC1

SUSPEND#

DMAREQ#/MFUNC2

E14

C15

E17

D19

A16

PCM_INTB#

PCM_INTA#

C667
.1UF

W12

U7

VCC

VCC

VCC

Slot

A

DMAGNT#/MFUNC5

LOCK#/MFUNC4

CLKRUN#/MFUNC6

F13

B15

N15

G19

VCC

C14

+3V

VCC

RIOUT#/PME#

12

B14

VCC

+3V

C668
.1UF

C9

E7

M5

VCC

VCC

GND

GND

GND

J5

P2

G2

PCM_PME#
PCM1_LED

PCM2_LED

VCCB

GND

P9

GND

M17

VCCA

GND

V14

K18

1 2

C664 .1UF

1 2

C681 .1UF

CBRST#

A11

A_D0/CAD27

GRST#

A_D1/CAD29

A_D2/RSVD
A_D3/CAD0

A_D4/CAD1
A_D5/CAD3
A_D6/CAD5

A_D7/CAD7
A_D8/CAD28
A_D9/CAD30

A_D10/CAD31

A_D11/CAD2
A_D12/CAD4
A_D13/CAD6
A_D14/RSVD
A_D15/CAD8

A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18

A_A8/CC/BE1#

A_A9/CAD14
A_A10/CAD9

A_A11/CAD12

A_A12/CC/BE2#

A_A13/CPAR

A_A14/CPERR#

A_A15/CIRDY#

A_A16/CCLK

A_A17/CAD16

A_A18/RSVD

A_A19/CBLOCK#

A_A20/CSTOP#

A_A21/CDEVSEL#

A_A22/TRDY#

A_A23/CFRAME#

A_A24/CAD17
A_A25/CAD19

A_BVD1/CSTSCHG

A_CD1#/CCD1#

A_CD2#/CCD2#

A_READY/CINT#
A_WAIT#/CSERR#
A_WP/CCLKRUN#
A_INPACK/CREQ#

A_CE1#/CC/BE0#

A_CE2#/CAD10

A_WE#/CGNT#

A_IORD#/CAD13

A_IOWR#/CAD15

A_OE#/CAD11

A_VS1#/CVS1
A_VS2#/CVS2

A_REG#/CC/BE3#

A_RESET/CRST#

GND

GND

GND

GND

GND

GND

E18

F12

B10

E8

C5

PCM_PME# 33
PM_CLKRUN# 17,19,22,25,28,29,33
PCM1_LED 34
PCM_RI# 29
INT_SERIRQ 17,19,25,33
PCM2_LED 34

R307 22K

2 1

D27

D

CBRST# 15,21,22,24,28,29

U51

H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13

J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18

H19
V11

H17
J17
J14
H18
L14

P13
R13
R19
W15
V15
U14

S1_VS1S2_VS1

J18

S1_VS2

M19
K17

S1_RST

L18

PCI1420-GHK

+3V

PCM_SUSP# 33

RB751V

D

S2_VCC
S1_VCC

E

CARDBUS
PCI1420

+3V

12

C691
.1UF

+3V

12

C687
1000PF

R466

1 2

47

Placement near
to PCMCIA
controller

S1_BVD1 24
S1_BVD2 24
S1_CD1# 24
S1_CD2# 24
S1_RDY# 24
S1_WAIT# 24
S1_WP 24
S1_INPACK# 24

S1_CE1# 24
S1_CE2# 24
S1_WE# 24
S1_IORD# 24
S1_IOWR# 24
S1_OE# 24
S1_VS1 24
S1_VS2 24
S1_REG# 24
S1_RST 24

PCM_INTA#

PCM_INTB#

R477
22K

12

C693
.1UF

12

C688
1000PF

S1_A23
S1_WP

+3V

12

+3V

12

R468 22K

1 2

R470

+3V

R472
22K

D41

21
RB751V
D40

21
RB751V

C669
.1UF

C692
1000PF

22K

PIRQA# 15,17,19,22

PIRQB# 17,19,21

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

E

S1_VCC
S1_VCC

23 87Thursday, September 13, 2001

12

C666
.1UF

12

C690
1000PF

1A

of

PCMCIA POWER CTRL.

1 2
1 2
1 2
1 2
1 2
1 2
1 2

S1_A[0..25]23

S1_D[0..15]23
S2_A[0..25]23

S2_D[0..15]23

S2_VPP

S1_VPP

C671
10UF_16V_1206

C678
10UF_16V_1206

C231
1UF_25V_0805

C226
.1UF
C225

.1UF

C227

.1UF

C660

.1UF

C638

.1UF

C641

.1UF

OCCB#34

+3V

12

12

1 2

R455
100K

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

W=30mils

C233

.01UF

W=30mils

C229

.01UF

12
C234

12
C663

56PF

56PF

12

RTCCLK15,17,23,29

C673

SLDATA23
SLATCH23

12

12

.1UF

C661

.1UF

+5V_CBS

+3V

12

C659

1UF_25V_0805

C228
1UF_25V_0805

S1_VCC

12

C662

1000PF

S2_VCC

12

C674

1000PF

+12V

U19

25

VCC_5V

7

12V

24

12V

1

5V

2

5V

30

5V

15

3.3V

16

3.3V

17

3.3V

3

DATA

5

LATCH

4

CLOCK

13

APWR_GOOD#

19

BPWR_GOOD#

18 12

OC# GND

TPS2206AI/TPS2216

1UF_10V_0603

C718

S1_VPP

8

AVPP

9

AVCC

10

AVCC

11

RESET#

12

AVCC
BVPP

BVCC
BVCC
BVCC

RESET

NC
NC
NC
NC

PCIRST#8,15,17,19,20,21,22,23,25,28,29,35

G_RST#33

S2_VPP

23
20
21
22

6
14

26
27
28
29

+5V +5V_CBS

R533 10K

1 2
1 2

R534

10K

W=40mils

12

C240

4.7UF_10V_0805

W=40mils

12

C237

4.7UF_10V_0805

CBRST#

12

C116
.1UF

14

2 3
7

1
2
3 6
4

1
2
3 6
4

S1_VPP
S1_VCC

S2_VPP
S2_VCC

+3V

U37A

1

74LVC125

+3V POWER

JP29

1 2

PAD-OPEN 4x4m

U58

IN
IN
RST# SET
SHDN#

MAX1857

U59

IN
IN
RST# SET
SHDN#

MAX1857

1 2

R348 0

1 2

R349 @0

80 mils80 mils

8

OUT

7

OUT

5

GND

8

OUT

7

OUT

5

GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

PCMRST# 34

CBRST#

12

+3V

4.926V

R531
100K_1%

1 2

1.25V

R532
34K_1%_0603

1 2

R354

10K

CBRST# 15,21,22,23,28,29

12

C719

2.2UF_0805

S1_CD1#

@1000PF

S1_CD2#

@1000PF

S2_CD1#

@1000PF

S2_CD2#

@1000PF

CARDBUS

SOCKET

JP19

A77

a68

A76

S1_CD2#23

S1_WP23

S1_BVD123

S1_BVD223

S1_REG#23

S1_INPACK#23

S1_WAIT#23

S1_RST23
S1_VS223

S1_VPP S2_VPP
S1_VCC

S1_RDY#23

S1_WE#23

S1_IOWR#23

S1_IORD#23

S1_VS123
S1_OE#23

S1_CE2#23

S1_CE1#23

S1_CD1#23

C670

1 2

C686

1 2

C689

1 2

C665

1 2

S1_CD2#
S1_WP

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

S1_A16

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13

S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#

S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10

S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6

S1_D12 S2_D12
S1_D5
S1_D11
S1_D4

S1_CD1#

S1_D3

a34

A75

a67

A74

a33

A73

GND

A72

a66

A71

a32

A70

a65

A69

a31

A68

a64

A67

a30

A66

a63

A65

GND

A64

a29

A63

a62

A62

a28

A61

a61

A60

a27

A59

a60

A58

a26

A57

GND

A56

a59

A55

a25

A54

a58

A53

a24

A52

a57

A51

a23

A50

a56

A49

GND

A48

a22

A47

a55

A46

a21

A45

a54

A44

a20

A43

a53

A42

GND

A41

a19

A40

a52

A39

a18

A38

a51

A37

a17

A36

a50

A35

a16

A34

a49

A33

a15

A32

a48

A31

a14

A30

a47

A29

a13

A28

GND

A27

a46

A26

a12

A25

a45

A24

a11

A23

a44

A22

GND

A21

a10

A20

a43

A19

a9

A18

a42

A17

a8

A16

GND

A15

a41

A14

a7

A13

a40

A12

a6

A11

a39

A10

a5

A9

GND

A8

a38

A7

a4

A6

a37

A5

a3

A4

a36

A3

a2

A2

a35

A1

a1

PCMC154PIN

Title

Size Document Number Rev

B

Date: Sheet

B77

b68

B76

b34

B75

b67

B74

b33

B73

GND

B72

b66

B71

b32

B70

b65

B69

b31

B68

b64

B67

b30

B66

b63

B65

GND

B64

b29

B63

b62

B62

b28

B61

b61

B60

b27

B59

b60

B58

b26

B57

GND

B56

b59

B55

b25

B54

b58

B53

b24

B52

b57

B51

b23

B50

b56

B49

GND

B48

b22

B47

b55

B46

b21

B45

b54

B44

b20

B43

b53

B42

GND

B41

b19

B40

b52

B39

b18

B38

b51

B37

b17

B36

b50

B35

b16

B34

b49

B33

b15

B32

b48

B31

b14

B30

b47

B29

b13

B28

GND

B27

b46

B26

b12

B25

b45

B24

b11

B23

b44

B22

GND

B21

b10

B20

b43

B19

b9

B18

b42

B17

b8

B16

GND

B15

b41

B14

b7

B13

b40

B12

b6

B11

b39

B10

b5

B9

GND

B8

b38

B7

b4

B6

b37

B5

b3

B4

b36

B3

b2

B2

b35

B1

b1

Compal Electronics, inc.

SCHEMATIC, M/B LA-1121
401191 (FOR ATL02 / ACL00)

S2_CD2#
S2_WP

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3

S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22

S2_A16

S2_A21
S2_RDY#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

S2_A17
S2_A8
S2_IOWR#
S2_A9
S2_IORD#

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10

S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6

S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

S2_CD2# 23
S2_WP 23

S2_BVD1 23

S2_BVD2 23
S2_REG# 23

S2_INPACK# 23

S2_WAIT# 23
S2_RST 23
S2_VS2 23

S2_VCC

S2_RDY# 23
S2_WE# 23

S2_IOWR# 23
S2_IORD# 23

S2_VS1 23
S2_OE# 23
S2_CE2# 23

S2_CE1# 23

S2_CD1# 23

24 87Thursday, September 13, 2001

1A

of

A

SUPER I/O SMsC FDC47N227

1 1

B

C

C713

1 2

PCIRST#8,15,17,19,20,21,22,23,24,28,29,35

LPCRST

1 2

R524
10K

+3V

.1UF

12

C714
.1UF

D

U55

5 6

VCC Y1

1

A1

3

A2

GND

NC7WZ14

E

21

1 2

R518 10K

LPC_RST#

LPCRST

4

Y2

2

D45

RB751V

+3VS

LPC_RST# 33

1 2

1 2

R228

@33

C307

@22PF

LPC_AD[0..3]

LPC_FRAME#17,33

LPC_DRQ#117,19

SUS_STAT#15,17,21,35

INT_SERIRQ17,19,23,33
PM_CLKRUN#17,19,22,23,28,29,33
CLK_LPC_SIO12

CLK_SIO1412

BT_DET#27

1 2

R195 10K

1 2

R196 10K

+3VS

+3VS

PID015
PID115
PID215
PID315

+3VS

C278

4.7UF_10V_0805
10V

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1 2

R209 10K

CLK_LPC_SIO

CLK_SIO14

1 2

R520 10K

12

C294
.1UF

LPC_RST#

R248 10K

12

C338
.1UF

1 2

12

C276
.1UF

U29

20

LAD0

21

LAD1

22

LAD2

23

LAD3

24

LFRAME#

25

LDRQ#

26

PCIRST#

27

LPCPD#

50

GPIO12/IO_SMI#

17

IO_PME#

30

SIRQ

28

CLKRUN#

29

PCICLK

19

CLK14

48

GPIO10

54

GPIO15

55

GPIO16

56

GPIO17

57

GPIO20

58

GPIO21

59

GPIO22

6

GPIO24

32

GPIO30

33

GPIO31

34

GPIO32

35

GPIO33

36

GPIO34

37

GPIO35

38

GPIO36

39

GPIO37

40

GPIO40

41

GPIO41

42

GPIO42

43

GPIO43

44

GPIO44

45

GPIO45

46

GPIO46

47

GPIO47

51

GPIO13/IRQIN1

52

GPIO14/IRQIN2

64

GPIO23/FDC_PP

18

VTR

53

VCC

65

VCC

93

VCC

7

VSS

31

VSS

60

VSS

76

VSS

SMsC LPC47N227

PD0/INDEX#

PD1/TRK0

PD2/WRTPRT#

PD3/RDATA#

PD4/DSKCHG#

PD6/MTR0#

BUSY/MTR1#

PE/WDATA#

SLCT/WGATE#

ERROR#/HDSEL#

ACK#/DS1#

INIT#/DIR#

AUTOFD#/DRVDEN0#

STROBE#/DS0#
SLCTIN#/STEP#

DTR2#

CTS2#
RTS2#

DSR2#

TXD2
RXD2

DCD2#

DTR1#

CTS1#
RTS1#

DSR1#

TXD1
RXD1

DCD1#

IRMODE/IRRX3

IRRX2

IRTX2

RDATA#
WDATA#

WGATE#

HDSEL#

STEP#

DS0#

INDEX#
DSKCHG#
WRTPRT#

TRK0#

MTR0#

DRVDEN0
DRVDEN1

GPIO11/SYSOPT

PD5
PD7

RI2#

RI1#

DIR#

LPD0

68

LPD1

69

LPD2

70

LPD3

71

LPD4

72

LPD5

73

LPD6

74

LPD7

75

LPTBUSY

79

LPTPE

78

LPTSLCT

77

LPTERR#

81

LPTACK#

80
66
82
83
67

100

CTS#2

99
98

DSR#2

97
96
95

DCD#2

94

RI#2

92

DTR#1

89

CTS#1

88

RTS#1

87

DSR#1

86

TXD1

85

RXD1

84

DCD#1

91

RI#1

90
63

61
62

16
10
11
12
8
9
5
13
4
15
14
3
1

2
49

Base I/O Address

0 = 02Eh

*

1 = 04Eh

R223 1K

R213 1K

RDATA#
WDATA#
WGATE#

HDSEL#

FDDIR#

STEP#

DRV0#

INDEX#

DSKCHG#

WP#

TRACK0#

MTR0#

LPTBUSY 26
LPTPE 26
LPTSLCT 26
LPTERR# 26
LPTACK# 26
INIT# 26
LPTAFD# 26
LPTSTB# 26
SLCTIN# 26

1 2

1 2

R247 10K

1 2

R208 1K

IRMODE 26
IRRX 26
IRTXOUT 26

RDATA# 20
WDATA# 20
WGATE# 20
HDSEL# 20
FDDIR# 20
STEP# 20
DRV0# 20,34
INDEX# 20
DSKCHG# 20
WP# 20
TRACK0# 20
MTR0# 20
3MODE# 20

12

+5VS

LPD[0..7]

DCD#1
RI#1
CTS#1
DSR#1

LPD[0..7] 26

1 8
2 7
3 6
4 5

RP10

8P4R_4.7K

+3VS

CTS#2
DSR#2
DCD#2
RI#2

+5V

RXD129

TXD129

DSR#129

RTS#129
CTS#129

DTR#129

RI#129

DCD#129

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1 8
2 7
3 6
4 5

RP11

8P4R_4.7K

JP24

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

+3VS

LPC_AD[0..3]17,33

2 2

3 3

CLK_SIO14

CLK_LPC_SIO

R249

10

1 2

C339

15PF

1 2

4 4

Compal Electronics, inc.

Title

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

25 87Thursday, September 13, 2001

E

of

1A

C7

68UF_4V_B2

+3VS

+

FIR Module

12

IRMODE25

W=40mils

12

C1
.47UF

1 2

R4 10K

1 2

R3 10K

IRMODE

The component's most place
cloely IRDA MODULE.

1

4
5
3

U1

VCC

MODE0
MODE1
FIR_SEL

HSDL-3600

LEDA

AGNDGND

TXD

RXD

+3VS

12

12

R2

R5

4.7_1206

4.7_1206

FIR_VCC

10
27
9
8
6

N.C

W=40mils

IRTXOUT
IRRX

1/4W

12

R561
@ 10K

(R561 For VCH ONLY)

IRTXOUT 25
IRRX 25

12

+

C259
68UF_4V_B2

+5V_PRN

109876

12345

+5V_PRN

109876

12345

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

RP7
10P8R_2.7K

+5V_PRN

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

FD4
FD5
FD6
FD7

RP8
10P8R_2.7K

+5V_PRN

FD3
FD2
FD1
FD0

PARALLEL PORT

+5V_PRN

D4

2 1

+5VS

LPTSTB#25

R189
33

R188
33

LPD[0..7]

LPTINIT#

LPTSLCTIN#

RP6

1 8
2 7
3 6
4 5

8P4R_68

RP5
1 8
2 7
3 6
4 5

8P4R_68

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

INIT#25

SLCTIN#25

LPD[0..7]25

1 2

1 2

LPD0 FD0
LPD1 FD1
LPD2 FD2
LPD3 FD3

LPD7 FD7
LPD6 FD6
LPD5 FD5
LPD4 FD4

LPTAFD#25

LPTERR#25

LPTACK#25

LPTBUSY25

LPTPE25

LPTSLCT25

LPTSTB#
AFD#/3M#

FD0
LPTERR#

LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

RB420D

R191

R190

R192

2.2K

C251
220PF

33

1

33

14

2

15

3

16

4

17

5

18

6

19

7

20

8

JP4

21

9

LPTCN-25

22
10
23
11
24
12
25
13

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

401191 (FOR ATL02 / ACL00)

Date: Sheet

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

FD0
FD1
FD2
FD3FD1

FD4
FD5
FD6
FD7

CP2
1 8
2 7
3 6
4 5

8P4C_220PF

CP1
4 5
3 6
2 7
1 8

8P4C_220PF

CP3
1 8
2 7
3 6
4 5

8P4C_220PF

CP4
1 8
2 7
3 6
4 5

8P4C_220PF

26 87Thursday, September 13, 2001

of

1A

USB PORT

+5VS

USB_OC#018

F4

POLYSWITCH_0.75A

12

C560

1000PF

USB_VCCA

12

12

R353
470K

R355
560K

12

C208
.1UF
USB_AGND

C153

150UF_E

+

+5VS

USB_OC#318

F3

POLYSWITCH_0.75A

USB_VCCC

12

12

R194
470K

C279

1000PF

12

R197
560K

12

C263
.1UF

USB_CGND

C267

150UF_E

+

Bluetooth

RFOFF#34,35

L36

+3VALW+5VALW

1 2
1 2

3
1

12

C201

+

4.7UF_10V_1206

0_0603

L34
0_0603

12

C172
.1UF

BT_VCC

12

12

C721

C720

47PF

47PF

CHB4516G750_1806

BT_DETACH34

BT_WAKE_UP34

BT_RESET#34

12

L35

4516

USB_PP218 BT_DET# 25
USB_PN218

BT_VCC

12

USB2_D+
USB2_D-

USB_PN018

USB_PP018

R163
100K

1 2

13

22K

2

Q40

22K

DTC124EK

USB0_D­USB0_D+

2

Q10

12

SI2301DS

C171
.1UF

JP9

1
2
3
4

SUYIN USB Connector 2569A-04G3T-B

C535

.1UF

12

R171
100K

JP15

12
34
56
78
910

121411
13
15 16

12

C198
.1UF

171918

20

@ HRS DF15-08-20DS-065V

+5VS

USB_OC#118

USB_PN318

USB_PP318

F2

POLYSWITCH_0.75A

12

USB_PN118

USB_PP118

C273

1000PF

USB_VCCB

12

12

USB3_D­USB3_D+

R203
470K

R204
560K

USB1_D­USB1_D+

L19
0_0603

1 2
1 2

L18
0_0603

L13

CHB4516G750_1806

4516

12

C272

C281

150UF_E

.1UF

USB_BGND

L16
0_0603

1 2
1 2

L15
0_0603

L14

CHB4516G750_1806

4516

12

12

C271
.1UF

+

12

12

C725

C275
.1UF

C724
47PF

47PF

12

12

12

12

C723

C722

47PF

47PF

JP1

1
2
3
4
5
6
7
8

SUYIN 2553A-0BG5T-A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, inc.

Title

SCHEMATIC, M/B LA-1121

Size Document Number Rev

B

401191 (FOR ATL02 / ACL00)

Date: Sheet

27 87Thursday, September 13, 2001

of

1A