Compal LA-1044 Schematics

A

B

C

D

E

Cover Sheet

1 1

2 2

888Z3 LA-1044 REV2.0 SCHEMATIC DOCUMENT

Intel (Tualatin) with VIA(VT8606-TwisterT + VT8231)

3 3

BOM &'
LN_ SKU W/SS ()

L@ SKU WO/SS ()
%394@ SKU W/%394 ()
TV@ SKU W/TVOUT ()

4 4

DJ@ SKU W/AUDIO DJ ()
DJN_ SKU WO/AUDIO DJ ()
EQ@ SKU W/EQ ()
EQN_ SKU WO/EQ ()
F@ SKU W/FPR ()
FN_ SKU WO/FPR ()
SPR@ SKU W/DOCKING CONN. ()

A

!"#$:
JOPEN%

JOPEN8
JOPEN9
JOPEN%0

PCB Layer
Structure:

TOP
GND%
IN%
GND2
VCC
IN2
GND3
BOT

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-1044

Size Document Number Rev

B

401196

*+,

-.

,

Date: Sheet

17, 2002

E

144

of

2A

A

Compal confidential

B

C

D

E

Block Diagram

Model Name : 888Z3/LA-1044 (Intel Tualatin)

Intel

Tualatin Micro-FCPGA

1 1

SpeedStep
Logic

page 6

VID
SELECT

page 7

CRT Connector

page 14

Power On/Off
Reset Circuit

page 32

DC/DC Interface
RTC Battery

page 33

2 2

Mini PCI

PCMCIA

Socket

page 36 page 16

TFT/HPA Panel
Interface

page 15

TV/Out
Connector

page 14

VIA VT6306

1394 ControllerENE CB1410

page 18

TV Encoder

CH7005

page 14

AC97
Codec

page 3,4,5

VIA North Bridge

Twister-T

page 8,9,10

MD(0..63)

AD(0..31)

AC Link

VIA South Bridge

page 24

DCLKWR

MA(0..13)

SO-DIMM 0
(Bank 0,1)

VT8231

page 19,20,21

page 12

PCI BUS

CLK_SDRAM0,1

SO-DIMM 1
(Bank 2,3)

Clock Generator

DCLKO

CLK_SDRAM1,2

page 13

CLK_48MHZ
14M_3V

Y1

14.318MHZ

CY28317-2

page 11

+3VSUS
+3VRUN

PCLK_PIIX4

14M_3V
14M_5V

PCLK_DOCK

PCLK_PCM

FingerPR

USB

Port 3

page 36

USB
HUB

page 37

PCB1

LA-1044 PCB

Slot 0

page 17

Speaker

page 26

14M_5V

I/O Buffer

B

page 33

page 32

BIOS

page 32

Audio
EQ

page 25

LPC BUS

KeyBoard

NS87591

page 31

KBDTouch Pad

page 32

AMP
Jack

page 26

IDE Damping
Resistor

page 22

HDD
Connector

page 22

CD Player
OZ163

page 23

CD-ROM
Connector

page 22

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

* HSP Modem Card
* Combo for HSP Modem and

802.11b
* Controllerless Modem
* Combo for Controllerless

3 3

Modem and 802.11b

RJ45/RJ11
Jack

page 30

LAN

RTL8100

page 29

Power Circuit
DC/DC

page 37,38,39,40

4 4

A

D

Port 0,1

page 28

PIO

page 28

FIR

page 27

USB

USB

Port 2

page 27

USB

Port 3

Bluetooth

page 37

Docking Connector

* DC-IN
* 2 USB Port
* TV Out (S Video)
* VGA Out
* 2 PS/2
* LAN
* Parallel Port
* Serial Port
* Line Out
* Headphone
* Microphone

page 35

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

E

244

of

2A

A

B

C

D

E

Tualatin/Celeron-T CPU

+CPU_CORE

1 1

D22

F22

E21

H22

G21

K22

J21

M22

L21

P22

N21

T22

R21

V22

U21

Y22

W21

AB22

AA21

AC21

D20

F20

E19

AB20

AA19

AC19

D18

F18

E17

AB18

AA17

AC17

D16

F16

E15

AB16

AA15

AC15

D14

F14

E13

AB14

AA13

AC13

D12

F12

E11

AB12

AA11

AC11

D10

F10E9AB10

AA9

AC9D8F8E7AB8

AA7

VCC_55

VSS_53

B18

D17

VCC_56

VCC_57

VSS_54

VSS_55

F17

E18

VCC_58

VSS_56

AC7D6F6E5H6G5K6J5N5T6V6

VCC_59

VCC_61

VCC_62

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

Data

Signals

VCC_76

VCC_77

VCC_78

VCC_79

VCC_80

VSS_57

AB6

AA5

AC5M6P6

AB17

H_D#[0..63]

VCC_68

VCC_69

VCC_70

VCC_71

VCC_72

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

VCC_73

VCC_74

VCC_75

U5Y6W5

A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32

H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] 8

B11

A10
A13

C12
C10

A15
A14
B13
A12

AA3

AB3
C14

AF23

AF4

C22

AD23

AA2

K1

J1
G2
K3

J2
H3
G1
A3

J3
H1
D3
F3
G3
C2
B5

C6
B9
B7
C8
A8

B3
A9

C3

A6

R1
L3
T1
U1
L1
T4

W2

P3

A7
C4

R2
L2
V3

U2
T3

U8A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

TUALATIN

VCC_0

VCC_1

VCC_2

VCC_3

Address

Lines

Request

Signals

Error

Interface

Arbitration

Signals

Snoop

Signals

VSS_0

VSS_1

E16R4E25

VCC_4

VCC_5

VSS_2

VSS_3

G25

VCC_6

VSS_4

J25

L25

VCC_7

VCC_8

VSS_5

VSS_6

N25

VCC_9

VSS_7

R25

VCC_10

VSS_8

U25

VCC_11

VSS_9

W25

VCC_12

VSS_10

AA25

AC25

VCC_13

VCC_14

VSS_11

VSS_12

AF25

AE26

VCC_15

VCC_16

VSS_13

VSS_14

C23

F23

VCC_17

VCC_18

VSS_15

VSS_16

H23

K23

VCC_19

VCC_20

VSS_17

VSS_18

M23

P23

VCC_21

VCC_22

VSS_19

VSS_20

T23

V23

VCC_23

VCC_24

VSS_21

VSS_22

Y23

AB23

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

Mobile

Tualatin

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

AE23

B22

D21

F21

E22

H21

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC

VSS VCC

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

G22

K21

J22

M21

L22

P21

N22

T21

R22

V21

U22

Y21

W22

AB21

AA22

AC22

AE21

B20

D19

AB19

AA20

AC20

AE19

H_A#[3..31]8

2 2

H_REQ#[0..4]8

H_ADS#8

3 3

H_BREQ0#8

PIR(37)

H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#[0..4] H_D#33

+1.5VS

1 2
1 2
1 2

H_BPRI#8

H_BNR#8

H_LOCK#8

H_HIT#8

H_HITM#8

H_DEFER#8

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

R229 1.5K_0402

R249 @0_0402
R250 10_0402

+CPU_CORE

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1044

Size Document Number Rev

Custom

401196

*+

,-.

Date: Sheet

, 17, 2002

3

44

E

of

2A

A

B

C

D

E

+VCPU_IO

+1.5VS

+1.5VS

+1.5VS

Place CPURST#

1 1

R208<0.1" from
U6

R208

1K_0402

12

R228

1.5K_0402

12

R225

3K_0402

PIR(37)

H_PWRGD6

CPURST#8,20

PIR(37)

BSEL111

2 2

C598

L@1UF_0603

CLK_CPU_APIC11

+1.5VS +1.5VS

R202

150_0402

*26.7_1%_0402

12

12

R200
150_0402

1 2

R194 0_0402

PIR(19)

+VS_CMOSREF

3 3

12

R226

1.5K_0402

+3VS

12

12

H_TRDY#8

GT_A20M#6

GT_IGNNE#6

GT_SMI#6

GT_STPCLK#6

H_DPSLP#20,40

GT_INTR6

GT_CPUINIT#6

H_DBSY#8

H_DRDY#8

R218 1K_0402
1 2
1 2

R220 @1K_0402

R196
@137_1%_0402

CPU_LO/HI#6

Note :
GHI# Pull-Up internally

H_RS#08
H_RS#18
H_RS#28

GT_NMI6

PIC_CLK

C278

1 2

R199 @33_0402

@10PF_0402

1 2

R212 56.2_1%_0402

GT_A20M#
H_FERR#
H_FLUSH#
GT_IGNNE#

GT_INTR
GT_NMI

H_THERMDA
H_THERMDC

1 2

R60 110_1%_0402

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_PREQ#
ITP_PRDY#

AC3

AF6

AF5
AD9
AD3

AB4

AE4

AF8

AD15
AE14

AE6

B15

AF13
AF14

AE12
AF10
AF16

AD19
AD17
AF20

AF22
AE20
AD22
AD21

AD10

AD7

AD11

AF7

AF15
AF19
AE22

AF12

AD5

AE16

W1

W3

But pull high too weak

12

R51
10K_0402

CRTIT0
CRTIT1
H_THERMDA

12

C87
2200PF_0402

+3VS

+3VS

1 2

R52 10K_0402

R45 1K_0402

1 2

R214 1K_0402

1 2

W=40mil

16

NC

13

NC
OS#

5

CRIT0

1

CRIT1

3

DXP

4

DXN

12

R55
200_0402

2

15

U25MAX1617

VCC

14

STBY#

SMBC

12

SMBD

11

ALERT#

ADD1

GND

GND

ADD0

678910

Address:1001_110X

C89
.1UF_0402

1 2

Thermal Sensor
MAX1617

R44
@10K_0402

1 2

+3VS

B

MAINP

+3VS

+3VS

12

12

R57

R59

@0_0402

@0_0402

R46 @0_0402

1 2

4 4

12

12

R54

R58

@0_0402

@0_0402

R187 @0_0402

THERMDA_59131
THERMDC_59131

1 2
1 2

R188 @0_0402

A

AA18

AC18

AE17

B16

D15

F15

AB15

AA16

AC16

AE15

B14

D13

F13

E14

AB13

AA14

AC14

AE13

B12

D11

F11

E12

AB11

U8B

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

Y3

RS#0

V1

RS#1

U3

RS#2

M5

Request

RSP#

Signals GND

TRDY#

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#

Compatibility

DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#

DBSY#

Y1

DRDY#

THERMDA
THERMDC

SELFSB0
SELFSB1
EDGECTRLP

PICD0
PICD1
PICCLK

RP2#
RP3#
BPM0#
BPM1#

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

CMOSREF_1
CMOSREF_0
RTTIMPDEP

L5

GHI#

+VCPU_IO

EC_SMC2 23,31,35
EC_SMD2 23,31,35

From 87591

VCCT_1

VCCT_2

A26

G23

1.5K_0402

APIC

Debug
Break

Point

Test

Access

PORT
( ITP )

VCCT_3

VCCT_4

VCCT_5

VCCT_6

VCCT_7

VCCT_8

VCCT_9

VCCT_10

VCCT_11

VCCT_12

VCCT_13

VCCT_14

VCCT_15

VCCT_16

J23

L23

N23

R23

U23

W23

AA23

C21

C19

AD20

C17

AD18

C15

C13

+3VS+1.5VS

12

12

R201

R62

4.7K_0402

1

Q12

2

FDV301N

3

H_FERR#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AA12

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VCCT VID

VCCT_17

VCCT_18

VCCT_19

VCCT_20

VCCT_21

VCCT_22

AD14

C11

AD12C9C7

AD8C5AD6

FERR# 20

C

AC12

AE11

VSS_81

VSS_82

VCCT_23

VCCT_24

AC23

B10D9F9

VSS_83

VSS_84

VSS_85

VCCT_25

VCCT_26

VCCT_27

AA4E4G4J4L4

+VCPU_IO

VSS_86

VCCT_28

E10

AB9

AA10

AC10

AE9B8D7F7E8

AB7

AA8

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

Mobile

Tualatin

VCCT_29

VCCT_30

VCCT_31

VCCT_32

VCCT_33

VCCT_34

VCCT_35

VCCT_36

VCCT_37

VCCT_38

AC4V4AE3

AF2

AF1

AE18D5E6

R191

1 2

56.2_1%_0402
R492

+1.5VS

PIR(1)

ITP_TMSH_THERMDC

1 2

RP8

10

9
8
7
6

10P8R-1.5K

200_0402

AC8

AE7B6F5H5G6K5J6N6L6T5R6V5U6Y5W6

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VID0

VID1

VID2

VID3

VID4

VSS

VSS

VSSNCNC

AB1

AC2

AE2

AF3R3B26M4AF26C1AF17

ITP_PRDY#

ITP_PREQ#

ITP_TRST#

1

ITP_TDO

2

ITP_TCK

3

ITP_TDI

4
5

AB5

AA6

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

NC

N4

CPU_VR_VID4 7
CPU_VR_VID3 7
CPU_VR_VID2 7
CPU_VR_VID1 7
CPU_VR_VID0 7

D

AC6

AE5B4D4F4H4K4M3U4W4B2D2F2H2

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

Data

Signals

VTT Ref

Analog

VTTPWRGOOD

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

AD2

AE1

A25

C25

E20

F19

VTT_PWRGD#11,31,42

CLK_BCLK11

CLK_BCLK#11

Title

Size Document Number Rev

Custom

Date: Sheet

VSS_127

VSS_128

NCHCTRLP

VSS_130

VSS_131

K2M2P2T2V2Y2AB2

Tualatin/Celeron-T CPU

VSS_129

AE24

DEP#0

AD25

DEP#1

AE25

DEP#2

AC24

DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

VREF_1
VREF_2
VREF_3
VREF_4
VREF_5
VREF_6
VREF_7
VREF_8

TESTLO

VCC
PLL1
PLL2

NC
NC
NC
NC

CLK0

CLK0#

TESTLO

NC

TESTHI

NC
NC
NC

TESTHI

NC

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7

NC

TUALATIN

CLK_BCLK CLK_HCLK

12

R266
475_1%_0402

+VCPU_IO

AF24
AD26
AC26
AD24

AF21
AB26
H26
A21
AF9
A4
N1
AA1

Y4
R5
N3
N2
P1
P5
E1
F1

AC1
AD1
M1

AF18
AD16
AF11
AE8
N24
AE10
E2

P4

AD4
A5
D1
AD13
B1
P26
A11

E3

D26

+V_AGTLREF

TESTLO1
VCPU_PLL1

VCPU_PLL2

C370 33UF_16V_D2

CLK_HCLK
CLK_HCLK#
TESTLO2

NCHCTRLP
TESTHI1

TESTHI2

VTT_PWRGD

VTT_PWRGD#

2N7002

R259 33_0402

1 2

R264 60.4_1%_0402

1 2

Place all these Block's
Components near CPU (U6)

R261 60.4_1%_0402

1 2

R260 33_0402

1 2

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
401196

*+

,-.

, 17, 2002

RP28
1 8
2 7
3 6
4 5

8P4R_1K_0804

+CPU_CORE

L46

1 2

LQG21N4R7K10_4.7UH

+

1 2

R209 14_1%_0402

CLK_HCLK CLK_HCLK#

R262
@33_0402

1 2

C369
@10PF_0402

Q31

2

E

+VCPU_IO

1
3

12

12

4

1 2

R267
2K_0402

VTT_PWRGD

C371
@2.2UF_10V_0805

CLK_HCLK#CLK_BCLK#

of

TESTLO1
TESTLO2
TESTHI2
TESTHI1

+VCPU_IO

+VCPU_IO

R258
@33_0402

C367
@10PF_0402

44

2A

A

B

C

D

E

CPU Decoupling CAP.

Layout note :

1 1

Place close to CPU, Use 2~3 vias per PAD.
Place 0.22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Layout note :

Place close to CPU,
Use 2 vias per PAD.

+CPU_CORE

12

.22UF

12

.22UF

C321

C303

12

C287

.22UF

12

C319

.22UF

12

C67
10UF_6.3V_P

12

C232
10UF_6.3V_P

12

.22UF

12

.22UF

C288

C320

12

.22UF

12

.22UF

C284

C335

12

.22UF

12

.22UF

C285

C317

12

12

.22UF

C339

.22UF

C318

12

12

C275

C274

.22UF

.22UF

+CPU_CORE

12

12

C336

C338

2 2

3 3

.22UF

.22UF

+CPU_CORE

12

C71
10UF_6.3V_P

+CPU_CORE

12

C236
10UF_6.3V_P

+CPU_CORE

12

C76

+

470UF_4V_D4

ESR=%8m ohm ESR=%8m ohm

+

12

C283

.22UF

12

C337

.22UF

12

C70
10UF_6.3V_P

12

C235
10UF_6.3V_P

12

C62
470UF_4V_D4

12

.22UF

12

.22UF

C270

C299

12

12

12

+

12

C271

.22UF

12

C300

.22UF

C69
10UF_6.3V_P

C234
10UF_6.3V_P

C104
470UF_4V_D4

12

.22UF

12

.22UF

C272

C302

+

12

C68
10UF_6.3V_P

12

C233
10UF_6.3V_P

12

C102
470UF_4V_D4

ESR=%8m ohmESR=%8m ohm

+VCPU_IO

12

C286
1UF_10V

12

C368

+

220UF_2.5V_D2

ESR=25m ohm

12

C304
1UF_10V

C=690uF

C=690uF

C=690uFC=690uF

ESR=%0.

ESR=%0.465m ohm .

465m ohm .

ESR=%0.ESR=%0.

465m ohm .465m ohm .

(CPU)

(CPU)

(CPU)(CPU)

12

12

C322

C273

1UF_10V

1UF_10V

12

C289
1UF_10V

12

C92

+

470UF_4V_D4

ESR=%8m ohm

+VCPU_IO

12

C269
1UF_10V

Tualatin

D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)

-------------------------------------------------------

0

110

111

0 1.15V0

-------------------------------------------------------

1.40V

0

12

C301
1UF_10V

12

C316
1UF_10V

12

12

C340

C334

1UF_10V

1UF_10V

300 MHz & 0.95V : 4.11A
500 MHz & 1.05V : 6.38A
533 MHz & 1.05V : 6.61A
700 MHz & 1.10V : 8.40A
733 MHz & 1.15V : 9.39A
800 MHz & 1.15V : 9.84A
1000 MHz & 1.40V : 16.83 A
1066 MHz & 1.40V : 17.46 A
1133 MHz & 1.40V : 18.11 A

EMTS updated by the note released on April 27 , 2001.

+CPU_CORE

12

C231

+

220UF_2.5V_D2

ESR=25m ohm ESR=25m ohm

4 4

A

12

C230

+

220UF_2.5V_D2

Ctotal=2320uF

Ctotal=2320uF

Ctotal=2320uFCtotal=2320uF

ESR=3.309m

ESR=3.309m

ESR=3.309mESR=3.309m
ohm

ohm

ohmohm

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1044

Size Document Number Rev

Custom

401196

*+

,-.

Date: Sheet

, 17, 2002

5

44

E

of

2A

A

B

C

D

E

Geyserville Logic

without Geyserville,
GHI#(CPU_LO/HI#) can

+1.5VS

+VCPU_IO

+3V

+3VS

+3VS

+3VS

+3VS

FD5

1

FIDUCIAL MARK

CF5

1

FIDUCIAL MARK

CF14

1

FIDUCIAL MARK

CF17

1

FIDUCIAL MARK

CF4

1

FIDUCIAL MARK

OPEN

+3V
+3VS
+3VS
+3VS
+3VS

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

RP39

8P4R_1.5K_0804

RP22
1 8
2 7
3 6
4 5

LN_8P4R_4.7K_0804
1 2
1 2

1 2
1 2
1 2
1 2
1 2

1

FIDUCIAL MARK

1

FIDUCIAL MARK

1

FIDUCIAL MARK

GT_NMI
GT_INTR
GT_IGNNE#
GT_A20M#

GT_CPUINIT#
GT_STPCLK#
GT_SMI#
CPU_LO/HI#

VR_HI/LO#

G_VR_POK

GT_CPU_STP#

GT_SUSTAT1#

FD3

CF16

CF13

1 8
2 7
3 6
4 5

1 2

R129 1K_0402

1 2

R138 680_0402

1 2

R322 330_0402

1 2

R128 L@1.5K_0402

1 2

R135 10K_0402

1 2

R357 LN_10K_0402

1 2

R333 4.7K_0402

1 2

R345 10K_0402

R137 LN_4.7K_0402
R323 10K_0402

R349 LN_1K_0402
R341 10K_0402
R347 LN_10K_0402
R328 @10K_0402
R334 @10K_0402

FD6

CF6

CF18

CF11

CF1

HCPUINIT#
HNMI
HINTR
HSMI#

HSTPCLK#
VRCHGNG#

CRESET#
GT_LO/HI#
SUS_STAT#
HA20M#
HIGNNE#

PIR(28)

FD1

1

FIDUCIAL MARK

CF10

1

FIDUCIAL MARK

CF7

1

FIDUCIAL MARK

FD2

1

FIDUCIAL MARK

CF19

1

FIDUCIAL MARK

CF3

1

FIDUCIAL MARK

U32
LN_AMI11686-001

HNMI

HNMI20

R494

100K_0402

22K

2

Q61
DTC124EK

C484
LN_15PF_0402

+5VS

C

B

22K

HOLEB

HINTR
HCPUINIT#

HSMI#
HSTPCLK#

SUS_STAT#
CPUSTP#

GT_LO/HI#

VGATE

CRESET#

LN_14.318MHZ

12

12

2

G

13

E

HA6
HOLEA

1

1

HB1

1

1

Y6

1 2

13

D

S

HOLEB

R346
LN_1K_0402

12

LN_15PF_0402

HNMI

Q60
2N7002

PIR(6)

HA1
HOLEA

1

1

HB4

1

1

12

HINTR20

1 1

2 2

3 3

HCPUINIT#20

HSTPCLK#20

SUS_STAT#20,29

CPUSTP#11,20,33

GT_LO/HI#20

CRESET#9

CRESET#

HSMI#20

VR_ON31,34,40
VGATE40

C481

HA3
HOLEA

1

HB2

HOLEB

1

20

NMI

16

INTR

22

INIT#

24

A20M#

21

IGNNE#

17

SMI#

23

STPCLK#

19

SUSSTAT1#

13

CPU_STP#

14

G_LO/HI#

15

VR_ON

29

VGATE

43

IGN_VGATE#

28

VR100/50#

44

PLL30/60#

41

CRESET#

26

CLK_IN

25

CLK_OUT

45

CLKEN#L

38

STB#

37

DIN

36

DOUT

GND

GND

618314227

HA20M#20 GT_A20M# 4

HIGNNE#20

HA2

HA5

HOLEA

HOLEA

1

1

HB3

HOLEB

1

1

1

HC1

HOLEC

1

1

1

G_NMI

G_INTR

G_INIT#

G_A20M#

G_IGNNE#

G_SMI#

G_STPCLK#

G_SUSSTAT1#

G_CPU_STP#

RESERVED

CPUPWRGD

VRPWRGD

VRCHGNG#

VR_HI/LO#

LP_TRANS#

RESERVED
RESERVED
RESERVED

GND

GND

GND

VCC3

VCC3

30

7

12
C423

LN_.01UF_0402

CPUSTP#
HINTR
HSMI#
HCPUINIT#

HNMI
SUS_STAT#

VGATE G_VR_POK
HSTPCLK# GT_STPCLK#

HA4
HOLEA

1

1

1

1

HD1

HOLED

1

1

GT_NMI

1

GT_INTR

4

GT_CPUINIT#

8
48
2

GT_SMI#

5

GT_STPCLK#

3

GT_SUSTAT1#

11

GT_CPU_STP#

47
46
10

GHI#

H_PWRGD

9

G_VR_POK

32

VRCHGNG#

12

VR_HI/LO#

33
34

35
39
40

12
C466

LN_.1UF_0402

HA20M#

HIGNNE#

RP43

L@16P8R_0
R361 L@0_0402
R134 L@0_0402

for without Geyserville

HA7
HOLEA

1

1

HD2

HOLED

1

1

1 2

+3V

R327
0_0402

R331

0_0402

1 2
1 2

R136

LN_10K_0402

12

12

89
710
611
512
413
314
215
116

HA8
HOLEA

1

1

2

G

GT_A20M#

GT_IGNNE#

GT_CPU_STP#
GT_INTR
GT_SMI#
GT_CPUINIT#

GT_NMI
GT_SUSTAT1#

HA9
HOLEA

1

GT_NMI 4
GT_INTR 4
GT_CPUINIT# 4

GT_SMI# 4
GT_STPCLK# 4

GT_SUSTAT1# 9
GT_CPU_STP# 7,11

H_PWRGD 4
G_VR_POK 33

VRCHGNG# 20
VR_HI/LO# 7,40

CPU_LO/HI#

13

D

Q18

S

LN_SI2302DS

1

L@_1.5K_0402

H_PWRGD

GT_IGNNE# 4

CPU_LO/HI# 4

R499

+3VS

12

2

31
Q63
L@_FDV301N

SPWROFF# 19,20,31,33

PIR(16)

Fiducial Mark

FD4

1

FIDUCIAL MARK

CF12

1

FIDUCIAL MARK

CF15

1

FIDUCIAL MARK

CF8

1

FIDUCIAL MARK

CF2

1

FIDUCIAL MARK

4 4

A

HE1
HOLEE

1

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

E

644

2A

of

A

B

C

D

E

+3VS

U11

5

PCISTP#11,20

PM_SLP_S1#10,19,20,31,33

1 1

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3

CPU_VR_VID4

RP14
1 8
2 7
3 6
4 5

L@8P4R-0
1 2

R263

L@0_0402

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

CPU_VID4

GT_CPU_STP#6,11

DPSLP#20

1 2

R79 @1.2K_0402

1 2

R78 @56_0402

C116

@1UF_10V

C118

@.1UF_0402

1
2

3

12

+3VS

5
1

2
3

12

@7SH32

U9

@7SH32

4

R493

@0_0402

4

+3VS

2
1

U10
@7SH00

1 2

3 5

DPRSLPVR

4

12

R501
0_0402

DPRSLPVR 40

CPU Voltege ID

PIR(28,30)

201

VCC3SCL

19

ASEL

18

WP

17
16

15

Y-0

14

Y-1

13

Y-2

12

Y-3

11

Y-4

RP79
1 8
2 7
3 6
4 5

LN_8P4R_0
1 2

R502

LN_0_0402

U12

B0 D0
B1 D1
B2 D2
B3 D3
B4 D4

BE#

@SN74CBT3383

+3V

12

C374
LN_.1UF_0402

R275 LN_0_0402

1 2

VID0
VID1
VID2
VID3
VID4

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

CPU_VID4

C0A0
C1A1
C2A2
C3A3
C4A4

VCC

GNDBX

+VCPU_IO

12

R48

+1.5VS

1K_1%_0402

12

R53
2K_1%_0402

PIR(22)

12

R230
510_0402

12

R235
1K_0402

R272

1 2

LN_0_0402

ADDRESS: ASEL = LOW => 6E/6F

R274 LN_10K_0402

1 2

13

D

Q32

2

G

S

LN_SI2302DS

CPU_VID0

23

CPU_VID1

67

CPU_VID2

1011

CPU_VID3

1617

CPU_VID4

2021

+5V
24
1213

12

C117
@.01UF_0402

+3V

CPU_VID0 40
CPU_VID1 40
CPU_VID2 40
CPU_VID3 40
CPU_VID4 40

GTL Reference Voltage

Layout note :

1. Place R48 and R53 between the TwisterT and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

12

C255
.1UF_0402

12

C256
.1UF_0402

12

C351
.1UF_0402

12

C350
.1UF_0402

+V_AGTLREF

CMOS Reference Voltage

Layout note :

1. Place R230 and R235 between the TwisterT and CPU.

2. Place decoupling caps near CPU.

12

C308
.1UF_0402

12

C352
.1UF_0402

+VS_CMOSREF

R271 @0_0402

R76
@0_0402

1 2

R270

1 2

@0_0402

R72

@10K_0402

R71

@0_0402

1 2

R273 LN_0_0402

1 2

R269 LN_0_0402

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3

CPU_VR_VID4

+3V

12

182736

45

RP21
@8P4R_10K_0804

12

12

12

12

12

U28

2

SDA

3

Override#

4

I-0

5

I-1

6

I-2

7

I-3

8

I-4

9

Level

10

GND

LN_FM3560

VID0
VID1
VID2
VID3
VID4

STRAP_VID0
STRAP_VID1
STRAP_VID2
STRAP_VID3
STRAP_VID4

DPRSLPVR

Non_Mux_Out

Mux_Sel

VR_HI/LO#6,40

VID0
VID1
VID2
VID3

VID4

4 5

8 9
14 15
18 19
22 23

1

EC_SMC131,32,41

SMB_SB_CK12,20

EC_SMD131,32,41

SMB_SB_DA12,20

2 2

3 3

4 4

+3V

CPU_VR_VID04
CPU_VR_VID14
CPU_VR_VID24
CPU_VR_VID34
CPU_VR_VID44

Default for Resistors Should
be +VCC_CPU = 0.85V, for
Deeper Sleep Only.
VID[4:0]->10101

R73

R74
@0_0402

@0_0402

@0_0402

RP27

1 8
2 7
3 6
4 5

8P4R_1K_0804

1 2

R268 1K_0402

R75

PIR(30)

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SCHEMATIC, M/B LA-1044

Size Document Number Rev

Custom

401196

*+

,-.

Date: Sheet

, 17, 2002

7

44

E

of

2A

A

B

C

D

E

TwisterT(VIA_VT8606)-A

W=40mils

12

C312

1UF_10V

H_REQ#[0..4]
H_RS#[0..2]
H_D#[0..63]
H_A#[3..31]

12

+

C246
47UF_6.3V_B

12

+

C280
47UF_6.3V_B

CPURST#4,20
H_ADS#3
H_BNR#3
H_BPRI#3

H_DBSY#4
H_DEFER#3

H_DRDY#4

H_HIT#3
H_HITM#3
H_LOCK#3
H_TRDY#4

H_BREQ0#3

12

C358

1UF_10V

12

C357
1000PF_0402

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R232

1 2

0_0402

H_RS#0
H_RS#1
H_RS#2

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HCLK_NB

12

C305
1000PF_0402

2.5V +- 5%

+2.5VS

U7A

A25

HA3#

D24

HA4#

B25

HA5#

B26

HA6#

E23

HA7#

C26

HA8#

C24

HA9#

A23

HA10#

C25

HA11#

D22

HA12#

B24

HA13#

D25

HA14#

F22

HA15#

C23

HA16#

D21

HA17#

A20

HA18#

C22

HA19#

A21

HA20#

B23

HA21#

A22

HA22#

B21

HA23#

E20

HA24#

B22

HA25#

B19

HA26#

C20

HA27#

A24

HA28#

B20

HA29#

D20

HA30#

C21

HA31#

A19

CPURST#

J24

ADS#

D26

BNR#

E26

BPRI#

H26

DBSY#

F26

DEFER#

J23

DRDY#

G24

HIT#

G26

HITM#

G23

HLOCK#

G25

HTRDY#

J25

BREQ0#

H23

RS0#

K23

RS1#

H25

RS2#

E24

HREQ0#

F23

HREQ1#

F24

HREQ2#

F25

HREQ3#

E25

HREQ4#

G22

HCLK

E12

GTLVREF

E21

GTLVREF1

VIA_VT8606

L9M9R9T9V10

J11

J12

J15

V15

J16

L18

M18

T18

U18

J9K9U9V9J10

V11

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VDD25

VT8606
TwisterT

HOST INTERFACE

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

N6

B2N3L11

GND

GND

GND

GND

GND

GND

GND

GND

N11

A18

P11

T11

M12

N12

P12

R12

GND

AF18

C19

AD19

F21

N21

P21

AA21

V12

VDD25

GND

D23

V16

AC23

J17

VDD25

VDD25

GND

GND

H24

V17

VDD25

GND

W24

J18

VDD25

GND

A26

K18

VDD25

GND

J26

R18

VDD25

GND

V26

V18

VDD25

GND

AF26

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

H_D#0

E19

H_D#1

B18

H_D#2

B16

H_D#3

A16

H_D#4

C18

H_D#5

C17

H_D#6

D18

H_D#7

D15

H_D#8

D17

H_D#9

C16

H_D#10

B17

H_D#11

D16

H_D#12

A17

H_D#13

A15

H_D#14

E16

H_D#15

D19

H_D#16

A14

H_D#17

E18

H_D#18

E17

H_D#19

B14

H_D#20

C15

H_D#21

E14

H_D#22

B11

H_D#23

D14

H_D#24

B15

H_D#25

D13

H_D#26

C13

H_D#27

E9

H_D#28

C12

H_D#29

D12

H_D#30

E15

H_D#31

A13

H_D#32

B12

H_D#33

B13

H_D#34

A12

H_D#35

E13

H_D#36

D11

H_D#37

D10

H_D#38

A11

H_D#39

E10

H_D#40

E8

H_D#41

C9

H_D#42

D9

H_D#43

C11

H_D#44

B10

H_D#45

A10

H_D#46

E7

H_D#47

D8

H_D#48

B8

H_D#49

C10

H_D#50

B6

H_D#51

B9

H_D#52

F8

H_D#53

D6

H_D#54

D7

H_D#55

C7

H_D#56

E5

H_D#57

A7

H_D#58

E6

H_D#59

B7

H_D#60

C6

H_D#61

D5

H_D#62

A6

H_D#63

A8

H_REQ#[0..4]3

H_RS#[0..2]4

12

C342
.1UF_0402

12

C309
.1UF_0402

H_D#[0..63]3

H_A#[3..31]3

12

C282
.1UF_0402

12

C323
.1UF_0402

1 1

+2.5VS

12

12

12

12

12

12

C295

C291

C307

C326

.01UF_0402

.01UF_0402

.01UF_0402

+2.5VS

12

12

12

C266

C324

.01UF_0402

.01UF_0402

2 2

C354
.01UF_0402

12

.1UF_0402

C330
.1UF_0402

C292
.1UF_0402

12

C310
.1UF_0402

C327
.1UF_0402

12

C268
.1UF_0402

12

C279
.1UF_0402

12

C281
.1UF_0402

PIR(37)

R213

1 2

75_1%_0402

150_1%_0402

+GTL_VREF

2/3 +VCPU_IO +- 2%

12

R215

3 3

HCLK_NB11

+VCPU_IO

12

R242

@10_0402

12

C366

@27PF_0402

** Place as close to
TwisterT as possible.

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

E

844

2A

of

A

B

C

D

E

TwisterT(VIA_VT8606)-B

1 1

MMD[0..63]13

+3VS

12

C277

C293

C311

C315

12

C297

.01UF_0402

12

C329

.01UF_0402

12

C332

.01UF_0402

12

C306

.01UF_0402

C296
.01UF_0402

12

C294
.01UF_0402

12

C314
.01UF_0402

12

C328
.01UF_0402

12

1000PF_0402

2 2

+3VS

12

1000PF_0402

+3VS

12

1000PF_0402

3 3

+3VS

12

1000PF_0402

4 4

MMD[0..63]

** Place as close to
VT8606 as
possible.

12

C331
.1UF_0402

12

C349
.1UF_0402

12

C325
.1UF_0402

12

C265
.1UF_0402

12

C348
.1UF_0402

12

C356
.1UF_0402

12

C355
.1UF_0402

12

C290
.1UF_0402

12

C347
1000PF_0402

12

C333
1000PF_0402

MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

+3VS +- 5%

+3VS +VCPU_IO

M23

M26
M24

AD22
AF22
AB21
AE21
AB20
AD20
AE20
AC19
AF19
AC18
AE18
AD17
AF17
AB17
AE16
AC16

M22
M25

AE22
AC21
AD21
AF21
AC20
AF20
AB19
AE19
AB18
AD18
AA19
AE17
AC17
AD16
AF16
AB16

K25
L26
L25

N26
N24
P23
P25
R23
R25
P22
T23
T25
T22

K26
L23

L24
N23

N25
N22
P26
P24
R26
R24
R22
T26
T24
U23

U7B

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

VIA_VT8606

GND

GND

GND

P1

AF1D4AC4F6P6

G6

H6

VCC3

J6

VCC3

VCC3

L4

R21

VCC3

T4

VCC3

VCC3

U21

VCC3

V6

V21

VCC3

W6Y6AA7

VCC3

VCC3

VCC3

Y21

VCC3

AA9

VCC3

AA10

VCC3

VT8606
TwisterT

DRAM INTERFACE

GND

GND

GND

GND

GND

GND

GND

GND

GND

AA6C8AD8A9N9P9AF9

GND

GND

GND

GND

GND

M11

R11

L12

T12

F13

VCC3

GND

AA17

J13

VCC3

GND

AA18

V13

AA20

VCC3

GND

L13

VCC3

GND

M13

GND

F7

F10

F12

F17

G21

F20

F18

E11

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

GND

N13

VTT

GND

GND

GND

GND

GND

GND

GND

GND

P13

R13

T13

AA13

AD13

C14

J14

V14

L15

VTT

GND

K21

J21F9F19

VTT

GND

T15

M16

VTT

RAS0#/CS0#
RAS1#/CS1#
RAS2#/CS2#
RAS3#/CS3#
RAS4#/CS4#
RAS5#/CS5#

DQM0/CAS0#
DQM1/CAS1#
DQM2/CAS2#
DQM3/CAS3#
DQM4/CAS4#
DQM5/CAS5#
DQM6/CAS6#
DQM7/CAS7#

SRASA#
SCASA#

SWEC#/CKE0

SCASC#/CKE1

SWEB#/CKE2
SCASB#/CKE3
SRASC#/CKE4
SRASB#/CKE5

VSUS25

SUSST#

PLLTEST

CRSTD#

PWROK

PCIRST#

GND

GND

GND

GND

R16

N18

P18

M21

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8

MA9
MA10
MA11
MA12
MA13
MA14

SWEA#

DCLKO

DCLKI

GND

GND

T21

+VCPU_IO

12

W=5mils

C365

R237
@100_0402

1 2

R248

@500

1 2

PIR(26)

PIR(26)

12

+3V

+

C298
47UF_6.3V_B

W=5mils

R234
10_0402

1 2
12

C345
15PF_0402

R265

4.7K_0402

21

MMA0

AA23

MMA1

AB23

MMA2

AB26

MMA3

AB25

MMA4

AB24

MMA5

AC26

MMA6

AC25

MMA7

AC24

MMA8

AD26

MMA9

AD25

MMA10

AE26

MMA11

AD24

MMA12

AE24

MMA13

AE25

MMA14

AF25

RRAS0#

R256 22_0402

Y26

RRAS1#

Y25

RRAS2#

Y24

RRAS3#

Y23
Y22
W21

RRCAS#0

V23

RRCAS#1

W23

RRCAS#2

AF24

RRCAS#3

AE23

RRCAS#4

W26

RRCAS#5

W25

RRCAS#6

AD23

RRCAS#7

AF23

S_RASA#

AA24

S_CASA#

U22

RM_WEA#

U24

CKE0_1

U26

CKE1_1

V24

CKE2_1

U25

CKE3_1

V25
AA26
AA25

DCLKO_R

J22

W=5mils

K22

V22

N/C

W22

NC PINs

N/C

AB22

N/C

VSUS25

AA22

AC22
K24

CRESET#

E22
AD14
AE15

1 2

R252 22_0402

1 2

R240 22_0402

1 2

R239 22_0402

1 2

RP30 8P4R_22_0804

4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8

RP35 8P4R_22_0804

R246 10_0402

1 2

R238 10_0402

1 2

R247 10_0402

1 2

R257 33_0402

1 2

R245 33_0402

1 2

R251 33_0402

1 2

R253 33_0402

1 2

R241

1 2

18_0402

@22PF_0402

place
closely to
VT8606

GT_SUSTAT1# 6
CRESET# 6

PWROK 33
PCIRST# 14,16,18,19,22,23,29,31,36

12

C353

@.1UF_0402

PIR(14,35)

12

D14
1N4148

VSUS25

+VCPU_IO +VCPU_IO

12

C592
1000PF_0402

RAS#0 12
RAS#1 12
RAS#2 13
RAS#3 13

RCAS#0 12,13
RCAS#1 12,13
RCAS#2 12,13
RCAS#3 12,13
RCAS#4 12,13
RCAS#5 12,13
RCAS#6 12,13
RCAS#7 12,13

SRASA# 12,13
SCASA# 12,13
RMWEA# 12,13

CKE0 12
CKE1 12
CKE2 13
CKE3 13

DCLKO 11
DCLKRW 11

12

C593
.1UF_0402

MMA[0..14]

PIR(17)

+3VS

12

+

C341
47UF_6.3V_B

MMA[0..14] 13
RCAS#[0..7] 12,13

+3VS

R65 @10K_0402

MMA4

1 2

R255 @10K_0402

MMA3

1 2

R254 @10K_0402

MMA2

1 2

R66 10K_0402

MMA6

1 2

R67 10K_0402

MMA8

1 2

R64 @10K_0402

MMA12

1 2

MA4 L DISABLE INTA# CLAIM

H ENSABLE INTA# CLAIM

MA3 L DISABLE I/O ACCESS

H ENABLE I/O ACCESS

MA2 L ADDRESS MAPPING 1

H ADDRESS MAPPING 0

MA12 MA8

00=66 MHZ
01=AUTO
11 = 133 MHZ
10 = 100 MHZ

MA6 GTL INTRNAL PULLUPS
0 ENABLE
1 DISABLE

CPU FSB FREQ.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

E

944

2A

of

A

C364
1UF_10V

RP7

1
2
3
4
5

@10P8R_10K

RP6

1
2
3
4
5

10P8R_10K

CBE#[0..3]
AD[0..31]

HB-1M2012-601JT

12

C360

+

10UF_10V_1206

10
9
8
7
6

10
9
8
7
6

+3VS

53

2 4

L43

GNT#0
GNT#1
GNT#2
GNT#3

REQ#0
REQ#1
REQ#2
REQ#3

U23

NC7S04

+2.5VS

+3VS

+3VS

REQ#036
REQ#136
REQ#229
REQ#316
REQ#418,21

GNT#036
GNT#136
GNT#229
GNT#316
GNT#418,21

PREQ#19

PGNT#19

FRAME#16,18,19,29,36

PLOCK#19

PAR16,18,19,29,36
SERR#16,19,29,36
TRDY#16,18,19,29,36

IRDY#16,18,19,29,36
STOP#16,18,19,29,36

DEVSEL#16,18,19,29,36
PCLK_NB11
CLKRUN#16,19,31,36

LVDS2_C+15
LVDS2_C-15
LVDS2_2+15
LVDS2_2-15
LVDS2_1+15
LVDS2_1-15
LVDS2_0+15
LVDS2_0-15
LVDS1_C+15
LVDS1_C-15
LVDS1_2+15
LVDS1_2-15
LVDS1_1+15
LVDS1_1-15
LVDS1_0+15
LVDS1_0-15

SUSPEND

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE#0
CBE#1
CBE#2
CBE#3

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

PREQ#
PGNT#

PCLK_NB

+VCCA

16,18,19,29,36

CBE#[0..3]

AD[0..31]16,18,19,29,36

1 1

+3VS

2 2

+3VS

3 3

4 4

C362

1000PF_0402

GNT#4

PGNT#
PREQ#
REQ#4

12

12

PM_SLP_S1#7,19,20,31,33

+VCCA

PCLK_NB

R221

10_0402

C313

15PF_0402

AF14
AE14
AE13
AF13
AC14
AB14
AC13
AB13
AE12
AD12
AB12
AC12
AF11
AE11
AD11
AC11

AA8
AC9
AF8
AE8
AE7
AB8
AF7
AC8
AC7
AB7
AF6
AE6
AD6
AC6
AB6
AF5

AF12
AB11

AD9
AD7

AC5
AD5
AE4
AD4
AF2

AB5
AF4
AF3
AE3
AE2

AC15
AD15

AE9

AE5
AB10
AF10
AD10
AC10
AE10

AB9
AB15
AF15

AD1

AE1

AA4

AB4

AC3

AD3

AC2

AD2

AB1

AC1

AA5

AA3

AB3

Y5

W4

Y4

H22
H21

B

U7C

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

REQ0#
REQ1#
REQ2#
REQ3#
REQX#

GNT0#
GNT1#
GNT2#
GNT3#
GNTX#

PREQ#
PGNT#

FRAME#
PLOCK#
PAR
SERR#
TRDY#
IRDY#
STOP#
DEVSEL#
PCLK
CLKRUN#

ZCP
ZCM
Z2P
Z2M
Z1P
Z1M
Z0P
Z0M
YCP
YCM
Y2P
Y2M
Y1P
Y1M
Y0P
Y0M

VCCA
VCCA

VIA_VT8606

GNDA

L22

GNDA

L21

+DACVDD

C1D1A5

VCCDAC

PCI INTERFACE LVDS

GND

GND

GND

F14

L14

M14

LAVDDPLLVDD2

LVDD

PLLVDD1

B3

VCCRGB

VCCPLL1

W1W2Y2

VCCPLL2

LVDSVCCA

LAVDD

LVDS1VCCA

VT8606
TwisterT

GND

GND

GND

GND

GND

GND

GND

GND

GND

N14

P14

R14

T14

AA14

M15

N15

P15

R15

VDDD

GND

AA15

C

VCCRGB
VCCA
VCCDAC
VCCPLL1

1 2

R193 4.7K_0402

WSC#

DFTIN

BISTIN

AB2

PLLVCCA

GND

GND

GND

GND

GND

F16

L16

N16

P16

T16

GNDPLL1

A4

F15

AA11

WSC

BISTIN

GNDRGB

GNDPLL2

F11

DFTIN

GNDDAC

B1A1B5

1 2

R189 4.7K_0402

C4

B4

STP_AGP

AGP_BUSY

STRW/GPOUT

SUSPEND
STANDBY

PANELDET

PANELCLK
PANELDEN

PANELVS

PANELHS
PD0/TVD11
PD1/TVD10

DISPLAY INTERFACE

PD8/TVD9

PD9/TVD8

PD16/TVCLKR

PD17/TVBLANK

PD24/TVD6
PD25/TVD4
PD26/TVD5
PD27/TVD7
PD28/TVD0
PD29/TVD1
PD30/TVD3
PD31/TVVS

PD32/TVCLK

PD33/TVD2
PD34/TVHS

LVDSGND

LVDS1GND

PLLGND

VSSD

Y1

AA1

Y3

AA2

GREEN

BLUE
HSYNC
VSYNC

SPD1

SPCLK1

COMP

RSET

GOP0

FPGPIO

XTLO

INTA

SPCLK2

SPD2

LD10
LD11
LD12
LD13
LD14
LD15

HREF

LCLK

ENVEE
ENVDD

PD10
PD11
PD12
PD13
PD14
PD15

PD18
PD19
PD20
PD21
PD22
PD23

PD35

RED

XTLI

PD2
PD3
PD4
PD5
PD6
PD7

N/C

LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9

VS

+3VS

C2
D3
D2
E2
E1
F2
F3
E4

IRSET

E3

GOP0

C3
G1
AA12
A2
A3
W5

SUSPEND

F5

STANDBY

F4
U6
M2
M3

R6
T2
T1
R5
R2
R4
R1
R3
P5
P2
P3
P4
N5
N2
N1
N4
T3
U1
U3

AA16
H5
F1
G4
H3
G3
G5
G2
H2
H1
J2
J1
H4
K6
J4
J3
L5
K2
J5
K1
K3
L6
L2

R195 22_0402

K5
L1
L3
M6
K4
M4
M5
M1
T6
T5
U4
U2
V1
V2
V3
W3
V4
U5
V5
C5

VCCPLL2
VCCLPLL
VCCLVDS
VDDD

C359 .1UF_0402

R190 @33K_0402

12

R197

10K_0402

R224 33K_0402

PANELDET

TVD11
TVD10

TVD[0..11]

TVD9
TVD8

TVD6
TVD4
TVD5
TVD7
TVD0
TVD1
TVD3

TVD2

12

12

2.5V +- 0.25V

2.5V +- 0.25V

2.5V +- 0.25V

2.5V +- 0.25V

2.5V +- 0.25V

3.3V +- 0.3V

3.3V +- 0.3V

2.5V +- 0.25V

+2.5VS

+3VS

R33
10_0402

C79
15PF_0402

12

C264
15PF_0402

12

R198
10_0402

12

C276
15PF_0402

D

RED 14,35
GREEN 14,35
BLUE 14,35
HSYNC 14
VSYNC 14
SPDAT1 14
SPCLK1 14

OSCGUI 11
PIRQA# 16,19

DDCCLK 14
DDCDATA 14

ENVEE 15,31
ENVDD 15

TVD[0..11] 14

TVCLKR 14

TVVS 14
TVCLK 14

TVHS 14

-> 2.5V +- 0.25V

+2.5VS

+2.5VS

FBM_L11-201209-601LMT

+2.5VS

FBM_L11-201209-601LMT

+2.5VS

LAVDD

E

TwisterT(VIA_VT8606)-C

WSC#
BISTIN
DFTIN
IRSET

L40

HB-1M2012-601JT

L37

L38

HB-1M2012-601JT

L41

C254
.1UF_0402

+3VS

C245
1000PF_0402

C267
1000PF_0402

C260
1000PF_0402

C253
.1UF_0402

L39

HB-1M2012-601JT

1 2

R216 10K_0402

1 2

R222 1K_0402

1 2

R217 1K_0402

1 2

R182 147_1%

1 2

R223 @0_0402

1 2

R219 @0_0402

+DACVDD

C244
1UF_10V

PLLVDD2

C263
1UF_10V

PLLVDD1

C261
1UF_10V

12

C251

+

10UF_10V_1206

LVDD

C257
.1UF_0402

+3VS

PIR(3)

12

C240

+

10UF_10V_1206

12

C262

+

10UF_10V_1206

12

C249

+

10UF_10V_1206

C252
.1UF_0402

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

10 44

E

2A

of

A

B

C

D

E

F

G

H

Clock Generator

1 1

12

C136
1000PF_0402

12

C140
.1UF_0402

+VCLK_CPU

PWR_DWN#

GT_CPU_STP#

FS1
FS0

+3VS_CPUCLK

U13

46

VDDCPU_2.5

45

VDDCPU_3.3

5

VDDREF

9

VDDPCI

29

VDDSDRAM

35

VDDSDRAM

28

AVDD48

21

*PD#

19

*CPU_STOP#

20

*PCI_STOP#

24 43

SDATA CPUCLKC

25

SCLK

26

24_48MHz/FS1*

27

48MHz/FS0*

4

Vtt_PWRGD#

22

MULTSEL

40

IREF

41

RESET#

1

GND

6

GND

12

GND

23

GND

32

GND

38

GND

42

GND

7 8

X1 X2

CY28317-2

1 2

12

C163
15PF_0402

14.318MHZ

*FS4/PCICLK_F

*FS3/PCICLK0

Y1

REF0

*FS2/REF1

PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

CPUCLK1
CPUCLK0
CPUCLKT

SDRAM_IN

SDRAM0
SDRAM1

SDRAM2
SDRAM3

SDRAM4
SDRAM5

SDRAM6

PIR(20)

R105 33_0402

1 2

R106 33_0402

3

FS2

2

FS4

10

FS3

11
13
14
15
16
17

47
48

HOST_CPU

44

HOST_CPU# CLK_BCLK#

18
37

36
34

33
31

30
39

12

C164
15PF_0402

1 2

R110 33_0402

1 2

R87 22_0402

1 2

R116 22_0402

1 2

R127 22_0402

1 2

R117 22_0402

1 2

R118 22_0402

1 2

R119 22_0402

1 2

R120 22_0402

1 2

R123 22_0402

1 2

R99 22_0402

1 2

R100 @22_0402

1 2

R89 0_0402

1 2

R90 0_0402

1 2

R97 10_0402

1 2

R98 10_0402

1 2

R94 10_0402

1 2

R95 10_0402

1 2

R96 22_0402

1 2

12

R121
@10_0402

12

C166
@15PF_0402

PIR(14)

CLK_BCLK
CLK_BCLK

C134

15PF_0402

14.318M_TV 14
OSCGUI 10
OSCSB 21
CLK_CPU_APIC 4
PCLK_SB 19
PCLK_LAN 29
PCLK_LPC 31
PCLK_NB 10
PCLK_PCM 16
PCLK_MINI 36
PCLK_1394 18

HCLK_NB 8
CLK_BCLK 4

CLK_BCLK# 4

DCLKO 9

CLK_SDRAM0 12
CLK_SDRAM1 12

CLK_SDRAM2 13
CLK_SDRAM3 13

DCLKRW 9

L23

+3VS

VTT_PWRGD#4,31,42

1 2

1 2

HB-1M2012-121JT

4.7UF_10V_0805

1 2

HB-1M2012-121JT

12

C161
1000PF_0402

12

C141
1000PF_0402

GT_CPU_STP#6,7

SDACLK12
SCKCLK12
BSEL14
USBCLK19

C131

L21

12

C160
.01UF_0402

+3VSCLK

PCISTP#7,20

+2.5V_CLK

+3VSCLK

L25

1 2

+3VS

HB-1M2012-121JT

C158

4.7UF_10V_0805

L22

1 2

+3VS

HB-1M2012-121JT

C130

4.7UF_10V_0805

2 2

CPUSTP#6,20,33

3 3

12

C159
.01UF_0402

+3VS_SDR

Width=40 mils

12

C132
.01UF_0402

1 2

R109 @0_0402

Width=40 mils

12

12

+3VSCLK

12

R108
@10K_0402

C139
1000PF_0402

C138
1000PF_0402

GT_CPU_STP#

12

C162
.01UF_0402

12

C142
.01UF_0402

R86 220_1%_0402

Width=40 mils

12

C135
.01UF_0402

Width=40 mils

12

C167
1000PF_0402

R107 10K_0402

1 2

R101 100_0402

1 2
1 2

R92 22_0402

12

R112

10K_0402

12

C137
@33PF_0402

+3VSCLK +3VSCLK +3VSCLK +3VSCLK+3VSCLK

12

12

12

R124

R88

10K_0402

10K_0402

12

R125

4 4

@10K_0402

A

R122
10K_0402

12

R111
@10K_0402

12

R93
10K_0402

12

R91
10K_0402

FS0
FS1
FS2
FS3
FS4

FS4 FS3 FS2 FS1 FS0 CPUCLK/PCICLK

1

1

0

1

0

1

11

1
111
01

1

133.30/33.30 (0 ~ -0.5% down spread)

133.60/33.40 (+/-0.25% center spread)

133.90/33.47 (+/-0.25% center spread)

11101 100.00/33.30 (0 ~ -0.5% down spread)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

E

F

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

G

11 44

of

H

2A

A

B

C

D

E

F

G

H

SO-DIMM0 (Bank 0,1)

+3V

INHIB
ENDIM0
ENDIM1

12

12

C155
1UF_25V_0805

12

12

6

10

9

3

13

0

0

1

X

12

C144

C145

.1UF_0402

.1UF_0402

12

C152
.01UF_0402

12

C422

4.7UF_25V_1206

C165
.01UF_0402

SM BUS

C444
.1UF_0402

8P4R_10K_0804

16

INH
A
B

X
Y

X0
X1

VCC

X2
X3

Y0
Y1
Y2
Y3

GND

GND

7

8

ENDIM0

0

1 SO-DIMM1

0

X

12

12

C146

C143

.01UF_0402

.01UF_0402

12

C157
.01UF_0402

12

C156
.01UF_0402

+3V+3V

RP42

1 8

2 7

3 6

U36

1
5
2
4

12
14
15
11

74HC4052

4 5

Channel ONENDIM1

SO-DIMM0

Clock Generator

NONE

12

C418
.01UF_0402

12

+3V

12

C421
10UF_10V_1206

C149
1UF_25V_0805

RP44
8P4R_10K_0804

1 8

2 7

3 6

4 5

SCKDIMM0

SDADIMM0

SCKDIMM1 13
SCKCLK 11

SDACLK 11

RCAS#[0..7]9,13

MA[0..14]13

MD[0..63]13

JP28

1
MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

RCAS#0
RCAS#1

MA0
MA1
MA2

MD8
MD9
MD10
MD11

MD12
MD13
MD14

C427

12

@15PF_0402

CLK_SDRAM011 CKE0 9

PIR(14)

R325 @10_0402

12

SRASA#9,13

RMWEA#9,13

RAS#09
RAS#19

MD15

RMWEA#
RAS#0
RAS#1

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MA6
MA8

MA9
MA10

RCAS#2
RCAS#3

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

SDADIMM0

3

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

SO-DIMM144

RCAS#[0..7]

MA[0..14]

MD[0..63]

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU/CKE1

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0
A12/BA1

A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

VSS

VSS

VSS

VSS

RFU
RFU

RFU
VSS

VSS

VSS

VSS

VSS
SCL

+3V+3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

A3

32

A4

34

A5

36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104

A7

106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

1/20 ADD MMA14 LINK

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

RCAS#4
RCAS#5

MA3
MA4
MA5

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

MA14

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

MA7
MA11

MA12
MA13

RCAS#6
RCAS#7

MD56
MD57
MD58
MD59

MD60
MD61
MD62
MD63

SCKDIMM0

+3V +3V

SCASA# 9,13

12

12

12

R103
@10K_0402

R104
@10_0402

C150
@15PF_0402

PIR(14)

12

R102
@10K_0402

CLK_SDRAM1 11

CKE1 9

12

1 1

+3V

12

+3V

12

2 2

INHIB

CHANGE FROM

4.7K_0402 07/05

3 3

10K_0402

ENDIM021
ENDIM121

SMB_SB_CK7,20
SMB_SB_DA7,20 SDADIMM1 13

12

C148
1000PF_0402

C153
1000PF_0402

C151
1000PF_0402

C420
1UF_25V_0805

12

C154
1000PF_0402

12

C147
1000PF_0402

1 2

R365 10K_0402

+3V

12

12

R367

R336
10K_0402

INHIB

0

0

0

1

4 4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

E

F

Title

SCHEMATIC, M/B LA-1044

Size Document Number Rev

B

401196

*+,

-.

,

Date: Sheet

17, 2002

G

12 44

of

H

2A

A

B

C

D

E

SO-DIMM1 (Bank 2,3)

RCAS#[0..7]9,12

1 1

2 2

3 3

4 4

+3V

MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

MMA[0..14]9

MMD[0..63]9

12

C123
.1UF_0402

12

C106

4.7UF_25V_1206

12

C109
1UF_25V_0805

PIR(26)

12

C124
.1UF_0402

12

12

C115
.01UF_0402

MMA[0..14]

MMD[0..63]

12

C121
.01UF_0402

MMD32
MMD33
MMD34
MMD35

MMD36
MMD37
MMD38
MMD39

MMD40
MMD41
MMD42
MMD43

MMD44
MMD45
MMD46
MMD47

MMD48
MMD49
MMD50
MMD51

MMD52
MMD53
MMD54
MMD55

MMD56
MMD57
MMD58
MMD59

MMD60
MMD61
MMD62
MMD63

C125
.01UF_0402

12

C114
.01UF_0402

12

C110
.01UF_0402

RP34 8P4R_22_0804
4 5
3 6
2 7
1 8

RP19 8P4R_22_0804
1 8
2 7
3 6
4 5

RP18 8P4R_22_0804
1 8
2 7
3 6
4 5

RP17 8P4R_22_0804
1 8
2 7
3 6
4 5

RP13 8P4R_22_0804
4 5
3 6
2 7
1 8

RP11 8P4R_22_0804
4 5
3 6
2 7
1 8

RP9 8P4R_22_0804
4 5
3 6
2 7
1 8

RP25 8P4R_22_0804
4 5
3 6
2 7
1 8

12

C126
.01UF_0402

B

12

1UF_25V_0805

12

C111
.01UF_0402

C127

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

MD56
MD57
MD58
MD59

MD60
MD61
MD62
MD63

12

C107
10UF_10V_1206

CLK_SDRAM211 CKE2 9

RP31 8P4R_10_0804

MMA0

4 5

MMA1

3 6

MMA2

2 7

MMA3

1 8

RP16 8P4R_10_0804

MMA4

4 5

MMA5

3 6

MMA6

2 7

MMA7

1 8

RP29 8P4R_10_0804

MMA8

4 5

MMA9

3 6

MMA10

2 7

MMA11

1 8

RP15 8P4R_10_0804

MMA12

4 5

MMA13

3 6

MMA14 MA14

2 7
1 8

MA0
MA1
MA2
MA3

MA4
MA5
MA6
MA7

MA8
MA9
MA10
MA11

MA12
MA13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C105

12

@15PF_0402

MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

RCAS#0
RCAS#1

MA0
MA1

MD8
MD9
MD10
MD11

MD12
MD13
MD14

PIR(14)

R68

12

@10_0402

SRASA#9,12
RMWEA#9,12
RAS#29
RAS#39

C

MD15

RMWEA#
RAS#2
RAS#3

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MA6
MA8

MA9
MA10

RCAS#2
RCAS#3

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

12

+3V

12

+3V +3V +3V

12

MMD0
MMD1
MMD2
MMD3

MMD4
MMD5
MMD6
MMD7

MMD8
MMD9
MMD10
MMD11

MMD12
MMD13
MMD14
MMD15

MMD16
MMD17
MMD18
MMD19

MMD20
MMD21
MMD22
MMD23

MMD24
MMD25
MMD26
MMD27

MMD28
MMD29
MMD30
MMD31

A

12

C122
1000PF_0402

C119
1000PF_0402

C113
1000PF_0402

C128
1UF_25V_0805

12

C120
1000PF_0402

12

C112
1000PF_0402

RP20 8P4R_22_0804
1 8
2 7
3 6
4 5

RP33 8P4R_22_0804
4 5
3 6
2 7
1 8

RP32 8P4R_22_0804
4 5
3 6
2 7
1 8

RP36 8P4R_22_0804
4 5
3 6
2 7
1 8

RP26 8P4R_22_0804
4 5
3 6
2 7
1 8

RP12 8P4R_22_0804
4 5
3 6
2 7
1 8

RP10 8P4R_22_0804
4 5
3 6
2 7
1 8

RP24 8P4R_22_0804
4 5
3 6
2 7
1 8

MA[0..14]12

MD[0..63]12

JP17

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144_H5.6

RCAS#[0..7]

MA[0..14]

MD[0..63]

D

VSS
DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

VSS

CE4#
CE5#

VCC

VSS
DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

VSS

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

VSS

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

VSS
DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0

VSS

A12/BA1
A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

VSS
DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VSS

VCC

+3V+3V

2

MD32

4

MD33

6

MD34

8

MD35

10
12

MD36

14

MD37

16

MD38

18

MD39

20
22

RCAS#4

24

RCAS#5

26
28

MA3

30

A3
A4
A5

A7

SCL

MA4

32

MA5MA2

34
36

MD40

38

MD41

40

MD42

42

MD43

44
46

MD44

48

MD45

50

MD46

52

MD47

54
56
58
60

62
64
66
68

MA14

70
72
74
76
78
80
82

MD48

84

MD49

86

MD50

88

MD51

90
92

MD52

94

MD53

96

MD54

98

MD55

100
102

MA7

104

MA11

106
108

MA12

110

MA13

112
114

RCAS#6

116

RCAS#7

118
120

MD56

122

MD57

124

MD58

126

MD59

128
130

MD60

132

MD61

134

MD62

136

MD63

138
140
142
144

Title

Size Document Number Rev

B

*+,

Date: Sheet

12

SCASA# 9,12

12

R80
@10_0402

12

C129
@15PF_0402

R82
@10K_0402

12

R81
@10K_0402

CLK_SDRAM3 11

PIR(14)

SCKDIMM1 12SDADIMM112

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
401196

-.

,

17, 2002

E

CKE3 9

13 44

of

2A

A

1 1

RED10,35

GREEN10,35

BLUE10,35

HSYNC10

2 2

3 3

PIR(8)

4 4

VSYNC10

@10K_0402

CRTVDD

+5VS

+3VS

TVD[0..11]10

L36

1 2

TV@FBM_L10-201209-201LMT

TV@10UF_10V_1206

L19

1 2

TV@FBM_L10-201209-201LMT

TV@10UF_10V_1206

R35 4.7K_0402

1 2

R37 4.7K_0402

1 2

SPDAT110
SPCLK110

TVCLKR10
TVHS10

TVVS10 TVCLK 10

PCIRST#9,16,18,19,22,23,29,31,36

TVD[0..11]

12

R8
75_1%

12

R3

C241

C75

TVD7
TVD6
TVD5
TVD4
TVD3
TVD2
TVD1
TVD0

TV@10_0402

12

12

12

12

R49

R6
75_1%

R22
@10K_0402

CRT Connector

12

12

C13

R9
75_1%

@22PF_0402

Q3
2N7002

1 2

+12VS

R10 100K_0402

12

C238
TV@.1UF_0402

12

C81
TV@.1UF_0402

312530516

26

SD

27
39
40

41

6
4
3
2

1
44
43
42

29

12

12

C86
TV@15PF_0402

SC
XCLK
H

V
D7

D6
D5
D4
D3
D2
D1
D0

RESETB

AVDD

AGND

3423198183628

S

VDD

CH7005

GND

G

GND

12

C10
@22PF_0402

D

13

2

Q6
2N7002

DVDD

DVDD

DGND

DGND

S

DVDD

DGND

G

38

DVDD

DGND

B

2

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

1 2

FCM2012C-800_0805

12

C12
@22PF_0402

1 2

FBM-11-160808-121

D

1 2

13

FBM-11-160808-121

12

C223
TV@.1UF_0402

U22

CVBS/B

Y/R

C/G

CSYNC

BCO

P-OUT

XO/FIN

D10
D11
D12
D13
D14
D15

RSET

TV@CH7005

L1

L2

L3

L4

L16

12

20
22
21

17
35
37

33
32

XI

7

D8

9

D9

10
11
12
13
14
15

24

D1

DAN217

2

12

C4
18PF_0402

C222

TV@FBM_L10-201209-201LMT

TV@10UF_10V_1206

COMPS
LUMA
CRMA

1

1 2
R43 TV@0_0402
14M_TV1
14M_TV2

TVD8
TVD9
TVD10
TVD11

12

R179
TV@360

C

+5VS

F1

POLYSWITCH_0.5A

D2

DAN217

3

12

C8
68PF_0402

12

2

12

C6
18PF_0402

COMPS 35
LUMA 35
CRMA 35

12

C84
TV@15PF_0402

1

12

+3VS

14M_TV2

12

1

L18

TP1

Notes : If Rx mount, remove Yx/Cx, and

D3

CRTVDD

DAN217

1

3

2

3

12

C3
18PF_0402

C40
68PF_0402

1 2

TV@14.318MHZ

C248
TV@10PF_0402

Y3

100PF_0402

LUMA

CRMA

COMPS

TV@75_1%

14M_TV1

Cx change to 0_0603 resister.

2 1

RB411D

MSEN#31,35

DDC_MD2

12

C7

12

R173

1 2

R185 @0_0402

12

C247
TV@10PF_0402

D4

12

C39

.1UF_0402

12

C5

220PF_0402

DOCK_VSYNC 35

DOCK_HSYNC 35

12

12

R175

TV@75_1%

12

C9
220PF_0402

R178

TV@75_1%

14.318M_TV 11

W=40mils

12

C33
TV@150PF_0402

Q1
2N7002

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

D

1 3

12

D

R24

2.2K_0402

JP3
CRT-15P

Q5
2N7002

D

S

1 3

S

G

2

G

2

1 2

R25 100K_0402

1 2

C30 TV@47PF_0402

L6

1 2

TV@FBM-11-160808-121

1 2

C29 TV@47PF_0402

L5

1 2

TV@FBM-11-160808-121

C34
TV@150PF_0402

12

12

DOCK_DDCD 35
DOCK_DDCC 35

12

C227
TV@150PF_0402

R11

2.2K_0402

CRTVDD

DDCDATA 10

DDCCLK 10

+12VS

12

C26
TV@270PF_0402

E

CRT Conn./TV Encoder

TV-Out Connector

S-Video

JP5

1
2
3
4
5
6
7

TV@S CONN._FOXCONN

12

C27
TV@270PF_0402

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

B

401196

*+,

-.

,

17, 2002

14 44

E

2A

of