Compal JBL00, E6400 Laptop Schematics

A

B

COMPAL CONFIDENTIAL

C

D

E

1 1

PCB NO :
BOM P/N :

LA-3801P ( DA800009P1L)
43152331L01

MODEL NAME :

JBL00

M09 Roush UMA

2 2

uFCPGA Mobile Penryn

Intel Cantiga GM + ICH9M

2008-06-12

REV : 1.0(A00)

@ : Nopop Component

3 3

1@ : Use PCMCIA card only
2@ : Use Express card only
3@ : Use ATG only
4@ : Use China TPM only
5@ : Use BROADCOM TPM only
6@ : All TPM Disabled for CCC - Depop D70, Pop R483

4 4

MB PCB

Part Number Description

DA800009P0L

A

PCB 03I LA-3801P REV0 M/B UMA

B

7@ : Non- ATG only

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3801P

166Thursday, June 12, 2008

E

0.8

of

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B

C

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E

Block Diagram
Compal confidential
Model : JBL00

FAN

CRT CONN

+5V_RUN

+FAN1_VOUT

1 1

RGB

DP CONN

+5V_RUN

2 2

DOCKING

page 18 page6page 7

page 20

RGB

SVID

page 21

DPB

DPB

LVDS CONN

+PWR_SRC
+5V_ALW
+3.3V_RUN

page 19

PORT

page 35

DAI

USB[8,9]

SATA5

DOCK LPC BUS

+3.3V_RUN/ +1.5V_RUN 100MHz

PCIE3 PCIE2 PCIE1

Mini Card3

WPAN/BT/Robson

+3.3V_RUN
+1.5V_RUN

3 3

page 34

SD/MMC

CONN

+3.3V_RUN

page 31

PCI Express BUS

Mini Card2

WLAN

+3.3V_WLAN
+1.5V_RUN +1.5V_RUN

page 34 page 34

USB[4] USB[5]USB[6]

Smart Card

page 36

RFID

page 36

Trough Cable

Biometric

1.8V/1.25V/0.9V

4 4

page 52

VCORE (IMVP-6)

page 47

CHARGER

page 48 page 43

1.5V/1.05V

A

+3.3V_RUN

BATT IN3V/5V

DC IN DC/DC Interface

page 45

Thermal

GUARDIAN III
EMC4002

+3.3V_SUS

Vedio Switch
TS3DV520ERHUR

+3.3V_RUN

DP Switch
TS2DP512

+5V_RUN_DP

PCI BUS

IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)

CardBus

R5C847

+3.3V_RUN

Mini Card 1

+3.3V_RUN

+5V_RUN
+3.3V_RUN

page 33

page 31,32

USB[7]

WWAN

73S8009CN

page 36

USBH

page 43page 44

page 18

page 20

page 21

+3VRUN 33MHz

Trough Cable

USH

+3.3V_RUN
+2.5V_RUN
+1.2V_RUN

Touch Pad

page 39

Power Sequence

Power On/Off
SW & LED

B

RGB

SVID

DPB

DPC

LVDS

IEEE1394

page 42

Option

TPM1.2

For China

TPM1.2
SSX35BCB
BCM5880

page 36

USB[10]

SMBUS

Stick

page 41

page 42

Pentium-M

+1.5V_RUN
+1.05V_VCCP
+VCC_CORE

H_A#(3..35) H_D#(0..63)

Penryn -4MB (Socket P)

uFCPGA CPU

478pin

System Bus

FSB 800/1066 MHz

INTEL

+3.3V_RUN
+1.8V_MEM
+1.5V_RUN
+VCC_GFXCORE
+1.05V_M
+1.05V_VCCP

Cantiga

1329pin BGA

page 10,11,12,13,14,15

DMI

+1.5V_RUN
100MHz

+RTC_CELL
+3.3V_ALW_ICH
+3.3V_RUN
+1.5V_RUN
+1.05V_VCCP

LPC BUS

+3V_RUN
33MHz

INTEL

ICH9-M

676pin BGA

page 22,23,24,25

SPI

W25X32VSSIG

+3.3V_M

32M 4K sector

SMSC KBC
MEC5035

+RTC_CELL
+3.3V_ALW

page 38

DOCK LPC BUS

BC BUS

ECE1077

+3.3V_ALW

page 39

Int.KBD &

page 39

Stick

page 40

C

page 7,8,9

page 24

BC BUS

CPU ITP Port

+1.05V_VCCP

Memory BUS
(DDR2)

48MHz USB0 : Right side pair top

GLCI/LCI

Azalia I/F

S-ATA 0/1/4/5

E-Module

+5V_MOD

+1.8V_MEM 533 / 667MHz

USB[11]

SATA4

USB[2,3] L SIDE

USB[0,1] R SIDE

SATA1 SATA0

S-HDD

+5V_HDD
+3.3V_RUN

page 26

page 26

Camera

+5V_RUN

E-SATA

USB Ports X2

+5V_ALW

USB Ports X2

+5V_ALW

+3V_RUN/ +1.5V_RUN 100MHz

Azalia Codec

92HD71B

+3.3V_RUN
+VDDA

SMSC SIO

ECE5028

+3.3V_ALW

page 37

MDC

+3V_SUS

page 26

On IO/B

RJ11

Trough Cable

D

Clock Generator
CK505
SLG8LP554

+3.3V_M

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.8V_MEM
+0.9V_DDR_VTT

page 19

page 33

page 26

page 16,17

Trough LVDS Cable

USB2 : Left side pair top
USB3 Rear Right pair bottom

USB1 : Right side pair bottom

On IO/B

Intel Boaz
82567LM

+3.3V_ALW
+1.8V_LAN_M

page 27

AMP & INT.
Speaker

+5V_RUN

page 28

HeadPhone &
MIC Jack

+3.3V_RUN

page 26

+1V_LAN_M

page 29

LAN SWITCH
PI3L500-AZFEX

+3.3V_ALW

RJ45

page 26

SNIFFER

DAI

SSM2602

+3.3V_RUN

page 27

DOCK

Dig. MIC

page 19

Trough LVDS Cable

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram
LA-3801P

266Thursday, June 12, 2008

E

pg 30

On IO/B

0.8

of

5

4

3

2

1

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW HIGH HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP
S5#

HIGH

S4
STATE#

SLP
M#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

CLOCKS

ICH9-M

USB PORT#

0
1
2
3
4
5
6
7

DESTINATION
JUSB1 (Ext Right Side Top)
JUSB1 (Ext Right Side Bottom)
JESA1 (Ext Left Side Top)
JESA1 (Ext Left Side Bottom)
WLAN
WWAN
WPAN
Card Bus/Express card
DOCKING8

C C

PM TABLE

State

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW_ICH
+3.3V_RTC_LDO

+3.3V_SUS
+1.8V_MEM

+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.9V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP

+3.3V_M +3.3V_M
+1.05V_M +1.05V_M

(M-OFF)

PCI EXPRESS

Lane 1

ON

ON

ON

ON

OFF

OFF

OFFOFF

Lane 2
Lane 3
Lane 4
Lane 5

S0

S3

B B

S5 S4/AC

S5 S4/AC don't exist

ON

ON

ON ON

ON

OFF

OFFOFF

OFFON

OFF

OFF

9

11

DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
MINI CARD-3 BT/UWB
EXPRESS CARD
None

DOCKING
USH->BIO10
Camera

Lane 6

10/100/1G LAN

PCI TABLE

REQ#/GNT#

R5C847 REQ#1 / GNT#1AD17

A A

PIRQPCI DEVICE IDSEL

PIRQ[B..D]

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Index and Config.

LA-3801P

366Thursday, June 12, 2008

1

0.8

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5

4

3

2

1

RUN_ON

FDS4435

Q16

+INV_PWR_SRC

ADAPTER

D D

GFX_CORE_ON

ADP3209

(PU15)

+VGFX_COREP

+PWR_SRC

BATTERY

CHARGER

C C

ALW_ON

3.3V_SUS_ON

ISL6236

(PU2)

STS11NF30L

(Q60)

ISL6260

(PU7)

IMVP_VR_ON

+VCC_CORE

ISL88550

(PU16)

DDR_ON

0.9V_DDR_VTT_ON

+1.8V_MEM +0.9V_DDR_VTT

ISL6236

(PU3)

M_ON

1.5V_RUN_ON

+1.05V_M +1.5V_RUN

ISL6236

(PU2)

ALWON

ALWON

+5V_ALW

+3.3V_ALW

ENAB_3VLAN

STS11NF30L

RUN_ON

3.3V_RUN_ON

(Q44)

+15V_ALW

+5V_RUNSTS11NF30L

(Q55)

SI4336DY

(Q61)

+5V_ALW

B B

+3.3V_SUS

+3.3V_LAN

+3.3V_RUN

EMC4002
LDO Out

HDDC_EN

MODC_EN

RUN_ON

REGCTL_PNP1

REGCTL_PNP18

(U3)

BCP69 BCP69

SI3456BDVSI3456BDV

(Q29)(Q32)

MAX9789A

(U22)

(Q46)

(Q45)

+1.8V_RUN

A A

+5V_HDD

+5V_MOD

+VDDA

+1V_LAN_M +1.8V_LAN_M

DELL CONFIDENTIAL/PROPRIETARY

On IO/B

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Power Rail
LA-3801P

466Thursday, June 12, 2008

1

0.8

of

5

G16

ICH_SMBCLK
ICH_SMBDATA

A13

ICH9-M

D D

C17
B18

AMT_SMBCLK
AMT_SMBDAT

2.2K

2.2K

10K

10K

4

+3.3V_ALW

+3.3V_ALW_ICH

2N7002
2N7002

MEM_SCLK

MEM_SDATA

3

2.2K

2.2K

+3.3V_M

197
195

DIMMA

197
195

DIMMB

SMBUS Address [TBD]

SMBUS Address [TBD]

2

1

2.2K

9493

2A 2A

C C

6

5

8
7

DOCK_SMB_CLK
DOCK_SMB_DAT

LCD_SMBCLK
LCD_SMDATA

1A

1A

1B
1B

2.2K

2.2K

2.2K

+3.3V_ALW

+3.3V_ALW

6

5

6

5

DOCKING

INVERTER
(JLVDS)

SMBUS Address [TBD]

SMBUS Address [TBD]

2.2K

PBAT_SMBCLK

112

10
9

100
99

98
97

PBAT_SMBDAT

CARD_SMBCLK
CARD_SMBDAT

KBC

B B

1C1C111

1D
1D

1E
1E

1F
1F

2.2K

2.2K

2.2K

MEC 5035

96

1G

95

1H

2.2K

12

13

CKG_SMBDAT

CKG_SMBCLK

1H

1H

2.2K

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

100 ohm
100 ohm

3

BATTERY

4

CONN

2N7002
2N7002

SMBUS Address [TBD]

2.2K

2.2K
CLK_SDATA

CLK_SCLK

+3.3V_M

17

16

CLK GEN

2N7002
2N7002

2N7002
2N7002

2N7002
2N7002

32

WWAN

SMBUS Address [TBD]

2.2K

2.2K

EXP_SMBCLK
EXP_SMBDATA

2.2K

2.2K

WLAN_SMBCLK
WLAN_SMBDATA

2.2K

2.2K

MINI_SMBCLK
MINI_SMBDATA

30

SMBUS Address [TBD]

+3.3V_SUS

7
8

Express card

+3.3V_WLAN

30
32

WLAN

+3.3V_RUN

30
32

BT/UWB

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

A A

5

106

1J

105

1J

1K
1K

Dedicated JTAG

103
102

Dedicated JTAG

9

Charger

10

SMBUS Address [TBD]

2N7002
2N7002

DAI

SMBUS Address [TBD]

4

3

USH

SMBUS Address [TBD]

2.2K

2.2K

+3.3V_RUN

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SMBUS TOPOLOGY
LA-3801P

566Thursday, June 12, 2008

1

0.8

of

5

+3.3V_M

1 2

R3

@

0_0402_5%~D

CKG_SMBDAT<27,38,48>

D D

CKG_SMBCLK<27,38,48>

FSC FSB FSA CPU

CLKSEL2 CLKSEL0CLKSEL1

000

*

00

1

0

11

C C

0

1

1

0

11

+3.3V_M

12

R51

@

10K_0402_5%~D

FSA

12

R55

@

10K_0402_5%~D

B B

+3.3V_RUN

10K_0402_5%~D

R43

1 2

PCI_DOCKING

+3.3V_RUN

10K_0402_5%~D

R46

1 2

+3.3V_RUN

10K_0402_5%~D

@

R50

1 2

A A

PCI_SIO

10K_0402_5%~D

12

R54

PCI_ICH

*

*

*

6 1

Q1A
2N7002DW-7-F_SOT363-6~D

+3.3V_M

1

0

00

1

0

TME

ITP_EN

2
5

Q1B
2N7002DW-7-F_SOT363-6~D

3

4

1 2

R9

@

0_0402_5%~D

SRC

MHz

MHz

100

266

100

133

100

200

100

166

100

333

100

100

100

400

PIN 32

0

overclocking enabled

1

overclocling disabled

PIN 37

0

Pin 5/6 as SRC_10

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

33.3

1 Pin 5/6 as CPU_ITP

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0=UMA

1=DIS

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

2.2K_0402_5%~D

12

R1

Place crystal within
500 mils of CK505

12

2.2K_0402_5%~D

R2

CLK_SDATA

CLK_SCLK

CLK_ICH_48M<24>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>

CPU_MCH_BSEL2<8,10>

CLK_PCI_5028<37>

CLK_PCI_TPM_CHA<29>

CLK_PCI_DOCK<35>

CLK_PCI_5035<38>

CLK_ICH_14M<24>
CLK_SIO_14M<37>
MCH_DREFCLK<10>
MCH_DREFCLK#<10>

CLK_PCI_ICH<22>

CLK_PCI_PCM<31>
CLK_PCI_TPM<36>

CLK_PWRGD<24>

0=UMA
1=Disc. GRFX down

5

4

1 2

0.1U_0402_16V4Z~D
L1

1

2

4.7U_0603_6.3V4Z~D

0.047U_0402_16V4Z~D

1

1

@

C11

C12

2

2

X1

14.31818MHz_20P_1BX14318CC1A~D

12

C16

33P_0402_50V8J~D

C17

33P_0402_50V8J~D

12

CLK_ICH_48M FSA
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_PCI_PCM
CLK_PCI_TPM_CHA

CLK_PCI_5035 PCI_EC
CLK_ICH_14M
CLK_SIO_14M
MCH_DREFCLK
MCH_DREFCLK#

CLK_PWRGD

4

BK2125HS601-T 0805~D

C1

+CK_VDD_MAIN2

1 2

L2

@

BLM21PG600SN1D_0805~D

+CK_VDD_REF+CK_VDD_48

0.047U_0402_16V7K~D

1

C13

2

12

R17 0_0402_5%~D

1 2

5.2

R19 33_0402_5%~D
R22 2.2K_0402_5%~D
R1044 0_0402_5%~D

R24 10K_0402_5%~D

R26 33_0402_5%~D
R30 22_0402_5%~D
R29 22_0402_5%~D5@
R854 22_0402_5%~D4@
R27 33_0402_5%~D

R32 33_0402_5%~D
R33 22_0402_5%~D
R35 22_0402_5%~D
R37 33_0402_5%~D
R38 33_0402_5%~D

R41 33_0402_5%~D

1 2
1 2

1 2

1 2

1 2
1 2
1 2
1 2

12

12
12
12

12
12

12

1 2

R12 0_0603_5%~D

1 2

R14 0_0603_5%~D

+CK_VDD_MAIN+3.3V_M

0_0805_5%~D

1 2

3

+CK_VDD_MAIN

1

R851

2

1

2

+CK_VDD_REF
+CK_VDD_48

CLK_XTAL_IN

CLK_XTAL_OUT

FSB
FSC

PCI_SIOCLK_PCI_5028
PCI_TPMCLK_PCI_TPM
PCI_DOCKINGCLK_PCI_DOCK

CLKREF

DOT96
DOT96#

PCI_ICHCLK_PCI_ICH

CLK_SCLK

CLK_SDATA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

C3

C2

2

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1

@

C9

C8

2

1 2

R10 2.2_0603_5%~D

U1

1

VDD_SRC

49

VDD_SRC

54

VDD_SRC

65

VDD_SRC

30

VDD_PCI

36

VDD_PCI

12

VDD_CPU

18

VDD_REF

40

VDD_48

20

XTAL_IN

19

XTAL_OUT

41

USB_48MHz/FSLA

45

FSL_B/TEST_MODE

23

REF_0/FSL_C/TEST_SEL

34

PCICLK4/FCT_SEL

33

PCICLK3

32

PCICLK2/TME

27

PCICLK1

22

REF_1

43

DOT_96/27M

44

DOT_96#/27M_SS

37

PCICLK_F0/ITP_EN

39

CKPWRGD/PD#

9

NC

16

SMBCLK

17

SMBDAT

4

VSS_SRC

15

VSS_CPU

21

VSS_REF

31

VSS_PCI

35

VSS_PCI

42

VSS_48

68

VSS_SRC

73

THRM_PAD

SLG8LP554VTR_QFN72_10X10~D

1

2

1

2

SLG8LP554VTR

0.1U_0402_16V4Z~D

C4

0.1U_0402_16V4Z~D

C10

0.1U_0402_16V4Z~D

1

C5

2

+CK_VDD_A

PCI_STP#

CPU_STP#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

CLKREQ_9#

CLKREQ_8#

CLKREQ_7#

CLKREQ_6#

CLKREQ_5#

CLKREQ_4#

CLKREQ_3#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

1

2

VDD_A
VSS_A

CPU_1

CPU_1#

CPU_0

CPU_0#

SRC_9

SRC_9#

SRC_8

SRC_8#

SRC_7

SRC_7#

SRC_6

SRC_6#

SRC_5

SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

0.1U_0402_16V4Z~D

C6

7
8

25
24

11
10

14
13

6
5

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48

2

0.1U_0402_16V4Z~D

1

C7

2

0.047U_0402_16V4Z~D

4.7U_0603_6.3V4Z~D

1

1

2

H_STP_PCI#
H_STP_CPU#

MCH_BCLK CLK_MCH_BCLK
MCH_BCLK#

CPU_BCLK
CPU_BCLK#

CPU_ITP
CPU_ITP#

PCIE_MINI1
PCIE_MINI1#
MINI1CLK_REQ#
PCIE_MINI2
PCIE_MINI2#
MINI2CLK_REQ#
PCIE_ICH
PCIE_ICH#

MINI3CLK_REQ#

PCIE_EXP#
EXPCLK_REQ#
MCH_3GPLL

CLK_3GPLLREQ#_R

PCIE_SATA CLK_PCIE_SATA
PCIE_SATA#
SATA_CLKREQ#_R
DOT96_SSC
DOT96_SSC#

2

C15

C14

2

1 2

R11 33_0402_5%~D

1 2

R13 33_0402_5%~D

1 2

R15 33_0402_5%~D

1 2

R16 33_0402_5%~D

1 2

R18 33_0402_5%~D@

1 2

R21 33_0402_5%~D@

1 2

R23 33_0402_5%~D

1 2

R25 33_0402_5%~D

1 2

R28 33_0402_5%~D

1 2

R31 33_0402_5%~D

1 2

R34 33_0402_5%~D

1 2

R36 33_0402_5%~D

1 2

R39 33_0402_5%~D

1 2

R40 33_0402_5%~D

1 2

R408 33_0402_5%~D

1 2

R415 33_0402_5%~D

1 2

R45 33_0402_5%~D

1 2

R47 33_0402_5%~D

1 2

R48 475_0402_1%~D

1 2

R49 33_0402_5%~D

1 2

R52 33_0402_5%~D

1 2

R53 475_0402_1%~D

1 2

R523 33_0402_5%~D

1 2

R670 33_0402_5%~D

CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_ITP
CLK_CPU_ITP#

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_MINI3PCIE_MINI3
CLK_PCIE_MINI3#PCIE_MINI3#

CLK_PCIE_EXPPCIE_EXP
CLK_PCIE_EXP#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#MCH_3GPLL#
CLK_3GPLLREQ#

CLK_PCIE_SATA#

1

+3.3V_RUN

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
MINI3CLK_REQ#
EXPCLK_REQ#

H_STP_PCI# <24>

H_STP_CPU# <24>

CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>

CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>

CLK_PCIE_MINI1# <34>

MINI1CLK_REQ# <34>

CLK_PCIE_MINI2 <34>
CLK_PCIE_MINI2# <34>

MINI2CLK_REQ# <34>

CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>

CLK_PCIE_MINI3 <34>
CLK_PCIE_MINI3# <34>

MINI3CLK_REQ# <34>

CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>

EXPCLK_REQ# <32>
CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

CLK_3GPLLREQ# <10>

CLK_PCIE_SATA <23>

CLK_PCIE_SATA# <23>

SATA_CLKREQ# <24>
DREF_SSCLK <10>
DREF_SSCLK# <10>

1 2

R4 10K_0402_5%~D

1 2

R5 10K_0402_5%~D

1 2

R6 10K_0402_5%~D

1 2

R7 10K_0402_5%~D

1 2

R8 10K_0402_5%~D

1 2

R356 10K_0402_5%~D

CLK_PCIE_MINI1 <34>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Clock Generator
LA-3801P

666Thursday, June 12, 2008

1

of

0.8

5

4

3

2

1

H_A#[3..35]<10>

D D

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

C C

H_ADSTB#1<10>

H_A20M#<23>

H_FERR#<23>

H_IGNNE#<23>
H_STPCLK#<23>

H_INTR<23>
H_NMI<23>
H_SMI#<23>

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2

H_REQ#4
H_A#17

H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25 ITP_TCK
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JCPU1A

J4

ADDR GROUP_0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

ADDR GROUP_1

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4
AB2
AA3

V1
A6

A5

C4
D5

C6

B4
A3

M4
N5

T2
V3
B2

D2

D22

D3

F6

THERMAL

A[33]#
A[34]#

PROCHOT#

A[35]#
ADSTB[1]#

ICH

A20M#
FERR#

THERMTRIP#

IGNNE#
STPCLK#

LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

RESERVED

TYCO_1-1674770-2_Penryn~D

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#H_REQ#3

G2

H_HIT#

G6

H_HITM#

E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1
AC5

ITP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

EC_CPU_PROCHOT#

H_THERMTRIP#
CLK_CPU_BCLK

CLK_CPU_BCLK#

R1104 0_0402_5%~D
R1105 0_0402_5%~D
R1106 0_0402_5%~D
R1107 0_0402_5%~D
R1108 0_0402_5%~D

H_THERMDA

H_THERMDC

H_ADS# <10>

H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>
H_DRDY# <10>

H_DBSY# <10>

H_BR0# <10>

H_INIT# <23>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_TRDY# <10>

H_HIT# <10>

H_HITM# <10>

1 2
1 2
1 2
1 2
1 2

ITP_DBRESET# <24>

2

C18

@

100P_0402_50V8K~D

1

H_THERMTRIP# <18>

CLK_CPU_BCLK <6>

CLK_CPU_BCLK# <6>

R1103 0_0402_5%~D@

1 2

R780 0_0402_5%~D@

1 2

R59
56_0402_5%~D

+1.05V_VCCP

+1.05V_VCCP

R781 0_0402_5%~D@

1 2

R782 0_0402_5%~D@

1 2

R783 0_0402_5%~D@

1 2

R784 0_0402_5%~D@

1 2

R785 0_0402_5%~D@

1 2

R57 124_0402_1%~D

1 2

R1111 0_0402_5%~D@

1 2

CLK_CPU_ITP
CLK_CPU_ITP#

R58 22.6_0402_1%~D

1 2

R1109 0_0402_5%~D@

1 2

R1112 0_0402_5%~D@

1 2

R1113 0_0402_5%~D@

1 2

1 2

R61 56_0402_5%~D

1 2

R912 51_0402_5%~D@

R56

56_0402_5%~D

12

+1.05V_VCCP

CLK_CPU_ITP<6>
CLK_CPU_ITP#<6>

+1.05V_VCCP

12

H_THERMDA <18>

H_THERMDC <18>

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_THERMTRIP#

ITP_BPM#5

Place close to CPU within 200 mil

+1.05V_VCCP

ITP_DBRESET#R
ITP_BPM#0R
ITP_BPM#1R
ITP_BPM#2R
ITP_BPM#3R
ITP_BPM#4R
ITP_BPM#5R

H_RESET#R
ITP_TCK_R

ITP_TDO_R
ITP_TCK_R
ITP_TRST#R

ITP_TMS_R
ITP_TDI_R

+3.3V_ALW_ICH

R60 150_0402_5%~D

+1.05V_VCCP

+1.05V_VCCP

1

2

Place near JITP

1 2

1 2

R62 56_0402_5%~D
R63

@

1 2

R64 39_0402_5%~D

1 2

R67 27_0402_5%

Place close to JITP within 200ps = 1000 mil

+1.05V_VCCP

29

JITP1

28

VTT1

27

GND6

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

GND7

MOLEX_52435-2891_28P~D

30

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C20

C19

2

ITP_DBRESET#

ITP_TDO
H_RESET#

51_0402_1%~D

ITP_TMS

This shall place near CPU

ITP_TCK

JCPU1D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3
E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

TYCO_1-1674770-2_Penryn~D

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

1 2

R65 150_0402_5%~D

1 2

R66 649_0402_1%~D

A A

Place close to CPU within 200ps = 1000 mil

ITP_TDI

ITP_TRST#

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Penryn Processor(1/2)
LA-3801P

766Thursday, June 12, 2008

1

0.8

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

1 2

A A

1K_0402_5%~D

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

@

R72

H_D#[0..63]<10>

+V_CPU_GTLREF

@
@

@

1K_0402_5%~D

@

R73

1 2

H_DSTBN#0<10>

H_DSTBP#0<10>

H_DSTBN#1<10>

H_DSTBP#1<10>

H_DINV#0<10>

H_DINV#1<10>

T1PAD~D
T138PAD~D

T4PAD~D

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21

H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

TEST7

R1041 0_0402_5%~D
R1042 0_0402_5%~D
R1043 0_0402_5%~D

TEST1
TEST2

JCPU1B

E22

D[0]#

F24

D[1]#

E26

G22

F23

G25

E25
E23
K24

G24

J24
J23
H22
F26
K22
H23

J26
H26
H25

N22

K25

P26

R23

L23
M24

L22
M23

P25

P23

P22

T24
R24

L25

T25
N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1

A26

C3

1 2
1 2
1 2

@
@

B22

B23
C21

T2PAD~D
T3PAD~D

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

FSB

BCLK BSEL2 BSEL1 BSEL0

533

133

667

166

800

200

DATA GRP 0

D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#

DATA GRP 1

D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

TYCO_1-1674770-2_Penryn~D

TEST3
TEST5

001

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#

DATA GRP 2DATA GRP 3

D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

100

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

110

1067 266 0 0 0

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54H_D#22
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

+V_CPU_GTLREF

H_DPRSTP# <10,23,47>

H_DPSLP# <23>

H_DPWR# <10>

H_PWRGOOD <23>

H_CPUSLP# <10>

H_PSI# <47>

+1.05V_VCCP

12

R77
1K_0402_1%~D

12

R78
2K_0402_1%~D

H_DSTBN#2 <10>
H_DSTBP#2 <10>

H_DINV#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>

H_DINV#3 <10>

54.9_0402_1%~D

12

R68

Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.

12

12

R69

12

R70

54.9_0402_1%~D

27.4_0402_1%~D

27.4_0402_1%~D
R71

JCPU1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

TYCO_1-1674770-2_Penryn~D

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]

V6

VCCP[02]

J6

VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

1

+

2

Length match within 25 mils, Z0=27.4 ohm

Place R75 and R76 near CPU

+VCC_CORE

1 2

R75 100_0402_1%~D

1 2

R76 100_0402_1%~D

Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spacing and R75 & R76
keep to pad max 1 inch

+1.05V_VCCP

220U_D2_4VY_R15M~D

C21

CRB was 270uF

VID0 <47>
VID1 <47>
VID2 <47>
VID3 <47>
VID4 <47>
VID5 <47>
VID6 <47>

VCCSENSE <47>

VSSSENSE <47>

VCCSENSE=18 mils

VCCSENSE

VSSSENSE

10U_0805_10V4Z~D

0.01U_0402_16V7K~D

+1.5V_RUN

1

1

C23

C22

2

2

1 2

R833 27.4_0402_1%~D@

Reserve for testing
only

DELL CONFIDENTIAL/PROPRIETARY

Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Penryn Processor(2/2)
LA-3801P

866Thursday, June 12, 2008

1

0.8

of

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side

D D

C C

Secondary)

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C24
10U_0805_4VAM~D

C34
10U_0805_4VAM~D

C44
10U_0805_4VAM~D

C50
10U_0805_4VAM~D

1

C25
10U_0805_4VAM~D

2

1

C35
10U_0805_4VAM~D

2

1

C45
10U_0805_4VAM~D

2

1

C51
10U_0805_4VAM~D

2

4

1

C26
10U_0805_4VAM~D

2

1

C36
10U_0805_4VAM~D

2

1

C46
10U_0805_4VAM~D

2

1

C52
10U_0805_4VAM~D

2

1

C27
10U_0805_4VAM~D

2

1

C37
10U_0805_4VAM~D

2

1

C47
10U_0805_4VAM~D

2

1

C53
10U_0805_4VAM~D

2

1

C28
10U_0805_4VAM~D

2

1

C38
10U_0805_4VAM~D

2

1

C48
10U_0805_4VAM~D

2

1

C54
10U_0805_4VAM~D

2

1

C29
10U_0805_4VAM~D

2

1

C39
10U_0805_4VAM~D

2

1

C49
10U_0805_4VAM~D

2

1

C55
10U_0805_4VAM~D

2

3

1

C30
10U_0805_4VAM~D

2

1

C40
10U_0805_4VAM~D

2

1

C31
10U_0805_4VAM~D

2

1

C41
10U_0805_4VAM~D

2

1

2

1

2

2

C32
10U_0805_4VAM~D

C42
10U_0805_4VAM~D

1

C33
10U_0805_4VAM~D

2

1

C43
10U_0805_4VAM~D

2

1

10uF 0805 X6S -> 85 degree C

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

270U_X_2VM_R4.5M~D

270U_X_2VM_R4.5M~D

1

+

@

C59

2

270U_X_2VM_R4.5M~D

1

North Side Secondary

+

@

@

C60

C61

2

ESR <= 1.5m ohm

South Side Secondary

270U_X_2VM_R4.5M~D

1

1

+

+

2

C57

C56

2

1

1

+

+

C58

2

2

270U_X_2VM_R4.5M~D

270U_X_2VM_R4.5M~D

Capacitor > 1320uF

B B

+1.05V_VCCP

1

C62

0.1U_0402_10V7K~D

2

A A

1

C63

0.1U_0402_10V7K~D

2

1

C64

0.1U_0402_10V7K~D

2

1

C65

0.1U_0402_10V7K~D

2

1

C66

0.1U_0402_10V7K~D

2

1

C67

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CPU Bypass

LA-3801P

966Thursday, June 12, 2008

1

0.8

of

5

+15V_ALW

100K_0402_5%~D

2

R1120

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

12

61

F2
G8

F8
E6
G2
H6
H2

F6
D4
H3
M9

M11

J1

J2

N12

J6
P2

L2
R2
N9

L6
M5

J3
N2
R1
N5
N6

P13

N8

L7

N10

M3
Y3

Y6

Y10
Y12
Y14

Y7

W2

AA8

Y9

AA9

AE9
AA2
AD8
AA3
AD3
AD7

AF3
AC1
AE3
AC3

AE8
AG2
AD6

C5
E3

C12

E11

A11
B11

2N7002DW-7-F_SOT363-6~D

U2A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA ES_FCBGA1329~D

ICH_AZ_MCH_BITCLK<23>
ICH_AZ_MCH_RST#<23>
ICH_AZ_MCH_SDOUT<23>
ICH_AZ_MCH_SYNC<23>
ICH_AZ_MCH_SDIN2<23>

+3.3V_ALW

Q153

SI3456BDV-T1-E3_TSOP6~D

+3.3V_RUN_D

D

6

S

2
1

G

3

Q153_GATE

470K_0402_5%~D

12

@

Q154A

R1121

1

2

45

100P_0402_50V8J~D

H_D#[0..63]<8>

D D

+1.05V_VCCP

12

R91
221_0402_1%~D

H_SWNG

100_0402_1%~D

C C

+H_VREF

B B

+3.3V_ALW +3.3V_RUN_D

A A

2N7002DW-7-F_SOT363-6~D

0.1U_0402_16V7K~D

12

R95

1

C74

2

+1.05V_VCCP

12

R90
1K_0402_1%~D

0.1U_0402_16V7K~D

2K_0402_1%~D

12

1

R94

2

1 2

R82 24.9_0402_1%~D

H_RESET#<7>

H_CPUSLP#<8>

@

Q155

NTR4003NT1G_SOT23-3

D

1 3

G

2

Q153_GATE

Q154B

ICH_PWRGD<24,41>

S

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

@

C73

H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
+H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

+3.3V_ALW2

100K_0402_5%~D

12

R1119

3

5

4

5

HOST

0.1U_0402_16V4Z~D

ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
ICH_AZ_MCH_SDIN2

10K_0402_5%~D

12

R1122

8.2K_0402_5%~D

12

R1123

C1049

+3.3V_RUN

H_ADSTB#_0
H_ADSTB#_1

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

+3.3V_RUN_D

C1046

1 2

@

0_0603_5%~D

U67_OD_DELAY

MCH_TSATN#

4

SDVO_CTRLCLK

12

R180 2.2K_0402_5%~D

R182 2.2K_0402_5%~D
R183 2.2K_0402_5%~D

Place close to U2.
N28,M28,G36,E36

H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

R1118

SDVO_CTRLDATA

12

R181 2.2K_0402_5%~D

DDPC_CTRLCLK

12

DDPC_CTRLDATA

12

H_A#3

A14

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9

H_ADS#

H_HIT#

+3.3V_RUN

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_BNR#

A9

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

E9

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_BCLK#

AH6

H_DPWR#

J11

H_DRDY#

F9

H_HIT#

H9

H_HITM#

E12

H_LOCK#

H11

H_TRDY#

C9

H_DINV#0

J8

H_DINV#1

L3

H_DINV#2

Y13

H_DINV#3

Y1

H_DSTBN#0

L10

H_DSTBN#1

M7

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

L9

H_DSTBP#1

M8

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

0.1U_0402_16V4Z~D

1

2

U67

16

VCCB

15

CLK_OUT

14

CMD_B

13

B0

12

B1

11

B2

10

B3
GND9OE

FXL2SD106BQX_DQFN16_2P5X3P5~D

+1.05V_VCCP

12

R103
0_0402_5%~D

MMST3904-7-F_SOT323-3~D

4

+1.5V_RUN

C1047

VCCA
CLK_IN
CMD_A

A0
A1
A2
A3

12

R101

54.9_0402_1%~D

1 2

R104
330_0402_5%~D

+1.8V_MEM

+V_DDR_MCH_REF

H_ADS# <7>

H_ADSTB#0 <7>

H_ADSTB#1 <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DBSY# <7>

CLK_MCH_BCLK <6>

CLK_MCH_BCLK# <6>
H_DPWR# <8>
H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>
H_DINV#1 <8>
H_DINV#2 <8>
H_DINV#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

1

2

1
2

GMCH_HDA_BITCLKICH_AZ_MCH_BITCLK

3

GMCH_HDA_RST#

4

GMCH_HDA_SDOUT

5

GMCH_HDA_SYNC

6

GMCH_HDA_SDIN2

7
8

2

B

E

Q4

H_A#[3..35] <7>

R79 80.6_0402_1%~D
R80 80.6_0402_1%~D

0.1U_0402_16V4Z~D

1

2

+1.05V_M

1K_0402_1%~D

12

499_0402_1%~D

R87

1 2

R89
10K_0402_5%~D

12

+3.3V_RUN

1K_0402_5%~D

1K_0402_5%~D

12

12

R99

R98

C

2

B

E

C

3 1

Q3

MMST3904-7-F_SOT323-3~D

3 1

3

M_CLK_DDR0<16>
M_CLK_DDR1<16>
M_CLK_DDR2<17>
M_CLK_DDR3<17>

M_CLK_DDR#0<16>
M_CLK_DDR#1<16>
M_CLK_DDR#2<17>
M_CLK_DDR#3<17>

DDR_CKE0_DIMMA<16>
DDR_CKE1_DIMMA<16>
DDR_CKE2_DIMMB<17>
DDR_CKE3_DIMMB<17>

DDR_CS0_DIMMA#<16>
DDR_CS1_DIMMA#<16>
DDR_CS2_DIMMB#<17>
DDR_CS3_DIMMB#<17>

SMRCOMP

12

SMRCOMP#

12

0.1U_0402_16V4Z~D

1

C68

C69

2

R83

0.1U_0402_16V4Z~D
C70

1

2

R42 33_0402_5%~D
R44 33_0402_5%~D
R685 0_0402_5%~D
R686 33_0402_5%~D
R687 33_0402_5%~D

MCH_TSATN_EC <37>

R81

499_0402_1%~D

1 2

MCH_DREFCLK<6>

MCH_DREFCLK#<6>

DREF_SSCLK<6>

DREF_SSCLK#<6>

CLK_MCH_3GPLL<6>
CLK_MCH_3GPLL#<6>

DMI_MRX_ITX_N0<24>
DMI_MRX_ITX_N1<24>
DMI_MRX_ITX_N2<24>
DMI_MRX_ITX_N3<24>

DMI_MRX_ITX_P0<24>
DMI_MRX_ITX_P1<24>
DMI_MRX_ITX_P2<24>
DMI_MRX_ITX_P3<24>

DMI_MTX_IRX_N0<24>
DMI_MTX_IRX_N1<24>
DMI_MTX_IRX_N2<24>
DMI_MTX_IRX_N3<24>

DMI_MTX_IRX_P0<24>
DMI_MTX_IRX_P1<24>
DMI_MTX_IRX_P2<24>
DMI_MTX_IRX_P3<24>

GFX_VR_ON<49>

CL_CLK0<24>
CL_DATA0<24>

ICH_CL_PWROK<24,38>

CL_RST0#<24>

DDPC_CTRLCLK<21>

DDPC_CTRLDATA<12,21>

SDVO_CTRLCLK<21>

SDVO_CTRLDATA<21>

CLK_3GPLLREQ#<6>
MCH_ICH_SYNC#<24>

When pop R314, then R42,
R44, R685, R686, R687
should be no stuff

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0

M_ODT0<16>

M_ODT1

M_ODT1<16>

M_ODT2

M_ODT2<17>

M_ODT3

M_ODT3<17>

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+V_DDR_MCH_REF

SM_PWROK

MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

GFX_VID0

GFX_VID0<49>

GFX_VID1

GFX_VID1<49>

GFX_VID2

GFX_VID2<49>

GFX_VID3

GFX_VID3<49>

GFX_VID4

GFX_VID4<49>

GFX_VR_ON

CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLK_3GPLLREQ#
MCH_ICH_SYNC#

MCH_TSATN#

HD support 1.5V

GMCH_HDA_BITCLK_R

1 2

GMCH_HDA_RST_R#

1 2

GMCH_HDA_SDI N2_ R

1 2

GMCH_HDA_SDOUT_R

1 2

GMCH_HDA_SYNC_R

1 2

AP24
AT21
AV24
AU20

AR24
AR21
AU24
AV20

BC28
AY28
AY36
BB36

BA17
AY16
AV16
AR13

BD17
AY17
BF15
AY13

BG22
BH21

BF28
BH28

AV42
AR36
BF17
BC36

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

G33

AH37
AH36
AN36
AJ35
AH34

M28
G36

U2B

B38
A38
E41
F41

F43
E43

B33
B32

F33
E33

C34

N28

E36
K36
H36

B12

B28
B30
B29
C29
A28

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP
SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

PEG_CLK
PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

2

M36

RSVD

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35

TP_MCH_RSVD14

T24
B31

B2
M1

AY21

BG23
BF23
BH18
BF18

TP_MCH_RSVD2
TP_MCH_RSVD3

TP_MCH_RSVD6
TP_MCH_RSVD7
TP_MCH_RSVD8

ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS

TP_MCH_RSVD15

TP_MCH_RSVD20

TP_MCH_RSVD24
TP_MCH_RSVD25

R804 100_0402_5%~D@
R805 100_0402_5%~D@
R806 100_0402_5%~D@
R807 100_0402_5%~D@
R1088 51K_0402_1%~D@

T151PAD~D
T152PAD~D

T155PAD~D
T156PAD~D
T157PAD~D

1 2
1 2
1 2
1 2
1 2

T6 PAD~D

T9 PAD~D

T12 PAD~D
T159PAD~D

DDR CLK/ CONTROL/COMPENSATION

CLK

CFG

CFG_10

DMI

PM

GRAPHICS VID

CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#

PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1

PWROK

THERMTRIP#

DPRSLPVR

MEHDA

NC

MISC

CANTIGA ES_FCBGA1329~D

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9

RSTIN#

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

R29
B7
N33
P32
AT40
AT11
T20
R32

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PM_SYNC#
H_DPRSTP#
PM_EXTTS#

ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR

GFX_VR_ON

PLTRST1#_R

+3.3V_RUN

CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>

CPU_MCH_BSEL2 <6,8>

T14 PAD~D
T15 PAD~D

CFG5 <12>
CFG6 <12>
CFG7 <12>

T16 PAD~D

CFG9 <12>

T17 PAD~D
T18 PAD~D
T19 PAD~D
T20 PAD~D
T21 PAD~D
T22 PAD~D

CFG16 <12>

T23 PAD~D
T24 PAD~D

CFG19 <12>

CFG20 <12>

PM_SYNC# <24>
H_DPRSTP# <8,23,47>

PM_EXTTS# <18>

ICH_PWRGD <24,41>

THERMTRIP_MCH# <18>

DPRSLPVR <24,47>

PM_EXTTS#

THERMTRIP_MCH#

SM_PWROK

12

R156
30K_0402_5%~D

12

R157
100K_0402_5%~D

R100 100_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(1 of 6)

LA-3801P

1

@
@

@
@
@

T125PAD~D

@

@

+1.8V_MEM
@
@

3.01K_0402_1%~D

1K_0402_1%~D

@
@

@
@

@
@
@
@
@

@
@

Use for DDR3 signls,
if support DDR2 need
connect to GND

12

+1.05V_VCCP

Reserve 100ohm
and Test point
for ME JTAG
debug

12

R88
1K_0402_1%~D

SMRCOMP_VOH

0.01U_0402_16V7K~D

1

2

SMRCOMP_VOL

0.01U_0402_16V7K~D

1

2

Notes refer
page 12

12

1 2

12

PLTRST1# <22,32>

10 66Thursday, June 12, 2008

C71

C75

of

12

R93

12

R97

R84 10K_0402_5%~D

R102 56_0402_5%~D

R86 0_0402_5%~D

1

@

2.2U_0603_6.3V6K~D

1

2

2.2U_0603_6.3V6K~D

1

2

+3.3V_RUN

+1.05V_VCCP

C72

C76

0.8

5

D D

4

3

2

1

DDR_A_BS0<16>
DDR_A_BS1<16>
DDR_A_BS2<16>

DDR_A_RAS#<16>
DDR_A_CAS#<16>
DDR_A_WE#<16>

DDR_A_DM[0..7]<16>

C C

B B

DDR_A_DQS[0..7]<16>

DDR_A_DQS#[0..7]<16>

DDR_A_MA[0..14]<16>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#

DDR_A_DM0 DDR_A_D11
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

BD21
BG18

AT25
BB20

BD20

AY20

AM37

AT41
AY41

AU39

BB12

AY6
AT7
AJ5

AJ44
AT44

BA43
BC37
AW12

BC8
AU8

AM7
AJ43
AT43
BA44

BD37

AY12

BD8
AU9

AM8
BA21

BC24
BG24
BH24
BG25

BA24

BD24
BG27

BF25

AW24
BC21
BG26
BH26
BH17

AY25

U2D

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#
SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51

DDR SYSTEM MEMORY A

SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62

CANTIGA ES_FCBGA1329~D

SA_DQ_63

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6DDR_A_WE#
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10

DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_B_BS0<17>
DDR_B_BS1<17>
DDR_B_BS2<17>

DDR_B_RAS#<17>
DDR_B_CAS#<17>
DDR_B_WE#<17>

DDR_B_DM[0..7]<17>

DDR_B_DQS[0..7]<17>

DDR_B_DQS#[0..7]<17>

DDR_B_MA[0..14]<17>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

BC16
BB17
BB33

AU17
BG16
BF14

AM47

AY47
BD40
BF35
BG11

AL47
AV48
BG41
BG37

AL46
AV47
BH41
BH37

BG9

AV17
BA25
BC25
AU25

AW25

BB28
AU28

AW28

AT33
BD33
BB16

AW33

AY33
BH15
AU33

BA3
AP1
AK2

BH9
BB2
AU1
AN6

BC2
AT2
AN5

U2E

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#
SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8

SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52

DDR SYSTEM MEMORY B

SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62

CANTIGA ES_FCBGA1329~D

SB_DQ_63

AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK47

DDR_B_D[0..63] <17>DDR_A_D[0..63] <16>

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(2 of 6)

LA-3801P

11 66T h u r s da y, June 12, 2008

1

0.8

of

5

U2C

BIA_PWM<19>

D D

The value is recommended per Intel

C C

B B

R688 2.4K_0402_1%~D

CRT_HSYNC<20>

CRT_VSYNC<20>

PANEL_BKEN_MCH<37>

LDDC_CLK_MCH<19>
LDDC_DATA_MCH<19>

1 2

LCD_ACLK-_MCH<19>
LCD_ACLK+_MCH<19>
LCD_BCLK-_MCH<19>
LCD_BCLK+_MCH<19>

LCD_A0-_MCH<19>
LCD_A1-_MCH<19>
LCD_A2-_MCH<19>

LCD_A0+_MCH<19>
LCD_A1+_MCH<19>
LCD_A2+_MCH<19>

LCD_B0-_MCH<19>
LCD_B1-_MCH<19>
LCD_B2-_MCH<19>

LCD_B0+_MCH<19>
LCD_B1+_MCH<19>
LCD_B2+_MCH<19>

75_0402_5%~D

12

R1114

CRT_BLU<20>
CRT_GRN<20>
CRT_RED<20>

CRT_HSYNC CRT_HSYNC_R

R672 976_0402_1%~D

CRT_VSYNC CRT_VSYNC_R

BIA_PWM
PANEL_BKEN_MCH

LDDC_CLK_MCH
LDDC_DATA_MCH

ENVDD<19>

12

ENVDD
L_IBG

LCD_ACLK-_MCH
LCD_ACLK+_MCH
LCD_BCLK-_MCH
LCD_BCLK+_MCH

LCD_A0-_MCH
LCD_A1-_MCH
LCD_A2-_MCH

LCD_A0+_MCH
LCD_A1+_MCH
LCD_A2+_MCH

LCD_B0-_MCH
LCD_B1-_MCH
LCD_B2-_MCH

LCD_B0+_MCH
LCD_B1+_MCH
LCD_B2+_MCH

75_0402_5%~D

75_0402_5%~D

R1116

12

R1115

CRT_BLU
CRT_GRN
CRT_RED

G_CLK_DDC2
G_DAT_DDC2

1 2

R480 30_0402_1%~D

CRT_IREF

12
1 2

R673 30_0402_1%~D

L32
G32

M32
M33

K33
J33

M29

C44
B43
E37
E38
C41
C40
B37
A37

H47
E46
G40
A40

H48
D45
F40
B40

A41
H38
G37

J37

B42
G38
F37
K37

F25
H25
K25

H24

C31
E32

E28
G28

J28
G29
H32

J32

J29
E29
L29

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK

CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

4

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6

LVDS

TV

VGA

PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

CANTIGA ES_FCBGA1329~D

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

+VCC_PEG

1 2

PEGCOMP

DPB_AUX#

DPC_DOCK_AUX#

DPB_AUX
DPB_HPD#

DPC_DOCK_AUX
DPC_DOCK_HPD#

DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
DPC_LANE_N0
DPC_LANE_N1
DPC_LANE_N2
DPC_LANE_N3

DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
DPC_LANE_P0
DPC_LANE_P1
DPC_LANE_P2
DPC_LANE_P3

3

49.9_0402_1%~D

0.1U_0402_10V7K~D

1

R105

C77

2

DPB_AUX# <21>

DPC_DOCK_AUX# <21>

DPB_AUX <21>

DPB_HPD# <21>

DPC_DOCK_AUX <21>

DPC_DOCK_HPD# <35>

C716 0.1U_0402_10V7K~D

12

C717 0.1U_0402_10V7K~D

12

C718 0.1U_0402_10V7K~D

12

C719 0.1U_0402_10V7K~D

12

C720 0.1U_0402_10V7K~D

12

C721 0.1U_0402_10V7K~D

12

C722 0.1U_0402_10V7K~D

12

C723 0.1U_0402_10V7K~D

12

C724 0.1U_0402_10V7K~D

12

C725 0.1U_0402_10V7K~D

12

C726 0.1U_0402_10V7K~D

12

C727 0.1U_0402_10V7K~D

12

C728 0.1U_0402_10V7K~D

12

C729 0.1U_0402_10V7K~D

12

C730 0.1U_0402_10V7K~D

12

C731 0.1U_0402_10V7K~D

12

DPB_LANE_N0_C <21>
DPB_LANE_N1_C <21>
DPB_LANE_N2_C <21>
DPB_LANE_N3_C <21>
DPC_LANE_N0_C <35>
DPC_LANE_N1_C <35>
DPC_LANE_N2_C <35>
DPC_LANE_N3_C <35>

DPB_LANE_P0_C <21>
DPB_LANE_P1_C <21>
DPB_LANE_P2_C <21>
DPB_LANE_P3_C <21>
DPC_LANE_P0_C <35>
DPC_LANE_P1_C <35>
DPC_LANE_P2_C <35>
DPC_LANE_P3_C <35>

2

CFG5 DMI X2 Select

iTPM Host

CFG6

Interface
Management

CFG7

Engine Crypto
Strap

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

CFG19

DMI Lane
Reversal

SDVO/PCIE

CFG20

Concurrent
Operation

SDVO_CRTL_DATA

DDPC_CTRLDATA

DDPC_CTRLDATA<10,21>

Strap Pin Table

Low = DMI x 2
High = DMI x 4 (Default)
Low = iTPM enable
High = iTPM disable(Defult)
Low = TLS cipher s u i t e wit h n o c onfidentiality
High = TLS cip h e r s u i t e with

confidentiality(Default)
Low = Reverse Lane

High = Normal O p e r a t i o n(Default)

Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed

Low=Only SDVO or PCIEx1 is
operational (default)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present

Low=DisplayPort disabled (default)
High=DisplayPort device present

R106 2.21K_0402_1%~D@

CFG5<10>
CFG6<10>
CFG7<10>
CFG9<10>
CFG16<10>

CFG19<10>
CFG20<10>

1 2

R107 2.21K_0402_1%~D@

1 2

R108 2.21K_0402_1%~D@

1 2

R109 2.21K_0402_1%~D@

1 2

R110 2.21K_0402_1%~D@

1 2

CFG[5:16] have internal pullup

R111 4.02K_0402_1%~D@
R112 4.02K_0402_1%~D@
R113 4.02K_0402_1%~D@

1 2
1 2
1 2

+3.3V_RUN

CFG[19:20] have internal pulldown

1

+3.3V_RUN

R675

2.2K_0402_5%~D

5

CRT_BLU
CRT_GRN
CRT_RED
ENVDD

G_DAT_DDC2 DAT_DDC2

1 2

R679 150_0402_1%~D

1 2

R680 150_0402_1%~D

1 2

R681 150_0402_1%~D

1 2

A A

R682 100K_0402_5%~D

NO CONNECT FOR DISCRETE

12

12

R676

2.2K_0402_5%~D

1 2

R860

@

0_0402_5%~D

+3.3V_RUN

2
5

4

1 2

R861

@

0_0402_5%~D

4

CLK_DDC2G_ C LK_DDC2

61

Q123A
2N7002DW-7-F_SOT363-6~D

Q123B
2N7002DW-7-F_SOT363-6~D

3

CLK_DDC2 <20>

DAT_DDC2 <20>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(3 of 6)

LA-3801P

12 66T h u r s da y, June 12, 2008

1

of

0.8

5

220U_D2_4VY_R15M~D

1

C109

2

4.7U_0603_6.3V6M~D

1

1

C115

2

2

+VCC_AXF

12

1

2

+VCC_TX_LVDS

C136

+VCC_PEG

+VCC_DMI

1

2

0.47U_0402_10V4Z~D

C142

C143

1

2

C147

10U_0805_4VAM~D

+1.05V_VCCP

0.47U_0402_10V4Z~D

C110

2.2U_0603_10V7K~D

C116

10U_0805_4VAM~D

@

1

C125

2

+1.8V_SM_CK

0.1U_0402_16V4Z~D

C137

GMCH_VTTLF1
GMCH_VTTLF2
GMCH_VTTLF3

0.47U_0402_10V4Z~D

1

2

12

12

1U_0603_10V4Z~D

C144

CRB 270uF

1

+

2

D D

4.7U_0603_6.3V6M~D

1

C114

2

+1.05V_M

C C

R118
0_1210_5%~D

+3.3V_RUN

1 2

R1076 0_0603_5%~D

0.1U_0402_16V4Z~D

1

B B

A A

2

0.47U_0402_10V4Z~D

1

2

+1.8V_MEM +1.8V_SM_CK

L7
LQM21FN1R0 N 0 0 _0805~D

Rdc=0.1~0.2,rated
current=220mA(MAX)

U2H

U13

VTT_1

T13

VTT_2

U12

VTT_3

T12

VTT_4

U11

VTT_5

T11

VTT_6

U10

VTT_7

T10

VTT_8

U9

VTT_9

T9

VTT_10

U8

VTT_11

T8

VTT_12

U7

VTT_13

T7

VTT_14

U6

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VTT

T6

U5

T5
V3

U3

V2

U2

T2
V1

U1

POWER

C126

B22

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

BF21

VCC_SM_CK_1

BH20

VCC_SM_CK_2

BG20

VCC_SM_CK_3

BF20

VCC_SM_CK_4

K47

VCC_TX_LVDS

C35

VCC_HV_1

B35

VCC_HV_2

A35

VCC_HV_3

V48

VCC_PEG_1

U48

VCC_PEG_2

V47

VCC_PEG_3

U47

VCC_PEG_4

U46

VCC_PEG_5

AH48

VCC_DMI_1

AF48

VCC_DMI_2

AH47

VCC_DMI_3

AG47

VCC_DMI_4

A8

VTTLF1

L1

VTTLF2

AB2

VTTLF3

L47
HK1608R10J-T_0603~D

1_0603_5%~D

12

R121

5

AXF

SM CK

HV

PEG

DMI

VTTLF

12

0.1U_0402_16V4Z~D

1

C146

2

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

CRTPLLA PEGA SM

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG

A LVDS

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4

VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5

A CK

VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCCA_TV_DAC_1
VCCA_TV_DAC_2

TV

HDA

VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

D TV/CRT

VCCD_LVDS_1
VCCD_LVDS_2

LVDS

CANTIGA ES_FCBGA1329~D

+VCC_TX_LVDS+1.8V_MEM

1

2

1000P_0402_50V7K~D

C744

22U_0805_6.3V6M~D

1

C745

2

118.8mA Max.

VCC_HDA

4

+3.3V_CRT_DAC

B27
A26

A25
B25

F47

+1.05V_M_DPLLA

L48

+1.05V_M_DPLLB

AD1

+1.05V_M_HPLL

AE1

+1.05V_M_MPLL

+VCC_TX_LVDS

J48
J47

+VCCA_PEG_BG

AD48

AA48

+1.05V_M_PEGPLL

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

+1.05V_M_SM_CK

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

B24
A24

A32

M25
L28
AF1
AA47

M38
L37

1U_0603_10V4Z~D

1

2

2 1

D1

@

RB751V_SOD323-2~D

Follow CRB to
VCC_HV(C35,B35,A35)

4

+1.8V_MEM

C743

1U_0603_10V4Z~D

1

C121

2

0.1U_0402_16V4Z~D

1

C127

2

+1.5V_RUN

+1.05V_M_PEGPLL

VCC_HV

+3.3V_CRT_DAC

0.01U_0402_25V7K~D

1

2

1 2

R778 0_0402_5%~D

1 2

@

R779 0_0402_5%~D

1

C117

0.1U_0402_16V4Z~D

2

+1.05V_M_A_SM

4.7U_0603_6.3V6M~D

1

1

C122

2

2

22U_0805_6.3V6M~D

1

1

C128

2

2

0.1U_0402_16V4Z~D

1

C998

2

0.1U_0402_16V4Z~D

1

C141

2

1 2

R122

@

10_0603_5%~D

3

0.01U_0402_25V7K~D

1

0.1U_0402_16V4Z~D

1

C735

C734

2

R116

1 2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0_0805_5%~D

@

1

C123

C124

2

1 2

2.2U_0603_6.3V6K~D
R119 0_1210_5%~D

@

C129

+1.5V_RUN_QDAC +1.5V_RUN

0.01U_0402_25V7K~D

1

C737

2

+1.05V_M

0.1U_0402_16V4Z~D

1

2

220U_D2_4VY_R15M~D

+3.3V_RUN+1.05V_VCCP

1

C732

2

2

+1.5V_RUN
+3.3V_RUN

+1.05V_M

100U_D2E_6.3VM_R15M~D

1

+

C120

2

+1.05V_M

0.1U_0402_16V4Z~D
L44
BLM18PG181SN1_0603~D

1

C738

2

C140

+VCC_DMI

@

C145

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

L43

0.1U_0402_16V4Z~D
BLM18PG181SN1_0603~D

C733

+VCC_TX_LVDS

1000P_0402_50V7K~D

1

C736

2

12

@

L6

1

LBC2518T91NM_1210~D

+

2

3

2

+3.3V_RUN+3.3V_CRT_DAC

12

12

PJP1

@

PAD-OPEN1x1m

12

+VCC_PEG

220U_D2_4VY_R15M~D

4.7U_0603_6.3V6M~D

1

+

2

+1.05V_M

10U_0805_4VAM~D

+1.05V_M_HPLL

+1.05V_M_DPLLA +1.05V_M_DPLLB

64.8mA Max. 64.8mA Max.

+VCC_PEG

+1.05V_M

1

1

C111

C112

2

2

L3

BLM21PG221SN1D_0805~D

1 2

C118

12

R117

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6M~D

1

1

C130

2

2

220U_D2_4VY_R15M~D

0.1U_0402_16V4Z~D

1

1

+

C741

2

2

1 2

R114

22U_0805_6.3V6M~D

0_1210_5%~D

1 2

@

R115

C113

0_1210_5%~D

+1.05V_M_PEGPLL

1_0402_5%~D

+1.05V_M +1.05V_M

L4

12

BLM18AG121SN1D_0603~D

C131

L45

12

10UH_LB2012T100MR_20%_0805~D

C739

2

+1.05V_M

+1.05V_VCCP

Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP

0.1U_0402_16V4Z~D

1

C119

2

1

+1.05V_M_MPLL

139.2mA Max.24mA Max.

0.1U_0402_16V4Z~D
L5
LQH32CNR15M33L_1210~D
R120

1

C132

0_0603_5%~D

1 2

2

1

C133
22U_0805_6.3VAM~D

2

10UH_LB2012T100MR_20%_0805~D

0.1U_0402_16V4Z~D

220U_D2_4VY_R15M~D

1

1

+

C742

2

2

12

+1.05V_M+1.05V_M

L46

12

C740

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(4 of 6)

LA-3801P

13 66T h u r s da y, June 12, 2008

1

of

0.8

5

4

3

2

1

AP33
AN33
BH32
BG32

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31

BF31
BG30
BH29
BG29

BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16
BB21

AW16
AW13

AT13

AE25
AB25
AA25
AE24
AC24
AA24

AE23
AC23
AB23
AA23

AJ21
AG21
AE21
AC21
AA21

AH20

AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15

AF15
AB15
AA15

AN14

AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

U2G

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

+VCC_GFXCORE

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

@

@

Layout Note:

1

1

+

2

1

2

0.1U_0402_10V7K~D

1

2

C747

C746

+

Place close to GMCH

2

1U_0603_10V4Z~D

0.47U_0402_16V4Z~D

1

C749

C748

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_10V7K~D

C157

C158

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C750

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C159

C160

1

1

2

2

C751

10U_0805_10V4Z~D

22U_0805_6.3VAM~D

1

1

C752

C753

2

2

0.47U_0402_10V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

C161

C162

1

2

C163

1

1

2

2

+1.8V_MEM

+1.05V_M

D D

CRB 270uF

220U_D2_4VY_R15M~D

1

C152

+

2

Layout Note:
Place close to GMCH

C C

Layout Note:
Inside GMCH cavity.

B B

A A

0.22U_0402_10V4Z~D

22U_0805_6.3VAM~D

C153

1

1

C154

2

2

0.1U_0402_10V7K~D

0.22U_0402_10V4Z~D

C156

C155

1

1

2

2

1 2

R123
0_0402_5%~D

AG34
AC34
AB34
AA34

U34
AM33
AK33

AJ33
AG33
AF33

AE33
AC33
AA33

W33

U33
AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

U2F

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

VCC CORE

POWER

VCC NCTF

CANTIGA ES_FCBGA1329~D

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+1.05V_M

Layout Note:
Place close to GMCH

0.1U_0402_10V7K~D

2

C149

1

330U_D2_2.5VY_R15M

1

C148

+

2

Layout Note:
Place on the edge

VCC_AXG_SENSE<49>
VSS_AXG_SENSE<49>

22U_0805_6.3V6M~D

1

1

C150

2

2

+VCC_GFXCORE

VCC_AXG_SENSE
VSS_AXG_SENSE

22U_0805_6.3V6M~D

C151

CANTIGA ES_FCBGA1329~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(5 of 6)

LA-3801P

14 66T h u r s da y, June 12, 2008

1

of

0.8

5

4

3

2

1

U2I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

D D

C C

B B

A A

AB47

BD46
BA46
AY46
AV46
AR46

AM46

BF44
AH44
AD44
AA44

M44

BC43
AV43
AU43

AM43

BG42
AY42
AT42
AN42

AJ42

AE42

BD41
AU41

AM41

AH41
AD41
AA41

M41

BG40
BB40
AV40
AN40

AT39

AM39

AJ39

AE39

BH38
BC38
BA38
AU38
AH38
AD38
AA38

BF37
BB37

AW37

AT37
AN37

AJ37

BG36
BD36
AK15
AU36

VSS_9
VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26
VSS_27
VSS_28
VSS_29
VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33
VSS_34

F44

VSS_35
VSS_36
VSS_37
VSS_38
VSS_39

J43

VSS_40

C43

VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

N42

VSS_48

L42

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58
VSS_59

G41

VSS_60

B41

VSS_61
VSS_62
VSS_63
VSS_64
VSS_65

H40

VSS_66

E40

VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93

H37

VSS_94

C37

VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

CANTIGA ES_FCBGA1329~D

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BG21

AW21

AU21
AP21
AN21
AH21
AF21
AB21

BC20
BA20

AW20

AT20

AJ20

AG20

BG19
BG17

BC17

AW17

AT17

BA16
AU16

AN16

BG15
AC15

W15

BG14
AA14

BG13
BC13
BA13

AN13

AJ13

AE13

BF12
AV12
AT12

AM12

AA12

BD11
BB11
AY11
AN11
AH11

BG10
AV10
AT10

AJ10
AE10
AA10

AM9

U2J

VSS_199

L12

VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223
VSS_224

A18

VSS_225
VSS_226
VSS_227
VSS_228
VSS_229

R17
M17
H17
C17

N16

K16

G16

E16

A15

C14

N13

L13

G13

E13

J12
A12

Y11
N11
G11
C11

M10
BF9
BC9
AN9

AD9

G9

B9
BH8
BB8
AV8
AT8

VSS_230
VSS_231
VSS_232
VSS_233

VSS_235
VSS_237

VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS NCTF

VSS_NCTF_15
VSS_NCTF_16

VSS SCB

NC

CANTIGA ES_FCBGA1329~D

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cantiga(6 of 6)

LA-3801P

15 66T h u r s da y, June 12, 2008

1

0.8

of

5

DDR_A_DQS#[0..7]<11>

DDR_A_D[0..63]<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>

DDR_A_MA[0..14]<11>

D D

+1.8V_MEM

2.2U_0603_6.3V6K~D
C166

1

2

0.1U_0402_16V4Z~D

C C

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

B B

A A

1

1

2

2

C176

C175

DDR_A_MA3
DDR_A_MA1

56_0404_4P2R_5%~D

DDR_A_BS0
DDR_A_MA10

56_0404_4P2R_5%~D

DDR_CS0_DIMMA#
DDR_A_RAS#

56_0404_4P2R_5%~D

DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5%~D

DDR_CS1_DIMMA#
M_ODT1

56_0404_4P2R_5%~D

DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_A_BS2

56_0404_4P2R_5%~D

0.1U_0402_16V4Z~D

1

2

C177

5

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C167

1

2

0.1U_0402_16V4Z~D

C171

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

1

2

C178

RN1

1 4
2 3

RN3

1 4
2 3

RN5

1 4
2 3

RN7

1 4
2 3

RN9

1 4
2 3

R130
56_0402_5%~D

RN12

2 3
1 4

C168

1

2

0.1U_0402_16V4Z~D

C172

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C179

+0.9V_DDR_VTT

12

2.2U_0603_6.3V6K~D

1

2

C173

1

2

0.1U_0402_16V4Z~D

1

2

C180

RN2

RN4

RN6

RN8

RN10

RN11

RN13

2.2U_0603_6.3V6K~D

C169

0.1U_0402_16V4Z~D

1

2

1

2

C181

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

14
23

56_0404_4P2R_5%~D

Layout Note:
Place near JDIMMA

C170

1

2

C174

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C182

DDR_A_MA12
DDR_A_MA8

DDR_A_MA6
DDR_A_MA7

DDR_A_MA5
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_BS1
DDR_A_MA0

DDR_A_MA13
M_ODT0

DDR_A_MA11
DDR_A_MA14

0.1U_0402_16V4Z~D

1

2

C184

C183

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C186

C185

Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"

4

3

+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

JDIMMA

1

VREF

3

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11

DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D30
DDR_A_D27

DDR_CKE0_DIMMA<10>

DDR_A_BS2<11>

DDR_A_BS0<11>
DDR_A_WE#<11>

DDR_A_CAS#<11>

DDR_CS1_DIMMA#<10>

M_ODT1<10>

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C188

C187

MEM_SDATA<17,24>
MEM_SCLK<17,24>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59
MEM_SDATA

MEM_SCLK

+3.3V_M

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
C190

C189

1

1

2

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND1

TYCO_1-1734074-1~D

REVERSE

NC/CKE1

DIMMA

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

GND2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO

2

1

+V_DDR_MCH_REF

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

M_CLK_DDR#0

32
34

DDR_A_D14DDR_A_D10

36

DDR_A_D15

38
40

42

DDR_A_D20

44

DDR_A_D21DDR_A_D17

46
48
50

DDR_A_DM2

52
54

DDR_A_D22

56

DDR_A_D23DDR_A_D19

58
60

DDR_A_D28

62

DDR_A_D29

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72
74

DDR_A_D31

76
78

DDR_CKE1_DIMMA

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90
92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D38

134

DDR_A_D39

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D46

152

DDR_A_D47

154
156

DDR_A_D52DDR_A_D48

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D54

174
176
178

DDR_A_D60DDR_A_D56

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

R128 10K_0402_5%~D

198
200
202

1 2

R129 10K_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

1

C164

2

M_CLK_DDR0 <10>

M_CLK_DDR#0 <10>

DDR_CKE1_DIMMA <10>

DDR_A_BS1 <11>

DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DDR1 <10>

M_CLK_DDR#1 <10>

1

C165

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3801P

16 66T h u r s da y, June 12, 2008

1

0.8

of

5

DDR_B_DQS#[0..7]<11>

DDR_B_D[0..63]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS[0..7]<11>

DDR_B_MA[0..14]<11>

D D

C C

B B

A A

+1.8V_MEM

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C202

DDR_B_MA3
DDR_B_MA1

56_0404_4P2R_5%~D

DDR_B_BS0
DDR_B_MA10

56_0404_4P2R_5%~D

DDR_B_BS1
DDR_B_MA0

56_0404_4P2R_5%~D

DDR_B_RAS#
DDR_CS2_DIMMB#

56_0404_4P2R_5%~D

DDR_B_WE#
DDR_B_CAS#

56_0404_4P2R_5%~D

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C193

C194

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C198

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

1

2

2

RN14

RN16

RN18

RN20

RN22

RN25

5

2

C204

C205

+0.9V_DDR_VTT

12

C203

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

R133
56_0402_5%~D

2 3
1 4

2.2U_0603_6.3V6K~D

1

2

C199

1

2

0.1U_0402_16V4Z~D

1

2

C206

RN15

RN17

RN19

RN21

RN23

RN24

RN26

2.2U_0603_6.3V6K~D
C196

C195

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C200

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C207

DDR_B_MA12

14

DDR_B_BS2

23

56_0404_4P2R_5%~D

DDR_B_MA14

14

DDR_B_MA11

23

56_0404_4P2R_5%~D

DDR_B_MA5

14

DDR_B_MA8

23

56_0404_4P2R_5%~D

DDR_B_MA7

14

DDR_B_MA6

23

56_0404_4P2R_5%~D

DDR_B_MA4

14

DDR_B_MA2

23

56_0404_4P2R_5%~D

M_ODT2

14

DDR_B_MA13

23

56_0404_4P2R_5%~D

DDR_B_MA9

14

DDR_CKE2_DIMMB

23

56_0404_4P2R_5%~D

Layout Note:
Place near JDIMMB

2.2U_0603_6.3V6K~D
C197

1

2

C201

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C208

C209

0.1U_0402_16V4Z~D

1

2

C210

4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C211

Layout Note:
Place these resistor
closely DIMMB,all
trace length<750 mil

Layout Note:
Place these resistor
closely DIMMB,all
trace length
Max=1.3"

0.1U_0402_16V4Z~D

1

1

2

2

C213

C212

4

3

JDIMMB

1

VREF

3

C216

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND1

TYCO_2-1734072-2~D

DIMMB

STANDARD

DDR_B_D0 DDR_B_D5
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16 DDR_B_D20
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB<10>

DDR_B_BS2<11>

DDR_B_BS0<11>
DDR_B_WE#<11>

DDR_B_CAS#<11>

DDR_CS3_DIMMB#<10>

MEM_SDATA<16,24>
MEM_SCLK<16,24>

M_ODT3<10>

+3.3V_M

1

2

C214

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0 DDR_B_RAS#
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
MEM_SDATA

MEM_SCLK

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

C215

1

1

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO
GND2

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

SA1

2

+1.8V_MEM+1.8V_MEM +V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

+V_DDR_MCH_REF

DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_CS2_DIMMB#
M_ODT2

DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%~D

12

R132

2.2U_0603_6.3V6K~D

M_CLK_DDR2 <10>

M_CLK_DDR#2 <10>

DDR_CKE3_DIMMB <10>

DDR_B_BS1 <11>

DDR_B_RAS# <11>

DDR_CS2_DIMMB# <10>

M_ODT2 <10>

M_CLK_DDR3 <10>

M_CLK_DDR#3 <10>

R131

10K_0402_5%~D

1

2

+3.3V_M

12

0.1U_0402_16V4Z~D

C191

1

1

C192

2

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3801P

17 66T h u r s da y, June 12, 2008

1

0.8

of

5

+3.3V_M

12

R134

8.2K_0402_5%~D

+1.05V_VCCP

R135

D D

H_THERMTRIP#<7>

THERMTRIP_MCH#<10>

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

+1.05V_VCCP

R138

2.2K_0402_5%~D

1 2

MMST3904-7-F_SOT323-3~D

Q5

Q6

2

B

2

B

C

E

3 1

+3.3V_M

12

C

E

3 1

THERMATRIP1#

1

C218

0.1U_0402_16V4Z~D

2

R137

8.2K_0402_5%~D

THERMATRIP2#

1

C220

0.1U_0402_16V4Z~D

2

RB751S40T1_SOD523-2~D

Place under CPU

C231

C

3 1

1

C225

2

C

3 1

1

+RTC_CELL

C229

0.1U_0402_16V4Z~D

2

1

2

E

E

100P_0402_50V8K~D

C C

H_THERMDA<7>

H_THERMDC<7>

Q9 Place near DIMM

Place C227 close
to Q9

B B

+3.3V_M

1

Place C223 close to the Q8 as possible
Place C224, C225 close to the Guardian pins as possible

470P_0402_50V7K~D

Place C228 close to the Guardian pins as possible

1

C227

@

100P_0402_50V8K~D

2

1 2

R142

0_0603_5%~D

0.1U_0402_16V4Z~D

2

C223

@

Rset=953,Tp=88degree

+3.3V_M

12

R155

8.2K_0402_5%~D

A A

THERMATRIP3#

1

C240

0.1U_0402_16V4Z~D

2

5

4

D2

2 1

19.2

2

B

Q8
MMBT3904WT1G_SC70-3~D

2

B

Q9

MMBT3904WT1G_SC70-3~D

12

R151
953_0402_1%~D

2200P_0402_50V7K~D

R887 0_0603_5%~D

1 2

+5V_RUN

*

4

+3.3V_M

FAN1_DET#<22>

1

C219

2

22U_0805_6.3VAM~D

BC_DAT_EMC4002<38>

BC_CLK_EMC4002<38>

2

C224
2200P_0402_50V7K~D

1

REM_DIODE1_P
REM_DIODE1_N

1

C228

2

1U_0603_10V4Z~D

1

C230

3.3V_M_PWRGD<38,41>

2

ICH_PWRGD#<41>

+3VSUS_THRM

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

+3.3V_RUN

C235

1

1

C234

2

2

Pull-up Resistor
on ADDR_MODE/XEN

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

1

1

C236

2

2

EC_32KHZ_OUT<38>

<= 4.7K +/- 5% 2F(r/w)

10K
18K

>= 33K

REM_DIODE3_P
REM_DIODE3_N

+3VSUS_THRM
+RTC_CELL_R

1 2

R146 1K_0402_5%~D

1 2

R148 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

VSET

R150 4.7K_0402_5%~D

+FAN1_VOUT

C237

FAN1_TACH_FB

EC_32KHZ_OUT

For Remote1
mode

2N3904

2N3904
Thermistor
Thermistor

3

12

R136
10K_0402_5%~D

+FAN1_VOUT

FAN1_TACH_FB

12

SMBUS
Address

2E(r/w)
2F(r/w)
2E(r/w)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

U3
EMC4002

10
11

36
35

38
37

41
40

4

21

18
17

22
23
24

42

3

6
5

9
7

8

15
14

3

JFAN1

1

1

2

2

3

5

3

G1

4

6

4

G2

MOLEX_53398-0471~D

200K_0402_1%~D

SMDATA/BC-LINK_DATA
SMBCLK/BC-LINK_CLK

DP1/VREF_T
DN1/THERM

DP2
DN2

DP3/DN7
DN3/DP7

VCC

ATF_INT#/BC-LINK_IRQ#

RTC_PWR3V

THERMTRIP_SIO/PWM1/GPIO5

VCC_PWRGD
3V_PWROK#

THERMTRIP1#
THERMTRIP2#
THERMTRIP3#

VSET
ADDR_MODE/XEN

VDD_5V
VDD_5V

VDD_3V
FAN_OUT

FAN_OUT
TACH1/GPIO3

CLK_IN/GPIO2

LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2

VSS

49

R930

0_0402_5%~D

12

R997

39

VIN1

48

VCP1

45

VCP2

44

DP4/DN8

43

DN4/DP8

47

DP5/DN9

46

DN5/DP9

DN6/VIN2

LDO_POK

LDO_SET

1
2

12
26
27
20
25

19
34
33

32
31

28
29

30
16

13

4

R1014 0_0402_5%~D@
R1015 0_0402_5%~D@

DP6/VREF_T2

POWER_SW#
ACAVAIL_CLR

SYS_SHDN#

LDO_SHDN#

VDDH/VDD_5V2
VDDH/VDD_5V2

VDDL/VDD_3V2

TACH2/GPIO4

PWM2/GPIO1

74AHC1G08GW_SOT353-5~D

POWER_SW#

R998

1 2

12

4.7K_0402_5%~D

Place C221 close to the
Guardian pins as possible.

REM_DIODE4_P
REM_DIODE4_N

12

R141 10K_0402_5%~D

POWER_SW#

12

R149 10K_0402_5%~D

12

R211 10K_0402_5%~D@

LDO_SET

+3V_LDOIN

R926

0_0402_5%~D

+RTC_CELL

0.1U_0402_16V4Z~D

5

P

IN1

O

IN2

G

3

1 2
1 2

1 2

1
2

U68

2

PWR_MON_GFX <49>
PWR_MON <47>
ISL88731_ICM <48>

1

C221

2

2200P_0402_50V7K~D

THERMISTOR OPTION:
Single-ended ro ut in g t o thermistor is permissible
(ground retu r n ) . Pl a c e R139 and C226 near EMC4002

+3.3V_M

BC_INT#_EMC4002 <38>
ACAV_IN <38,48>

2.5V_RUN_PWRGD <37,41>

+1.8V_RUN

10U_0805_10V6K~D

0.1U_0402_16V4Z~D

1

1

C238

2

2

12

C1050

PM_EXTTS# <10>

R143

0_0402_5%~D

R144

0_0402_5%~D

2

1 2

R139

1.2K_0402_1%~D

+3.3V_SUS

10U_0805_10V4Z~D

1

2

C239

12
12

1

Diode circui t a t DP 4 /DN4 is used for skin
temp sensor (p la ce d o ptimally between CPU,
MCH and MEM).

C

Q7

2

B

MMBT3904WT1G_SC70-3~D

E

3 1

1 2

R140

10KB_0603_1%_TSM1A103F34D3R~D

C226

0.1U_0402_16V4Z~D

1 2

12

R145 10K_0402_5%~D

1 2

R147 47K_0402_1%~D@

At maximum loa d c ur rent of 600mA,the the
voltage drop a c r o ss the should be keep
in the range of 0.5V to 1V

0.1U_0402_16V4Z~D
R152

0.82_1210_1%~D

1

C232

C233

2

DOCK_PWR_SW# <38>
POWER_SW_IN# <38>

+3.3V_M

THERM_STP# <44>

+RTC_CELL

+3.3V_RUN

12

1

C222

@

100P_0402_50V8K~D

2

Place C222 close to Q7 as
possible.

+1.8V_RUN

LDO_SET

Voltage margi ning circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT / 1.12)-1)*Rb.

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-3801P

1

12

R153

Ra

3.16K_0402_1%~D

12

R154

Rb

5.1K_0402_1%~D

18 66T h u r s da y, June 12, 2008

0.8

of

5

4

3

2

1

JLVDS1

59

MGND1

60

MGND2

61

MGND3

62

MGND4

63

MGND5

64

MGND6

65

MGND7

66

MGND8

67

MGND9

68

D D

C C

MGND10

69

MGND11

70

MGND12

71

MGND13

72

MGND14

Diag_Loop_CAM

JAE_FI-DP58SB-VF88L

DATA EEDID

For Webcam

+CAMERA_VDD

B B

100K_0402_5%~D

Webcam PWR CTRL

CCD_OFF<37>

A A

CCD_OFF

Even_ClkIN+

Even_ClkIN-

VSS

Even_Rin2+

Even_Rin2-

VSS

Even_Rin1+

Even_Rin1-

VSS

Even_Rin0+

Even_Rin0-

VSS
Odd_ClkIN+
Odd_ClkIN-

VSS

Odd_Rin2+

Odd_Rin2-

VSS

Odd_Rin1+

Odd_Rin1-

VSS

Odd_Rin0+

Odd_Rin0-

VSS
CLK EEDID

VSS

VEEDID

MIC_CLK

3.3V

MIC_SIG

USB-

USB+

GND

CONNTST

SMB_CLK

SMB_DATA

INV_SRC
INV_SRC
INV_SRC
INV_SRC

VBL­VBL­VBL­VBL-

INV_PWM

+5V_ALW

TEST

VDD

VDD

VDD

CONNTST

PWR_LED
BATT2_LED
BATT1_LED

VSS

0.1U_0402_16V4Z~D

1

2

2

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

5V

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

PMV45EN_SOT23-3~D

10U_1206_16V4Z~D

1

C249

2

+15V_ALW

12

R169

13

D

G

S

LDDC_DATA_MCH
LDDC_CLK_MCH
LVDS_CBL_DET#

CAM_MIC_CBL_DET#
DMIC_CLK

DMIC0
USBP11_D-

USBP11_D+

LCD_SMBCLK
LCD_SMBDAT

LCD_TST

BREATH_BLUE_LED
BATT_YELLOW_LED
BATT_BLUE_LED

Q132

S

G

C250

Q133

2N7002W-7-F_SOT323-3~D

1 2

C246

0.1U_0603_50V4Z~D

D

+CMOS_VDD

13

2

1

C1044

0.1U_0402_25V4K~D

2

LCD_BCLK+_MCH <12>

LCD_BCLK-_MCH <12>
LCD_B2+_MCH <12>

LCD_B2-_MCH <12>

LCD_B1+_MCH <12>

LCD_B1-_MCH <12>

LCD_B0+_MCH <12>

LCD_B0-_MCH <12>

LCD_ACLK+_MCH <12>

LCD_ACLK-_MCH <12>
LCD_A2+_MCH <12>

LCD_A2-_MCH <12>

LCD_A1+_MCH <12>

LCD_A1-_MCH <12>

LCD_A0+_MCH <12>

LCD_A0-_MCH <12>

LDDC_DATA_MCH <12>

LDDC_CLK_MCH <12>

LVDS_CBL_DET# <22>

+3.3V_RUN

CAM_MIC_CBL_DET# <22>

+CAMERA_VDD

LCD_SMBCLK <38>
LCD_SMBDAT <38>

+INV_PWR_SRC

LCD_TST <37>

+LCDVDD

PNL_BKLT_CBL_DET# <22>

BREATH_BLUE_LED <42>

BATT_YELLOW_LED <42>

BATT_BLUE_LED <42>

R170

@

0_0603_5%~D

12

R995

0_0603_5%~D

12

1

C1043

0.1U_0402_16V4Z~D

2

+3.3V_RUN

12

@

10K_0402_5%~D

+3.3V_RUN

+5V_RUN

+3.3V_RUN

D47

@

2 1

R165

SD05.TCT_SOD323-2~D

1 2

R166 0_0402_5%~D

Close to JLVD1.9 Close to JLVD1.6,7,8

1 2

R159 2.2K_0402_5%~D

1 2

R160 2.2K_0402_5%~D

LDDC_CLK_MCH
LDDC_DATA_MCH

Place near to JLVDS1

DMIC_CLK <27>

+3.3V_RUN

DMIC0 <27>

D48

D56

@

@

2 1

2 1

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

BIA_PWM <12>

+5V_ALW

1

C245

0.1U_0402_16V4Z~D

2

+3.3V_RUN +LCDVDD

0.1U_0402_16V4Z~D

1

C243

2

0.1U_0402_16V4Z~D

1

C244

2

LCD Power

2N7002DW-T/R7_SOT363-6~D

LCD_VCC_TEST_EN<37>

ENVDD<12>

Dual layout for Q17

Overlap on Q16 for pop option

+PWR_SRC

Q17
SI3457DV-T1_TSOP6~D

D

6

S

4 5

2
1

G

3

PWR_SRC_ON

SI3457DV : P CHANNAL

USBP11-<24>

USBP11+<24>

USBP11+

USBP11_D-

Q13A

D3

3

2

BAT54CW_SOT323~D

1 2

R164 0_0402_5%~D@

+INV_PWR_SRC

L59

@

DLW21SN121SQ2L_4P~D

1

1

4

4

1 2

R457 0_0402_5%~D

1 2

R513 0_0402_5%~D

U50

@

1

GND

2

IO1

PRTR5V0U2X_SOT143-4~D

+LCDVDD

1

IO2
VIN

12

61

2

3

3
4

470_0402_5%~D

R161

2

2

2

3

USBP11_D+

+15V_ALW

I

40mil

1000P_0402_50V7K~D

1

C248

2

+15V_ALW +3.3V_RUN

100K_0402_5%~D

12

R162

5

1

O

Q15

G

DDTC124EUA-7-F_SOT323-3~D

3

+PWR_SRC

12

USBP11_D-USBP11-

USBP11_D+

+CAMERA_VDD

+LCDVDD

12

R158
100K_0402_5%~D

2N7002DW-T/R7_SOT363-6~D

3

12

Q13B

4

R167
100K_0402_5%~D

PWR_SRC_ON

1 2

R168 100K_0402_5%~D

RUN_ON<28,37,40,41>

D

S

4 5

G

SI3456DV-T1-E3_TSOP6~D

3

100K_0402_5%~D

0.1U_0402_25V4Z~D

@

R163

1

C242

2

Q16

@

FDS4435_NL_SO8~D

8
7

1

6

2

5

3

4

D

1 3

6
2

1

Q12

Q18
2N7002W-7-F_SOT323-3~D

S

G

2

1

C241

0.1U_0402_16V4Z~D

2

40mil

1

C247

0.1U_0603_50V4Z~D

2

FDS4435: P CHANNAL

+INV_PWR_SRC

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LVDS Conn

LA-3801P

19 66T h u r s da y, June 12, 2008

1

0.8

of

2

+3.3V_RUN

RED_CRT

GREEN_CRT

BLUE_CRT

12

R172

150_0402_1%~D

B B

DAT_DDC2<12>

CLK_DDC2<12>

CRT_VSYNC<12>
CRT_HSYNC<12>

CRT_RED<12>
CRT_GRN<12>
CRT_BLU<12>

CRT_SWITCH<37>

SEL CRT
0 MB
1 APR/SPR

+3.3V_RUN

DAT_DDC2
CLK_DDC2

CRT_SWITCH

U4

4

VCC

10

VCC

18

VCC

27

VCC

38

VCC

50

VCC

56

VCC

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

A8

20

A9

17

SEL

1

GND

6

GND

9

GND

13

GND

16

GND

21

GND

24

GND

28

GND

33

GND

39

GND

44

GND

49

GND

53

GND

55

GND

TS3DV520ERHUR_QFN56_11X5~D

12

12

R174

R173

150_0402_1%~D

150_0402_1%~D

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

10P_0402_50V8J~D

10P_0402_50V8J~D

1

1

@

@

C255

2

2

DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_BUF
HSYNC_BUF
RED_CRT
GREEN_CRT
BLUE_CRT

DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
HSYNC_DOCK
RED_DOCK
GREEN_DOCK VSYNC_CRT
BLUE_DOCK

10U_0805_10V4Z~D

1

2

10P_0402_50V8J~D

1

@

C256

C257

2

DAT_DDC2_DOCK <35>
CLK_DDC2_DOCK <35>
VSYNC_DOCK <35>
HSYNC_DOCK <35>
RED_DOCK <35>
GREEN_DOCK <35>
BLUE_DOCK <35>

0.1U_0402_16V4Z~D

1

1

C259

C260

2

2

1 2

R1095
0_0402_5%~D

1 2

R1096
0_0402_5%~D

1 2

R1097
0_0402_5%~D

To MB CRT Conn.

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C262

C261

2

10P_0402_50V8J~D

1

2

0.1U_0402_16V4Z~D

1

1

C263

2

2

RED_CRT_L

GREEN_CRT_L

BLUE_CRT_L

10P_0402_50V8J~D

1

1

C390

C518

2

2

To Dock Conn.

+3.3V_RUN

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C264

C265

2

1

2

10P_0402_50V8J~D

C996

0.1U_0402_16V4Z~D

C266

1 2

L61
BLM18BB470SN1D_0603~D

1 2

L62
BLM18BB470SN1D_0603~D

1 2

L63
BLM18BB470SN1D_0603~D

DAT_DDC2_CRT
CLK_DDC2_CRT

HSYNC_CRT

R177 0_0402_5%~D

R178 0_0402_5%~D

2

10P_0402_50V8J~D

1

C251

2

1 2

1 2

1

3

DA204U_SOT323-3~D

@

D5

+5V_RUN_SYNC

HSYNC_L2

VSYNC_L2

DA204U_SOT323-3~D

1

@

D6

2

3

10P_0402_50V8J~D

1

C252

2

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

R794

L11

BLM11A121S_0603~D

1 2

1 2

L12

BLM11A121S_0603~D

R793

2

10P_0402_50V8J~D

1

C253

2

1K_0402_5%~D

12

@

R175

22P_0402_50V8J~D

1

@

C267

2

1

DA204U_SOT323-3~D

1

@

D7

3

1K_0402_5%~D

12

@

R176

22P_0402_50V8J~D

1

@

C268

2

+5V_RUN

5A_125V_R451005.MRL~D

@

F2

1 2

SDM10U45-7_SOD523-2~D

21

D8

+CRT_VCC

+5V_RUN_CRT

0_1206_5%~D

R171

1 2

R

G
JVGA_HS

B
+CRT_VCC
JVGA_VS
M_ID2#

1

C258

2

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

1

C254

2

JCRT1

6

11

1
7

12

2
8

16

13

17
3
9

14

4

10
15

5

SUYIN_070546FR015S558ZR

+5V_RUN

21

D9
SDM10U45-7_SOD523-2~D

C269

0.1U_0402_16V4Z~D

HSYNC_BUF HSYNC_CRT

A A

1 2

C270

0.1U_0402_16V4Z~D

1

5

P

OE#

A2Y

G

U5
SN74AHCT1G125GW_SC70-5~D

3

1

5

P

OE#

A2Y

G

U6
SN74AHCT1G125GW_SC70-5~D

3

+5V_RUN_SYNC

1 2

4

4

1 2

R179 1K_0402_5%~D

VSYNC_CRTVSYNC_BUF

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CRT/Video switch

LA-3801P

20 66T h u r s da y, June 12, 2008

0.8

of