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COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME :DDM60
PCB NO : LA-F391P
BOM P/N : 431A8K31LXX
BR MLK12 KBL-U UMA
Kabylake U42
2 2
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
3 3
U42@ : KBL-R U42 Component
2017-09-25
REV :1.0 (A00)
U22@ : KBL-R U22 Component
DS3@ : Support DS3 Component
MB PCB
Part Number
DAA000EB00 0
4 4
COPYRIGHT 2015
ALL RIGHT RESERVED
REV:X00
PWB: 9RJMF
Descriptio n
PCB 258 LA-F391P REV0 MB 1
Layout Dell logo
A
NDS3@ : No Support DS3 Component
650@ : Pop NPCT650VB2YX Component
750@ : Pop NPCT750JAAYX Component
PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ( "DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Dat e: Shee t o f
Dat e: Shee t o f
D
Dat e: Shee t o f
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-F391P
LA-F391P
LA-F391P
1 70Monday, September 25, 2017
1 70Monday, September 25, 2017
1 70Monday, September 25, 2017
E
0.2
0.2
0.2
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B
C
D
E
BreckenridgeMLK 12 UMA Block Diagram
Memory BUS (DDR4)
DDR4 2133MHz for KBL-U
DDR4 2400MHz for KBL-H
Up to 2x8GB Modul es
USB
USH TPM1.2
BCM58102
USB2.0[9]
SLGC55544BVTR
USB POWER SHARE
HD Audio I/F
SATA REPEATER
PI3EQX6741STZDEX
SATA/PCIE REPEATER
PS8558 x2
USB2.0[10 ]
USH board
P39
1 1
VGA
CONN
P24
2 2
PCIE[1 ]
Card reader
RTS524 2
SD4.0
3 3
P31
P31
Intel Jacksonville
WGI219LM
PCIE[4 ]
Transformer
RJ45
P30
P30
P30
EDP CONN
HDMI 1.4
CONN
DP TO VGA
RTD216 6
SATA[1]/ PCIE[8 ]
M.2,3042 Key B
WWAN/LTE/HC A
USB3.0[2]
P29
P23
SW2_DP1
To Type C
P24
P33
USB2.0[4]
2-Lane eDP1.3
HDMI
SW2_DP3
To VGA
M.2,3030 Key A
WLAN+ BT
DP DeMUX
PS8338B
PCIE[3 ]
P33
USB2.0[7]
DDI[1 ]
INTEL
Kaby Lake Refresh U MCP
DDI[2 ]
P22
PAGE 6~19
SATA[0]
ESPI
SMSC KBC
MEC510 5
SPI
P35-3 6
SATA[2]/PC IE[12] [11]
W25Q128JVS IQ
128M 4K sector
P8
W25Q128JVS IQ
128M 4K sector
TPM1.2/2.0 Nuvoton
NPCT750 JAAYX
KB/TP CONN
FAN CONN
P8
reserve
P45
P36
P38
Non-AR Type C
DP1.2 4 lanes
TX/RX
USB 3.0 + AM
Type C CONN.
4 4
USB2.0
CC
Vbus
HS Redriver Switch
TUSB546 @
PS8743 @
P25
GPIO
PD Solut i on
TPS6598 2DC
P26-2 7P28
SW2_DP1
USB3.0[1]
SMBUS
USB2.0[1]
Smart Card
TDA8034HN
RFID/NF C
Fingerprin t
CONN
SPI
SPI
Reverse Type
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
USB2.0[8]
USB2.0[5]
USB2.0[9]_P S
P43
USB3.0[6]
USB2.0[2]
USB3.0[3]
HDA Codec
ALC32 54
P39
P34
P41
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
USB3.0 Conn
(Ext Port 2)
INT.Speake r
Universal Jack
Dig. MIC
P29
P29
P43
P44
P34
P34
P29
Trough eDP Cable
SATA HDD
Conn
P41
M.2 2280
SSD Conn
P40
Trough eDP Cable
LID SWITCH
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
Free Fall sensor
DC/DC Interface
POWER ON/OFF
SW & LED
LED board
P46
P38
P14
P11
P41
P47
P46
5V VR
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY N OTE: THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANS FERRED OR COPIED WITHOUT THE EXPRESS W RITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
C
PARTY WITHOUT DELL 'S EXP RESS WRITTEN CONSENT.
D
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-F391P
LA-F391P
LA-F391P
E
2 70Monday, September 25, 2017
2 70Monday, September 25, 2017
2 70Monday, September 25, 2017
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POWER STATES
Signal
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M 3
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M -OFF
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW
LOW
LOW LO W LOW
LOW LO W LOW LOW
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH ON ON ON
HIGH HIGH
LOW
LOW
LOW
HIGH HIGH
HIGH
ALWAY S
SLP
PLANE
A#
ON
HIGH
HIGH
ON ON
ON ON
HIGH
ON ON
LOW
ON
ON
PM TABLE
+5V_A LW
+3.3V_A LW
+3.3V_ALW_D SW
power
C C
State
S0
S3
S5 S4/AC
S5 S4/AC doesn't exist
plane
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CEL L
+1.8V_PRIM
+1.0V_PRIM
+1.0V_P RIM_ CORE
+5V_ALW2
+3.3V_A LW2
+3.3V_RTC_ LDO
+1.0V_MPHYGT
ON
ON
ON
+3.3V_CV2
+2.5V_MEM
+1.0 V_VCCST
+5V_ RUN
+3.3 V_RUN
+0.6V_DD R_VTT
+1.8 V_RUN
+VCC_ CORE
+VCC_G T
+VCC_SA
+1.0VS_VCCIO
ON ON
ON
OFF
OFFOFF
4
M
PLA NE
ON
OFF OFF OFF
OFF OFF OFF OFF
OFF OFF OFF OFF
OFF
OFF
OFF
RUN
SUS
PLA NE
PLANE
ON ON ON
OFF
OFF
OFF
OFF
OFFLOW
CLOCK S
OFF
OFF
OFF
USB3.0
USB3.0- 1
USB3.0- 2
USB3.0- 3
USB3.0- 4
USB3.0- 5
USB3.0- 6
SSIC
SSIC
3
2
1
For Breckenridge12/14/15 UMA
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
SATA-0
SATA-1
M.2 3042(SATA Cache or HCA)
SATA-1 *
SATA-2
M.2 2280 SSD
(PCIex2 or SATA)
12" not support JUSB3
Type-C Port Type-C Port
M.2 3042(LTE)
JUSB2-->Lef t
JUSB3-->Rear Lef t
Card Reader
JUSB1-->Right
M.2 3030(WLAN)
LOM
NA
NA
SATA HDD
NA
NA
USB PORT#DESTINATION
DESTINATION
1
2
3
4
5
6
7
8
9
10
JUSB2-->Lef t
JUSB3-->Rear Lef t
M2 3042(WWAN)
Camera
NA
M.2 3030(BT)
Touch Screen
JUSB1-->Right
USH
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F391P
LA-F391P
LA-F391P
1
3 70Monday, September 25, 2017
3 70Monday, September 25, 2017
3 70Monday, September 25, 2017
0.2
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Barrel
ADAP TER
D D
CHAR GER
ISL953 8
(PU901)
Type-C
ADAP TER
+PWR_SRC
BATTERY
C C
SY8210A
(PU200)
SYX198D
(PU301)
SY8288C
(PU102)
SY8288B
(PU100)
4
SIO_SLP_S4 #
0.6V_DDR_ VTT_ON
PCH_ PRIM_EN
(SIO_SLP_SUS #)
ALWO N
ALWO N
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
+3.3V_RTC_LDO
+3.3V_ALW2
TPS22961
(UZ26)
3
PCH_ PRIM_EN
(SIO_SLP_SUS #)
SIO_SLP_S4 #
+VCC_SFR_O C
TPS62134C
(PU401)
TPS62134D
(PU402)
EM5209
(UZ4)
SLGC55544 C
(UI3)
SY6288
(UI1)
RUN_ ON
PCH_ PRIM_EN
(SIO_SLP_SUS #)
RUN_ ON
USB_POWE RSHARE _VBUS_E N
USB_PWR _EN1#
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+USB_EX2_PWR
TPS22961
(UZ19)
TPS22961
(UZ21)
+5V_RUN
+5V_USB_CHG_PWR
2
1
CPU PWR
PCH PWR
GT3 PWR
RUN_ ON
SIO_SLP_S0 #
SIO_SLP_S4 #
LP2301
(QV8)
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCS T
3.3V_TS_E N
@PCH_3.3V_T S_EN
AUD_P WR_E N
Peripheral Device PWR
TYPE-C Power
GPU PWR
+3.3V_TSP
+5V_RUN_A UDIO
+3.3V_ALW
RT8097A
CSD97396Q
ISL95857
(PU602)
IMVP_VR _ON
B B
+VCC_ SA
CSD97396Q
(PU612)
IMVP_VR _ON
+VCC_GT
(PU610)
CSD 97396Q
(PU613)
U42@
IMVP_VR _ON
+VCC_COR E
AO6405
(QV1)
EN_IN VPWR
+BL_P WR _SRC
(PU501)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
PCH_ PRIM_EN
(SIO_SLP_SUS #)
SIO_SLP_ LAN#
3.3V_ WWAN_E N
@PCH_ALW _ON
PCH_ PRIM_EN
(SIO_SLP_SUS #)
RUN_ ON
@SIO_SLP_ WLAN#
AUX_EN_W OW L
LCD_VCC_TE ST_E N
ENVDD _PC H
+1.8V_PRIM
+3.3V_LAN
+3.3V_WWAN
+3.3V_ALW_PC H
+3.3V_RU N
+3.3V_WLAN
+LCDVD D
AOZ1336
(UZ8)
LP2301A
(QZ1)
EM5209
(@UZ5)
RUN_ ON
3.3V_C AM_EN#
AUD_P WR_E N
+1.8V_RU N
+3.3V_CAM
+3.3V_RUN_ AUDIO
TYPE-C
+TBTA_VBUS(5V~20V)
TPS22967
(UZ18)
AP7361C
A A
AP2204
(UT8)
5
+5V_ALW
+5V_TBT_VBUS
AP2112K
(UT7)
+3.3V_TBT_SX
4
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CV2_O N
SIO_SLP_S4 #
+3.3V_CV2
+2.5V_MEM
for DDR4
USH/ B
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
2
Date : Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-F391P
LA-F391P
LA-F391P
1
4 70Tuesday, September 19, 2017
4 70Tuesday, September 19, 2017
4 70Tuesday, September 19, 2017
0.2
0.2
0.2
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5
4
3
2
1
PD &
FW ref lash
2.2K
2.2K
+3.3V_RU N
202
200
202
200
DIMM1
DIMM2
53
51
1
4
XDP
LNG2DMTR
1K
+3.3V_ALW _PC H
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW _PC H
+3.3V_TP
+3.3V_AL W
+3.3V_AL W
+3.3V_AL W
0ohm short pad
0ohm short pad
DMN66D0LDW -7
DMN66D0LDW -7
28
31
LOM
UPD1_SMBCL K_Q
UPD1_SMBD AT_Q
DDR_XDP_ WAN_SMBC LK
DDR_XDP _WAN_SMB DAT
2.2K
2.2K
@2.2K
@2.2K
9
TP
8
+3.3V_CV 2
M9
US H
L9
USH/B
+3.3V_TBT A_FLASH
B5
A5
R7
R8
D D
SKL-U
R9
W3
SML1_SMBDATA
SML1_S MBCLK
03
W2
02
02
01
01
V3
E11 D8
03
C C
MEM_SMBCLK
MEM_SMBD ATA
SML0_S MBCLK
SML0_SMBDATA
1K
1K
DAT_TP_SIO_I 2C_CLK
C12
CLK_TP_SIO_I 2C_DAT
E10
B3
USH_EXPANDER_S MBCLK
E5
USH_EXPANDER_S MBDAT
+3.3V_ALW _PC H
1K
499
499
KBC
00 D7
00
MEC 5105
04
04
05
05
B B
06
06
E7
C3
B4
F7
B6
A12
N10
UPD2_SMBCLK
UPD2_S MBDAT
UPD1_SMBCLK
UPD1_S MBDAT
07
M4
M7
07
C508
C8
08
F6
09
E9
09
10
A A
10
PBAT_CHARGER_S MBCLK
N2
M3
PBAT_CHARGER_S MBDAT
2.2K
2.2K
+3.3V_AL W
100 ohm
100 ohm
4
5
Charger
BATTER Y
CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F391P
LA-F391P
LA-F391P
1
5 70Monday, September 25, 2017
5 70Monday, September 25, 2017
5 70Monday, September 25, 2017
0.2
0.2
0.2
Vinafix.com
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4
3
2
1
For 2LANE EDP,BR/SB12
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
HDMI
PS8338(NON AR)
+1.0VS_VCCIO
C C
B B
CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>
CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>
CPU_DP1_CTRL_CLK
12
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23
EDP_COMP
CPU_DP1_CTRL_CLK<23>
CPU_DP1_CTRL_DATA<23>
CPU_DP2_CTRL_CLK<22>
CPU_DP2_CTRL_DATA<22>
@
T120
PAD~D
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max l ength=100 mils .
CPU@
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
EDP_RCOMP
KBL-RU42_BGA1356
KBL-RU42_BGA1356.olb
CPU@
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
KBL-RU42_BGA1356
KBL-R U4+2
DDI
DISPLAY SIDEBANDS
KBL-R U4+2
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
Rev_0.1
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
Rev_0.1
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD
RSVD
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
1 OF 20
C37
D37
C32
D32
C29
D29
B26
A26
CSI2_COMP
E13
TBT_FORCE_PWR
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
EMMC_RCOMP
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
CPU_DP1_AUXN
G50
CPU_DP1_AUXP
F50
E48
F48
CPU_DP3_AUXN
G46
CPU_DP3_AUXP
F46
L9
L7
L6
N9
L10
R12
R11
U13
1 2
RC3 100_0402_1%
1 2
RC4 200_0402_1%
PAD~D
EDP_TXN0 <29>
EDP_TXP0 <29>
EDP_TXN1 <29>
EDP_TXP1 <29>
EDP_AUXN <29>
EDP_AUXP <29>
PAD~D
PAD~D
CPU_DP2_AUXN <22>
CPU_DP2_AUXP <22>
PAD~D
PAD~D
CPU_DP1_HPD <23>
CPU_DP2_HPD <22>
EDP_HPD <29>
PANEL_BKLEN <29>
EDP_BIA_PWM <29>
ENVDD_PCH <29>
@
T19
@
T281
@
T282
@
T1
@
T2
EDP_HPD
1 2
RC1 100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-F391P
LA-F391P
LA-F391P
6 70Tuesday, September 19, 2017
6 70Tuesday, September 19, 2017
6 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For DDR4
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
DDR_A_DQS#[0..7]<20>
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_A_ALERT#
DDR_A_PARITY
+DDR_VREF_A_DQ
CPU@
UC1C
DDR_A_D16
DDR_A_D17
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
T3
PAD~D
@
T4
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20> DDR_B_ODT1 <21>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR 4
DDR_A_ALERT# <20>
DDR_A_PARITY <20>
+DDR_VREF_CA
@
T132
PAD~D
+DDR_VREF_B_DQ
DDR_VTT_CTRL <20>
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
Interleave / Non-Interleaved
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-RU42_BGA1356
KBL-R U4+2
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
3 OF 20
DDR3L / LPDDR3 / DDR4
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
Interleave / Non-Interleaved
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
Rev_0.1
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR4, Ballout for side by side(Non-Interleave)
D D
CPU@
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
C C
B B
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
UC1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
Interleave / Non-Interleaved
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-RU42_BGA1356
KBL-R U4+2
DDR3L / LPDDR3 / DDR4
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
Interleave / Non-Interleaved
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR CH - A
2 OF 20
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
Rev_0.1
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_PAR
DDR_VREF_CA
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_DQS#[0..7]<21>
DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>
DDR_B_MA[0..16]<21>
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA15
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>
DDR_B_CKE0 <21>
DDR_B_CKE1 <21>
@
T5
PAD~D
@
T6
PAD~D
DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_BG0 <21>
DDR_B_ACT# <21>
DDR_B_BG1 <21>
DDR_B_BA0 <21>
DDR_B_BA1 <21>
DDR1_PAR,DDR1_ALERT# for DDR 4
DDR_B_ALERT# <21>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 m il, Spacing=20 mils
Max trace length= 500 m il
A A
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-F391P
LA-F391P
LA-F391P
7 70Tuesday, September 19, 2017
7 70Tuesday, September 19, 2017
7 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
1 2
PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>
D D
RC10 1K_0402_1%CXDP@
1 2
RC11 1K_0402_1%CXDP@
+3.3V_1.8V_ESPI
PCH_SPI_CS#2<37>
PCH_CL_CLK1<33>
PCH_CL_DATA1<33>
PCH_CL_RST1#<33>
ESPI_ALERT#<35>
RC21 8.2K_0402_1%
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
12
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
KBL-RU42_BGA1356
4
UC1E
CPU@
SPI - FLASH
SPI - TOUCH
C LINK
KBL-R U4+2
LPC
3
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
5 OF 20
Rev_0.1
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CLK
PCI_CLK_LPC1
CLKRUN#
SML0_SMBCLK <30>
SML0_SMBDATA <30>
SML1_SMBCLK <35>
SML1_SMBDATA <35>
1 2
RC366 15_0402_5%
1 2
RC367 15_0402_5%
1 2
RC368 15_0402_5%
1 2
RC369 15_0402_5%
ESPI_CS# <35,36>
ESPI_RESET# <35,36>
1 2
RC16EMI@ 15_0402_5%
1 2
RC22
@
2
MEM_SMBCLK
MEM_SMBDATA
ESPI_IO0 <35,36>
ESPI_IO1 <35,36>
ESPI_IO2 <35,36>
ESPI_IO3 <35,36>
22_0402_5%
+3.3V_RUN
6
5
DMN65D8LDW-7_SOT363-6
3 4
QC2B
DMN65D8LDW-7_SOT363-6
ESPI_CLK_5105 <35,36>
For BR/SB
2
1
DDR_XDP_WAN_SMBCLK <14,20,21,41>
QC2A
DDR_XDP_WAN_SMBDAT <14,20,21,41>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
1
+3.3V_RUN
1 2
RC318 2.2K_0402_5%
1 2
RC319 2.2K_0402_5%
+3.3V_ALW_PCH
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
ENABLE
DISABL E
ESPI
LPC
ENABLED
DIABL ED
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
C C
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC28
33P_0402_50V 8J
@EMI@
12
CC7
B B
33_0402_5%
@EMI@
12
RC29
33P_0402_50V 8J
@EMI@
12
CC8
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
+3.3V_SPI
RC30 1K_0402_5%@
RC31 1K_0402_5%@
RC316 1K_0402_5%@
@
1 2
RC37 0_0402_5%
1 2
RC39 33_0402_5%
12
12
12
03/02:follow Intel MOW_2015WW06
PCH_SPI_D2_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_D1_R1<37>
PCH_SPI_D0_R1<37>
PCH_SPI_CLK_R1<37>
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
128Mb Flash ROM
UC5
1
/CS
2
IO1
3
IO2
4
GND
W25Q128JVSIQ_SO8
128Mb Flash ROM
UC6
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
A A
1 2
RC42 0_0402_5%
@
1 2
RC43 33_0402_5%
@
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
@
1
/CS
2
IO1
3
IO2
4
GND
W25Q128JVSIQ_SO8
SOFTWARE TAA
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
@
@
@
@
VCC
IO3
CLK
IO0
VCC
IO3
CLK
IO0
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 2
RC407 33_0402_5%
1 2
RC408 33_0402_5%
1 2
RC409 33_0402_5%
1 2
RC410 33_0402_5%
+3.3V_SPI
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
CC9
1 2
0.1U_0201_10V6K
CC10
@
1 2
0.1U_0201_10V6K
PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
+3.3V_SPI
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
RC32 0_0402_5%
@
+3.3V_ALW_PCH
12
12
12
12
12
12
12
@
RC330_0402_5%
@
RC340_0402_5%
@
RC350_0402_5%
@
RC360_0402_5%
@
RC380_0402_5%
@
RC400_0402_5%
12
RC410_0402_5%
PCH_SPI_CS#1_R1
PCH_SPI_CS#1
PCH_SPI_D0_R1
PCH_SPI_D0
PCH_SPI_D1_R1
PCH_SPI_D1
PCH_SPI_CLK_R1
PCH_SPI_CLK
PCH_SPI_CS#0_R1
PCH_SPI_CS#0
PCH_SPI_D2_R1
PCH_SPI_D2
PCH_SPI_D3_R1
PCH_SPI_D3
@
RF Request
1 2
CC316@RF@ 33P_0402_50V8J
1 2
CC318@RF@ 33P_0402_50V8J
1 2
CC319@RF@ 33P_0402_50V8J
1 2
CC320@RF@ 33P_0402_50V8J
Place c lose CPU side
CONN@
ACES_50506-02041-P01
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
JSPI1
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20K PD
GPP_C5
ESPI@
EC interface
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20k PD
GPP_B23
RC317 150K_0402_5%
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
1 2
RC19 499_0402_1%@
1 2
RC20 499_0402_1%@
1 2
RC27 8.2K_0402_5%LPC@
1 2
RC23 2.2K_0402_5%
1 2
RC25 4.7K_0402_5%
1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-F391P
LA-F391P
LA-F391P
8 70Tuesday, September 19, 2017
8 70Tuesday, September 19, 2017
8 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
HDD_FALL_INT
12
PCH_3.3V_TS_EN
12
SIO_EXT_SCI#
12
LPSS_UART2_RXD
12
LPSS_UART2_TXD
12
TPM_PIRQ#<37>
SIO_EXT_WAKE#
12
LPSS_UART2_RXD
12
LPSS_UART2_TXD
12
5
MEDIACARD_IRQ#<31>
RC560 0_0402_5%
RC561 0_0402_5%
@
12
12
Reser ve
HDD_FALL_INT<41>
PCH_3.3V_TS_EN<29>
RC405 100K_0402_5%@
SBIOS_TX<36>
I2C1_SDA_TP<45>
I2C1_SCK_TP<45>
+3.3V_RUN
RC370 10K_0402_5%
RC282 100K_0402_5%@
RC237 10K_0402_5%
RC402 49.9K_0402_1%@
D D
RC403 49.9K_0402_1%@
+3.3V_ALW_PCH
RC283 10K_0402_5%
RC330 49.9K_0402_1%@
RC331 49.9K_0402_1%@
C C
ONE_DIMM#
TPM_PIRQ#_R
NRB_BIT
HDD_FALL_INT
SIO_EXT_SCI#
BBS_BIT6
GPP_C8
12
TYPEC_CON_SEL1
TYPEC_CON_SEL2
LPSS_UART2_RXD
LPSS_UART2_TXD
4
3
2
1
For BR/SB UMA
UC1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
KBL-RU42_BGA1356
CPU@
LPSS ISH
KBL-R U4+2
Rev_0.1
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
MEM_INTERLEAVED
AR_DET#
ISH_I2C2_SDA
ISH_I2C2_SCL
9/24: Reserve for embed ded lo cati on ,r ef er I nt el P DG 0. 9
RTD3_CIO_PWR_EN
HDD_EN
CLKDET#
TPM_TYPE
LID_CL#_PCH
ISH_I2C2_SDA <33>
ISH_I2C2_SCL <33>
ISH_UART0_RXD <33>
ISH_UART0_TXD <33>
ISH_UART0_RTS# <33>
ISH_UART0_CTS# <33>
SIO_EXT_WAKE# <35>
@
T18
PAD~D
LCD_CBL_DET# <29>
HDD_EN <41>
@
T258
PAD~D
@
PAD~D
T268
GPP_A GROUP is +1.8V
WWAN
WLAN
ISH_I2C2_SDA
ISH_I2C2_SCL
LCD_CBL_DET#
1 2
RC363 1K_0402_5%
1 2
RC362 1K_0402_5%
1 2
RC287 100K_0402_5%
+1.8V_RUN
+3.3V_RUN
TPM_TYPE
+3.3V_RUN
RC186 4.7K_0402_5%@
NRB_BIT
12
+3.3V_RUN
10K_0402_5%
RC267@
TPM_TYPE no function,Reserve GPIO f or future use,
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Internal 20k PD
B B
+3.3V_ALW_PCH
RC184 8.2K_0402_5%@
BOOT BIOS Dest i nat i on(Bi t 6)
HIGH
LOW(DEFAULT)
Internal 20k PD
A A
No REBOOT
REBOOT ENABLE
BBS_BIT6
12
LPC
SPI
5
1 2
ONE_DIMM#
10K_0402_5%
12
RC268
DIMM Detect
HIGH
LOW
TYPEC_CON_SE L1 LOW
TYPEC_CON_SE L2
1 DIM M
2 DIM M
RC555
@
10K_0402_5%
1 2
12
RC556
@
10K_0402_5%
Vendor TBDTBDF OXCONJAE
+3.3V_ALW_PCH
+3.3V_ALW_PCH+3.3V_ALW_PCH
RC553
@
10K_0402_5%
TYPEC_CON_SEL2TYPEC_CON_SEL1
1 2
12
RC554
@
10K_0402_5%
MEM_INTERLEAVED
RC371
@
10K_0402_5%
1 2
12
10K_0402_5%
RC372
DIMM TYPE
HI GH
AR_DET#
Inter leave
Non-In terleaveLOW
+3.3V_ALW_PCH
RC400
10K_0402_5%
1 2
12
10K_0402_5%
RC401
@
AR_DET#
HI GH NON AR
LOW AR
DELL CONFIDENTIAL/PROPRIETARY
HI GHHI GH
HI GH
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
3
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-F391P
LA-F391P
LA-F391P
LOW
4
LOW
HI GH LOW
RC349 100_0402_1%@
1
1 2
RC349
POP
DEPOP TPM
9 70Tuesday, September 19, 2017
9 70Tuesday, September 19, 2017
9 70Tuesday, September 19, 2017
China TPM
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For NON AR, Breckenridge 12/14/15 UMA
CPU@
UC1H
PCIE / USB3 / SATA
D D
Card Reader RTS5242----->
Ext USB3 Port 1 Charge----->
M.2 3030(WLAN) --->
10/100/1G LAN --->
C C
Spindle HDD--->
M.2 3042(SATA Cache
or/HCA)--->
M2 2280 SSD --->
B B
PCIE_PRX_DTX_N1<31>
PCIE_PRX_DTX_P1<31>
PCIE_PTX_DRX_N1<31>
PCIE_PTX_DRX_P1<31>
USB3_PRX_DTX_N6<43>
USB3_PRX_DTX_P6<43>
USB3_PTX_DRX_N6<43>
USB3_PTX_DRX_P6<43>
PCIE_PRX_DTX_N3<33>
PCIE_PRX_DTX_P3<33>
PCIE_PTX_DRX_N3<33>
PCIE_PTX_DRX_P3<33>
PCIE_PRX_DTX_N4<30>
PCIE_PRX_DTX_P4<30>
PCIE_PTX_DRX_N4<30>
PCIE_PTX_DRX_P4<30>
SATA_PRX_DTX_N0<41>
SATA_PRX_DTX_P0<41>
SATA_PTX_DRX_N0<41>
SATA_PTX_DRX_P0<41>
PCIE_PRX_DTX_N8<33>
PCIE_PRX_DTX_P8<33>
PCIE_PTX_DRX_N8<33>
PCIE_PTX_DRX_P8<33>
1 2
RC45 100_0402_1%
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
PCIE_PRX_DTX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PTX_DRX_N11<39>
PCIE_PTX_DRX_P11<39>
PCIE_PRX_DTX_N12<39>
PCIE_PRX_DTX_P12<39>
PCIE_PTX_DRX_N12<39>
PCIE_PTX_DRX_P12<39>
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL-RU42_BGA1356
KBL-R U4+2
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
Rev_0.1
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USBCOMP
USB2_ID
USB2_VBUSSENSE
USB_OC2#
USB_OC3#
Reser ve
M3042_PCIE#_SATA
M2280_PCIE_SATA#
SATALED#
USB3_PRX_DTX_N1 <25>
USB3_PRX_DTX_P1 <25>
USB3_PTX_DRX_N1 <25>
USB3_PTX_DRX_P1 <25>
USB3_PRX_DTX_N2 <33>
USB3_PRX_DTX_P2 <33>
USB3_PTX_DRX_N2 <33>
USB3_PTX_DRX_P2 <33>
USB3_PRX_DTX_N3 <44>
USB3_PRX_DTX_P3 <44>
USB3_PTX_DRX_N3 <44>
USB3_PTX_DRX_P3 <44>
USB20_N1 <26>
USB20_P1 <26>
USB20_N2 <44>
USB20_P2 <44>
USB20_N4 <33>
USB20_P4 <33>
USB20_N5 <29>
USB20_P5 <29>
USB20_N7 <33>
USB20_P7 <33>
USB20_N8 <29>
USB20_P8 <29>
USB20_N9 <43>
USB20_P9 <43>
USB20_N10 <38>
USB20_P10 <38>
1 2
RC44 113_0402_1%
USB2_ID <26>
1 2
RC338 1K_0402_5%
USB_OC0# <43>
USB_OC1# <44>
HDD_DEVSLP <41>
M3042_DEVSLP <33>
M2280_DEVSLP <40>
HDD_DET# <39,41>
M3042_PCIE#_SATA <35>
M2280_PCIE_SATA# <39,40>
SATALED# <33,40,46>
----->Type-C Port
-----> M.2 3042(LTE)
-----> Ext USB3 Port 2
-----> Typce-C(Non AR)
-----> Ext USB Port 2(LEFT)
-----> M2 3042(WWAN)
-----> Camera
-----> M.2 3030(BT)
-----> LCD Touch
-----> Ext USB Port 1 Charge(RIGHT)
-----> USH
USB2_ID
RC337 10K_0402_5%
1 2
+3.3V_ALW_PCH
USB_OC2#
USB_OC0#
USB_OC1#
USB_OC3#
M2280_PCIE_SATA#
HDD_DET#
SATALED#
M3042_PCIE#_SATA
A A
10K_8P4R_5%
1
2
3
4 5
RPC3
RPC4
4 5
3
2
1
10K_8P4R_5%
8
7
6
+3.3V_RUN
6
7
8
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-F391P
LA-F391P
LA-F391P
10 70Tuesday, September 19, 2017
10 70Tuesday, September 19, 2017
10 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For BR UMA
For KBL-R U22
1M_0402_ 1%
U22@
RC46
21
1 2
1 2
@
RC295 0_0402_5%
For Skylake,YC1 24 MHz (50 Ohm ESR)
For Canno nlake,YC1 38.4 MHz (30 O hm ESR)
546765_546765 _2014WW48_Skylake_MOW_Rev_1 _0
1M_0402_ 1%
U42@
RC421
1 2
1 2
RC422 33_0402_5%U42@
For Skylake,YC3 24 MHz (50 Ohm ESR)
RC54
10M_0402_5%
1 2
1 2
@
RC296 0_0402_5%
SIO_SLP_SUS#
@DS3@
RC441 0_0402_5%
VCCDSW_EN_Q
NDS3@
8/21 can change to 10K for merge to RP
PCH_BATLOW#
AC_PRESENT
INTRUDER#
MPHYP_PWR_EN
VRALERT#
SIO_SLP_LAN#
SUSCLK
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
POWER_SW#_MB<36,46>
D D
CLK_PCIE_N0<33>
WWAN--->
WLAN--->
M.2 SDD--->
LAN--->
Card Reader --->
+3.3V_LAN
C C
RL70 10K_0402_5%@
+3.3V_ALW_DSW
RC323 10K_0402_5%
RC67 1K_0402_5%
+1.0V_VCCST
RC71 1K_0402_5%
+3.3V_ALW_PCH
RC74 10K_0402_5%@
10/6 depop , prevent singal step .
RC411 10K_0402_5%@
B B
+3.3V_1.8V_PGPPA
H_CPUPWRGD VCCST_PWRGD
100P_040 2_50V8J
12
CC300ESD@
A A
ESD Request:place near CPU side
CLK_PCIE_P0<33>
CLKREQ_PCIE#0<33>
CLK_PCIE_N1<33>
CLK_PCIE_P1<33>
CLKREQ_PCIE#1<33>
CLK_PCIE_N3<40>
CLK_PCIE_P3<40>
CLKREQ_PCIE#3<40>
CLK_PCIE_N4<30>
CLK_PCIE_P4<30>
CLKREQ_PCIE#4<30>
CLK_PCIE_N5<31>
CLK_PCIE_P5<31>
CLKREQ_PCIE#5<31>
LAN_WAKE#
12
12
PCH_PCIE_WAKE#
12
VCCST_PWRGD
12
ME_SUS_PWR_ACK
12
PCH_PWROK
12
@
RC551 1K_0402_5%
100P_040 2_50V8J
12
CC301ESD@
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
12
RC189 10K_0402_5%
RC47 10K_0402_5%
RC50 10K_0402_5%
RC59 10K_0402_5%
RC51 10K_0402_5%
RC190 10K_0402_5%
PCH_PLTRST#
SUSACK#_R
RC215
POP
DE-POP
PCH_DPWROK PCH_RSMRST#_AND
0.01UF_04 02_25V7K
1
@
CC266
2
12
12
12
12
12
12
12
12
12
12
12
@
@
TC7SH08FU_SSOP5~D
@
T9
PAD~D
VCCST_PWRGD<14,35,36>
ME_SUS_PWR_ACK<35>
NO Support Deep sleep
Support Deep sleep
1 2
RC215 0_0402_5%
NDS3@
100K_040 2_1%
12
RC220
@RF@
RC3730_0402_5%
@RF@
RC3740_0402_5%
@RF@
RC3760_0402_5%
@RF@
RC3770_0402_5%
@RF@
RC3780_0402_5%
1 2
RC62 0_0402_5%
1 2
RC244 0_0402_5%
+3.3V_ALW_PCH
1
2
UC7
SUSACK#<35>
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
5
P
PCH_PLTRST#_AND
B
4
O
12
A
G
3
100K_0402_5%
PCH_RSMRST#_AND<14,45>
1 2
RC77 1K_0402_5%@
1 2
RC78 60.4_0402_1%
1 2
@
RC444 0_0402_5%
1 2
RC443 0_0402_5%@
12
RC75
10K_0402_5%
PLTRST_LAN# <30>
PCH_PLTRST#_EC <36>
RC65
@
PCH_DPWROK<35>
PCH_PCIE_WAKE#<35,36>
PM_LANPHY_ENABLE<30>
XDP_DBRESET#<14>
+3.3V_RUN
PCH_PLTRST#_AND <31,33,38,40>
PCH_RSMRST#_AND
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
SYS_PWROK<14,35>
PCH_PWROK<56>
ME_SUS_PWR_ACK_R
SUSACK#_R
LAN_WAKE#<30,35>
3.3V_CAM_EN#<29>
RC311 10K_0402_5%
RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%
CPU@
UC1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
KBL-RU42_BGA1356
PCH_PLTRST#
PCH_PLTRST#_AND
PCH_PLTRST#
SYS_RESET#
XDP_DBRESET#
AN10
B5
AY17
A68
B65
B6
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
12
12
12
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
KBL-R U4+2
CLOCK SIGNALS
1 2
RC60 0_0402_5%@
1 2
@
RC325 0_0402_5%
CPU@
UC1K
SYSTEM POWER MANAGEMENT
GPP_B13/PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD
KBL-RU42_BGA1356
1 2
@
RC290 0_0402_5%
+3.3V_RUN
5
1
P
B
2
A
G
3
4
O
74AHC1G09GW_TSSOP5
ME_RESET#
KBL-U / KBL-R U4+2
RSVD_E3/XTAL24_IN
RSVD_C7/XTAL24_OUT
XTAL24_OUT/NC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
KBL-R U4+2
SYS_RESET#_R
UC12@
Rev_0.1
XTAL24_IN/NC_2
GPD8/SUSCLK
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
PLTRST_TPM# <37>
GPP_B11/EXT_PWR_GATE#
RC224 1K_0402_5%
XTAL24_IN_U42_CPU XTAL24_IN_U42
E3
XTAL24_OUT_U42_CPU
C7
XTAL24_IN_U22_CPU
E37
XTAL24_OUT_U22_CPU
E35
CLK_ITPXDP_N
F43
CLK_ITPXDP_P
E43
BA17
SUSCLK
XCLK_BIASREF
E42
PCH_RTCX1
AM18
PCH_RTCX2
AM20
AN18
SRTCRST#
AM16
PCH_RTCRST# <35>
PCH_RTCRST#
CMOS1 must take care sho rt & to uch risk on layout placement
Close to CPU
1 2
RC417 33_0402_5%U42@
1 2
RC418 33_0402_5%U42@
1 2
RC419 33_0402_5%U22@
1 2
RC420 33_0402_5%U22@
1 2
RC297 0_0402_5%@
1 2
RC298 0_0402_5%@
SUSCLK <33,40>
1 2
RC52 2.7K_0402_1%
1 2
RC324 59_0402_1%@
546765_546765 _2014WW48_Skylake_MOW_Rev_1 _0
1 2
RC56 20K_0402_5%
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5%
1 2
CC25 1U_0402_6.3V6K
1
1
SHORT PADS~D
@
CMOS1
2
2
VCCDSW_EN_GPIO<18>
VCCDSW_EN<35>
ALW_PWRGD_3V_5V<45,51>
Support DS3
No Support DS3
'V' mean POP, 'X' mean DE-POP
SIO_SLP_S0#
PCH_BATLOW#
PME#
INTRUDER#
MPHYP_PWR_EN
VRALERT#
SIO_SLP_S0# <17,37,54>
SIO_SLP_S3# <35,36>
SIO_SLP_S4# <17,35,52,55>
SIO_SLP_S5# <35>
SIO_SLP_SUS# <35>
SIO_SLP_LAN# <35,47>
SIO_SLP_WLAN# <35,47>
SIO_SLP_A# <35>
SIO_PWRBTN# <14,35>
AC_PRESENT <35>
@
PAD~D
GPP_B12/SLP_S0#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_B2/VRALERT#
1 2
Rev_0.1
GPD4/SLP_S3#
GPD5/SLP_S4#
SLP_SUS#
SLP_LAN#
GPD6/SLP_A#
GPP_A11/PME#
INTRUDER#
11 OF 20
+3.3V_RUN
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
connect to VCCMPHYGTAON_1P0 enable pin
@
RC291
10K_0402 _5%
1 2
SYS_RESET#
XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC52,depop RC324
For Canno nlake, pop RC324 ,depop RC52
RC439
T115
+RTC_CELL_PCH
@
RC445
1 2
0_0402_5%
RC440RE5 36RC21 5RC441RC4 42
V V V
X
V V V
X X
SYS_RESET#
0.1U_040 2_25V6
@ESD@
12
CC302
ESD Request:place near CPU side
XTAL24_IN_U22
XTAL24_OUT_U22
For KBL-R U42
XTAL24_IN_U42
XTAL24_OUT_U42
PCH_RTCX1
PCH_RTCX2
DC1
NDS3@
2 1
RB751S40T1G_SOD523-2
DC2
NDS3@
RB751S40T1G_SOD523-2
X
X
X
XTAL24_OUT_U22_R
XTAL24_OUT_U42_R
PCH_RTCX2_R
1 2
RC442
1 2
0_0402_5%
RC72 8.2K_0402_5%
RC243 10K_0402_5%
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
3
1
3
1
RC387 10K_0402_5%@
RC73 10K_0402_5%@
RC344 10K_0402_5%@
RC68 10K_0402_5%@
RC48 1K_0402_5%@
U22@
1 2
15P_0402_50V8J
4
U22@
YC1
24MHZ_12PF_X3G024000DC1H
2
U22@
1 2
15P_0402_50V8J
U42@
CC334
1 2
12P_0402_50V8J
4
U42@
YC3
24MHZ_12PF_X3G024000DC1H
2
U42@
CC335
1 2
12P_0402_50V8J
CC23
1 2
15P_0402_50V8J
12
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
PCH_PRIM_EN <17,47,53,54,55>
1 2
1 2
1 2
RC69 1M_0402_5%
1 2
1 2
1 2
1 2
1 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_50506-01841-P01
CC21
CC22
+3.3V_ALW_DSW
+RTC_CELL_PCH
+3.3V_ALW_PCH
+3.3V_ALW
JAPS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY N OTE: THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANS FERRED OR COPIED WITHOUT THE EXPRESS W RITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL 'S EXP RESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-F391P
LA-F391P
LA-F391P
1
11 70Tuesday, September 19, 2017
11 70Tuesday, September 19, 2017
11 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
D D
+1.0V_VCCST
RC79 49.9_0402_1%@
RC80 1K_0402_5%
+1.0V_VCCSTG
RC83 1K_0402_5%
+3.3V_RUN
RC414 10K_0402_5%
RC413 10K_0402_5%
C C
B B
A A
RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
RC404 10K_0402_5%
+3.3V_ALW_PCH
RC346 10K_0402_5%
RC288 10K_0402_5%
+3.3V_ALW_PCH +3.3V_ALW_PCH
RC183 8.2K_0402_5%@
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
Internal 20k PD
H_CATERR#
12
H_THERMTRIP#
12
12
PROCHOT#
TOUCHPAD_INTR#
12
CAM_MIC_CBL_DET#
12
CONTACTLESS_DET#
12
TOUCH_SCREEN_PD#
12
AUD_PWR_EN
12
IR_CAM_DET#
12
HOST_SD_WP#
12
FFS_INT2
12
SIO_EXT_SMI#
12
12
HDA_BIT_CLK_R<34>
12
SPKR
ENABLE
DISABL E
5
KB_DET#
HDA_SYNC_R<34>
HDA_SDOUT_R<34>
HDA_RST#_R<34>
RF@
47P_0402_50V8J
Close to RC93
TOUCH_SCREEN_PD# don't move to RPC,
ME_FWP_PCH
HDA_BIT_CLK_R
1
CC27
2
PECI_EC<35>
PROCHOT#<35,56,59>
H_THERMTRIP#<20,21,36>
TOUCH_SCREEN_PD#<29>
TOUCHPAD_INTR#<35,45>
TOUCH_SCREEN_DET#<29>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMI@
1 2
RC94 33_0402_5%
1 2
RC223 1K_0402_5%
1 2
RC95 33_0402_5%
RC187 4.7K_0402_5%@
FFS_INT2<41>
IR_CAM_DET#<29>
HDA_SDOUT
12
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
DISABLE
ENABLE
1 2
RC84 499_0402_1%
XDP_OBS0_R<14>
XDP_OBS1_R<14>
T10
T11
12
KB_DET#<45>
SPKR<34>
@
@
RC88
PAD~D
PAD~D
12
49.9_0402_1%
4
XDP_OBS2_R
XDP_OBS3_R
SIO_EXT_SMI#
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
12
RC89
RC90
49.9_0402_1%
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<34>
HDA_RST#
FFS_INT2
IR_CAM_DET#
KB_DET#
4
H_CATERR#
PROCHOT#_R
H_THERMTRIP#
EOPIO_RCOMP
12
RC91
49.9_0402_1%
49.9_0402_1%
3
CPU MISC
KBL-R U4+2
KBL-R U4+2
JTAG
PROC_TCK
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
Rev_0.1
PROC_TDI
JTAGX
4 OF 20
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
KBL-RU42_BGA1356
CPU@
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
KBL-RU42_BGA1356
CPU@
AUDIO
RF Request. Place near CPU side (Intel MOW)
1
2
HDA_RST#
CC331
2.2P_0402_50V8C
@RF@
HDA_SDIN0
1
2
CC332
2.2P_0402_50V8C
@RF@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
1
2
3
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
SDIO / SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
HDA_SDOUT
CC333
2.2P_0402_50V8C
@RF@
RC87 1K_0402_5%@
Rev_0.1
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
SD_RCOMP
GPP_F23
7 OF 20
2
CPU_XDP_TCLK XDP_JTAGX
1 2
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
1 2
@
RC328 0_0402_5%
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
+1.0V_VCCSTG
CONTACTLESS_DET#
AUD_PWR_EN
SD_RCOMP
RC96 200_0402_1%
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
0.1U_0402_25V6
@ESD@
12
CC303
1 2
RC86 51_0402_5%@
CAM_MIC_CBL_DET# <29>
CONTACTLESS_DET# <38>
AUD_PWR_EN <34>
SPK_DET# <34>
1 2
0.1U_0402_25V6
12
ESD request,Place near CPU side.
2
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
Service Mode Switch:
Add a switch to M E_FWP signal to unlo ck the ME region and
allow the ent ir e r egi on of the SPI f l ash to be updat ed us i ng FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail )
FLASH DESCRIPTOR SECURITY OVERRIDE
HOST_SD_WP# <31>
@ESD@
CC304
ME_FWP
@
RC221 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
RC222
@
1K_0402_5%
1 2
ME_FWP<35>
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
0.1U_0402_25V6
@ESD@
12
CC305
1 2
RC81 51_0402_5%
1 2
RC82 100_0402_5%
1 2
RC130 51_0402_5%
ME_FWP_PCH
1 2
@
1
H_THERMTRIP#
0.1U_0402_25V6
@ESD@
12
CC312
2
3
4
5
ME_FWP_PCH
SW1
A
B
C
G1
G2
SS3-CMFTQR9_3P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-F391P
LA-F391P
LA-F391P
1
+1.0V_VCCSTG
PROCHOT#
0.1U_0402_25V6
@ESD@
12
CC310
1
0.2
0.2
12 70Tuesday, September 19, 2017
12 70Tuesday, September 19, 2017
12 70Tuesday, September 19, 2017
0.2
Vinafix.com
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] f or SKYLAKE-H CPU C FG strap pin
12
RC113 10K_0402_1%@
CFG0
RC112 10K_0402_1%@
RC110 10K_0402_1%@
12
12
Stall reset sequence
HIGH(DEFAULT)
LOW
C C
RC109 1K_0402_5%
eDP ena ble
HIGH(DEFAULT)
LOW
B B
No stall(N ormal Operat i o n)
sta ll
12
CFG4
Disa bled
Enabl ed
+1.0V_PRIM_XDP
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
1 2
U42@
RC436 0_0402_5%
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
UC1S
E68
CFG[0]
B67
CFG[1]
D65
CFG[2]
D67
CFG[3]
E70
CFG[4]
C68
CFG[5]
D68
CFG[6]
C67
CFG[7]
F71
CFG[8]
G69
CFG[9]
F70
CFG[10]
G68
CFG[11]
H70
CFG[12]
G71
CFG[13]
H69
CFG[14]
G70
CFG[15]
E63
CFG[16]
F63
CFG[17]
E66
CFG[18]
F66
CFG[19]
E60
CFG_RCOMP
E8
ITP_PMODE
AY2
RSVD_AY2
AY1
RSVD_AY1
D1
RSVD_D1
D3
RSVD_D3
K46
RSVD_K46
K45
RSVD_K45
AL25
RSVD_AL25
AL27
RSVD_AL27
C71
RSVD_C71
B70
RSVD_B70
F60
RSVD_F60
A52
RSVD_A52
BA70
RSVD_TP_BA70
BA68
RSVD_TP_BA68
J71
RSVD_J71
J68
RSVD_J68
F65
VSS_F65
G65
VSS_G65
F61
RSVD_F61
E61
RSVD_E61
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
RESERVED SIGNALS-1
Rev_0.1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP
RSVD_TP
MSM#
PROC_SELECT#
19 OF 20
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
1 2
RC120 100K_0402_5%@
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014W W48_S kylake_ MOW_Rev_1_0
PROC_SELECT#:This pin is f or compatibility
with future platforms. It should be unconnected
for KBL
UC1T
@
T12
@
T13
@
T14
@
T15
@
T128
@
T129
@
T130
@
T126
@
T127
ZVM# for SKYLAKE-U 2+3e
@
T113
@
T114
MSM# for SKYLAKE-U 2+3e
+1.0V_VCCST
1/5 2014WW52 MOW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%@
+VCC_1P8+1.8V_PRIM
AW69
AW68
AU56
AW48
U12
U11
1
2
@
H11
CC222
1U_0402_6.3V6K
KBL-RU42_BGA1356
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_U12
RSVD_U11
RSVD_H11
SPARE
Rev_0.1
RSVD_F6
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
C11
B11
A11
D12
C12
F52
KBL-R U4+2
CPU@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-F391P
LA-F391P
LA-F391P
13 70Tuesday, September 19, 2017
13 70Tuesday, September 19, 2017
13 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
@
CC29
5
+1.0V_PRIM_XDP
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124CXDP@
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,35>
RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@
RC5 need to close to JCPU1
1 2
1 2
1K_0402_5%
FIVR_EN
RC217 0_0402_5%@
CFG0
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@
DDR_XDP_WAN_SMBDAT<8,20,21,41>
DDR_XDP_WAN_SMBCLK<8,20,21,41>
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,35>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM
1 2
RC216 0_0603_1%@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,35,36>
PCH_RSMRST#_AND<11,45>
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
4
XDP_PRSNT_PIN1
1 2
RC121 0_0402_5%
1 2
RC122 0_0402_5%@
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
CXDP@
CFG3
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
TDI
+1.0V_PRIM_XDP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
3
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
2
+3.3V_RUN
CC30
12
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<35>
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
GND
GND PAD
1
3
1B
6
2B
8
3B
11
4B
7
15
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
FIVR_EN_R
C C
B B
RC132 150_0402_5%
+1.0V_VCCST
RC218 150_0402_5%@
RC219 10K_0402_5%@
+3.3V_RUN
+1.0V_PRIM_XDP
RC137 3K_0402_5%
RC138 51_0402_5%@
12
FIVR_EN
12
FIVR_EN
12
XDP_DBRESET#
12
CPU_XDP_PREQ#
12
+3.3V_ALW_PCH+1.0VS_VCCIO
RC133
1.5K_0402_5%
1 2
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
0.1U_0402_25V6
12
CC33@
Place near JXDP1.47
Place near JXDP1.48
XDP_DBRESET#
0.1U_0402_25V6
CXDP@
12
CC32
SIO_PWRBTN#
Place near JXDP1.41
+3.3V_ALW_DSW
1.5K_0402_5%
1 2
0.1U_0402_25V6
12
@
RC241
CC269
@
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
0.1U_0402_25V6
@ESD@
12
CC306
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
12
0.1U_0402_25V6
@ESD@
CC307
CPU_XDP_TMS
RC131 51_0402_5%
CPU_XDP_TDI
RC134 51_0402_5%
CPU_XDP_TDO
RC135 100_0402_5%
CPU_XDP_TRST#
RC136@ 51_0402_5%
CPU_XDP_TCLK
RC139 51_0402_5%
XDP_TMS
TDI_XDP
TDO_XDP
1 2
@
RC228 0_0402_5%
1 2
@
RC229 0_0402_5%
1 2
@
RC230 0_0402_5%
1 2
1 2
1 2
1 2
1 2
0.1U_0402_25V6
@ESD@
12
CC308
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-F391P
LA-F391P
LA-F391P
14 70Tuesday, September 19, 2017
14 70Tuesday, September 19, 2017
14 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cach e)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
UC1L
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD
AK32
RSVD
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
CPU POWER 1 OF 4
Rev_0.1
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <56>
RC143 0_0603_5%@
+VCC_CORE
1 2
12
1 2
RC140
RC141
100_0402_1%
100_0402_1%
VCCSENSE <56>
VSSSENSE <56>
+1.0V_VCCSTG
VIDSCLK
RF Request
1 2
CC321@RF@ 33P_0402_50V8J
Place c lose CPU side
PSC(Primary side cap) : Place as close to the pa ckage as possible
BSC(Backside cap) : Place on secondary si de, underneath the pack age
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk ca ps >Power sour ce
B B
SVID ALERT
VIDALERT_N<56>
SVID DATA
A A
VIDSOUT<56>
+1.0V_VCCST
1 2
+1.0V_VCCST
1 2
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors clo se to CPU
RC204 close to CPU 300 - 1500mil s
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors clo se to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-F391P
LA-F391P
LA-F391P
15 70Tuesday, September 19, 2017
15 70Tuesday, September 19, 2017
15 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+VCCGT: 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on p ower page)
+VCC_GT_+VCC_CORE +VCC_GT
UC1M
D D
+VCC_GT_K52
+VCC_GT
+VCC_GT
C C
VCC_GT_SENSE<56>
VSS_GT_SENSE<56>
B B
1 2
@
RC437 0_0402_5%
+VCC_GT
RC161
100_0402_1%
1 2
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
KBL-U / KBL-R U4+2
A48
VCCGT/VCCCORE_5
A53
VCCGT/VCCCORE_6
J43
VCCGT/VCCCORE_44
J45
VCCGT/VCCCORE_45
J46
VCCGT/VCCCORE_46
J48
VCCGT/VCCCORE_47
J50
VCCGT/VCCCORE_48
J52
VCCGT/VCCCORE_49
K48
VCCGT/VCCCORE_57
K50
VCCGT/VCCCORE_58
K52
VCCGT/RSVD_6
A58
VCCGT
A62
VCCGT
A66
VCCGT
AA63
VCCGT
AA64
VCCGT
AA66
VCCGT
AA67
VCCGT
AA69
VCCGT
AA70
VCCGT
AA71
VCCGT
AC64
VCCGT
AC65
VCCGT
AC66
VCCGT
AC67
VCCGT
AC68
VCCGT
AC69
VCCGT
AC70
VCCGT
AC71
VCCGT
J53
VCCGT
J55
VCCGT
J56
VCCGT
J58
VCCGT
J60
VCCGT
K53
VCCGT
K55
VCCGT
K56
VCCGT
K58
VCCGT
K60
VCCGT
L62
VCCGT
L63
VCCGT
L64
VCCGT
L65
VCCGT
L66
VCCGT
L67
VCCGT
L68
VCCGT
L69
VCCGT
L70
VCCGT
L71
VCCGT
M62
VCCGT
N63
VCCGT
N64
VCCGT
N66
VCCGT
N67
VCCGT
N69
VCCGT
J70
VCCGT_SENSE
J69
VSSGT_SENSE
KBL-RU42_BGA1356
KBL-R U4+2
CPU@
CPU POWER 2 OF 4
KBL-U / KBL-R U4+2
VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17
VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22
VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31
VCCGTX_AK52/RSVD_5
Rev_0.1
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on p ower page)
+VCC_GT_AK52
Avoid adding via to ad just DDR trace
So, f l oa t ing pi n of AK70 , BB57, BB66, AU58 , AU63
Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0
+VCC_GT_+VCC_CORE
1 2
@
RC438 0_0402_5%
VCCGTX for KBL-U 2+3e only
+VCC_GT
+VCC_GTX
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-F391P
LA-F391P
LA-F391P
16 70Tuesday, September 19, 2017
16 70Tuesday, September 19, 2017
16 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+5V_ALW
CZ104
@
1 2
4
O
@
1
2
CC253
UZ34
1U_0402_6.3V6K
1
2
+1.2V_MEM
1
2
CC250
1U_0402_6.3V6K
@
RZ119 0_0402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
CC251
1U_0402_6.3V6K
SIO_SLP_S0#
SIO_SLP_S3#
AND
1 2
+VCCPLL_OC source
+1.2V_MEM+1.2V_MEM_CPUCLK
@
1 2
RC231 0_0402_5%
D D
PSC
1
1
2
1
CC177
CC176
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
PSC
22U_0603_6.3V6M
CC294
1
1
2
2
+1.0V_VCCST
C C
PSC
1
2
CC195
1U_0402_6.3V6K
1
CC178
2
10U_0402_6.3V6M
22U_0603_6.3V6M
CC295
1
2
+1.0V_VCCSTG
CC179
10U_0402_6.3V6M
22U_0603_6.3V6M
CC296
BSC
1
2
@
VDDQ: 8.45A
PSC
1
CC297
2
10U_0402_6.3V6M
+VCC_SFR_OC
CC199
1U_0402_6.3V6K
+1.2V_MEM_CPUCLK
1
1
2
2
CC288
1U_0402_6.3V6K
RF Request
+1.2V_MEM
CC322
RF@
2.2P_0402_50V8C
UC1N
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
KBL-RU42_BGA1356
+1.0V_VCCST
CPU@
1
2
CPU POWER 3 OF 4
PSC
CC202
1U_0402_6.3V6K
KBL-R U4+2
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
+VCC_SA
Rev_0.1
AK28
VCCIO
AK30
VCCIO
AL30
VCCIO
AL42
VCCIO
AM28
VCCIO
AM30
VCCIO
AM42
VCCIO
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
1 2
RC168 100_0402_1%
+1.0VS_VCCIO
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <56>
VSA_SEN+ <56>
RC165
1 2
12
RC167
100_0402_1%
VCCIO_SENSE <54>
VSSIO_SENSE <54>
100_0402_1%
VCCSTG_EN
PCH_PRIM_EN<11,47,53,54,55>
SIO_SLP_S4#<11,17,35,52,55>
CZ102 1U_0402_6.3V6K
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
5
1
P
B
2
A
G
3
+1.0VS_VCCIO
PSC
1
2
CC252
12
0.1U_0402_10V7K
TC7SH08FU_SSOP5~D
1U_0402_6.3V6K
+VCC_SFR_OC
6
VOUT
5
GND
S0 S0Ix S3
HI GH
HI GH
HI GH LOW LOW
LOW
HI GH
LOW
LOW
1 2
CZ103 0.1U_0201_10V6K
B B
CZ100 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,35,52,55>
A A
5
+1.0V_VCCST source
12
+1.0V_PRIM
+5V_ALW
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4moh m/6A
TR=12.5us@Vin= 1.05V
VOUT
GND
6
5
4
+1.0V_VCCST_C
PJP1
12
+1.0V_VCCST
PAD-OPEN1x1m
1 2
CZ101 0.1U_0201_10V6K
+1.0V_VCCSTG source
+1.0V_PRIM
VCCSTG_EN
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4moh m/6A
TR=12.5us@Vin= 1.05V
2
VOUT
GND
12
CZ105 1U_0402_6.3V6K
SIO_SLP_S0#<11,37,54>
RUN_ON<35,36,47,54>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
3
UZ35
RZ320 0_0402_5%@
+5V_ALW
+3.3V_ALW
5
1
P
B
2
A
G
3
1 2
4
O
+1.0V_VCCST+1.0V_VCCSTG
1 2
RZ151 0_0603_5%@
pop option with UZ19
1 2
CZ106 0.1U_0201_10V6K
6
5
12
PJP2
PAD-OPEN1x1m
+1.0V_VCCSTG_C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-F391P
LA-F391P
LA-F391P
1
0.2
0.2
17 70Tuesday, September 19, 2017
17 70Tuesday, September 19, 2017
17 70Tuesday, September 19, 2017
0.2
Vinafix.com
5
+1.0V_PRIM
D D
+1.8V_PRIM
C C
+3.3V_ALW_PCH
+1.8V_PRIM
@ESPI@
B B
1 2
@
RC299 0_0603_5%
1 2
@
RC300 0_0402_5%
1 2
@
RC301 0_0402_5%
1 2
@
RC302 0_0402_5%
1 2
@
RC303 0_0402_5%
1 2
@
RC304 0_0402_5%
1 2
RC234 0_0402_5%@
1 2
@
RC235 0_0402_5%
1 2
RC211 0_0402_5%LPC@
1 2
RC212 0_0402_5%
1 2
@
RC305 0_0402_5%
1 2
@
RC306 0_0402_5%
1 2
@
RC307 0_0402_5%
1 2
@
RC308 0_0402_5%
+3.3V_ALW_PCH
1 2
LC1 BLM15GA750SN1D_2P
1
CC215
2
@
1U_0402_6.3V6K
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
close UC1.AF20 and <400mil
+3.3V_1.8V_PGPPA
+3.3V_1.8V_ESPI
PJP4
1 2
+3.3V_PGPPB+3.3V_ALW_PCH
PAD-OPEN1x1m
Must be +1.8V for eSPI I/F
+3.3V_PGPPC
+3.3V_PGPPD
+3.3V_PGPPE
8/28 schematic r eview
LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402)
+3.3V_VCCHDA
1
CC313
2
0.1U_0201_10V6K
close UC1.AJ19 a nd <400mil
A A
1 2
@
RC173 0_0402_5%
close UC1.N20 and <100mil
5
+1.0V_CLK4+1.0V_PRIM
1
CC226
2
@
47U_0805_6.3V6M
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
+1.0V_MPHYGT
close UC1.N15 and CC210 <400mil, C C211 <120mil
1
2
+1.0V_SRAM
1
2
close UC1.K15, UC1.L15 and <100mil
@
1 2
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
1 2
LC2 BLM15GA750SN1D_2P
1
CC225
2
@
47U_0805_6.3V6M
close UC1.V15 and <100mil
1 2
@
RC170 0_0402_5%
close UC1.K19 an d <100mil
4
close UC1.AL1 and <120mil
1
2
CC204
1U_0402_6.3V6K
1
CC210
2
CC211
@
1U_0402_6.3V6K
47U_0805_6.3V6M
CC217
+1.0V_APLLEBB
@
1U_0402_6.3V6K
1
2
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
CC219
2
@
+1.0V_CLK2+1.0V_PRIM
1
CC220
2
@
4
+1.0V_PRIM_CORE+1.0VO_DSW
1
2
close UC1.AB19 an d <400milclose UC1.K17 an d <120mil
CC205
@
1U_0402_6.3V6K
close UC1.AF18 and <400mil
+1.0V_AMPHYPLL
+1.0V_APLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
+1.0V_PRIM
close UC1.N18 and <120mil
CC218
1U_0402_6.3V6K
close UC1.K15 an d <120mil
1
2
CC264
@
1U_0402_6.3V6K
47U_0805_6.3V6M
+1.0V_APLL
1
CC314
2
0.1U_0201_10V6K
47U_0805_6.3V6M
+1.0V_PRIM
1
CC206
2
@
1U_0402_6.3V6K
Support DS3
No Support DS3
3
PCH PWR
UC1O
CPU@
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB_1P0
KBL-RU42_BGA1356
+3.3V_ALW_DSW +3.3V_ALW_PCH
'V' mean POP, 'X' mean DE-POP
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
KBL-R U4+2
CPU POWER 4 OF 4
VCCPRIM_3P3_V19
VCCRTCPRIM_3P3
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
1 2
RC440 0_0402_5%NDS3@
1 2
RC214 0_0402_5%@
1 2
@DS3@
22U_0603_6.3V6M
1
2
RC43 9
V V V
X X
RC439 0_0402_5%
@
22U_0603_6.3V6M
@
CC279
CC280
1
2
RC44 0RE53 6RC215RC441RC442
X
X
V V V
3
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTC_AK19
VCCRTC_BB14
Rev_0.1
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
15 OF 20
+3.3V_ALW_DSW_R
X
X
2
close UC1.AG15 a nd <120mil
Must be +1.8V
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
close UC1.BB10 and <120mil
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
+3.3V_PGPPB
close UC1.AK19 a nd <120mil
+DCPRTC
CORE_VID0 <54>
CORE_VID1 <54>
Take care!!! Note1 on Page 19
QC7
LP2301ALT1G_SOT23-3
123
D
S
499K_0402_1%
12
G
0.1U_0402_25V6K
12
@
CC340
49.9K_0402_1%
RC433
12
L2N7002WT1G_SC-70-3
13
D
QC6
2
G
S
2
close UC1.Y16 and <400mil
+3.3V_PGPPC
1
1
CC265
2
@
2
1U_0402_6.3V6K
close UC1.AA1 and <400mil
+RTC_CELL_PCH
1
2
CC214
0.1U_0201_10V6K
+1.0V_CLK6
1
CC216
2
@
+3.3V_ALW
RC432
100K_0402_5%
RC431
1 2
VCCDSW_EN_GPIO <11>
1
+1.0V_MPHYGT
1 2
@
RC309 0_0603_5%
1 2
@
RC310 0_0603_5%
+3.3V_1.8V_PGPPG
close UC1.AD15 a nd <400mil
1
CC326
2
CC209
close UC1.V19 and <120mil
@
1U_0402_6.3V6K
1
2
CC207
@
1U_0402_6.3V6K
CC270
+3.3V_PGPPE
close UC1.T16 an d <400mil
1
2
1
2
CC213
1U_0402_6.3V6K
0.1U_0201_10V6K
CC208
@
1U_0402_6.3V6K
+1.8V_PRIM
1
2
+3.3V_ALW_PCH
1
2
CC212
1U_0402_6.3V6K
close UC1.A10 an d <120mil
1
2
CC323
RF@
RF Request
1
2
CC324
RF@
2.2P_0402_50V8C
1
CC221
2
@
47U_0805_6.3V6M
2.2P_0402_50V8C
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
1U_0402_6.3V6K
@
close UC1.L19 an d <100mil
+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB
1 2
RC171 0_0402_5%
close UC1.AK17 a nd <120mil
PJP3
1 2
PAD-OPEN1x3m
561280_561280_KBL_UY_PDG_Rev0p9 :
MPHY has defeature
+1.0V_MPHYGT source
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-F391P
LA-F391P
LA-F391P
1
+1.0V_SRAM
+1.0V_APLLEBB
1U_0402_6.3V6K
1
2
CC325
RF@
2.2P_0402_50V8C
1
1
CC223
2
2
CC224
1U_0402_6.3V6K
0.1U_0201_10V6K
+1.0V_MPHYGT+1.0V_PRIM
0.2
0.2
18 70Tuesday, September 19, 2017
18 70Tuesday, September 19, 2017
18 70Tuesday, September 19, 2017
0.2
Vinafix.com
5
4
3
2
1
CPU@
KBL-R U4+2
UC1P
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
D D
C C
B B
VSS
AA65
VSS
AA68
VSS
AB15
VSS
AB16
VSS
AB18
VSS
AB21
VSS
AB8
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD20
VSS
AD21
VSS
AD62
VSS
AD8
VSS
AE64
VSS
AE65
VSS
AE66
VSS
AE67
VSS
AE68
VSS
AE69
VSS
AF1
VSS
AF10
VSS
AF15
VSS
AF17
VSS
AF2
VSS
AF4
VSS
AF63
VSS
AG16
VSS
AG17
VSS
AG18
VSS
AG19
VSS
AG20
VSS
AG21
VSS
AG71
VSS
AH13
VSS
AH6
VSS
AH63
VSS
AH64
VSS
AH67
VSS
AJ15
VSS
AJ18
VSS
AJ20
VSS
AJ4
VSS
AK11
VSS
AK16
VSS
AK18
VSS
AK21
VSS
AK22
VSS
AK27
VSS
AK63
VSS
AK68
VSS
AK69
VSS
AK8
VSS
AL2
VSS
AL28
VSS
AL32
VSS
AL35
VSS
AL38
VSS
AL4
VSS
AL45
VSS
AL48
VSS
AL52
VSS
AL55
VSS
AL58
VSS
AL64
VSS
KBL-RU42_BGA1356
GND 1 OF 3
Rev_0.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
CPU@
UC1Q
AT63
VSS
AT68
VSS
AT71
VSS
AU10
VSS
AU15
VSS
AU20
VSS
AU32
VSS
AU38
VSS
AV1
VSS
AV68
VSS
AV69
VSS
AV70
VSS
AV71
VSS
AW10
VSS
AW12
VSS
AW14
VSS
AW16
VSS
AW18
VSS
AW21
VSS
AW23
VSS
AW26
VSS
AW28
VSS
AW30
VSS
AW32
VSS
AW34
VSS
AW36
VSS
AW38
VSS
AW41
VSS
AW43
VSS
AW45
VSS
AW47
VSS
AW49
VSS
AW51
VSS
AW53
VSS
AW55
VSS
AW57
VSS
AW6
VSS
AW60
VSS
AW62
VSS
AW64
VSS
AW66
VSS
AW8
VSS
AY66
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
BA10
VSS
BA14
VSS
BA18
VSS
BA2
VSS
BA23
VSS
BA28
VSS
BA32
VSS
BA36
VSS
F68
VSS
BA45
VSS
KBL-RU42_BGA1356
KBL-R U4+2
GND 2 OF 3
Rev_0.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17 OF 20
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
CPU@
UC1R
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
KBL-RU42_BGA1356
KBL-R U4+2
GND 3 OF 3
Rev_0.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
18 OF 20
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmenda t i on
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (14/14)
CPU (14/14)
CPU (14/14)
LA-F391P
LA-F391P
LA-F391P
19 70Tuesday, September 19, 2017
19 70Tuesday, September 19, 2017
19 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..16]<7>
Layout No te:
D D
C C
B B
A A
Place near JDIMM1
+1.2V_MEM
10U_0603_10V6M
10U_0603_10V6M
CD2
CD1
12
12
+1.2V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD10
CD9
+0.6V_DDR_VTT
12
DIMM Select
SA01SA1
DIM M1
DIM M2
DIM M3
DIM M4
10U_0603_10V6M
CD3
12
1U_0402_6.3V6K
12
CD11
Layout No te:
Place near
JDIMM1.258
10U_0603_10V6M
CD22
0
0
0
1
0
1
1
10U_0603_10V6M
CD4
12
12
1U_0402_6.3V6K
12
12
CD12
1U_0402_6.3V6K
CD23
1
1
2
2
SA2
0
0
0
0
10U_0603_10V6M
10U_0603_10V6M
CD5
12
1U_0402_6.3V6K
12
CD13
1U_0402_6.3V6K
CD24
10U_0603_10V6M
1U_0402_6.3V6K
CD6
CD14
12
12
12
12
RD4
@
0_0402_5%
@
RD5
0_0402_5%
10U_0603_10V6M
330U_D3_2.5VY_R6M
12
@
CD7
CD8
CD17
12
+
+2.5V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD16
CD15
+DDR_VREF_A_CA
+3.3V_RUN+3.3V_RUN+3.3V_RUN
12
RD6
@
0_0402_5%
12
@
RD7
0_0402_5%
12
12
0.1U_0402_10V6K
1
2
RD8
@
0_0402_5%
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
@
RD9
0_0402_5%
1U_0402_6.3V6K
10U_0603_10V6M
1U_0402_6.3V6K
1
1
CD18
2
2
2.2U_0402_6.3V6M
@
1
CD26
CD25
2
+3.3V_RUN
10U_0603_10V6M
1
1
CD20
CD19
CD21
2
2
DDR_A_CKE0<7>
DDR_A_BG1<7>
DDR_A_BG0<7>
DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_PARITY<7>
DDR_A_CS#0<7>
DDR_A_ODT0<7>
DDR_A_CS#1<7>
DDR_A_ODT1<7>
12
@
RD10
0_0603_5%
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
2.2U_0402_6.3V6M
CD28
1
1
CD27
2
2
DDR_A_D1 DDR_A_D4
DDR_A_D0
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D2
DDR_A_D13
DDR_A_D12
DDR_A_D15
DDR_A_D14
DDR_A_D35
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D34
DDR_A_D44
DDR_A_D45
DDR_A_D42
DDR_A_D46
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PARITY
DDR_A_BA1
DDR_A_BA1<7>
DDR_A_CS#0
DDR_A_MA14
DDR_A_MA14<7>
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
T51PAD~D @
DDR_A_D30
DDR_A_D26
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D27
DDR_A_D29
DDR_A_D21
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D63
+3.3V_RUN_DIMM1
+2.5V_MEM
JDIMM1
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
DM3_n/DBI3_n75DQS3_t
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LCN_DAN05-Q0406-0103
CONN@
LINK DAN05-Q0406-010 3 DONE
VSS11
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
VSS20
VSS22
VSS24
VSS26
VSS27
VSS29
VSS31
VSS33
VSS35
DQS3_c
VSS38
VSS40
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
ACT_n
ALERT_n
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A10/AP
VDD14
RAS_n/A16
VDD16
CAS_n/A15
VDD18
C0/CS2_n/NC
VREFCA
VSS54
VSS56
VSS58
DM4_n/DBI4_n
VSS59
VSS61
VSS63
VSS65
VSS67
DQS5_c
DQS5_t
VSS70
VSS72
VSS74
VSS76
VSS78
DM6_n/DBI6_n
VSS79
VSS81
VSS83
VSS85
VSS87
DQS7_c
DQS7_t
VSS90
VSS92
VSS94
VSS2
VSS4
VSS6
VSS7
VSS9
DQ12
DQ14
DQ11
DQ20
DQ16
DQ22
DQ18
DQ28
DQ24
DQ31
DQ27
CKE1
VDD2
VDD4
VDD6
VDD8
DQ36
DQ32
DQ39
DQ35
DQ45
DQ41
DQ47
DQ43
DQ53
DQ48
DQ54
DQ50
DQ60
DQ57
DQ63
DQ59
GND2
+1.2V_MEM+1.2V_MEM
2
4
DQ4
6
8
DQ0
10
12
14
16
DQ6
18
20
DQ2
22
24
26
28
DQ8
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
A11
122
A7
124
126
A5
128
A4
130
132
A2
134
136
138
140
142
144
A0
146
148
150
BA0
152
154
156
158
A13
160
162
164
166
SA2
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
SDA
256
SA0
258
VTT
260
SA1
262
DDR_A_D5
DDR_A_D3
DDR_A_D7
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D32
DDR_A_D36
DDR_A_D39
DDR_A_D33
DDR_A_D40
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D43
DDR_DRAMRST#_R
DDR_A_CKE1
DDR_A_ACT#
DDR_A_ALERT#
DDR_A_MA11
DDR_A_MA7
DDR_A_MA5
DDR_A_MA4
DDR_A_MA2
JDIMM1_EVENT#
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_MA0
DDR_A_MA10
DDR_A_BA0
DDR_A_MA16
DDR_A_MA15
DDR_A_MA13
DIMM1_SA2
DDR_A_D31
DDR_A_D25
DDR_A_D28
DDR_A_D24
DDR_A_D20
DDR_A_D16
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D23
DDR_A_D53
DDR_A_D52
DDR_A_D54
DDR_A_D55
DDR_A_D61
DDR_A_D60
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D59DDR_A_D62
DIMM1_SA0
DIMM1_SA1
DDR_A_CKE1 <7>
DDR_A_ACT# <7>
DDR_A_ALERT# <7>
DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>
DDR_A_BA0 <7>
T50 PAD~D@
+DDR_VREF_A_CA
DDR_XDP_WAN_SMBDAT <8,14,21,41>DDR_XDP_WAN_SMBCLK<8,14,21,41>
+0.6V_DDR_VTT
1 2
@
RD12 0_0402_5%
1
CD29
@
0.1U_0402_25V6
2
JDIMM1_EVENT#
+DDR_VREF_A_CA
DDR_VTT_CTRL<7>
1 2
RD14 1K_0402_5%@
UD1
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
VCC
6/8 Change to SA00007WE00 DII
+1.2V_MEM
+1.2V_MEM
5
4
Y
+1.2V_MEM
470_0402_1%
12
RD11
1K_0402_1%
12
RD15
1 2
RD17 2_0402_1%
1K_0402_1%
12
RD16
1 2
CD32@ 0.1U_0201_10V6K
1 2
RD19 100K_0402_5%
DDR_DRAMRST#
24.9_0402_1%
H_THERMTRIP# <12,21,36>
0.6V_DDR_VTT_ON <52>
RD18
0.022U_0402_16V7K
12
12
+3.3V_RUN
DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>
+DDR_VREF_CA+DDR_VREF_A_CA
CD31
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
DDR4
DDR4
DDR4
LA-F391P
LA-F391P
LA-F391P
1
20 70Tuesday, September 19, 2017
20 70Tuesday, September 19, 2017
20 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..16]<7>
Layout No te:
10U_0603_10V6M
CD34
12
1U_0402_6.3V6K
12
CD42
+0.6V_DDR_VTT
SA01SA1
0
1
0
1
Place near JDIMM2
10U_0603_10V6M
10U_0603_10V6M
CD35
CD36
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD44
CD43
10U_0603_10V6M
CD54
1
12
2
SA2
0
0
0
0
0
0
1
10U_0603_10V6M
CD37
12
12
1U_0402_6.3V6K
12
12
CD45
Layout No te:
Place near
JDIMM2.258
1U_0402_6.3V6K
1U_0402_6.3V6K
CD55
1
2
12
RD20
@
0_0402_5%
12
@
RD21
0_0402_5%
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
12
@
CD40
CD38
CD39
CD49
12
12
+
+2.5V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD48
CD47
CD46
CD56
+3.3V_RUN+3.3V_RUN+3.3V_RUN
12
12
@
RD22
RD24
@
0_0402_5%
0_0402_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
12
12
@
RD23
@
RD25
0_0402_5%
0_0402_5%
1U_0402_6.3V6K
1
CD50
2
+DDR_VREF_B_CA
1
2
+3.3V_RUN
1U_0402_6.3V6K
1
CD51
2
0.1U_0402_10V6K
CD57
1
2
12
@
RD26
0_0603_5%
2.2U_0402_6.3V6M
12
CD59
D D
+1.2V_MEM
10U_0603_10V6M
CD33
12
+1.2V_MEM
1U_0402_6.3V6K
12
CD41
C C
B B
DIMM Select
DIM M1
DIM M2
DIM M3
*
DIM M4
A A
10U_0603_10V6M
1
1
CD52
2
2
2.2U_0402_6.3V6M
@
CD58
+3.3V_RUN_DIMM2
0.1U_0201_10V6K
1
CD60
2
4
3
2
1
For DDR4
JDIMM2
DDR_B_D1
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D6
DDR_B_D13
DDR_B_D12
DDR_B_D14
DDR_B_D15
DDR_B_D33
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D39
DDR_B_D38
DDR_B_D42
DDR_B_D43
10U_0603_10V6M
CD53
DDR_B_CKE0<7>
DDR_B_BG1<7>
DDR_B_BG0<7>
DDR_B_CLK0<7>
DDR_B_CLK#0<7>
DDR_B_PARITY<7>
DDR_B_CS#0<7>
DDR_B_ODT0<7>
DDR_B_CS#1<7>
DDR_B_ODT1<7>
DDR_B_BA1<7>
DDR_B_MA14<7>
+2.5V_MEM
T55PAD~D @
+3.3V_RUN_DIMM2
DDR_B_D44
DDR_B_D45
DDR_B_CKE0
DDR_B_BG1
DDR_B_BG0
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_PARITY
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D54
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
DM3_n/DBI3_n75DQS3_t
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LCN_DAN05-Q0406-0103
CONN@
LINK DAN05-Q0406-010 3 DONE
VSS11
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
VSS20
VSS22
VSS24
VSS26
VSS27
VSS29
VSS31
VSS33
VSS35
DQS3_c
VSS38
VSS40
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
ACT_n
ALERT_n
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A10/AP
VDD14
RAS_n/A16
VDD16
CAS_n/A15
VDD18
C0/CS2_n/NC
VREFCA
VSS54
VSS56
VSS58
DM4_n/DBI4_n
VSS59
VSS61
VSS63
VSS65
VSS67
DQS5_c
DQS5_t
VSS70
VSS72
VSS74
VSS76
VSS78
DM6_n/DBI6_n
VSS79
VSS81
VSS83
VSS85
VSS87
DQS7_c
DQS7_t
VSS90
VSS92
VSS94
VSS2
VSS4
VSS6
VSS7
VSS9
DQ12
DQ14
DQ11
DQ20
DQ16
DQ22
DQ18
DQ28
DQ24
DQ31
DQ27
CKE1
VDD2
VDD4
VDD6
VDD8
DQ36
DQ32
DQ39
DQ35
DQ45
DQ41
DQ47
DQ43
DQ53
DQ48
DQ54
DQ50
DQ60
DQ57
DQ63
DQ59
GND2
+1.2V_MEM+1.2V_MEM
2
4
DQ4
6
8
DQ0
10
12
14
16
DQ6
18
20
DQ2
22
24
26
28
DQ8
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
A11
122
A7
124
126
A5
128
A4
130
132
A2
134
136
138
140
142
144
A0
146
148
150
BA0
152
154
156
158
A13
160
162
164
166
SA2
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
SDA
256
SA0
258
VTT
260
SA1
262
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D3
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D11
DDR_B_D10
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_DRAMRST#_R
DDR_B_CKE1
DDR_B_ACT#
DDR_B_ALERT#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA5
DDR_B_MA4
DDR_B_MA2
JDIMM2_EVENT#
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_MA0
DDR_B_MA10
DDR_B_BA0
DDR_B_MA16
DDR_B_MA15
DDR_B_MA13
DIMM2_SA2
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_B_D53
DDR_B_D48
DDR_B_D50
DDR_B_D51
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DIMM2_SA0
DIMM2_SA1
DDR_B_CKE1 <7>
DDR_B_ACT# <7>
DDR_B_ALERT# <7>
DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>
DDR_B_BA0 <7>
T54 PAD~D@
+DDR_VREF_B_CA
DDR_XDP_WAN_SMBDAT <8,14,20,41>DDR_XDP_WAN_SMBCLK<8,14,20,41>
+0.6V_DDR_VTT
+DDR_VREF_B_CA
JDIMM2_EVENT#
1 2
RD27 1K_0402_5%@
1
2
+DDR_VREF_B_CA
CD61
@
0.1U_0402_25V6
DDR_DRAMRST#_R <20>
+1.2V_MEM
1K_0402_1%
12
RD28
1 2
RD30 2_0402_1%
1K_0402_1%
12
RD29
H_THERMTRIP# <12,20,36>
0.022U_0402_16V7K
CD62
12
24.9_0402_1%
12
RD31
+DDR_VREF_B_DQ
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
DDR4
DDR4
DDR4
LA-F391P
LA-F391P
LA-F391P
1
21 70Tuesday, September 19, 2017
21 70Tuesday, September 19, 2017
21 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
A
B
C
D
E
+3.3V_RUN
SW2_DP1_AUXN
RV70 100K_0402_5%
RV72 100K_0402_5%
1 1
RV73 1M_0402_5%
RV75 1M_0402_5%
RV76 100K_0402_5%
RV78 100K_0402_5%
@
@
RV81
RV79
1 2
2 2
3 3
4.7K_0402_5%
12
RV82
RV80
@
@
4.7K_0402_5%
12
SW2_DP3_AUXN
12
SW2_DP1_CADET
12
SW2_DP3_CADET
12
SW2_DP1_AUXP
12
SW2_DP3_AUXP
12
CPU_DP2_P0<6>
+3.3V_RUN
@
@
RV89
RV87
RV85
RV83
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
12
12
RV84
@
@
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
12
RV86
4.7K_0402_5%
4.7K_0402_5%
12
RV88
RV90
@
4.7K_0402_5%
4.7K_0402_5%
@
@
RV93
RV91
1 2
1 2
4.7K_0402_5%
12
12
RV92
@
4.7K_0402_5%
RV95
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
12
RV94
RV96
@
@
4.7K_0402_5%
4.7K_0402_5%
SW2_PS8338_P0
SW2_PS8338_P1
SW2_PS8338_SW
SW2_PS8338_PEQ
SW2_PS8338_CFG0
SW2_PS8338_PC10
SW2_PS8338_PC11
SW2_PS8338_PC20
SW2_PS8338_PC21
12
CPU_DP2_N0<6>
CPU_DP2_P1<6>
CPU_DP2_N1<6>
CPU_DP2_P2<6>
CPU_DP2_N2<6>
CPU_DP2_P3<6>
CPU_DP2_N3<6>
CPU_DP2_CTRL_CLK<6>
CPU_DP2_CTRL_DATA<6>
for support TMDS signal need contact SCL/SDA to P22,23
CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>
CV62 CV61 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
0.01UF_0402_25V7K
12
CV81
CV86 0.1U_0201_10V6K
CV87 0.1U_0201_10V6K
CV88 0.1U_0201_10V6K
CV89 0.1U_0201_10V6K
CV90 0.1U_0201_10V6K
CV91 0.1U_0201_10V6K
CV92 0.1U_0201_10V6K
CV93 0.1U_0201_10V6K
1 2
CV94 0.1U_0201_10V6K
1 2
CV95 0.1U_0201_10V6K
0.01UF_0402_25V7K
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_DP2_HPD<6>
0.1U_0201_10V6K
CV83
1
1
CV82
2
2
+3.3V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
CV85
CV84
1
2
CPU_DP2_P0_C
CPU_DP2_N0_C
CPU_DP2_P1_C
CPU_DP2_N1_C
CPU_DP2_P2_C
CPU_DP2_N2_C
CPU_DP2_P3_C
CPU_DP2_N3_C
T204@ PAD~D
T223@ PAD~D
SW2_PS8338_P1
SW2_PS8338_P0
CPU_DP2_AUXP_C
CPU_DP2_AUXN_C
SW2_PS8338_CFG0
SW2_PS8338_PC10
SW2_PS8338_PC11
SW2_PS8338_PC20
SW2_PS8338_PC21
UV7
5
21
30
51
57
6
7
9
10
12
13
15
16
4
3
2
1
60
22
23
24
25
59
58
56
55
54
53
11
19
52
61
PS8338BQFN60GTR-A0_QFN60_5X9
For Breckenridge 12/14/15
Priority: Type-C -> VGA
VDD33
VDD33
VDD33
VDD33
VDD33
IN_D0p
IN_D0n
IN_D1p
IN_D1n
IN_D2p
IN_D2n
IN_D3p
IN_D3n
IN_CA_DET
IN_HPD
I2C_CTL_EN
Pl1/SCL_CTL
Pl0/SDA_CTL
IN_DDC_SCL
IN_DDC_SDA
IN_AUXp
IN_AUXn
CFG0
CFG1
PC10
PC11
PC20
PC21
GND
GND
GND
PAD(GND)
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
OUT1_D2p
OUT1_D2n
OUT1_D3p
OUT1_D3n
OUT2_D0p
OUT2_D0n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
OUT2_D3p
OUT2_D3n
PEQ
CEXT
REXT
SW
PD
50
49
47
46
45
44
42
41
40
39
37
36
35
34
32
31
26
27
28
29
SW2_DP1_CADET
43
48
SW2_DP3_CADET
33
38
SW2_PS8338_SW
18
SW2_PS8338_PEQ
8
14
17
20
RV97
SW2_DP1_P0 <25>
SW2_DP1_N0 <25>
SW2_DP1_P1 <25>
SW2_DP1_N1 <25>
SW2_DP1_P2 <25>
SW2_DP1_N2 <25>
SW2_DP1_P3 <25>
SW2_DP1_N3 <25>
SW2_DP3_P0 <24>
SW2_DP3_N0 <24>
SW2_DP3_P1 <24>
SW2_DP3_N1 <24>
SW2_DP1_AUXP <25,26>
SW2_DP1_AUXN <25,26>
SW2_DP3_AUXP <24>
SW2_DP3_AUXN <24>
SW2_DP1_HPD <25,26>
SW2_DP3_HPD <24>
T224@PAD~D
2.2U_0402_6.3V6M
12
12
CV96
4.99K_0402_1%
-----> TYPE C
-----> VGA
Port switching control or priority configuration. Internal pull down ~150KΩ ,
3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged
SW = H: Port2 has higher priority when both ports are plugged (default)
vender sugguest MUX use LLEQ PEQ=M and PI0=H !!
Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O
PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2
4 4
PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O
PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ( "DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Dat e: Shee t o f
Dat e: Shee t o f
Dat e: Shee t o f
Compal Electronics, Inc.
DP SW2 PS8348B
DP SW2 PS8348B
DP SW2 PS8348B
LA-F391P
LA-F391P
LA-F391P
22 70Tuesday, September 19, 2017
22 70Tuesday, September 19, 2017
22 70Tuesday, September 19, 2017
E
0.2
0.2
0.2
Vinafix.com
0.1U_02 01_10V6K
1
@
CV39
2
+3.3V_RUN
+3.3V_RUN
+5V_RUN
1
AP2330W-7 _SC59-3
IN
UV2
GND2OUT
3
12
RV19@10K_0402_5%
RV10 470_0402_1%
1 2
1 2
RV11 470_0402_1%
1 2
RV12 470_0402_1%
1 2
RV13 470_0402_1%
1 2
RV14 470_0402_1%
1 2
RV15 470_0402_1%
1 2
RV16 470_0402_1%
1 2
RV17 470_0402_1%
1 2
RV18 10K_0402_5%
2
+VHDMI_VCC
0.1U_02 01_10V6K
1
@
2
HDMI_HPD
HDMI_CTRL_DATA
HDMI_CTRL_CLK
HDMI_CEC
HDMI_L_CLKN
HDMI_L_CLKP
HDMI_L_TX_N0
HDMI_L_TX_P0
HDMI_L_TX_N1
HDMI_L_TX_P1
HDMI_L_TX_N2
HDMI_L_TX_P2
HDMI_OB
2
G
For 1.65G HDMI from CPU
10U_060 3_10V6M
CV41
12
CV40
1
HDMI connector
JHDMI1
CONN@
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Utility
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
LOTES_AHDM0046-P002A
LINK AHDM0046-P002A DONE
1
D
QV4
L2N7002WT1G_SC-70-3
S
3
GND4
GND3
GND2
GND1
23
22
21
20
5
D D
C C
CPU_DP1_P0<6>
CPU_DP1_N0<6>
CPU_DP1_P1<6>
CPU_DP1_N1<6>
CPU_DP1_P2<6>
CPU_DP1_N2<6>
CPU_DP1_P3<6>
CPU_DP1_N3<6>
1 2
CV31 0.1U_0402_25V6
1 2
CV32 0.1U_0402_25V6
1 2
CV33 0.1U_0402_25V6
1 2
CV34 0.1U_0402_25V6
1 2
CV35 0.1U_0402_25V6
1 2
CV36 0.1U_0402_25V6
12
0.1U_0402_25V6
CV37
12
0.1U_0402_25V6
CV38
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
EMI@
4
1 2
RV24 5.6_0402_5%EMI@
HCM1012GH900BP_4P
2
2
1
1
@EMI@
1 2
RV25 5.6_0402_5%EMI@
1 2
RV27
HCM1012GH900BP_4P
2
2
1
1
@EMI@
1 2
RV28
1 2
RV30 5.6_0402_5%EMI@
HCM1012GH900BP_4P
2
2
1
1
@EMI@
1 2
RV31
1 2
RV33
HCM1012GH900BP_4P
2
2
1
1
@EMI@
1 2
RV34 5.6_0402_5%EMI@
LV3
LV6
LV9
LV12
3
3
4
4
5.6_0402_5%EMI@
3
3
4
4
5.6_0402_5%EMI@
3
3
4
4
5.6_0402_5%EMI@
5.6_0402_5%
3
3
4
4
HDMI_L_TX_P2
EMI@
RV26
200_0402_5%
1 2
HDMI_L_TX_N2
HDMI_L_TX_P1
EMI@
RV29
200_0402_5%
HDMI_L_TX_N1
1 2
HDMI_L_TX_P0
EMI@
RV32
200_0402_5%
HDMI_L_TX_N0
1 2
HDMI_L_CLKP
EMI@
RV35
200_0402_5%
1 2
HDMI_L_CLKN
3
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
+3.3V_RUN
1M_0402_ 5%
RV20
CPU_DP1_HPD<6>
1 2
G
123
D
S
QV5
L2N7002WT1G_SC-70-3
HDMI_HPD
1 2
RV21 20K_0402_5%
B B
+3.3V_RUN
QV3A
2
DMN65D8LDW-7_SOT363-6
HDMI_CTRL_CLK
1
CPU_DP1_CTRL_CLK<6>
CPU_DP1_CTRL_DATA<6>
5
QV3B
DMN65D8LDW-7_SOT363-6
6
HDMI_CTRL_DATA
34
1 2
RV22 2.2K_0402_5%
1 2
RV23 2.2K_0402_5%
+VHDMI_VCC
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-F391P
LA-F391P
LA-F391P
23 70Tuesday, September 19, 2017
23 70Tuesday, September 19, 2017
23 70Tuesday, September 19, 2017
0.2
0.2
0.2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Vinafix.com
5
4
3
2
1
For Breckenridge 12/14/15
For Realtek Solution
+3.3V_RUN
+3.3V_RUN
D D
RV106 4.7K_0402_5%@
RV107 4.7K_0402_5%@
RV102 100K_0402_5%
C C
12
ISPSCL
12
ISPSDA
SW2_DP3_HPD
12
SW2_DP3_AUXP<22>
SW2_DP3_AUXN<22>
SW2_DP3_P0<22>
SW2_DP3_N0<22>
SW2_DP3_P1<22>
SW2_DP3_N1<22>
60ohm/1A
1 2
LV14 BLM15PX600SN1D_2P
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_VGA
1 2
CV1110.1U_0402_10V7K
1 2
CV1120.1U_0402_10V7K
1 2
CV1070.1U_0402_10V7K
1 2
CV1080.1U_0402_10V7K
1 2
CV1090.1U_0402_10V7K
1 2
CV1100.1U_0402_10V7K
1 2
RV123 4.7K_0402_5%
1 2
RV124 4.7K_0402_5%
1 2
RV620 4.7K_0402_5%
1 2
RV622 4.7K_0402_5%
CLK_DDC2_CRT
DAT_DDC2_CRT
SW2_DP3_HPD<22>
+VCCK_12
SW2_DP3_AUXP_C
SW2_DP3_AUXN_C
SW2_DP3_P0_C
SW2_DP3_N0_C
SW2_DP3_P1_C
SW2_DP3_N1_C
ISPSCL
ISPSDA
SW2_DP3_HPD
UV6
1
AVC33
4
AVCC_12
14
VCC_33
2
AUX_P
3
AUX_N
5
LANE0_P
6
LANE0_N
7
LANE1_P
8
LANE1_N
10
POL1/SPI_CEB
9
POL2
11
GPI1/SPI_CLK
12
GPI2/SPI_SI
13
GPI3/SPI_SO
15
VGA_SCL
16
VGA_SDA
30
SMB_SCL
29
SMB_SDA
32
HPD
RTD2166
RTD2166-CG_QFN32_4X4
VDD_DAC_33
VCCK_12
PVCC_33
HVSYNC_PWR
VSYNC
HSYNC
BLUE_P
GREEN_P
RED_P
LDO_RSTB
EXT_CLK_IN
EXT1.2V_CTRL
GND
EPAD_GND
20
25
26
17
18
19
21
22
23
27
28
31
24
33
+VDD_DAC_33
+VCCK_12
VSYNC_CRT
HSYNC_CRT
BLUE_CRT
GREEN_CRT
RED_CRT
60ohm/1A
+3.3V_RUN
+CRT_VCC
0.1U_0402_25V6
1
2
+3.3V_RUN
12
LV30BLM15PX600SN1D_2P
1
2
4.7U_0402_6.3V6M
CV102
CV101
1
2
Place near UV6.4 Place near UV6.25 Place near UV6.26
+VCCK_12
0.1U_0402_25V6
0.1U_0402_25V6
CV100
CV103
1
2
2.2U_0402_16V6K
0.1U_0402_25V6
CV105
CV104
1
1
2
2
+3.3V_RUN
1
2
0.1U_0402_25V6
CV106
Operation Mode Table
POL1(P10)
10
0
X
X
POL2
(P9)
B B
A A
5
1
ROM EEPROM
4
PJDLC05C_SOT23-3
2
3
@ESD@
DV5
RED_CRT
GREEN_CRT
BLUE_CRT
12
RV116
75_0402_1%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
12
12
RV117
75_0402_1%
3
RV118
75_0402_1%
1
2
12P_0402_50V 8J
CV126
DAT_DDC2_CRT
CLK_DDC2_CRT
HSYNC_CRT
VSYNC_CRT
CV127
1
2
12P_0402_50V 8J
+CRT_VCC
RV119
2.2K_0402_5%
RV650 75_0402_1%EMI@
RV651 75_0402_1%EMI@
LV16 BLM15BB470SN1D_2PEMI@
LV17 BLM15BB470SN1D_2PEMI@
LV18 BLM15BB470SN1D_2PEMI@
1
2
CV128
1 2
1 2
1 2
1 2
12P_0402_50V 8J
RV120
1 2
2.2K_0402_5%
1 2
1 2
RV121
@
1K_0402_5%
CV132
2P_0402_50V8 C~D
1
1
2
RV122
1 2
@
1
2
CV133
1
@
CV129
2
3.3P_0402_50V8C
1 2
1K_0402_5%
1
2
2P_0402_50V8 C~D
2
PJDLC05C_SOT23-3
2
3
@ESD@
DV6
1
1
@
@
CV130
CV131
2
3.3P_0402_50V8C
3.3P_0402_50V8C
+5V_RUN
1
IN
GND2OUT
UV4
AP2330W-7_SC59-3
3
40mils
@
0.1U_0402_16V4Z
CV135
1
2
+CRT_VCC
T87 PAD~D
HSYNC_CONN
VSYNC_CONN
M_ID2#
1
CV134
1U_0402_6.3V6K
2
JCRT-11
RED
GREEN
BLUE
JCRT1
6
11
1
7
12
2
8
13
3
9
14
G
4
16
G
10
17
15
5
CCM_C070546HR015M29CZR
CONN@
Link C070546HR015M29CZR don
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP to VGA & VGA Conn
DP to VGA & VGA Conn
DP to VGA & VGA Conn
LA-F391P
LA-F391P
LA-F391P
24 70Tuesday, September 19, 2017
24 70Tuesday, September 19, 2017
24 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
e
Vinafix.com
5
4
3
2
1
+3.3V_RUN_UT9
1 2
LT11 BLM15PX600SN1D_2P
D D
C C
PS8743B Pin Control Mode
USB HOST faci ng TX channel
De-emphasis setting. Internally pull down at 150k.
Tolerant to VDD_DCI only.
B B
SSDE =
L: -3.5dB Output De-emphasis(default)
H: -6dB Output De-emphasis
+3.3V_RUN
+3.3V_VDD_PIC
0_0603_5%
+3.3V_RUN_UT9
546@
RT308
4.7K_0402_5%
1 2
12
8743@
RT416
4.7K_0402_5%
RT137
@
4.7K_0402_5%
SD028470180
(SSDE/DCI _DATA)
1 2
RT397 0_0603_5%@
1 2
AUX1_SNOOP_EN#
MUX1_SSEQ0
+3.3V_RUN_UT9
@
RT398
TUSB546:(AUX1_SNOOP_ EN#)
Pop RT308, Depop RT416
PS8743:(I2C_E N)
Pin Control mode Depop RT308,Pop RT416
I2C mode Pop RT308,Depop RT416
+3.3V_RUN_UT9
1K_0402_5%
@
RT137
1 2
546@
20K_0402_5%
@
1K_0402_5%
12
12
RT138
RT302
+3.3V_CPS
12
8743@
0.1U_0201_10V6K
10U_0402_6.3V6M
1
CT117
2
(REXT)
MUX1_DPEQ1
RT248
4.99K_0402_1%
SD034499180
CT118
1
2
USB3_PTX_DRX_P1<10>
USB3_PTX_DRX_N1<10>
0.1U_0201_10V6K
CT119
1
2
SW2_DP1_P0<22>
SW2_DP1_N0<22>
SW2_DP1_P1<22>
SW2_DP1_N1<22>
SW2_DP1_P2<22>
SW2_DP1_N2<22>
SW2_DP1_P3<22>
SW2_DP1_N3<22>
TBTA_RX1N<28>
TBTA_RX1P<28>
TBTA_RX2N<28>
TBTA_RX2P<28>
+3.3V_RUN_UT9
1 2
12
0.1U_0201_10V6K
0.1U_0201_10V6K
CT121
CT120
1
2
546@
1 2
1 2
CT103 0.1U_0402_25V6
CT104 0.1U_0402_25V6
1 2
1 2
CT105 0.1U_0402_25V6
CT106 0.1U_0402_25V6
1 2
1 2
CT107 0.1U_0402_25V6
CT108 0.1U_0402_25V6
1 2
1 2
CT109 0.1U_0402_25V6
CT110 0.1U_0402_25V6
1 2
1 2
CT113 0.1U_0402_25V6
CT114 0.1U_0402_25V6
SW2_DP1_HPD<22,26>
for pin control , connect to PD GPIO
Check I2C or Pin c ontrol
1K_0402_5%
@
RT247
546@
20K_0402_5%
@
1K_0402_5%
12
RT248
RT303
TUSB546: Pop RT246,Depop CT122
PS8740: Depop RT246,Pop CT122
PS8743: Depop RT246,Pop CT122(CEXT)
8743@
1 2
RT246 0_0402_5%
@
+3.3V_CPS_R1
SW2_DP1_P0_C
SW2_DP1_N0_C
SW2_DP1_P1_C
SW2_DP1_N1_C
SW2_DP1_P2_C
SW2_DP1_N2_C
SW2_DP1_P3_C
SW2_DP1_N3_C
USB3_PTX_C_DRX_P1
USB3_PTX_C_DRX_N1
1 2
RT380 0_0402_5%
MUX1_USB_EQ0
12
CT1222.2U_0402_6.3V6M
AUX1_SNOOP_EN#
+3.3V_RUN_UT9
1K_0402_5%
1 2
1K_0402_5%
12
UT9
1
VCC
6
VCC
20
VCC
28
VCC
9
DP0p
10
DP0n
12
DP1p
13
DP1n
15
DP2p
16
DP2n
18
DP3p
19
DP3n
31
RX1n
30
RX1p
39
RX2n
40
RX2p
8
SSTXp
7
SSTXn
29
SNK_CAD/DCI_DAT
32
HPDIN/DCI_CLK
41
PAD
TUSB546A_QFN40_4X6
@
RT143
546@
20K_0402_5%
@
12
RT144
RT304
UT9
8743@
PS8743BQFN40GTR-B1_QFN40_4X6
SA00009E910
546@
PS8743B Pin Control Mode
USB Type-C connector facing RX channel receiver
equalization setting;Internally tied to VDD33/2, 3.3V I /O.
CEQ =
L: Compensation for channel loss up to 7dB
H: Compensation for c hannel loss up to 18.5dB
M: Compensation for channel loss up to 11.5dB(default)
EQ1
EQ0
I2C_EN
DPEQ1
DPEQ0/A1
SSEQ1
SSEQ0/A0
FLIP/SCL
CTL0/SDA
CTL1
TX1n
TX1p
TX2p
TX2n
SSRXp
SSRXn
SBU1
SBU2
AUXp
AUXn
35
38
17
2
14
3
11
21
22
23
34
33
37
36
5
4
27
26
24
25
@
4.7K_0402_5%
12
RT412
4.7K_0402_5%
@
12
RT413
TUSB546: Pop RT69,RT90,Depop RT417,RT418
PS8743: Depop RT69,RT90,Pop RT417,RT418
(EQ1=CE_USB ,EQ0=FLI P)
MUX1_USB_EQ1
MUX1_USB_EQ0
MUX1_I2C_EN
MUX1_DPEQ1
MUX1_DPEQ0
MUX1_SSEQ1
MUX1_SSEQ0
MUX1_FLIP_SEL
MUX1_USB_SEL
MUX1_DP_SEL
USB3_PRX_C_DTX_P1
USB3_PRX_C_DTX_N1
TUSB546A_SBU1_R
TUSB546A_SBU2_R
SW2_DP1_AUXP_C
SW2_DP1_AUXN_C
MUX1_USB_EQ1 <26>
MUX1_USB_EQ0 <26>
MUX1_FLIP_SEL <26>
MUX1_USB_SEL <26>
MUX1_DP_SEL <26>
TBTA_TX1N <28>
TBTA_TX1P <28>
TBTA_TX2P <28>
TBTA_TX2N <28>
CT111 0.1U_0402_25V6
CT112 0.1U_0402_25V6
RT132 0_0402_5%8743@
RT133 0_0402_5%8743@
CT115 0.1U_0402_25V68743@
CT116 0.1U_0402_25V68743@
+3.3V_RUN_UT9+3.3V_RUN_UT9
(DPEQ)(CEQ)
MUX1_FLIP_SELMUX1_USB_SEL
PS8743B Pin Control Mode
DP Receiver equalization setting;
Internal tied to VDD33/2, 3.3V I/O.
DPEQ =
L: Compensation for channel loss up to 7dB
H: Compensation for c hannel loss up to 14.5dB
M: Compensation for channel loss up to 10.5dB(default)
1 2
1 2
@
4.7K_0402_5%
12
RT411
4.7K_0402_5%
@
12
RT410
For NON-AR port1
TUSB546: Pop RT300,Depop RT145,RT301
PS8743:Depop RT301,Pop RT145,RT300(change to 0.1uf)(VDD_DCI)
RT145
8743@
0_0402_5%
SD028000080
(VDD_DCI )
MUX1_I2C_EN
I2C Programming or Pin Strap Programming Select,Internally
30k pull-up and 60k pull-down
I2C_EN =
0: Tie 1k to GND,Pin Strap(I2C disable)
R:Tie 20k to GND,TI Test Mode(I2C enabled)
F: Float,TI Test Mode(I2C enabled)
12
12
12
12
USB3_PRX_DTX_P1 <10>
USB3_PRX_DTX_N1 <10>
TBTA_SBU1 <26,28>
TBTA_SBU2 <26,28>
SW2_DP1_AUXP <22,26>
SW2_DP1_AUXN <22,26>
SW2_DP1_AUXN_C
SW2_DP1_AUXP_C
1:Tie 1k to VCC,I2C enabled
1 2
1 2
+3.3V_RUN_UT9
1 2
12
TUSB546A_SBU1_R
TUSB546A_SBU2_R
+3.3V_RUN_UT9
RT131100K_0402_5%
RT130100K_0402_5%
1K_0402_5%
1K_0402_5%
@
RT145
546@
RT300
8743@
8743@
20K_0402_5%
@
12
RT301
RT414
1 2
RT415
1 2
8743@
0.1U_0402_25V6
12
CT213
2M_0402_5%
2M_0402_5%
Ser the USB receiver equalizer gain for upstream facing
SSTXP/N,Internally 30k pull-up and 60k pull-down
SSEQ =
0: Ti e 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
RT135
@
4.7K_0402_5%
SD028470180
(ADDR/ DCICF G) (CDE/DCI _CLK)
MUX1_SSEQ1
RT136
A A
PS8743B Pin Control Mode
DCI mode configuration pin; Internally tied to
VDD33/2, 3.3V I/O.
DCICFG =
L: DCI mode disabled
H: DCI mode enabled
M: Automatic DCI mode entering enabled (default)
@
4.7K_0402_5%
SD028470180
+3.3V_RUN_UT9
1K_0402_5%
@
RT135
1 2
546@
20K_0402_5%
1K_0402_5%
12
12
RT136
PS8743:
I2C Control mode
ADDR: I2C control bus address LSB.
Internally pull down at 150k, 3.3VI/O.
[ADDR] =
L: 0x20/0x21
H: 0x22/0x23
5
@
RT305
Select the DisplayPort receiver equalizer gain ,Internally
30k pull-up and 60k pull-down
DPEQ =
0: Ti e 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
RT139
@
546@
1K_0402_5%
4.7K_0402_5%
SD028470180
PS8743B Pin Control Mode
USB Type-C connector facing TX channel
De-emphasis setting. Internally pull down at 150k.
Tolerant to VDD_DCI only.
CDE =
L: -3.5dB Output De-emphasis(default)
H: -6dB Output De-emphasis
RT139
1 2
20K_0402_5%
@
1K_0402_5%
12
12
RT306
@
RT140
4
Ser the USB receiver equalizer gain for downstream facing
RX1 and RX2 when USB utilized,Internally 30k pull-up and
60k pull-down
USB_EQ =
0: Ti e 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC
+3.3V_RUN_UT9+3.3V_RUN_UT9
1K_0402_5%
@
RT141
MUX1_USB_EQ1MUX1_DPEQ0
1 2
546@
20K_0402_5%
@
1K_0402_5%
12
12
RT142
RT307
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Compal Electronics, Inc.
DP/USB3 Repeater SW TUSB546
DP/USB3 Repeater SW TUSB546
DP/USB3 Repeater SW TUSB546
LA-F391P
LA-F391P
LA-F391P
25 70Tuesday, September 19, 2017
25 70Tuesday, September 19, 2017
25 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
+3.3V_TBTA_FLASH+3.3V_TBTA_FLASH
12
12
RT50
3.3K_0402_5%
D D
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R
C C
B B
A A
12
CT70
.1U_0402_16V7K
TBTA_ROM_HOLD#_PD
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
7
8
JXT_FP241AH-006GAAM
DIV = R2/(R1 +R2)
DIV_m in DIV_m ax
0.00 0.0 8
0.10 0.1 8
0.20 0.2 8
0.30 0.3 8
0.40 0.4 8
0.50 0.5 8
0.60 0.6 8
8
VCC
7
DO(IO1)
HOLD#(IO3)
6
WP#(IO2)
CLK
5
DI(IO0)
GD25Q80CSIGR_SO8
1 2
@
RT54 0_0402_5%
@
1 2
RT55 0_0402_5%
1 2
@
RT56 0_0402_5%
1 2
@
RT57 0_0402_5%
JDB1
1
TBTA_ROM_CLK_PD_R
1
2
TBTA_ROM_DI_PD_R
2
3
TBTA_ROM_DO_PD_R
3
4
TBTA_ROM_CS#_PD_R
4
5
GND
5
6
GND
6
CONN@
Factory D evice
Configur ati on
0
1
2
3
4
5
6
71.0 00.70
UT6
TBTA_ROM_CS#_PD_R
1
TBTA_ROM_DO_PD_R
CS#
2
TBTA_ROM_WP#_PD
3
4
GND
TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD
+3.3V_TBTA_FLASH
Descrip tio n
UFP only
5V @0.9A Sink capa bility with "Ask for Max/" for
anything from 0 .9 -3.0A
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes not su pported
TI VID s upported
UFP only
5V @0.9A Sink capa bility with "Ask for Max/" for
anything from 0 .9 -3.0A
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID s upported
UFP only
5V @3.0A So urce capability
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes not su pported
TI VID s upported
UFP only
5V @3.0A So urce capability
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID s upported
DRP
5V @0 .9-3.0A Sink capab ility
5V @3.0A So urce capability
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes not su pported
TI VID s upported
Accepts data and power role swap s, but does n ot
initia te.
DRP
5V @0 .9-3.0A Sink capab ility
5V @3.0A So urce capability
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes - So urce, C, D, and E
pin configurations.
TI VID s upported
Accepts power role swaps but w ill not initia te.
Accepts data role swap to UFP and can in itiate.
DRP
5V @0 .9-3.0A Sink capab ility
5V @3.0A So urce capability
TBT Alternate Modes no t suppo rted
DisplayPort Alternate Modes - So urce, C, D, and E
pin configurations.
TI VID s upported
Accepts power role swaps but w ill not initia te.
Accepts data role swap to DFP and can in itiate.
Infinite boo t retry from Flas h to Hos t I/F cycles .
12
RT51
3.3K_0402_5%
12
RT52
RT53
3.3K_0402_5%
3.3K_0402_5%
UPD1_SMBCLK<35>
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
12
RT405
@
1M_0402_5%
MUX1_FLIP_SEL_R TBTA_DEBUG3 TBTA_DEBUG4
RT81 100K_0402_5%
RT82 1M_0402_5%
@
Route in pass through manner so AUX can be snooped by 546
+3.3V_TBTA_FLASH
RT95 100K_0402_5%546@
RT96 100K_0402_5%546@
4
UPD1_SMBDAT<35>
UPD1_SMBINT#<35>
12
RT406
@
1M_0402_5%
+3.3V_TBTA_FLASH
10K_0402_1%
RT76
PD1_GPIO8
1 2
12
RT377
43K_0402_1%
UART_MOSI
12
UART_MISO
12
MUX1_FLIP_SEL/MUX1_USB_SEL control by:
GPIO: Pop RT69,RT90;Depop RT37 5,RT376
I2C:Depop RT69,RT90;pop RT375,RT376
TBTA_AUXN_C
12
TBTA_AUXP_C
12
+3.3V_VDD_PIC
126
QT1A
@
DMN66D0LDW-7_SOT363-6
1 2
@
RT58 0_0402_5%
DMN66D0LDW-7_SOT363-6
@
RT59 0_0402_5%
1 2
@
RT60 0_0402_5%
12
8743@
RT407
10K_0402_5%
TI is 3x1uf
MUX1_FLIP_SEL
MUX1_USB_SEL
RT375 0_0402_5%@
RT376 0_0402_5%@
5
QT1B
@
1 2
UPD1_SMBCLK_Q
34
1
CT71
2
2.2U_0402_16V6K
MUX1_USB_EQ0<25>
MUX1_FLIP_SEL<25>
SW2_DP1_HPD<22,25>
USB2_ID<10>
MUX1_DP_SEL<25>
MUX1_USB_SEL<25>
MUX1_USB_EQ1<25>
1 2
1 2
+VCC1V8D_TBTA_LDO
3
UPD1_SMBDAT_Q
UPD1_SMBINT#_R
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO
1
1
CT72
2
2
2.2U_0402_16V6K
EN_PD_HV_1<60>
AC1_DISC#<59,60>
SW2_DP1_AUXP<22,25>
SW2_DP1_AUXN<22,25>
RT97 0_0402_5%@
+3.3V_VDD_PIC
CT73
2.2U_0402_16V6K
+3.3V_TBTA_FLASH
+3.3V_ALW
MUX1_FLIP_SEL
EN_PD_HV_1
UART_MOSI
UART_MISO
T219@ PAD~D
T220@ PAD~D
MUX1_USB_SEL
UPD1_SMBCLK_Q TBTA_DEBUG1
UPD1_SMBDAT_Q
1 2
PJP7
1 2
PAD-OPEN1x1m
+3.3V_TBTA_FLASH
RT66 3.3K_0402_5%@
RT67 3.3K_0402_5%@
RT68 10K_0402_5%@
RT417 0_0402_5%8743@
RT69 0_0402_5%546@
RT71 1M_0402_5%
@
RT74 0_0402_5%
RT75 0_0402_5%@
RT339 0_0402_5%@
USB20_P1<10>
USB20_N1<10>
RT86 1M_0402_5%
1 2
RT87 0_0402_5%@
1 2
RT88 0_0402_5%@
1 2
@
RT89 0_0402_5%
RT90 0_0402_5%546@
RT418 0_0402_5%8743@
1 2
@
1 2
RT92 0_0402_5%
@
RT93 0_0402_5%
1 2
CT80 0.1U_0201_10V6K546@
1 2
CT81 0.1U_0201_10V6K546@
+3.3V_TBTA_FLASH
@
RT98
0_0402_5%
1 2
12
@
RT99
0_0402_5%
+5V_ALW
RT378 10K_0402_5%
RT379 10K_0402_5%
12
12
12
12
12
12
RT700_0402_5%
12
12
RT720_0402_5%
12
RT730_0402_5%
12
12
12
RT84 0_0402_5%@
RT85 0_0402_5%@
12
12
12
@
@
@
PJP8
1 2
PAD-OPEN 1x3m
1
@
CT74
2
1U_0402_16V6K
12
12
UPD1_SMBDAT_Q
UPD1_SMBCLK_Q
UPD1_SMBINT#_R
MUX1_FLIP_SEL_R
EN_PD_HV_1_R
PD1_GPIO2
AC1_DISC#_R
SW2_DP1_HPD_R
OTG_ID
PD1_GPIO6
PD1_GPIO7
PD1_GPIO8
TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD
12
@
RT830_0402_5%
12
12
TBTA_MRESET
TBTA_LSTX_R
TBTA_LSRX_R
TBTA_DEBUG3
TBTA_DEBUG4
TBTA_DEBUG2
TBTA_AUXP_C
TBTA_AUXN_C
TBTA_ROSC
12
RT100
15K_0402_1%
RT63 0_0402_5%
2
TI is 1x47uf+1x0.1uf
1
1
CT75
2
22U_0805_25V6M
+3.3V_VDD_PIC_PDA
1 2
UT5
F1
I2C_ADDR
D1
I2C_SDA1
D2
I2C_SCL1
C1
I2C_IRQ1_N
A5
I2C_SDA2
B5
I2C_SCL2
B6
I2C_IRQ2_N
B2
GPIO0
C2
GPIO1
D10
GPIO2
G11
GPIO3
C10
GPIO4
E10
GPIO5
G10
GPIO6
D7
GPIO7
H6
GPIO8
A3
SPI_CLK
B4
SPI_MOSI
A4
SPI_MISO
B3
SPI_SS_N
L5
USB_RP_P
K5
USB_RP_N
E2
UART_TX
F2
UART_RX
F4
SWD_DATA
G4
SWD_CLK
E11
MRESET
L4
TBT_LSTX/R2P
K4
TBT_LSRX/P2R
L3
DIG_AUD_P/DEBUG3
K3
DIG_AUD_N/DEBUG4
L2
DEBUG1
K2
DEBUG2
J1
AUX_P
J2
AUX_N
F10
BUSPOWER_N
G2
R_OSC
Link TPS65982D (from SA000 09W200 to SA00009 W210) 08/04
running change from SA0000 9W210 to SA0000AK400 12/31
1
1
CT76
CT78
CT77
2
2
2
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
+5V_ALW_PDA
B11
H1
B1
VDDIO
VIN_3V3
H10
K1
A2
LDO_1V8A
LDO_1V8D
GND
HRESET
GNDE5GND
E7
E6
A1
D6
12
RT101
100K_0402_5%
C11
LDO_BMC
GND
G5
GND
GNDH4GND
H5
A11
PP_5V0
PP_CABLE
GND
GND
GND
E8
B8
D8
0.22U_0402_16V7K
PP_5V0
GNDF6GNDF7GND
D11
PP_5V0
PP_5V0
F8
G6
CT87
E1
GND
F5
+TBTA_Vbus_1
RT64 0_0402_5%@
RT65 0_0402_5%@
HV_GATE1_A
HV_GATE2_A
B10
B7
A10
A9
GNDA6GNDA7GNDA8GND
SENSEP
SENSEN
HV_GATE1B9HV_GATE2
H11
VBUS
J10
VBUS
J11
VBUS
K11
VBUS
H2
VOUT_3V3
G1
LDO_3V3
K6
C_USB_TP
L6
C_USB_TN
K7
C_USB_BP
L7
C_USB_BN
L9
C_CC1
L10
C_CC2
WHEN CONNECT BUSPOWERZ TO GND,
CONNECT ALSO RPD_Gn to C_CCn
K9
RPD_G1
K10
RPD_G2
E4
DEBUG_CTL1
D5
DEBUG_CTL2
K8
C_SBU1
L8
C_SBU2
F11
RESET_N
GND
GND
GNDG7GND
SSH7GNDL1GND
TPS65982DC_BGA96
H8
G8
L11
12
1
RT103
2
@
0_0402_5%
1 2
1 2
+TBTA_Vbus_1
TI has 1x1uf
+3.3V_PDA_VOUT
12
CT82
1U_0603_25V6K
TI has 2x220pf
1 2
1 2
@
RT104 0_0402_5%
@
RT105 0_0402_5%
TBTA_DBG_CTL1
TBTA_DBG_CTL2
TBTA_SBU1_R
TBTA_SBU2_R
PDA_RESET#_R
1
For NON-AR port1
+3.3V_TBTA_FLASH
1
1
CT83
CT84
2
2
1U_0402_16V6K
10U_0603_6.3V6M
TBTA_TOP_P <28>
TBTA_TOP_N <28>
TBTA_BOT_P <28>
TBTA_BOT_N <28>
TBTA_CC1 <28>
TBTA_CC2 <28>
+3.3V_TBTA_FLASH
1 2
RT106 10K_0402_5%
1 2
RT107 10K_0402_5%
12
RT108 0_0402_5%546@
12
RT109 0_0402_5%546@
12
RT1100_0402_5% @
1
2
TBTA_SBU1 <25,28>
TBTA_SBU2 <25,28>
1
CT85
CT86
2
820P_0402_50V7K
820P_0402_50V7K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
[Type C]PD Controller TI
[Type C]PD Controller TI
[Type C]PD Controller TI
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
LA-F391P
LA-F391P
LA-F391P
1
26 70Tuesday, September 19, 2017
26 70Tuesday, September 19, 2017
26 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
+5V_ALW
5
4
3
2
1
DT1
+5V_TBT_VBUS
D D
C C
1N4148WS-L_SOD323-2
1N4148WS-L_SOD323-2
DT3
1 2
1N4148WS-L_SOD323-2
1U_0402_10V6K
1
CT93
2
12
DT2
12
+5V_TBTA_VBUS_D
+5V_PD_VDD
100K_0402_5%
12
3
VOUT
AP2204R-5.0TRG1_SOT89-3
@
0.1U_0201_10V6K
RT393
1
2
UT8
1
VCC
2
GND
CT88
1U_0402_10V6K
1
CT89
2
+TBTA_Vbus_1
1 2
RT111 100K_0402_5%
1U_0603_50V6K
1
CT94
2
UT7
VCC1VOUT
2
GND
EN3ADJ/NC
AP2112K-3.3TRG1_SOT23-5
1
CT90
1U_0402_10V6K
2
5
4
+3.3V_VDD_PIC
2.2U_0402_10V6M
12
12
CT91
0.1U_0402_25V6K
@
CT92
place near UT7
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
[Type C]PD Power
[Type C]PD Power
[Type C]PD Power
LA-F391P
LA-F391P
LA-F391P
27 70Tuesday, September 19, 2017
27 70Tuesday, September 19, 2017
27 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For NON AR Config
D D
+TBTA_VBUS+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS
JUSBC1
A1
GND_A1
A2
TX1+
A3
TX1-
A4
VBUS_A4
A5
CC1
A6
D+_A6
A7
D-_A7
A8
SBU1
A9
A10
A11
A12
1
2
3
TOP
VBUS_A9
RX2RX2+
GND_A12
GND1
GND2
GND3
JAE_DX07BD24JJ2
CONN@
DX07BD24JJ2 LINK DONE
12
CT990.01U_0201_25V6K
12
CT1010.01U_0201_25V6K
TBTA_TX1P_C
TBTA_TX1N_C
TBTA_CC1
TBTA_TOP_P_R
TBTA_TOP_N_R
1 2
TBTA_TX1P<25>
TBTA_TX1N<25>
TBTA_TOP_P<26>
C C
TBTA_TOP_N<26> TBTA_BOT_P <26>
CT95 0.22U_0201_6.3V6K
1 2
CT96 0.22U_0201_6.3V6K
TBTA_CC1<26>
1 2
@EMI@
1 2
RT120 0_0402_5%
@EMI@
RT121 0_0402_5%
TBTA_RX2N<25>
TBTA_RX2P<25>
B12
GND_B12
B11
RX1+
B10
RX1-
B9
VBUS_B9
SBU2
D-_B7
D+_B6
CC2
Bottom
VBUS_B4
TX2-
TX2+
GND_B1
GND4
GND5
GND6
TBTA_SBU2
B8
TBTA_BOT_N_R
B7
TBTA_BOT_P_R
B6
TBTA_CC2TBTA_SBU1
B5
B4
TBTA_TX2N_C
B3
TBTA_TX2P_C
B2
B1
4
5
6
TBTA_RX1P <25>
TBTA_RX1N <25>
1 2
CT100 0.01U_0201_25V6K
TBTA_SBU2 <25,26>
1 2
@EMI@
1 2
RT122 0_0402_5%
@EMI@
RT123 0_0402_5%
TBTA_CC2 <26>TBTA_SBU1<25,26>
1 2
CT102 0.01U_0201_25V6K
12P_0402 _50V8J
RF@
82P_0402 _50V8J
RF@
1
1
CT189
CT190
2
TBTA_BOT_N <26>
12
CT980.22U_0201_6.3V6K
TBTA_TX2N <25>
12
CT970.22U_0201_6.3V6K
TBTA_TX2P <25>
2
2
3
ESD@
L30ESD24VC3-2_SOT23-3
1
DT4
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
DT5, DT6, DT9, DT10, DT13, DT14, DT17,DT18,
change CPN from SC40000AT00 to SC40000DF00 06/07/2017
DT5
RF Request
B B
TBTA_TX1P_C
TBTA_TX1N_C
TBTA_RX2N
TBTA_RX2P
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT6
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT9
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT10
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
TBTA_RX1P
TBTA_RX1N
TBTA_TX2P_C
TBTA_TX2N_C
DT13
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT14
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT17
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT18
ESD@
1 2
AZ5B75-01B_CSP0603P2Y
DT39
TBTA_CC2 TBTA_SBU2
TBTA_CC1
TBTA_TOP_P_R
A A
TBTA_TOP_N_R
ESD@
1
1
2
2
4
4
5
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
5
9
10
9
8
7
7
6
6
TBTA_CC2
TBTA_CC1 TBTA_SBU1
TBTA_TOP_P_R
TBTA_TOP_N_R
TBTA_SBU2
TBTA_SBU1
TBTA_BOT_N_R
TBTA_BOT_P_R
DT40
ESD@
1
1
2
2
4
4
5
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
4
9
10
9
8
7
7
6
6
TBTA_BOT_N_R
TBTA_BOT_P_R
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS S HEET OF ENGINEERING DRAWING A ND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANS FERRED OR COPIED WITHOUT THE EXPRESS W RITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL 'S EXP RESS WRITTEN CONSENT.
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
LA-F391P
LA-F391P
LA-F391P
1
28 70Tuesday, September 19, 2017
28 70Tuesday, September 19, 2017
28 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
LINK 50398-04041-001 DONE
JEDP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D D
+BL_PWR_SRC
12
C C
Close to JEDP1.17~19
BIA_PWM
4.7K_040 2_5%
12
RV1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
ACES_50398-04041-001
CONN@
0.1U_060 3_50V7K
@RF@
CV11
Close to JEDP1.30~31 Close to JEDP1.11 Close t o JEDP1.1 Close t o JEDP1.10
DV1
1
BAT54CW_SOT323-3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+LCDVDD
3
2
+3.3V_TSP
USB20_N5_R
USB20_P5_R
LV1
EMI@
DISP_ON
TOUCH_SCREEN_DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
0.1U_020 1_10V6K
1
@
CV12
2
EDP_BIA_PWM
BIA_PWM_EC
+3.3V_RUN
+3.3V_CAM
CAM_MIC_CBL_DET# <12>
Pin15: LOOP_BACK
+BL_PWR_SRC
1 2
+LCDVDD
+3.3V_CAM
BIA_PWM
BLM15PX221SN1D_2P
EDP_HPD <6>
LCD_TST <35>
CV1 0.1U_0402_25V6
CV2 0.1U_0402_25V6
CV3 0.1U_0402_25V6
CV4 0.1U_0402_25V6
CV5 0.1U_0402_25V6
CV6 0.1U_0402_25V6
LCD_CBL_DET# <9>
0.1U_020 1_10V6K
1
@RF@
CZ1
2
EDP_BIA_PWM <6>
BIA_PWM_EC <35>
TOUCH_SCREEN_PD# <12>
TOUCH_SCREEN_DET# <12>
12
12
12
12
12
12
+3.3V_TSP
0.1U_020 1_10V6K
1
@RF@
CZ2
2
RF Request
+LCDVDD +3.3V_CAM +BL_PWR_SRC
12P_0402 _50V8J
RF@
82P_0402 _50V8J
RF@
12P_0402 _50V8J
12P_0402 _50V8J
RF@
82P_0402 _50V8J
B B
RF@
1
1
1
CV20
2
CV22
CV21
2
2
RF@
82P_0402 _50V8J
1
CV23
2
RF@
1
1
CV24
CV25
2
2
EDP_HPD
RV7 100K_0402_5%@
27P_0402 _50V8J
12
12
CA5@RF@
RF Request
1 2
EDP_AUXN <6>
EDP_AUXP <6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
DISP_ON
4.7K_040 2_5%
12
RV2
4
27P_0402 _50V8J
CA6@RF@
+3.3V_RUN
0.1U_020 1_10V6K
1
@RF@
CA7
2
1
BAT54CW_SOT323-3
+LCDVDD
Reserve for EA
DV2
DMIC0 <34>
DMIC_CLK0 <34>
3
2
223
1
3
1
USB20_N8_R
USB20_P8_R
AZC199-02SPR7 G_SOT23-3
@ESD@
DV4
TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events
ESD depop locat i on
TOUCH_SCREEN_DET#
If touch panel, GPIO Low-> Touch Mic. EQ ;
others the GPIO is High -> No n-Touch Mic.
EQ
PANEL_BKLEN <6>
PANEL_BKEN_EC <35>
+3.3V_RUN
10K_0402 _5%
1 2
3
EMI@
LV27
1 2
EXC24CQ900U_4P
RV8
PCH_3.3V_TS_EN<9>
34
3.3V_TS_EN<35>
RF Request
+3.3V_TSP
12P_0402 _50V8J
RF@
1
CV18
2
USB20_N8 <10>
USB20_P8 <10>
82P_0402 _50V8J
RF@
1
CV19
2
For Touchscreen
@
1 2
RV323 0_0402_5%
@
1 2
RV324 0_0402_5%
2
For 2LANE EDP &3.3V_TSP
For Breckenridge&Steamboat 12
JIR1
1
IR_CAM_DET# <12>
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50208-0060N-P01
CONN@
Link ACES_50208-0060N-P01 done
+3.3V_RUN
100K_040 2_5%
12
RV326
2
G
+PWR_SRC
For Breckenridge 12
10K_0402 _5%
RV6
1 2
1 2
RV400 0_0402_5%
L2N7002 WT1G_SC-70-3
13
D
QV7
S
RF Request
+PWR_SRC
QV8
LP2301ALT1G_SOT23-3
D
S
123
G
0.1U_040 2_25V6K
12
@
CV635
1
100P_040 2_50V8J
RF@
1
CZ3
2
+3.3V_RUN+3.3V_RUN +3.3V_TSP
LCDVDD POWER
WebCAM
3.3V_CAM_EN#<11>
A A
USB20_P5<10>
5
+3.3V_CAM +3.3V_RUN
LP2301ALT1G_SOT23-3
1 2
RZ380 0_0402_5%
EMI@
LZ1
1 2
EXC24CQ900U_4P
QZ1
D
123
34
S
G
0.1U_040 2_25V6K
12
@
CZ200
USB20_P5_R
USB20_N5_R
Backlight POWER
+PWR_SRC
1000P_04 02_50V7K
270K_040 2_5%
CV13
RV4
1 2
0.01U_04 02_50V7K
1
CV14
2
4
1 2
BL_PWR_SRC_ON
1 2
RV5 47K_0402_5%
EN_INVPWR<35>USB20_N5<10>
QV1
S
4 5
G
AO6405_TSOP6
3
L2N7002WT1G_SC-70-3
D
6
2
1
QV2
123
D
+BL_PWR_SRC_P
S
G
PJP13
1 2
PAD-OPEN1x2m
0.1U_060 3_50V7K
12
1 2
0.01_1206_1%
CV15
Co-l ay:
Short PJP13;Depop RZ90
@
RZ90
+BL_PWR_SRC
3
10U_0603_10V6M
PROPRIETARY N OTE: THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANS FERRED OR COPIED WITHOUT THE EXPRESS W RITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL 'S EXP RESS WRITTEN CONSENT.
+LCDVDD +EDP_VDD
CV16
@
12
Co-l ay:
Short PJP12;Depop RZ93
LCD_VCC_TEST_EN<35>
ENVDD_PCH<6>
PJP12
1 2
PAD-OPEN1x1m
@
RZ93
1 2
0.01_1206_1%
2
DV3
2
1
3
BAT54CW_SOT323-3
1
VOUT
2
GND
3
/OC
G524B1T11U_SOT23-5
EN_LCDPWR
+3.3V_ALW
UV24
5
VIN
4
EN
0.01UF_04 02_25V7K
@
CV17
12
100K_040 2_5%
RV3
1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
LA-F391P
LA-F391P
LA-F391P
1
0.2
0.2
29 70Friday, September 22, 2017
29 70Friday, September 22, 2017
29 70Friday, September 22, 2017
0.2
Vinafix.com
5
+3.3V_LAN
RL1@ 10K_0402_5%
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@
D D
PM_LANPHY_ENABLE<11>
+0.9V_LAN
0.1U_0201_10V6K
CL9
1
2
Note :
+1.0V_LAN wil l w ork at 0.95V to 1.15V
C C
TP_LAN_JTAG_TMS
12
TP_LAN_JTAG_TCK
12
CLKREQ_PCIE#4
12
+3.3V_LAN
10K_0402_5%
1 2
@
RL7 0_0402_5%
0.1U_0201_10V6K
@EMI@
0.1U_0201_10V6K
CL8
1
1
CL10
2
2
1 2
10K_0402_5%
12
XTALO_R
27P_0402_50V8J
12
CL13
CLKREQ_PCIE#4<11>
PCIE_PRX_DTX_P4<10>
PCIE_PRX_DTX_N4<10>
PCIE_PTX_DRX_P4<10>
PCIE_PTX_DRX_N4<10>
RL5 @
SMBus Device Address 0xC8
RL9@
1 2
@
RL34 0_0402_5%
YL1
3
IN
OUT
4
GND
GND
25MHZ_18PF_7V25000034
PLTRST_LAN#<11>
CLK_PCIE_P4<11>
CLK_PCIE_N4<11>
SML0_SMBCLK<8>
SML0_SMBDATA<8>
LAN_WAKE#<11,35>
T88@ PAD~D
T89@ PAD~D
12
1
2
12
CLKREQ_PCIE#4
PCIE_PRX_C_DTX_P4
1 2
CL1 0.1U_0402_25V6
PCIE_PRX_C_DTX_N4
1 2
CL2 0.1U_0402_25V6
PCIE_PTX_C_DRX_P4
1 2
CL5 0.1U_0402_25V6
PCIE_PTX_C_DRX_N4
1 2
CL6 0.1U_0402_25V6
RL11
1M_0402_5%
27P_0402_50V8J
CL14
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
LAN_TEST_EN
3.01K_0402_1%
1K_0402_5%
12
12
RL13
RL12
4
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTALO
XTAL_OUT
10
XTALI
XTAL_IN
30
TEST_EN
12
RBIAS
WGI219LM-QREF- A0_QFN48_6X6~D
change to SA00008 1G0L, S IC A32 WGI219LM QREF A0 QFN 48 P PHY
JTAG LE D
MDI_MINUS0
MDI_MINUS1
MDI
PCIE
MDI_MINUS2
MDI_MINUS3
RSVD_VCC3P3_1
SMBU S
MDI_PLUS0
MDI_PLUS1
MDI_PLUS2
MDI_PLUS3
SVR_EN_N
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
Place CL3, CL4 and LL1 close to UL1
LAN_MDIP0
13
LAN_MDIN0
14
LAN_MDIP1
17
LAN_MDIN1
18
LAN_MDIP2
20
LAN_MDIN2
21
LAN_MDIP3
23
LAN_MDIN3
24
6
+RSVD_VCC3P3_1
1
5
4
15
19
29
47
46
37
43
11
40
22
16
8
+REGCTL_PNP10RES_BIAS
7
49
VCT_LAN_R1
Layout Not ic e : Place bea d as
close UL4 as possible
1 2
RL71 2.2_0603_5%
1 2
RL72 2.2_0603_5%
1 2
RL73 2.2_0603_5%
1 2
RL74 2.2_0603_5%
1 2
RL75 2.2_0603_5%
1 2
RL76 2.2_0603_5%
1 2
RL77 2.2_0603_5%
1 2
RL78 2.2_0603_5%
1 2
+3.3V_LAN_OUT
BLM15PX181SN1D_2P
CL11
CL12
0.1U_0201_10V6K
22U_0603_6.3V6M
1
12
2
1 2
Idc_min =50 0m A
DCR=100 mo hm
@
1 2
LL2
EMI@
LL14.7UH_BRC2012T4R7MD_20%
1
2
3
RL30_0402_5%
+0.9V_LAN
0.1U_0201_10V6K
CL3
1 2
+0.9V_LAN
12
2
LAN_MDIP0_L
LAN_MDIN0_L
LAN_MDIP1_L
LAN_MDIN1_L
LAN_MDIP2_L
LAN_MDIN2_L
LAN_MDIP3_L
LAN_MDIN3_L
LAN_ACTLED_YEL#
RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN1
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIP1
RJ45_MDIN0
RJ45_MDIP0
LED_10_GRN#
LED_100_ORG#
RF Reque st
+3.3V_LAN_OUT
@RF@
@RF@
12P_0402_50V8J
82P_0402_50V8J
1
1
CL29
CL30
2
2
1 2
RL14 150_0402_5%
1 2
RL19 150_0402_5%
1 2
RL20 150_0402_5%
470P_0402_50V7K
1
12
CL18
2
LAN_ACTLED_YEL_R#
LED_10_GRN_R#
LED_100_ORG_R#
0.1U_0201_10V6K
+3.3V_LAN
CL19
RJ45 LOM circuit
+3.3V_LAN:20mils
JLOM1
10
Yellow LED-
9
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
SANTA_130456-821
CONN@
Link 130456-821 DONE
GND
GND
RL64.7K_0402_5%
12
10U_0603_10V6M
@
CL4
0.1U_0201_10V6K
22U_0805_6.3V6M
1
CL7
2
+3.3V_LAN
1 2
@
RL80_0603_5%
Place CL28 close to UL1.5
CL28
+3.3V_LAN
1
15
14
When LAN & WLAN are exist at the s ame time , WLAN w ill disa ble
+3.3V_LAN
CL15
@
1 2
0.1U_0201_10V6K
LOM_SPD100LED_ORG#
B B
A A
LOM_SPD10LED_GRN#
LOM_ACTLED_YEL#
+3.3V_LAN
12
RL29
1M_0402_5%
LOM_SPD100LED_ORG#
+3.3V_LAN
12
RL30
1M_0402_5%
LOM_SPD10LED_GRN#
For WLAN can't recogni ze during enable
Unobtrusive mode(BITS152 312)
5
1
P
B
2
A
G
3
QL1A
DMN65D8LDW-7_SOT363-6
126
LED_MASK#
QL1B
DMN65D8LDW-7_SOT363-6
34
5
LED_MASK#
QL2A
DMN65D8LDW-7_SOT363-6
126
LED_MASK#
QL2B
DMN65D8LDW-7_SOT363-6
34
5
4
O
UL2
TC7SH08FU_SSOP5~D
LAN_ACTLED_YEL#
LED_MASK# <35,46>
LED_100_ORG#
LED_10_GRN#
LOM_CABLE_DETECT# <35>
12
CL16 0.1U_0201_10V6K
12
CL17 0.1U_0201_10V6K
12
CL20 0.1U_0201_10V6K
12
CL21 0.1U_0201_10V6K
LAN_MDIN3_L
LAN_MDIP3_L
LAN_MDIN1_L
LAN_MDIP1_L
LAN_MDIN2_L
LAN_MDIP2_L
LAN_MDIN0_L
LAN_MDIP0_L
GND
GND
CHASSI S
CHASSI S
TL1
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
TD4-12MX4-
1 2
CL22 10P_1808_3KV8JEMI@
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
350UH_IH-160
24
23
22
21
20
19
18
17
16
15
14
13
Z2805
RJ45_MDIN3
RJ45_MDIP3
Z2807
RJ45_MDIN1
RJ45_MDIP1
Z2806
RJ45_MDIN2
RJ45_MDIP2
Z2808
RJ45_MDIN0
RJ45_MDIP0
+GND_CHASSIS
use 40mil trace if necessary
12
12
12
12
RL15 75_0402_1%
RL17 75_0402_1%
RL18 75_0402_1%
RL16 75_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
LAN Clarkvillie & RJ45
LAN Clarkvillie & RJ45
LAN Clarkvillie & RJ45
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
LA-F391P
LA-F391P
LA-F391P
1
30 70Tuesday, September 19, 2017
30 70Tuesday, September 19, 2017
30 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
A
B
C
D
E
For PCIE Interface
1 1
+3.3V_MMI_IN+3.3V_RUN
PJP14
+3.3V_MMI_AUX
RR19 10K_0402_5%
1 2
PAD-OPEN1x2m
1 2
12
+3.3V_MMI_AUX+3.3V_MMI_IN
R2740_0603_5%
@
MEDIACARD_IRQ#
support D3 Hot(if D3 cold PIN11,P IN27 need Add MOS on/o f f 3 V3AUX)
7/18 Vender sugge st.
PCH_PLTRST#_AND<11,33,38,40>
CLKREQ_PCIE#5<11>
CLK_PCIE_P5<11>
CLK_PCIE_N5<11>
1 2
PCIE_PTX_DRX_P1<10>
PCIE_PTX_DRX_N1<10>
PCIE_PRX_DTX_P1<10>
PCIE_PRX_DTX_N1<10>
CR11 0.1U_0402_25V6
CR12 0.1U_0402_25V6
CR13 0.1U_0402_25V6
CR14 0.1U_0402_25V6
+1.2V_LDO
CR13 close to UR2.10
CR9 CR10 close to UR2.14
4.7U_0603_6.3V6K
1
CR5
12
2
0.1U_0201_10V6K
1 2
1 2
1 2
CR6
MEDIACARD_IRQ#<9>
0.1U_0201_10V6K
+1.8V_RUN_CARD
1
CR7
2
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1
SD/MMCCD#
12
+RREF
RR4
6.2K_0402_1%
+3.3V_MMI_AUX
4.7U_0402_6.3V6M
1
CR1
2
UR1
1
PERST#
2
CLK_REQ#
5
REFCLKP
6
REFCLKN
3
HSIP
4
HSIN
7
HSOP
8
HSON
32
WAKE#
31
MS_INS#
30
SD_CD#
10
AV12
14
DV12S
13
SD_VDD2
9
RREF
1
2
0.1U_0201_10V6K
CR2
27
RTS5242
33
11
3V3_IN
3V3aux
E-PAD
+3.3V_MMI_IN
10U_0402_6.3V6M
0.1U_0201_10V6K
CR4
1
1
CR3
2
2
12
CARD_3V3
18
DV33_18
15
SD/MMCDAT1/RCLK-
SP1
16
SD/MMCDAT0/RCLK+
SP2
17
SD/MMCCLK
SP3
19
SD/MMCCMD
SP4
20
SD/MMCDAT3
SP5
21
SD/MMCDAT2
SP6
29
SDWP
SP7
SD_UHS2_D1P
22
SD_UHS2_D1N
SD_LN1_P
23
SD_LN1_M
SD_UHS2_D0P
26
SD_UHS2_D0N
SD_LN0_P
25
SD_LN0_M
24
+SDREG2
SDREG2
28
GPIO
RTS5242-GR_QFN32_4X4
+DV33_18
7/18 Vender suggest
CR15
SD_GPIO
+3.3V_RUN_CARD
@EMI@
1 2
1U_0402_6.3V6K
12
RR310K_0402_5%
1 2
CR22 1U_0402_6.3V6K
1 2
1 2
@
RR9 0_0402_5%
@
1 2
RR10 0_0402_5%
1 2
RR5 0_0402_5%
1 2
@
RR6 0_0402_5%
1 2
@
RR7 0_0402_5%
@
RR8 0_0402_5%
+3.3V_MMI_AUX
SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R
SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R
@EMI@
5P_0402_50V8C
12
CR21
EMI depop locat i on
RF Reque st
+3.3V_MMI_IN+3.3V_MMI_AUX
@RF@
@RF@
@RF@
12P_0402_50V8J
82P_0402_50V8J
1
1
CR27
CR28
2
2
2 2
@RF@
12P_0402_50V8J
82P_0402_50V8J
1
1
CR25
CR26
2
2
3 3
JSD1
1
DAT2
2
CD/DAT3
3
CMD
4
VDD1
5
CLK
6
VSS
7
DAT0/RCLK+
8
DAT1/RCLK-
9
CD
13
VDD2
14
SWIO
15
VSS
16
D0+
17
D0-
18
VSS
19
D1-
20
D1+
21
VSS
T-SOL_158-1000902614
CONN@
10
GND
11
GND
12
GND
22
GND
23
GND
HOST_S D_W P#
High
Low
SDW P_Q S DW P
High
High
Low
Low
High
High
Low
High
STATUS
Write Protect(SD LOCK)
Write Ena ble
Write Protect(SD& FW LOCK)
Write Protect(FW LOCK)
SD/MMCDAT2_R
QR1
L2N7002WT1G_SC-70-3
1 3
SDWP
D
S
G
HOST_SD_WP#<12>
2
+3.3V_RUN_CARD +1.8V_RUN_CARD
2
CR17
1 2
CR18
1
0.1U_0201_10V6K
4.7U_0603_6.3V6K
+3.3V_RUN_CARD
+1.8V_RUN_CARD
2
CR19
1
0.1U_0201_10V6K
1 2
SD/MMCDAT3_R
SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCCD#
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1N
SD_UHS2_D1P
CR20
4.7U_0603_6.3V6K
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
C
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
Card Reader RTS5242
Card Reader RTS5242
Card Reader RTS5242
LA-F391P
LA-F391P
LA-F391P
E
31 70Tuesday, September 19, 2017
31 70Tuesday, September 19, 2017
31 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
D D
4
3
2
1
C C
B B
A A
NO SUPPORT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCIE REPEATER for M.2 3042
PCIE REPEATER for M.2 3042
PCIE REPEATER for M.2 3042
LA-F391P
LA-F391P
LA-F391P
1
32 70Tuesday, September 19, 2017
32 70Tuesday, September 19, 2017
32 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
+3.3V_WWAN
WWAN_PWR_EN
12
RZ43 47K_0402_5%
D D
support SATA/PCIE
C C
+3.3V_WWAN
.047U_0402_16V7K
.047U_0402_16V7K
12
12
CZ17
CZ18
B B
SIM Card Push-Push
+SIM_PWR
CZ37
A A
100P_0402_50V8J
RF@
12
CZ198
PCIE_PTX_DRX_N8<10>
PCIE_PTX_DRX_P8<10>
33P_0402_50V8J
33P_0402_50V8J
22U_0603_6.3V6M
12
12
12
CZ20
CZ21
CZ19
USB3_PRX_DTX_P2<10>
USB3_PRX_DTX_N2<10>
USB3_PTX_DRX_P2<10>
USB3_PTX_DRX_N2<10>
4.7U_0402_6.3V6M
UIM_RESET
UIM_CLK
12
T-SOL_5-991503004000-6 LINK DON
UIM_CLK
47P_0402_50V8J
12
51_0402_5%
12
5
JSIM1
1
VCC
2
RST
3
CLK
4
RFU1
10
GND
11
GND
12
GND
13
GND
T-SOL_5-991503004000-6
@RF@
CZ38
@RF@
RZ334
NGFF_CONFIG_3<35>
NGFF_CONFIG_0<35>
WWAN_WAKE#<35>
PCIE_PRX_DTX_P8<10>
PCIE_PRX_DTX_N8<10>
1 2
CZ10 0.1U_0402_25V6
1 2
CZ11 0.1U_0402_25V6
CLK_PCIE_N0<11>
CLK_PCIE_P0<11>
NGFF_CONFIG_1<35>
NGFF_CONFIG_2<35>
+3.3V_WWAN
12
12
CI30 0.1U_0402_25V6
12
CI29 0.1U_0402_25V6
CONN@
5
GND
6
VPP
7
I/O
8
RFU2
9
DTSW
14
GND
15
GND
16
GND
UIM_DATA UIM_RESET
USB3_PRX_L_DTX_N2
USB3_PRX_L_DTX_P2
USB3_PTX_L_DRX_N2
USB3_PTX_L_DRX_P2
PCIE_PTX_C_DRX_N8
PCIE_PTX_C_DRX_P8
RF Reque st
47P_0402_50V8J
100P_0402_50V8J
RF@
RF@
12
12
CZ23
CZ24
USB3_PTX_C_DRX_P2
USB3_PTX_C_DRX_N2
UIM_DATA
SIM_DET
+SIM_PWR
@RF@
15K_0402_5%
12
RZ335
33P_0402_50V8J
@RF@
12
CZ39
USB20_P4_L
USB20_N4_L
RZ326 0_0402_5%@RF@
NGFF slot B Key B
12
T225PAD~D @
2000P_0402_50V7K
100U_B2_6.3VM_R35M
RF@
RF@
1
+
CZ25
CZ26
2
1 2
RI27 0_0402_5%@RF@
HCM1012GH900BP_4P
1 2
LI16
RF@
1 2
RI28 0_0402_5%@RF@
1 2
RI29 0_0402_5%@RF@
HCM1012GH900BP_4P
1 2
LI17
RF@
1 2
RI30 0_0402_5%@RF@
E
12
4
JNGFF2
1
CONFIG_3
3
GND_3
5
GND_5
FUL_CARD_PWR_OFF#
7
USB_D_P
9
USB_D_N
11
GND_11
21
CONFIG_0
23
WOWWAN#
25
DPR
27
GND_27
29
USB3.0_TX_N
31
USB3.0_TX_P
33
GND_33
35
USB3.0_RX_N
37
USB3.0_RX_P
39
GND_39
41
PET_N0
43
PET_P0
45
GND_45
47
PER_N0
49
PER_P0
51
GND_51
53
REFCLKN
55
REFCLKP
57
GND_57
59
ANTCTL0
61
ANTCTL1
63
ANTCTL2
65
N/C_65
67
RESET#
69
CONFIG_1
71
GND_71
73
GND_73
75
CONFIG_2
77
GND1
STATE #
W_DISABLE1#
W_DISABLE2#
REF_RFFE2_SCLK
REF_RFFE2_SDATA
CONCR_213BAAA42FA
USB3_PRX_L_DTX_P2
34
USB3_PRX_L_DTX_N2
USB3_PTX_L_DRX_P2
34
USB3_PTX_L_DRX_N2
CONFIG_0 CONFIG_21CONFIG_3 Module Type
0 GND
GND
8
14
HIGH
15
HIGH HIGH
+SIM_PWR
33P_0402_50V8J
@RF@
0.1U_0402_25V6
RF@
1
CZ40
CZ41
2
+3.3V_WWAN
CONN@
2
3.3V_2
4
WWAN_RADIO_DIS#<35>
GPS_DISABLE#<35>
6
8
10
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
WWAN_PWR_EN
WWAN_RADIO_DIS#_R
SLOT2_SATA_LED#
GPS_DISABLE#_R
UIM_RESET
UIM_CLK
UIM_DATA
ISH_I2C2_SCL_R
ISH_I2C2_SDA_R
PCH_PLTRST#_AND
PCIE_WAKE#
RZ132 0_0402_5%@
WWAN_COEX3
WWAN_COEX2
WWAN_COEX1
SIM_DET
USB20_P4<10>
USB20_N4<10>
RN101 0_0402_5%@
RZ76 0_0402_5%@
RZ77 0_0402_5%@
3.3V_4
LED1#
I2S_CLK
I2S_RX
I2S_TX
I2S_WA
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
N/C_38
GNSS_SCL
GNSS_SDA
GNSS_IRQ
SYSCLK
TX_BLANKING
PERST#
CLKREQ#
PEWAKE#
COEX3
COEX2
COEX1
SIM_DETECT
N/C_68
3.3V_70
3.3V_72
3.3V_74
GND2
CONFIG_1 M3042_PCIE#_SATA
GND
GND
GND
HIGH
GND
GND
GND
HIGH
HIGH
RF Reque st
4
3
1 2
9/24: Reserve for embedded loca t i on ,refer I ntel PDG 0. 9
CLKREQ_PCIE#0 <11>
12
RZ128 0_0201_5%@RF@
RZ129 0_0201_5%@RF@
RZ130 0_0201_5%@RF@
1 2
RB751S40T1G_SOD523-2
1 2
RB751S40T1G_SOD523-2
+SIM_PWR
12
12
HOST_DEBUG_TX <35,36>
1 2
1 2
1 2
DZ5
DZ6
SATALED# <10,40,46>
M3042_DEVSLP <10>
ISH_I2C2_SCL <9>
ISH_I2C2_SDA <9>
WLAN_COEX3
WLAN_COEX2
WLAN_COEX1
WWAN_RADIO_DIS#_R
GPS_DISABLE#_R
RF Reque st
1 2
RI47 0_0402_5%@RF@
1 2
GND
GND
GNDHIGH
HIGH
HIGH
MCM1012B900F06BP_4P
LI8
RF@
1 2
RI48 0_0402_5%@RF@
SSD- SATA
SSD-PCIE(2 lane)
WW AN
HCA-PCIE(1 lane)
NA
USB20_P4_L
34
USB20_N4_L
3
High
Low
Low
Low
Low
WLAN
2
for no AR,Brekenridge 12/14/15 UMA/Steamboat
NGFF slot A Key A
JNGFF1
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
WLAN_WIGIG60GHZ_DIS#_R
1 2
MCM1012B900F06BP_4P
LI9
RF@
1 2
RI50 0_0402_5%@RF@
1
GND_1
3
USB_D_P
5
USB_D_N
7
GND_7
DP_MLDIR_GND
DP_ML3N
DP_ML3P
GND_23
DP_ML2N
DP_ML2P
GND_29
DP_HPD
GND_33
PER_P0
PER_N0
GND_39
PET_P0
PET_N0
GND_45
REFCLK_P0
REFCLK_N0
GND_51
CLKREQ0#
PEWAKE0#
GND_57
PER_P1
PER_N1
GND_63
PET_P1
PET_N1
GND_69
REFCLK_P1
REFCLK_N1
GND_75
GND1
CONCR_213AAAA42FA
BT_RADIO_DIS#_R
USB20_P7_L
34
USB20_N7_L
USB20_P7_L
USB20_N7_L
1 2
WLAN_WIGIG60GHZ_DIS#<35>
BT_RADIO_DIS#<35>
CZ12 0.1U_0402_25V6
1 2
CZ13 0.1U_0402_25V6
PCIE_PRX_DTX_P3<10>
PCIE_PRX_DTX_N3<10>
CLK_PCIE_P1<11>
CLK_PCIE_N1<11>
CLKREQ_PCIE#1<11>
PCIE_WAKE#<36,40>
PCIE_PTX_DRX_P3<10>
PCIE_PTX_DRX_N3<10>
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3
PCIE_WAKE#
1 2
DZ1
RB751S40T1G_SOD523-2
1 2
DZ2
RB751S40T1G_SOD523-2
RF Reque st
RI49 0_0402_5%@RF@
USB20_P7<10>
USB20_N7<10>
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
2
CONN@
3.3V_2
3.3V_4
LED1#
LED2#
GND_18
DP_AUXN
DP_AUXP
GND_24
DP_ML1N
DP_ML1P
GND_30
DP_ML0N
DP_ML0P
GND_36
CLink_RST
CLink_DATA
CLink_CLK
COEX3
COEX2
COEX1
SUSCLK(32KHz)
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DATA
I2C_CLK
ALERT#
RESERVED
PERST1#
CLKREQ1#
PEWAKE1#
3.3V_72
3.3V_74
PWR
Rail
+3.3 V
1
+3.3V_WLAN
2
4
6
16
18
20
22
24
26
28
30
32
34
36
GND2
38
40
42
WLAN_COEX3
44
WLAN_COEX2
46
WLAN_COEX1
48
WIGIG_32KHZ
50
PCH_PLTRST#_AND
52
BT_RADIO_DIS#_R
54
WLAN_WIGIG60GHZ_DIS#_R
56
ISH_UART0_RXD_R
58
ISH_UART0_TXD_R
60
ISH_UART0_CTS#_R
62
ISH_UART0_RTS#_R
64
PCH_PLTRST#_AND
66
68
PCIE_WAKE#
70
72
74
9/24: Reserve for embedded loca t i on ,refer I ntel PDG 0. 9
76
+3.3V_WLAN
0.01UF_0402_25V7K
12
CZ28
1
2
+3.3V_WLAN
12
0.1U_0201_10V6K
CZ30
RF Reque st
15P_0402_50V8J
PCH_CL_RST1# <8>
PCH_CL_DATA1 <8>
PCH_CL_CLK1 <8>
@
1 2
RZ56 0_0402_5%
PCH_PLTRST#_AND <11,31,38,40>
RZ78 0_0402_5%@
RZ79 0_0402_5%@
RZ80 0_0402_5%@
RZ81 0_0402_5%@
10U_0603_10V6M
1
12
CZ27
2
Place near JNGFF1.2/JNGFF1.4Place near JNGFF1.72/JNGFF1.74
15P_0402_50V8J
15P_0402_50V8J
RF@
RF@
RF@
CZ35
12
12
CZ33
CZ34
Power Rating TBD
Volta ge
Tolera nce
Primary Power Aux Power
Peak N orma l Nor mal
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
NGFF Card
NGFF Card
NGFF Card
LA-F391P
LA-F391P
LA-F391P
1
SUSCLK <11,40>
12
ISH_UART0_RXD <9>
12
ISH_UART0_TXD <9>
12
ISH_UART0_CTS# <9>
12
ISH_UART0_RTS# <9>
0.1U_0201_10V6K
0.01UF_0402_25V7K
12
4.7U_0603_6.3V6K
1
12
CZ31
CZ29
CZ32
2
15P_0402_50V8J
RF@
CZ36
0.2
0.2
33 70Tuesday, September 19, 2017
33 70Tuesday, September 19, 2017
33 70Tuesday, September 19, 2017
0.2
Vinafix.com
2
7
G1
8
G2
RA58
10K_0402_5%
SPK_DET#
+1.8V_RUN
+5V_RUN_AUDIO
SPK_DE T#
Low
High
1 2
RA3 0_0603_5%
@
BLM15PX600SN1D_2P
HDA_SYNC_R<12>
HDA_SDOUT_R<12>
HDA_SDIN0<12>
+3.3V_RUN_AUDIO_DVDD
+3.3V_RUN_AUDIO
place close to pin20
10U_0603_10V6M
12
LA5
12
place close to pin40
10U_0603_10V6M
12
HDA_BIT_CLK_R<12>
DMIC0<29>
DMIC_CLK0 DMIC_CLK0_CODEC
DMIC_CLK0<29>
RA18 10K_0402_5%
AUD_SENSE_A
SLEEVE
RA6 2.2K_0402_5%
RING2
RA5 2.2K_0402_5%
+1.8V_RUN_AUDIO
0.1U_0201_10V6K
CA58
CA57
1
2
+VDDA_AVDD1
0.1U_0201_10V6K
CA8
1
CA9
2
HDA_SDOUT_R
Place RA9 close to codec
HDA_SDIN0_R
1 2
RA9 33_0402_5%
1 2
RA62 100K_0402_5%
1 2
RA14EMI@ 22_0402_5%
1 2
CA31 1U_0603_10V6K
1 2
AUD_SENSE_B
1 2
RA61 100K_0402_1%
1 2
CA35 2.2U_0402_6.3V6M
1 2
RA44 100K_0402_5%
1 2
CA51 10U_0603_10V6M
1 2
CA25 10U_0603_10V6M
12
+MIC2-VREFO-R
12
+MIC2-VREFO-L
1 2
CA49 1U_0603_10V6K
Place CA29 close to Codec
12
CA29 1U_0603_10V6K
1 2
CA52 10U_0603_10V6M
1 2
CA53 10U_0603_10V6M
UA1
6
I2C DATA
7
I2C CLK
15
SYNC
14
BCLK
17
SDATA-OUT
13
DC DET/EPAD
16
SDATA-IN
11
I2S-MCLK
10
I2S-BCLK
9
I2S-OUT
12
I2S-LRCK
8
I2S-IN
1
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4
GPIO0/DMIC-DATA12
5
GPIO1/DMIC-CLK
2
PD#
PDB
48
JD1
47
JD2
38
VREF
39
LDO1-CAP
32
MIC2-CAP
29
MIC2-VREFO-R
28
MIC2-VREFO-L
25
CPVEE
24
CBN
23
CBP
21
LDO2-CAP
19
LDO3-CAP
+3.3V_RUN_AUDIO_DVDD
0.1U_0201_10V6K
10U_0603_10V6M
CA10
CA61
1
12
2
+3.3V_RUN_AUDIO_IO
10U_0603_10V6M
0.1U_0201_10V6K
CA55
1
12
2
PCBEEP
MIC2-L/RING2
MIC2-R/SLEEVE
LINE1-L
LINE1-R
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R-
SPK-OUT-R+
HPOUT-L
HPOUT-R
5VSTB/AUX MODE
AVDD1
CPVDD/AVDD2
DVDD
DVDD-IO
PVDD1
PVDD2
AVSS1
AVSS2
ALC3254-VA3-CG_MQFN48_6X6
LA14 BLM15PX600SN1D_2P
LA12 BLM15PX600SN1D_2P
CA56
AUD_PC_BEEP
34
30
RING2
SLEEVE/RING2 please keep 40 mi ls trace width
31
SLEEVE
LINE1_L HP_OUT_L
36
CA43 10U_0603_10V6M
LINE1_R HP_OUT_R
35
CA44 10U_0603_10V6M
INT_SPK_L+
42
INT_SPK_L-
43
INT_SPK_R-
44
INT_SPK_R+
45
HP_OUT_L AUD_HP_OUT_L
27
HP_OUT_R AUD_HP_OUT_R
26
33
+VDDA_AVDD1
40
+1.8V_RUN_AUDIO
20
+3.3V_RUN_AUDIO_DVDD
3
+3.3V_RUN_AUDIO_IO
18
+5V_RUN_PVDD_L
41
46
49
G
37
22
2W x 1ch, 4ohm
Internal Speakers Header
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
40 mils trace keep 20 mil spacing
1000P_0402_50V7K
1000P_0402_50V7K
12
1000P_0402_50V7K
1000P_0402_50V7K
12
12
12
CA19@EMI@
CA22@EMI@
CA23@EMI@
1 2
LA6 BLM15PX330SN1D_2PEMI@
1 2
LA7 BLM15PX330SN1D_2PEMI@
1 2
LA8EMI@
1 2
LA9 BLM15PX330SN1D_2PEMI@
CA24@EMI@
PESD5V0U2BT_SOT23-3
PESD5V0U2BT_SOT23-3
2
3
1
SPK_DET#<12>
2
3
@ESD@
@ESD@
DA6
Link ACE S_50271-0060N-001 DONE
DA7
1
INT_SPKR_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_RSPK_DET#
JSPK1
1
1
2
2
3
3
4
4
5
5
6
6
ACES_50271-0060N-001
CONN@
+3.3V_RUN
12
Close to UA1 pin42~45
Close to UA1 pin14
HDA_BIT_CLK_R
33_0402_5%
B B
RA17
@EMI@
10P_0402_50V8J
1 2
12
CA33@EMI@
+3.3V_RUN_AUDIO
Place closely to Pin 48.
AUD_HP_NB_SENSE
12
place close to UA1 pin5
100K_0402_1%
12
RA59
200K_0402_1%
12
RA60
DMIC_CLK0
10P_0402_50V8J
CA54@EMI@
AUD_SENSE_A
12
0.1U_0402_25V6
@
CA41
PK23000U O00 M1
(FG-CPL088 00 0)
PK23000U O00 M2
(PB2610KFG04T- 033 -9MG 1)
Add for solve
pop noise and
detect issue
+3.3V_RUN_AUDIO
12
12
5/9 update
SPKR_R
12
CA27 0.1U_0402_25V6
CA28 0.1U_0402_25V6
1
2
RA57 0_0402_5%
@
RA53 0_0402_5%@
BEEP_R
12
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 m ils trace width
1 2
1 2
330P_0402_50V8J
330P_0402_50V8J
1
CA74
CA73
2
1 2
1 2
+RTC_CELL
+5V_ALW
1
+5V_RUN_PVDD_L
1 2
RA12 1K_0402_5%
1 2
RA13 1K_0402_5%
12
RA716.2_0402_1%
12
RA816.2_0402_1%
place close to pin41 pl ace close to pin46
0.1U_0201_10V6K
10U_0603_10V6M
CA45
1
1
1
CA46
2
2
2
SPKR <12>
BEEP <35>
+3.3V_RUN_AUDIO_DVDD
0.1U_0201_10V6K
CA47
Place CA70 close to code c
RF Reque st RF Req uest RF Request
+5V_RUN_AUDIO +1.8V_RUN +3.3V_RUN_AUDIO+1.8V_RUN_AUDIO
RF@
68P_0402_50V8J
RF@
12P_0402_50V8J
RF@
1
1
CA64
CA63
2
2
33P_0402_50V8J
CA69
1
2
10U_0603_10V6M
1
CA48
2
12P_0402_50V8J
1
2
LA13
1 2
HCB2012KF-121T50_2P
600 Ohm/2A
0.1U_0402_25V6
CA70
12
RF@
68P_0402_50V8J
RF@
1
CA65
CA66
2
5/10 update
SPKR_R
BEEP_R
+5V_RUN_AUDIO
10U_0603_10V6M
0.1U_0201_10V6K
CA60
1
1
CA59
2
2
100P_0402_50V8J
10K_0402_5%
@
12
12
CA72@
RA51
100P_0402_50V8J
10K_0402_5%
@
12
12
RA45
CA62@
12P_0402_50V8J
RF@
68P_0402_50V8J
RF@
1
1
CA67
CA68
2
2
CLASS-D POWER DOWN CONTROL CIRCUIT
1 2
RA48 0_0402_5%
@
21
DA8
+5V_RUN
+5V_ALW
+3.3V_RUN
@
RB751S40T1G_SOD523-2
1 2
RA50 0_0402_5%
@
UZ5
@
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
VOUT2
GPAD
CT1
GND
CT2
PD#
+5V_RUN_AUDIO_UZ5
14
13
12
11
10
9
+3.3V_RUN_AUDIO_UZ5
8
15
+5V_RUN_AUDIO
12
@
@
PJP15@
PAD-OPEN1x1m
1 2
CZ125 0.1U_0201_10V6K@
1 2
CZ126
1 2
CZ127
PJP16@
1 2
PAD-OPEN1x1m
1 2
CZ128 0.1U_0201_10V6K@
NB_MUTE#<35>
HDA_RST#_R<12>
HDA_Link is 3.3V,no need level shift circuit
A A
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.8V_RUN
Reserve for support D3 cold
AUD_PWR_EN<12>
place at AGND and DGND plane
1 2
RA35 0_0402_5%
@
1 2
RA36 0_0402_5%
@
1 2
RA37 0_0402_5%
@
PJP17
1 2
+5V_RUN
+3.3V_RUN +3.3V_RUN_AUDIO
220P_0402_50V7K
1000P_0402_50V7K
+3.3V_RUN_AUDIO
2
PAD-OPEN1x2m
PJP18
1 2
PAD-OPEN1x1m
+5V_RUN_AUDIO
2.5A
500mA
PJP19
1 2
PAD-OPEN1x1m
RING2
AUD_HP_OUT_L
AUD_HP_OUT_R
SLEEVE
EMI@
LA10 BLM15PX330SN1D_2PESD@
LA15 BLM15PX330SN1D_2PEMI@
LA16
LA11 BLM15PX330SN1D_2PESD@
1 2
1 2
1 2
1 2
BLM15PX330SN1D_2P
680P_0402_50V7K
@ESD@
1
CA13
2
RING2_R
AUD_HP_OUT_L1
AUD_HP_OUT_R1
SLEEVE_R
680P_0402_50V7K
@ESD@
2
CA1
1
@EMI@
@ESD@
@EMI@
330P_0402_50V8J
330P_0402_50V8J
1
1
1
CA3
CA2
2
2
2
ESD@
2
3
DA1
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
CA4
1
AUD_HP_NB_SENSE
ESD@
ESD@
2
3
2
3
DA2
DA3
AZ5123-02S.R7G_SOT23-3
PESD5V0U2BT_SOT23-3
1
1
680P_0402_50V7K
1
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
JHP1
7
GND
4
#4 G/M
1
#1 L/R
5
#5
6
#6 AGND
2
#2 R/L
3
#3 M/G
SINGA_2SJ3095-085111F
CONN@
@ESD@
Link 2SJ3095-085111F DONE
CA12
Norm al
Open
HP-Out-Rig ht
HP-Out -Le f t
Nokia-M IC
iPhone-MIC
Global Headset
Universal Jack
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
Codec ALC3253
Codec ALC3253
Codec ALC3253
LA-F391P
LA-F391P
LA-F391P
34 70Tuesday, September 19, 2017
34 70Tuesday, September 19, 2017
34 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
+RTC_CELL
+3.3V_ALW_UE1
+3.3V_ALW
+3.3V_ALW_UE1
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
CE19
1
1
2
2
close to pin G8/M9
RF Reque st
+3.3V_ALW
12P_0402_50V8J
RF@
1
CE59
2
+1.8V_PRIM
C C
+3.3V_ALW
RPE10
8
7
100K_0804_8P4R_5%
1 2
RE95 100K_0402_5%@
B B
1
1
JTAG1 @
@SHORT PADS~D
12
2
2
A A
32 KHz Clock
MEC_XTAL1 MEC_XTAL2
10P_0402_50V8J
32.768KHZ_9PF_X1A000141000200
12
CE28
+3.3V_ALW_UE1
CE20
+3.3V_ALW_UE1
68P_0402_50V8J
RF@
1
CE60
2
PJP20
1 2
1
PAD-OPEN1x1m
CE22
0.1U_0201_10V6K
2
@
1 2
PAD-OPEN1x1m
CV2_ON_R
1
IMVP_VR_ON_EC
2
PCH_ALW_ON
3456
RUN_ON_EC LCD_TST
TBT_RESET_N_EC_R
+3.3V_ALW
100K_0402_5%
RE63
1 2
JTAG_RST#
1U_0402_6.3V6K
100_0402_1%
12
CE30
RE65@
MEC_XTAL2_R
YE1
1 2
PJP21
+3.3V_ALW
+1.8V_3.3V_ALW_VTR3
@
RE505 100K_0402_5%
RE526 10K_0402_5%@
RE532 4.7K_0402_5%
+1.8V_3.3V_ALW_VTR3
12
12
12
@
8/28 s chematic review
10P_0402_50V8J
12
5
12
1
2
Close to pin H1
CE21
1
0.1U_0201_10V6K
Close to pin N5
2
+3.3V_ALW2
@
RE549
100K_0402_5%
ENABLE_DS#
RE550
100K_0402_5%
RE290
0_0402_5%
CE29
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m
CE16
0.1U_0201_10V6K
CE15
VCCST_PWRGD<11,14,36>
SLP_WLAN#_GATE<47>
12
12
12
PJP22
1 2
@
RE32 0_0402_5%
1
2
12
RE314100_0402_1%
+VSS_PLL
PCH_DPWROK<11>
SIO_SLP_SUS#<11>
1 2
@
RE308 0_0402_5%
1 2
@
RE552 0_0402_5%
T141
T142
LOM_CABLE_DETECT#
USH_DET#
BCM5882_ALERT#
12
RE57 1K_0402_5%@
@
T144
SYS_PWROK<11,14>
Deep Sleep support
non Deep Sleep
Deep Sle ep10
For EMI request
ESPI_CLK_5105
33_0402_5%
@EMI@
12
RE350
33P_0402_50V8J
@EMI@
12
CE57
0.1U_0201_10V6K
CE13
0.1U_0201_10V6K
1U_0402_6.3V6K
CE23
CE14
1
12
2
0.1U_0201_10V6K
22U_0603_6.3V6M
@
1
1
CE18
CE17
2
2
@DS3@
1 2
RE536 0_0402_5%
1 2
RE349 43K_0402_1%DS3@
WLAN_WIGIG60GHZ_DIS#<33>
CLK_TP_SIO_I2C_DAT<45>
DAT_TP_SIO_I2C_CLK<45>
@
PAD~D
@
PAD~D
@
T143
12
PAD~D
100K_0402_5%
RE58
SYS_PWROK RESET_OUT
PAD~D
@
RE548 0_0402_5%
For MEC5105 Re v.A:Pop RE361,Depo p RE36 0,RE362
For MEC5105 Rev.B/C:Depop RE361,Pop RE360,RE362
For WDT is sue fix options&a sses sment:Pop RE361, De pop R E362
RESET_IN#
+3.3V_ALW_UE1
+1.8V_3.3V_ALW_VTR3
RUN_ON_EC<36>
SIO_EXT_WAKE#<9>
BT_RADIO_DIS#<33>
PBAT_PRES#<50,59>
PCH_ALW_ON<47>
AC_PRESENT<11>
SML1_SMBDATA<8>
SML1_SMBCLK<8>
WWAN_WAKE#<33>
SUSACK#<11>
SIO_PWRBTN#<11,14>
LID_CL_SIO#<36>
JTAG_TDI<36>
JTAG_TDO<36>
JTAG_CLK<36>
JTAG_TMS<36>
TACH_FAN1<36>
LCD_TST<29>
PWM_FAN1<36>
PCH_RSMRST#<45>
BIA_PWM_EC<29>
HW_ACAVIN_NB<50,59,60>
PANEL_BKEN_EC<29>
BEEP<34>
SIO_SLP_WLAN#<11,47>
BCM5882_ALERT#<38>
MSDATA<36>
NB_MUTE#<34>
EN_INVPWR<29>
IMVP_VR_ON_EC<36>
SIO_SLP_S3#<11,36>
SIO_SLP_S5#<11>
@
T264
AC_DISC#<50,60>
USH_DET#<38>
WWAN_RADIO_DIS#<33>
BC_DAT_ECE1117<45>
BC_CLK_ECE1117<45>
NGFF_CONFIG_3<33>
VBUS2_ECOK<50,60>
ESPI_RESET#<8,36>
ESPI_ALERT#<8>
PCH_PLTRST#_5105<36>
ESPI_CLK_5105<8,36>
ESPI_CS#<8,36>
ESPI_IO0<8,36>
ESPI_IO1<8,36>
ESPI_IO2<8,36>
ESPI_IO3<8,36>
1 2
DCIN2_EN<50>
4
+RTC_CELL_VBAT
0.1U_0201_10V6K
CE11
1
2
+3.3V_EC_PLL
PCH_DPWROK_EC
WLAN_WIGIG60GHZ_DIS#
LCD_TST
PS_ID<50>
AC_DIS<59>
MSCLK<36>
PAD~D
GPU_PWR_LEVEL
WWAN_RADIO_DIS#
@
RE361 49.9K_0402_1%
RE362 100K_0402_5%
4
RUN_ON_EC
BT_RADIO_DIS#
SIO_SLP_SUS#_R
PCH_ALW_ON
WWAN_WAKE#
VCCST_PWRGD_EC
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
GPIO051
GPIO054
PCH_RSMRST#
TBT_RESET_N_EC_R
BEEP
AC_DIS
MSCLK
MSDATA
EN_INVPWR
RESET_IN#
IMVP_VR_ON_EC
VBUS3_ECOK
RTCRST_ON
GPIO011
VBUS2_ECOK
ENABLE_DS#
GPIO100
DCIN2_EN
MEC_XTAL1
MEC_XTAL2_R
1 2
1 2
eSPI
LPC
eSPI
LPC
UE1
A2
VBAT
B7
VTR_ANALOG
K2
VREF_ADC
F1
VTR_PLL
H1
VTR_REG
G8
VTR1
M9
VTR2
N5
VTR3
F8
GPIO020
E8
GPIO045
M12
GPIO120
C2
GPIO166
F9
GPIO175
N4
GPIO230
M8
GPIO231
K8
GPIO233
E11
GPIO007/SMB03_DATA/PS2_CLK0B
D8
GPIO010/SMB03_CLK/PS2_DAT0B
M13
GPIO110/PS2_CLK2
K12
GPIO111/PS2_DAT2
L13
GPIO112/PS2_CLK1A
K11
GPIO113/PS2_DAT1A
K10
GPIO114/PS2_CLK0A/nEC_SCI
N11
GPIO115/PS2_DAT0A
E10
GPIO154/SMB02_DATA/PS2_CLK1B
C12
GPIO155/SMB02_CLK/PS2_DAT1B
E9
GPIO145/SMB09_DATA/JTAG_TDI
F6
GPIO146/SMB09_CLK/JTAG_TDO
C8
GPIO147/SMB08_DATA/JTAG_CLK
C5
GPIO150/SMB08_CLK/JTAG_TMS
G13
JTAG_RST#
E3
GPIO050/FAN_TACH0/GTACH0
D1
GPIO051/FAN_TACH1/GTACH1
M2
GPIO052/FAN_TACH2/LRESET#
L10
GPIO053/PWM0/GPWM0
L11
GPIO054/PWM1/GPWM1
M5
GPIO055/PWM2/SHD_CS#/(RSMRST#)
J8
GPIO056/PWM3/SHD_CLK
N1
GPIO001/PWM4
L8
GPIO002/PWM5
N6
GPIO014/PWM6/GPTP-IN6
J9
GPIO015/PWM7
H11
GPIO035/PWM8/CTOUT1
D9
GPIO133/PWM9
H12
GPIO134/PWM10/UART1_RTS#
G10
GPIO135/UART1_CTS#
H10
GPIO170/TFDP_CLK/UART1_TX
G9
GPIO171/TFDP_DATA/UART1_RX
A4
GPIO022/GPTP-IN0
B2
GPIO023/GPTP-IN1
C1
GPIO024/nRESETI
N7
GPIO031/GPTP-OUT1
K9
GPIO032/GPTP-OUT0
N8
GPI0040/GPTP-OUT2
F13
GPIO121/PVT_IO0
E13
GPIO124/GPTP-OUT6/PVT_CS#
C13
GPIO125/GPTP-OUT5/PVT_CLK
E12
GPIO126/PVT_IO3
F11
GPIO122/BCM0_DAT/PVT_IO1
F12
GPIO123/BCM0_CLK/PVT_IO2
D12
GPIO046/BCM1_DAT
D13
GPIO047/BCM1_CLK
F4
GPIO041/SYS_SHDN#
B1
SYSPWR_PRES
K7
GPIO011/nSMI
N3
GPIO021/LPCPD#
K6
GPIO061/LPCPD#/ESPI_RESET#
H7
GPIO063/SER_IRQ/ESPI_ALERT#
K1
GPIO064/LRESET#
G7
GPIO065/PCI_CLK/ESPI_CLK
H6
GPIO066/LFRAME#/ESPI_CS#
K5
GPIO070/LAD0/ESPI_IO0
L4
GPIO071/LAD1/ESPI_IO1
G6
GPIO072/LAD2/ESPI_IO2
L5
GPIO073/LAD3/ESPI_IO3
L2
GPIO067/CLKRUN#
M1
GPIO100/nEC_SCI
G4
GPIO106/PWROK
L12
GPIO107/nSMI
A1
XTAL1
A3
XTAL2
1.8V_PRIM_PWRGD <55>
+3.3V_ALW
GPIO22 3
NA NAN A
SHD_ IO0
GPIO20 4
NA
RSMRS T#
GPIO22 4
SHD_ IO1
GPIO0 11
NA N A
SIO_EXT_S MI#
VSS1
A6
A13
RUN_ON<17,36,47,54>
3
GPIO22 7
GPIO01 6
*PR IM_P WRGD NA
SHD_ IO2
SHD_ IO3
* For Version B IC
GPIO10 0
SIO_EXT_S CI#
GPIO005/SMB01_DATA/GPTP-OUT4
GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#
GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#
GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#
GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#
VSS_ADCH4VR_CAPJ1VSS_PLL
+VR_CAP
12
CE31 1U_0402_6.3V6K
+3.3V_ALW
RE68
VSS_ANALOG
C4
100K_0402_5%
VSS2
VSS3
E6
1 2
RUN_ON#<47>
DMN65D8LDW-7_SOT363-6
61
2
3
GPIO05 6
GPIO05 5
PCH_R SMRS T#
SHD_ CLK
SHD_ CS #
GPIO02 1
GPIO06 7
SIO_ RC IN#
NA
LPCPD #
CLKR UN #
GPIO033/RC_ID0
GPIO034/RC_ID1/SPI0_CLK
GPIO036/RC_ID2/SPI0_MISO
GPIO003/SMB00_DATA/SPI0_CS#
GPIO004/SMB00_CLK/SPI0_MOSI
GPIO057/VCC_PWRGD
GPIO060/KBRST/48MHZ_OUT
GPIO104/UART0_TX
GPIO105/UART0_RX
GPIO127/A20M/UART0_CTS#
GPIO225/UART0_RTS#
GPIO025/TIN0/nEM_INT/UART_CLK
GPIO006/SMB01_CLK/GPTP-OUT7
RUN_ON#
GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3
GPIO017/GPTP-IN5
GPIO151/ICT4
GPIO152/GPTP-OUT3
GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO226/LED3
GPIO012/SMB07_DATA/TOUT3
GPIO013/SMB07_CLK/TOUT2
GPIO130/SMB10_DATA/TOUT1
GPIO131/SMB10_CLK/TOUT0
GPIO132/SMB06_DATA
GPIO140/SMB06_CLK/ICT5
GPIO200/ADC00
GPIO201/ADC01
GPIO202/ADC02
GPIO203/ADC03
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07
GPIO210/ADC08
GPIO211/ADC09
GPIO212/ADC10
GPIO213/ADC11
GPIO214/ADC12
GPIO215/ADC13
GPIO216/ADC14
GPIO217/ADC15
GPIO222/SER_IRQ
GPIO223/SHD_IO0
GPIO224/GPTP-IN4/SHD_IO1
GPIO227/SHD_IO2
GPIO016/GPTP-IN7/SHD_IO3/ICT3
GPIO221/GPTP-IN3/32KHZ_OUT
GPIO042/PECI_DAT/SB-TSI_DAT
GPIO160/PWM11/PROCHOT#
G1
RUNPWROK
BGPO0
GPIO164/VCI_OVRD_IN
VCI_OUT
GPIO163/VCI_IN0#
GPIO162/VCI_IN1#
GPIO161/VCI_IN2#
GPIO000/VCI_IN3#
GPIO165/32KHZ_IN/CTOUT0
GPIO044/VREF_VTT
GPIO043/SB-TSI_CLK
DN1_DP1A
DP1_DN1A
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
VSET
GPIO103/THERMTRIP2#
THERMTRIP1#
MEC5105_WFBGA169_11X11
+VSS_PLL
+3.3V_RUN
10K_0402_5%
RE67
1 2
DMN65D8LDW-7_SOT363-6
34
QE2B
5
QE2A
2
TYPEC_ID
F2
SYSTEM_ID
J10
BOARD_ID
J13
UPD2_SMBDAT
E7
UPD2_SMBCLK
D7
G3
GPS_DISABLE#
H5
G11
G12
B13
UPD1_SMBINT#
F10
PCIE_WAKE#_R
N13
N12
M11
H9
VGA_IDENTIFY
L9
M10
N9
C11
D10
D11
E1
E5
B3
VCCDSW_EN
M7
DGPU_PWROK
M4
PBAT_CHARGER_SMBDAT
M3
PBAT_CHARGER_SMBCLK
N2
N10
LED_MASK#
A12
GPU_SMDAT
B6
GPU_SMCLK
F7
UPD1_SMBDAT
B4
UPD1_SMBCLK
C3
I_BATT_R
J4
I_SYS_R
J5
J6
GPIO202
G2
H2
J2
J3
K3
D3
D2
E2
G5
F5
K4
L1
L3
H8
J7
L6
L7
M6
D6
C7
A5
D5
B5
D4
E4
C6
F3
J11
K13
J12
A8
A7
A10
A9
B9
B8
A11
B10
C10
VIN
C9
B11
VCP
H3
B12
H13
@
USH_PWR_STATE#
USB_POWERSHARE_VBUS_EN
USB_POWERSHARE_EN#
USB_PWR_EN1#
USB_PWR_EN2#
UPD2_SMBINT#
DCIN1_EN
CV2_ON_R
3.3V_TS_EN
MASK_SATA_LED#
1.8V_PRIM_PWRGD
VBUS1_ECOK
VCI_IN1#
VCI_IN2#
POA_WAKE#
32KHZ_OUT
+PECI_VREF
PECI_EC_R
M3042_PCIE#_SATA
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE4_P
+VR_CAP
VSET_5105
THERMTRIP2#
THERMTRIP1#
PROCHOT#_R1
12
L2N7002WT1G_SC-70-3
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TYPEC_ID <36>
SYSTEM_ID <36>
BOARD_ID <36>
RUNPWROK <14>
GPS_DISABLE# <33>
HOST_DEBUG_TX <33,36>
ME_FWP <12>
ME_SUS_PWR_ACK <11>
UPD1_SMBINT# <26>
PCIE_WAKE#_R <36>
SIO_SLP_S4# <11,17,52,55>
SIO_SLP_A# <11>
SIO_SLP_LAN# <11,47>
NGFF_CONFIG_1 <33>
NGFF_CONFIG_0 <33>
BREATH_LED# <46>
BAT1_LED# <46>
BAT2_LED# <46>
LCD_VCC_TEST_EN <29>
USH_EXPANDER_SMBDAT <38>
USH_EXPANDER_SMBCLK <38>
VCCDSW_EN <11>
PBAT_CHARGER_SMBDAT <50,59>
PBAT_CHARGER_SMBCLK <50,59>
NGFF_CONFIG_2 <33>
LED_MASK# <30,46>
UPD1_SMBDAT <26>
UPD1_SMBCLK <26>
1 2
RE64 300_0402_5%
1 2
RE312 300_0402_5%
1 2
RE318 0_0402_5%
USH_PWR_STATE# <38>
USB_POWERSHARE_VBUS_EN <43>
USB_POWERSHARE_EN# <43>
USB_PWR_EN1# <44>
AUX_EN_WOWL <47>
LOM_CABLE_DETECT# <30>
BC_INT#_ECE1117 <45>
DCIN1_EN <60>
PCH_PCIE_WAKE# <11,36>
LAN_WAKE# <11,30>
1 2
RE539 100_0402_5%
3.3V_TS_EN <29>
MASK_SATA_LED# <46>
VBUS1_ECOK <60>
EC_FPM_EN <38>
ACAV_IN <59>
ALWON <51>
POWER_SW_IN# <36>
POA_WAKE# <38>
3.3V_WWAN_EN <47>
1 2
CE54 10P_0402_50V8J@
1 2
RE60 43_0402_5%
1 2
CE24 2200P_0402_50V7K
1 2
CE26 2200P_0402_50V7K
1 2
CE27 2200P_0402_50V7K
VSET_5105 <36>
I_ADP <59>
THERMTRIP2# <36>
1 2
RE288 100_0402_5%
10K_0402_5%
1U_0402_6.3V6K
12
RE546
CE63
13
D
RTCRST_ON_R
2
QE17
G
S
12
I_BATT <59>
I_SYS <56,59>
TOUCHPAD_INTR# <12,45>
M3042_PCIE#_SATA <10>
LP2301ALT1G_SOT23-3
DE2
2 1
RB751S40T1G_SOD523-2
RE543
1 2
1M_0402_5%
22P_0402_50V8J
CE65
2
PAD~D
PAD~D
CV2_ON <38>
PECI_EC <12>
PROCHOT# <12,56,59>
123
D
VCCDSW_EN
@
T147
12
@
T262
RE59 close to UE2 at l east 250mils
+PECI_VREF
0.1U_0201_10V6K
CE25
12
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE4_P
+RTC_CELL+RTC_CELL_PCH
QE15
S
G
RE565 0_0402_5%
0.1U_0402_25V6
100K_0402_5%
@
CE64
RE541
12
1 2
0.1U_0402_25V6
@
CE66
12
RE590_0402_5%
1 2
+1.0V_VCCST
@
REM_DIODE1_N <36>
REM_DIODE1_P <36>
REM_DIODE2_N <36>
REM_DIODE2_P <36>
REM_DIODE4_N <36>
REM_DIODE4_P <36>
RTCRST_ON
1
For BR UMA
UPD1_SMBDAT
UPD1_SMBCLK
UPD1_SMBINT#
UPD2_SMBINT#
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK
GPU_SMDAT
GPU_SMCLK
SIO_SLP_SUS#_R
UPD2_SMBCLK
UPD2_SMBDAT
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_0
NGFF_CONFIG_3
USB_PWR_EN2#
USB_POWERSHARE_EN#
USB_PWR_EN1#
USB_POWERSHARE_VBUS_EN
AC_DIS
GPS_DISABLE#
WLAN_WIGIG60GHZ_DIS#
WWAN_WAKE#
LED_MASK#
THERMTRIP1#
PCIE_WAKE#_R
GPU_PWR_LEVEL
BC_DAT_ECE1117
WWAN_RADIO_DIS#
BT_RADIO_DIS#
VCI_IN1#
VCI_IN2#
POA_WAKE#
VGA_IDENTIFY
VGA_IDENTIFY
RE302 2.2K_0402_5%
RE303 2.2K_0402_5%
RE91 100K_0402_5%
RE92 100K_0402_5%
RE37 2.2K_0402_5%
RE43 2.2K_0402_5%
RE524 2.2K_0402_5%
RE525 2.2K_0402_5%
NDS3@
RE561 100K_0402_5%
2.2K_0804_8P4R_5%
100K_0804_8P4R_5%
100K_0804_8P4R_5%
RE83 100K_0402_5%@
RE12 100K_0402_5%
RE8 100K_0402_5%
RE38 10K_0402_5%
RE21 10K_0402_5%
RE301 10K_0402_5%
RE35 10K_0402_5%
RE5 10K_0402_5%
RE365 100K_0402_5%
RE10 100K_0402_5%
RE11 100K_0402_5%
1 2
RE507 100K_0402_5%
1 2
RE508 100K_0402_5%
1 2
RE324 100K_0402_5%
I_BATT_R
CE3 2200P_0402_50V7K
I_SYS_R
CE4 2200P_0402_50V7K
PCH_RSMRST#
RE342 10K_0402_5%
SYS_PWROK
RE56 10K_0402_5%
I_SYS_R
@
RE313
RE20 100K_0402_5%
EN_INVPWR
RE55 100K_0402_5%
3.3V_TS_EN
RE547 100K_0402_5%@
RE84 100K_0402_5%
RE85 100K_0402_5%@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
3
4 5
1
2
3
4 5
RPE11
1
2
3
4 5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Discrete
+RTC_CELL_PCH +RTC_CELL
1 2
RE551 0_0402_5%
@
RE94
@
1 2
75_0402_5%
13
RTCRST_ON
100K_0201_5%
D
2
@
G
L2N7002WT1G_SC-70-3
12
S
RE93
@
RPE12
RPE9
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VGA_IDENTIFY
QE12
8
7
6
8
7
6
8
7
6
10K_0402_5%
0
1UMA
PCH_RTCRST# <11>
+3.3V_ALW
+RTC_CELL
+3.3V_RUN
+3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
EC MEC5105
EC MEC5105
EC MEC5105
LA-F391P
LA-F391P
LA-F391P
1
35 70Tuesday, September 19, 2017
35 70Tuesday, September 19, 2017
35 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW
UE6
1
5
NC
VCC
PCH_PLTRST#_EC<11>
2
A
3
GND
74AUP1G07GW_TSSOP5
4
Y
1 2
RE340
10K_0402_5%
PCH_PLTRST#_5105 <35>
6/8 Change to SA00007WE00 DII
D D
11
GND
12
GND
JXT_FP241AH-010GAAM
CONN@
JXT_FP241AH-010GAAM LINK DONE
LPC 80Port Debug LPC ESPI
C C
+3.3V_RUN
JESPI
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
1
2
3
4
5
6
7
8
9
10
RE375 0_0402_5%LPC@
RE560 0_0402_5%@
+3.3V_RU N
+3.3V_RU N
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_FRAME #
PCH_PLTRST #
GND
LPC_CLOC K
1 2
1 2
+3.3V_RU N
+3.3V_RU N
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
ESPI_CS#
NA
GND
ESPI_CLK
PCH_PLTRST#_EC
ESPI_RESET#
ESPI_IO0 <8,35>
ESPI_IO1 <8,35>
ESPI_IO2 <8,35>
ESPI_IO3 <8,35>
ESPI_CS# <8,35>
ESPI_RESET# <8,35>
ESPI_CLK_5105 <8,35>
4
PAGE
8
ESPI LPC
RC25_10K
RC8_15ohm
RC13/RC27_8.2K
18 RC212_0ohm RC211_0ohm
0603 0603
RE337,RE338
31
RE339,RE340,
RE341
0_ohm
RE2 / RE3
32
0_ohm
3
2
1
For BR UMA
+RTC_CELL
100K_0402_5%
12
RE31
+3.3V_ALW
2.2U_0402_6.3V6M
12
100K_0402_5%
RE25
12
.047U_0402_16V7K
12
CE8
1 2
RE33 1K_0402_5%
CE12
RE26
10_0402_5%
POWER_SW_IN#<35>
LID_CL_SIO#
CE10@
1 2
1U_0402_6.3V6K
POWER_SW#_MB <11,46>
12
LID_CL# <46>LID_CL_SIO#<35>
RF Request
+3.3V_ALW
1
CE61
2
68P_0402_50V8J
RF@
TYPEC_ID<35>
CE62RE343
4700 p240K
*
4700 p130K
62K
33K
4700 p
8.2K
4700 p
4700 p
4.3K
2K
4700 p
4700 p
1K
PD_ACE_DET# rise t i me i s measured fr o m 5 %~68 %.
IMVP_VR_ON_EC<35>
SIO_SLP_S3#<11,35,36>
RUN_ON_EC<35>
+3.3V_ALW
12
RE343
240K_0402_5%
12
CE62
4700P_0402_25V7K
REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)
+3.3V_ALW
5
1
P
B
2
G
A
UE3
3
1 2
+3.3V_ALW
1
B
2
A
UE5
BOARD_ID
RE79
CE40
240K 470 0p
130K
4700 p
4700 p
62K470 0p
33K 470 0p
8.2K
4700 p
4700 p
4.3K
2K
4700 p
4700 p1K
VSET_5105
0.1U_0402_25V6
1.58K_0402_1%
12
12
CE38
12
RE2750_0402_5%
O
5
P
G
3
RE77
PCIE_WAKE#_R<35>
Stuff RE275 and n o stuff RE2 74 keep E5 design
Stuff RE274 and n o stuff RE2 75 to save t wo GP IOs on EC(PCH_PCIE _WAKE# should be o utput wi th OD)
IMVP_VR_ON_EC
SIO_SLP_S3#
TC7SH08FU_SSOP5~D
RUN_ON_EC
TC7SH08FU_SSOP5~D
BOARD_ID<35>
*
BOARD_ID rise t i me is meas ur ed fr o m 5 %~68 %.
@
12
@
RE3040_0402_5%
@
CE53
1 2
0.1U_0402_25V6K
4
@
RE2800_0402_5%
12
@
RE2920_0402_5%
@
CE52
1 2
0.1U_0402_25V6K
4
O
+3.3V_ALW
1 2
12
REV
X00
X01
X02
X03
reserved
A00
RE79
4.3K_0402_5%
CE40
4700P_0402_25V7K
VSET_5105 <35>
1 2
PCIE_WAKE# <33,40>
PCH_PCIE_WAKE# <11,35>
RE2740_0402_5% @
+3.3V_ALW
UE4
1
5
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
VCC
Y
4
VCCST_PWRGD <11,14,35>
IMVP_VR_ON
IMVP_VR_ON <56>
6/8 Change to SA00007WE00 DII
RUN_ON <17,35,47,54>
+3.3V_ALW
12
RE300
130K_0402_5%
SYSTEM_ID
SYSTEM_ID<35>
SYSTEM_ID rise t i me i s measured fr o m 5 %~68%.
240K 4 700p
*
130K 4 700p
62K
4.3K 4700 p
2K
1K
12
CE47
4700P_0402_25V7K
CE47RE30 0
PANEL SIZE
11"
12"
4700 p
13"
14"
4700 p3 3K
15"
4700 p8.2 K
17"
4700 p 15P
4700 p
+3.3V_ALW
+3.3V_ALW
1 2
RE306
@
0_0402_5%
RE69
1 2
8.2K_0402_5%
H_THERMTRIP#<12,20,21>
10K_0402_5%
100K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
12
RE72
RE75@
RE73
RE74
RE86
10K_0402_5%
1 2
0.1U_0402_25V6
THERMTRIP2# <35>
CE36
MMST3904-7-F_SOT323-3
12
C
QE4
2
B
E
3 1
10K_8P4R_5%
12
B B
JDEG1
+EC_DEBUG_VCC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
11
9
GND
9
12
10
GND
10
JXT_FP241AH-010GAAM
CONN@
JXT_FP241AH-010GAAM LINK DONE
A A
+1.0V_VCCST
RE71
10_0402_1%
+1.0VS_VCCIO
678
123
4 5
DEBUG_TX
1 2
@
RE30 0_0402_5%
QE11
@
1 3
D
L2N7002WT1G_SC-70-3
1 2
@
RE90 0_0402_5%
RPE7
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEBUG_TX
SBIOS_TX<9>
HOST_DEBUG_TX <33,35>
MSDATA <35>
MSCLK <35>
SIO_SLP_S3# <11,35,36>
2
G
S
JTAG_TDI <35>
JTAG_TMS <35>
JTAG_CLK <35>
JTAG_TDO <35>
1 2
RE70 2.2K_0402_5%
Rest=1.58K , Tp=96 degree???
+3.3V_RUN
1 2
RE48 10K_0402_5%
1 2
RE51 10K_0402_5%
Thermal diode mapping
5085 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a
DP3/DN3
DP4/DN4
DP4/DN4 for Sk in on
QE6, place QE6 close to
Vcore VR choke.
100P_0402_50V8J
C
@
2
CE39
B
E
QE6
3 1
1 2
MMST3904-7-F_SOT323-3
PWM_FAN1
TACH_FAN1
Locat i on
CPU (QE3)
WiGig (QE5)
DDR (QE7)
NA
CPU VR (QE6)
REM_DIODE4_P <35>
REM_DIODE4_N <35>
Link 50271-0040N-001 DONE
JFAN1
1
PWM_FAN1
1
2
TACH_FAN1
2
3
3
4
4
10U_0603_6.3V6M
5
GND1
6
12
GND2
ACES_50271-0040N-001
CONN@
Place und er CPU
Place CE35 clo se to the QE3 as possi ble
100P_0402_50V8J
C
2
CE35@
B
1 2
E
QE3
3 1
MMST3904-7-F_SOT323-3
DP2/DN2 for Wi Gig on QE5, place QE5 close
to WiGig and CE37 close to QE5
DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7
100P_0402_50V8J
CE46@
100P_0402_50V8J
12
31
E
12
C
C
CE37@
B
2
QE7
3 1
MMST3904-7-F_SOT323-3
PWM_FAN1 <35>
TACH_FAN1 <35>
+5V_RUN
@
DE1
CE32
BZV55-B5V6_SOD80C2
2 1
REM_DIODE1_P <35>
REM_DIODE1_N <35>
2
B
E
QE5
MMST3904-7-F_SOT323-3
REM_DIODE2_P <35>
REM_DIODE2_N <35>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHE ET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFID ENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE E XPRESS WR ITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
5
4
3
PARTY WITHOUT DELL'S EXPRES S WRITTEN CONSENT.
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
MEC5105 Support
MEC5105 Support
MEC5105 Support
Document Number Re v
Document Number Re v
Document Number Re v
LA-F391P
LA-F391P
LA-F391P
36 70Tuesday, September 19, 2017
36 70Tuesday, September 19, 2017
1
36 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For NUVOTON TPM
@
1 2
VSB
VDD
VHIO
VHIO
GND
GND
GND
GND
PGND
Reserved
@
+3.3V_ALW
1
8
14
22
2
NC
7
NC
10
NC
11
NC
25
NC
26
NC
31
NC
9
16
23
32
33
12
RZ367 0_0402_5%
1 2
RZ89 0_0402_5%
PJP391
PAD-OPEN1x1m
1 2
+3.3V_ALW_UZ12
0.1U_0201_10V6K
1
1
CZ51
2
2
+UZ12_TPM
+UZ12_VHIO
0.1U_0201_10V6K
1
CZ54
2
CZ53,CZ55 as close as UZ12.14
CZ54 as close as UZ12.22
+UZ12_TPM
10U_0402_6.3V6M
CZ75
1
2
10U_0603_10V6M
place CZ51,CZ 52 as close as UZ 12.1
CZ52
1 2
RZ366 0_0402_5%650@
1 2
@750@
RZ365 0_0402_5%
10U_0603_10V6M
0.1U_0201_10V6K
1
1
2
CZ55
CZ53
2
place CZ50, CZ75 as close as UZ12.8
0.1U_0201_10V6K
1
CZ50
2
+3.3V_M_TPM
+3.3V_RUN
+3.3V_M_TPM
+3.3V_RUN
D D
+3.3V_ALW
@
1 2
+3.3V_ALW_PCH
SIO_SLP_S0#<11,17,54>
C C
PCH_SPI_D1_R1<8>
PCH_SPI_D0_R1<8>
PCH_SPI_CLK_R1<8>
PCH_SPI_CS#2<8>
RZ369 0_0402_5%
1 2
@
RZ368 0_0402_5%
1 2
RZ69 10K_0402_5%
+3.3V_RUN
12
RZ362
@
10K_0402_5%
1 2
@750@
RZ112 0_0402_5%
1 2
RZ363 0_0402_5%650@
1 2
RZ58 33_0402_5%
1 2
RZ59 33_0402_5%
1 2
RZ60 33_0402_5%EMI@
@
1 2
RZ61 0_0402_5%
PLTRST_TPM#<11>
T283
TPM_PIRQ#
TPM_PIRQ#<9>
@
PAD~D
PCH_SPI_D1_2_R
PCH_SPI_D0_2_R
PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R
10K_0402_5%
12
@
RZ62
+3.3V_M_TPM
TPM_GPIO0
TPM_LPM#
TPM_GPIO4
UZ12
29
GPIO0/SDA/XOR_OUT
30
GPIO1/SCL
3
GPIO2/GPX
6
GPIO3/BADD
24
LAD0/MISO
21
LAD1/MOSI
18
LAD2/SPI_IRQ#
15
LAD3
19
LCKL/SCLK
20
LFRAME#/SCS#
17
LRESET#/SPI_RST#/SRESET#
27
SERIRQ
13
CLKRUN#/GPIO4/SINT#
28
LPCPD#
4
PP
5
TEST
NPCT750JAAYX_QFN32_5X5
9/13: cha nge to MP sample : SA0000AQ220
Pop Comment
NPCT65x RZ89, RZ366, RZ62, RZ363
B B
A A
NPCT75x RZ89, RZ365, RZ112
NPCT75x
RZ367, RZ36 6 RZ89, R Z365, RZ62
Depop
RZ365, RZ367, RZ112
RZ367, RZ36 6, RZ62, RZ363
VDD - V_RUN Power
VHIO - V_SPI Power
Option1 (recommended)
VDD and VHIO - V_RUN power
Option2 (for Z1 sample [early samp le])
VDD and VHIO - V_SPI power
PCH_SPI_CLK_2_R
33_0402_5%
@EMI@
RZ63
0.1U_0402_25V6
1 2
@EMI@
12
CZ56
RF Request RF Request
+3.3V_ALW +3.3V_M_TPM
12P_0402_50V 8J
68P_0402_50V 8J
RF@
RF@
1
1
CZ57
CZ58
2
2
12P_0402_50V 8J
RF@
1
CZ59
2
68P_0402_50V 8J
RF@
1
CZ60
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-F391P
LA-F391P
LA-F391P
37 70Tuesday, September 19, 2017
37 70Tuesday, September 19, 2017
37 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For ATMEL TPM
D D
+3.3V_ALW
C C
+PWR_SRC
POA_WAKE#<35>
PCH_PLTRST#_AND<11,31,33,40>
CONTACTLESS_DET#<12>
B B
@
RZ85 0_0402_5%
RZ364 100_0402_5%
RZ114 0_0402_5%@
RB751S40T1G_SOD523-2
USH_DET#<35>
PCH_PLTRST#_AND
.047U_0402_16V7K
12
CZ61ESD@
For ESD solution
1 2
RZ8 2.2K_0402_5%
1 2
RZ9 2.2K_0402_5%
1 2
RZ10 100K_0402_5%
1 2
1 2
USH_EXPANDER_SMBCLK<35>
USH_EXPANDER_SMBDAT<35>
1 2
DZ8
12
@
RZ87 0_0402_5%
RB751S40T1G_SOD523-2
BCM5882_ALERT#<35>
USH_PWR_STATE#<35>
1 2
DZ7
@
+5V_ALW
USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT
USH_PWR_STATE#
+PWR_SRC_R
CV2_ON<35>
EC_FPM_EN<35>
USB20_N10<10>
USB20_P10<10>
+3.3V_ALW
+5V_ALW
+3.3V_RUN
+5V_RUN
USH_RST#_R
CONTACTLESS_DET#_R
USH_DET#_R
12
0.1U_0201_10V6K
1
@
CZ64
2
USH CONN
CVILU_CF5026FD0RK-05-NH
Close to JUSH1
0.1U_0201_10V6K
1
@
CZ66
2
CONN@
28
GND2
27
GND1
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JUSH1
Link CVILU_CF5026FD0RK-05-NH
+3.3V_ALW+3.3V_RUN+5V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
2
@
@
CZ68
CZ67
2
68P_0402_50V 8J
1
2
RF Request
RF@
CZ73
USH_EXPANDER_SMBCLK
A A
USH_EXPANDER_SMBDAT
1 2
CZ62 68P_0402_50V8J@RF@
1 2
CZ63 68P_0402_50V8J@RF@
RF Request
68P_0402_50V 8J
RF@
1
CZ69
2
68P_0402_50V 8J
RF@
1
CZ71
2
+3.3V_ALW+3.3V_RUN+5V_RUN+5V_ALW
68P_0402_50V 8J
RF@
1
CZ72
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-F391P
LA-F391P
LA-F391P
38 70Tuesday, September 19, 2017
38 70Tuesday, September 19, 2017
38 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
10K_0402 _5%
@
RN28
RD1_A_DE0
RD1_A_DE1
RD1_B_DE0
RD1_B_DE1
10K_0402 _5%
@
RN41
@
12
RN57
12
RN61
10K_0402 _5%
@
RN58
RD2_A_DE0
RD2_A_DE1
RD2_B_DE0
RD2_B_DE1
10K_0402 _5%
@
RN62
5
+3.3V_RUN
10K_0402 _5%
10K_0402 _5%
10K_0402 _5%
@
12
12
12
RN49
RN50
RN51
10K_0402 _5%
10K_0402 _5%
10K_0402 _5%
@
@
@
12
12
12
RN53
RN52
RN54
+3.3V_RUN
+3.3V_RUN
10K_0402 _5%
10K_0402 _5%
10K_0402 _5%
@
@
@
12
12
D D
10K_0402 _5%
12
Programmable output de-emphasis level
set t i ng for ch annel A .
A_DE0: intern ally pull ed up at ~150K;
A_DE1 int ernally pul led down at ~150K
[A_DE1,A_DE0] ==
LL: -2dB
HL: -7. 5dB
LH: -3.5dB (default)
HH: -6 dB
Programmable output de-emphasis level
C C
set t i ng for ch annel B.
B_DE0: intern ally pull ed up at ~150K;
B_DE1 intern ally pul led down at ~150K
[B_DE1,B_DE0] ==
LL: -2dB
HL: -7. 5dB
LH: -3.5dB (default)
HH: -6 dB
Equalizer control and program for chan nel A.
A_EQ0, A_EQ1 and A_EQ2: internall y pulled down at ~150K
[A_EQ2,A_EQ1,A_EQ0] ==
LLL: For channel loss up to 17dB (default)
LHL: F or channel loss up to 1 4dB
HLL: F or channel loss up to 1 9dB
HHL: For channel loss up to 21dB
LLH: F or channel loss up to 1 8dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB
Equalizer control and program for channel B.
B_EQ0, B_EQ1 a nd B_EQ2: in ternally pu lled down at ~150K
[B_EQ2,B_EQ1,B_EQ0] ==
LLL: For channel loss up to 17dB (default)
B B
LHL: F or channel loss up to 1 4dB
HLL: F or channel loss up to 1 9dB
HHL: For channel loss up to 21dB
LLH: F or channel loss up to 1 8dB
LHH: For channel loss up to 10dB
HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB
+3.3V_RUN
A A
12
12
RN27
RN25
RN26
10K_0402 _5%
10K_0402 _5%
@
12
12
12
RN40
RN39
RN38
10K_0402 _5%
10K_0402 _5%
10K_0402 _5%
@
@
12
12
12
RN55
RN56
10K_0402 _5%
10K_0402 _5%
10K_0402 _5%
@
12
12
12
RN59
RN60
RD1_B_EQ0
RD1_B_EQ1
RD1_B_EQ2
IFDET_SATA_PCIE#
M2280_PCIE_SATA#
10K_0402 _5%
12
12
RN69
10K_0402 _5%
@
12
12
RN72
+3.3V_RUN
10K_0402 _5%
10K_0402 _5%
@
12
RN71
RN70
10K_0402 _5%
10K_0402 _5%
@
@
12
RN74
RN73
10K_0402 _5%
10K_0402 _5%
12
12
12
12
RN42
RN43
10K_0402 _5%
10K_0402 _5%
@
@
12
12
RN176
RN179
M2280_PCIE_SATA#
1 2
@
RN186 0_0402_5%
1 2
RN184 0_0402_5%
@
RD2_B_EQ0
RD2_B_EQ1
RD2_B_EQ2
10K_0402 _5%
RN44
10K_0402 _5%
@
RN174
RD1_A_EQ0
RD1_A_EQ1
RD1_A_EQ2
+3.3V_RUN
2
100K_040 2_5%
12
@
12
6
1
+3.3V_RUN
2
RN185
4
100K_040 2_5%
RN171
IFDET_SATA_PCIE#
QN4A
DMN65D8LDW- 7_SOT363-6
10K_0402 _5%
12
RN64
RD2_A_EQ1_R
6
1
DMN65D8LDW- 7_SOT363-6
4
IFDET_SATA_PCIE#
M2280_PCIE_SATA#
@
RN224 0_0402_5%
IFDET_SATA_PCIE#
QN5A
M2280_PCIE_SATA#
@
RN192 0_0402_5%
RN182 0_0402_5%
@
1 2
@
@
1 2
1 2
RD2_A_EQ1
1 2
RN189 0_0402_5%
1 2
RN187 0_0402_5%
12
100K_040 2_5%
@
RN183
+3.3V_RUN
5
+3.3V_RUN
5
100K_040 2_5%
12
@
RN188
10K_0402 _5%
12
RN65
34
RD2_A_EQ2_R
QN4B
DMN65D8LDW- 7_SOT363-6
10K_0402 _5%
12
RN63
RD2_A_EQ0_R
34
QN5B
DMN65D8LDW- 7_SOT363-6
3
1 2
@
RN223 0_0402_5%
1 2
@
RN225 0_0402_5%
3
PCIE_PTX_DRX_P11<10>
PCIE_PTX_DRX_N11<10>
PCIE_PRX_DTX_P11<10>
PCIE_PRX_DTX_N11<10>
RD2_A_EQ2
RD2_A_EQ0
2
+3.3V_RUN
4.7K_040 2_5%
12
RN228
HDD_UN4_UN5_EN
13
HDD_DET#<10,41>
HDD_DET#
+3.3V_RUN
0.1U_020 1_10V6K
1
2
D
2
QN7
G
L2N7002WT1G_SC-70-3
S
0.01UF_04 02_25V7K
CN20
1
CN21
2
PCIE/SATA Repeater
12
RD1_A_EQ0
RD1_A_EQ1
RD1_A_EQ2
RD1_B_EQ0
RD1_B_EQ1
RD1_B_EQ2
24
1
2
5
4
23
22
19
11
21
16
7
25
PCIE_PTX_C_RD_DRX_P11
1 2
CN220.22U_0402_10V6K
PCIE_PTX_C_RD_DRX_N11
1 2
CN230.22U_0402_10V6K
1 2
1 2
if signal is PCIE GEN3/S ATA GEN3 maybe change C value
or no need fo r DG0.9 SATA EXPRESS HDD
PCIE_PRX_C_RD_DTX_P11
CN260.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_N11
CN270.22U_0402_10V6K
M2280_PCIE_ SATA # DEVICE interface
+3.3V_RUN
0.1U_020 1_10V6K
0.01UF_04 02_25V7K
CN31
CN30
1
1
2
2
PCIE/SATA Repeater
PCIE_PTX_C_RD_DRX_P12
1 2
CN320.22U_0402_10V6K
PCIE_PTX_DRX_P12<10>
PCIE_PTX_DRX_N12<10>
PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>
if signal is PCIE GEN3/S ATA GEN3 maybe change C value
or no need fo r DG0.9 SATA EXPRESS HDD
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
1 2
1 2
PCIE_PTX_C_RD_DRX_N12
CN330.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_P12
CN360.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_N12
CN370.22U_0402_10V6K
2
RD2_A_EQ0
RD2_A_EQ1
RD2_A_EQ2
RD2_B_EQ0
RD2_B_EQ1
RD2_B_EQ2
1
For Parade 2 Lane solution
PCIE/SATA Redriver for 2280
UN4
VDD_3.3
VDD_3.3
A_INP
A_INN
B_OUTP
B_OUTN
A_EQ0
A_EQ1
A_EQ2
B_EQ0
B_EQ1
B_EQ2
GND
EPAD
PS8558BTQFN24GTR2-A_TQFN24_4X4
A_OUTP
A_OUTN
B_INP
B_INN
A_DE0
A_DE1
B_DE0
B_DE1
PWD
REXT
MODE
18
17
14
15
RD1_A_DE0
6
RD1_A_DE1
8
RD1_B_DE0
13
RD1_B_DE1
9
3
RD1_REXT
10
M2280_PCIE_SATA#
20
0
1
UN5
12
VDD_3.3
24
VDD_3.3
1
A_INP
2
A_INN
5
B_OUTP
4
B_OUTN
23
A_EQ0
22
A_EQ1
19
A_EQ2
11
B_EQ0
21
B_EQ1
16
B_EQ2
7
GND
25
EPAD
PS8558BTQFN24GTR2-A_TQFN24_4X4
A_OUTP
A_OUTN
B_INP
B_INN
A_DE0
A_DE1
B_DE0
B_DE1
REXT
MODE
PWD
18
17
14
15
RD2_A_DE0
6
RD2_A_DE1
8
RD2_B_DE0
13
RD2_B_DE1
9
3
RD2_REXT
10
M2280_PCIE_SATA#
20
Brekenrid ge12
Brekenridge14U UMA
Brekenridge14U DSC
Brekenridge15U UMA
Brekenridge15U DSC
Steamboa t12
Steamboa t14
Kirkwood1 2&13
PWD Funti on
0
1
PCIE_PTX_RD_DRX_P11 <40>
PCIE_PTX_RD_DRX_N11 <40>
PCIE_PRX_RD_DTX_P11 <40>
PCIE_PRX_RD_DTX_N11 <40>
1 2
RN229 0_0402_5%@
1 2
RN30 4.99K_0402_1%
M2280_PCIE_SATA# <10,40>
SATA
PCIE
PCIE_PTX_RD_DRX_P12 <40>
PCIE_PTX_RD_DRX_N12 <40>
PCIE_PRX_RD_DTX_P12 <40>
PCIE_PRX_RD_DTX_N12 <40>
1 2
RN230 0_0402_5%@
1 2
RN31 4.99K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SATA/PCIE REPEATER for M.2 2280
SATA/PCIE REPEATER for M.2 2280
SATA/PCIE REPEATER for M.2 2280
Need
Need
Need
Need
Need
No need
Need
Check
Normal mode(default)
power down mode
HDD_UN4_UN5_ENHDD_UN4_UN5_EN_R
HDD_UN4_UN5_ENHDD_UN4_UN5_EN_R
LA-F391P
LA-F391P
LA-F391P
1
39 70Tuesday, September 19, 2017
39 70Tuesday, September 19, 2017
39 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For Brekenridge 12/14/15 UMA/Steamboat
RF Request
D D
+3.3V_HDD_M2
68P_0402_50V 8J
@RF@
1
CN60
2
+3.3V_HDD_M2
0.1U_0201_10V6K
@
CN61
1
2
0.1U_0201_10V6K
22U_0603_6.3V6M
CN62
1
2
22U_0603_6.3V6M
12
12
CN63
CN64
2280 SSD
NGFF slot C Key M
Place near HDD CONN
2.8A
JNGFF3
1
1
3
3
5
5
7
7
9
9
+3.3V_HDD_M2
M2280_DEVSLP
1 2
C C
Co- lay :
B B
Short PJP31;Depop RZ99
RZ99 0.01_1206_1%@
RN37@ 10K_0402_5%
PCIE_PRX_RD_DTX_N11<39>
PCIE_PRX_RD_DTX_P11<39>
PCIE_PTX_RD_DRX_N11<39>
PCIE_PTX_RD_DRX_P11<39>
PCIE_PRX_RD_DTX_P12<39>
PCIE_PRX_RD_DTX_N12<39>
PCIE_PTX_RD_DRX_N12<39>
PCIE_PTX_RD_DRX_P12<39>
1 2
PJP31
1 2
PAD-OPEN1x3m
+3.3V_HDD_M2+3.3V_RUN
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG 0.9 SATA EXPRESS HDD
@
@
@
@
M2280_PCIE_SATA#<10,39>
PCIE_PRX_C_DTX_N11
PCIE_PRX_C_DTX_P11
PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11
PCIE_PRX_C_DTX_P12
PCIE_PRX_C_DTX_N12
PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12
CLK_PCIE_N3<11>
CLK_PCIE_P3<11>
12
12
RN820_0402_5%
RN810_0402_5%
12
CN69 0.22U_0402_10V6K
12
CN70 0.22U_0402_10V6K
CN71 0.22U_0402_10V6K
CN72 0.22U_0402_10V6K
12
12
RN770_0402_5%
RN780_0402_5%
12
12
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
67
67
69
69
71
71
73
73
75
75
77
GND1
LCN_DAN05-67356-0103
CONN@
GND2
Link DAN05-67356-0103 DONE
+3.3V_HDD_M2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
68
68
70
70
72
72
74
74
76
NVME_LED#
1 2
RN100 0_0402_5%@
PCIE_WAKE#
SUSCLK_R
@
RN99 0_0402_5%
M2280_DEVSLP <10>
PCH_PLTRST#_AND <11,31,33,38>
CLKREQ_PCIE#3 <11>
PCIE_WAKE# <33,36>
1 2
SATALED# <10,33,46>
SUSCLK <11,33>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
M2 2280 Socket
M2 2280 Socket
M2 2280 Socket
LA-F391P
LA-F391P
LA-F391P
40 70Tuesday, September 19, 2017
40 70Tuesday, September 19, 2017
40 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
pin 3
Pericom
*
D D
TDet_B#
GND
T I
GND
P a r a d e
SATA_PTX_DRX_P0<10>
SATA_PTX_DRX_N0<10>
SATA_PRX_DTX_N0<10>
SATA_PRX_DTX_P0<10>
Pericom PI3EQX6741ST
*
TI SN75LVCP601 P D
C C
Mai n
*
2nd
5
pin 6pin 13pin 16pin 18
N
C
TDet_A#
GND
DEW
2
REX
T
B_EQ2
HDD_UN7_EN HDD_UN7_EN_R
CN12 0.01UF_0402_25V7K
1 2
1 2
CN13 0.01UF_0402_25V7K
1 2
CN14 0.01UF_0402_25V7K
1 2
CN15 0.01UF_0402_25V7K
0
Pericom
NC
1 1.5d B
0
TI
NC
1
N
C
TDeT_EN
DEW
1
DEW
A_EQ2
1 2
RN227 0_0402_5%@
SATA_PTX_C_RD_DRX_P0
SATA_PTX_C_RD_DRX_N0
SATA_PRX_C_RD_DTX_N0
SATA_PRX_C_RD_DTX_P0
HDD_A_ EQ
PIN1 7
(RN11 )
(RN11 )
(RN11 )
A_E Q
3dB
6dB
9dB
7dB
0dB
14d B 14dB
GND
SATA Repeater
UN7
DEW2
DEW1
HDD_A_EQ HDD_B_EQ
HDD_A_PRE
PD
PD
PD
6
NC
16
NC
3
TDet_B#
17
A_EQ
9
A_EM
7
EN
1
AI+
2
AI-
4
BO-
5
BO+
21
GND
PI3EQX6741STZDEX_TQFN20_4X4
HDD_B_ EQ
HDD_A_ EQ2
PIN1 9
PIN1 8
PD
PD
(RN21 )
(RN13 )
PD
NC
(RN21 )
PD
PD
(RN21 )
(RN13 )
B_E Q B_EM
3dB
NC
6dB
1
9dB
7dB
0
0dB
NC
1
4
+3.3V_HDD
HDD_DET#
+3.3V_RUN
4.7K_040 2_5%
@
2
G
HDD_B_ PRE
PD
(RN9)
PH
(RN8)
NC
(1/2 VDD)
12
RN226
13
D
S
HDD_UN7_EN
QN6
L2N7002WT1G_SC-70-3
0.1U_02 01_10V6K
0.01UF_04 02_25V7K
1
1
CN17
CN16
2
10
VDD
20
VDD
13
TDet_A#
19
B_EQ
8
B_EM
18
TDeT_EN
15
AO+
14
AO-
12
BI-
11
BI+
HDD_B_ EQ2 DEW 2 HDD_ A_PRE
PD
(RN19 )
(RN19 )
PDParade PS8527C
(RN19 )
2
HDD_B_EQ2
HDD_B_PRE
HDD_A_EQ2
SATA_PTX_RD_DRX_P0 HDD_B_EQ
SATA_PTX_RD_DRX_N0
SATA_PRX_RD_DTX_N0
SATA_PRX_RD_DTX_P0
DEW 1
PIN 6
PIN1 6PIN13 PIN 9 PIN8
NCNC
PD
(RN7)
NC
(IPU)
NC
(1/2 VDD)
(IPU)
PD
(RN15 )
NC
PH
(RN6)
NC
(1/2 VDD)
A_E M
0dB0
0dB
1.5d B
0dB
-4d B
-2d B
0dB
-4d B
-2d B
3
2
1
For Breckenridge 12/14/15 UMA
+3.3V_HDD
@
@
HDD_A_PRE
HDD_B_PRE
HDD_A_EQ
DEW2
DEW1
HDD_B_EQ2
HDD_A_EQ2
4.7K_040 2_5%
4.7K_040 2_5%
12
RN6
4.7K_040 2_5%
4.7K_040 2_5%
RN7
1 2
4.7K_040 2_5%
4.7K_040 2_5%
RN8
1 2
4.7K_040 2_5%
RN9
1 2
4.7K_040 2_5%
4.7K_040 2_5%
12
12
@
@
RN10
RN11
@
RN12
RN14
1 2
7.87K_04 02_1%
4.7K_040 2_5%
1 2
4.7K_040 2_5%
@
RN15
RN13
1 2
1 2
DDR_XDP_WAN_SMBDAT<8,14,20,21>
DDR_XDP_WAN_SMBCLK<8,14,20,21>
@
RN16
@
RN17
4.7K_040 2_5%
12
4.7K_040 2_5%
1 2
+3.3V_RUN
12
4.7K_040 2_5%
12
12
@
@
RN20
RN18
+3.3V_RUN
100K_04 02_5%
12
RN2
6
FFS_INT2
LNG2DM
INT 1
INT 2
2
1
5
RES
12
11
6
7
GND
8
GND
4.7K_040 2_5%
12
12
RN19
RN21
0.1U_02 01_10V6K
10U_060 3_10V6M
12
CN2
CN1
0.1U_02 01_10V6K
12
CN3
Free Fall Sensor
LGA1
10
VDD_IO
9
VDD
3
SDO/SA0
4
SDA/SDI/SDO
SCL/SPC1GND
2
CS
LNG2DMTR_LGA12_2X2
100K_04 02_5%
5
DMN65D8LDW- 7_SOT363-6
QN1A
INT1/IN2:Push-Pull,active hi gh
FFS_INT2
+5V_HDD
12
RN1@
34
DMN65D8LDW- 7_SOT363-6
FFS_INT2_Q
QN1B
HDD_FALL_INT <9>
FFS_INT2 <12>
EQ1E Q2 A_E MB_EQ B_EMA_E Q
(M = VDD/2)
M
0
3rd
Parade
0 0
0
M
B B
M 0
M 1
1 M
1 0
2.4d B
7.4d B
14.4dB
1
12.2dB
M
9.4d B
13.3dB
6.2d B
11.2dB
1 1
+3.3V_RUN
12
RN4
@
10K_0402_5%
12
10K_0402_5%
HDD_EN
RN5
HDD_EN<9>
5
A A
2.4d B
7.4d B
14.4dB
12.2dB
9.4d B
13.3dB
6.2d B
11.2dB
5dB
5dB
+5V_HDD source
+5V_ALW
UZ23
@
1
VIN
2
VIN
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
0
M
1
VOUT
VOUT
GND
GND
CT
0dB
-3.5dB
-1.5dB
7
+5V_HDD_UZ23
8
6
5
9
0dB
-3.5dB
-1.5dB
Co- lay :
Short PJP32;D epop RZ102
CZ129 0.1U_0201_10V6K@
CZ130 470P_0402_50V7K@
4
* r e d c o l o r i s c u r r e n t
s e t t i n g
@
RZ102
1 2
0.01_1206_1%
PJP32
@
1 2
PAD-OPEN1x1m
1 2
1 2
1.5A
+5V_HDD
PJP33
12
PAD-OPEN1x1m
+3.3V_HDD
RN3@ 10K_0402_5%
SATA_PTX_RD_DRX_P0
SATA_PTX_RD_DRX_N0
SATA_PRX_RD_DTX_N0
SATA_PRX_RD_DTX_P0
+5V_HDD+5V_RUN
+3.3V_RUN
+5V_HDD +3.3V_HDD
0.1U_02 01_10V6K
1000P_0 402_50V7K
CN9
CN8
12
12
CN4 0.01UF_0402_25V7K
CN5 0.01UF_0402_25V7K
CN6 0.01UF_0402_25V7K
CN7 0.01UF_0402_25V7K
PJP34
1 2
PAD-OPEN1x2m
0.1U_02 01_10V6K
0.1U_02 01_10V6K
@
12
12
CN10
Place near HDD CONN
1 2
CN11
12
12
12
12
+5V_HDD
HDD_DEVSLP
+3.3V_HDD
HDD_DEVSLP<10>
HDD_DET#<10,39>
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
FFS_INT2_Q
JSATA1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
G1
22
G2
23
G3
24
G4
ACES_59003-02006-002
CONN@
Link SP010023HA0 DONE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
SATA Repeater&HDD CONN
SATA Repeater&HDD CONN
SATA Repeater&HDD CONN
LA-F391P
LA-F391P
LA-F391P
1
41 70Tuesday, September 19, 2017
41 70Tuesday, September 19, 2017
41 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
D D
C C
4
3
2
1
NO SUPPORT
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB3.0 Repeater
USB3.0 Repeater
USB3.0 Repeater
LA-F391P
LA-F391P
LA-F391P
42 70Tuesday, September 19, 2017
42 70Tuesday, September 19, 2017
42 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For w/o Repeater
+5V_USB_CHG_PWR
AZC199-02SPR7G_SOT23-3
ESD@
223
DI5
USB20_N9_R
USB20_P9_R
USB3_PRX_DTX_N6
USB3_PRX_DTX_P6
USB3_PTX_C_DRX_N6
USB3_PTX_C_DRX_P6
DI4
D D
USB3_PRX_DTX_N6<10>
USB3_PRX_DTX_P6<10>
USB3_PTX_DRX_N6<10>
USB3_PTX_DRX_P6<10>
12
CI13 0.1U_0402_25V6
12
CI16 0.1U_0402_25V6
USB3_PRX_DTX_N6
USB3_PRX_DTX_P6
USB3_PTX_C_DRX_N6
USB3_PTX_C_DRX_P6
ESD@
1
1
2
2
4
4
5
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
9
10
8
9
7
7
6
6
USB3_PRX_DTX_N6
USB3_PRX_DTX_P6
USB3_PTX_C_DRX_N6
USB3_PTX_C_DRX_P6
150U_B2_6.3VM_R35M
@
1
CI32
+
2
0.1U_0201_10V6K
100U_1206_6.3V6M
CI17
1
1
CI14
2
2
3
1
1
JUSB1
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
ACON_TCRA2-9U1U93
CONN@
GND
GND
GND
GND
10
11
12
13
Link TCRA2-9U1U93 DONE
RF Request
+5V_USB_CHG_PWR
LI7
SW_USB20_N9
SW_USB20_P9
C C
USB20_N9<10>
USB20_P9<10>
USB_OC0#<10>
USB_POWERSHARE_VBUS_EN<35>
USB_POWERSHARE_EN#<35>
+5V_ALW
ILIM_SEL
RI13
12
10K_0402_5%
ILIM_SEL
+5V_ALW
UI3
1
VIN
2
DM_OUT
3
DP_OUT
13
FAULT#
4
ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
SLGC55544CVTR_TQFN16_3X3
Link Seligro SA000097E10 Done
Thermal Pad
MAIN: SLGC55544CV TR
VOUT
DP_IN
DM_IN
ILIM_L
ILIM_HI
GND
NC
+5V_USB_CHG_PWR
12
SW_USB20_P9
10
SW_USB20_N9
11
15
16
RI14
9
14
17
12
22.1K_0402_1%
EMI@
1 2
EXC24CQ900U_4P
USB20_N9_R
34
USB20_P9_R
68P_0402_50V 8J
RF@
12P_0402_50V 8J
RF@
1
1
CI44
CI43
2
2
B B
A A
+5V_ALW
47U_0603_6.3V6M
47U_0603_6.3V6M
@
1
1
CI34
2
2
@
1
CI33
2
Place near UI3.1
10U_0402_6.3V6M
0.1U_0201_10V6K
@
CI19
1
CI31
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
JUSB1+PS
JUSB1+PS
JUSB1+PS
LA-F391P
LA-F391P
LA-F391P
43 70Tuesday, September 19, 2017
43 70Tuesday, September 19, 2017
43 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
For Breckenridge/Steamboat 12&Kirkwood
DI1
USB3_PRX_DTX_N3<10>
USB3_PRX_DTX_P3<10>
USB3_PTX_DRX_N3<10>
USB3_PTX_DRX_P3<10>
D D
C C
12
CI5 0.1U_0402_25V6
12
CI4 0.1U_0402_25V6
USB3_PRX_DTX_N3 USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3
USB20_P2<10>
USB20_N2<10>
USB20_P2
USB20_N2
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm
ESD@
1
1
2
2
4
4
5
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
LI3
1 2
EXC24CQ900U_4P
EMI@
9
10
8
9
7
7
6
6
34
USB20_P2_R
USB20_N2_R
+USB_EX2_PWR
+5V_ALW
12
RF Request
12P_040 2_50V8J
RF@
1
1
CI45
2
2
0.1U_02 01_10V6K
10U_060 3_10V6M
CI7
@
1
CI6
2
+USB_EX2_PWR
USB20_N2_R
223
1
1
USB20_P2_R
USB3_PRX_DTX_N3
USB3_PRX_DTX_P3
AZC199-02 SPR7G_SOT23-3
USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3
ESD@
DI2
0.1U_02 01_10V6K
68P_040 2_50V8J
RF@
CI46
100U_12 06_6.3V6M
CI3
1
12
CI1
3
2
JUSB2
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
ACON_TCRA2-9U1U93
CONN@
10
GND
11
GND
12
GND
13
GND
Link TCRA2-9U1U93 DONE
+USB_EX2_PWR
UI1
1
OUT
5
IN
2
GND
USB_PWR_EN1#<35>
4
EN
OCB
SY6288D20AAC_SOT23-5
3
USB_OC1# <10>
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
JUSB2
JUSB2
JUSB2
LA-F391P
LA-F391P
LA-F391P
1
44 70Tuesday, September 19, 2017
44 70Tuesday, September 19, 2017
44 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
Touch Pad
D D
DAT_TP_SIO_I2C_CLK<35>
CLK_TP_SIO_I2C_DAT<35>
C C
I2C1_SDA_TP<9>
I2C1_SCK_TP<9>
I2C From CPU
10P_0402_50V 8J
10P_0402_50V 8J
12
12
CZ80
CZ81
4
+3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
12
12
RZ22 0_0402_5%@
RZ23 0_0402_5%@
12
12
12
@
RZ3460_0402_5%
12
@
RZ3470_0402_5%
RZ19
RZ18
PS2
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C1_SDA_TP_R
I2C1_SCK_TP_R
I2C From EC
+3.3V_TP +3.3V_TP
10K_0402_5%
12
12
RZ21
RZ20
1 2
@
RZ26 0_0402_5%
1 2
@
RZ29 0_0402_5%
I2C1_SDA_TP_R
I2C1_SCK_TP_R
2.2K_0402_5%
2.2K_0402_5%
12
@
RZ116
3
+3.3V_RUN +3.3V_TP
PJP35
1 2
PAD-OPEN1x1m
Keyboard
KB_DET#<12>
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117<35>
BC_DAT_ECE1117<35>
BC_CLK_ECE1117<35>
10K_0402_5%
12
@
RZ117
+3.3V_TP
TOUCHPAD_INTR#<12,35>
2
KB_DET#
BC_INT#_ECE1117
BC_DAT_ECE1117
BC_CLK_ECE1117
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C1_SDA_TP_R
I2C1_SCK_TP_R
+3.3V_TP
1
RF@
68P_0402_50V8J
2
CONN@
JKBTP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND
22
GND
CVILU_CF5020FD0RK-05-NH
CZ83
1
RF Request
KB_DET#
BC_INT#_ECE1117
BC_DAT_ECE1117
BC_CLK_ECE1117
DAT_TP_SIO_R
CLK_TP_SIO_R
1 2
CZ84 68P_0402_50V8JRF@
1 2
CZ85 68P_0402_50V8J@RF@
1 2
CZ86 68P_0402_50V8J@RF@
1 2
CZ87 68P_0402_50V8J@RF@
1 2
CZ88 68P_0402_50V8J@RF@
1 2
CZ89 68P_0402_50V8J@RF@
+5V_RUN+3.3V_ALW+3.3V_TP
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
2
@
@
CZ91
CZ90
2
Place close to JKBTP1
0.1U_0201_10V6K
1
@
CZ92
2
Link HRS_TF49-20S-0P5SH done
Plan is for I2C to be driven by the EC for Win7 and Pre-OS ( will utilize I ntel I2C drivers for Win7)
For W in8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 fr om EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
PCH_RSMRST#<35>
ALW_PWRGD_3V_5V<11,51>
A A
5
4
1
2
1 2
0.1U_0201_10V6K
5
P
B
4
O
A
G
3
TC7SH08FU_SSOP5~D
CZ82
@
PCH_RSMRST#_AND <11,14>
UZ6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTH ER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOC UMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS WAY B E USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CON SENT.
3
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-F391P
LA-F391P
LA-F391P
45 70Tuesday, September 19, 2017
45 70Tuesday, September 19, 2017
45 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
Bat t er y LE D
means EC can sw itch battery white led a nd HDD LED by hot ke y “ Fn+H”
MASK_SATA_LED#<35>
D D
SATALED#<10,33,40>
BAT2_LED#<35,46>
HDD LED MUX
5
BAT2_LED#_R
34
QZ2B
@
DMN65D8LDW-7_SOT363-6
+3.3V_ALW
2
61
QZ2A
@
DMN65D8LDW-7_SOT363-6
BAT2_LED#_R
BATT_WHITE#
BAT2_LED#<35,46>
R1=10K;R 2=1 0K
QZ3
@
R2
2
DDTA114EUA-7-F_SOT323-3
Need L INK SB000 002T00 Symb ol
R1
1 3
RZ25 150_0402_5%@
1 2
BAT1_LED#<35>
1 2
RZ361 150_0402_5%
1 2
RZ28 330_0402_5%
BATT_WHITE#
BATT_YELLOW#
LED P/N change to SC50000FL00 from SC 50000BA00
Breath LED
QZ7B
C C
+3.3V_ALW
CZ93
@
1 2
0.1U_0201_10V6K
5
1
MASK_BASE_LEDS#
LED_MASK#<30,35>
LID_CL#<36,46>
B
2
A
P
4
O
G
UZ10
TC7SH08FU_SSOP5~D
3
BREATH_LED#<35>
DMN65D8LDW-7_SOT363-6
BREATH_LED#_Q BREATH_WHITE_LED_SNIFF#
34
5
MASK_BASE_LEDS#
1 2
RZ32 330_0402_5%
LTW-C193DC-C_WHITE
Place LED3 close to SW3
+5V_ALW
LED3
21
POWER & INSTANT ON SWITCH
LED board CONN
SW3
1
POWER_SW#_MB<11,36>
B B
Fiducial Mark
FD1@
1
FIDUCIAL MARK~D
FD2@
1
FIDUCIAL MARK~D
FD3@
1
FIDUCIAL MARK~D
FD4@
1
FIDUCIAL MARK~D
A A
Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
H1@
H2@
H_3P8
H_3P8
1
1
EDP Standof f
H34@
H_3P3
1
2
4
SKRBAAE010_4P
CPU
H3@
H4@
H_3P8
H_3P8
H_1P1N
1
1
For JAE JSIM 1 boss hole
H42@
H_0P7N
H_0P9N
1
3
LED Circuit Control Table
NGFF Standof f
H5@
1
H43@
1
H_1P1N
H7@
H6@
H_3P2
1
1
LED_MA SK# LID_C L#
H11@
H_2P1X3P6
1
X
0
1 0
H10@
H9@
H8@
H_2P8
H_2P8
H_3P2
1
1
1
H14@
H_4P2X5P2
1
H_2P8
+5V_ALW
BATT_YELLOW#
BATT_WHITE#
LID_CL#<36,46>
+3.3V_ALW
H19@
H15@
H_3P0
1
H18@
H17@
H16@
1
H_2P8
H_2P8
H_2P8
H_2P8
1
1
1
H22@
H20@
H_2P1
1
H23@
H21@
H_2P8
1
H24@
H_3P0
H_3P0
1
1
1
JLED1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND1
8
GND2
CVILU_CF5006FD0R0-05-NH
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENG INEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Size Docum ent Numb er Re v
Dat e: Shee t of
Dat e: Shee t of
Dat e: Shee t of
PAD, LED
PAD, LED
PAD, LED
LA-F391P
LA-F391P
LA-F391P
1
46 70Tuesday, September 19, 2017
46 70Tuesday, September 19, 2017
46 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+3.3V_WWAN/+3.3V_LAN source
PJP41
+3.3V_ALW
D D
3.3V_WWAN_EN<35>
3.3V_WWAN_EN
1 2
RZ40 100K_0402_5%
3.3V_WWAN_EN
+5V_ALW
SIO_SLP_LAN#<11,35>
UZ2
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VOUT2
VIN27VOUT2
GPAD
EM5209VF_SON14_2X3
+3.3V_WWAN_UZ2
14
13
12
CT1
11
GND
10
CT2
9
+3.3V_LAN_UZ2
8
15
1 2
PAD-OPEN1x3m
CZ119 0.1U_0201_10V6K
1 2
CZ109 470P_0402_50V7K
1 2
CZ110 470P_0402_50V7K
1 2
CZ111 0.1U_0201_10V6K
PJP37
1 2
PAD-OPEN1x1m
1 2
+3.3V_LAN
1A
+3.3V_WWAN
2.5A
+3.3V_WWAN_UZ2
1
RF@
2200P_0402_50V7K
2
RF Request
CZ124
+3.3V_ALW_PCH/+3.3V_RUN source
0.63A
PJP38
1 2
+3.3V_ALW
C C
1 2
PCH_ALW_ON<35>
PCH_PRIM_EN<11,17,53,54,55>
RZ65 0_0402_5%@
@
1 2
RZ64 0_0402_5%
+5V_ALW
RUN_ON
UZ3
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
GND
VOUT2
GPAD
CT1
CT2
+3.3V_ALW_PCH_UZ3
14
13
12
11
10
9
+3.3V_RUN_UZ3
8
15
PAD-OPEN1x1m
CZ112 0.1U_0201_10V6K
CZ113 470P_0402_50V7K
CZ114 1000P_0402_50V7K
CZ115 0.1U_0201_10V6K
1 2
PAD-OPEN1x3m
1 2
1 2
1 2
1 2
PJP39
+3.3V_ALW_PCH
+3.3V_RUN
3.435A
RUN_ON#<35>
Reserve for S3 no power issue (+5V_RUN discharge circuit)
+1.8V_RUN source
RUN_ON<17,35,36,47,54>
@
RZ345 0_0402_5%
Reserve R/C for Audio power s equence, + 5V->+3.3V->+1.8V
+5V_RUN
12
@
RZ370
100_0603_5%
+5V_RUN_CHG
13
D
@
2
QZ4
G
L2N7002WT1G_SC-70-3
S
1 2
RUN_ON_1.8V
+5V_ALW
12
CZ197
@
470P_0402_50V7K
+1.8V_PRIM
UZ8
1
VIN
2
VIN
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
VOUT
VOUT
GND
GND
CT
7
8
6
5
9
+1.8V_RUN_UZ8
0.013A
PJP42
1 2
PAD-OPEN1x1m
1 2
CZ120 0.1U_0201_10V6K
1 2
CZ121 470P_0402_50V7K
+1.8V_RUN
+5V_RUN/+3.3V_WLAN source
B B
PJP40
+5V_ALW
RUN_ON<17,35,36,47,54>
WLAN_PWR_EN
+3.3V_ALW
WLAN_PWR_EN
1 2
RZ38 100K_0402_5%
A A
5
UZ4
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
VOUT2
GPAD
GND
CT1
CT2
14
13
12
11
10
+3.3V_WLAN_UZ4
9
8
15
+5V_RUN_UZ4
1 2
PAD-OPEN1x2m
1 2
CZ116 0.1U_0201_10V6K
1 2
CZ117 470P_0402_50V7K
1 2
CZ118 470P_0402_50V7K
1 2
CZ122 0.1U_0201_10V6K
1 2
PAD-OPEN1x2m
@
1 2
0.01_1206_1%
Co- lay :
Short PJP36;Depop R Z96
4
PJP36
RZ96
2A
+5V_RUN
+3.3V_WLAN
+3.3V_ALW
12
RZ518
10K_0402_5%
SLP_WLAN#_GATE<35>
SIO_SLP_WLAN#<11,35>
S TR BSS138W 1N SOT-323-3
QZ15
2
1 3
D
G
S
SLP_WLAN#_M
AUX_EN_WOWL<35>
2A
EC request to reserve OR gate for W LAN power enable
1 2
RZ71 0_0402_5%@
DZ9
3
2
BAT54CW_SOT323-3
1 2
RZ70 0_0402_5%@
WLAN_PWR_EN
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CONTAINS C ONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DEL L") THIS DOCUME NT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Power control
Power control
Power control
LA-F391P
LA-F391P
LA-F391P
1
47 70Tuesday, September 19, 2017
47 70Tuesday, September 19, 2017
47 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
Timing Diagram for S5 to S0 mode
D D
6
C C
VCCST_PWRGD
12
H_CPUPWRG D
15
PCH_PLTRS T#
17
0.6V_DDR_VTT_ON
12
+1.0V _PRIM_COR E
+1.8V _PRIM
6
6
+1.0V _PRIM SYX19 8
CPU
VCCST_PWRGD
PROCPWRGD
PLTRST#
DDR_VTT_CN TL
+5V_ ALW
TLV621 30
+3.3V_ALW
RT809 7A
+PW R_SRC
VCCIO
VCCGT
VDDQ
VDDQC
VCCPLL_OC
VCCST
VCCS TG
VCCP LL
VCCS A
PCH_PRIM_E N
(SIO_SLP_SUS# )
+VCC _CORE
VCC
+1.0VS_ VCCIO
+VCC _GT
+1.2V _MEM
+1.0V _VCCST
+VCC _SA
4
+1.0V _PRIM
11
TPS22 961
SIO_SLP_S4#
+LCD VDD
11
+3.3V _TSP
3
+3.3V_ALW
+3.3V_S PI
3
+1.0V _MPHYGT
+3.3V_ALW _DSW
+3.3V _ALW_PCH
5
6
+1.0V _PRIM_COR E
6
17
4
+3.3V_ALW
G524B 1T11U
+3.3V_ALW
EM5209V F+3. 3V_LAN
+5V_ RUN
LP230 1ALT1G
+3.3V _RUN
LP230 1ALT1G+3.3V_CAM
+1.0V _PRIM
+1.8V _PRIM
+RTC _CELL
PCH_PLTRS T#
PCH_DPWROK
ENVDD_PC H
SIO_SLP_LAN#
3.3V_TS_EN
3.3V_CAM_EN#
VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW_1P 0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
VCCDSW_3P 3
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCP GPPA~ E
VCCR TCPR IM
VCCPGPPG
VCCATS
VCCRTC
VCCPRIM_CORE
PLTRST#
DSW_PWROK
EDP_VDDE N
SLP_LAN#
GPP_B21
GPD7
PCH
PWRBTN#
RSMRST#
SLP_SUS#
SLP_S5#
SLP_S4#
SLP_S3#
SLP_LAN#
SLP_WLAN#/GPD9
SYS_ PWR OK
PCH_PWROK
VCCST_PWRGD
PROCPWRGD
SLP_A#
2
SIO_PWRBTN#
PCH_RSMRST#
SIO_SLP_SUS #
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_WLAN#
RESET_OUT#
PCH_PWROK
VCCST_PWRGD
H_CPUPWRG D
10
SIO_SLP_S4#
0.6V_DDR_VTT_ON
11
16
14
12
15
10
5
8
7
9
+PW R_SRC
SY8210 A
1
+1.2V _MEM
+0.6V _DDR_VT T
12
VDDQ
VTT
DDR
Power Button
11
SIO_SLP_WLAN#
EC 5105
11
RUN_ON
+5V_ ALW
EM5209V F
+3.3V_ALW
EM5209V F
+5V_ RUN
+3.3V _RUN
+5V_ HDD
+3.3V _HDD
ADAPTE R
BATTE RY
2AC1BAT
+PW R_SRC
ALWON
+PW R_SRC
SY8288 CEC 5105
SY8288 B
+5V_ ALW2
+5V_ ALW
+3.3V _RTC_LD O
+3.3V_ALW 2
+3.3V_ALW
1BAT
2AC
B B
@SIO_SLP_WLAN #
+3.3V_ALW
+3.3V_W LAN EM5209V F
11
A A
AUX_EN_WOWL
+5V_ ALW
TPS62 134C
+1.0VS_ VCCIO
13
+VCC _SA
+VCC _CORE
+VCC _GT
PCH_PWROK
7
4
16
5
10
9
11
+PW R_SRC
ISL958 57
14
PCH_RSMRST#
PCH_DPWROK
RESET_OUT#
SIO_SLP_SUS #
SIO_SLP_S4#
SIO_SLP_S5#
SIO_SLP_LAN#
SIO_SLP_S3#
SIO_SLP_A#
12
IMVP_VR_ON
5
PCH_PRIM_E N
(SIO_SLP_SUS# )
@PCH_ALW_ON
EN_INVPWR
+3.3V_ALW
EM5209V F
+PW R_SRC
AO6405
+3.3V _ALW_PCH
+BL_ PWR_S RC
5
Pop option
+3.3V_S PI
18
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date : She et of
Date : She et of
Date : She et of
LA-F391P
LA-F391P
LA-F391P
Power Sequence
Power Sequence
Power Sequence
1
48 70Tuesday, September 19, 2017
48 70Tuesday, September 19, 2017
48 70Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
D D
1
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Stack-up
Stack-up
Stack-up
LA-F391P
LA-F391P
LA-F391P
49 70Tuesday, September 19, 2017
49 70Tuesday, September 19, 2017
49 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR2
PD3
PQ1B
3
PBAT_PRES# <35,59>PBAT_CHARGER_SMBCLK <35,59>
12
PR17
100K_0402_5%
34
+Z4012
2
1
PS_ID <35>
5
1K_0402_5%
1
2
+3.3V_VDD_DCIN
PR25
@
1 2
0_0402_5%
+COINCELL
+RTC_CELL
PC3
1U_0603_25V6K
12
PC10
2.2U_0402_10V6M
+3.3V_RTC_LDO
D D
1
PD1
ESD@
TVNST52302AB0_SOT523-3
2
Primary Battery Connector
PBATT1
@
1
1
2
2
3
3
4
4
5
5
12
PC1
EMC@
2200P_04 02_50V7K
C C
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
DEREN_40-42251-01001RHF
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
GND
NB_PSID PS_ID
2
3
1
PRP1
100_0804_8P4R_5%
PL3
EMC@
BLM15AG102SN1D_2P
PD4
ESD@
AZ5125-02S.R7G_SOT23-3
+DC_IN
PL4
EMC@
FBMJ4516HS720NT_2P
1 2
B B
12
PR28
100K_040 2_5%
+3.3V_ALW
12
PC5
EMC@
1000P_06 03_50V7K
HW_ACAVIN_NB<35,59,60>
PQ8
L2N7002WT1G_SC70-3
D
S
13
G
2
12
PR29
@
0_0402_5%
PJPDC1
@
-DCIN_JACK-DCIN_JACK
1
1
2
+DCIN_JACK
2
3
3
4
4
5
5
ACES_50290-0050N-001
A A
DCIN2_EN<35>
1 2
PR26
@
0_0402_5%
5
12
12
PC7
PR13
@
0.1U_060 3_25V7K
@EMC@
12
PR27
100K_0402_5%
+3.3V_VDD_DCIN
4.7K_080 5_5%
0.1U_0402_10V7K
PR21
@
1 2
0_0402_5%
1 2
PR22
@
0_0402_5%
12
PC9
12
1
B
2
A
PD6
PC6
1 2
@
0.022U_0 603_50V7K
DFLS160-7_ POWERDI123-2
+3.3V_VDD_DCIN
PU1
5
MC74VHC1G08DFT2G_SC70-5P
P
4
1 2
O
G
3
4
@
0_0402_5%
3
18
27
36
45
12
DC_IN+ Source
S1 S2
PQ9
EMZB08P03V 1P EDFN3X3-8
1
2
3 5
PR12
1M_0402_ 5%
12
4
12
PR18
1M_0402_5%
13
D
2
G
S
PR30
100K_0402_5%
PQ6
L2N7002 WT1G_SC70-3
12
PR23
2
100K_0402_1%
15K_0402_1%
12
PR14
1
PD2
ESD@
TVNST52302AB0_SOT523-3
3
PBAT_CHARGER_SMBDAT <35,59>
PR6
1 2
PR8
1 2
+DC_IN_SS
12
PC8
10U_080 5_25V6K
100K_040 2_5%
PBATT+_C
PR3
@
1 2
0_0402_5%
1 3
D
S
PQ2
FDV301N-G_SOT23-3
G
2
C
PQ3
2
B
MMST3904-7-F_SOT323~D
E
3 1
S SCH DIO 5A 100V 15UA 0.88V TO227-3
PL1
EMC@
FBMJ4516HS720NT_2P
1 2
PL2
EMC@
FBMJ4516HS720NT_2P
1 2
+PBATT
+3.3V_ALW
12
PR1
100K_0402_5%
BAS40CW SOT-323
+3.3V_ALW
PR4
PR5
33_0402_5%
1 2
2.2K_0402_5%
1 2
+5V_ALW
12
PR7
10K_0402_1%
PD5
2
1
3
PQ4
EMZB08P03V 1P EDFN3X3-8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF C OMPAL ELECTRONICS, INC.
3
1
2
35
4
12
PR16
49.9K_04 02_1%
13
D
2
1 2
PQ7
0_0402_5%
G
S
L2N7002 WT1G_SC70-3
+SDC_IN
+SDC_IN
12
12
PC4
12
PR11
499K_040 2_1%
0.022U_0 603_50V7K
AO3409 P- CHANNEL SOT-23
PR20
@
12
PR24
100K_0402_5%
S
D
1 3
DMN65D8LDW- 7_SOT363-6
PQ5
G
2
PQ1A
12
61
PR10
300K_0402_5%
PR15
100K_0402_5%
PR19
@
1 2
2
0_0402_5%
VBUS2_ECOK <35,60>
+3.3V_VDD_DCIN
DMN65D8LDW- 7_SOT363-6
2
12
PC2
JRTC1
@
EMC@
2200P_04 02_50V7K
1
3
1
G
4
22G
ACES_50271-0020N-001
+DC_IN
1000P_06 03_50V7K
PC11
12
3
AC_DISC# <35,60>
PU2
RT9058-33GX SOT-89 3P LDO
VOUT
11/11
1
VCC
2
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Shee t of
Date : Shee t of
Date : Shee t of
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-F391P
LA-F391P
LA-F391P
1
50 65Tuesday, September 19, 2017
50 65Tuesday, September 19, 2017
50 65Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
A
1 1
+PWR_SRC
PJP100
21
PAD-OPEN 1x2m~D
12
12
PC133
PC134
1000P_0402_50 V7K
1000P_0402_50 V7K
@EMC@
@EMC@
2 2
12
12
PC135
1U_0402_25V6K
@EMC@
12
PC151
PC136
1U_0402_25V6K
RF@
@EMC@
100P_0402_50V 8J
PC100
RF@
+3.3V_ALW
12
PC103
100P_0402_50V 8J
100P_0402_50V 8J
RF@
PR107
100K_0402_5%
1 2
PGOOD_3V
12
3V_VIN
PC105
12
PC104
10U_0805_25V6K
10U_0805_25V6K
B
BST_3V
2
EN112EN2
IN3IN4IN
FF13OUT14NC
3V_FB
1
IN
BS
20
LX
19
LX
18
GND
17
LDO
16
NC
21
GND
15
PC113
1000P_0402_50V7K
1 2
12
PC111
4.7U_0603_6.3V6K
PR108
1K_0402_5%
1 2
5
LX_3V
3V5V_EN
PU100
6
LX
7
GND
8
SY8288BRAC_QFN20_3X3
GND
9
PG
10
NC
11
ENLDO_3V5V
12
C
@
1 2
0_0603_5%
PR104
@
0_0402_5%
1 2
PR105
@
0_0402_5%
1 2
PR100
LX_3V
PC102
1 2
0.1U_0603_25V7K
+3.3V_ALW2
+3.3V_RTC_LDO
3.3V LDO 150mA~300mA
PR106
12
RF@
4.7_1206_5%
3V_SN
12
PC112
RF@
680P_0603_50V 7K
PGOOD_3V
PGOOD_5V
ENLDO_3V5V
PL100
1.5UH_9A_20%_7X7X3_M
1 2
D
PR119
@
0_0402_5%
1 2
1 2
PR120
@
0_0402_5%
PR102
499K_0402_1%
1 2
12
PR103
499K_0402_1%
12
12
PC106
22UF_0805_6.3V6M
12
12
PC107
PC108
22UF_0805_6.3V6M
22UF_0805_6.3V6M
Vout is 3.234V~3.366V
E
ALW_PWRGD_3V_5V <11,45>
+PWR_SRC
+3.3V_ALWP
12
12
12
PC129
PC109
22UF_0805_6.3V6M
+3.3V_ALWP +3.3V_ALW
PC153
PC110
RF@
22UF_0805_6.3V6M
22UF_0805_6.3V6M
3VALWP
100P_0402_50V 8J
TDC 6.8 A
Peak Current 9.7 A
OCP Current 9A f i x by I C
PJP102
2
112
JUMP_43X118
+PWR_SRC
PJP101
PAD-OPEN 1x2m~D
12
12
PC137
3 3
4 4
PC138
1000P_0402_50 V7K
1000P_0402_50 V7K
@EMC@
@EMC@
ALWON<35>
12
12
PC139
1U_0402_25V6K
@EMC@
PC140
@EMC@
1U_0402_25V6K
12
PC152
RF@
PR114
@
1 2
0_0402_5%
100P_0402_50V 8J
12
5V_VIN
21
12
12
PC116
100P_0402_50V 8J
RF@
3V5V_EN
PC128
4.7U_0603_6.3V6K~D
PC117
10U_0805_25V6K
12
PC118
10U_0805_25V6K
PR113
100K_0402_5%
1 2
PGOOD_5V
PC115
RF@
100P_0402_50V 8J
+3.3V_ALW
12
PR116
1M_0402_1%
EN1 and EN2 dont't floating
5
12
12
PC131
RF@
100P_0402_50V 8J
LX_5V
PU102
6
LX
7
GND
SYV828CRAC QFN 20P PWM
8
GND
9
PG
10
NC
EN112EN2
11
3V5V_EN
ENLDO_3V5V
IN3IN4IN
FF13OUT14LDO
2
1
IN
BS
LX
LX
GND
VCC
NC
GND
15
12
PC126
5V_FB
BST_5V
20
19
18
17
16
21
+5V_ALW2
5V LDO 150mA~300mA
4.7U_0603_6.3V6K
PC127
1000P_0402_50V7K
1 2
@
1 2
0_0603_5%
LX_5V
PC119
1 2
4.7U_0603_6.3V6K
1K_0402_5%
1 2
PR111
PR117
PC114
1 2
0.1U_0603_25V7K
PL101
1.5UH_9A_20%_7X7X3_M
1 2
12
PR112
RF@
4.7_1206_5%
5V_SN
12
PC125
RF@
680P_0603_50V 7K
12
12
PC132
RF@
100P_0402_50V 8J
12
12
PC120
22UF_0805_6.3V6M
PC122
PC121
22UF_0805_6.3V6M
22UF_0805_6.3V6M
5VALWP
TDC 6.5 A
Peak Current 9.3 A
OCP Current 9A f i x by I C
12
12
PC123
22UF_0805_6.3V6M
PJP103
112
JUMP_43X118
2
+5V_ALW+5V_ALWP
+5V_ALWP
12
PC130
PC124
22UF_0805_6.3V6M
22UF_0805_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-F391P
LA-F391P
LA-F391P
51 65Tuesday, September 19, 2017
51 65Tuesday, September 19, 2017
51 65Tuesday, September 19, 2017
E
0.2
0.2
0.2
Vinafix.com
5
D D
4
3
2
1
+PWR_SRC
C C
The current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 12A
B B
PJP202
PAD-OPEN 1x2m~D
21
PC200
10U_0603_25V6M
12
PC201
10U_0603_25V6M
+3.3V_ALW
1 2
1 2
0.6V_DDR_VTT_ON<20>
12
@
PR205
0_0402_5%
ILMT_DDR
@
PR207
0_0402_5%
2200P_0402_50V7K
0.1U_0402_25V6
12
12
SIO_SLP_S4#<11,17,35,55>
@EMC@
@EMC@
PC203
PC202
12
PC231
RF@
@
PR208
1 2
0_0402_5%
@
PR210
1 2
0_0402_5%
+3.3V_ALW
100P_0402_50V8J
1U_0402_6.3V6K
12
PR209
1M_0402_5%
+1.2V_DDR_B+
PC206
2.2U_0402_6.3V6M
12
12
@
12
PC207
ILMT_DDR
EN_1.2V
EN_0.6V
12
PC221
0.1U_0402_10V7K
1M_0402_5%
12
PR212
PU200
10
IN
13
BYP
14
VCC
4
VTTGND
9
PGND
15
SGND
17
ILMT
1
S5
2
S3
SY8210AQVC_QFN19_4X3
0.1U_0402_10V7K
@
PC222
19
OT
18
PG
12
BS
11
LX
16
FB
8
VDDQSNS
7
VLDOIN
6
VTT
5
VTTSNS
3
VTTREF
Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off
PR203
@
0_0603_5%
1 2
LX_DDR
+1.2V_DDRP
PC205
1 2
0.1U_0603_16V7K
PC218
1U_0402_10V6K
12
12
RF@
PR202
4.7_1206_5%
1 2
1 2
S COIL 1UH +-20% PCMB063T-1R0MS 12A
PC209
22U_0603_6.3V6M
1 2
+0.6VSP
22U_0603_6.3V6M
PC219
RF@
PC204
680P_0603_50V7K
1 2
PL201
330P_0402_50V7K
PC208
12
R1
R2
PJP200
JUMP_43X118
112
+1.2V_DDR
TDC 6.2A
Peak Current 8.9A
OCP Current 12A
+1.2V_DDRP
EMC@
10U_0603_6.3V6M
PJP201
EMC@
2200P_0402_50V7K
100P_0402_50V8J
PC214
12
PC217
PC216
12
+0.6V_DDR_VTT+0.6VSP+1.2V_MEM+1.2V_DDRP
2
102K_0402_1%
12
PR204
22U_0603_6.3V6M
PC210
12
100K_0402_1%
12
PR206
2
22U_0603_6.3V6M
22U_0603_6.3V6M
PC212
PC211
12
12
10U_0603_6.3V6M
22U_0603_6.3V6M
PC223
PC213
12
12
12
JUMP_43X39
112
0.6Volt +/- 5%
TDC 1.05A
Peak Current 1.5A
OCP Current 4.2A (fix)
Note: S3 - sleep ; S5 - power off
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EX CEPT AS AUTHORIZED B Y COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Dat e: Shee t o f
Dat e: Shee t o f
Dat e: Shee t o f
Compal Electronics, Inc.
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
LA-F391P
LA-F391P
LA-F391P
52 65Tuesday, September 19, 2017
52 65Tuesday, September 19, 2017
52 65Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
D D
+PWR_SRC
C C
PJP301
PAD-OPEN 1x2m~D
PCH_PRIM_EN<11,17,47,54,55>
21
12
PC301
RF@
PR312
@
0_0402_5%
1 2
PR302
1M_0402_1%
12
PC303
PC305
12
10U_0603_25V6M
100P_0402_50V8J
EN_+1VALWP
RF@
100P_0402_50V8J
+3.3V_ALW
12
PR307
@
B B
0_0402_5%
12
@
0_0402_5%
ILMT_+1VALWP
PR310
4
+1VALWP_B+
12
12
PC306
10U_0603_25V6M
+3.3V_ALW
PC312
4.7U_0603_6.3V6K
+1.0V_PRIM
TDC 5.4A
Peak Current 6.5 A
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
PU301
2
IN
3
IN
4
IN
5
IN
7
GND
8
GND
18
GND
11
EN
13
ILMT
15
BYP
12
SY8286RAC_QFN20_3X3
VCC
PAD
3
PR303
RF@
4.7_1206_5%
1 2
9
PG
BS
LX
LX
LX
FB
NC
NC
NC
1
6
19
20
14
17
10
12
16
21
BST_+1VALWP
PC304
0.1U_0603_25V7K
1 2
SW_+1VALWP
12
PC313
BST_+1VALWP_C
4.7U_0603_6.3V6K
PR304
@
1 2
0_0603_5%
FB_+1VALWP
PL301
0.68UH_7.9A_20%_5X5X3_M
1 2
SNB_+1VALWP
12
PR306
21.5K_0402_1%
12
PR311
31.6K_0402_1%
2
PC302
RF@
680P_0603_50V7K
1 2
12
12
PR308
1K_0402_5%
+1VALWP
12
PC307
330P_0402_50V7K
1
PJP302
2
112
JUMP_43X118
+1.0V_PRIM
+1VALWP
12
12
12
PC308
PC309
PC310
PC311
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EX CEPT AS AUTHORIZED B Y COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Dat e: Shee t o f
Dat e: Shee t o f
Dat e: Shee t o f
Compal Electronics, Inc.
+1VALWP
+1VALWP
+1VALWP
LA-F391P
LA-F391P
LA-F391P
53 65Tuesday, September 19, 2017
53 65Tuesday, September 19, 2017
53 65Tuesday, September 19, 2017
1
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
+3.3V_ALW
LPM LOGIC OUTPUT VOLTAGE
EN_1VS_VCCIO
13
PU401
EN
PVIN
PVIN
TPS62134CRGT_QFN16_3X3
AVIN
VID0
VID1
8
12
PR427
0_0402_ 5%
@
12
14
SS_1VS_VCCIO
@
PR404
0_0402_5%
LPM
12
PJP401
JUMP_43X79
2
+1VS_VCCIOP
12
PR421
0_0402_5%
112
PR422
@
1 2
0_0402_5%
12
12
PC406
PC407
22U_060 3_6.3V6M
VCCIO_SENSE <17>
VSSIO_SENSE <17>
12
12
PC425
22U_060 3_6.3V6M
10U_060 3_6.3V6M
+1VS_VCCIOP +1.0VS_VCCIO
15
17
TP
PGND16PGND
1
VOS
2
SW
3
SW
4
PG
FBS
AGND
5
6SS7
PC410
470P_040 2_50V7K
LX_1VS_VCCIO
+1VS_VCCIOP
PL402
1UH_1277AS-H-1R0N-P2_3.3A_30%
1 2
12
PR405
@EMC@
4.7_0603_5%
SNUB_1VS_VCCIO
12
PC401
@EMC@
470P_0402_50V7K
@
1 2
PR412
0_0402_5%
TPS62134 C 1 0
+1VS_VCCIOP
PC426
10U_060 3_6.3V6M
PR425
@
0_0402_5%
PR402
PR403
1M_0402_1%
1 2
12
VIN_1VS_VCCIO
VID0_VCCIO
VID1_VCCIO
12
PC402
@
0.1U_040 2_25V6
12
11
10
9
SIO_SLP_S0#<11,17,37,54>
@
0_0402_5%
RUN_ON<17,35,36,47>
D D
PL405
@
3A_Z120_40M_0603_2P
Vin=3~1 7V
+5V_ALW
+3.3V_ALW
PR413
PR415
12
PR414
10K_0402_1%
12
PR416
@
10K_0402_1%
VID0_VCCIO
VID1_VCCIO
12
@
10K_0402_1%
12
C C
10K_0402_1%
1 2
PJP403
1 2
PAD-OPEN1x1m
PC408
@EMC@
12
12
PC409
RF@
0.1U_040 2_25V6
1 2
12
12
PC404
PC403
10U_060 3_10V6M
10U_060 3_10V6M
100P_040 2_50V8J
VID1 LOGIC
0
1
1
1
+1.0VS_VCCIO
TDC 2.2 A
Peak Current 3.1 A
OCP Current 4.2 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
"R" for SILERGY
VID0 LOGIC
X
0
1
1
X
0
1
0
1 1.05
0(LPM)
0.80
0.95
1.00
+3.3V_ALW
12
PR410
PR426
@
0_0402_5%
SIO_SLP_S0#<11,17,37,54>
1 2
@
0_0402_5%
PJP402
Ru p
JUMP_43X79
112
2
+1.0V_PRIM_COREP
12
12
PC424
PC415
22U_060 3_6.3V6M
22U_060 3_6.3V6M
+1.0V_PRIM_ CORE
TDC 1.8 A
Peak Current 2.6 A
OCP Current 4.2 A Fix by IC
TYP MAX
Choke D CR 48.0mohm
12
12
PC428
PC427
10U_060 3_6.3V6M
10U_060 3_6.3V6M
TPS62134 D 1 0
LPM LOGIC OUTPUT VOLTAGE
VID1 LOGIC
0
1
1
1
VID0 LOGIC
X
0
1
1
X
0
1
0
1 1.00
0.7(LPM)
0.85
0.90
0.95
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date : Shee t o f
Date : Shee t o f
2
Date : Shee t o f
Compal Electronics, Inc.
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
LA-F391P
LA-F391P
LA-F391P
1
54 65Tuesday, September 19, 2017
54 65Tuesday, September 19, 2017
54 65Tuesday, September 19, 2017
0.2
0.2
0.2
PR406
@
0_0402_5%
PCH_PRIM_EN<11,17,47,53,55>
PL406
@
3A_Z120_40M_0603_2P
B B
+3.3V_ALW
PR417
PR419
12
10K_0402_1%
12
@
10K_0402_1%
12
10K_0402_1%
12
@
10K_0402_1%
A A
PR418
VID0_PRIM_CORE
VID1_PRIM_CORE
PR420
Vin=3~1 7V
+5V_ALW
1 2
1 2
PJP404
PAD-OPEN1x1m
PC417
0.1U_040 2_25V6
@EMC@
CORE_VID0<18>
CORE_VID1<18>
12
PC418
RF@
1 2
12
12
PC413
PC412
10U_060 3_10V6M
10U_060 3_10V6M
12
100P_040 2_50V8J
PR407
1M_0402_1%
VIN_1V_PRIM
PR408
@
0_0402_5%
1 2
PR411
@
0_0402_5%
1 2
12
12
PC411
EN_1.0V_PRIM_C OREP
@
0.1U_040 2_25V6
13
15
14
PU402
EN
PVIN
PVIN
TPS62134DRGT_QFN16_3X3
AVIN
VID0
VID1
8
VID1_PRIM_CORE
LPM
SS_1V_PRIM
12
12
11
10
9
VID0_PRIM_CORE
17
PGND16PGND
AGND
5
6SS7
12
PR428
@
PC420
1M_0402_ 1%
470P_040 2_50V7K
+1.0V_PRIM_COREP +1.0V_PRIM_CORE
TP
1
VOS
SW
SW
PG
FBS
+1.0V_PRIM_COREP
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1V_PRIM
2
3
12
@
100K_0402_1%
SNUB_1V_PRIM
PR424
12
12
4
PL404
1 2
PR409
@EMC@
4.7_0603_5%
PC419
@EMC@
470P_0402_50V7K
PR423
@
0_0402_5%
1 2
"R" for SILERGY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
5
4
3
Vinafix.com
5
+3.3V_ALW
D D
PCH_PRIM_EN<11,17,47,53,54>
C C
4
PC531
1 2
10U_0603_6.3V6M
12
12
PC505
@
0.1U_0402_16V7K
1 2
10U_0603_6.3V6M
VIN_1.8VALW
EN_1.8VALW
PU501
4
IN
5
PG
FB6EN
RT8097ALGE SOT23 6P PWM
PC530
PL502
@
3A_Z120_40M_0603_2P
1 2
PJP501
1 2
PAD-OPEN1x1m
PR505
1M_0402_1%
PR517
100K_0402_5%
12
+3.3V_ALW
1.8V_PRIM_PWRGD<35>
1 2
PR504
@
0_0402_5%
Not e:
When design Vin=5V, please stuff snubber
to prevent Vin damage
3
PJP502
PL501
1 2
20K_0402_1%
FB_1.8VALW
10K_0402_1%
1 2
PAD-OPEN1x1m
PR501
PR506
12
Ru p
12
Rdo wn
+1.8VALWP
Imax= 2A, Ipeak= 3A
FB=0.6 V
LX_1.8VALW
3
LX
2
GND
1
1UH_1277AS-H-1R0N-P2_3.3A_30%
12
PR502
@EMC@
4.7_0603_5%
SNUB_1.8VALW
12
PC506
@EMC@
680P_0402_50V7K
+1.8V_PRIM
12
PC503
68P_0402 _50V8J
2
+1.8VALWP
12
12
PC501
PC504
22U_060 3_6.3V6M
22U_060 3_6.3V6M
+1.8V_PRI M
TDC 0.7 A
Peak Current 1 A
OCP Current 3.5A f i x by I C
1
Vout=0.6V* (1+Rup/Rdown)
B B
+2.5V_M EN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88 W < 1.7W
OCP is 1.1~1.5A
PJP505
+3.3V_ALW
SIO_SLP_S4#<11,17,35,52>
A A
1 2
PAD-OPEN1x1m
1 2
PR513
@
0_0402_5%
1M_0402_1%
PR514
+2.5V_VIN
12
PC514
4.7U_0603_6.3V6K
12
EN_2.5V
12
@
.1U_0402_16V7K
PU503
AP7361C-FGE-7-01_U-DFN3030-8_3X3
9
GND
8
IN
7
NC
6
NC
5
EN
PC513
ADJ/NC
1
OUT
2
NC
3
4
GND
PR515
21.5K_0402_1%
12
12
PR516
10.2K_0402_1%
2.5VSP
12
0.01UF_0402_25V7K
PC515
PAD-OPEN1x1m
12
PC516
22U_0603_6.3V6M
PJP506
1 2
+2.5V_MEM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date : Shee t o f
Date : Shee t o f
Date : Shee t o f
Compal Electronics, Inc.
+1.8VALWP/+1.2V_RUN/2.5V_MEM
+1.8VALWP/+1.2V_RUN/2.5V_MEM
+1.8VALWP/+1.2V_RUN/2.5V_MEM
LA-F391P
LA-F391P
LA-F391P
1
55 65Tuesday, September 19, 2017
55 65Tuesday, September 19, 2017
55 65Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
4
3
2
1
+1.0V_VCCST
12
12
12
Local sense put on HW site
D D
PROCHOT#<12,35,59>
470K_0402_5%_B25/50 4700K
PH601
1 2
1 2
PR631
27.4K_0402_1%
2200P_0402_50V7K
VCCSENSE<15>
C C
VSSSENSE<15>
ISUMP_IA<57>
@
20M_0402_5%
ISUMN_IA<57>
B B
A A
PR658
@
1 2
330P_0402_50V7K
PC619
1 2
0.01UF_0402_25V7K
12
1 2
12
PH602
10K_0402_5%_B25 /50 4250K
PC614
1 2
PC618
PR628
4.99K_0402_1%
12
12
PC641
.1U_0402_16V7K
@
33P_0402_50V8J
PR633
@U42
0.022U_0402_16V7K
@U42
0.022U_0402_16V7K
1 2
1 2
PC605 47P_0402_50V8J~D
PR610
10K_0402_1%
1 2
PR617
4.3K_0402_1%
1 2
PC616
1 2
12
@
11K_0402_1%
PC635
1 2
PC638
ISEN2_IA
12
PC620
@
PC624
0.033U_0402_16V7K
ISEN1_IA<57>
ISEN2_IA<57>
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
PR678
100_0402_1%
1 2
PC617
@
1200P_0402_50V7K
1 2
PC621
680P_0402_50V7K
1 2
0.082U_0402_16V7K
12
PC626
@
0.047U_0402_25V7K
PR613
@
90.9K +-1% 0402
1 2
PC613
330P_0402_50V7K
@
1 2
PR622
@
1.91K_0402_1%
1 2
1 2
PR632
1K_0402_1%
1 2
@
374_0402_1%
1 2
ISEN1_IA
1 2
PR621
316_0402_1%
PR623
2K_0402_1%
PC627
2200P_0402_50V7K
PR638
PR634
@U22
0_0402_5%
1 2
1 2
@U22
PR615
0_0402_5%
1 2
PR601
@
45.3_0402_1%
+3.3V_RUN
I_SYS<35,59>
+5V_ALW
VCC_GT_SENSE<16>
VSS_GT_SENSE<16>
12
PR605
PR604
75_0402_1%
100_0402_1%
PCH_PWROK<11>
IMVP_VR_ON<36>
PR620
@
0_0402_5%
1 2
FCCM_IA<57>
PWM1_IA<57>
PWM2_IA<57>
PH603
470K_0402_5%_B25/50 4700K
1 2
PR647
27.4K_0402_1%
1 2
PC629
2200P_0402_50V7K
1 2
PC639
1500P_0402_50V7K
1 2
1 2
PR648
1.91K_0402_1%
PC651
@
1 2
330P_0402_50V7K
PC654
1 2
0.01UF_0402_25V7K
PC602
0.1U_0402_25V6
1 2
1 2
1 2
1 2
1 2
PR614 0_0402_5%@
1 2
PR616 0_0402_5%@
PU602
1
2
3
4
5
6
7
8
9
10
41
PC625
330P_0402_50V7K
1 2
PR629
88.7K_0402_1%
1 2
1 2
10K_0402_1%
PR639
3.09K_0402_1%
1 2
PC636
33P_0402_50V8J
1 2
PR645
1 2
PR6250_0402_5%@
PR62610_0402_1%
PR6121.91K_0402_1%
PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B
AGND
PR635
316_0402_1%
PR61849.9_0402_1%
39
40
VR_ENABLE
FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A
12
1 2
12
PC653
@
1 2
PR602
@
0_0402_5%
1 2
PR603
@
12
12
1 2
VIDSOUT_B
VIDSCLK_B
VIDALERT_N_B
36
37
38
35
SCLK
ALERT#
VR_HOT#
VR_READY
16
IMON_GT
NTC_GT
COMP_GT
2K_0402_1%
PR650
PC647
680P_0402_50V7 K
0.082U_0402_16V7K
PR608
88.7K_0402_1%
1 2
PR611
1.87K +-1% 0402
32
33
34
VIN
VCC
SDA
PROG231PROG1
PWM_C
FCCM_C
ISUMN_C
ISUMP_C
RTN_C
FB_C
COMP_C
IMON_C
PWM_A
FCCM_A
FB_A
RTN_A18ISUMP_A19ISUMN_A
17
20
ISL95857AHRTZ-T TQFN 40P PWM
FB_GT
PR657
4.42K_0402_1%
1 2
PR653
@
20M_0402_5%
ISUMP_GT <57>
PC604
PC603
0.22U_0603_25V7K
1U_0603_10V6K
PWM_VSA
30
FCCM_VSA
29
28
27
26
FB_VSA
25
COMP_VSA
24
IMON_VSA
23
22
21
12
PC630
2200P_0402_50V 7K
12
PR644
1K_0402_1%
PC642
0.022U_0402_16V7K
1 2
PC646
0.047U_0402_25V7K
1 2
PR656
11K_0402_1%
1 2
PH605
1 2
10K_0402_5%_B25/50 4250K
12
0_0402_5%
PWM_GT <57>
FCCM_GT <57>
12
CPU_B+
PR640
PC645
374_0402_1%
.1U_0402_16V7K
+5V_ALW
12
ISUMN_GT <57>
For ISUMN_IA Setting
PC624 @U42
0.015U 25V K X7R 0402
PR619 2.2_0603_5%
1 2
1
PC611
0.22U_0603_16V7K
1 2
2
PWM_SA
PR606
@
0_0402_5%
12
12
330P_0402_50V7 K
3
12
PR630
12
4700P_0402_25V 7K
PC631
12
PR651
113K_0402_1%
12
PWM_VSA
PC628
33P 50V J NPO 0402
PC643
VCC_SA U22
TDC 4.0A
Peak Current 4.5A
OCP current 10A
Choke DCR 6.2 m ohm
PC624 @U22
0.022U_0402_16V7K
SA_UGATE
PU614
S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE
UGATE
BOOT
PWM
GND4LGATE
2.49K_0402_1%
12
@
12
PHASE
FCCM
VCC
TP
9
+5V_ALW
1 2
PC632
1000P_0402_50V7K
PR646
1 2
316_0402_1%
1.62K_0402_1%
PR652
2K_0402_1%
PC601
@
680P_0402_50V7 K
8
7
6
SA_LGATE
5
12
PC685
1U_0402_10V6K
1 2
PR636 665 +-1% 0402
PC640
1 2
2200P_0402_50V7K
PR649
1 2
12
PR679
0_0402_5%
FCCM_VSA
1 2
1K_0402_1%
4
D110D2/S1
5
@
PR641
D1
S2
Local sense put on HW site
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
VCC_SA U42
TDC 4.0A
Peak Current 5A
OCP current 10A
Choke DCR 6.2 m ohm
PJP603
VCCSA_B+ CPU_B+
1 2
PAD-OPEN1x1m
VCCSA_B+
12
12
PC608
PC612
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
1
3
2
PQ614
PE642DT 2N PDFN3X3S
D1
D1
G1
SA_SW
9
S2
S2
G2
6
7
8
@EMC@
PR627
PC622
@EMC@
12
PC637
0.033U 25V K X7R 0402
PC644
.1U_0402_16V7K
1 2
@
12
4.7_1206_5%
SA_SNUBSA_SNUB
12
680P_0603_50V7 K
PC650
0.082U_0402_16V7K
12
1 2
4
3
12
PR624
3.65K_0603_1%
ISUMP_VSA
PC633
4700P 50V K X7R 0402
0.01UF_0402_25V7K
330P_0402_50V7K
PL614
0.47UH_MMD05CZR47M_12A_20%
1
+VCC_SA
2
ISUMN_VSA
ISUMP_VSA
12
PR642
2.61K_0402_1%
PR643
12
10KB_0402_5%
1 2
11K_0402_1%
PH604
VSA_SEN- <17>
PC649
1 2
@
PC652
1 2
VSA_SEN+ <17>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Date : S heet of
Date : S heet of
Date : S heet of
Compal Electronics, Inc.
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
LA-F391P
LA-F391P
LA-F391P
1
56 65Tuesday, September 19, 2017
56 65Tuesday, September 19, 2017
56 65Tuesday, September 19, 2017
ISUMN_VSA
0.1
0.1
0.1
Vinafix.com
5
+PWR_SRC
PJP601
1 2
12
PC606 10 0U_D_20VM_R55 M
PC695 100 P_0402_50V8 JRF@
PU610
PGND10SW
VIN9SW
8
VIN
7
PHASE
6
N/C
5
BOOT
4
AGND
3
VCC
2
FCCM
1
PWM
FDMF3035_PQFN31_5X5
8
7
6
5
4
3
2
1
PAD-OPEN 4x4m
PL602
@EMC@
1 2
9A Z80 10M 1812_2P
1
1
+
+
2
2
PC607 10 0U_D_20VM_R55 M
11
12
13
GL
14
PGND
15
PVCC
16
N/C
17
N/C
18
GL
19
AGND
PU613
@U42
PGND10SW
VIN9SW
VIN
GL
PHASE
PGND
N/C
PVCC
BOOT
N/C
AGND
N/C
VCC
FCCM
GL
PWM
AGND
FDMF3035_PQFN31_5X5
11
12
13
14
15
16
17
18
19
CPU_B+
RF@
RF@
12
D D
C C
B B
12
PC682
10U 25V M X5R 0603 ZRB
1 2
+5V_ALW
+5V_ALW
PC656
10U 25V M X5R 0603 ZRB
PR688
1_0603_5%
FCCM_IA<56,57>
PWM1_IA<56>
PC683
@U42
10U 25V M X5R 0603 ZRB
12
12
12
PC657
10U 25V M X5R 0603 ZRB
PC686
0.1U 25V K X5R 0402
VCC_IA1
12
12
PC684
@U42
10U 25V M X5R 0603 ZRB
12
@U42
1_0603_5%
1 2
FCCM_IA<56,57>
PWM2_IA<56>
PC658
10U 25V M X5R 0603 ZRB
PC676
1U_0402 _10V6K
PR659
@
0_0402_5%
1 2
PR687
@
0_0402_5%
1 2
PC672
@U42
10U 25V M X5R 0603 ZRB
PC688
@U42
0.1U 25V K X5R 0402
PR691
12
12
0.22U_0603_16V7K
1 2
3.9_0603_1%
12
PC673
@U42
10U 25V M X5R 0603 ZRB
VCC_IA2
12
PC677
@U42
1U_0402 _10V6K
@U42
0_0402_5%
1 2
@U42
0_0402_5%
1 2
12
PC659
0.1U_040 2_25V6K~D
PC655
1 2
PR660
@U42
0.22U_0603_16V7K
1 2
PR672
@U42
3.9_0603_1%
PR671
PR692
PC660
2200P_04 02_50V7K
PC671
1 2
12
4
12
12
PC689
PC690
1000P_04 02_50V7K
1000P_04 02_50V7K
@EMC@
@EMC@
12
12
PC692
PC691
1U_0402 _25V6K
1U_0402 _25V6K
@EMC@
@EMC@
+5V_ALW
12
12
PC661
PR686
@
1U_0402 _10V6K
10K_0402 _1%
+5V_ALW
12
12
PR689
PC697
@
10K_0402 _1%
1U_0402 _10V6K
@U42
VCC_core (U22)
TDC 21A
Peak Current 32A
OCP current 38.4A
Choke DCR 0.9 +-7%m ohm
12
PC696
RF@
100P_040 2_50V8J
IA_SW1
12
@EMC@
PR663
PR667
3.65K_0603_1%
1 2
4.7_120 6_5%
ISEN1_IA<56>
IA_SNUB1
12
PR676
@EMC@
PC678
@EMC@
IA2N
ISUMP_IA
IA_SW2
@U42
3.65K_0603_1%
1 2
ISUMP_IA
<56,57>
PR674
ISEN2_IA<56>
PC662
680P_060 3_50V7K
@EMC@
12
4.7_120 6_5%
IA_SNUB2
12
680P_060 3_50V7K
PL610
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
4
3
2
IA1N
PR668
12
PL613
@U42
4
3
PR675
@U42
1 2
100K_0402_1%
PR677
@
1 2
100K_0402_1%
12
ISUMN_IA
1
2
PR666
10_0402_1%
IA1P
@U42
1 2
100K_0402_1%
PR670
@
100K_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
IA2P
IA1N
<56,57>
3
VCC_core (U42)
TDC 42A
Peak Current 64A
OCP current 76.8A
Choke DCR 0.9 +-7%m ohm
+VCC_CORE
<56,57>
+VCC_CORE
IA2N
12
PR673
@U42
10_0402_1%
<56,57>
ISUMN_IA
+5V_ALW
+VCC_CORE
@U42
PR682 SOLDER_PREFORMS_0603
2
112
@U22
+VCC_GT
For KBL U42 : Pop PR682 and PR684
For KBL U22 : Pop PR683
SOLDER_PREFORMS_0603
PR683
112
@U42
PR684
SOLDER_PREFORMS_0603
112
12
PC675
PC674
10U 25V M X5R 0603 ZRB
12
PC687
0.1U 25V K X5R 0402
PR680
1_0603_5%
1 2
FCCM_GT<56>
PWM_GT<56>
10U 25V M X5R 0603 ZRB
2
2
12
PC664
10U 25V M X5R 0603 ZRB
VCC_GT
12
PC669
1U_0402 _10V6K
+VCC_GT_+VCC_CORE
+VCC_GT_+VCC_CORE+VCC_CORE
CPU_B+
12
12
PC665
10U 25V M X5R 0603 ZRB
0.22U_0603_16V7K
PR662
@
0_0402_5%
1 2
PR664
@
0_0402_5%
1 2
2
PC663
1 2
1 2
PR665
3.9_0603_1%
U42
PC626 @U42
0.1U 25V 0402
PR638 @U42
475 +-1% 0402
PR613 @U42
93.1K +-1% 0402
PR622 @U42
3.09K_0402_1%
U22
PGND
PVCC
AGND
SW
GL
N/C
N/C
GL
PR613 @U22
86.6K +-1% 0402
PR622 @U22
1.5K +-1% 0402
GT_SW
11
12
13
14
15
16
17
18
19
PC626 @U22
0.047U_0402_25V7K
PR638 @U22
365 +-1% 0402
PU612
PGND10SW
9
VIN
8
VIN
7
PHASE
6
N/C
5
BOOT
4
AGND
3
VCC
2
FCCM
1
PWM
FDMF3035_PQFN31_5X5
VCC_GT (U22)
TDC 18A
Peak Current 31A
OCP current 37.2A
Choke DCR 0.9 +-7%m ohm
12
PR681
@
PR621 @U42
1K +-1% 0402
PC616 @U42
68P 50V J 0402
PR621 @U22
316 +-1% 0402
PC616 @U22
33P 50V J 0402
PR669
EMC@
4.7_1206_5%
1 2
+5V_ALW
12
PC668
1U_0402 _10V6K
10K_0402 _1%
1
PC617 @U42
220P 50V 0402
PC617 @U22
1200P 50V 0402
PC670
EMC@
680P_0603_50V7K
GT_SNUB
1 2
PL612
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
4
3
12
PR661
3.65K_0603_1%
<56>
ISUMP_GT
VCC_GT (U42)
TDC 12A
Peak Current 28A
OCP current 33.6A
Choke DCR 0.9 +-7%m ohm
+VCC_GT
2
<56>
ISUMN_GT
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS, INC.
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
PWR_VCORE_ISL95857
LA-F391P
LA-F391P
LA-F391P
1
0.1
0.1
57 65Tuesday, September 19, 2017
57 65Tuesday, September 19, 2017
57 65Tuesday, September 19, 2017
0.1
Vinafix.com
4 4
3 3
2 2
1 1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
+VCC_CORE +VCC_GT
+220u_D7*3 pcs
22U_0603 * 33 pcs +1U_0201*35 pcs
VCC_CORE Place on CPU
A
B
C
VCC_GT_+VCC_CORE Place on CPU
22U_0603 * 6 pcs
A
PC1326
22U_0603_6.3V6M
PC1325
22U_0603_6.3V6M
PC1324
22U_0603_6.3V6M
PC1323
22U_0603_6.3V6M
PC1322
22U_0603_6.3V6M
PC1327
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC_SA Place on CPU
22U_0603 * 12 pcs + 1U_0201*7 pcs
PC1330
PC1331
PC1332
PC1333
PC1334
+VCC_GT_+VCC_CORE
12
12
12
12
12
12
12
12
12
12
12
1
2
+
PC1127
1
2
+
PC1062
1
2
+
PC1321
@U42
PC1191
RF@
12
100P_0402_50V 8J
PC1192
RF@
12
100P_0402_50V 8J
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
PC1099
1U_0201_6.3V6M
PC1095
1U_0201_6.3V6M
PC1094
1U_0201_6.3V6M
PC1096
1U_0201_6.3V6M
PC1090
1U_0201_6.3V6M
PC1093
1U_0201_6.3V6M
PC1091
1U_0201_6.3V6M
PC1097
1U_0201_6.3V6M
PC1092
1U_0201_6.3V6M
PC1098
1U_0201_6.3V6M
PC1050
1U_0201_6.3V6M
PC1051
1U_0201_6.3V6M
PC1052
1U_0201_6.3V6M
PC1053
1U_0201_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
PC1083
1U_0201_6.3V6M
12
PC1030
1U_0201_6.3V6M
12
PC1031
1U_0201_6.3V6M
12
PC1032
1U_0201_6.3V6M
12
PC1033
1U_0201_6.3V6M
12
PC1034
1U_0201_6.3V6M
12
PC1035
1U_0201_6.3V6M
12
PC1036
1U_0201_6.3V6M
12
PC1037
1U_0201_6.3V6M
12
PC1038
1U_0201_6.3V6M
12
PC1039
1U_0201_6.3V6M
12
PC1084
1U_0201_6.3V6M
12
PC1086
1U_0201_6.3V6M
12
PC1085
1U_0201_6.3V6M
12
PC1088
1U_0201_6.3V6M
12
PC1087
1U_0201_6.3V6M
12
PC1089
1U_0201_6.3V6M
PC1081
22U_0603_6.3V6M
PC1080
22U_0603_6.3V6M
PC1082
22U_0603_6.3V6M
PC1067
22U_0603_6.3V6M
PC1072
22U_0603_6.3V6M
PC1069
22U_0603_6.3V6M
PC1074
22U_0603_6.3V6M
PC1070
22U_0603_6.3V6M
PC1061
22U_0603_6.3V6M
PC1071
22U_0603_6.3V6M
PC1066
22U_0603_6.3V6M
PC1073
22U_0603_6.3V6M
PC1068
22U_0603_6.3V6M
PC1075
22U_0603_6.3V6M
PC1064
22U_0603_6.3V6M
PC1065
22U_0603_6.3V6M
PC1076
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
22U_0603_6.3V6M
PC1078
22U_0603_6.3V6M
PC1077
22U_0603_6.3V6M
PC1079
22U_0603_6.3V6M
PC1001
22U_0603_6.3V6M
PC1002
22U_0603_6.3V6M
PC1003
22U_0603_6.3V6M
PC1004
22U_0603_6.3V6M
PC1005
22U_0603_6.3V6M
PC1006
22U_0603_6.3V6M
PC1007
22U_0603_6.3V6M
PC1008
22U_0603_6.3V6M
PC1009
22U_0603_6.3V6M
PC1010
22U_0603_6.3V6M
PC1011
22U_0603_6.3V6M
PC1012
22U_0603_6.3V6M
PC1013
22U_0603_6.3V6M
D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Re v
Date: Sheet o f
Title
Size Document Number Re v
Date: Sheet o f
Title
Size Document Number Re v
Date: Sheet o f
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-F391P
LA-F391P
LA-F391P
E
58 65Tuesday, September 19, 2017
58 65Tuesday, September 19, 2017
58 65Tuesday, September 19, 2017
12
PC1153
1U_0201_6.3V6M
12
PC1147
1U_0201_6.3V6M
12
PC1148
1U_0201_6.3V6M
12
PC1149
1U_0201_6.3V6M
12
PC1150
1U_0201_6.3V6M
12
PC1151
1U_0201_6.3V6M
12
PC1152
1U_0201_6.3V6M
12
PC1198
RF@
100P_0402_50V 8J
12
PC1199
RF@
100P_0402_50V 8J
PC1057
22U_0603_6.3V6M
PC1058
22U_0603_6.3V6M
PC1059
22U_0603_6.3V6M
PC1060
22U_0603_6.3V6M
PC1139
22U_0603_6.3V6M
PC1140
22U_0603_6.3V6M
PC1141
22U_0603_6.3V6M
PC1142
22U_0603_6.3V6M
PC1143
22U_0603_6.3V6M
PC1144
22U_0603_6.3V6M
PC1145
22U_0603_6.3V6M
PC1146
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
+VCC_SA
2
+
2
+
PC1181
@
22U_0603_6.3V6M
PC1180
@
22U_0603_6.3V6M
@
PC1177
22U_0603_6.3V6M
PC1179
@
22U_0603_6.3V6M
PC1176
@
22U_0603_6.3V6M
PC1178
@
22U_0603_6.3V6M
@
PC1175
22U_0603_6.3V6M
VCC_GT Place on CPU (U22)
22U_0603 * 26 pcs +1U_0201*12 pcs
+220u_D7*2 pcs
1
330U_D2_2.5VM_R9M
PC1128
1
330U_D2_2.5VM_R9M
PC1063
12
12
12
12
12
12
12
12
PC1040
1U_0201_6.3V6M
12
PC1041
1U_0201_6.3V6M
12
PC1042
1U_0201_6.3V6M
12
PC1043
1U_0201_6.3V6M
12
PC1044
1U_0201_6.3V6M
12
PC1045
1U_0201_6.3V6M
12
PC1046
1U_0201_6.3V6M
12
PC1047
1U_0201_6.3V6M
12
PC1048
1U_0201_6.3V6M
12
PC1049
1U_0201_6.3V6M
12
PC1055
1U_0201_6.3V6M
12
PC1056
1U_0201_6.3V6M
12
PC1328
1U_0201_6.3V6M
12
PC1329
1U_0201_6.3V6M
PC1133
22U_0603_6.3V6M
PC1137
22U_0603_6.3V6M
PC1129
22U_0603_6.3V6M
PC1132
22U_0603_6.3V6M
PC1136
22U_0603_6.3V6M
PC1134
22U_0603_6.3V6M
12
12
12
12
12
12
PC1014
22U_0603_6.3V6M
PC1015
22U_0603_6.3V6M
PC1016
22U_0603_6.3V6M
PC1017
22U_0603_6.3V6M
PC1018
22U_0603_6.3V6M
PC1019
22U_0603_6.3V6M
PC1020
22U_0603_6.3V6M
PC1021
22U_0603_6.3V6M
PC1022
22U_0603_6.3V6M
PC1023
22U_0603_6.3V6M
PC1024
22U_0603_6.3V6M
PC1025
22U_0603_6.3V6M
PC1026
22U_0603_6.3V6M
12
12
12
12
12
12
12
12
12
12
12
12
12
D
E
0.1
0.1
0.1
Vinafix.com
A
+SDC_IN
1 1
PC926
DCIN_ISL9538
VDD_ISL9538
ACIN_ISL9538
OTGEN/CMIN
ACOK_ISL9538
PC938
10P_0402_50V8J
1 2
PR934
499_040 2_1%
PC944
0.01UF_04 02_25V7K
1U 25V K X5R 0402
ADP_ISL9538
17
18
19
20
21
22
23
24
PR933
100K_0402_1%
1 2
PR951
0_0402_5%@
1 2
COMP_ISL9538
12
PC943
@
12
PD901
+PWR_SRC
DIO 30MA 30V 0.5UA 0.4V SOD323-2
+VBUS_DC_SS
2 2
+DC_IN_SS
DIO 30MA 30V 0.5UA 0.4V SOD323-2
ACAV_IN1
AC_DIS<35>
12
3 3
PD903
2 1
RB520SM-30T2R_EMD2-2
PD904
PC931
1U_0603_25V6
1 2
1U_0402_6.3V6K
PQ909
13
D
2
154K_0402_1%
G
S
L2N7002WT1G 1N SC-70-3
PR927
1M_0402_1%
12
12
PC933
PR925
PR916
1_0805_5%~D
1 2
12
0.1U_0402_25V6
PR918
100K_0402_1%
1 2
PBAT_CHARGER_SMBDAT<35,50>
12
PBAT_CHARGER_SMBCLK<35,50>
PBAT_PRES#<35,50>
+SDC_IN
12
12
12
PC955
PR960 0_0402_5%@
1 2
PROCHOT#<12,35,56>
PROCHOT#_ISL9538<60>
PR931
100K_0402_1%
1 2
PR944
442K_0402_1%
ACIN_ISL9538
PR945
100K_0402_5%
@
0_0402_5%
1 2
1 2
1 2
1 2
PR928 0_0402_5%@
1 2
@
100K_0402_1%
1 2
PR919
PR920 0_0402_5%@
PR922 0_0402_5%@
PR926 0_0402_5%@
PR930
PR943
1 2
0_0603_5%
PROCHOT#_ISL9538
+3.3V_ALW
CMOUT<60>
PR901
0.01_1206_1%
1
2
12
PR909
2_0603_1%
4.7U_0402_6.3V6M
CSIP_ISL9538 CSIN_ISL9538
1 2
12
CSIP_ISL9538
15
16
ADP
CSIP
DCIN
VDD
ACIN
OTGEN/CMIN
SDA
SCL
PROCHOT#
ACOK
BATGONE
OTGPG/CMOUT26PROG
25
12
12
PR947
0_0402_ 5%
@
560P_040 2_50V7K
I_BATT
I_BATT <35>
For PSYS Setting
4 4
PR948 @U42
11.8K +-1% 0402
PR948 @U22
Close to EC ADP_I pin
12.7K_0402_1%
PC925
CSIN_ISL953 8
14
CSIN
27
12
PR932
PR935 0_04 02_5%
@
I_ADP <35>
13
28
105K_040 2_1%
12
B
+PWR_SRC_AC
4
12
3
PD906
DIO SMF4L22A SOD123FL-2
12
PR910
2_0603_1%
PC930
0.22U_0603_25V7K
1 2
PR914
3.3_0603_1%
1 2
BOOT1_ISL95 38
UG1_ISL95 38
11
10
12
BOOT1
PHASE1
UGATE1
ASGATE
CMOP
PSYS30VBAT
AMON/BMON
29
31
VBAT1_ISL9538
12
PC947
0.1U_040 2_25V6
I_ADP
0.1U_0402_25V6
PL901
EMC@
1UH +-20% 6.6A 5X5X3 MOLDING
PJP901
1 2
PAD-OPEN 4x4m
@
12
PC927
1U 25V K X5R 0402
LG1_ISL9 538
LX1_ISL95 38
1 2
PU901
9
33
ISL9538HRTZ-TS2778 TQFN 32P CHARGER
PAD
VDDP_ISL9538
8
LGATE1
VDDP
LG2_ISL9538
7
LGATE2
LX2_ISL9538
6
PHASE2
UG2_ISL9538
5
UGATE2
BOOT2_ISL9538
4
BOOT2
3
VSYS
CSOP_ISL9538
2
CSOP
CSON_ISL9538
1
CSON
BGATE
32
BGATE_ISL9538
12
12
PR936
0_0402_ 5%
PR948
@
@
12.7K_04 02_1%
I_SYS <35,56>
PC950
@
1 2
12
PR915
4.7_0603_5%
100_0402_5%
VDD_ISL9538
PC932
1U_0402_6.3V6K
PC934
0.22U_0603_25V7K
12
PR940
12
PC902
0.1U_040 2_25V6
@EMC@
12
PR921
4.7_0603_5%
12
PR929 0_0402_5%@
1 2
1U_0402_25V6M
+PBATT
12
12
12
PC903
PC911
RF@
100P_040 2_50V8J
10U_080 5_25VAK
12
12
PC904
PC951
10U_080 5_25VAK
UG1_ISL9538 LG1_ISL9538
LX1_ISL9538
PC906
PC905
10U_080 5_25VAK
10U_080 5_25VAK
12
12
PC952
10U_080 5_25VAK
1
2
3
4
PQ905
FDPC5030SG 2N POWER CLIP 56-8
+PWR_SRC
1 2
PC939 0.1U_0402_25V6@
PC942
@
1U 25V K X5R 0402
1 2
PR937
1_0603_1%
1 2
1 2
PR938
1_0603_1%
1 2
PC946
0.22U_0402_25V6K
1 2
PC945
+CHARGER_SRC
12
PC909
@
10U_080 5_25VAK
15U_B2_2 5VM_R100M
9
G1
G2
D1
D2/S1
S1/D2
D2/S1
D1
D1
D2/S1
S2
10
AC1_DISC#<26,60>
HW_ACAVIN_NB<35,50,60>
C
1
+
2
8
PL902
7
2.2UH_PCMB103T-2R2MS_13A_20%
1 2
6
5
LX1_ISL9538
12
PR923
4.7_120 6_5%
EMC@
SNUB_CHG1
12
PC940
680P_060 3_50V7K
EMC@
LG2_ISL9538 UG2_ISL9538
LX2_ISL9538
12
PR924
4.7_120 6_5%
EMC@
SNUB_CHG2
12
PC941
680P_060 3_50V7K
EMC@
PR939
0_0402_5%@
3
1 2
PR941
0_0402_5%@
1 2
2
9
8
G2
D1
7
D2/S1
6
D2/S1
5
D2/S1
S2
10
PD905
BAT54CW-7-F SOT-323
1
12
PR961
@
1
G1
2
S1/D2
3
D1
4
D1
PQ904
FDPC5030SG 2N POWER CLIP 56-8
PR950
@
0_0402_5%
1 2
ACAV_IN1
1 2
@
0_0402_5%
100K_040 2_1%
LX2_ISL9538
PC949
0.1U_0402_10V7K
1 2
PR942
+PWR_SRC
PR917
0.005_1206_1%
1
2
LM393_P
5
1
B
2
A
3
P
G
12
PC913
10U_080 5_25VAK
12
PC928
100P_040 2_50V6
RF@
12
12
PC915
PC914
10U_080 5_25VAK
10U_080 5_25VAK
12
PC929
PC956
2200P_04 02_50V7K
@EMC@
@EMC@
+VCHGR
4
3
PC935
PU903
MC74VHC1G08DFT2G SC70 5P
PR946
@
0_0402_5%
4
1 2
Y
12
PC916
10U_080 5_25VAK
12
PC957
1000P_04 02_50V7K
@EMC@
12
PC936
10U_080 5_25VAK
1 2
D
1
+
PC921
2
15U_B2_2 5VM_R100M
12
PC958
1000P_04 02_50V7K
@EMC@
12
10U_080 5_25VAK
ACAV_IN<35>
PR953
100K_0402_1%
12
12
PC959
1U_0402 _25V6K
1U_0402 _25V6K
@EMC@
PQ906
EMZB08P03V 1P EDFN3X3-8
1
2
3 5
4
PC937
1 2
@
4700P_04 02_25V7K
For IT8010 voltage
leakage issue
12
PC1193
RF@
12
12
PC1194
RF@
100P_040 2_50V8J
12
PC1195
PC1196
RF@
RF@
100P_040 2_50V8J
100P_040 2_50V8J
100P_040 2_50V8J
+PBATT
BGATE_ISL9538
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS, INC.
C
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PWR_charger_ISL9538
PWR_charger_ISL9538
PWR_charger_ISL9538
LA-F391P
LA-F391P
LA-F391P
D
0.1
0.1
0.1
65Tuesday, September 19, 2017
65Tuesday, September 19, 2017
65Tuesday, September 19, 2017
59
59
59
Vinafix.com
5
DCIN_AC_D ete ctor
PC1201
@
0.01UF 25V +-10% X7R 0402
1 2
+3.3V_VDD_DCIN
+DC_IN
D D
C C
+3.3V_VDD_DCIN
+3.3V_VDD_PIC
12
12
PR1201
PR1208
240K_0402_1%
102K_0402_1%
(>17 .6V)
12
PR1219
23.2K_0402_1%
12
12
PC1205
PR1217
84.5K_0402_1%
100P_0402_50V8J~D
+TBTA_VBUS
+TBTA_Vbus_1 +3.3V_VDD_PIC
B B
12
PR1239
150K_0402_1%
@
12
12
PC1211
@
PR1246
100P_0402_50V8J
100K_0402_1%
@
3
2
BAT54CW-7-F SOT-323
12
PC1206
220P_0402_50V8J~D
12
PC1215
100P_0402_50V8J
@EMC@
DIO 30MA 30V 0.5UA 0.4V SOD323-2
12
PR1237
@
100K_0402_1%
12
PR1247
100K_0402_1%
@
PC1212
@
PD1801
1 2
100P_0402_50V8J
1
1.8M_0402_1%
LM393_P
8
3
P
+
2
-
G
4
EMI Par t
EMC@
5A_Z80_20M_0805_2P
1 2
1 2
5A_Z80_20M_0805_2P
EMC@
12
PC1208
EMC@
1000P_0402_50V7K
S3 OVP
PD1205
@
0_0402_5%
1 2
5
6
12
LM393_P
PR1203
1 2
PU1201A
LM393DGKR_VSSOP8
1
O
PL1201
PL1202
PR1238
LM393_P
8
P
+
O
-
G
4
+3.3V_VDD_DCIN
12
12
PC1207
1200P_0402_50V7K
12
12
PC1209
0.1U_0402_25V6
@EMC@
PU1201B
LM393DGKR_VSSOP8
7
PC1213
@
PR1206
1K_0402_1%
HW_ACAVIN_NB
PR1227
100K_0402_5%
12
12
1200P_0402_50V7K
12
PC1216
100P_0402_50V8J
EMC@
PR1240
100K_0402_1%
PR1243
@
0_0402_5%
1 2
HW_ACAVIN_NB<35,50,59,60>
+TBTA_Vbus_1
OVP set t i ng: 5. 5V
LPS_PROTECT#
PT1
@
PAD~D
EN_PD_HV_1 <26,60>
(From EC)
PR1248
12
PR1249
10K_0402_5%
@
0_0402_5%
1 2
PR1250
@
0_0402_5%
1 2
D
13
2
G
S
PQ1212
L2N7002WT1G_SC70-3
+TBTA_Vbus_1
4
12
+3.3V_VDD_PIC
5
PC1214
@
0.01UF_0402_25V7K
1 2
34
+AC_IN
PJP1202
@
112
JUMP_43X118
S3
PQ1206
EMZB08P03V 1P EDFN3X3-8
4
12
PR1236
61
100K_0402_5%
2
PQ1209B
DMN65D8LDW-7_SOT363-6
EN_PD_HV_1<26,60>
2
1
2
35
12
1 2
PC1210
1500P_0402_50V7K
PR1229
49.9K_0402_1%
PQ1209A
DMN65D8LDW-7_SOT363-6
+3.3V_VDD_PIC
PR1228
499K_0402_1%
PR1251
300K_0402_5%
PR1252
100K_0402_5%
12
PR1253
100K_0402_5%
EN_PD_HV_1#
34
5
(From TI GPIO1)
DCIN1_EN<35>
12
PR1255
@
150K_0402_1%
3
S4 S5
PQ1213
EMZB08P03V 1P EDFN3X3-8
1
2
12
S
PQ1215
G
2
12
D
1 3
AO3409 P-CHANNEL SOT-23
61
2
PQ1214A
DMN65D8LDW-7_SOT363-6
PQ1214B
DMN65D8LDW-7_SOT363-6
PR1210
1M_0402_5%
12
PR1221
+3.3V_ALW
PR1211 0_0402_5%@
1 2
@
12
PR1224
100K_0402_5%
AC1_DISC#<26,59>
EN_PD_HV_1<26,60>
@
0_0402_5%
1 2
12
12
PC1202
PR1205
499K_0402_1%
0.47U 25V K X7R 0603
12
PR1216
@
0_0402_5%
PC1204
0.1U_0402_10V7K
PR1254
@
0_0402_5%
1 2
1 2
1
2
PR1215
0_0402_5%
PQ1205
L2N7002WT1G_SC70-3
D
S
13
G
2
12
PR1225
0_0402_5%
@
EN_PD_HV_1<26,60>
3 5
4
PR1212
49.9K_0402_1%
2
12
PR1262
100K_0402_5%
+3.3V_VDD_PIC
12
PU1200
5
MC74VHC1G08DFT2G SC70 5P
P
B
4
O
G
A
3
PR1226
1 2
100K_0402_5%
+3.3V_VDD_PIC
PR1260
@
0_0402_5%
1 2
1 2
PR1244
@
0_0402_5%
12
61
PQ1201A
DMN65D8LDW-7_SOT363-6
100K_0402_5%
5
PR1259
G
+3.3V_ALW
1 2
34
S
D
HW_ACAVIN_NB<35,50,59,60>
+VBUS_DC_SS
VBUS2_ECOK<35,50>
VBUS1_ECOK<35,60>
PR1234
100K_0402_5%
2
G
PQ1208B
PR1261
@
0_0402_5%
1 2
S TR DMN65D8LDW-7 2N SOT363-6
VBUS1_ECOK<35,60>
+3.3V_ALW
1 2
61
D
S
PR1241
@
0_0402_5%
1 2
VBUS1_ECOK
PR1242
@
0_0402_5%
1 2
1 2
PR1257
@
0_0402_5%
PQ1208A
100K_0402_5%
S TR DMN65D8LDW-7 2N SOT363-6
PR1232
5
2
12
G
PD1202
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
3
PQ1202
EMZB08P03V 1P EDFN3X3-8
4
12
PR1213
49.9K_0402_1%
34
PR1220
5
1 2
0_0402_5%
@
PR1222
100K_0402_5%
+3.3V_ALW +3.3V_ALW
PR1235
@
100K_0402_5%
1 2
+3.3V_ALW
1 2
61
D
2
G
PQ1211A
S
+3.3V_ALW
S TR DMN65D8LDW-7 2N SOT363-6
1 2
2
G
34
D
PQ1207B
S TR DMN65D8LDW-7 2N SOT363-6
S
1 2
PR1258
@
0_0402_5%
1
1
2
35
12
12
PR1207
499K_0402_1%
PQ1201B
DMN65D8LDW-7_SOT363-6
PR1233
@
100K_0402_5%
AC_DISC# <35,50,60>
34
D
5
G
S
PQ1211B
PR1230
100K_0402_5%
S TR DMN65D8LDW-7 2N SOT363-6
1 2
61
D
PQ1207A
S TR DMN65D8LDW-7 2N SOT363-6
S
PC1203
1500P_0402_50V7K
+3.3V_ALW
12
@
AO3409 P-CHANNEL SOT-23
1 2
61
D
S
PC1217
1500P_0402_50V7K
S
PQ1203
D
1 3
PR1231
100K_0402_5%
@
0_0402_5%
1 2
PQ1210A
S TR DMN65D8LDW-7 2N SOT363-6
2
DMN65D8LDW-7_SOT363-6
G
PQ1204B
PR1245
2
G
12
PR1202
300K_0402_5%
12
PR1209
100K_0402_5%
34
5
1 2
PR1218
@
0_0402_5%
1
+SDC_IN
+3.3V_VDD_PIC
12
PR1214
100K_0402_5%
61
PR1223
1 2
2
0_0402_5%
@
AC_DISC# <35,50,60>
PQ1204A
DMN65D8LDW-7_SOT363-6
CMOUT <59>
34
D
5
G
S
PQ1210B
S TR DMN65D8LDW-7 2N SOT363-6
PROCHOT#_ISL9538 <59>
D
13
2
G
S
PQ1216
L2N7002WT1G_SC70-3
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHE ET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROP ERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL
AND TRADE SECRET INFORMATION. THIS S HEET M AY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT A S AUTHORIZED BY COM PAL ELECT RONICS, INC. NEITHER THIS SHEET NOR T HE INFORM ATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCL OSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COM PAL E LECTRONICS, INC.
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Breckenridge_TypeC_PD
Breckenridge_TypeC_PD
Breckenridge_TypeC_PD
Document Number R e v
Document Number R e v
Document Number R e v
LA-F391P
LA-F391P
LA-F391P
1
60 65Tuesday, September 19, 2017
60 65Tuesday, September 19, 2017
60 65Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
Version Change List ( P. I. R.
4
3
2
1
List )
Item Issue
D D
C C
B B
53
54
1
2
3
4
5
6
Add RF team portion
56
57
Change DrMOS58
51
57
Add EMI portion
59
53
54
Add RF team portion
56
57
56
57
Acoustic solution
59
Change Charger
Dual-MOS
7
ALL Change MLCC PN
8
Add Charger portion
9
59
Date
Request
Owner
2017
04/06
06/08
2017
06/09
2017
06/13
2017
06/13
2017
06/13
2017
07/28
2017
07/31
2017
08/03
Description
RF pop PC100,PC103,PC115,PC116,PC131,PC132,PC151,PC152,
Compal
RF request & modify Components
Compal Change DrMOS from TI to Fairchild DrMOS change from CSD97396 to FDMF30352017
Compal
Compal
Compal
Compal59
Compal60 EMI portion
EMI request & modify Components
RF request & modify Components
For acoustic solution
CPU input MLCC change to 0603 low noise MLCC
Change Dual-MOS from TI to AOS
EMI request & modify Components
Compal Change MLCC P/N L-end to 0-end 0-end P/N for all MLCC cap
Compal
Intersil FAE request PSYS Setting
PC153,PC231,PC301,PC303,PC409,PC418,PC695,PC696,
PC903,PC928,PC1191,PC1192,PC1193,PC1194,PC1195,
PC1196
1. Depop PC133, PC134, PC135, PC136, PC137, PC138,PC139,PC140, PC689,
PC690, PC691, PC692, PC956, PC957,PC958, PC959
2. Pop PL901.
RF pop PC1198,PC1199
1. Remove PC917, PC918, PC919, PC920 , add PC921 B2 POS CAP
2. CPU input MLCC size change from 0805 to 0603 low noise MLCC
PC608, PC612, PC656, PC657, PC658, PC664, PC665, PC672, PC673, PC674,
PC675, PC682, PC683, PC684
3. Pop PC607
Dual-MOS change from CSD87351 to AOE6936
Tpye-C PD Bead EOL ,so change BR_MLK12_14_15 PL1201/PL1202 Bead
to 80 ohm bead,
Change SM01000P200 to SM01000U400
For ISL9538 PSYS Setting PR948 change value
1.UMA U42 change from
SD034127280(12.7kohm) to SD034118280 (11.8kohm)
2.UMA U22 keep SD034127280(12.7kohm)
Solution
Description
Rev.Page# Title
X00
X01
X01
X01
X01
X01
X02
X02
X02
5961Change Charger
10
11
12
ALL
59
portion
0 ohm short pad
Change Charger
portion
2017
08/11
2017
08/11
2017
08/11
Compal
Compal
Compal
Change current sense for component derating
by Intersil FAE confirm
0hom change to 0 ohm short pad
Power request
PR937,PR938,PR909,PR910,PR915 change 0402 to 0603
SD00001QK80
For 0ohm no short pad:
U42 DSC:Keep PR943,PR421,PR671,PR692 pop SD028000080
Add PD906 SC40000EL00 before PL901 Isum choke
(SC40000EL00- S ZEN DIO SMF4L22A SOD123FL-2)
X02
X02
X02
13
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
LA-F391P
LA-F391P
LA-F391P
1
61 65Tuesday, September 19, 2017
61 65Tuesday, September 19, 2017
61 65Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
Version Change List ( P. I. R.
4
3
2
1
List )
Item Issue
D D
13
14
IMVP8 CPU
56
Controller
Portion
Change Charger
59
portion
Date
2017
08/11
2017
08/11
Request
Owner
Compal
Compal
Description
Intersil FAE request
Solution
Description
Tune value for ISL95857A R,C match
U42
1. Change PC624 SE068103K80 to SE075153K80(0.015uF)
2. Change the PR629 from 86.6kOhm to 88.7kOhm. ( IMON of GT )
3. Change the PC642 from 0.033uF to 0.022uF. ( RC Match of GT )
U22
1. Change PC624 SE068103K80 to SE076223K80(0.022uF)
2. Change the PR638 from 383 Ohm to 365 Ohm
PD901,PD904 change from SCS0340L010 to SCS00009P00, for common partBuyer request
Rev.Page# Title
X02
X02
15
C C
16
17
18
19
B B
20
21
22
23
A A
24
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
25
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
LA-F391P
LA-F391P
LA-F391P
1
62 65Tuesday, September 19, 2017
62 65Tuesday, September 19, 2017
62 65Tuesday, September 19, 2017
0.2
0.2
0.2
Vinafix.com
5
Version Change List ( P. I. R.
4
3
2
1
List )
Item
D D
1 40 EE 0.1(X00)For align with spindle HDD. Add UZ37 circuit for 2280 SSD imdenpenden loadswitch
3 2017/03/14 EE 0.1(X00)KBL-R U42 X'tal
4 34 Prevent POA_WAKE# ESD
5 All
C C
6 36
7 All
B B
A A
11 Add RC417~RC422,CC334,CC335, YC3 for U42 crystal
TitlePage# Rev.
M2 2280
Socke t
All
CPU (6/14)
USH & TPM
All
MEC5105
Support
All
Date
2017/03/9
2017/03/9 X9 request UC1 CPU change from U22 to U42.2 All EE 0.1(X00)
2017/03/24 EE Add RTC reset circuit 1. RTCRST_ON_GPIO122 change to RTCRST_ON...
Request Owner
Issue
Description
Solution
Description
--> add CN50~51, UZ37, PJP30_1*2(and no stuff all)
EE Add RZ364 100 ohm to POA_WAKE#2017/03/17 0.1(X00)
EE Remove IO expander2017/03/17 1-1.Delete expander IO UE2 relating circuit(RE524,@RE525 change to 0 ohm)
EE Remove Reset Threshold circuit2017/03/24 1. Delete UE7 relating circuit. keep RE536 only
remove UE2, CE1, CE2, RE13~18, RE6, CE500, CE504, CE505
4/13 add UMA RE524/525(2.2kohm)--> B6/F7
4/17 B6/F7 change netname to GPU_SMDAT/CLK
1-2. GPIO change (RE374 reserve)
PCH_RSMRST#_GPIO204 -> USH_PWR_STATE# (delete RE363)
PORT80_DET# -> DCIN1_EN (delete RE512,RE513,RZ131)
SHD_IO3 -> VBUS1_ECOK (delete RE366~RE373, RE376,RE377,RE98,UE9)
SHD_IO1 -> SATA_LED_EN
ENVDD_PCH -> DCIN2_EN
SIO_RCIN#_EC -> VBUS2_ECOK
1-3 For DSC (keep RE524, RE525)change name GPU_SMDAT/GPU_SMCLK
SIO_EXT_SCI#_EC -> GPU_PWR_LEVEL (delete RE341)
EXPANDER_GPU_SMCLK -> DGPU_PWROK
RTCRST_ON_GPIO141(B6) -> GPU_SMDAT
X(F7) -> GPU_SMCLK
remove UE7, QE13, RE34, RE348, RE536, RE537, RE530
CE5, CE6, CE503
add RE536 on EC side
2-1. +RTC_CELL_PCH circuit (Dell request)
Delete RE514,RE515...
Add QE14~QE17...
Add RE540~RE546...
Add CE63...
Change RC56.2 net name to +RTC_CELL_PCH...
Change UC1.AK19, UC1.BB14 net name to +RTC_CELL_PCH...
2- 2. ba se d on AR D 1 .3
3. +3.3V_ALW_DSW enable circuit (Dell request)
Delete RE524...
Add RC431~RC433...
Add UC13,UC14...
Change UE1.M7 net name to VCCDSW_EN_GPIO...
4. GPIO change
USH_SMBCLK -> USH_EXPANDER_SMBCLK
USH_SMBDAT -> USH_EXPANDER_SMBDAT
Delete RTCRST_ON_GPIO141
PRIM_PWRGD_GPIO024 -> RESET_IN#
5. UC13 chante to QC6, UC14 change to QC7
4/17 RTC power Gate circuit rev.2
Delete RE540, RE542, RE544, RE545, QE14, QE16
Change RE543 to 1M ohm and RE546 to 10K ohm
Add DE2, CE65,
Reserve CE66 for VCCDSW_EN
R TC c ircuit
RE551
+RT C _CELL_PCH.
0.1(X00)
0.1(X00)
0.1(X00)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (1/8)
EE P.I.R (1/8)
EE P.I.R (1/8)
LA-F391P
LA-F391P
LA-F391P
63 70Tuesday, September 19, 2017
63 70Tuesday, September 19, 2017
63 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
Version Change List ( P. I. R. List )
3
2
1
Item
D D
8 All EE 0.1(X00)
C C
11 37 0.1(X00)
B B
13 16
14 10
15 9
16 8
17 31,11
18 28
TitlePage# Rev.
All
CPU (4/14)
USH & TPM
USH & TPM
CPU (8/14)
CPU (11/14)
CPU (5/14)
CPU (4/14)
CPU (3/14)
Card Reader
RTS5242 2017/03/29 EMI EMI request 1. RR5~RR10 change to 0ohm
CPU (6/14)
USB 3.0 CONN
TYPE C
Date
Owner
2017/03/14 co-lay DS3/non-DS3 1. DS3 / non-DS3 co-lay
2017/03/27 For antenna request9 09 EE 1. Add RC434, RC435 0ohm for JUART1 power option
Prevent contactless_det# backdrive2017/03/27
2017/03/15 EE TPM650 include
2017/03/15 EE12 13 Follow CRB
2017/03/15 EE Follow MOW08 UC1.K52/AK52 Must be NOT connected 0.1(X 00)
2017/03/28 EE X9 Port MAP check 1. USB3.0 port1 with port6 swap
2017/03/29 EE For Layout power trace add +UART1_R power netname on JUART1 0.1(X00)
2017/03/29 ME Connector check JSPI1 change from ENTERY_SP01001FW00 to ACES_SP01001CB10 0.1(X00)
2017/03/29 ESD ESD request 1. Change DT7, DT8, DT11, DT12 to DT39
Request
Issue
Description
Add DC2, (DC1 add NDS3 @)
Add RC501, RC503, RC505 for DS3
Add RC502, RC504, RC506 for Non-DS3
Use the original 0ohm, RC215 instead of RC504, RE536 instead of RC503
3/14
1. based on EDS that add RC503 / RC504 on SUSACK # / ME_SUS_PWR_ACK for DS3
2. UZ3 enable pin change netname to PCH_PRIM_EN
3. RE349 + DS3 @
4. UZ34 input in form SIO_SLP_SUS # to PCH_PRIM_EN
3/15
1. For align KW that change as below "Part Reference"
A RC501 -> RC439
B. RC502 -> RC440
C. RC503 -> RC443
D RC504 -> RC444
E. RC505 -> RC441
F RC506 -> RC442
3/27
Parallel 0ohm in DC2, reserved to avoid NDS3 @, EC too late to load code
4/17 RTC Power Gate Circuit option
RC445 change to connect to VCCDSW_EN and pop
4/17 JUART whether pin swap, Align with SB.
--> Pin swap align SB
--> EVT phase pop JUART, DVT phase remove
4/20
2. Remove RC435
1. Add DZ8 to prevent contactless_det# backdriveEE3810 0.1(X00)
1. TPM
a. Delete RZ113, RZ111, QZ9
b. Add RZ365 and connect to +UZ12_TPM
Add RZ366 and connect to +3.3V_M_TPM
UC1.F65 & G65 to GND
add RC436 to GND before UC1.F65 & G65
2. USB2.0 port1 with port9 swap
2. RC417~RC420 change from 0ohm to 33ohm
2. Change DT15, DT16, DT19, DT20 to DT40
Solution
Description
0.1(X00)
0.1(X00)
0.1(X00)
0.1(X00)
0.1(X00)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (2/8)
EE P.I.R (2/8)
EE P.I.R (2/8)
LA-F391P
LA-F391P
LA-F391P
64 70Tuesday, September 19, 2017
64 70Tuesday, September 19, 2017
64 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
Version Change List ( P. I. R. List )
3
2
1
Item
D D
19 16
20 All
21 37
22 35
23 8
24 26
25 36
C C
26 All
27 All
B B
TitlePage# Rev.
CPU (11/14)
All
USH & TPM
EC MEC5105
CPU (3/14)
[Type C]PD
Controller TI
MEC5105
Support
All
All
Date
Owner
2017/03/29 EE For BRMLK12 layout request Let AK70,BB57,BB66,AU58,AU63 flooting 0.1(X00)
2017/03/31 EE Follow ARD1.3 remove WIGIG
2017/03/31 EE TPM NPCT65X and NPCT75X schematic colay UZ12 relating circuit and change UZ12 to SA0000AQ200 0.1(X00)
2017/04/05 EE RTCRST_ON glitch Reserve CE64 0.1(X00)
2017/04/05 EE Winbond 16MB SPI ROM EOL (change to J-die) Change UC5, UC6 to SA00005VV20 0.1(X00)
2017/04/05 EE Change PD to PD3.0 Change UT5 to SA0000AP500 0.1(X00)
2017/04/05 EE Board ID define change change RE79 to 240K for X00 0.1(X00)
2017/04/05 EE EC GPIO check
2017/04/06 EE EC GPIO check
Request
Issue
Description
1-1.change Source 1:3 demultiplexer(PS8348B) to 1:2 demultiplexer(PS8338B)
1-2,remove RV71, RC74, RV77, CV80
2-1. (DP)JNGFF1 remove CV145~150, CV152, CV153, CV156, CV157
2-2. (PCIE)JNGFF1 remove CZ14, CZ15
UC1 remove RC375
1. rename form AUD_NB_MUTE# to NB_MUTE# for EC team request
2. rename form SYS_LED_MASK# to LED_MASK# for EC team request
3. change net name form THERMATRIP1# to THERMTRIP1# for EC team request
4. swap WWAN_RADIO_DIS# from UE1.M2 to UE1.F12
5. swap LCD_TST from UE1.D1 to UE1.M2
1. rename form FAN1_TACH to TACH_FAN1 for EC team request
2. DSC_swap DGPU_PWR_EN to GPIO100 for save level shift at BR MLK project
3-1. DSC_swap GPU_PWR_LEVEL to GPIO126 for save level shift at BR MLK projcet
3-2. DSC_ remove RE5 of GPIO126,
3-3. UMA_remove RE341 of SIO_EXT_SCI#
4. SYS_PWROK reserved 0ohm add netname to RESET_OUT
5. rename form ME_FW_EC to ME_FWP for EC team request
rename from ME_FWP to ME_FWP_PCH
6. rename from THERMATRIP2# to THERMTRIP2# for EC team request
7. rename from HW_GPS_DISABLE# to GPS_DISABLE# for EC team request
8-1. rename from VGA_ID to VGA_IDENTIFY for EC team request
8-2. swap to GPIO035 form GPIO017 for ECteam suggestion BEEP need
change to PWM function
8-3. Swap BEEP pin to GPIO035 form GPIO017 EC team request.
9. rename from H_PROCHOT# to PROCHOT# for EC team request
10. rename from USB_PWR_SHR_VBUS_EN to USB_POWERSHARE_VBUS_EN for
EC team request
Solution
Description
0.1(X00)
0.1(X00)
0.1(X00)
28 47
29 8
30 24
31 36
A A
Power
control
CPU (3/14)
DP to VGA &
VGA Conn
MEC5105
Support
2017/04/07 EE +5V_RUN discharge circuit for S3
2017/04/07 ME JSPI1 footprint pin1 Reversal 180 of
2017/04/07 EE When the system can not read the VGA EDID,
2017/04/07 EE To increase power current rail for
no power issue
ENTERY to ACES
the maximum resolution will be pressed
at 1024x768
each debug card
1. Add but not stuff QZ4 and RZ370
2. Add zener diode DE1 (no stuff) for + 5V_RUN discharge
3. RZ370 into 0603 packaging, add net name
0.1(X00)
Symbol reverses 180 degrees 0.1(X00)
reserve RV620 PU to +3.3V_RUN
** Pop RV620
RE71 changed to SD034100A80, that change 49.9 to 10ohm
current limiting resistor to smaller.
0.1(X00)
0.1(X00)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (4/8)
EE P.I.R (4/8)
EE P.I.R (4/8)
LA-F391P
LA-F391P
LA-F391P
65 70Tuesday, September 19, 2017
65 70Tuesday, September 19, 2017
65 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
Version Change List ( P. I. R. List )
3
2
1
TitlePage#
D D
32 All
All33 EC GPIO checkEE2017/04/10 0.1(X00)
C C
34 PCH GPIO checkEE2017/04/11 0.1(X00)
All
All35 Following port MAPEE2017/04/11 0.1(X00)
All
All
All
All
Date Issue DescriptionItem
2017/04/07 EE EC GPIO check 1. rename from USB_PWR_SHR_LFT_EN# to USB_POWERSHARE_EN# for
Owner
EC team request
1. 3.3V_TS_EN rename to PCH_3.3_TS_EN
SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option
2. SHD_CLK -> PS_ID and delete RE374
3. CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
4. change net name form PANEL_ID to SYSTEM_ID
5 .SIO_EXT_SMI#_EC -> free and delete RE338
6. SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
7. rename from SATA_LED_EN to MASK_SATA_LED# for EC team request
8. rename form FAN1_PWM_1 to PWM_FAN1 for EC team request
9.GPIO054(PS_ID) swap to GPIO056 for EC team request
10. PCH_ALW_ON keep GPIO231 and assign DCIN2_EN to GPIO107
11. EXPANDER_GPU_SMCLK -> free and delete RE525
12. this pin should be change to reserved,Current EC no use PCH_ALW_ON
to control +3.3V_ALW_PCH, it control by SIO_SLP_SUS# directly
13. rename from SLOT2_CONFIG_1 to NGFF_CONFIG_1 for EC team request
14. rename from ACAV_IN_NB to HW_ACAVIN_NB for EC team request
15. rename from SLOT2_CONFIG_0 to NGFF_CONFIG_0 for EC team request
16. rename from SLOT2_CONFIG_2 to NGFF_CONFIG_2 for EC team request
17. rename from LID_CL_NB# to LID_CL_SIO# for EC team request
1. Follow SB reserve CLKDET# net,for x7~x8 no use
2. Follow SB reserve CLKRUN# net,for no use LPC mode
3. DEL SIO_RCIN# net,for no use LPC mode
4. Follow SB reserve SIO_EXT_SCI#,for no use LPC mode
5. Rename PCH_3.3V_TS_EN from 3.3V_TS_EN
6. Follow SB reserve PCI_CLK_LPC1, for no use LPC mode
7. Follow SB reserve PME#, for no use LPC mode
8. Follow SB reserve SIO_EXT_SMI# net, for no use LPC mode
LOM port to be replaced to port 4
Solution Description
Rev.
0.1(X00)
Request
36 EMI EMI request
B B
37 EE For All of Repeater
38 EE GPIO map change 0.1(X00)2017/04/17 4/17 PCH_3.3V_TS_EN PU +3.3V_RUN change page to QV7.2
A A
All
All
All
All
All
All
2017/04/13
2017/04/17 4/17 PWD pin setting double check for all of redrive(dual, signal, USB3)
change 0ohm short pad to 0ohm of as below.
RC328,RT54~57,RZ56,RN99
4/21
UMA
1. SATA repeater --> add QN6, RN226, RN227
2. PCIE/SATA repeater --> add QN7, RN228,RN229,RN230
DSC
1. PCIE/SATA repeater --> add QN6, RN226, RN227
-->Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN
1. RC443 BOM structure change to @
2. UMA : GPIO126->GPU_PWR_LEVEL
3. Add RTCRST_ON_R net neme for QE17.2
4. Add SIO_SLP_SUS#_R net name and PU RE561
5. RC27.2->NC for CLKRUN#
6. UMA : HDD_DET#->SATAGP0
7. Remove RE360/RE364 .
0.1(X00)
0.1(X00)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (3/8)
EE P.I.R (3/8)
EE P.I.R (3/8)
LA-F391P
LA-F391P
LA-F391P
66 70Tuesday, September 19, 2017
66 70Tuesday, September 19, 2017
66 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
Version Change List ( P. I. R. List )
3
2
1
TitlePage#
D D
39 47
43 JUSH1 add net nameEE 0.1(X00)
C C
45 EE BOM option by “ 650@” o r “ 750@ 0.1(X00)2017/04/24
46 EE JUART1 remove
47 EE Schematic align
48 EE GPIO map change 0.1(X00)GPIO013 net name change to DGPU_PWROK
49 34
B B
50 34
Power control
3640 EC request to reseve ESPI_RESET# for JESPIEE 0.1(X00)
38
3744 TPM change to NPCT650xEE2017/04/21 0.1(X00)
37
9
11
All
MEC5105
Support
All
EC MEC5105
USH & TPM
USH & TPM
USH & TPM
CPU (4/14)
CPU (6/14)
All
Codec ALC3253
Codec ALC3253
Date Issue DescriptionItem
2017/04/19 EE EC request to reseve OR gate for
Owner
WLAN power EN
Reserve DZ9
4/20 RZ38 PD change to WLAN_PWR_EN_UZ2
2017/04/19 Reserve RE560
2017/04/1941 EE OTG supportAll
2017/04/1942 35 EE Dell request to add test point for
EC free pins
2017/04/19
Pop RT74, Depop RC337
4/20 RC337 10K to GND
Add test point T141 for UE1.D1->GPIO051
Add test point T142 for UE1.L11->GPIO054
Add test point T264 for UE1.F13->VBUS3_ECOK
Add test point T143 for UE1.K7->GPIO011
Add test point T144 for UE1.M1->GPIO100
Add test point T262 for UE1.J6->GPIO202
Add test point T147 for UE1.M4->DGPU_PWROK only UMA
1. Add net name at DZ8.1 .
Change UZ12 to SA00008EL80 and related resistors
1. The pop option for VHIO power:
NPCT750: VHIO=+3.3V_RUN
NPCT650: VHIO=+3.3V_ALW_PCH
2. The pop option for SLP_S0# connection:
NPCT750: pop RZ112 (SLP_S0#=GPIO0)
NPCT650: pop RZ363 (SLP_S0#=GPIO2)
3. RZ62 can be removed
2017/04/24
2017/04/24
2017/04/24
remvoe JUART1, RC434
INTRUDER# PU change to +RTC_CELL_PCH
UPD1_ALERT#-->UPD1_SMBINT#
UPD1_SMBUS_ALERT#-->UPD1_SMBINT#_R
EE Follow ARD1.3 change Codec to 3254 Change Codec schematic from ALC3253 to ALC3254 0.1(X00)2017/03/31
EE Swap ESD diode pin for layout2017/04/13 DT39 & DT40 swap pin 0.1(X00)
Solution Description
Rev.
0.1(X00)
0.1(X00)
0.1(X00)
0.1(X00)
0.1(X00)
Request
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (5/8)
EE P.I.R (5/8)
EE P.I.R (5/8)
LA-F391P
LA-F391P
LA-F391P
67 70Tuesday, September 19, 2017
67 70Tuesday, September 19, 2017
67 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
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5
4
Version Change List ( P. I. R. List )
3
2
1
TitlePage#
D D
32 All
All33 EC GPIO checkEE2017/04/10 0.1(X00)
C C
34 PCH GPIO checkEE2017/04/11 0.1(X00)
All
All35 Following port MAPEE2017/04/11 0.1(X00)
All
All
All
All
Date Issue DescriptionItem
2017/04/07 EE EC GPIO check 1. rename from USB_PWR_SHR_LFT_EN# to USB_POWERSHARE_EN# for
Owner
EC team request
1. 3.3V_TS_EN rename to PCH_3.3_TS_EN
SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option
2. SHD_CLK -> PS_ID and delete RE374
3. CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
4. change net name form PANEL_ID to SYSTEM_ID
5 .SIO_EXT_SMI#_EC -> free and delete RE338
6. SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
7. rename from SATA_LED_EN to MASK_SATA_LED# for EC team request
8. rename form FAN1_PWM_1 to PWM_FAN1 for EC team request
9.GPIO054(PS_ID) swap to GPIO056 for EC team request
10. PCH_ALW_ON keep GPIO231 and assign DCIN2_EN to GPIO107
11. EXPANDER_GPU_SMCLK -> free and delete RE525
12. this pin should be change to reserved,Current EC no use PCH_ALW_ON
to control +3.3V_ALW_PCH, it control by SIO_SLP_SUS# directly
13. rename from SLOT2_CONFIG_1 to NGFF_CONFIG_1 for EC team request
14. rename from ACAV_IN_NB to HW_ACAVIN_NB for EC team request
15. rename from SLOT2_CONFIG_0 to NGFF_CONFIG_0 for EC team request
16. rename from SLOT2_CONFIG_2 to NGFF_CONFIG_2 for EC team request
17. rename from LID_CL_NB# to LID_CL_SIO# for EC team request
1. Follow SB reserve CLKDET# net,for x7~x8 no use
2. Follow SB reserve CLKRUN# net,for no use LPC mode
3. DEL SIO_RCIN# net,for no use LPC mode
4. Follow SB reserve SIO_EXT_SCI#,for no use LPC mode
5. Rename PCH_3.3V_TS_EN from 3.3V_TS_EN
6. Follow SB reserve PCI_CLK_LPC1, for no use LPC mode
7. Follow SB reserve PME#, for no use LPC mode
8. Follow SB reserve SIO_EXT_SMI# net, for no use LPC mode
LOM port to be replaced to port 4
Solution Description
Rev.
0.1(X00)
Request
36 EMI EMI request
B B
37 EE For All of Repeater
38 EE GPIO map change 0.1(X00)2017/04/17 4/17 PCH_3.3V_TS_EN PU +3.3V_RUN change page to QV7.2
A A
All
All
All
All
All
All
2017/04/13
2017/04/17 4/17 PWD pin setting double check for all of redrive(dual, signal, USB3)
change 0ohm short pad to 0ohm of as below.
RC328,RT54~57,RZ56,RN99
4/21
UMA
1. SATA repeater --> add QN6, RN226, RN227
2. PCIE/SATA repeater --> add QN7, RN228,RN229,RN230
DSC
1. PCIE/SATA repeater --> add QN6, RN226, RN227
-->Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN
1. RC443 BOM structure change to @
2. UMA : GPIO126->GPU_PWR_LEVEL
3. Add RTCRST_ON_R net neme for QE17.2
4. Add SIO_SLP_SUS#_R net name and PU RE561
5. RC27.2->NC for CLKRUN#
6. UMA : HDD_DET#->SATAGP0
7. Remove RE360/RE364 .
0.1(X00)
0.1(X00)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (6/8)
EE P.I.R (6/8)
EE P.I.R (6/8)
LA-F391P
LA-F391P
LA-F391P
68 70Tuesday, September 19, 2017
68 70Tuesday, September 19, 2017
68 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
Vinafix.com
5
4
Version Change List ( P. I. R. List )
3
2
1
TitlePage#
D D
42
43 EE PD ROM main source change 0.2(X01)
44 EE Schematic align, avoid SUSACK#_R floating 0.2(X01)
45 EE Nuvoton request to change TPM_PIRQ# power rail
46 EE RTD2166 question 0.2(X01)
C C
47 ESD ESD request 0.2(X01)
48 EE For RBOM request. 0.2(X01)
49 EE Correct the symbol 0.2(X01)
50 EE Main source change 0.2(X01)
51 2017/06/08 DFB DFB request 0.2(X01)PCB hole from 3.2mm to 3.3mm
52
53
B B
54 EMI2017/06/14 EMI request add +0.9V_LAN LL2 180 ohm bead 0.2(X01)
35
47
16
47
26
11
37
24
28
33
33
20,36
46
ALL
36
30
MEC5105 ESPI
EC
Power control
MCP(11/14 )
PWR-VCCGT
MEC5105 ESPI
Power control
[Type C]PD
Controller TI-1
MCP(6/14)
CLK,PM,RT C
NuvotonTPM1 .2
DP to VGA &
VGA ConnRTD2166
[Type C]USB 3.0
CONN TYPEC1
NuvotonTPM1 .2
NGFF Card
All
All
All
MEC5105
Support
LAN
Date Issue DescriptionItem
Owner
2017/06/06 GPIO map change UPD2_ALERT#-->UPD2_SMBINT#
2017/06/06 Change netname align with SB WLAN_PWR_EN_U2--> WLAN_PWR_EN
2017/06/06 Add netname for layout
2017/06/06 Add QZ15 and RZ518
EE 0.2(X01)40
EE 0.2(X01)41
WLAN power EN
RC437.2 --> +VCC_GT_K52
RC438.1 --> +VCC_GT_AK52
Change SIO_SLP_WLAN# to SLP_WLAN#_GATE (EC side UE1.K10) & Add RE552
2017/06/06 UT6 change to SA000095R10 (GD)
2017/06/07 Reserve RC551
2017/06/07 TPM_PIRQ# power rail change to +3.3V_ALW_PCH
TPM change to NPCT750
Change UZ12 to SA0000AQ200 and related resistors
2017/06/07 UV6.12 add RV622 PU to +3.3V_RUN
2017/06/07 DT10, DT13, DT14, DT17,DT18,DT5,DT6,DT9 change from
SC40000AT00 to SC40000DF00
2017/06/07 CZ75 from 4.7uF to 10uF
2017/06/07 Update JNGFF1/JNGFF2 symbols
2017/06/08 UD1, UE4, UE6 change to SA00007WE00
Location:H34,H35
LA13 symbol change to " TAI-T_HCB2012KF-121T50_2P"
DELL Dell request to change cap to L-end P/N L-end P/N for all cap2017/06/12 0.2(X01)
EE BOARD_ID change Change RE79 to 130Kohm (rev. X01)2017/06/14 0.2(X01)
Solution Description
Rev.
0.2(X01)EE39
0.2(X01)EE EC request to reseve OR gate for
0.2(X01)
Request
55 RF2017/06/14 RF request CA5,CA6 change to 27pf 0.2(X01)
56
57
58
A A
29
41
9
47
DMIC
All
MCP(4/14)GS PI
,I2C,UART,I SH
Power Control
2017/06/15 0.2(X01)
DELL DELL request
EE2017/06/15 GPIO map change Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3
1-1. pop PJP33
1-2. Non-pop UZ23,CZ129,CZ130,PJP32
2-1. del UZ37,CN50,CN51,PJP30
Reserve RC553-RC556 for connector selection
0.2(X01)
EE2017/06/15 EC request to reseve OR gate for WLAN power EN Change QZ15 to SB00000T000 0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (7/8)
EE P.I.R (7/8)
EE P.I.R (7/8)
LA-F391P
LA-F391P
LA-F391P
69 70Tuesday, September 19, 2017
69 70Tuesday, September 19, 2017
69 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
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5
4
Version Change List ( P. I. R. List )
3
2
1
TitlePage#
D D
59 41
60
61
62
63
64
65
C C
66
67
68
69
70
71
B B
72
9
47
25
30
24
26
34
ALL
26
28
25
ALL
36
All
MCP(4/14)GS PI
,I2C,UART,I SH
Power Control
DP/USB Redriver
SW1 TUSB546
Codec ALC3246
DP to VGA &
VGA ConnRTD2166
[Type C]PD
Controller TI-1
Codec ALC3246
All
[Type C]PD
Controller TI
USB 3.0
CONN TYPE C
DP/USB3 Repeater
SW TUSB546
All
MEC5105 Support
Date Issue DescriptionItem
2017/06/15 0.2(X01)
Owner
DELL DELL request
EE2017/06/15 GPIO map change Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3
1-1. pop PJP33
1-2. Non-pop UZ23,CZ129,CZ130,PJP32
2-1. del UZ37,CN50,CN51,PJP30
Reserve RC553-RC556 for connector selection
EE2017/06/15 EC request to reseve OR gate for WLAN power EN Change QZ15 to SB00000T000 0.2(X01)
EE2017/06/15 PS8743 colay Add RT410, RT411, RT412,RT413, RT414, RT415, RT416,CT213
Add RT405, RT406, RT407, RT417, RT418
EMC2017/06/16 EMC request CL11,CL12 change to close UL1.46,47 0.2(X 01)
EE2017/06/21 RTK suggest
LV19/LV20 --> RV650/RV651 75 Ω ;
CV132/CV133 2P
EE2017/06/21 TPS65982(UT5) update version DB --> DC (SA0000AX700) 0.2(X01)
ESD2017/07/26 ESD request DA2, DA6, DA7 change main source from SCA00002900 to SCA00001A00 0.3(X02)
2017/08/01 EE Change cap to 0-end P/N 0-end P/N for all cap 0.3(X02)
2017/08/02 EE TI TPS65982 request(TBTA_DEBUG4) pop RT407 when pop 8743 & change to 10K 0.3(X02)
2017/08/02 EE SE part COS issue. CT99, CT100, CT101, CT102 change to 0.01u_X5R_0201_25V (SE00000YH00) 0.3(X02)
EE TI update version(TUSB546A) TUSB546 change form SA00009R710 to SA00009R7202017/08/02 0.3(X02)
2017/08/03 EE To avoid in-rush current caused voltage drop Add soft start solution(only reserved) on QV8,QZ1
(add CV635, CZ200, RZ380,RV400)
8/4
Add soft start solution(only reserved) on QE15,QC7
(add CC340,RE565)
2017/08/08 EE BOARD_ID change Change RE79 to 62Kohm (rev. X02) 0.3(X02)
Solution Description
Rev.
0.2(X01)
0.2(X01)
0.2(X01)
0.3(X02)
Request
73
74
75
A A
9
ALL
30
CPU (4/14)
All
All
2017/08/09 EE TPM Pin connectivity requirement Add RC560,RC561(reserved) BOM options. 0.3(X02)
2017/08/11 EE Buyer request main source change
1 .SC1N4148180 --> SC100005500
2. SC100000S00 --> SCS00003700
0.3(X02)
2017/08/11 EMI EMI request CL10 depop 0.3(X02)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (8/8)
EE P.I.R (8/8)
EE P.I.R (8/8)
LA-F391P
LA-F391P
LA-F391P
70 70Tuesday, September 19, 2017
70 70Tuesday, September 19, 2017
70 70Tuesday, September 19, 2017
1
0.2
0.2
0.2
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