Commodore PC40-III a

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SERVICE MANUAL

PC40-III

MARCH, 1989 PN-314134-01

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ft commodore

COMPUTERS

SERVICE MANUAL

PC40-III

MARCH, 1989 PN-314134-01

CBM INTER-COMPANY

(NOT FOR RESALE)

Commodore Business Machines, Inc.

12 00 Wilson Drive, W est Chester, Pennsylvania 19 38 0 U.S.A .

Commodore makes no expressed or implied war ranties with regard to the information contained herein. The information is made available solely on an as is basis, and the entire risk as to quality and accuracy is with the user. Commodore shall not be liable for any consequential or incidental damages in connection with the use of the information con tained herein. The listing of any available replace ment part herein does not constitute in any case a recommendation, warranty or guaranty as to quality or suitability of such replacement part. Reproduction or use without expressed permission, of editorial or pictorial content, in any matter is prohibited.

This manual contains copyrighted and proprietary information. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written permis sion of Commodore Electronics Limited.

PC40-III SERVICE MANUAL

TABLE OF CONTENTS

SECTION 1 — SPECIFICATIONS

SECTION 2 — THEORY OF OPERATIONS

SECTION 3 — TROUBLESHOOTING GUIDE

SECTION 4 — PARTS

SECTION 5 — IC PINOUTS, SCHEMATICS

APPENDIX A — POWER SUPPLIES

APPENDIX B — DISK DRIVES

APPENDIX C — KEYBOARD

APPENDIX D — OPTIONS

APPENDIX E — TECHNICAL UPDATES

PC40-III SERVICE MANUAL

SECTION 1

SPECIFICATIONS

PC40-III SERVICE MANUAL

DESCRIPTION

This specification describes the Functional Requirements for the PC40-III computer. This system consists of a processor, memory, control unit and keyboard. This system is compatible with the IBM AT series of computers. The monitor for the system is an independent unit and must be VGA compatible.

STANDARD FEATURES

MICROPROCESSOR SPEEDS MEMORY CAPACITY VIDEO OUTPUT VIDEO DISPLAY RAM PARALLEL OUTPUT SERIAL OUTPUT MOUSE PORT

AutoConfig BIOS BATTERY BACKED UP CLOCK EXPANSION SLOTS

DISK STORAGE

112 WATT POWER SUPPLY

80286 6, 8, 12 MHz user selectable

1 MByte on board Video Graphics Array compatible Horizontal scan frequency 31.5 KHz 256 KByte Centronics (IBM) Compatible RS-232 IBM Compatible Commodore 1352 mouse Hardware and Software Compatible with Microsoft Bus Mouse

3 AT style slots

1 XT style slot 40 MByte hard disk (formatted) (AT style drive with embedded controller)

1.2 MByte Floppy Disk (formatted)

OPTIONAL FEATURES

Math Coprocessor 80287.

Disk and Tape storage

1 40 MByte hard disk drive inside the case. 1 5.25" 1.2 MByte floppy drive accessible from the front of the unit. 1 unused slot that can be used for a second floppy or a streaming tape unit.

Either or both floppy drives may be 3.5" drives.

Expansion slots

The three full length expansion slots conform to the standard AT bus structure, therefore, all options that are available for the AT on the after sale market are available on this unit.

The one XT expansion slot is for short cards that do not require a full length slot.

VIDEO FEATURES ALPHANUMERIC MODES MODE # COL X ROW CHAR MATRIX RESOLUTION

COLORS

STANDARD

0, 1

40 X 25

8 X 8 320 X 200

16

CGA (1)

9 X 16 360 X 400

16 OF 256K

VGA (2)

2, 3

80 X 25

8 X 8

640 X 200 16

CGA (1)

9 X 16 720 X 400 16 OF 256K VGA (2)

7

80 X 25

9 X 14

720 X 350 MONOCHROME MDA

9 X 16 720 X 400

MONOCHROME

VGA (2)

54

132 X 43

7 X 9 924 X 387

COLOR

ENHANCED

55

132 X 25

7 X 16 924 X 400

COLOR

ENHANCED

56

132 X 43

7 X 9 924 X 387 MONOCHROME ENHANCED

57

132 X 25

7 X 16 924 X 400 MONOCHROME ENHANCED

IBM, AT and XT are registered trademarks of International Business Machine. AutoConfig is a registered trademark of Commodore Business Machine.

1-1

PC40 III SERVICE MANUAL

GRAPHICS MODES: MODE #

RESOLUTION

COLORS

STANDARD

4, 5

320 X 200

4 4 OF 256K

CGA (1) VGA (1) & (2)

6

640 X 200

2 2 OF 256K

CGA VGA (1) & (2)

D

320 X 200

16 OF 256K VGA (1)

E

640 X 200 16 OF 256K VGA (1)

F

640 X 350

MONOCHROME VGA

10

640 X 350

16 OF 256K VGA

11

640 X 480

2 OF 256K VGA/MCGA

12

640 X 480

16 OF 256K VGA

13

320 X 200

256 OF 256K

VGA/MCGA (1)

NOTES

(1) All 200 line modes are double scanned for 400 line resolution. (2) The VGA implementation of these modes is the default.

VIDEO SIGNALS

Vertical

Horizontal sync

Vertical sync

Resolution

Frequency

Polarity Frequency Polarity

350 lines

31.5 KHz +

70.1 Hz

400 lines

31.5 KHz

-

70.1 Hz +

480 lines

31.5 KHz

-

59.9 Hz

600 lines*

35.2 KHz

-

56.2 Hz

*Requires an Analog MultiSync compatible monitor.

BLOCK MEMORY MAP

Standard Memory 640 KBytes range 0 to 655360 decimal (Oh to 9FFFFh) 384 KBytes range 1048576 to 1441792 decimal (lOOOOOh to 160000h) The top 384 KBytes of memory can be disabled to function with third party add on boards.

KEYBOARD FEATURES

standard

United States ASCII 101 International 102 key

optional

Dvorak

Special keyboards and drivers are available to customize the keyboard for the following countries. Germany, Spain, France, Italy and the United Kingdom.

ADDITIONAL FEATURES

Numeric keypad 4 cursor keys in an inverted T formation

OTHER FEATURES

Security lock for keyboard lock out

Built in speaker External Configuration switches Battery backed-up real time clock/calendar. Metal Case (can support monitor)

MultiSync is a registered trademark of NEC

1-2

PC40III SERVICE MANUAL

SPEED SELECTION

One of the three operating speeds is selected by either a program or by the operator. Default speed is 6 MHz. The operator or program can change the speed by issuing the following command strings. Control Alternate S for standard 6 MHz Control Alternate T for turbo 8 MHz Control Alternate D for double 12 MHz

PHYSICAL SPECIFICATIONS

Height

5.75 inches 14.6 cm

Depth

15 inches 38.1 cm

Width

14 inches

35.6 cm

Weight

21 pounds 9.55 Kg

Minimum Clearances Right side

4 inches 10.2 cm

Back side

4 inches

10.2 cm

ENVIRONMENT SPECIFICATION

ENVIRONMENTAL —temperature—

Operational Storage Gradient

—humidity—

Relative Gradient Wet Bulb

4 to 40 C. ( + 39 to + 122 F)

-40 to +60 C. (- 40 to +160 F) + 10 C/Hour (+18 F/Hour)

8% to 80% RH (no condensation) 20% per Hour (no condensation) 26 C, 78 C (no condensation), maximum

VIBRATION

Operational

0.048 in. Dbl. Amplitude (5 - 17 Hz)

Non-Operate

0.73 G, 17 - 150 Hz

0.33 G, 200 to 500 Hz use linear interpolation for acceleration levels between 150 Hz and 200 Hz

1.0 G, 5 - 2000 Hz, sweep of .067 decades/minute

SHOCK

Operational

10 G, 11 mS Half Sine Wave; any axis.

Non-Operate

50 G, 25 mS Square Wave; any axis. 25 G, 25 mS Square Wave; heads over data.

ALTITUDE

Operational

-457 to 2,972 Meters ( - 1,500 to + 9,750 Ft)

Non-Operate

-457 to 12,192 Meters ( - 1,500 to +40,000 Ft)

ACOUSTIC NOISE

45 dBA at 1 meter

REGULATORY APPROVALS:

STANDARD

DESCRIPTION

USA/Canada:

UL 478 FCC CSA 22.2

EUROPE

VDE IEC 435

Electronic Data Processing Units and Systems FCC Class B, Part 15 Subpart J Data Processing Equipment, Consumer and Commercial Products.

1-3

PC40-III SERVICE MANUAL

SECTION 2

THEORY OF OPERATIONS SYSTEM BLOCK DIAGRAM SYSTEM OVERVIEW NOTES — OPERATIONS GUIDE

CN301

SYSTEM BLOCK DIAGRAM

PC40-III SERVICE MANUAL

SYSTEM OVERVIEW

(To be released)

2-2

PC40-III SERVICE MANUAL

NOTES FROM OPERATIONS GUIDE

AUTOCONFIG

AUTOCONFIGuration is a unique feature of Commodore PC personal computers like the PC40-III, allowing the computer to automatically sense additional peripheral devices plugged into the expansion bus. Once these additional devices are detected, the resident peripherals on the PC40-III motherboard are adjusted so as not to conflict with expansion peripherals. The AUTOCONFIG''' feature can prevent hardware damage to peripherals and motherboard, as well as ease the installation of expansion cards.

The AUTOCONFIG"' process is described in this section.

Video

The PC40-III first examines the expansion bus for any expansion Advanced Video Adapter BIOS in the OCOOOOh — 0C7FFFh

memory range. If an expansion video BIOS is found, then an external VGA or EGA controller is assumed to be on the bus and the onboard VGA controller is disabled to avoid conflict. If an expansion video BIOS is not found, the video output is configured in accordance with the default CONFIG Control video setting, as defined by the CONFIG dip switches 1, 2 and 3.

You can add an expansion MDA or CGA compatible controller in conjunction with the onboard VGA controller or provide two video screens. (This makes many CAD packages easier to use.)

NOTE: When using the PC40-IITs onboard video controller, a VGA compatible monitor such as Commodore Models 1403 and 1450 (monochrome) or 1950 (color) must be connected to the 15 pin video output connector (no matter what video mode you have selected).

If you want to use two video screens, there are several things you should remember. First, you should use a CGA, MDA or compatible adapter — one that has no BIOS ROM of any kind.

Also, if you were to use an MDA/Herc adapter (monochrome) and you have the CONFIG switches set for VGA color, the PC40-III will boot using your VGA monitor and you will see a blinking cursor on your monochrome monitor, indicating that it has been initialized. If, while using the MDA/Herc adapter in the expansion port, you have the CONFIG switches on the back of the System Unit set to MDA/Herc, your PC40-III will use the monochrome monitor as the boot monitor and the VGA monitor will be initialized with the blinking cursor.

In either case, you can switch between the VGA and the monochrome monitors by using the MS-DOS MODE command. The syntax for the MODE command is as follows:

• MODE MONO — sets the MDA as the default monitor

• MODE co80 — places the onboard VGA adapter into 80 column mode and sets it as the default monitor

• MODE co40 — places the onboard VGA adapter into 40 column mode and sets it as the default monitor

Serial Port (COMn:)

Before the onboard serial port is enabled a scan of the two standard COMn: hardware locations is made. If serial hardware (serial card/modem) is found operational, possible bootup message(s) may be:

EXPANSION COM at 03F8h

and/or

EXPANSION COM at 02F8h

If both available COM: addresses are occupied by expansion boards, then the onboard serial port will not be enabled. The

onboard serial port will be configured and tested at I/O address 03F8h if no expansion COM:’s are found and will be con

figured and tested to the unused COM: address if only one expansion COM: is found. If the onboard serial port is configured and tested successfully a message will be output during bootup:

ONBOARD COM at 03F8h

or

ONBOARD COM at 02F8h

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PC40-III SERVICE MANUAL

Parallel Port (LPTn: or PRN:)

Before the onboard parallel port is enabled a scan of the three standard LPTn: hardware locations is made. If parallel hard ware (e.g., a printer card) is found operational, possible bootup message(s) may be:

EXPANSION LPT at 0378h

and/or

EXPANSION LPT at 0278h

and/or

EXPANSION LPT at 03BCh

If all available LPT: addresses are occupied by expansion boards, then the onboard parallel port will not be enabled. The onboard parallel port will be configured and tested at I/O address 03BCh if no expansion LPT:’s are found, and will be con figured and tested to the unused LPT: address if two expansion LPT:’s are found. If only one expansion LPT: is found, the onboard parallel port will be enabled to the first available I/O address, when searching in the following sequence:

03BCh, 0378h, 0278h

If the onboard parallel port is configured and tested successfully, a message will be output during bootup:

ONBOARD LPT at 03BCh

or

ONBOARD LPT at 0378h

or

ONBOARD LPT at 0278h

Mouse Port

A check is made for a standard Microsoft Bus Mouse. If it is found in the I/O channel then the onboard Microsoft compatible mouse hardware is never enabled. The following message will appear during bootup:

EXPANSION MOUSE at 023Ch

If no expansion mouse is found the onboard mouse is enabled and tested. If mouse is operational then the following message will appear during bootup:

ONBOARD MOUSE at 023Ch

NOTE: The onboard mouse hardware is enabled/tested independent of the presence o f the actual mouse. The bootup messages

will appear even if the Commodore PC Mouse Kit is not attached.

80287 Numeric Coprocessor

A test is made for the presence of an 80287 Numeric Coprocessor during bootup. If an 80287 is detected the following message will be output:

80287 Numeric Coprocessor

NOTE: 80287 coprocessors are available in 5, 6, 8 and 12 MHz speeds. However, the units are downwardly compatible only — for example, an 8 MHz coprocessor will function if the PC40-III is running at 6 or 8 MHz, but a 6 MHz unit will not

function properly if the PC40-III is running at 12 MHz. In order to use the 80287 at all three CPU speeds (6, 8, 12 MHz), an 80287-8 (an 8 MHz part) is necessary.

NOTES FOR THE PROGRAMMER

It is possible to override the configuration done at bootup. We STRONGLY recommend that only advanced programmers

with experience with low-level hardware/software interaction attempt this.

NOTE: If software override of the default configuration is performed, the presence o f any expansion hardware should be taken into account to prevent hardware conflict resulting in damage of the expansion hardware or the PC40-III motherboard.

Configuration is performed via the COMMODORE CONFIGURATION REGISTER at I/O address 0230h. This register is read/write with only bit7 changing its meaning from read to write. The register values are shown in the following table.

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PC40-III SERVICE MANUAL

COMMODORE CONFIGuration REGISTER — I/O addr 230h

R/W bit7

bit6

bit5

bit4

bit3

bit2 bitl

bitO

R mono rtc

X

mouse

coml

comO lptl

lptO

W venb’ rtc

X

mouse

coml

comO

lptl

lptO

mono — indicates that the onboard video adapter is setup as a monochrome adapter when high, color when low.

venb’ — when set low the onboard video adapter will be enabled,

rtc — when set high the onboard real-time clock will be enabled. X — this bit is reserved for future use. mouse — when set high the onboard mouse will be enabled.

coml comO

lptl lptO

low low

— onboard serial port is disabled.

low low

— onboard parallel port is disabled.

low

high

— serial port enabled at I/O addr 02F8h

low

high — parallel port enabled at I/O addr 03BCh

high low

— serial port enabled at I/O addr 03F8h

high

low

— parallel port enabled at I/O addr 0378h

high high

— this configuration is reserved.

high high — parallel port enabled at I/O addr 0278h

THE PC40-III HARDWARE CONFIGURATION

Using the PC40-III Setup Utility

Once MS-DOS has finished booting and the C > prompt has appeared, you can use the built-in Setup utility to give the system detailed information on your PC40-III configuration. To run the Setup utility, hold down the Control and Alt keys and simultaneously press the Esc key. The main menu of the Setup utility will appear and will look like this:

r

Commodore Setup Utility

Date 23.08.88 Time 14:23:08 Diskette 1 1.2M Diskette 2 NONE Hard Disk 1 28 Hard Disk 2 NONE Video SPECIAL Coprocessor NONE Base Memory 640 KB Extended Memory 384 KB

Base memory found: 640 KB Extended memory found: 384 KB

Use | , 1 to select items Use to select predefined values Use <PgDn> to view more hard disk

types Press <Esc> to abort SETUP Press <End> to exit and update

Hard Disk Type Information

Type Cyln Head Sect W-pc L

-zone

Size

1

306

4 17

128

305 10 MB

2

615

4 17

300 615 20 MB

3

615

6

17

300

615

30 MB

4

940

8

17

512

940

62 MB

5

940

6 17

512

940

46 MB

6

615

4 17

NONE

615

20 MB

7

462 8

17

256

511

30 MB

8

733 5

17

NONE 733 30 MB

9

900 15

17

NONE

901

112 MB

10 820 3

17

NONE

820

20 MB

11 855 5

17

NONE

855

35 MB

12

855

7 17

NONE

855

49 MB

13

306 8

17

128 319

20 MB

14 733

7

17 NONE

733 42 MB

15

0

0 0 0 0

0 MB

16 612 4 17

0 633

20 MB

V .

COMMODORE SETUP UTILITY MAIN MENU

2-5

PC40-III SERVICE MANUAL

As noted on the Setup screen, you can use the cursor keys and the keyboard to define or change the system configuration, as follows:

• Use the up and down cursor keys to move from option to option in the main menu.

• Use the left and right cursor keys to select the predefined entries for each option.

• Use the keyboard to type in any information that is not predefined.

• Use PgDn to tell the pulldown menu (see Figure below) to display additional hard disk types.

Following is specific information about the various Setup menu options.

Setting the Date and Time for the Real Time Clock/Calendar

The PC40-III has a Real Time Clock/Calendar with a battery backup. This means that once set, the clock/calendar will keep the correct date and time even when the computer is turned off. You use the first two lines of the Setup Utility to set the

Real Time Clock/Calendar, as follows:

Date: Allows you to set the correct date into the Real Time Clock. This option does not have any predefined entries; simply enter the date from the keyboard, in the format dd/mm/yy.

Time: Allows you to set the correct time into the Real Time Clock, without invoking MS-DOS. This option also does not have any

predefined entries; simply enter the time from the keyboard, in the format hh:mm:ssf where hh = 00-23,mm = 00-59,and ss = 00-59. Setting the Floppy Disk Drive Options

You can have a maximum of two floppy diskettes configured into your PC40-III. The next two Setup menu options, Diskette 1 and Diskette 2, allow you to tell the system how many floppy drives are available and what type they are. Here’s how to set these options: Diskette 1: Predefined entries: None, 360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5. The floppy drive in your PC40-III is always considered Diskette 1. Since PC40-III is equipped with a high density (1.2 MB) drive, select 1.2 Mb 5.25 for Diskette 1. Diskette 2: Predefined entries: None, 360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5. If you have not installed a second

floppy drive in your PC40-III, select None for Diskette 2. If you have installed a second floppy drive, select whichever drive

type (360 Kb 5.25, 1.2 Mb 5.25, 720 Kb 3.5, 1.44 Mb 3.5) applies to the installed drive.

Setting the Hard Disk Drive Options

Hard Disk 1 and Hard Disk 2, the next two options in the Setup utility, define how many hard disk drives are available and

what kind of hard disk drives they are. Hard disk drives are identified by a pre-assigned Drive Type (1, 2, etc.). This number tells the PC40-III the drive manufacturer and capacity.

r

Commodore Setup Utility

■ \

Date 23.08.88 Time 14:26:26 Diskette 1 1.2M Diskette 2 NONE Hard Disk 1 28 Hard Disk 2 NONE Video SPECIAL Coprocessor NONE Base Memory 640 KB Extended Memory 384 KB

Base memory found: 640 KB Extended memory found: 384 KB

Use | . 1 to select items

Use to select predefined values Use <PgDn> to view more hard disk

types Press <Esc> to abort SETUP Press <End> to exit and update

Hard Disk Type Information

Type

Cyln 1

Head

Sect

W-pc

L-zone

Size

17

977

5 17

300 977

40

MB

18

977

7

17

NONE 977

56

MB

19 1024

7

17

512

1023

59 MB

20

733 5

17

300 732

30 MB

21

733 7

17

300

732

42 MB

22

733

5 17

300

733

30 MB

23

306 4

17

0 336

10 MB

24

805 4 26

0

820

40 MB

25 776

8

33 0

800

100MB

26

745

4

28

0

800

40

MB

27

625

5

27

0 871 41

MB

28

965

5 17

0 1000

40 MB

29

965 10 17

0

1000

80

MB

30 782 4

28

0

800

42

MB

31 0

0 0

0

0 0 MB

32 0

0

0 0 MB

J

SETUP UTILITY PULLDOWN MENU FOR HARD DISK DRIVE TYPE

2-6

PC40-III SERVICE MANUAL

Here’s how to define your hard disk configuration: Hard Disk 1: Your PC40-III comes equipped with a 40 MB hard disk drive. This drive is always considered Hard Disk 1. The Drive Type for this drive is shown on a sticker located on the back of your System Unit. Find this number and type it

in after Hard Disk L

The PC40-III Setup utility includes a menu of hard disk drive types with their individual ID numbers. You can page through the menu by pressing the PgDn key. For example, the opening Setup screen on Page 2-3 lists drive types 1 through 16. If you press PgDn, the Setup screen will be as shown on Page 2-4, with drive types 17 through 32 listed. Hard Disk 2: This option is not supported by the onboard controller.

Other Setup Options

Video: Tells system what the default video is. Factory-set default is special. To change this setting, see the permissible default modes listed in Appendix H.

Coprocessor: Tells system if an 80287 Numeric Coprocessor (NCP) is installed. Factory-set default is none. Select Yes if you have installed an 80287 Numeric Coprocessor (see Appendix N for information on using an 80287 Numeric Coprocessor).

Base memory: Lets you customize base memory for specific applications. Extended Memory: Tells system how much extended memory is available. The default 384 Kbytes of extended memory can

be enabled or disabled as required by setting the CONFIG Control dip switch 4.

SETTING THE MICROPROCESSOR CLOCK SPEED

The 80286 microprocessor in the PC40-III is capable of running at three different clock (i.e., processor or CPU) speeds:

• Standard speed = 6 Mhz

• Turbo speed = 8 MHz

• Double speed = 12 MHz

The PC40-III is preset to the standard 6 MHz speed. You can switch between the clock speeds by using special key combina tions or by using the MS-DOS ATSPEED command.

To set the clock speed from the keyboard, use these key sequences:

• CTRL-ALT-S for standard speed (6 MHz)

• CTRL-ALT-T for turbo speed (8MHz)

• CTRL-ALT-D for double speed (12 MHz)

NOTE: Some software may require that you select standard or turbo speeds for normal operation.

To set the clock speed using the ATSPEED command, first make-sure the MS-DOS prompt is showing on the screen. Then

type the word ATSPEED, followed by a space, a dash (—), and then a letter (S, T, or D) denoting the desired speed. For instance, if you are in standard speed and you want to change to turbo speed (8 MHz), type the following and press Enter:

ATSPEED —T

Extended Memory Dip Switch

Dip switch 4 enables or disables the 384K of extended memory in the PC40-III.

ENABLE EXT. MEM. jj DISABLE EXT. MEM. gj

4

THE RESET SWITCH

The Reset switch protrudes slightly on the right side of the machine, just behind the keyboard connector. The switch provides an alternative to cycling power when an application program may have “crashed” the computer. Pressing this switch will effectively reboot the computer as if the power had been cycled OFF and then ON. All information in the computer’s RAM

memory will be lost. Be careful not to press this button during disk access, or you may lose information that was being written to mass storage devices (e.g., hard disks or floppy disks) while the switch was depressed.

2-7

PC40-III SERVICE MANUAL

000000

09FFFF 0 AO 0 0 0

OBFFFF 0C0000

OCFFFF 0C8000

OEFFFF 0F0 000

0F80 00

OFFFFF

100000

15FFFF

640K RAM

VIDEO RAM

VGA BIOS

OPTION ROMS

INTERNAL USE

32K AT ROM BIOS

384K RAM (EXTENDED MEMORY)

1MB

.15MB

PC40-III MEMORY MAP

2-8

PC40 III SERVICE MANUAL

JUMPER SETTINGS ON MOTHERBOARD

Jumper Locations on Motherboard

JUMPER FUNCTION DEFAULT

RESULT

JMP 903

Disable HD

Not Installed

HD Installed

JMP 904

HD Type Location A

Location B

Conner HD Quantum HD

PAD 301

80287 Clock Mode

-5-3 Mode

8 MHz Part runs up to 12 MHz

PAD 302

80287 Clock Speed CPU Clock (-h3) 8 MHz Part runs up to 12 MHz

PAD 301 & PAD 302 may be changed to take full advantage of using a 12 MHz 80287. This is a dealer installation only.

2-9

IRQ Vectors Used in the PC40-III

There are two interrupt controllers on the PC40-III:

IRQ 0 — System Timer (built-in)

1 — Keyboard (built-in)

2 — Cascade #2

CPU Interrupt

n

3 — COM2 (built-in or expansion) 4 — COM1 (built-in or expansion) 5 — XT Compact HD (unused) 6 — Floppy (built-in) 7 — LPT1,2,3 (All ports: built-in plus expansion)

PC40-III SERVICE MANUAL

Cascade 2

IRQ 8 — Real Time Clock

9 — Onboard Mouse 10 — Unused 11 — Unused 12 — Unused 13 — Unused 14 — AT Hard Disk (built-in or expansion) 15 — Unused

2-10

PC40-III SERVICE MANUAL

SECTION 3

TROUBLESHOOTING GUIDE

TECHNICAL SERVICE NOTES

WARNING: PC40-III PRINTED CIRCUIT BOARD CONTAINS CMOS CIRCUITRY, USE STATIC PRECAUTIONS

WHEN HANDLING OR SERVICING THIS PRODUCT.

IMPORTANT:

• PC40-III PCB’S RETURNED FOR CREDIT MUST BE SHIPPED IN AN ANTI-STATIC BAG, AVAILABLE THROUGH THE COMMODORE PARTS DEPT. ANY PCBS RETURNED FOR CREDIT BY SERVICE CENTERS WHICH ARE NOT PACKAGED CORRECTLY WILL BE SENT BACK TO THE SERVICE CENTER AND NO CREDIT WILL BE ISSUED.

• PC40-III HARD DRIVES RETURNED FOR CREDIT MUST BE INSERTED IN AN ANTI-STATIC BAG AND PACKED IN A COMMODORE SPECIFIED HIGH DENSITY FOAM SHIPPING BOX, BOTH AVAILABLE THROUGH THE PARTS DEPT. FAILURE TO DO SO WILL VOID WARRANTY.

COMPONENT REPAIR:

PC40-III MAIN BOARD IS A MULTI-LAYERED PCB ASSEMBLY. COMPONENT REPAIR BEYOND THE SOCKETTED CHIP LEVEL RESULTING IN NON-REPAIRABLE DAMAGE WILL VOID WARRANTY. USE STATIC PRECAUTIONS WHEN SERVICING THIS PCB ASSEMBLY.

PC40-III SERVICE MANUAL

TROUBLESHOOTING ERROR MESSAGES

Troubleshooting Guide

Error Messages

Customer Response

Service POD Test (H)

1. DMA 1 error

See your dealer

Test OB

2. DMA 2 error

See your dealer

Test 0C

3.

Interrupt controller 1 error See your dealer

Test 0D

4.

Interrupt controller 2 error

See your dealer

Test 0E

5. PIO error

See your dealer

Test OF

6. Parity error

See your dealer

Test 10

7.

Real time clock is not working

See your dealer

Test lE

8. Illegal shutdown code in CMOS

See your dealer

Test 02

9.

Virtual Mode CPU error

See your dealer

Test 26

10.

Parity error on main circuit board

See your dealer

Misc

11.

Parity error on expansion bus

See your dealer

Misc

12.

Non-recoverable error-Processor halted

See your dealer

Misc

13. Press FI key to continue

Press FI key

Misc

14.

Battery Failure

Run Setup Utility/See your dealer

Test 11

15. Base memory configuration error

Run Setup Utility Test 17

16.

Extended memory configuration error

Run Setup Utility

Test 18

17.

Floppy 0 configuration error

Run Setup Utility

Test 1A

18. Floppy 1 configuration error

Run Setup Utility

Test 1A

19. Coprocessor (80287) configuration error

Run Setup Utility Test ID

20. The realtime clock has not been initialized

Run Setup Utility

Test IE

21.

Keyboard

Check keyboard

Test 14

23. Boot failure, check disk and hit any key to try again

Check for non-MS-DOS disk in Drive A:; run Setup Utility

Misc

3-1

PC40-III SERVICE MANUAL

POWER ON DIAGNOSTICS

PC40-III Trouble Shooting — Section 3

The Commodore 80286 ROM bios contains a “ Power on Diagnostic” program which tests the functions of hardware and checks the configuration prior to passing control to the operating system.

The number of the test routine being run is passed to addr 03 78 (H) prior to the start of each test section. The 80286 processor is initialized by the “ RESET” signal. Refer to RESET description in IC pinout section, note that “VCC” and

“CLK” to CPU must be correct and “HOLD” must not be active for 34 ticks from leading edge to trailing edge of initial reset. RESET will terminate all instruction execution and local bus activity until it is negated. Prior to fetching, decoding and executing,

the first instruction, located at physical address FF FF F0 (H), the 80286, in real address mode, processes some micro code located in its internal ROM, this takes about 38 ticks.

Test 01 (H) 0000 0001 (B)

The first test performed by the power on diagnostic checks the 8088 flags, the arithmetic logical unit, and the CPU registers. If a failure is detected in Test 01, a “HALT” instruction is executed. This will stop program execution and prevent the CPU

from using the local bus. The 80286 can be forced out of the halted state by “RESET” , “NMI” or “ INTR” (when “ INTR” is used for RESTART, the interrupt enable bit of flag register must be on (set to 1), and the effective address computed from CS:IP will point to the next instruction after the halt instruction).

***Failure in test 01 indicates defective 80286.

Test 02 (H) 0000 0010 (B)

This routine checks to see if a “SHUTDOWN” has occurred. A shutdown can indicate a severe error which would prevent the CPU from further processing.

NOTE: A halt or shutdown condition is signaled externally, by the 80286 as a bus operation. Low states on SO', SI', COD/INTA',

and a high state on M/IO' indicate a halt or shutdown. The state of address line 1 will indicate which condition, A1 high is halt, A1 low is shutdown.

After the test number is moved to the parallel port a check for keyboard reset is conducted and the program branches to test 04 (H) if it has.

The check for shutdown begins by examining the 8242 keyboard controller status port. In all ten shutdown conditions are tested, of these, three unexpected shutdown conditions, numbers 6, 7 or 8, any one of which if true, will generate the console message:

“ Illegal Shutdown Code in CMOS”

NOTE: Branch information for shutdown routines are stored in CMOS memory. The shutdown command is sent to the 8242,

the UPI status port, which will halt the CPU. Return depends on the shutdown code in CMOS memory.

An error code, F6, F7 or F8, (HEX) is sent to the parallel port before calling the display routine which generates the above message.

In real address mode a shutdown could occur under the following conditions: Interrupt number 8, interrupt number 13, or a “CALL INT” or “ PUSH” instruction which wraps stack segment when SP

is ODD. Routines also perform valid shutdowns to exit protected mode. During these the DMA page register will be initialized and

interrupt control words (ICW) 1, 2, 3 and 4 will be reinitialized. Other routines within the test enable “NMI” , parity and set the I/O check bit.

***Failures in test 02 could indicate problems on the local bus, or expansion bus. This would include: 80286, FE3000, FE3010,

or any third party cards.

Test 03 (H) 0000 0011 (B)

Eprom checksum test verifies contents of eprom by adding bytes and checking for result of zero. A compensation byte is fac tored into the addition to make the sum zero.

Detection of an error results in a halt condition and would invalidate tests 01 and 02. ***Failure in test 03 indicates defective ROM.

3-2

PC40-III SERVICE MANUAL

Test 04 (H) 0000 0100 (B)

Test 04 checks the DMA page registers by writing and reading bits starting at address 80 (H). ***Failure in test 04 indicates possible defective FE3010, or local bus.

Test 05 (H) 0000 0101 (B)

Timer 1 and timer 2 are checked for correct operation. Interrupts are masked off during the test. ***Failure in test 5 indicates possible defective FE3010.

Test 06 (H) 0000 0110 (B)

Memory refresh test. Timer and DMA are setup to initiate refresh cycles every 15.1 microseconds. Size of virual memory is calculated.

***Failure in test 06 indicates possible FE3010, Refresh logic or memory problem.

Test 07 (H) 0000 0111 (B)

Test 07 checks the 8242 keyboard controller by writing and reading the keyboard buffers. ***Failure in test 07 indicates possible defective 8242 or associated circuitry.

Test 08 (H) 0000 1000 (B)

Test 08 writes and reads the first 128K of RAM and verifies block size is 128K. First pass writes addresses into data, the second pass writes the complement of the address into data. Memory is cleared after test. The battery status is also confirmed in test 08.

***Failure in test 08 indicates possible defective RAM or RAM logic.

Test 09 (H) 0000 1001 (B)

Test and configure video. A search is made to determine if MDA, CGA or a special video adapter is configured, if not the onboard VGA is enabled and a call to VGA bios is executed. The dip switches are read to determine the default video mode.

NOTE: The mode register setting in the 5720 controls the reset signal to the onboard VGA controller chip. If no special video

adapters are found on the expansion bus then “NOVID'” from the 5720 to the PVGA is negated.

On completion of this test the title and copyright message are displayed.

Test 0A (H) 0000 1010 (B)

Test RAM from 128K to 640K. A display message is generated indicating that the base RAM of 128K, Test 08, is OK. Blocks of 128K, starting at 128K are then tested by writing, reading and verifying RAM. The first pass writes addresses to data,

that is, the address which defines the physical location is also used as the bit pattern that is being written. The second pass writes complement of address into data.

The test displays results in blocks of 128K to the console each time a 128K boundary is reached. At completion of the onboard memory test the CPU is placed in virual mode and a test for virtual memory (over 1 MEG) is started. NOTE: See test 26 (H).

***Failure in test 0A indicates a defective RAM.

Test 0B (H) 0000 1011 (B)

DMA controller #1 register check. NOTE: Appendix L of the PC40-III operator guide lists error messages starting with this test, see page 85 of operations guide

part number 319983-01.

Four current address registers (16 bits wide, each) and four current word count registers (16 bits wide, each) for each of the

four DMA channels are written to and read from to verify operation.

A failure in test 0B will generate the following display on the console:

“ DMA 1 error”

The beeper will sound, and a halt instruction will be executed.

♦ ♦♦Failure in test 0B indicates A defective FE3010.

3-3

PC40-III SERVICE MANUAL

Test OC (H) 0000 1100 (B)

DMA controller #2 register check. The second functional 8237 containing four current address registers (16 bits wide, each) and four current word count registers (16 bits wide, each) within the FE3010 are written to and read from to verify operation.

Successful completion of the test OC will set the modes for DMA channels 0 through 3 and enable cascading by channels 4, 5 and 6 (DMA 1).

A failure in test OC will generate the following display on the console:

“ DMA 2 error” The beeper will sound, and a halt instruction will be executed. ♦♦♦Failure in test OC indicates a defective FE3010.

Test OD (H) 0000 1101 (B)

Interrupt controller #1 test. Patterns are written to, and read from the interrupt mask register (IMR) which controls the inter rupt request register (IRR).

A verification is made that no interrupts can occur if “IMR” is set to FF (H). A vector is initialized to a temporary interrupt service routine in the event of a failure.

A test for correct timer 0 interrupt is also made. A failure in test OD will generate the following display on the console:

“ Interrupt controller 1 error” The beeper will sound, and a halt instruction will be executed.

♦♦♦A failure in test OD indicates a defective FE3010.

Test OE (H) 0000 1110 (B)

Interrupt controller #2 test. The second functional 8259 contained in the FE3010 is tested as in test OD, without timer test. A failure in test OE will generate the following display on the console:

“ Interrupt controller 2 error” The beeper will sound, and a halt instruction will be executed.

♦♦♦A failure in test OE indicates a defective FE3010.

Test OF (H) 0000 1111 (B)

Check peripheral in/out register. Write and read from PIO register. A failure in test OF will generate the following display on the console:

“ PIO error” The beeper will sound, and a halt instruction will be executed.

♦♦♦A failure in test OF indicates a defective FE3010.

Test 10 (H) 0001 0000 (B)

RAM parity test. Blocks of RAM are written to and read from, parity check for odd parity is made. Parity disabled after successful test.

NOTE: PC40-III does not use parity, third parity boards that use parity will enable parity.

“NMI” is enabled and a service routine for a parity error generates the following console message.

“Parity error”

The beeper will sound, and a halt instruction will be executed.

♦♦♦Failure in test 10 indicates a defective RAM, third party card, NMI, or local bus.

Test 11 (H) 0001 0001 (B)

Test CMOS clock for battery failure and checksum failure.

Beeper will sound if failure is detected. Console will display:

“Battery failure” or “CMOS checksum failure” or both.

♦♦♦Failure of test 11 indicates a defective battery, defective oscillator, or M146818A.

3-4

PC40 III SERVICE MANUAL

Test 12 (H) 0001 0010 (B)

This test is disabled. It is used only in manufacturing tests. The beeper will sound for a set length prior to the start of test 13 (H). In a system which has passed all tests to this point

the beeper sound heard now would be the one heard in the power up routine.

Test 13 (H) 0001 0011 (B)

Setup interrupt controller and move vector tables to RAM. Vector addresses are fetched from top 8K module. NOTE: Vectors for video were setup in test 09. Master and slave interrupts are enabled at this point. Test 13 does not create any error messages.

Test 14 (H) 0001 0100 (B)

Keyboard test. Functional test of the 8242 keyboard controller at U203. A test for a stuck key on keyboard is performed. Check is made to see if key lock is locked.

A failure in test 14 will display the following error message on console:

“Keyboard error”

***Error indicates a defective 8242 controller or a defective keyboard.

Test 15 (H) 0001 0101 (B)

Test and configure the parallel port. Parallel port addresses are setup, reads and writes to ports are done. Set time out. No error messages are generated by this test.

NOTE: PPC1 at U602 controls parallel output. Test 16 (H) 0001 0110 (B)

Configure serial COM1 and COM2 for 8250 at U604. Read serial interrupt ID, set number of serial channels. No error messages are generated by this test.

Test 17 (H) 0001 0111 (B)

Configure memory less than 640K. Parity (for EXPANSION RAM) is enabled. Memory was tested in test 0A, and “CMOS STATUS” set. A check for a warm boot (ALT/CNTRL/DEL) is made and a

comparison of the old and new memory configuration is performed. If a memory size mismatch is detected, the beeper will sound and the following non-fatal error message will be displayed on the console:

“ Base memory configuration error”

The new configuration is stored.

***Check the settings for RAM size in the setup utility if you encounter this message.

Test 18 (H) 0001 1000 (B)

Configure memory over 1 megabyte (virtual memory). Check is made on address line 20, a low indicates virtual address mode. CMOS status is checked as in test 17, a memory size mismatch will sound the beeper and generate the following non-fatal

error message on the console:

“Extended memory configuration error”

The new configuration is stored.

***Check the settings for RAM size in the setup utility if you encounter this message.

Test 19 (H) 0001 1001 (B)

Configure keyboard test. Setup keyboard buffers, enable keyboard interrupt and test if key switch is turned to the on position.

If the key switch is off the following message will be displayed on the console:

“Key switch is off. Turn it on to continue.”

NOTE: You are in a loop until you turn on the key switch.

3-5

PC40-III SERVICE MANUAL

Test 1A (H) 0001 1010 (B)

Configure the floppy disk drive. Calculate number of floppy drives present. Check drive type, compare settings stored in CMOS, if a mismatch the following message will be displayed on console:

“Floppy 0 configuration error” ***Check settings in setup utility if above message is displayed. Test checks second floppy configuration, if a mismatch the following message will be displayed on the console:

“Floppy 1 configuration error” ***Check settings in setup utility if above message is displayed. New configuration is stored in CMOS. Floppy interrupt is enabled.

NOTE: Refer to installation instructions when adding a second floppy to the system. It may be necessary to change jumpers

on drive for proper operation.

Test IB (H) 0001 1011 (B)

Configure the hard drive. Check configuration if a mismatch hard drive will not be setup. No error message is generated.

Test 1C (H) 0001 1100 (B)

Test number is not moved to parallel port for this configuration. This routine only turns on the game card bit in the “EQUIP FLAG” .

No error message is generated.

Test ID (H) 0001 1101 (B)

Configure 80287 coprocessor. Check if 80287 is present. Enable 80287 interrupt and set “ EQUIP FLAG” if it is. Compare configuration with CMOS, store new configuration, beep the speaker, and display the following message is setup

changed.

Coprocessor (80287) configuration error”

***Check setup utility for correct settings if this message is displayed.

Test IE (H) 0001 1110 (B)

Check CMOS clock to see if it was initialized and is working. Enable timer interrupt. Sound beeper, and initialize if failure detected, then display one of the following messages on the console:

The Real Time Clock has not been initialized”

OR: Real Time Clock error”

***Check the RTC chip, M146818A at U201 if second message above is displayed.

Test IF (H) 0001 1111 (B)

Generate a new CMS checksum and save it in CMOS RAM. Call made to auto configuration program at this point. No error message generated.

Test 20 (H) Not Implemented Test 21 (H) 0010 0001 (B)

Initialize ROM drivers, including hard drive. Checksum generated, and all ROMS tested. System will now begin boot up. System speed is determined, 6 MHz, 8MHz or 12MHz. ***Refer to operations manual for opening screen display.

Tests 22, 23 Not Implemented

3-6

PC40-III SERVICE MANUAL

Test 24 (H) 0010 0100 (B)

Test operation of the RTC chip. Recheck battery, make sure clock is counting, test memory.

System will execute a halt instruction on memory failure. No error message is generated.

Test 25 (H) 0010 0101 (B)

Used in manufacturing to loop through diagnostics.

Test 26 (H) 0010 0110 (B)

Virutal memory test (over 1 megabyte). Call made to this routine from test 09. Display Message: “ Testing Extended RAM”

Display Message: “Total System RAM = XXXX” at finish. During this test the exception interrupt vector tables and descriptor tables are built, and moved from ROM to RAM. A test of address line 20 is made (controls real or virtual CPU mode). If not in virtual mode display following message:

“T est

_

26: Virtual Mode CPU error” And send F3 (H) (1111 0011 to parallel port. Then execute a halt instruction. Test address lines 19 through 23 are tested. Shutdown if error. Exception interrupt codes are moved to the parallel port prior

to shutdown. The following list defines the code sent to the port and the type of exception interupt ( EXECP INT ).

81

(H)

EXECP INT 01

Single Step

82

(H)

EXECP

INT 02

NMI

83

(H)

EXECP INT 03

Breakpoint

84

(H)

EXECP INT 04

Into Detect

85

(H)

EXECP

INT 05 Boundary

86

(H)

EXECP INT 06

Invalid OP Code

87

(H)

EXECP INT 07

—

88

(H)

EXECP INT 08 Double Exception

89

(H)

EXECP

INT 09 Processor Segment Error

8A

(H)

EXECP

INT 10

—

8B

(H)

EXECP

INT 11

Segment Not Present

8C

(H)

EXECP

INT 12

Stack Segment Not Present

8D

(H)

EXECP INT 13 General Protection Error

8E

(H)

EXECP INT 14

—

8F

(H)

EXECP INT 15

—

90

(H)

EXECP INT 16

Processor Extension Error Power on diagnostic program is finished at the time of boot up ( end of test 21 ). Note that during execution of “ POD” calls are made to auto configure and to miscellaneous interrupt routines. All error messages listed in appendix L of operations guide are listed in the overview above with the exception of the following

which are generated from the miscellaneous interrupt routines.

10 “ Parity error on main circuit board” 11 “Parity error on expansion bus” 12 “Non-recoverable error - Processor halted” 13 “Press FI key to continue”

Messages 10, 11 are generated after a parity error has been detected and a memory check has determined that it was on the main board, or the expansion bus. If the check finds the error the CPU is halted and message 12 is displayed. If no error is found after the check, message 13 is displayed and processing will continue.

3-7

PC40-III SERVICE MANUAL

SECTION 4

PARTS SECTION

PC40-III MAJOR PARTS LIST

Refer to Service Reference Diagram

1. Top Cover

312226-01

2. Spacer Plate

313011-01 Sub:-02

3.

Mounting Bracket 313066-02 Sub:-01

4. PBC Guide

251118-01

5. Main Chassis Base 312225-01

6. Foot 380128-01

7.

Bezel

312244-01

8. Keyswitch Assy. 313061-01

9. Plate Logo 380133-05

10.

Name Plate 316468-01

11. FD Hole Cover

312679-01

12. LED Power On

380016-01

13.

LED Hard Drive 380020-02

14.

Power Supply Assy 390269-02 (US)

15. Floppy Disk Drive

380825-02

16. Hard Disk Drive 313065-01

17.

Extension Card Panel 380120-01

18.

Keyboard Assy. 312709-01 (US/Canada)

19. 1352 Mouse Option -1352

20.

Floppy Drive Cable

380012-08

21.

Hard Drive Cable 312695-01

22. PCB Assy. 313055-01 Ground Cable (HD)

380811-01 (Not shown)

Power Cord

903508-15 (US) (Not shown)

PC40-III Service Manual 314134-01

1403 Monitor Service Manual 314882-01

PC40-III MAJOR PARTS LIST

Software Sub. Assy. (US) 315835-01

Includes

DOS 3.30A Manual 319293-01 Basis 3.22 Manual

319292-01

Operations Guide

319983-01

Disk Assembly

317768-01

PC40-III SERVICE MANUAL

Service Reference Diagram

4-1

PC40-III SERVICE MANUAL

COMPONENT PARTS LIST PCB ASSEMBLY #313055-01

Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore. Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips, Transistors, etc. are available in manual form through the Service Department, order #314000-01.

IC COMPONENTS

CRYSTAL, OSCILLATORS (Continued)

390300-04

80286 12 MHZ PROCESSOR

U301

900560-01 CRYSTAL, 32.768 KHZ

Y201

309316-01 FE3000A

U801

900556-13 CRYSTAL, 1.8 MHZ

Y601

390317-02 FE3010B U802

900558-01

CRYSTAL, 14.318 MHZ

Y801

390319-01 FE3020

U303

RESISTOR NETWORKS

390318-01 FE3030 U304

902441-11 150 OHM 6P, 5EL SIP

390302-01 PVGA-1A PARADISE VIDEO U101

RP1001

318091-01 PPC1, PRINTER INTERFACE U602

902442-06 68 OHM, 8PIN, 4 ELEMENT RP701,702

390304-03 390303-01

WD37C65, FLOPPY CONTROLLER IMS171, INMOS COLOR LOOKUP

TABLE

8250, SERIAL INTERFACE

U1001 U112

902422-03

902422-02

33 OHM, 8 PIN, 4 ELEMENT, SIL

IK OHM, 8 PIN, 4 ELEMENT, SIL

RP101-106,601,602, RP703,RP704 RP801

380205-01

U604

902441-31 4.7K 6 PIN, 5 ELEMENT, SIP RP107,201,304,604,

RN401

380259-01 M14818A RTC/CMOS RAM U201

902442-55 4.7K, 8 PIN, 7 ELEMENT, SIP

390341-01 8242 KEYBRD CONTROL U203

RP303,603,605

318087-01

MOS 5720, MOUSE-I/O CONTROL U601

902442-35

10K, 8 PIN, 7 ELEMENT, SIP

RP108

390307-02 PAL20L8 VGA DECODER #0 U114

902410-08 4.7K, 10 PIN, 9 ELEMENT, SIP

RP301.302

390335-02

PAL20L8 VGA DECODER #1

U115

902410-07

10K, 10 PIN, 9 ELEMENT, SIP

RP502,507

390308-01

PAL20L10 I/O DECODER U401

902441-15 330 OHM, 6 PIN, 5 ELEMENT, SIP RP508

390336-02

PAL20L10 HDC DECODER U905

RESISTORS 5% @ 1/4 WATT

390309-02

PAL16L8 DRAM DECODER U706

901550-39

CARBON FILM, 3.9K OHM R1203

390083-04

DRAM, 64 X 4 (256K BIT) @100NS

U118-U125

901550-64 CARBON FILM, 10 OHM

R503-R506.R210-R212

318099-02 DRAM, 256 X 4 (1 MEG BIT DRAM)

U707-U714

901550-63

CARBON FILM, 22 OHM R102,812

@ 100NS

901550-105

CARBON FILM, 33 OHM

R402,603,R 1206,609,

390337-02

EPROM 1, VGA BIOS - LOW (27128-15)

U108

701,813,410

390338-02

EPROM2, VGA BIOS - HIGH (27128-15) U109

901550-94 CARBON FILM, 68 OHM R114,1001,101,409,401,

390339-01 EPROM3, PC40 III BIOS - LOW U1101

R209

(21728-12)

901550-45 CARBON FILM, 75 OHM R801.R411

390340-01

EPROM4, PC40-III BIOS - HIGH

U1102

901550-124 CARBON FILM, 160 OHM

R1201

(27128-12)

901550-52 CARBON FILM, 220 OHM R804, R902, R507, R207

901521-02 74LS04

U206

901751-70

CARBON FILM, 210K OHM, 1%

R210

901521-30 74LS14 U501

901550-12 CARBON FILM, 22K OHM

R1202

901521-20

74LS125A

U205,U414

901550-58

CARBON FILM, 470 OHM R206,207

901521-63

74LS174

U113

901550-01 CARBON FILM, IK OHM R204,407,702,1204,412,

901521-13

74LS244

U102,U103,U107,U110,

502,508,1003,1004

U901,U902,U106

901550-49 CARBON FILM, 100 OHM

R115.R117

901521-46

74LS245

U104,U105,U502,U603

901550-18

CARBON FILM, 2.2K OHM

R604,R608

318066-01 74F00

U721.U807 901550-19 CARBON FILM, 4.7K OHM

R105,R404,R606,901,

390110-01

74F04

U413,U715,

R803,R1002,R904,806,

390203-01 74F08 U718,U719,U1201

R406,R509,R903,811

390313-01 74F10

U717

901550-03

CARBON FILM, 5.IK OHM

R805

390279-01 74F20

U1204

901550-20

CARBON FILM, 10K OHM

R202,R501 ,R605,905,

390077-01

74F32

U305

302,R113,R116

390080-01 74F138 U803,U1202 901550-84 CARBON FILM, 1M OHM

R203,R601 ,R602,R807,

390611-01 74F153

U403 205

390312-01 74F175

U404

901600-28 CARBON FILM, 2.2 OHM

R208,R610

390109-01

74F240

U704

901550-17

CARBON FILM, 1.2 OHM R1205

390314-01

74F253

U701 901550-110

CARBON FILM, 51 OHM

R403

390315-01

74F258

U702,U703

901550-92 CARBON FILM, 20K OHM

R301

390578-01

74F573

U705,U1205

901550-70 CARBON FILM, 300 OHM

R809 390089-01 390310-01 390579-01 901522-06 390359-01

74F245 74HCT74 74ALS244A 7406 74ACT00

U903,U904 U412,U411,U716 U402 U1002 U720

RESISTORS \°7o @ 1/4 WATT 901751-44

901751-61 901751-55 901751-38

CARBON FILM, 150 OHM CARBON FILM, 365 OHM CARBON FILM, 2K OHM CARBON FILM, 4.64K OHM

R107-R109,1005,1006

R110

R111 ,R 112

R104 390081-01

390323-01

74F74

4069

U405-U409.U410 U204

901751-62

CARBON FILM, 340 OHM

R106 318827-01

LM339

U116

RADIAL CERAMIC CAPACITORS 5% @ 50 VOLT

390322-01

LM10CN

U202

900019-13

RADIAL LEAD, 22pF C601.C402

390324-01

TL431

U117

900019-25

RADIAL LEAD, 27pF C202

901527-03 7905

VR501

900019-17

RADIAL LEAD, 47pF

C204,C205,C602,C803,

390364-01

74LS175

U1203

C804 901882-01

1488

U605

900020-04

RADIAL CERAMIC .0047uF

C201 901883-01

1489

U606

900019-15 RADIAL LEAD, lOOpF C603,C621-626,C514-

CRYSTAL, OSCILLATORS

900019-20 900019-21 900022-03

RADIAL LEAD, lOpF RADIAL LEAD, lOOOpF MONO., RAKIAL LEAD, .luF

C532

C401

C206,C627,C207

C203-CB102,CB115,

CB1011,CB1014,

CB2031 -2034.CB205,

CB206,CB3011 ,CB3012,

390273-01 325566-20 325566-18

OSCILLATOR, 48.00 MHZ OSCILLATOR, 36.00 MHZ OSCILLATOR, 25.175 MHZ

OSC401 OSC103 OSC102

315566-19

OSCILLATOR, 28.322 MHZ

OSC101

325566-17

OSCILLATOR, 9.6 MHZ

OSC1001

4-2

PC40-III SERVICE MANUAL

COMPONENT PARTS LIST

PCB ASSEMBLY #313055-01 (Continued)

RADIAL CERAMIC CAPACITORS- 5°7o @ 50 VOLT (Continued) 900022-03

900019-07 900022-05

900022-01

MONO., RAKIAL LEAD, .luF

(continued)

.047 UF MONO., RADIAL LEAD, .33uF

MONO., RADIAL LEAD, .22uF

CB302,CB3031-3039, CB3041 -3048,CB401-412 CB501 ,CB502,CB6011, CB6012.CB602-605, CB6051 ,CB6052,CB706, CB716,CB722,CB8011, CB8012,CB8021, CB8022,CB902,1001, CB901,CB905,116, CB1002,1121,CB1101, CB1102 C301,C101 CB118-125,707-714,403- 407,409^411.CB415, CB416,CB701-705,715, 717-721,803,CB903, 904,1201-1205,413, CB305

C511,CB126 ELECTROLYTIC CAPACITORS 390101-08

ELECT., ALUM., RADIAL, luF C507.C513 900402-01 CAP ELECT., TAN, lOuF C208 390101-01 ELECT., ALUM., RADIAL, 47uF C501-C506,C508-C510,

C512

390101-06 ELECT., ALUM., RADIAL lOuF

C1202 MISCELLANEOUS 251842-02 EMI FILTER 100PF EM1624-1631,1201

390257-01

EMI FILTER 22000PF EMI 1203

390297-03 EMI FILTER 2200PF

EMI201.202 390297-02 EMI FILTER MURRATA

DSS306-55Y5101M

EMI101-105

390275-04 EMI FILTER 150 PF EMI607-623 903025-08

FERRITE BEADS (AXIAL) FB403,404,101,1001,

FBI 03 903025-01

FERRITE BEADS (AXIAL)

FB104,601-608,405,102 390253-02 FERRITE BEADS THREE TURN

FB201-204 900850-01

DIODE 1N4148

CR201 ,CR202,CR501,

CR502,CR601-CR603

MISCELLANEOUS (Continued) 380393-01 BATTERY, NICAD 3.6V BT201.BT202

390280-01 FUSE, PICO, 4A FU601 390321-01 DELAY LINE 10 TAP @ 20 NS DL701 902658-01

TRANSISTOR 2N3904

Q601,Q801,Q1201

312680-01 PIEZO BEEPER QMB12

PZ801

251260-01

PUSH BUTTON N.O. SWITCH

PB501

904775-01

PIANO DIP SWITCH, I PIN, 4 POS.

SW101

904150-05 SOCKET, 28 PIN, DIP U108,U109,U1101,

U1102

904150-06

SOCKET, 40 PIN, DIP U302

390185-02

SOCKET, 68 PIN, PLCC

U301,U601

390185-01

SOCKET, 84 PIN, PLCC U303,304,801,802 390185-04 SOCKET, 100 PIN, PLCC U101 390242-01 D-SUB, 9 PIN, RT. ANGLE MALE CN601 390334-01

D-SUB, 15 PIN, RT. ANGLE FEMALE

CN101

390242-05

D-SUB, 25 PIN, RT. ANGLE MALE

CN603 390241-05 D-SUB, 25 PIN, TR. ANGLE FEMALE CN602 903446-25

EXPANSION CONNECTOR, 62 PIN CN501.CN503

903446-04

EXPANSION CONNECTOR, 36 PIN

CN505,CN507,CN502,

CN504,CN506,CN507 252166-03

DIN, TK PIN, ROUND, FEMALE CN201

252122-01

JACK, RCA RT. ANGLE, FEMALE

CN1201 903326-03

HEADER, 3 PIN, SIL CB902, JMP904,CN512,

CN202 903326-02 HEADER, 2 PIN, SIL

JMP 903 (REMOVE

PINS 3,20)

903345-17 HEADER, 34 PIN, DIL CN1001 903345-20

HEADER, 40 PIN, DIL CN901

903349-01 POWER CONNECTOR, 6 PIN.

CN509

390043-01 SHORTING BLOCKS, 2 POS. SEE 8 OF 8 390186-01 JUMPER

R810, R213, R103

SUBSTITUTE PARTS 390317-01

IC, FE3010A

U802 SUB:

390304-01

IC, WD37C65 U1001 SUB:

390304-02 IC, WD37C65A U1001 SUB:

4-3

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PCB Assembly #313055-01, Rev. 5

4^

PC40-III SERVICE MANUAL

MOUSE PORT

CmOl (5mm)

Pin No.

1

2

3 4

5

6

7

8

9

Signal

Vertical Horizontal Vertical Q Horizontal Q Button (3) Button (1)

+ 5V

Ground Button (2)

VIDEO PORT

CS101 (3/16")

5 4 3 2 1

m t t

15 14 13 12 11

Pin Function

1. Red Video

2. Green Video

3. Blue Video

4. Monitor ID Bit 2 (not used)

5. ground

6. Red Return (ground)

7. Green Return (ground)

8. Blue Return (ground)

9. Key (no pin)

10. Sync Return (ground)

11. Monitor ID Bit 0 (not used)

12. Monitor ID Bit 1 (not used)

13. Horizontal Sync

14. Vertical Sync

15. not used

SERIAL PORT

CJS603 (5mm)

> > > > > > > > > > > / >

> > > » » » > »

PARALLEL PORT

CIS602 (5mm)

Computer

Side

Peripheral

Side

Computer

Side

Printer

Side

1

2

3 4 5

6

7

8

9

10

20

22

CHASSIS GROUND T xD

--------------------

R xD

--------------------

RTS

------------------------

CTS

------------------------

DSR

------------------------

SIG GND

-----------------

DCD

------------------------

+ 12V

------------------

-1 2 V

--------------------

DTR------------------------

Rl

---------------------------

1 —

2 —

3 — 4 — 5 —

6 —

7 —

8 —

9 —

l O -

11 —

12

—

13 — 14 — 15 — 16 — 17 — 18-25

STROBE

-----

DO

------------

D1

------------

D2

------------

D3

------------

D4

------------

D5

------------

D6

------------

D7

------------

ACK

------------ B US Y --------- PE

------------ SLCT --------- AUTO FDXT

ERROR

-----

IN IT

------------ SLCT IN

-----

GND

------------

4-5

EXPANSION PARALLEL SERIAL VIDEO MOUSE

PC40-III MAJOR ICs AND CONNECTORS

4^

On

PC40-III SERVICE MANUAL

SECTION 5

• IC PINOUTS

• SCHEMATICS

INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY. COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR

OEM ASSEMBLIES.

PC40-III SERVICE MANUAL

IC PIN OUTS & SIGNAL DESCRIPTIONS

1)

80286 CPU

390300-01

2)

FE3000A

CPU CNTRL

390316-01

3)

FE3010B PERP CNTRL 390317-02

4)

FE3020

ADDR BUFFER

390319-01

5)

FE3030

DATA BUFFER

390318-01

6)

P VGA-1 A

PARADISE VIDEO

390302-01

7)

PPC1

PRINTER INTERFACE 318091-01

8)

WD37C65 FDC 390304-03

9)

8250

SERIAL INTERFACE

380205-01

10)

5720

MOUSE CONTROL 318087-01

5-1

PC40-III SERVICE MANUAL

1) 80286 CPU 390300-01

Component Pad Views—As viewed from underside of component when mounted on the board.

P.C. Board Views—As viewed from the component side of the P.C. board.

0 0 0 0 0 0 0 0 0 0 0 0

C? Q <

PIN NO 1 M ARK

u bJi ij Lij yii Ji i jai i jM QayH y

u IS IS 15 s s K i

___________

I

SYMBOL

CLK

D15-D0

A23-A0

BHE

si, 55

TYPE NAME AND FUNCTION

I SYSTEM CLOCK provides the fundamental timing for 80286 systems. It is divided by two inside the 80286 to generate the processor clock. The internal

divide-by-two circuitry can be synchronized to an external clock generator by a LOW to HIGH transition on the RESET input.

I/O DATA BUS inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data during memory and I/O write cycles. The data bus is

active HIGH and floats to 3-state OFF during bus hold acknowledge.

O ADDRESS BUS outputs physical memory and I/O port addresses. A0 is LOW when data is to be transferred on pins D7-0. A23-A16 are LOW during

I/O transfers. The address bus is active HIGH and floats to 3-state OFF during bus hold acknowledge.

O BUS HIGH ENABLE indicates transfer or data on the upper byte of the data bus. D15-8. Eight-bit oriented devices assigned to the upper byte of the data

bus would normally use BHE to condition chip select functions. BHE is active LOW and floats to 3-state OFF during bus hold acknowledge.

BHE and A0 Encodings

BHE Value A0 Value Function

0 0 Word transfer 0 1 Byte transfer on upper half of data bus (D15-8)

1 0 Byte transfer on lower half of data bus (D7-0) 1 1 Will never occur

__

_____

O BUS CYCLE STATUS indicates initiation of a bus cycle and, along with M/IO and COD/INTA, defines the type of bus cycle. The bus is in a Ts state

whenever one or both are LOW, 5! and 53 are active LOW and float to 3-state OFF during bus hold acknowledge.

_____

80286 Bus Cycle Status Definition

COD/INTA M/m 51 53 Bus Cycle Initiated 0 (LOW) 0 0 0 Interrupt acknowledge 0 0 0 1 Will not occur 0 0 1 0 Will not occur 0 0 1 1 None; not a status cycle 0 1 0 0 IF A1 = 1 then halt; else shutdown 0 1 0 1 Memory data read 0 1 1 0 Memory data write 0 1 1 1 None; not a status cycle

(HIGH) 0 0 0 Will not occur

0 0 1 I/O read 0 1 0 I/O write 0 1 1 None; not a status cycle

1 0 0

1 0 1 1 1 0

Will not occur Memory instruction read Will not occur None; not a status cycle

5-2

PC40-III SERVICE MANUAL

SYMBOL

M/IO

COD/lNTA

LOCK

READY

HOLD HLDA

INTR

NMI

PEREQ PEACK

BUSY

ERROR

RESET

Vss Vcc

CAP

TYPE SA ME AMD FUNCTION

O MEMORY I/O SELECT distinguishes memory access from I/O access, if HIGH during Ts, a memory cycle or a halt/shutdown cycle is in progress. It

LOW, an I/O cycle or an interrupt acknowledge cycle is in progress. M/IO floats to 3-state OFF during bus hold acknowledge.

O CODE/INTERRUPT ACKNOWLEDGE distinguishes instruction fetch cycles from memory data read cycles. Also distinguishes interrupt acknowledge cycles

from .I/O cycles. COD/INTA floats to 3-state OFF during bus hold acknowledge. Its timing is the same as M/IO.

_____

0 BUS LOCK indicates that other system bus masters are not to gain control of the system bus for the current and the following bus cycle. The LOCK signal

may be activated explicitly by the “LOCK” instruction prefix or automatically by 80286 hardware during memory XCHG instructions, interrupt acknowledge, or descriptor table access. LOCK is active LOW and floats to 3-state OFF during bus hold acknowledge.

_______

1 BUS READY terminates a bus cycle. Bus cycles are extended without limit until terminated by READY LOW. READY is an active LOW synchronous input re

quiring setup and hold times relative to the system clock be met for correct operation. READY is ignored during bus hold acknowledge.

I BUS HOLD REQUEST AND HOLD ACKNOWLEDGE control ownership of the 80286 local bus. The HOLD input allows another local bus master to

0 request control of the local bus. When control is granted, 80286 will float its bus drivers to 3-state OFF and then activate HLDA, thus entering the bus

hold acknowledge condition. The local bus will remain granted to the requesting master until HOLD becomes inactive which results in the 80286 deactivating HLDA and regaining control of the local bus. This terminates the bus hold acknowledge condition. HOLD may be asynchronous to the system clock. These signals are active HIGH.

1 INTERRUPT REQUEST requests the 80286 to suspend its current program execution and service a pending external request. Interrupt requests are masked

whenever the interrupt enable bit in the flag word is cleared. When the 80286 responds to an interrupt request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt vector that identifies the source of the interrupt. To assure program interruption, INTR must remain active until the first interrupt acknowledge cycle is completed. INTR is sampled at the beginning of each processor cycle and must be active HIGH at least two processor cycles

before the current instruction ends in order to interrupt before the next instruction. INTR is level sensitive, active HIGH, and may be asynchronous to the system clock.

I NON-MASKABLE INTERRUPT REQUEST interrupts the 80286 with an internally supplied vector value of 2. No interrupt acknowledge cycles are performed.

The interrupt enable bit in the 80286 flag word does not affect this input. The NMI input is active HIGH, may be asynchronous to the system clock, and

is edge triggered after internal synchronization. For proper recognition, the input must have been previously LOW for at least four system clock cycles and remain HIGH for at least four system clock cycles. PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE extend the memory management and protection capabilities of the 80286 to processor extensions. The PEREQ input requests the 80286 to perform a data operand transfer for a processor extension. The PEACK output signals the pro cessor extension when the requested operand is being transferred. PEREQ is active HIGH and floats to 3-state OFF during bus hold acknowledge. PEACK may be asynchronous to the system clock. PEACK is active LOW.

_____ I PROCESSOR EXTENSION BUSY AND ERROR indicate the operating condition of a processor extension to the 80286. An active BUSY input stops 80286 pro- I gram execution on WAIT and some ESC instructions until BUSY becomes inactive (HIGH). The 80286 may be interrupted while waiting for BUSY to become in

come inactive. An active ERROR input causes the 80286 to perform a processor extension interrupt when executing WAIT or some ESC instructions. These inputs are active LOW and may be asynchronous to the system clock. These inputs have internal pull-up resistors.

I SYSTEM RESET clears the internal logic of the 80286 and is active HIGH. The 80286 may be reinitialized at any time with a LOW to HIGH transition

on RESET which remains active for more than 16 system clock cycles. During RESET active, the output pins of the 80286 enter the state shown below:

80286 Pin State During Reset

Pin Value Pin Names 1 (HIGH) SO, SI, PEACK, A23-A0, BHE, LOCK 0 (LOW) M/IU, COD/INTA, HLDA (Note 1) 3-state OFF D15-D0 Operation of the 80286 begins after a HIGH to LOW transition on RESET. The HIGH to LOW transition of RESET must be synchronous to the system clock. Approximately 38 CLK cycles from the trailing edge of RESET are requried by the 80286 for internal initialization before the first bus cycle, to fetch code from the power-on execution address, occurs. A LOW to HIGH transition of RESET synchronous to the system clock will end a processor cycle at the second HIGH to LOW transition of the system clock. The LOW to HIGH transition of RESET may be asynchronous to the system clock; however, in this case it cannot be predetermined which phase of the processor clock will occur during the next system clock period. Synchronous LOW to HIGH transitions of RESET are required only for systems where the processor clock must be phase synchronous to another clock.

I SYSTEM GROUND: 0 Volts. I SYSTEM POWER: +5 Volt Power Supply. I SUBSTRATE FILTER CAPACITOR: a 0.047 /zF ± 20% 12V capacitor must be connected between this pin and ground. This capacitor filters the output

of the internal substrate bias generator. A maximum DC leakage current of 1 /xA is allowed through the capacitor. For correct operation of the 80286, the substrate bias generator must charge this capacitor to its operating voltage. The capacitor chargeup time is 5 milliseconds (max.) after Vcc and CLK reach their specified AC and DC parameters. RESET may be applied to prevent spurious activity by the CPU during this time. After this time, the 80286 processor clock can be synchronized to another clock by pulsing RESET LOW synchronous to the system clock.

I

O

NOTE: HLDA is only Low if HOLD is inactive (Low).

5-3

PC40-III SERVICE MANUAL

2) FE3000A CPU CNTRL 390316-01

S53 I s ls s l^ g a ls - g i g i a uu c s < < zz z z z > xc x > o o < z z o

j S , a O ** j j ^ f l< zz ^u SHSS uuQ a.uu u i > > xg “«i5:5zZN

BuOft-OS O Q ~ OS Z 2 ~ Z ffl

>'■£'■£ DSZZ zzflwzflz z

s> os os a. z >*J

F14M F119M HLDA1 NENDCY XD7 XA3

SI

SO RC OUT1 NZROWS NENFAST NRESIN NRAMSL NNMICS

■ NIOS16

■NIOCHK

•NERROR

■UNUSED

■ IOCHCK

■ LSAO

TYPE SYMBOL FUNCTION

18

1

ENPAL2 ENABLE EXTERNAL WAIT STATE

Active high — Disables external wait state generator.

19

I

F16 16 BIT MEMORY OPERATION

Active high — Indicates that the current memory cycle

20 I

HLDA

HOLD ACKNOWLEDGE FROM THE 80286 Active high — Indicates that the 80286 has released the bus in response to a CPUHRQ signal.

21 I HRQ1 HOLD REQUEST

Active high — Bus request from a DMA controller.

22

I IOCRDY

EXPANSION BUS READY Active high — Signal from the expansion bus to in dicate that the current cycle may complete.

23

I

MDPINO PARITY BIT FROM RAM BANK 0

Parity bit from on board RAM bits 0-7.

24 I MDPIN1

PARITY BIT FROM RAM BANK 1 Parity bit from on board RAM bits 8-15.

25 I

MNIO

MEMORY I/O SELECT Active high — Signal from the 80286 indicating the next cycle is a memory cycle.

26 I NAEN1

ENABLE DMA CHANNELS 0-3 TO USE DATA BUS Active low

27

I NAEN2 ENABLE DMA CHANNELS 5-7 TO USE DATA

BUS

Active low

28 I NBUSY

BUSY STATUS ASSERTED BY 80287

Active low

29

I NCS287 80287 I/O CHIP DECODE

Active low

30 O

NIRQ13

INTERRUPT REQUEST 13

Active low — Co-processor error

TYPE

SYMBOL FUNCTION

1

vss

GROUND

2

I/O

NXBHE BUS HIGH ENABLE

Active low — Indicates the current bus cycle will transfer a byte on the upper byte.

3 I/O

NYIOR

I/O READ COMMAND Active low — Indicates a read of an I/O device.

4

I/O

NYIOW

I/O WRITE COMMAND Active low — Indicates a write of an I/O device.

5

I/O

NYMEMR MEMORY READ COMMAND

Active low — Indicates a read of memory.

6

I/O

NYMEMW

MEMORY WRITE COMMAND Active low — Indicates a write of memory.

7

O

AIOW

EXTENDED I/O WRITE COMMAND Active high — Used for external wait state generator.

8

O AS

REAL TIME CLOCK ALE Active high — Used to latch the address in the clock calender chip (Motorola 146818)

9

O

BALE

BUS ADDRESS LATCH ENABLE Active high — Or of ALE and HLDA.

10

O

CPUHRQ

BUS HOLD REQUEST TO 80286 Active high — Bus request to 80286 CPU caused by refresh or a DMA cycle.

11

O

CTLOFF

DATA LATCH CONTROL Active high — Latch data bits 0-7 of first bus cycle of a word transfer on a byte device.

12 O

DMARDY

READY TO DMA Active high — Indicates that the DMA may com plete its cycle.

13 O DMACLK

CLOCK TO DMA DEVICES Clock in sync with and half the frequency of the SYSCLK (ie: 3, 4, or 5 MHz)

14

1

A0

80286 ADDRESS A0 Active high — Address bit 0 from the 80286.

15

1

A1

80286 ADDRESS A1 Active high — Address bit 1 from the 80286.

16

1

EAIOCK

ENABLE I/O CHECK Active high — Enable error signal from the expan sion bus.

17

I EMBRMCK

ENABLE RAM PARITY CHECK CONTROL Active high — Enable parity check from on board

31

1

NDMAMR

DMA MEMORY READ COMMAND Active low — Memory read command from a DMA

controller

32

O RST287 RESET TO 80287

Active high

33 O SYSCLK SYSTEM CLOCK

System clock in phase with and half the frequency of the PROCLK. (ie: 6, 8, or 10MHz)

34

o RESCPU RESET TO 80286

Active high — Reset to CPU from a command to

exit protected mode or an external reset.

35

0

REFDET

REFRESH DETECT Signal that toggles each time there is a refresh cycle to the RAM.

36 o

Ql

START OF BUS CYCLE. Active high — Indicates start of a bus cycle to the external wait state generator.

37

o

PCK

PARITY CHECK Active high — Indicates a RAM parity error has been detected.

38

o PCLK

CLOCK TO 8042

39

0 PROCLK

PROCESSOR CLOCK TO 80286 Clock twice the processor speed, (ie: 12, 16, or 20 MHz)

40

o

NPCLK

INVERTED CLOCK TO 8042

41

I/O NRFSH

REFRESH CYCLE Active low — Indicates the current bus cycle is a RAM refresh cycle.

42

VSS

GROUND

43

VDD

+ 5 VOLTS SUPPLY

44

I/O XA0 ADDRESS A0

Active high — System address bit 0

45 0 NDEN0

GATE DATA 0-7 Active low

46 o

NDEN1 GATE DATA 8-15

Active low

47

o

DIR245 BYTE SWAP DIRECTION

Signal to control byte swap direction on a 16 bit transfer on a 8 bit device.

48 o NERFSH

ENABLE REFRESH ADDRESS Active low — Signal to enable the refresh address to the address bus during a RAM refresh cycle.

49 o NNPCS

80287 CHIP SELECT

RAM.

Active low

5-4

PC40-III SERVICE MANUAL

TYPE

SYMBOL

FUNCTION

50 O

NEDMMR

ENABLE DMA MEMORY READ

Active low — Gates a memory read to the bus dur

ing a DMA cycle.

51 O

NINTA

INTERRUPT ACKNOWLEDGE

Active low — Interrupt acknowledge to the inter

rupt controllers.

52 O

NNM1

NMI OUTPUT TO 80286

Active low — Non-maskable interrupt to 80286.

53 O

NBZ286

80287 BUSY TO 80286

Active low

54 O

LSAO LATCHED SYSTEM ADDRESS A0

Active high — System address bit 0 during a CPU

bus cycle.

55 O IOCHCK I/O DEVICE ERROR

Active high — Indicates an error from the expan

sion bus.

56 UNUSED UNUSED

Must be left open

57

I NERROR

80287 ERROR

Active low — Error from the 80287.

58

I NIOCHK I/O CHECK

Active low — Error signal from the expansion bus.

59

I

NIOS16

16 BIT I/O TRANSFER

Active low — Signal from the expansion bus to in

dicate that the current bus cycle is a 16 bit I/O

transfer.

60 I

NNMICS

NMI PORT DECODE

Active low — Decode of NMI enable port.

61 I

NRAMSL ON BOARD RAM DECODE

Active low

62

I

NRESIN RESET IN

Active low — External reset in used to generate a

system reset.

63 I

NENFAST ENABLE LOOK AHEAD DECODE

Active low — Causes early eneration of memory

read and write signals with zero wait states.

64 I NZROWS ZERO WAIT STATES

Active low — Indicates the current bus cycle should

have no wait states.

65 I

OUT1 TERMINAL COUNT OF TIMER CHANNEL 1

Active high — Terminal count from timer channel

1. RESET TO CPU 80286 Active high — Input to generate RESET to CPU.

66 I RC

67 I SO BUS CYCLE STATUS SO FROM 80286 68

I

SI

BUS CYCLE STATUS SI FROM 80286

69

I

XA3 ADDRESS A3

Active high — System address bit 3

70 I

XD7 SYSTEM DATA BUS BIT 7

Active high

71

I

NENDCY TERMINATE CURRENT CYCLE

Active low — Signal from external wait state generator to end the current bus cycle.

72

O

HLDA1

HOLD ACKNOWLEDGE TO DMA Active high — Hold acknowledge to one of DMA

controllers.

73

o

F119M

1.19 MHz CLOCK TO TIMER

74

o

F14M

14.318 MHz SIGNAL TO EXPANSION BUS

75

o

GTE245

ENABLE BUS SWAP Active low — Gates data during the swap of a byte on a 16 bit transfer on a 8 bit device.

76 o

NRESET RESET TO SYSTEM LOGIC

Active low

77

o

NREADY

SYNCHRONIZED READY TO CPU Active low — Ready to CPU indicating that the current bus cycle may terminate.

78

I

X18284

CRYSTAL TO 8284 CLOCK GENERATOR

79

o

X28284

CRYSTAL TO 8284 CLOCK GENERATOR

80 I

X1284

CRYSTAL TO 82284 CLOCK GENERATOR

81 o

X2284

CRYSTAL TO 82284 CLOCK GENERATOR

82

o

DTNR

DATA DIRECTION CONTROL Active low — A low indicates a bus read cycle.

83 o

ALE

ADDRESS LATCH ENABLE Active high — Signal to latch the address from the

80286.

84 VDD

+ 5 VOLTS SUPPLY

5-5

PC40-III SERVICE MANUAL

3) FE3010A (B) PERP. CNTRL 390317-02 (-02)

Q ^ fit U

%<<<<<<<<<

O'O 'O'O'

SJ<<<<<<c<^aSS22>acacofioc

QIQQQQQQQQ>>ZZZZ^QQQQ

— — 9eoo9caooor~i-~r~r~i-

DM ACLK-----------

12

74

----------

DRQ5

NM ASTER----------- 13

73

----------

DRQ6

k b in t ----------- 14

72

----------

DRQ7

IR Q 3----------- 15

71

----------

AEN

1RQ4-----------

16

70

----------

TC

IR Q 5----------- 17

69

----------

HRQ

IR Q 6----------- 18

68

----------

NDACKEN

IR Q 7

----------

19

67

----------

DACK0

IN T R

----------

20

66

----------

DACK1

OUT 1

----------

21

65

----------

DACK2

VS S

----------

22 FE3010A FARADAY 64

----------

VSS

TC L K

----------

23

63

----------

NCLEAR

SP K R

----------

24

62

----------

NIRQ13

NIRQ 8

----------

25

61

----------

IRQ14

IR Q 9

----------

26

60

----------

1RQ15

IRQ10

----------

27

59

----------

NINTA

IRQ11

----------

28

58

----------

NRTCCS

IRQ12

----------

29

57

----------

ALE

AL(0 )

----------

30

56

----------

NRFSH

AL(1 )

----------

31

55

----------

AH(13)

AL(2 )

----------

32 54

rr)rr)rr>rr)rr,rr)rri-*tTTTrTT-&Tr-$TT-*titir>ir>inirt

----------

AH(12)

<< << << <<<

<<<<<<<<•*

28

29

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

I

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

o o

o o o o o o o o

IRQ10

IRQ11

IRQ12

AL(0)

AL(1) AL(2) AL(3) AL(4) AL(5)

AL(6)

AL(7) AL(8)

AL(9) AH(0) AH(1)

vss

VDD AH(2) AH(3) AH(4) AH(5) AH(6) AH(7) AH(8) AH(9)

AH(10) AH(ll) AH(12) AH(13)

INTERRUPT REQUEST 10 Active high INTERRUPT REQUEST 11 Active high INTERRUPT REQUEST 12 Active high ADDRESS BIT 0 ADDRESS BIT 1 ADDRESS BIT 2 ADDRESS BIT 3 ADDRESS BIT 4 ADDRESS BIT 5 ADDRESS BIT 6 ADDRESS BIT 7 ADDRESS BIT 8 ADDRESS BIT 9 ADDRESS BIT 10 ADDRESS BIT 11 GROUND

+ 5 VOLTS SUPPLY ADDRESS BIT 12 ADDRESS BIT 13 ADDRESS BIT 14 ADDRESS BIT 15 ADDRESS BIT 16 ADDRESS BIT 17 ADDRESS BIT 18 ADDRESS BIT 19 ADDRESS BIT 20 ADDRESS BIT 21 ADDRESS BIT 22 ADDRESS BIT 23

PIN TYPE

SYMBOL

FUNCTION 56

I

NRFSH REFRESH ADDRESS

1

VSS GROUND

Active low — Signal to enable the refresh to the ad

2

I/O

DATA(0) DATA BIT 0

dress bus during a RAM refresh cycle.

3

I/O DATA(l) DATA BIT 1 57

I

ALE

ADDRESS LATCH ENABLE

4

I/O DATA(2) DATA BIT 2

Active high

5

I/O DATA(3) DATA BIT 3

58 O NRTCCS REAL TIME CLOCK CHIP SELECT

6

I/O DATA(4) DATA BIT 4

Active low

7

I/O DATA(5) DATA BIT 5

59

I

NINTA INTERRUPT ACKNOWLEDGE FROM CPU

8 I/O

DATA(6) DATA BIT 6 (80286)

9

I/O DATA(7) DATA BIT 7 Active low — Interrupt acknowledge to the inter

10 I

HLDA

HOLD ACKNOWLEDGE rupt controllers. Active high — Acknowledge from the CPU (80286)

60 I IRQ15 INTERRUPT REQUEST 15

for a request for the bus from the DMA controller. Active high

11 I

DMARDY DMA READY

61

I

IRQ14 INTERRUPT REQUEST 14 Active high — Signal to indicates that DMA may Active high complete its current cycle.

62

I

NIRQ13

INTERRUPT REQUEST 13

12

I DMACLK DMA CLOCK Active low — Error interrupt from (80287).

System Clock DMACLK 63

I

NCLEAR SYSTEM CLEAR

6 MHz 8 MHz

10 MHz

3 or 6 MHz 4 or 8 MHz 5 MHz

64 65

VSS

DACK2

13

1

NMASTER

BUS MASTER Active low — Signal to indicate that a master on the expansion bus has control of the bus.

14

I

KBINT

KEYBOARD INTERRUPT Active high

15

I

IRQ3

INTERRUPT REQUEST 3 Active high

16

1

IRQ4

INTERRUPT REQUEST 4 Active high

17

1

IRQ5 INTERRUPT REQUEST 5

Active high

18

1

IRQ6

INTERRUPT REQUEST 6 Active high

19

I IRQ7

INTERRUPT REQUEST 7

20

O INTR

INTERRUPT REQUEST TO CPU (80286) Active high

21

O OUT 1

TIMER CHANNEL 1 OUTPUT

22

VSS GROUND

23

1

TCLK

TIMER CLOCK (1.19 MHz clock for timer)

24

o SPKR

SPEAKER

25

I

NIRQ8

INTERRUPT REQUEST 8 Active low

26

1

IRQ9

INTERRUPT RQUEST 9 Active high

Active low GROUND DMA ACKNOWLEDGE BIT 2

DACK2 DACK1 DACK0

DMA Channel

Acknowledge

2 3

Illegal

6 7

66 O DACK1

DMA ACKNOWLEDGE BIT 1

67

O DACK0

DMA ACKNOWLEDGE BIT 0

68

o

NDACKEN

DMA ACKNOWLEDGE ENABLE Active low — Signal to enable DACK0, DACK1, and DACK2 decodes.

69

o HRQ DMA REQUEST TO CUP (80286)

Active high

70 o

TO DMA END OF OPERATION

Active high — Signal to indicate the DMA con troller has finished its cycle.

71 o

AEN DMA AEN

Active high — Signal to indicate that the current bus is a DMA cycle.

72 I DRQ7

CHANNEL 7 DMA REQUEST Active high

5-6

TYPE SYMBOL

73 I DRQ6

74 I

75 I

76 I

77 I DRQ1 CHANNEL 1 DMA REQUEST

78 I

79 O

80 I/O NIOR

81 I/O

82 83 o

84 VDD

DRQ5 CHANNEL 5 DMA REQUEST

DRQ3 CHANNEL 3 REQUEST

DRQ2 CHANNEL 2 DMA REQUEST

DRQO

SYSALE

NIOW

NMEMR

o

NMEMW

FUNCTION

CHANNEL 6 DMA REQUEST Active high

Active high

Active high CHANNEL 0 DMA REQUEST Active high SYSTEM ALE Active high — Signal to latch the address in the ad dress latch. I/O READ COMMAND Active low I/O WRITE COMMAND Active low MEMORY READ COMMAND Active low MEMORY WRITE COMMAND Active low

+ 5 VOLTS SUPPPLY

PC40-III SERVICE MANUAL

5-7

PC40-III SERVICE MANUAL

4) FE3020 ADDR BUFFER 390319-01

_i at

VCC2

GDD2

A3 ADD14 ADD13

N.C.

A4

A5

A16

ADD12

VCC3

GDD3 ADD11 ADD10

A17 ADD9 ADD8

A18

A19 GDD4

VCC4

VCC8 GDD8 A15 A14 A13 A12 LA20 NYMEMW NRAMCS NMASTER NGTMEMR NBHE LASO HLDA ADSTB A 23 A22 NMEMR NEBHE GDD7 VCC7

80

I/O NABHE

FE3000 BUS BYTE HIGH ENABLE Active low — Indicates a transfer of data on the upper byte of the data bus.

81

O NPROMSEL

PROM SELECT Active low — BIOS PROM select

79

o MEM245

DIR

MEMORY BUFFER DIRECTION Direction control for the on board memory buffers.

62

I LASO

FE3000 ADDRESS BIT 0

3 I/O ADR(0)

FE3000/FE3010 ADDRESS BIT 0

4

I/O A1

80286/FE3010 ADDRESS BIT

1

8 I/O A2

80286/FE3010 ADDRESS BIT

2

14

I/O A3 80286/FE3010 ADDRESS BIT

3

18 I/O

A4

80286/FE3010 ADDRESS BIT

4

19 I/O A5

80286/FE3010 ADDRESS BIT

5

38

I/O

A6 80286/FE3010 ADDRESS BIT

6

44

I/O

A7

80286/FE3010 ADDRESS BIT 7

45 I/O A8 80286/FE3010 ADDRESS BIT

8

46 I/O A9

80286/FE3010 ADDRESS BIT 9

52 I/O A10

80286/FE3010 ADDRESS BIT 10

53

I/O

A ll

80286/FE3010 ADDRESS BIT 11

69

I/O A12 80286/FE3010 ADDRESS BIT 12

70 I/O

A13 80286/FE3010 ADDRESS BIT 13

71 I/O A14

80286/FE3010 ADDRESS BIT

14

72

I/O

A15 80286/FE3010 ADDRESS BIT 15

20

I/O A16 80286/FE3010 ADDRESS BIT 16

26 I/O

A17

80286/FE3010 ADDRESS BIT

17

29

I/O A18 80286/FE3010 ADDRESS BIT

18

30

I/O

A19

80286/FE3010 ADDRESS BIT 19

37

I/O A20

80286 ADDRESS BIT 20

68 I/O LA20 FE3010 ADDRESS BIT 20

2

I/O

A20GT

8042 GATE ADDRESS

- 0 0 0 2 gQQO<

<uooo 2<<<UflQ OQ;;

UOOO* yo o oo <<

Active high — ENable address

% << <

> o < <

43

I

A21

80286/FE3010 ADDRESS BIT 58 I A22 80286/FE3010 ADDRESS BIT 59 I

A23 80286/FE3010 ADDRESS BIT

51 I/O ADDO AT BUS ADDRESS BIT 0

PIN TYPE

SYMBOL FUNCTION

50 I/O ADD1 AT BUS ADDRESS BIT 1

65 I

NMASTER

MASTER

49

I/O ADD2 AT BUS ADDRESS BIT 2

Active low — Signal from the AT bus which allows

42

I/O ADD3 AT BUS ADDRESS BIT 3

the bus master to control the bus.

41 I/O ADD4 AT BUS ADDRESS BIT 4

61

I

HLDA

HOLD ACKNOWLEDGE

36 I/O ADDS AT BUS ADDRESS BIT 5

Active high — Signal from the 80286 to indicate

35 I/O ADD6 AT BUS ADDRESS BIT 6

that the bus has been released in response to a CPU

34

I/O

ADD7

AT BUS ADDRESS BIT 7

HRQ signal.

28 I/O ADD8 AT BUS ADDRESS BIT 8

62

I

ADSTB ADDRESS STROBE

27

I/O

ADD9

AT BUS ADDRESS BIT 9

Active high — Signal from the FE3010 that latches

25

I/O

ADD10

AT BUS ADDRESS BIT 10

the address.

24

I/O

ADD11

AT BUS ADDRESS BIT 11

63

I

NRAMCS

RAM CHIP SELECT

21 I/O ADD12 AT BUS ADDRESS BIT 12

Active low — On board RAM chip select.

16 I/O ADD13 AT BUS ADDRESS BIT 13

64

I/O

NYMEMW

MEMORY WRITE COMMAND

15 I/O

ADD14 AT BUS ADDRESS BIT 14

Active low — Signal to indicate a write of memory

11

I/O ADD15

AT BUS ADDRESS BIT 15

during a CPU, DMA, or Master cycle.

10

I/O

ADD16

AT BUS ADDRESS BIT 16

82

I/O

NYMEMR

MEMORY READ COMMAND

9 I/O ADD17 AT BUS ADDRESS BIT 17

Active low — Signal to indicate a read of memory

5 I/O ADD18 AT BUS ADDRESS BIT 18

during a CPU or Master cycle.

1 I/O ADD19

AT BUS ADDRESS BIT 19

64

I

NGTMEMR

GATE MEMORY READ

17

N/C

Active low — Signal to indicate a read memory dur

6

VCC1

5V ± 5%

ing a DMA cycle.

12

VCC2

5V ± 5%

76

I/O

NMEMW

AT BUS MEMORY WRITE COMMAND

22

VCC3 5V ± 5%

Active low — Signal to indicate a write of memory

32

VCC4 5V ± 5%

during a CPU, DMA, or Master cycle.

39

VCC5

5V ± 5%

57 I/O

NMEMR

AT BUS MEMORY WRITE COMMAND

47

VCC6 5V ± 5<7o

Active low — Signal to indicate a read of memory

54 VCC7

5V ± 5 °7o

during a CPU, DMA, or Master cycle.

74

VCC8 5V ± 5%

78 o

NSMEMW

PC BUS MEMORY WRITE COMMAND

84

VCC9

5V ± 5<7o

Active low — Signal to indicate a write of memory

7

GDD1

GROUND

below 1MB during a CPU, DMA, or Master cycle.

13 GDD2

GROUND

77

o

NSMEMR

PC BUS MEMORY READ COMMAND

2

GDD3

GROUND

Active low — Signal to indicate a read of memory

31

GDD4

GROUND

below 1 MB during a CPU, DMA, or Master cycle.

33

GDD11 GROUND

56

I/O

NEBHE AT BUS BYTE HIGH ENABLE

40

GDD5 GROUND

Active low — Indicates a transfer of data on the

48

GDD6 GROUND

upper byte of the data bus.

55

GDD7 GROUND

63 I

NBHE

80386 BUS BYTE HIGH ENABLE

73

GDD8 GROUND

Active low — Indicates a transfer of data on the

75

GDD9 GROUND

upper byte of the data bus.

83

GDD10 GROUND

bit 20

21

22 23

5-8

PC40-III SERVICE MANUAL

5) FE3030 DATA BUFFER 390318-01

HHHhflUK2hh22<<<<<<<CO QQQQO>UUZZZZUUUUUUUUO

58

I/O

NC245EN

NYIOW

VC C2-----------

12

— — evocr~'OU'>Tt, r')<N — aco cocooacr^r~ r~r~i"'

74

GD D2-----------

13

73

DA TA 4-----------

14

72

DA TA 5----------- 15

71

DA TA 6-----------

16

70

DA TA 7----------- 17 69

VC C3

----------

18

68

GDD 3

----------

19

67

DA TA 8

----------

20

66

DA TA 9

----------

21 65

DA TA10

----------

22

FE3030 FARADAY

64

PA TAU 23

63

VC C4

----------

24

62

GDD 4

----------

25

61

DA TA 12

----------

26

60

DATA 13

----------

27

59

DA TA 14

----------

28

58

DA TA15

----------

29

57

NIOW

----------

30

56

GD D5

----------

31

55

VC C5

----------

32

54

-VCC8

-GDD9

-N WRP IO

-N RESET

-NSELDATA

-NIN TA

-H LDA

-NMA ST ER

-N GTP IO

-IOC K

.prK

-NF24 5D IR

-NF245EN

-NRT CCS

-ADR(O)

-DGATECTL

-NC 245EN

-D T R

- ND646EN

-G DD8

-VCC 7

84 I/O

30 I/O

34 I/O

61

2

36 37 38 41 42 43 44 45 46

I

O

I/O I/O I/O I/O I/O I/O I/O I/O I/O

NYIOR

NIOW

NIOR

NRTCCS

NRTCRD

NRTCWR

DO D1 D2 D3 D4 D5 D6 D7 D8

U q QQOQQQ

48 I/O D10

49 I/O

D ll

50 I/O

D12

PIN TYPE

SYMBOL FUNCTION

51 I/O D13

65

I

IOCK I/O DEVICE ERROR

52

I/O

D14

Active high — This signal from the FE3000 in

53 I/O D15

dicates an error from the PC/AT bus.

8 I/O DATA0

64 I PCK

PARITY CHECK

9 I/O DATA1

Active high — This signal from the FE3000 in

10

I/O DATA2

dicates a parity error from the on board RAM.

11 I/O DATA3

66

I NGTPIO

GATE PIO

14 I/O DATA4

Active low — This signal gates the IOCK and PCK

15 I/O DATA5

signals on to the data bus during a status read.

16

I/O

DATA6

72 I NWRPIO

WRITE PIO

17 I/O

DATA7

Active low — Write the error enable register.

20 I/O DATA8

4 O ENIOCK

ENABLE IO CHECK

21

I/O

DATA9

Active high

22 I/O DATA10

5

O ENRAMCK

ENABLE PARITY CHECK

23 I/O DATA11

Active high

26 I/O DATA12

71 I

NRESET RESET

27

I/O

DATA13

Active low — System reset from the FE3000.

28 I/O DATA14

70

I

NSELDATA SELECT DATA

29

I/O

DATA15

Active low — This signal gates the E data bus.

76 I/O

EDATA0

69

I

NINTA

INTERRUPT ACKNOWLEDGE

77 I/O

EDATA1

Active low — This signal gates the interrupt vector

78 I/O

EDATA2

on the EDATA bus to the CPU.

79 I/O

EDATA3

68

I

HLDA

HOLD ACKNOWLEDGE

80 I/O EDATA4

Active high — Signal from the 80286 to indicate

81 I/O EDATA5

that the bus has been released in response to a CPU

82 I/O EDATA6

HRQ signal.

83 I/O

EDATA7

35

o

ACK

ACKNOWLEDGE

6 VCC1

Active high — Signal to indicate that the current cy

12

VCC2

cle is a DMA cycle.

18 VCC3

67

I NMASTER MASTER

24 VCC4

Active low — Signal from the AT bus which allows

32

VCC5

the bus master to control the bus.

39 VCC6

63 I NF245DIR BYTE SWAP DIRECTION

54

VCC7

Controls the data bus direction for byte swap.

74

VCC8

62

I

NF245EN BYTE SWAP ENABLE

7 GDD1

Active low — This signal enables the byte swap bus.

13

GDD2

57

I DTR

DATA DIRECTION

19 GDD3

This signal determines the data direction on the bus.

25

GDD4

60 I

ADDRESS(0) AT BUS ADDRESS BIT 0

31

GDD5

56 I ND646 EN

DATA BUS ENABLE D (0:7)

33

GDD6

Active low — This signal enables the data bit 0-bus.

40

GDD7

59

I

DGATECTL

DATA GATE CONTROL

55

GDD8

Active high — Signal to latch read data 0-7 on a 16

73

GDD9

bit read of a 8 bit device.

75 GDD10

DATA BUS ENABLE D (8:15)

Active low — This signal enables the data bit 8-15

bus.

I/O WRITE COMMAND

Active low — Signal to indicate a I/O write during

a CPU, DMA, or Master cycle.

I/O READ COMMAND Active low — Signal to indicate a I/O read during a CPU, DMA, or Master Cycle. PC BUS I/O WRITE COMMAND Active low — Signal to indicate a I/O write during a CPU, DMA, or Master Cycle. PC BUS I/O WRITE COMMAND Active low — Signal to indicate a I/O read during a CPU, DMA, or Master Cycle. REAL TIME CLOCK CHIP SELECT Active low REAL TIME CLOCK READ Active low REAL TIME CLOCK WRITE Active low 80286 DATA BIT 0 80286 DATA BIT 1 80286 DATA BIT 2 80286 DATA BIT 3 80286 DATA BIT 4 80286 DATA BIT 5 80286 DATA BIT 6 80286 DATA BIT 7 80286 DATA BIT 8 80286 DATA BIT 9 80286 DATA BIT 10 80286 DATA BIT 11 80286 DATA BIT 12 80286 DATA BIT 13 80286 DATA BIT 14 80286 DATA BIT 15 AT DATA BUS BIT 0 AT DATA BUS BIT 1 AT DATA BUS BIT 2 AT DATA BUS BIT 3

AT DATA BUS BIT 4

AT DATA BUS BIT 5

AT DATA BUS BIT 6

AT DATA BUS BIT 7

AT DATA BUS BIT 8

AT DATA BUS BIT 9

AT DATA BUS BIT 10

AT DATA BUS BIT 11

AT DATA BUS BIT 12

AT DATA BUS BIT 13

AT DATA BUS BIT 14

AT DATA BUS BIT 15

PERIPHERAL DATA BUS BIT 0

PERIPHERAL DATA BUS BIT 1

PERIPHERAL DATA BUS BIT 2

PERIPHERAL DATA BUS BIT 3

PERIPHERAL DATA BUS BIT 4

PERIPHERAL DATA BUS BIT 5

PERIPHERAL DATA BUS BIT 6

PERIPHERAL DATA BUS BIT 7

5V ± 5<Vo

5V ± 5%

GROUND

5-9

6) PVGA-1A VIDEO CNTRL 390302-01

PC40-III SERVICE MANUAL

SYMBOL

RSET

MCLK

VCLKO

VCLK1 VCLK2

DA15

EMEM

MRDN IN

MWRN IN

IN/OUT

IN/OUT A19 A18 A17 IN A16 A15

IN/OUT 20 D1

DA14 IN/OUT 19

IN/OUT 18 Cl

DA13 DA12 IN/OUT DA11

IN/OUT

DA10

IN/OUT 13

DA9

IN/OUT

DA8 DA7 IN/OUT DA6 IN/OUT

IN/OUT

DA5 DA4 IN/OUT

IN/OUT

DA3 DA2 IN/OUT

DAI IN/OUT DAO IN/OUT

EION IN 33 J2

BHEN IN 9 A4

IORN IN

IOWN

MD15 IN/OUT 89 MD14 IN/OUT MD13 MD12 IN/OUT 92 B ll MD11 IN/OUT MD10

MD9 IN/OUT 95 MD8

PLCC

TYPE

PINS

IN 36 IN 76

IN 75

74 H12 73

IN 28 G1

27

IN

24 F2 Address bus bit 17 IN 23 F3 IN 22

17 C2 16 B1 14

12 46 M5 Multiplexed data/address bus bit 7 45

44 M4 Multiplexed data/address bus bit 5

43 N3 Multiplexed data/address bus bit 4

42 M3 Multiplexed data/address bus bit 3

41

40

39

21 E2

IN

31

32

29 HI

IN

30 H2

IN/OUT

IN/OUT 94

IN/OUT

90 B12

91 A12

93 A ll

96 B9

PGA

DESCRIPTION

PINS

Active high signal from external circuit during power up

LI

Up to 36 MHz for 120 ns DRAMS

G12

Up to 44.5 MHz for 100 ns DRAMS

25.175 MHz reference clock input

H13

28.322 MHz clock input* User defined external clock input*

HU

Address bus bit 19

Address bus bit 18

G3

Address bus bit 16 Address bus bit 15

El

Multiplexed data bit 15 with Monitor type input Multiplexed data/address bus bit 14

D2

Multiplexed data/address bus bit 13 Multiplexed data/address bus bit 12

Multiplexed data/address bus bit 11 A1 Multiplexed data/address bus bit 10 B3 Multiplexed data/address bus bit 9 A2 Multiplexed data/address bus bit 8

N4 Multiplexed data/address bus bit 6

N2

Multiplexed data/address bus bit 2

M2

Multiplexed data/address bus bit 1

N1

Multiplexed data/address bus bit 0 Enable display memory. Active high Programmable enable I/O. Active low or high Bus high byte enable. Active low

H3 Display memory read strobe. Active low

J1 Display memory write strobe. Active low

I/O read strobe. Active low I/O write strobe. Active low

A13 Display memory data bit 15

Display memory data bit 14 Display memory data bit 13 Display memory data bit 12 Display memory data bit 11

B10

Display memory data bit 10

A10

Display memory data bit 9 Display memory data bit 8

5-10

PC40-III SERVICE MANUAL

PIN PIN PLCC

PGA

SYMBOL

TYPE

PINS

DESCRIPTION

MD7

IN/OUT 97

A9

Display memory data or configuration bit 7 upon power up

MD6

IN/OUT

98

C8

Display memory data or configuration bit 6 upon power up

MD5

IN/OUT 99

B8

Display memory data or configuration bit 5 upon power up

MD4

IN/OUT

2

Cl

Display memory data or configuration bit 4 upon power up

MD3 IN/OUT 3

A7

Display memory data or configuration bit 3 upon power up

MD2 IN/OUT

4 A6

Display memory data or configuration bit 2 upon power up

MD1

IN/OUT 5 B6

Display memory data or configuration bit 1 upon power up

MDO

IN/OUT 6

C6

Display memory data or configuration bit 0 upon power up

RASION OUT

79 F13

Row address strobe bank 0 (Memory Maps 1 & 0). Active low

CAS10N OUT 80

F12

Column address strobe bank 0. Active low

OEION OUT 81

Fll Output enable bank 0. Active low

WE1N OUT 86 C13

Write enable bank 0 upper byte (Memory map 1). Active low

WEON OUT 85 D12

Write enable bank 0 lower byte (Memory map 0). Active low

RAS32N

OUT

82 E13

Row address strobe bank 1 (Memory maps 3 and 2). Active low

CAS32N OUT 83

E12 Column address strobe bank 1. Active low

OE32N OUT 84 D13

Output enable bank 1. Active low

WE3N OUT

88

C12 Write enable bank 1 upper byte (Memory map 3). Active low

WE2N OUT 87 B13

Write enable bank 1 lower byte (Memory map 2). Active low

MA8

OUT

63

M il

Display memory multiplexed RAS/CAS address bit 8

MA7 OUT 65

M12

Display memory multiplexed RAS/CAS address bit 7

MA6

OUT 66

M13

Display memory multiplexed RAS/CAS address bit 6

MA5

OUT 67

L12

Display memory multiplexed RAS/CAS address bit 5

MA2 OUT

70

K13 Display memory multiplexed RAS/CAS address bit 2

MAI OUT

71

J12

Display memory multiplexed RAS/CAS address bit 1

MAO OUT 72

J13 Display memory multiplexed RAS/CAS address bit 0

MA4 OUT

68

L13 Display memory multiplexed RAS/CAS address bit 4

MA3 OUT 69 K12

Display memory multiplexed RAS/CAS address bit 3

VID7

OUT 48

L6

Video color look up table address bit 7

VID6

OUT 49 M6 Video color look up table address bit 6

VID5

OUT 50 N6

Video color look up table address bit 5

VID4 OUT 53

N7 Video color look up table address bit 4

VID3 OUT 54

N8 Video color look up table address bit 3

VID2

OUT

55

M8 Video color look up table address bit 2

VID1 OUT 56

L8 Video color look up table address bit 1

VIDO

OUT 57 N9 Video color look up table address bit 0

PLCK

OUT

59

N10 Pixel clock

BLNKN OUT 62

N12 Color monitor blank pulse. Active low

HSYNC

OUT

60

M10

Color monitor horizontal synchronization pulse. Active high

VSYNC

OUT

61

N il Color monitor vertical synchronization pulse. Active high

RPLTN

OUT 47 N5 Read color look up pallet. Active low

SKDBKN OUT 10

B4 Card select feedback during memory or I/O access. Active low

WPLTN OUT 58

M9 Write color look up pallet. Active low

REDY

OUT 34

K1 A tristate active high ready output to signal processor that memory access

is available

IRQ OUT 35

K2

Programmable processor interrupt request. Active low or high with tristate

DS16N OUT

8

B5 Programmable enable 16 bit word transfer. Active low

EBROMN OUT 7 A5 Enable BIOS ROM. Active low

EABUFN OUT

11

A3 Enable processor address buffer. Active low

EDBUFN

OUT

38

L2 Enable processor data buffer. Active low

DIR

OUT 37

Ml

Directional control for processor data bus. Bits 0 through 15 high for read cycles

VDD

...

25

FI + 5V DC

VDD

...

52

L7

+ 5V DC

VDD

...

78

G13 + 5V DC

VDD

...

100

A8 + 5V DC

vs s

...

1

B2

GND

v s s

...

15

G2 GND

v s s

...

26

M7

GND

v s s

...

51

N13 GND

v s s

...

64 G il GND

v s s

...

77

B7 GND

5-11

PC40-III SERVICE MANUAL

7) PPC1 PARALLEL PRINTER CNTRL 318091-01

G N D

1

40

D7 2

39

DATO 3

38

AO 4 37

G N D 5

36

DA T 1

6 35

A1 7

34

D A T 2 8 33

A2 9 32

D A T 3

10

31

A3 11 30

D A T4 12

29

A4

13

28

D A T 5

14

27

A5 15

26

G N D

16

25

D A T6

17

24

PA PE

18

23

D A T7

19

22

BUSY

20

21

D6 D5 D4 D3 D2 VCC D1 DO RSTN IO RN IO W N SLCN IN IN A F X N STBN ERR N SLCT CEN AC K N IR Q

P/N

CODE

DESCKll'I ION

l

GND

Ground

2

D7

Data Bit 7 In

3

DATO

Data Bit 0 Out

4

AO

Address Line 0

5 GND

Ground

6 DAT1

Data Bit 1 Out

7

A1

Address Line 1

8 DAT2

Data Bit 2 Out

9

A2

Address Line 2

10

DAT3

Data Bit 3 Out

11

A3

Address Line 3

12

DAT4

Data Bit 4 Out

13

A4

Address Line 4

14

DATS

Data Bit 5 Out

15 A5

Address Line 5

16 GND

Ground

17

DAT6

Data Bit 6 Out

18 PAPE

Paper Out

19 DAT7

Data Bit 7 Out

20 BUSY

Printer busy

21 IRQ

Interrupt #7

22

ACKN

Acknowledge

23

CEN

Chip Select

24 SLCT

Printer Select

25

ERRN

Error

26

sTBn

Strobe

27 AFXN

Autofeed

28

ININ Initial Reset

29

SLCN

Select From Printer 30 IOWN I/O Write 31

IORN I/O Read

32

rSTn

Reset 33 DO Data Bit 0 In 34

D1 Data Bit 1 In

35 VCC

+ 5V 36

D2 Data Bit 2 In

37 D3

Data Bit 3 In 38

D4 Data Bit 4 In

39

D5

Data Bit 5 In 40

D6 Data Bit 6 In

5-12

PC40-III SERVICE MANUAL

8) WD37C65 FDC 390304-03

RD —

1

40

— vcc

W R —

2

39 — ID X

CS — 3

38 — TR00

A0 —

4

37 — W P

DA C K — 5

36

— RW C, RPM

TC — 6

35

— H D L

DB 0 — 7

34 — M 0 2, D S 4

DB1 — 8

33 — M O l, DS3

DB 2 —

9

32 — D S 2

DB3 — 10

31 — vss

D B 4 —

11

30 — DS1

DB5 —

12

29 — STEP

DB 6 — 13 28

— DIRC

DB 7 —

14 27

— W D

D M A —

15 26 — W E

IR Q —

16 25

— ITS

LD O R —

17 24

— DC V AL

LD C R — 18

23

— CLK1

RST —

19

22

— DRV

A D D —

20

21

— CL K K

D/P PIN

SIGNAL

NUMBER MNEMONIC

NAME

1/1

RD

READ

2/2 WR

WRITE

3/3 CS

CHIP SELECT

4/4

A0

ADDRESS LINE

5/5

DACK

DMA

ACKNOWLEDGE

6/6 TC

TERMINAL

COUNT

7-14 7-14

15/15

16/16

17

17/18

DBO thru

DB7

DMA

IRQ

DATA BUS 0 thru

DATA BUS 7

DIRECT MEMORY

ACCESS

INTERRUPT

LDOR LOAD

OPERATIONS

REGISTER

18/19

LDCR

LOAD CONTROL

REGISTER

19/20 RST

RESET

20/21

RDD

READ DISK

DATA

21/

CLK2

CLOCK2

/22

XT2 XTAL2

/23 XT2

XTAL2

22/24 DRV

DRIVE TYPE

23/

CLK1

CLOCK1

/25

xTT

XTAL1

/26

XT1

XTAL1

24/27

PCVAL PRECOMPEN

SATION VALUE

I/O FUNCTION

I Control signal for transfer of data or status onto the data bus by the WD37C65. I Control signal for latching data from the bus into the WD37C65 Buffer Register. I Selected when 0 (low) allowing RD or WR operation from the Host.

___

I Address line selecting data (-1) or status (-0) information. (AO - logic 0 during WR is illegal).

__

I Used by the DMA controller to transfer data from the WD37C65 onto the bus. Logical equivalent to CS and AO-1. In

Special or PC/AT Mode, this signal is qualified by DMAEN from the Operations Register.

I This signal indicates to WD37C65 that data transfer is complete. If DMA operational mode is selected for command execu-

tion, TC will be qualified by DACK, but not in the programmed I/O execution. In PC/AT or Special Mode, qualification by PACK requires the Operations Register signal DMAEN to be logically true. Note also that in PC/AT Mode, TC will be quali fied by DACK, whether in DMA or non-DMA Host operation. Programmed I/O in PC/AT Mode will cause an abnormal ter mination error at the completion of a command.

I/O 8-Bit, bi-directional, tri-state, data bus. DO is the least significant bit (LSB). D7 is the most significant bit (MSB).

O DMA request for byte transfers of data. In Special or PC/AT mode, this pin is tri-stated, enabled by the DMAEN signal from

the Operation Register. This pin is driven in the Base Mode.

0 Interrupt request indicating the completion of command execution or data transfer requests (in non-DMA mode). Normally

driven in base mode. In Special or PC/AT Mode, this pin is tri-stated, enabled by the DMAEN signal from the Operations

Register. Not connected in the 44 Pin PLCC.

___

1 Address decode which enables the loading of the Operations Register. Internally gated with WR creates the strobe which

latches the data bus into the Operations Register.

I Address decode which enables loading of the Control Register. Internally gated with WR creates the strobe which latches the

two LSBs from the data bus into the Control Register.

I Resets controller, placing microsequencer in idle. Resets device outputs. Puts device in Base Mode, not PC/AT or Special

Mode.

I This is the raw serial bit stream from the disk drive. Each falling edge of the pulses represents a flux transition of the encoded

data.

I TTL level clock input used for non-standard data rates; is 9.6MHz for 300 Kb/s, and can only be selected from the Control

Register.

0 XTAL oscillator drive output for 44 Pin PLCC (See Figure 6). Should be left floating if TTL inputs used at pin 23.

1 XTAL oscillator input used for non-standard data rates. It may be driven with TTL level signal. I Drive type input indicates to the device that a two-speed spindle motor is used if logic is 0. In that case, the second clock input

will never be selected and must be grounded.

I TTL level clock input is used to generate all internal timings for standard data rates. Frequency must be 16MHz ± 0.1%, and

may have 40/60 or 60/40 duty cycle.

0 XTAL oscillator drive output for 44 Pin PLCC (See Figure 6). Should be left floating if TTL inputs used at pin 26.

1 XTAL oscillator input requiring 16MHz crystal. This oscillator is used for all standard data rates, and may be driven with a

TTL level signal.

I PRECOMPENSATION VALUE select input. This pin determines the amount of write precompensation used on the inner

tracks of the diskette. Logic 1 - 125ns, Logic 0 - 187 ns.

5-13

PC40-III SERVICE MANUAL

D/ P PIN

NUMBER MNEMONIC

25/28 HS HEAD SELECT

26/29

27/30 28/31 D1RC 29/32 STEP 30/33 DSI

31/34 32/35

33/36

34/37 M02, DS4

35/38 36/39

40

37/41 WP

38/42 Troo

39/43 IDX INDEX

40/44

WE WRITE ENABLE 0

WD WRITE DATA

vs s DS2

MOl, DS3

HDL

RWC, RPM

VCC + 5VDC

SIGNAL

NAME

DIRECTION 0 This HCD output determines the direction of the head stepper motor. Logic 1 - outward motion. Logic 0 - inward motion.

STEP PULSE 0 This HCD output issues an active low pulse for each track to track movement of the head.

DRIVE SELECT 1

GROUND

DRIVE SELECT 2 0

MOTOR ON 1, 0

DRIVE SELECT 3

MOTOR ON 2, 0

DRIVE SELECT 4

HEAD LOADED 0

REDUCED WRITE 0 This HCD output when active low causes a REDUCED WRITE CURRENT when bit density is increased toward the inner

CURRENT

REVOLUTIONS

PER MINUTE

WRITE

PROTECTED

TRACK 00 I

FUNCTION

I/O

0 High current driver (HCD) output selects the head (side) of the floppy disk that is being read or written. Logic 1 - side 0.

Logic 0 - side 1. This HCD output becomes true, active low, just prior to writing on the diskette. This allows current to flow through the write head.

0

This HCD output is WRITE DATA. Each falling edge of the encoded data pulse stream causes a flux transition on the media.

0

This HCD output, when active low is DRIVE SELECT 1 in PC/AT Mode, enabling the interface in this disk drive. This signal comes from the Operations Register. In Base, or Special Mode, this output is #1 of the four decoded Unit Selects, as specified in the device command syntax. Ground. This HCD output when active low is DRIVE SELECT 2, in PC/AT Mode, enabling the interface in this disk drive. This signal comes from the Operations Register, in Base or the Special Mode, this output is #2 of the four decoded Unit Selects as speci fied in the device command syntax.

This HCD output when active low is MOTOR ON enable for disk drive #1, in PC/AT Mode. This signal comes from the Operations Register. In the Base or Special Mode, this output is #3 of the four decoded Unit Selects as specified in the device command syntax. This HCD output when active low is MOTOR ON enable for disk drive #2, in PC/AT mode. This signal comes from the Oper ations Register. In the Base or Special Mode, this output is #4 of the four decoded Unit Selects as specified in the device command syntax. This HDC output when active low causes the head to be loaded against the media in the selected drive.

tracks, becoming active when tracks greater than 28 are accessed. This condition is valid for Base or Special Mode, and is indicative of when write precompensation is necessary. In the PC/AT mode, (on two-speed disk drives) this signal will be active when 250 MFM or 125 FM data rate is selected. Not connected in the 44 Pin PLCC. This Schmitt Trigger (ST) input senses status from the disk drive indicating active low, when a diskette is WRITE PROTECTED. This ST input senses status from disk drive indicating active low, when the head is positioned over the outermost track, TRACK 00. This ST input senses status from the disk drive indicating active low, when the head is positioned over the beginning of a track

I

marked by an index hole. Input power supply.

5-14

1-8

9

10

11

12

13 14 15

16 17 18 19

20

21

22 23 24 25

26 27 28 29 30 31 32 33

34 35 36 37 38

39

PC40-III SERVICE MANUAL

PIN NAME

DATA BUS

RECEIVE CLK

SERIAL INPUT

SERIAL OUTPUT

CHIP SELECT CHIP SELECT CHIP SELECT

BAUDOUT

EXTERNAL CLOCK IN

EXTERNAL CLOCK OUT

DATA OUT STROBE DATA OUT STROBE

GROUND DATA IN STROBE DATA IN STROBE DRIVER DISABLE

CHIP SELECT OUT

ADDRESS STROBE

REGISTER SELECT A2 REGISTER SELECT A1 REGISTER SELECT AO

NO CONNECT

INTERRUPT

OUTPUT 2

REQUEST TO SEND

DATA TERMINAL

READY

OUTPUT 1

MASTER RESET

CLEAR TO SEND

DATA SET READY

RECEIVED LINE

SIGNAL DETECT

RING INDICATOR

+ 5V

9) 8250 SERIAL INTERFACE 380205-01

DO D1 D2 D3 D4 D5 D6

B7

RCLK

SIN

SO U T

CS0 CS1

B A UD O U T

XTA L 1 X T A L2 DO S T R

DO S T R

vss

■ NC

— D IS T R

SYMBOL

D0-D7

RCLK

SIN

SOUT

cso

CS1

C§2

BAUDOUT

XTAL 1 XTAL 2

DOSTR

VSS DISTR DISTR

DDIS

CSOUT

ADS

A2 A1 A0

NC

INTRPT

UUT2

RTS

DTR

FUNCTION

3-state input/output lines. Bi-directional communication lines between WD8250 and Data Bus. All assembled data TX and RX, control words, and status information are transferred via the D0-D7 data bus. This input is the 16X baud rate clock for the receiver section of the chip (may be tied to BAUDOUT pin 15). Received Serial Data In from the communications link (Peripheral device, modem or data set). Transmitted Serial Data Out to the communication link. The SOUT signal is set to a (logic 1) marking condition upon a MASTER RESET.

___

____ When CSO and CS1 are high, and CS2 is low, chip is selected. Selection is complete when the address strobe ADS latches the chip select signals.

16X clock signal for the transmitter section of the WD8250. The clock rate is equal to the oscillator frequency divided by the divisor loaded into the divisor latches. The BAUDOUT signal may be used to clock the receiver by tying to (pin

9) RCLK. These pins connect the crystal or signal clock to the WD8250 baud rate divisor circuit. See Fig. 3 and Fig. 4 for circuit connection diagrams.

_______ When the chip has been selected, a low DOSTR or high DOSTR will latch data into the selected WD8250 register (a CPU write). Only one of these lines need be used. Tie unused line to its inactive state. DOSTR — high or DOSTR — low. System signal ground.

______ When chip has been selected, a low DISTR or high DISTR will allow a read of the selected WD8250 register (a CPU read). Only one of these lines need be used. Tie unused line to its inactive state. DISTR — high cr DISTR — low. Output goes low whenever data is being read from the WD8250. Can be used to reverse data direction of external transceiver. Output goes high when chip is selected. No data transfer can be initiated until CSOUT is high. When low, provides latching for Register Select (A0, Al, A2,) and Chip Select (CSO, CS1, CS2) NOTE: The rising edge (I) of the ADS signal is required when the Register Select (A0, A l, A2) and the Chip Select (CSO,

CS1, CS2) signals are not stable for the duration of a read or write operation. If not required, the ADS input can be tied permanently low.

These three inputs are used to select a WD8250 internal register during a data read or write. See Table below.

No Connect Output goes high whenever an enabled interrupt is pending.

_____ User-designated output that can be programmed by Bit 3 of the modem control register = 1, causes OUT2 to go low. Output when low informs the modem or data set that the WD8250 is ready to transmit data. See Modem Control Register. Output when low informs the modem or data set that the WD8250 is ready to communicate.

OUT1

MR

CTS

DSR

RSLD

Rl

VCC

User designated output can be programmed by Bit 2 of Modem Control Register = 1 causes OUT1 to go low. When high clears the registers to states as indicated in Table 1. Input from DCE indicating remote device is ready to transmit. See Modem Control Register. Input from DCE used to indicate the status of the local data set. See Modem Control Register.

Input from DCE indicating that it is receiving a signal which meets its signal quality conditions. See Modem Control Register. Input, when low, indicates that a ringing signal is being received by the modem or data set. See Modem Control Register.

+ 5 Volt Supply.

5-15

10) 5720 MOUSE CONTROL 318087-01

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PC40-III SERVICE MANUAL

P/N SIGNAL NAME

1 2 3 4 5 6 BAO 7 8

9 10 11 12 13 14 BD0 15 16 17 18 19 vss 20 21 22 23 24 25 26 27 28 29 30 31 HQ 31 33 34 VP

VDD

NBDACKO 1NP

BA3 INP BA2 INP BA1

PSCLK INP

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RSO

PNWAIT

RSI

IOCHRDY

RS2

BD1 BD2 BD3

vss

BD4 BD5 BD6 BD7

PNBDACK2

NIDIR

NOVID

NBR

PNMONO

NBM

NBL

HP VQ

RSO

NRESET

PSCLK

BAO BA1 BA2 BA3

NBDACKO

VDD

BA4 BA5 BA6 BA7 BA8 BA9

PNBIORC

BAEN

PAD TYPE

INP INP

INP Schmitt trigger INP INP with pullup INP OUT open drain INP I/O with pullup I/O with pullup I/O with pullup I/O with pullup

I/O with pullup I/O with pullup I/O with pullup I/O with pullup INP OUT OUT open drain with pullup INP Schmitt trigger with pullup INP with pullup INP Schmitt trigger with pullup INP Schmitt trigger with pullup INP Schmitt trigger with pullup INP Schmitt trigger with pullup INP Schmitt trigger with pullup INP Schmitt trigger with pullup

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35 36 37 IRQ2 38 39 40 41

42 43 44 45 46 47 48 NCSHDC OUT 49 50 PNCSLDOR OUT 51 52 VSS 53 PTEST INP 54 55 PNCSLPT 56 NIOWDLY OUT 57 NIORDLY 58 59 60 61 62 PNBIORC INP 63 64 65 66 67 BA5 INP 68

VDD M16

IRQ3 IRQ4 OUT tristate IRQ6

PIRQ6IN INP

DRQ2 PDRQ2IN INP DVRSEL2 DRVSEL1

FDCRESET

NCSRTC OUT

NCSFDCXTR

PNCSFDC

PNCSCOM

NCOMOUT

PCOMINT

PNBIOWC INP

BAEN

BA9 BA8 BA7 INP BA6

BA4

NBR PNMONO NBM NBL HQ

HP

VQ

VP VDD M16

IRQ2

IRQ3 IRQ4

IRQ6

PIRQ6IN DRQ2 PDRQ2IN

INP Schmitt trigger

OUT tristate OUT tristate

OUT tristate

OUT OUT OUT

OUT

OUT OUT

OUT INP Schmitt trigger INP Schmitt trigger

INP

INP INP

INP

5-16

Schematic #313056, Rev. C

Sheet 1 of 12

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PC40-III SERVICE MANUAL

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Schematic #313056, Rev. C

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PC40-1II SERVICE MANUAL

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Schematic #313056, Rev. C

Sheet 3 of 12

PC40-III SERVICE MANUAL

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BDflTfl (15:0)

EDRTR (7:0)

CB 3Q 31.1

I 3 0 f e “

C B 3032.1 C B 30^3.1

CB3 0 ^ 4 . 1

CB 30^57

__

j. 1

C B 3 0 I 6 . F CB30 ^ 7 .1

CB 30^8. I"

30^9.1

CB

BYP f lSS_ FOR_ 303 Q

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CB30 4 1 .1 CB30il'2. I

C B l o fe d CB3 0 J!u. 1

C B 3 Q 4^57

CB30^67

_____J. I

CB 3 Qd*7 . l" CB3 0df87 L

-------------II

---------

5-19

Schematic #313056, Rev. C

Sheet 4A of 12

PC40-III SERVICE MANUAL

5-20

Schematic #313056, Rev. C

Sheet 4B of 12

SH. 4

NT 10W ' o r

SH.S IGW-D LT ’ o 2-

SH. 3

REN

o 2-

u4 13

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SH. 3

PC40-III SERVICE MANUAL

SH.3 SR DO R !9: 0) o 2-

Sri. 3

SH.S

n :cr

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fiEN 6

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SH. 8.-i OSCR

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5-21

Schematic #313056, Rev. C

Sheet 5 of 12

PC40-III SERVICE MANUAL

5-22

Schematic #313056, Rev. C

Sheet 6 of 12

PC40-III SERVICE MANUAL

5-23

Schematic #313056, Rev. C

Sheet 7 of 12

PC40-III SERVICE MANUAL

5-24

Schematic #313056, Rev. C

Sheet 8A of 12

PC40-III SERVICE MANUAL

VC C

SH.5 SH . 4

SH . 3 SH. 3 SH.3 SH .3 SH .3 SH .3

SH .3

SH. 12

SH .5 SH.3 SH.3 SH .3 SH .3 SH. 2 SH .3 SH. il SH. 7 SH .5 SH .5

SH .5 SH. BB SH. BB

SH. BB SH. BB

SH .3

SH. BB

SH .3

S H . 9

R E S E T I N 'O -

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S G ' O

! 66

SI 'O

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t 25

M N I O O AD OR (0) O AD DR (1) O

BA D DR (3) O

N A B H E ' O N I O C K ' O

N B U S Y ' O NER R O R 'O NC S 2 8 7 'O

E N I O C K O

N S E T S D ' O

EDATA (7) O

N N M I C S ' O

N Z E R O W S ' O N10C5 1 6 ' O —

N1016 '

IO CHRDY O —

NA EN1 ’O -

N D HA M EM R O -

N R A M S L ' O -

NA EN2 ' O —

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I

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22 0PF HR B02

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hr

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63

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81

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67

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70

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NN MTCS

19

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NZRQ WS

NI OS 16 X 18284 X282 84

23

MD PINQ

24

MDPIN1

17

EB RMCK

22

I0CRD Y

21

HR Q 1

26

NAEN1

NDMA MR

65

OUT 1

NEND CT

NRflMSL

63

NFflST

27

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56

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18

ENPA L2

44

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U8Q 1

42

T

. 1

CB 801 1

. 1

CB8 012

NY I OR

NY IDW

NTMEMW

NYMEMR NRESET PRO CLK

NR EADY RE SCP U

NINTA

ND ENG NDEN1

NN PCS

RS T28 7 NB Z286

IO CHCK

SY SCL K DM ACLK

NP CLK

FI 19M

CT LOF F

NI RQ13 NE RFSH REFDET NR FSH DM ARO Y HL DA 1 CP UHRQ

NE DMMR

DI R245 GT E245

AIOW

ALE DT NR

NNMI

PC LK

LS AQ F14M

Q1

BALE

AS

PCK

76 39 77 34

7

51 83 82 45 46 49 32 53 55 52 33

13

38

M.

54 74 73

11

36 30_

48

35

41

12

72

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9 50_

8

37 47_

75

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13

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o

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■^ON YM EMW ' ^ONY M E M R ' ^ONR E S E T '

■^ONREA DY '

-2O C P UR5 T

-2ONINTA'

- O A L E

-t >DTR

-O N D 6 4 6E N

-2O N C 2 45EN

-2O N NP C S

-^ ONP RST

-2O N N P BUSY '

-2O I O C K

■^ONNMIf

-O E S Y S C LK

-^ ODMACLK

-^ OPCLK

-ONP C L K '

■^ OLASQ

-^ OOSCA

- O TC L K

-^ ODEGAT ECTL

-t >NIRQ13'

-^NERFSH '

-2O N RE FRES H '

-OHDMARDY

-t >HDLDAl

-O>H0LDRQ

-0 >BLA LE

-t >NG TME MR

-0 >RT CAL E

-0 >PCK JON F 2 4 5 D IR

-JO NF 2 4 5 E N '

SH .3/8 B S H .3/4 SH. 3 /8B/ 1 2 SH 3 ./1 2 SH.1 / 2 / 3 /4/5/ 6 /8B/9

SH .3 SH.3

SH. 345H . BB S H . 3S.SH. BB SH .3 SH.3 SH .3 SH .3 SH .3 SH .3 SH .3 SH .3 SH .4 SH .8B S H . 2 S H . 2 SH .3 SH .4 SH .8B SH .3

SH .8B SH .8B

SH.54 S H . 7 SH .8B SH .8B SH.3 SH.44 5 H . 7 SH.3

SH . 2 SH.3 SH .3 SH.3

PA D8G 1

RB 09

300

R81G

0

■ O C P U CL K 5H.34SH. 12

2

5-25

Schematic #313056, Rev. C

Sheet 8B of 12

SH .3

SH.546

SH. 5

SH.541 0

S H . 5 SH. 5 S H . 5 SH. 5 SH. 5

SH . 5 SH. 5

S H . 5 SH. 5 S H . 5 SH. 5 SH. 5 S H . 5

SH. 5 SH .8R

SH .8R SH.8 A

SH .8R 5H .8R

SH-.8R

SH 8.R SH .8R

SH. 8R

SH.8 R

SH. 4

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NYM EMWR ' o ^

SH.3

SH .8R

SH. 5 SH. 2

SH.2.

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1RQ3 O 1RQ4 O 1 IRQ5 O 3- 1RQ6 O 3-

IRQ9 O

IR QI G O 3- IRQ11 O 2 IRQ 12 O * IRQ 14 O 3- IRQ 15 C>2-

DRQ1 O

DR Q3 DR Q5 O 2- DR Q6 O 2- DR Q7 O 2-

RL E O 2-

NIR Q13 ' O 2—

NIN TR ’ c>2 -

TC LK O 2-

OMR C LK O 2-

DMR RDT O 2- H0 LDR 1 o>2-

N E R F S H ' O 2-

NYI DR * O 2-

DLY WR O 3-

NRE SET f O 3-

NMR STER ' O 2-

NIR Q8 ' c>2-

KBD INT 0>*-

,0 ,2

,5

0

_____________________________17

^

_________

____

19

, 27

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84

43

2

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3

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4

0RTR2

5

0RTR3

6

DR TR4

7

DR TR5

8

0RTR6

9

DR TR7

15

IRQ3

IB

IRQ4 IRQ5

18

IRQ6

IRQ7 FE301O

26

IRQ9 IRQ 1Q

28

IRQ11

IRQ12

61

IRQ1 4

60

IRQ15

78

OR QO

77

0RQ1 0R Q2

75

DRQ3

74

DRQ5

73

DRQ6

72

DRQ7

57

RLE

62

NI RQ1 3

59

NI NTR

23

TCLK

12

DM RCL K DM RRD T HLDR

56

NR FSH

8Q

NIOR

81

NIOW

82

NM EMR

83

NMEMW

63

NCLERR

13

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14

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vcc

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fill fl 12

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R16

R17

R) 8

R19

R2 0

R21

R22 R23

REN

DR C K2

DR CKO DRCK1

ND R CKE N

INTR

TC

SY SRL E

NRT CCS

OU T 1

HRQ

GND1

GN D2 GND3 GN D4

R 8 0 4

VCC

4 . 7 K R 8 0 3

—an—

1 C 8 0 2

47PF

2N39041

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30 31 32

33

34

R4

35

R5

36

R6

37

R7

38

RB

39

R9

40

41 44 45

46

47 48 49 50 51 52 53 54 55

.. 15,

n_

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66 20

70

79 56

21

_________________________________

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22

42

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6/

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10 , 1 1,

12,

CO

14,

16/ 17, 18,

CD

20, 21/ 22,

23 . J

220

PC40-III SERVICE MANUAL

- t > S P K R SH. 12

R 80 5

5. IK

t r

P Z 8 0 1

O

-va+1 2V

^ R D R ( 0) s h .3

*oRDDR (23 : 11SH.3

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n \ _ y LL-

74 FQ0

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7 4 H C T 7 4

■ LJ> 1 U 1 o n . *4

■ - - U > U U I 1 On. On

--------------------------------------------------------------------------

- t > N R E N l ' s h . 8a

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O N D R C K 0 1

-o>NDRCK 1 1 JoN D R C K 2 1 o>NDRCK31 o>NDRCK5 1 o>NDRCK61 ON D R C K 7 1

«—v T M T R D <?h 0

L—^ 1 IN 1 M U on • 0

r s T r p s h >i ?r->,n n < RT R qu q

U J 1 D on . 0

r ^ M R T r P R ' SH 3

.......

<— ■nN n 1 U L J on.o

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SH. 5 S H . 5 SH. 5 SH. 5 S H . 5 SH. 5 SH. 5

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U8(§3

^ C&M3

GNO

5-26

Schematic #313056, Rev. C

Sheet 9 of 12

R ENo2-

NH I OR ' o 2-

N I 0W ' o2-

R LEo2-

NRESE T 'o 2- BRDDR (2) o 2- BRDDR (1) o 2- BRDDR (0) o 2-

BflDDR (9:0)

PC40-III SERVICE MANUAL

U90 5

P R L2QL 1 0

11

2

12

3

13

4

14

s \

s

5 6

7 8 9

10

13

023 15 1/022 IB

1/021 1/020

17

1/019

IB

1/018

19

1/017

110

1/016

111

1/015

014

113

*=>IRQ14 3=>ENRBLEHD_L0W' ^oB DRT R (7)

<oHD_DRTR7 cH D _ I RQ 14

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ON 1016 r

o E N R B L E H D_H I G H '

CS1 r o 2- C5Q ’o 2-

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17

07

16

06

15

05 04

14 13

03

12

02

11

01

10 00

IG '

2G '

17

07

16

06

15 05

04

14 13 03 12 02

[ 1

01

10 00

18

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74 LS 244

3 5 7

9 12 14 16

CN902

CN901

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as. 23 2 8 1

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{£}

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BORTR (15) BDRTR (14) BDRT R (13) BDRTR (12) BDRTR (1 1) BDRTR (IQ)

BDRTR (9) BDRTR (8)

BDRTR (S) o 2— BDRTR (5) o 2- BDRTfl (4) o 2- BDRTR (3) o 2- BDRTR (2) o 2- BDRTR (1) o 2- BDRTR (0) o 2-

o 2-

o 2- o 2-

ii

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7 4 L S Q 4

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B7 07 B6 B5 95 B4 94 B3 B2 B1 BO

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7 6 5

93

4

92

3

91

2

90

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74 F 245

97

B7

96

B6

95

B5

94

B4

93

B3

92

B2

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T gn o T CND T GND T cnd T

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CB9Q1

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CB9Q2

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1^ ^ 1

33

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CB904

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1

CB905

12

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34

{U

5-27

Schematic #313056, Rev. C

Sheet 10 of 12

PC40-III SERVICE MANUAL

5-28

Schematic #313056, Rev. C

Sheet 11 of 12

PC40-III SERVICE MANUAL

vcc

s

__

P A D 1 1 Q 1

r© © 0-i

vcc

C B 1 1 G 1

. 1

DIGITAL

P AD 1 102 Ycc

1

^4 ^b

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27

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25 24 21 23

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vcc

1

VPP

11

PGM'

00

9

fll

8

02

7

03

6

04

5

05

4

06

3

07 08 09

010

011

2

012

013

OE

CE'

R0M2

U 1 1 0 1

DO

GND

01 D2

03 D4 05

D6

D7

_____

b

%

b>

b/ 0

12 13 15 16 17 18 19

14

P R D1 1G 4 V?CC

T

f 2

'3 " ^4

"b

"6 "/

"6

'S

^ 1 0 " 1 1

" 1 2

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15

16

VCC

VPP

27

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10

00

9

01

8

02

7

03

6

04

5

05

4

06

3

07

25

08

24

09

21

010

23

011

2

012

26

013

22

0E'

20

CE'

R0M2

U 11 02

GND

DO

01

D2

03 04

D5

06 D7

11

12 13 15 16 17 18 19

14

b

lb

\uJ

1 by

V

S H . 3 B A D D R (16: 13 o*-

SH. 3 N P R O M S E L

'c*

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DIGITAL

v

DIGITAL

V

DIGITAL

V

DIGITAL

5-29

PC40-III SERVICE MANUAL

Schematic #313056, Rev. C

Sheet 12 of 12

vcc

5-30

PC40-II1 SERVICE MANUAL

APPENDIX A

POWER SUPPLY SECTION

• PC40-111 POWER SUPPLY SCHEMATIC (VDE, BS1, SEV, 5AA)

• PC40-111 POWER SUPPLY SCHEMATIC (CSA, UL)

INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY. COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR

OEM ASSEMBLIES.

soo/

PC40III SERVICE MANUAL

PC40-111 POWER SUPPLY 390269

Input Requirements VDE, BS1 CSA, UL

AC INPUT Parameter

390269-01

390269-02

Voltage Voltage Range Frequency (Hz) Surge Protection

(maximum)

230 VAC

180 - 270 VAC 50 Hz 3 KV, 25 A for 30 usee

110 VAC 90 - 135 VAC 50 - 60 Hz 3 KV, 25 A for 30 usee

Inrush Current

(maximum)

40 A for

30 usee

CN1

A-l

PC40-III SERVICE MANUAL

NOTE: FOR REFERENCE ONLY, —COLOR CODES AND SPECIFICATIONS MAY CHANGE.

Connector CN1 : CPU

PIN SIGNAL

AWG COLOR

LENGTH (mm)

1

PWR GOOD

18 BRN

150.0 ±10%

2 -12V

18 RED 150.0 ±10%

3

+ 12V

18 ORG

150.0 ±10%

4

GND

16 BLU

150.0 ±10%

5 GND

16 BLU 150.0 ±10%

6

+ 5V

14 YEL

150.0 ±10%

Connector CN1 (Recommended)

Vendor

Housing Pin

Remarks

AMP

350715-1

350552-1

MATE-n-LOK

BURNDY

UPH 600

UHM2200

—

Connector CN2 : HD 1

PIN SIGNAL

AWG COLOR

LENGTH (mm)

1

+ 12V

18

ORG

330.0 ±20%

2 GND

18

BLU 330.0 ±20%

3

GND

18

BLU 330.0 ±20%

4 + 5V

18

YEL

330.0 ±20%

Connector CN2 (Recommended)

Vendor

Housing

Pin Remarks

AMP

1-480424-0 611117-1

MATE-n-LOK

J.S. TERM

LCP-04

SLC21T2.0

—

A -2

PC40III SERVICE MANUAL

NOTE: FOR REFERENCE ONLY, — COLOR CODES AND SPECIFICATIONS MAY CHANGE.

Connector CN3 : FDD 1

SIGNAL AWG COLOR

LENGTH (mm)

1 + 12V 18

ORG

330.0 ±20%

2 GND 18

BLU 330.0 ±20%

3

GND 18

BLU 330.0 ±20%

4

+ 5V

18

YEL 330.0 ±20%

Connector CN3 (Recommended)

Vendor Housing

Pin Remarks

AMP 1-480424-0

611117-1

MATE-n-LOK

J.S. TERM

LCP-04 SLC21T2.0

—

Connector CN4 = FDD 2

PIN SIGNAL

AWG COLOR

LENGTH (mm)

1

+ 12V

18 ORG 150.0 ±10%

2 GND

18 BLU

150.0 ±10%

3

GND

18 BLU 150.0 ±10%

4

+ 5V 18

YEL

150.0 ±10%

NOTE: Cable CN4 shall be daisy-chained from connector CN3.

Connector CN4 (Recommended)

Vendor Housing Pin Remarks

AMP 1-480424-0 611117-1

MATE-n-LOK

J.S. TERM LCP-04 SLC21T2.0

—

A-3

FOR REFERENCE ONLY

PC40-III SERVICE MANUAL

06

PN #390269-01

PC40-III POWER SUPPLY (VDEf BS1, SEV, SAA)

>

FOR REFERENCE ONLY

D6

>

PC40-III POWER SUPPLY (CSA, UL)

PN#390269-02

PC40-IH SERVICE MANUAL

PC40-III SERVICE MANUAL

APPENDIX B

DISK DRIVE SECTION

• PC40-III 40MB HARD DRIVE

• PC40-III Hard Drive PN #313065-01 Vendor : Quantum Model : Prodrive 40AT

• PC40-III FLOPPY DISK DRIVE

• PC40-III Floppy Disk Drive PN #380825-02

Vendor : Chinon

Model : FZ506

• 910, 920 ADD ON NOTES

INFORMATION IN THIS SECTION IS FOR REFERENCE ONLY. COMMODORE WILL NOT SUPPLY COMPONENT PARTS FOR

OEM ASSEMBLIES.

The information included in this section is for reference only. Vendors are subject to change without notice. Commodore service will provide alignment procedures and test diagnostics to authorized service centers for field repairs. The

drive exchange program will be in effect and Commodore service will not provide discrete components for field replacement.

PC40-III SERVICE MANUAL

PC40-III HARD DRIVE 313065-01

GENERAL DESCRIPTION The Quantum ProDrive Series™ is a family of ten 3/2 -inch form factor hard disk drives using non-removable rigid disk plat

ters as storage media. These drives feature formatted capacities ranging from 42 to 168 megabytes and a variety of interfaces. This manual covers the ProDrive™ 40AT and ProDrive 80AT, which feature an IBM PC-AT® embedded controller and are available with or without an adapter board. With the adapter board, the ProDrive 40AT/80AT can plug directly into a 16-bit expansion slot in an IBM PC AT or compatible personal computer. Without the adapter board, the ProDrive 40AT/80AT is compatible with other AT-Bus architectures and can be plugged into an embedded AT adapter or into an existing adapter board in a PC AT compatible.

The ProDrive 40AT features 42 megabytes of formatted capacity on two disks with three movable heads; the ProDrive 80AT

provides 84 megabytes of formatted capacity on three disks with six movable heads. Media defects and error recovery are efficiently managed within these products and can be fully transparent to the user. The

ProDrive Series drives feature an in

novative design using an integrated controller, minimum number of parts, and close control of product quality during manufac

ture, resulting in low cost, highly reliable products.

NOTE: Throughout this manual, ProDrive 40AT/80AT or ProDrive will refer to either the ProDrive 40AT or the

ProDrive 80AT. ProDrive 40AT and ProDrive 80AT will be used to refer specifically to the 42 and 84

megabyte versions, respectively.

SPECIFICATIONS Key features of the ProDrive 40AT/80AT include:

• Formatted storage capacity of 42 or 84 megabytes

• Industry standard 3

Vi -inch form factor

• 19 millisecond average access time

• Data transfer rate up to 4.0 megabytes/second using programmed I/O

• 64K-byte look-ahead DisCache®

• 48-bit computer generated Error Correcting Code (ECC) with 11-bit burst correction capability

• Automatic retry for read disk errors

• Transparent defect mapping

• High-performance in-line defective sector skipping and reassignment of new defective sectors without need to reformat

• Patented AIRLOCK® automatic shipping lock and dedicated landing zone

• Read/Write with 1:1 interleave operation

• Emulation of IBM PC AT task file register and all AT fixed disk commands

• Ability to daisy-chain two drives on the interface

PHYSICAL SPECIFICATIONS Environmental Limits

Ambient Temperature —

Non-Operating:

- 40°F to 140°F ( - 40°C to 65°C)

Operating:

42°F/hr (20°C/hr) gradient

39°F to 122°F (4°C to 50°C)

Ambient Relative Humidity —

Non-Operating:

23°F/hr (10°C/hr) gradient

5% to 95% without condensation

Operating:

Maximum wet bulb = 115°F (46°C) 8 % to 85% without condensation

Altitude (relative to sea level) —

Non-Operating:

Maximum wet bulb = 79°F (26°C)

-2 00 (- 60M) to 40,000 ft. (12 km)

Operating:

-2 00 (-60M ) to 10,000 ft. (3 km)

ProDriverM and ProDrive Ser/es™ are trademarks of Quantum Corporation

AIRLOCK® and DisCache® are registered trademarks of Quantum Corporation

Printed in U.S.A.

B-l

PC40-III SERVICE MANUAL

Mechanical Dimensions (Exclusive of Faceplate)

Height = 1.625 in. (41.3 mm) Width = 4.0 in. (101.6 mm) Depth = 5.75 in. (144.9 mm) Weight = 1.9 lb. (0.88 kg)

Heat Dissipation

Average Power Consumption (idle): 8 Watts (27.3 BTU/Hr) Typical Power Consumption (30% Seeking): 9Watts (30.7 BTU/Hr)

Shock and Vibration

The table below lists specified levels for shock and vibration applied to any of the three mutually perpendicular axes (the prin cipal drive base axes). The term “operating” implies that the drive will be fully functional while being subjected to the shock or vibration level listed during operation. “Non-operating” implies that there will be no change in performance once the drive is powered up after being subjected to the listed shock or vibration in the powered-down (non-operating) condition.

Vibration and Shock Specification

Operating

Non-Operating

VIBRATION:

5-500 Hz Sine Wave (Peak to Peak)

0.50 G 2.00 G

1 Oct/Min Sine Sweep

SHOCK:

10 G (1 soft error/shock)

Vi Sine Wave of 60 G

11 msec Duration (10 hits maximum)

(6 G No soft errors)

In addition, the ProDrive as packaged in the shipping container will withstand drops onto a concrete surface from 48 inches

on all surfaces, six edges and three corners. It will withstand vibration applied to the container of 0.5 G, 5-100 Hz (0 to Peak) and 1.5 G, 100-500 Hz (0 to Peak).

PERFORMANCE SPECIFICATIONS Capacity

ProDrive 40AT ProDrive 80AT

Formatted capacity (MB) 42* 84* Number of 512 byte sectors 82,029 164,058

*40, and 80 megabytes, respectively when a megabyte is defined as 2 ^ bytes

Data Transfer Rates Buffer to AT-Bus - Up to 4.0 Mbytes/second using programmed I/O

Disk to Buffer - Up to 1.25 Mbytes/second in bursts

Seek Times/Miscellaneous Times

TYPICAL

MAXIMUM

NOMINAL

WORST CASE

DESCRIPTION

CONDITION

Single Track Seek (msec)

6

7

Average Seek (msec)

19

21

23

!/s Stroke Seek (msec)

20 23

25

Full Stoke Seek (msec)

35

40

45

Average Rotational Latency (msec) 8.2

8.2 8.2

Sequential Head Switch (msec)

3.0

3.0 3.0

Power-Up Time (sec)

13

15

18

B -2

PC40-III SERVICE MANUAL

NOTES: Quoted seek times include head settling time but do not include command overhead or latency time. Seek time is

the time required for the actuator to seek and settle on track.

Seek times are measured by averaging 1000 seeks of the indicated length. Average seek time is the average of 1000 random seeks. In the rare occurrence of a seek error, any individual seek may take up to 5 seconds for recovery.

Sequential head switch time is the time required for the head to move from the end of the last sector on a track to the beginning of the next sequential sector, located on the next track, same cylinder. This time is fixed by the track skewing feature of the drive. (See Appendix B.)

Power-up time is the time from the supply voltages reach operating range to the time the drive is able to accept all commands.

Nominal conditions are defined as 25°C ambient temperature, nominal supply voltages, and no applied shock or vibration. Worst case conditions are defined as worst case extremes of temperature and supply voltages.

Media Quality

The ProDrive features defect management, which eliminates the need to manually indentify defects. Defect management is

completely transparent to the user. See Appendix C for a detailed description of the ProDrive’s defect handling procedure and ECC capability.

Error Rates

Random Data Errors (2): 1 error per Defect Data Errors (3): 1 error per Unrecoverable Data Errors (4): 1 error per Seek Errors (5): 1 error per

Error rates are defined as follows:

1) A data error is one (1) sector read incorrectly. Data error rates are defined as average rates measured over at least 1000

different sectors under any of the specified conditions except applied shock or vibration.

2) Random errors are those which do not exhibit a repeating error pattern, i.e, the error does not occur twice in a row within a specified number of retry reads; the default is eight. (Retries are terminated once data is read correctly.) The sectors will not be automatically reallocated since the errors are probably not due to media defects.

3) Defect errors are those which exhibit a repeating error pattern, i.e., the error occurs twice in a row within eight retry reads, and cannot be read without error up to that point. Such errors are likely due to media defects.

4) Unrecoverable errors are those whose final retry error pattern is uncorrectable using ECC: retry reads are terminated by either a repeating error pattern, or eight attempts without reading correctly.

5) A seek error is any seek in which the drive does not locate the desired cylinder, or any seek in which the drive must go through a full recalibration routine to locate the desired cylinder. A full recalibration takes approximately five seconds.

FUNCTIONAL SPECIFICATIONS

PHYSICAL FORMAT

ProDrive 40AT ProDrive 80AT

Nom Rotational Speed (RPM) 3,662 ±0.3%

3,662 ±0.3%

Max Recording Density (bpi)

22,055 22,055

Max Flux Density (fci)

14,700

Track Density (tpi)

1,000 1,000

Data Cylinders

834

Data Tracks

2,502

5,004 R/W Heads 3 6 Disks

2

3

Encoding Scheme

RLL 2,7 RLL 2,7

10^ bits read (maximum)

12

10 bits read (maximum)

14

10 bits read (maximum) 106 seeks (maximum)

B-3

PC40III SERVICE MANUAL

LOGICAL FORMAT

The logical layout is how the drive appears to an AT-Bus system.

ProDrive 40AT

ProDrive 80AT

Data Cylinders 965 965 Sectors/Track 17 17 R/W Heads 5

10

RELIABILITY SPECIFICATIONS MTBF (Mean Time Between Failure): 50,000 POH (Power On Hours) typical usage

PM (Preventative Maintenance): Not required MTTR (Mean Time To Repair): 30 minutes Start/Stop: 10,000 cycles

ACOUSTICS

Idle Mode: 45 dBa maximum at 1 foot in any direction

Pro Drive Mechanical Dimensions

B -4

PC40-1II SERVICE MANUAL

MOUNTING/DIMENSIONS (DIMENSIONS EXCLUSIVE OF FACEPLATE) The drive may be mounted in any orientation. Clearance from the drive to any other surface (except shock mount brackets or faceplate) should be 0.10 inch minimum. HEIGHT 1.625 in. 41.3 mm

WIDTH 4.0 in. 101.6 mm DEPTH 5.75 in. 146.1 mm WEIGHT 1.9 1b. 0.88 kg

3 .5±. 1 0

i

144.9

±. 2 5

DIMENSIONS ARE IN MILLIMETERS; SCREW SIZE IS 6-32

PC40-III HARD DRIVE

B-5

PC40-III SERVICE MANUAL

POWER REQUIREMENTS

No damage or loss of data occurs if power is applied or removed in any order or manner, except that data may be lost in the sector being written to at the time of the power loss. This includes opening up or shorting out either voltage or return line, and transient voltages + 10% to - 100% from nominal, while powering up or down.

VOLTAGE

+ 12V + 5V

NOMINAL

+ 12V

+ 5V

TOLERANCE ±10% ±5%

CURRENT

TYPICAL (IDLE)

0.5A 0.5A

TYPICAL (SEEKING)

0.8A 0.6A

MAXIMUM (POWER-UP)

1.6A 0.65A RIPPLE AND NOISE (MAXIMUM) AVERAGE POWER CONSUMPTION

TYPICAL POWER CONSUMPTION (30% SEEK) MAXIMUM POWER

lOOmVp-p

8W 9W

11W

50mVp-p

POWER RESET LIMITS

When powering up, the drive remains reset (inactive) until both supplies reach the upper threshold value. When powering

down, the drive becomes reset when either supply voltage drops below the lower threshold value. Hysteresis is 50m V minimum.

5V 4.50V TO 4.20V

12V 10.4V TO 9.70V

PC40-III Power Connector - HD

PIN Signal

1

+ 12 Volts

2 Ground

3

Ground

4

+ 5 Volts

DC POWER CONNECTOR

The DC power connector (Jl) is a 4-pin DuPont Connector (SK 20055-000) mounted on the back edge of the Printed Circuit

Board (PCB) near the AT-Bus connector. See Figure 1. The recommended mating connector (P2) (AMP P/N 1-480424-0) utilizes AMP pins [P/N 350078-4 (strip) or P/N 61173-4 (loose piece)]. Jl pins are labeled on the connector.

Pin 1 + 12 volts DC Pin 2 +12 volt return (ground) Pin 3 +5 volt return (ground) Pin 4 +5 volts DC

NOTE: Pins 2 and 3 are connected on the drive.

4 3 2 1

FIGURE 1 — DC POWER CONNECTOR (Jl)

B -6

PC40-III SERVICE MANUAL

AT-BUS INTERFACE CONNECTOR

One AT-Bus interface cable connector (J2) is required for the ProDrive. Details of the signals required can be found in AT-Bus Interface and Commands.

Connection to J2 is through a 40-pin Universal Header connector. A connector sketch is shown in Figure 2. A key slot is provided to prevent incorrect installation of the mating connector. The recommended mating connector for J2 is xxxxx.

NOTE: Unkeyed mating connectors should not be used due to the possibility of plugging the connector in backwards.

□□□□□□□□□□□□□□□□□□□a

FIGURE 2 — AT-BUS INTERFACE CONNECTOR (J2)

JUMPER OPTIONS

Configuration of a ProDrive 40AT/80AT disk drive varies depending on the system in which it is to be installed. This section describes the user-selectable hardware options available on the disk drive PCB. These jumpers should be set prior to installa tion. Figure 3 identifies the location of the shorting plugs and terminators on the drive PCB.

NOTE: Additional jumper options are provided on the adapter board for systems in which the adapter board is used with

the drive.

DC CONNECTOR (Jl) MICROPROCESSOR

BACK OF

DRIVE

HDA CONNECTORS

FACE PLATE SIDE

FIGURE 3 — Shorting Plug Locations on the Drive PCB

B -7

PC40-III SERVICE MANUAL

SELF SEEK TEST OPTION

The self seek test continuously exercises the actuator of the drive. When shorting plug option SS is installed, the drive will perform random seek patterns, verifying track IDs after every seek. The pattern will repeat as long as power is applied to the drive, until the shorting plug is removed, or until an error has occurred.

The ProDrive is sent from the factory with shorting plug SS not installed (Self Seek Test disabled).

DRIVE SELECT

Two drives can be daisy-chained on the AT-Bus interface. When two drives are attached, one must be configured as the primary drive, and the other as the secondary drive, using the Drive Select (DS) jumper. With the DS shorting plug installed, the drive is configured as the primary drive (Drive 0); with no shorting plug on jumper DS, the drive is configured as the secondary drive (Drive 1).

The ProDrive is sent from the factory with the DS shorting plug installed (Drive 0)

RESERVED JUMPER

The third jumper is reserved for future use.

FACEPLATE LED OPERATION

The green LED located on the faceplate illuminates when the drive is executing a command. It lights at the beginning of a command and does not go off until the command is completed or aborted.

ADAPTER BOARD

This section is relevant only for systems which implement the ProDrive AT-Bus drive with the adapter board.

ADAPTER BOARD JUMPER OPTIONS

Five jumpers labeled J2 through J6 are provided on the adapter board; the functions of these jumpers are described below. See Figure for the locations of the jumpers on the PCB.

J2 - Allows the drives interrupt logic to control IRQ14. This jumper is provided for compatibility with systems whose

BIOS does not read the STATUS register when the drive issues an interrupt.

• for systems that do not read the STATUS register, jumper from the center pin of J2 to E4;

• for systems that do read the STATUS register, jumper from the center pin of J2 to E3. J3 - Always open. Option for grounding pin #34 of the drive interface. J4 - Forwards IO CH RDY to the drive for use with systems running Chips & Technologies chip set. J5 - Secondary board enable. J6 - For manufacturers use only; do not install a jumper.

INTRODUCTION

The ProDrive 40AT/80AT uses the standardized IBM PC AT Bus interface and is available with or without an Adapter Board. With the Adapter Board, the ProDrive can plug directly into a 16-bit expansion slot on an AT compatible computer. Without the Adapter Board, the drive is compatible with other AT-Bus architectures and can be plugged into an embedded AT Adapter or existing Adapter Board.

ADAPTER BOARD

The Adapter Board is an IBM PC AT I/O bus-compatible interface. The I/O extended bus connector is required for data bus D8-D15, IRQ14 and IO CS16. The Adapter Board buffers data and control signals between the drive and the host system, and performs address decoding of the Host Address Bus. The Task File Registers, which accept commands from the host system BIOS, are located on the drive itself.

NOTE: Some host systems will not read the STATUS register after the drive issues an interrupt. In such cases, the interrupt will

not be acknowledged. A jumper option is provided on the Adapter Board to overcome this problem. This jumper allows interrupts to be controlled by the drive’s interrupt logic. See jumper option J2.

AT-BUS INTERFACE CHARACTERISTICS

The AT-Bus interface supports one or two hard disk drives per adapter board, and will accomodate two adapter boards for a total of four drives. Regardless of the number of drives, there is a master/slave relationship between the host and the drive. The drive always maintains control of the bus; there is no arbitration.

ELECTRICAL CHARACTERISTICS

All signals are TTL compatible with a logic one being greater than 2.0 volts but less that 5.25 volts, and a logic zero being greater than 0.0 volts but less than 0.7 volts.

B-8

PC40III SERVICE MANUAL

AT-BUS INTERFACE SIGNALS The AT-Bus interface connector is a 40-pin shrouded connector with two rows of 20 male pins on 100 mil centers. The connec

ting cable is a 40-conductor flat ribbon with a maximum length of 18 inches. Table 1 describes each signal on the AT-Bus

interface. Refer to Table 1 for the AT-Bus interface pinouts and their relationship with the AT system bus.

NOTE: The direction Table 1 is in reference to the drive, i.e., IN means to the drive. PINS are in reference to the 40-pin

AT-Bus connector.

TABLE 1 — AT-Bus Interface Pin Assignments

SIGNAL NAME DIR PIN

DESCRIPTION

- HOST RESET

IN 1

Reset signal from the host system; active low during system power-up.

GROUND

2

Ground between host system and drive. HOST DATA D0-D15

I/O 3-18

16-bit bi-directional data bus between the host and the drive. D0-D15 are used to transfer 8-bit information for register and ECC READ/WRITE. Data Bit D7 is disabled when the host reads the digital input register. These are tri-state lines with 24mA drivers.

GROUND

19

Ground between host system and drive.

KEY

20

Unused pin for keying ribbon cable to the drive.

- HOST IO CH RDY

OUT

21 Enables host wait state generation to lengthen the I/O read and write cycles.

Driven low by the drive immediately upon detecting a valid I/) address select.

GROUND 22 Ground between host system and drive.

- HOST IOW

IN

23

Write strobe. Clocks data from the O F-HO ST to the drive over data lines D0-D7 and/or D8-D15 on the rising edge of HOST IOW.

GROUND

24

Ground between host system and drive.

- HOST IOR IN

25

Read strobe. Clocks data from the drive to host data lines D0-D7 and/or D8-D15 on the rising edge of -HO ST IOR.

GROUND 26 Ground between host system and drive. RESERVED

27

Reserved for future definition.

HOST ALE

IN 28

Address Latch Enable from the host. Not currently used, but provided to main tain compatibility.

RESERVED 29 Reserved for future definition. GROUND

30 Ground between host system and drive.

HOST IRQ14

OUT

31

Interrupt signal to the host. Active only when the drive is selected and the drive interrupt enable bit is high. Goes to a high impedance state when the drive is not selected or the interrupt enable bit is low. The interrupt is cleared upon receiving the next command, when the status register is read or when the drive is reset.

-HOST IO CS16

OUT 32

Informs the host that one of the drive registers has been enabled and that the drive is prepared to perform a 16-bit I/O transer. Open collector output with 24mA driver.

HOST ADDR 1

IN

33

Address line from the host to the drive that is used to select a register on the

drive.

GROUND 34

Ground between host system and drive.

HOST ADDR 0

IN 35

Address line from the host to the drive that is used to select a register on the

drive.

HOST ADDR 2

IN

36

Address line from the host to the drive that is used to select a register on the

drive.

- HOST CSO

IN

37

Decoded address select from the host indicating that access to one of the 8

task file registers is desired.

-HOST CS1

IN

38

Decoded address select from the host indicating that access to one of the 3

diskette function registers is desired.

- HOST SLAVE

OUT

39

Indicates the presence of a second drive. When this signal is low, a second

drive is present. Open collector output with 24mA driver.

GROUND

40

Ground between host system and drive.

B-9

PC40-III SERVICE MANUAL

AT SYSTEM BUS SIGNALS

The table below presents the signals on the AT system bus that are used by the AT-Bus interface for the AT-Bus interface pinouts and their relationship with the AT system bus.

NOTE: The direction in Table 2 is in reference to the host system, i.e., IN means to the host system

40-pin AT system bus connector.

TABLE 2 — AT System Bus Pin Assignments

SIGNAL NAME

DIR PIN DESCRIPTION

SA0-SA9

OUT

A22-A31 System address bus

SD0-SD15 I/O A2-A9 &

C11-C18

System address bus

AEN OUT All Signal indicating a DMA address is on the system address bus. Active when

high.

-IO W

OUT

B13 Signals that the enabled I/O device should read the data on the data bus.

Active when low.

- IOR OUT

B14

Signals that the enabled I/O device should gate data onto the system data bus. Active when low.

BALE OUT

B28 Indicates a valid system address is available. Active when changing from

high to low.

IRQ14

IN D7

System interrupt request indicating an I/O device needs attention. Active when changing low to high.

RESET OUT B2

Used to reset or initialize system hardware at power up. Active when high.

-IO CH RDY IN

A10 Pulled low during a bus transaction by an enabled I/O device to lengthen

the read/write cycles. Open collector onto host bus.

. You should refer to Figure

. PINS are in reference to the

AT-Bus Interface Pin Assignments

DISK CONNECTOR AT BUS CONNECTOR

PIN NO SIGNAL NAME

DIRECTION

PIN NO SIGNAL NAME

1

-HOST RESET

<— INV

B2

RESET DRV

2

GROUND GROUND

3

HOST DATA 7

A2

SD7

4

HOST DATA 8

Cll SD8

5

HOST DATA 6

A3 SD6

6

HOST DATA 9

◄—►

C12

SD9

7

HOST DATA 5

A4

SD5

8

HOST DATA 10

C13 SD10

9

HOST DATA 4

A5

SD4

10 HOST DATA 11 C14

SD11

11

HOST DATA 3 A6

SD3

12

HOST DATA 12

C15

SD12

13

HOST DATA 2

A7 SD2

14

HOST DATA 13 C16

SD13

15

HOST DATA 1 A8

SD1

16

HOST DATA 14

C17 SD14

17

HOST DATA 0 A9 SDO

18

HOST DATA 15 C18 SD15

B -1 0

PC40-III SERVICE MANUAL

AT-Bus Interface Pin Assignments (continued)

DISK CONNECTOR AT BUS CONNECTOR

PIN NO SIGNAL NAME DIRECTION

PIN NO SIGNAL NAME

19 GROUND

____

GROUND

20

KEY

NO CONNECTION

21 -HOST IO CH RDY

*

A10

-IO CH RDY

22 GROUND

—

GROUND

23

-HOST IOW

<—

B13

-IOW

24 GROUND

— —

GROUND

25 -HOST IOR

*

B14

-IOR

26 GROUND

— —

GROUND

27

RESERVED

NO CONNECTION

28

HOST ALE

*—

B28 BALE

29

RESERVED

NO CONNECTION

30 GROUND

—

GROUND

31

HOST IRQ 14

*

D7 IRQ14

32

-HOST IOCS16

*

D2

-IOCS16

33

HOST ADDR 1

< —

A30 SA1

34

GROUND

— —

GROUND

35

HOST ADDR0

*—

A31

SA0

36 HOST ADDR2

<

A29 SA2

37

-HOST CSO

38

-HOST CS1

39

-HOST SLV

40

GROUND

— —

GROUND

NOTES: All grounds are connected together on the ground plane of the adapter board.

-HOST CSO, -HOST CS1 and -HOST SLV are generated on the adapter board; there are no directly related AT-Bus signals.

Recommended [1]

Connectors

CABLE CONNECTOR

DESCRIPTION DC POWER PLUG DC POWER PIN I/O CONNECTOR

DISK DRIVE [2] CONNECTOR AMP 1-4807222-0 AMP 350079-4 BURNDY FRHL40R-2

[1] THESE NUMBERS ARE FOR SIZE REFERENCE ONLY [2] PROVIDED BY DRIVE VENDOR [3] PROVIDED BY COMMODORE

HOST (CPU) [3] CONNECTOR AMP 1-480424-0 AMP 350078-4 BURNDY FRS40BD-8P

B -l 1

PC40-III SERVICE MANUAL

I/O INTERFACE CIRCUIT

NOTE: Wiring shall be ribbon cable or twisted pair.

DIMENSIONS ARE IN INCHES

FIRST POSITION

B

h

GROUND CIRCUIT

NOTE: Wiring shall be ribbon cable or twisted pair.

AC GROUND FRAME GROUND

CBM PART NUMBER

DESCRIPTION

VENDOR

03 324594-02

TERMINAL 4.6 X 0.3 DIN 46247 WEITKOWITZ 44113

05

903451-10

TERMINAL RING TONGUE 0 4.3 DIN 4623

MOLEX AA

06

905451-01

TERMINAL RING TONGUE 0 3.2 DIN 46234

07

903733-10

LEAD WIRE STRIPLENGTH 2 X 3 MM

08

903753-10

LEAD WIRE AWG 18 BLACK L = 60 MM

09

906475-05

TUBEHEAT SHRINK

B -12

PC40-III SERVICE MANUAL

PC40-III FLOPPY DISK DRIVE — 380825-01 (Dark Bezel); 380825-02 (Light Bezel)

SCOPE

This specification describes 5-14 " double-sided 96-TPI minifloppy disk drive (hereafter abbreviated as FDD) CHINON FZ-506.

FEATURES

The features of the FZ-506 are as follows: (1) Large Capacity Up-to 1.6M bytes

The FZ-506 is a double-sided, high-density, double-track type and its capacity is 1.6M bytes, in unformatted mode. The read/write selection of the high density 1.6M bytes, 96 TPI and double density 1M bytes, 96 TPI disk can be carried out by changing either the motor speed (360 rpm/300 rpm) or transfer rate (500K BPS/300K BPS). In addition, as the data retrieval from 250K bytes, 48 TPI disk to 500K bytes, 96 TPI disk is possible, the former software packages can be read.

(2) Pop-up Mechanism

With the newly employed pop-up mechanism, the disk can be loaded/unloaded with ease, preventing mischucking at disk insertion.

(3) Low Power Consumption

As a newly designed LSI (C-MOS chip) is employed in the read/write and control circuits, high performance and low power consumption are achieved. In stand-by mode, power consumption is only 1.59W, and in operation mode 3.81W, making system design easy.

(4) Built-in Disk-in sensor

With the built-in disk-in-sensor, when no disk is loaded, the motor is stopped. This extends the motor service life and reduces power consumption. When chucking the disk, the DD motor is rotated temporarily to assure the centering of the disk. DISK CHANGE signal will be output by the sensor, also.

(5) Various Disk Readings

With the FZ-506, the various disk readings shown below are possible, existing software written in 48 TPI format can be used without any conversion.

Disk Used

Normal Density

High

Density

Track Density

48 TPI

96 TPI

Storage Capacity

250 KB 500 KB 500 KB 1 MB

1.6 MB

Rate of Data

Transfer

250K/300K

BPS

250K/300K

BPS

250K/300K

BPS

250K/300K

BPS

500K BPS

Rotational Speed

300/360

rpm

300/360

rpm

300/360

rpm

300/360

rpm

360 rpm

Data Read

o o

o

Data Write

*o

o

* Data can be read by this drive, but data can not be read by a head made solely for 48 TPI use.

B-13

PC40-III SERVICE MANUAL

SPECIFICATIONS Specification (1)

Item

CHARACTERISTIC

HIGH DENSITY

NORMAL DENSITY

Recording mode

FM MFM

FM

MFM

Storage capacity

Unformatted

Per disk 833 KB 1666 KB 500 KB

1000 KB

Per track 5.208 KB

10.416 KB 3.125 KB 6.25 KB

Formatted

Per disk 615 KB

1229 KB 368.640 KB 737.280 KB

Per track 3840 B 7680 B

2304 B 4608 B

Number of sectors

15 16

Per sector

256 B 512 B 128 B

256 B

Recording density

4935 BPI

9870 BPI

2961 BPI

5922 BPI

Rate of data transfer 250K BPS 500K BPS

125K/150K

BPS

250K/300K

BPS

Access time

Power-on to ready time

0.5 sec or less

Single track seek time

3 msec

Average access time

94 msec Settling time 15 msec Average latency time 83.3 msec 100 msec/83.3 msec

Rotation speed 360 rpm

300/360 rpm

Number of tracks

160

Number of cylinders

80

Track density

96 TPI

Number of heads

2

Number of index

1

Radius of track

Outer track

Side 0

57.150 mm

Side 1 55.033 mm

Inner track

Side 0 36.248 mm Side 1 34.131 mm

B -1 4

PC40-I1I SERVICE MANUAL

Specification (2)

Item

Specification

Physical dimensions

146 (W) x 41 (H) x 193 (D) mm

Weight

approx. 1 kg

Power supply

DC+12 V ±5% DC +5 V ± 5%

Power consumption

^

+5 V +12 V

POWER

Stand-by 290 mA TYP. 14 mA TYP.

1.62 W TYP.

Read

330 mA TYP.

200 mA TYP.

4.05 W TYP.

Write

330 mA TYP. 210 mA TYP.

4.17 W TYP.

Seek 260 mA TYP.

440 mA TYP. 6.58 W TYP.

Spindle Motor Starting current (0.5 sec. max.)

900 mA MAX.

Ripple voltage allowance

DC +12 V Less than 150 mVp-p (including spike noise) DC +5 V

Less than 100 mVp-p (including spike noise)

Noise

Less than 55 phons (class A) (separated from the drive by 1 m)

Cabinet specifications

Front panel

Material: ABS Color: Beige

Front lever

Material: ABS Color: Beige

B-15

PC40-III SERVICE MANUAL

Installation Conditions

Item

Specification

Mounting position

Horizontal Vertical

In horizontal position, the front panel can be raised a maximum of 15°

Temperature

During operation

5 ~ 45 8C

During non-operation

0 ~ 50°C

During storage

-2 0 ~ 608C

Humidity

During operation

20 ~80 % RH Maximum wet bulb temperature 29°C During non-operation 5 ~ 90% RH No dew condensation During storage 8 ~ 90% RH No dew condensation

Environment conditions

Temperature change

1 58C/H

During operation

Continuous vibration

Amplitude Less than 0.5 mm 5 ~ 25 Hz

0.25G 25 ~ 100 Hz

Single vibration

Less than 10G (10 ms)

During non-operation

and storage

(W/Protect sheet)

Continuous vibration

Amplitude Less than 7 mm 5 ~ 9 Hz

0.5G9 ~ 100 Hz

Single vibration Less than 30G (10 ms)

Vibration

Drop shock

Fall height in packing State: 70 cm (corner: one time, sides: three times, flat surfaces: six times)

B -16

PC40-III SERVICE MANUAL

Reliability

Item Specification

Drive

MTBF

10,000 POH

MTTR 0.5 H

Drive life Five years

Error rate

Software errors

10*9 times/bit

Hardware errors 10"12 times/bit

Seek errors 10'6 times/seek

Life

Drive

Number of mountings of the media

30,000 times or more

Seek

10,000,000 seeks or more

Head

10,000 H or more CO Q)

2

Number of identical track passes

3,000,000 passes or more

Number of mountings 10,000 times or more

* Maintenance is not required under normal use conditions. *1 Reference value

B-17

149+0.5

PC40-III SERVICE MANUAL

DIMENSIONS

B -18

PC40-III SERVICE MANUAL

INTERFACE SIGNALS

The interface signal has 12 input signal lines and 5 output signal lines.

Signal Voltage Levels

The interface signal interfaces with the controller at the TTL level. For all signals, low is true. The I/O signal level into the drives have the following specifications. (1) Input level OV to + 0.40V

High level + 2.40V to + 5.25V Input impedance 15012

(2) Output signal

Low level 0V to + 0.40V High level + 5.25V max. (by receiving the end terminator) Output current (for low level) 48 mA (max.) Output current (for high level) 250

fiA (max.)

Input Signals

(1) DRIVE SELECT 0 to 3 signal lines

When one of these signal lines goes into low level, the drive corresponding to the signal line is selected and the I/O gate is opened. Up to four drives can be controlled using these four signal lines. The drive corresponding to one of the DRIVE SELECT 0 to 3 signal lines is determined by the position of the short plug in the drive.

(2) MOTOR ON signal line

This line controls the ON/OFF of the spindle motor. When this signal line is set to low level, the spindle motor revolves. When it is set to high level, it stops. 0.5 seconds is the required start up time of the spindle motor. The motor start operation is not executed when no disk is loaded. This signal operates independently of the DRIVE SELECT signals.

(3) DIRECTION SELECT signal line

This signal determines the direction of movement of the head when a pulse is sent via the STEP signal line. When this signal line is set to low level and the STEP signal pulse is sent, the head moves towards the center of the disk. When it is set to high level and the STEP signal pulse is sent, the head moves away from the center.

The logic level of this signal should be held for at least 1 microsecond after the trailing edge of the STEP pulse.

(4) STEP signal line

This signal line moves the head. With the rise of a single low level pulse, this signal line changes from LOW level to HIGH level and the head moves one track in the direction determined by the DIRECTION SELECT signal.

However, this signal is not accepted when the FDD is in WRITE mode. The head is stabilized 20 ms after the trailing edge of the last STEP pulse, and the FDD is ready for data read/write operation.

(5) WRITE GATE signal line

This signal line specifies drive write and read status. When this signal line is set to low level, write enable status occurs and the data is stored on the disk surface by the WRITE DATA signal. When this signal line is set to high level, read status occurs.

After the writing operation, a period of 1.2 ms is necessary before a valid READ DATA signal appears on the interface.

(6) WRITE DATA signal line

Data written on the disk surface is transferred on the signal line. With the decline of the pulse sent to this signal line

(when the signal line changes from the high level to the low level), data is written on the disk surface.

(7) SIDE SELECT signal line

This signal line selects the head. When this signal line is set to high level, the side 0 head is selected; when it is set to low level, the side 1 head is selected.

Side 0 stands for the one-sided medium recording surface.

The selection is completed 100 microseconds after the change of the SIDE SELECT signal line, and read/write becomes

possible.

(8) MODE SELECT signal line

This signal status selects’either 1.6M Byte mode or 1M Byte mode. The line can be configured in positive or negative logic by position of short plug.

B -1 9

PC40-III SERVICE MANUAL

Output Signals

(1) INDEX signal line

Whenever the disk rotates once, this signal line outputs a low level pulse indicating the start of the track. A decline of the pulse signal (when this signal line changes from high level to low level) indicates the start of the track. However, the pulse is only output when the disk is inserted.

(2) TRACK 00 signal line

When this signal line is set to low level, the head is located at the track 00 position and the specific phase of the stepping motor is excited.

(3) WRITE PROTECT signal line

When this signal line is set to low level, the inserted disk cannot be written on. This signal line may also be set to low level even when no disk is inserted in the drive. The write function of the drive becomes inoperative when write-inhibited disk is inserted.

(4) READ DATA signal line

This signal line is used for the transfer of the pulse series read from the disk, in which clock pulses and data pulses are mixed. The negative-going edge (the moment of change from high level to low level) of the pulse output at this signal line indicates the readout data (clock and data pulses).

(5) READY signal line

When this output signal line is set to low level, the disk is inserted and the number of disk rotations is fixed. When the READY signal is ON, read and write operations can be performed on the disk. Immediately after the MOTOR

ON signal is turned ON, power is supplied. After the disk is inserted, check that the READY signal is ON before perfor

ming write and read operations.

(6) DISK CHANGE signal

This signal line is set to low level by power on or when a disk is ejected, and set to high level by STEP signal input

when a disk is loaded.

POWER ON

DISKIN

DISK CHANGE

STEP

u

B -2 0

PC40-III SERVICE MANUAL

Input Signal Line Terminator

The FZ-506 is operable with either daisy chain or star chain systems. It is possible to use 4 pcs. Drives by daisy chain. When more than one drives are connected, termination resistors of all drives except the drive at the end of interface cable must be disconnected. (The termination resistors can be disconnected by taking away the short-plug at the connector J 1 -1) Each of the input signal lines has a 150fl terminal resistor.

Interface Circuit

(1) Drives-receivers When recommend the following drivers-receivers.

+5V

(2) Wire material Flat cables or twisted pair wires

B-2 1

PC40-II1 SERVICE MANUAL

CONTROLLER SIDE

DRIVE SIDE

MODE SELECT

IN USE/H EAD

LOAD

4

DRIVE

SELEC T

3

6 '

DRIV E

SEL E CT

0

10

DRIV E

SEL E CT 1

12

D R I V E

SELE CT

2 14

MOTOR

ON

16

DIR E C TI ON SELECT

18

STEP

20

WRITE

DATA

22

WR IT E

GATE

24

SIDE SELECT

32

26 TRACK

0 0

28

WR IT E

PROTECT

30

READ

DATA

34

READY

* (DISK CHANGE)

■M2 V DC

©

DC GROUND

-M 2 V

RETU RN

©

+ 5 V

RETURN

+

5 V DC

©

IND E X

* possible to change with J1

100 xn.

771

SIG N A L GROUND

0.01>jF

AC GROUND FRAM E GROUND

B -2 2

PC40III SERVICE MANUAL

POWER-ON SEQUENCE

Recalibration of the head position is performed during the power-sequence of the FDD. The figure below shows the power-on sequence.

600ms

max

POWER-ON SEQUENCE

POWER SUPPLY INTERFACE Power Supply Specifications

The DC power (+ 12V, + 5V) shown in Specification is required by the power supply. There are four power lines ( + 12V,

+ 5V, and the two return lines).

Frame Ground

The frame ground and signal ground are connected through a capacitor and a resistor. The values are as follows:

R = 100 kO C = 0.01/iF

Connect the frame ground where the AC ground and DC ground are one point connected in the host system.

Power Supply Sequence

(1) The power ON sequence is not specified. However, the time in which the supplied power voltage rises up to 90% of

the specified value, should be set to 100 ms or less.

(2) If the drive is in a status other than write operation, and the DC power is disconnected, the disk and the data stored

on the disk are not destroyed. However, its contents will be destroyed if the WRITE GATE is not set to high level.

B-23

PC40-III SERVICE MANUAL

INTERFACE CONNECTOR AND PIN ASSIGNMENT Interface Connector

(1) DC power connector

Drive Side

Host Side

Connector/housing AMP 172349-1

or equivalent

AMP 1-480424-0

or equivalent

Pin — AMP 60619-1

or equivalent

(2) Interface signal connector

Drive Side

Connector

Card Edge

Connector

Pin Assignment

The assignment of each pin is shown. This diagram shows the back of the drive.

PJ1 (I/O Connector) PJ2 (Power Connector)

4 3 2 1

PIN ASSIGNMENT

B - 2 4

PC40-III SERVICE MANUAL

(1) DC Power connector

Pin number

Signal

1 + 12V DC

2 + 12V RETURN

3

+ 5V RETURN

4

+ 5V DC

(2) Interface signal connector

Pin number

Signal Pin number

Signal

2 MODE SELECT

1 GND

*1 4 IN USE/HEAD LOAD

3 GND

6 DRIVE SELECT 3

5

GND

8 INDEX 7

GND

10 DRIVE SELECT 0

9 GND

12 DRIVE SELECT 1

11 GND

14 DRIVE SELECT 2

13 GND

16 MOTOR ON

15

GND

18 DIRECTION SELECT 17

GND

20 STEP

19

GND

22

WRITE DATA 21 GND

24

WRITE GATE

23

GND

26

TRACK 00

25

GND

28

WRITE PROTECT 27

GND

30

READ DATA

29 GND

32 SIDE SELECT

31

GND

*2 34 READY/DISK CHANGE

33

GND

GND: SIGNAL GROUND

*1: “ HEAD LOAD” is optional. *2: As for switching over between READY and DISK CHANGE,

see paragraph 9; SHORT PLUG.

B -25

SHORT PLUG AND FRONT LED Short Plug

The assignment of each pin is shown.

PC40-III SERVICE MANUAL

FRONTSIDE

J1

CONTROL PCB

/

± 3

oooo.......................................oo

13 1211,10

This diagram shows the side of the drive.

.....................................

SHORT PLUG

2,1

CHINON FZ-506 high density 1.6 MB to 1 MB switchable floppy disk drive can be configured in several modes of operation using “ SHORT-PLUGS” according to the table below.

Connector “J l”

Mode descriptions

1 2 3 4 5

6 7 8 9 10 11

12 13

1.6 MB to 1 MB variable speed switchable using Pin #2 as change-over signal input Pin #2: High = 1.6 MB (360 rpm)/Low = 1 MB (300 rpm)

*1 Pin #2: High = 1 MB (300 rpm)/Low = 1.6 MB (360 rpm)

1.6 MB to 1 MB switchable at 360 rpm, IBM PC/AT compati

ble, Pin #2 as change-over input

Pin Wl: High = 1.6 MB (360 rpm)/Low = 1 MB (360 rpm) *2

o o — — — o o — — —

o — o — — o — — o — 0 — 0

-------

o — o —

o —

o — o —

—

o — — o

o — o — o —

o —

o — — o

— o — o

1.6 MB 360 rpm non-switchable (Disregards pin #2 signal

o o — — — o —

o —

— —

o —

*1. The short-plug is factory set at this position. 12: READY *2. PC40-III Close 1, 3, 6, 10, 13 13: DISK CHANGE

“O” = Position closed “—” = Position open

Note: Position 1 through 5 of the “Jl” are designated as follows.

POS. 1: Connect the termination resistors when closed POS. 2: Configure the drive as “ DRIVE 0” when closed POS. 3: Configure the drive as “DRIVE 1” when closed POS. 4: Configure the drive as “ DRIVE 2” when closed POS. 5: Configure the drive as “ DRIVE 3” when closed

Note: Only one of the positions 2 through 5 of “ J l” can be closed. Above example demonstrates in the case of

“ DRIVE 0” and the termination resistors connected. PIN #2: Card-Edge Connector (PJl)-2

Front LED The front LED lights when the DRIVE SELECT signal selected by the short plug is set to low level.

B -2 6

PC40III SERVICE MANUAL

Handling of Connectors

(1) Types of connectors

1. PJ1 : Interface connector (34-pin, card-edge type)

2. PJ2 : Power connector

3. PJ3 : Stepping motor connector

4. PJ4, 5 : Head connectors

5. PJ6 : DD motor connector and track 00 sensor connector

6. PJ7 : Disk-in sensor connector

7. PJ8 : Frond LED connector and index, write protect sensor connector

8. J 1 : Short pin connector (13-pair) for drive selection

(2) Removal of connector wire

Be sure that power switch is turned off whenever inserting or removing the connector wire, etc. Pull out the connec tor wire can be removed from the connector on the PC board.

(3) Insertion of connector wire

Each connector wire should be set in a proper position as shown in Fig. Also, as each wire has a stripe on one side make sure to insert so that the striped side is the same side as the pin no. 1 of the connector.

(4) Insertion of head FPC

Side 0 and side 1 of the head FPC are shown in Fig. Make sure to properly insert side 0 FPC into connector PJ4 of control PCB and side 1 FPC into connector PJ5.

W/P SENSOR

INDEX SENSOR

DD MOTOR

TRACK 00 SENSOR

PJ2

J

1

DISK-IN SENSOR

PJ 5 PJ4

STRIPE

g i n

in

B-27

PC40-III SERVICE MANUAL

Functions of Test Points

The following eight test points (with GND) are provided on the control board, each of which is used in observing the waveform

for FDD adjustment or check.

(1) TP1, TP2 (pre-amp output) and TPC (analog GND)

These are the test points of the read amp output. Amplified about 200 times by pre-amp, the signal from the head can be observed at TP1 and TP2 through LPF. TP1 and TP2 are 180° phase off (inverted phase).

For accurate waveform observation, it is necessary to add the signals of both channels together (the signal of the one channel is inverted in phase) to observe these signals as one waveform using an oscilloscope with two channels. TP3 is used in grounding the oscilloscope. TP1 and TP2 are used in checking the read/write head for its different characteristics or in checking and adjusting the tracking alignment, and the index burst timing.

(2) TP4 (read data signal)

This is the test point of the read data pulse. The READ DATA signal appears here. In FM mode, a data signal with 2F or IF period is observed, while MFM mode, a data signal with 2F, 1.5F or IF

period is observed. (See Table)

This test point is used in check of asymmetry.

Mode

Frequency

1 MB

1.6 MB

2F

4 fis

2 (xs

1.5F

6 fis 3 [is

IF

8 fis 4 fis

(3) TP5 (index sensor)

This is the test point of the index sensor photo-transistor output. A waveform with soft leading and trailing edges

appears here, since the sensor output signal is taken out before flowing across the Schmitt inverter. Here it is necessary to check that the output voltage of the index sensor is normal (with no waveform split).

(4) TP6 (write protect sensor)

This is the test point of the write protect sensor photo-sensor photo-transistor output. The WRITE PROTECT out

put signal appears here. With a disk in which a measure for write protection is taken (its notches are masked), it becomes low level.

The voltage at this test point should be more than 3 V in the write enable state (the notches are open) and less than

0.5 V in the write protect state. This test point is used in check of the write protect sensor.

(5) TP7 (Disk-in sensor)

This is the test point of the disk-in sensor photo-transistor output. This signal becomes low level when a disk is inserted into the FDD.

(6) TP8 (track 00 sensor)

This is the test point of the tract 00 sensor photo-transistor output. The voltage at this test point should be within the range shown in the Figure on the following page.

B -28

PC40-III SERVICE MANUAL

Mo re than 3.0V

Adjust so that the level of the sensor output changes between track 01 (Low level) and track 03 (High level)

TEST POINTS AND CONNECTORS ON THE CONTROL PC BOARD ASSY.

NOTE: When the various signals are extracted, proper test pin should be mounted at the test point since the test point is

not equipped with the test pin. Sufficient caution should be taken for the mounting of test pin and wiring of signal lines because it may cause damage if test pin and other places are short circuited.

INSTALLING THE OPTIONAL COMMODORE 910 and 920 FLOPPY DRIVES

In addition to following the general installation instructions given in the manuals for the Commodore 910 and 920 floppy

drives the user must also perform the specific procedures for PC40-III installation described below.

Commodore 910 Floppy Drive

To install the Commodore 910 3.5 inch 720Kb drive as Drive B: in the PC40-III, the user must do the following:

• Set the drive select jumper to position I.

• The M jumper should be in position 5.

• The R-D jumper should be in position 6.

• The first time you power up, use the Setup utility to identify your second drive (Diskette 2 on the menu) as a 720Kb 3.5

drive.

Commodore 920 Floppy Drive

To install the Commodore 920 5.25 inch 360Kb floppy drive as Drive B: in the PC40-III, the user must do the following:

• Set the drive select jumper to position 1.

• Cut JP6 (located on the bottom side of JP1) in half.

• The first time you power up, use the Setup utility to identify your second drive as a

360Kb 5.25 drive.

B -29

Commodore PC40-III a

Specifications and Main Features

Frequently Asked Questions

User Manual