Commodore PC-40 III Service Schematic Manual

SERVICE

PC40-II

MANUAL

v"

commoclore

COMPUTERS

SERVICE

PC40-IH

MANUAL

MARCH,

Commodore

1200

Wilson

.

- . accuracy

1989

CBM

(NOT

Drive,

Commodore
ranties
herein.

anasis

liable
in

connection
tained
ment

a

recommendation,

quality

Reproduction
of

editorial

prohibited.

with

The

basis,

is

for

any

herein.

part

or

West

information

with

herein

suitability

or

PN-314134-01

INTER-COMPANY

FOR

Business

Chester,

makes

regard

and

the

the

consequential

with

The

listing

does

or

use

pictorial

no

expressed

to

the

is

entire

user.

the

use

not

warranty

of

without

content,

RESALE)

Machines,

Pennsylvania

or

information

made

available

risk

as

to

Commodore

or

incidental

of

the

information

of

any

available

constitute

or

guaranty

such

replacement

expressed

in

any

implied

19380

war-

contained

solely

quality

shall

in

permission,

and

not

damages

con-

replace-

any

case

as

part.

matter

Inc.

U.S.A.

on

be

to

is

This

manual

of

this
transmitted
photocopying,

sion

of

Copyright © 1989

All

rights

contains

publication

in

any

recording

Commodore

reserved.

copyrighted

may

be

form

or

Electronics

by

Commodore

and

reproduced,

or

by

any

otherwise,

Limited.

proprietary

stored

means,

without

Electronics

information.

in a retrieval

electronic,
the

prior

written

Limited.

No

part

system,

mechanical,

or

permis-

PC40-III

SERVICE

MANUAL

TABLE

SECTION 1 —

SECTION 2 —

SECTION 3 —

SECTION 4 —

SECTION 5 —

APPENDIX

APPENDIX B —

APPENDIX

APPENDIX

OF

SPECIFICATIONS

THEORY

TROUBLESHOOTING

PARTS

IC

A

—

C

—

D

—

CONTENTS

OF

OPERATIONS

PINOUTS,

POWER

DISK

KEYBOARD

OPTIONS

DRIVES

SCHEMATICS

SUPPLIES

GUIDE

APPENDIX

E

—

TECHNICAL

UPDATES

PC40-II

SERVICE

MANUAL

SECTION

1

SPECIFICATIONS

DESCRIPTION
This

specification

control

an

unit

and

independent

describes

keyboard.

unit

and

the

Functional

This

must

system

be

VGA

Requirements

is

compatible

compatible.

for

with

the

the

PC40-III

IBM

computer.

AT

series

PC40-IH

This

of

computers.

system

SERVICE

consists

The

monitor

MANUAL

of a processor,

for

the

memory,

system

is

STANDARD

FEATURES

MICROPROCESSOR
SPEEDS

MEMORY

VIDEO
VIDEO

PARALLEL

SERIAL
MOUSE

AutoConfig

BATTERY

EXPANSION

DISK

112

WATT

OPTIONAL

Math

Disk

1

40

1

5.25”

l

unused

Either

CAPACITY

OUTPUT

DISPLAY

OUTPUT
OUTPUT
PORT

BIOS

BACKED

STORAGE

POWER

FEATURES

Coprocessor

and

Tape

MByte

or

1.2

hard

MByte

slot

both

that

SLOTS

80287.

storage

disk

floppy

can

floppy

RAM

UP

SUPPLY

drive

be

drives

CLOCK

inside

drive

used

may

80286
6,

8,

1

MByte

Video

256

KByte

Centronics

RS-232

Commodore

Mouse

3

AT

1

XT

40

MByte

(AT

1.2

MByte

the

case.

accessible

for a second

be

3.5”

drives.

12

MHz

on

Graphics

IBM

style slots
style

hard

style

drive

from

the

floppy

user

selectable

board

Array

(IBM)

Compatible

Compatible

1352

mouse

slot

disk

(formatted)

with

embedded

Floppy

front

Disk

of

or a streaming

compatible

Hardware

controller)

(formatted)

the unit.

tape

Horizontal

and

Software

unit.

scan

frequency

Compatible

31.5

with

KHz

Microsoft

Bus

Expansion

The

the

AT

The

VIDEO

three

full

on

one

XT

FEATURES

slots

length

the

after

expansion

ALPHANUMERIC
MODE

0,1

2,

7

54
55
56
57

IBM,

AutoConfig

3

AT

#

and

XT

are

is a registered

COL X ROW

40 X 25

80 X 25

80 X 25

132 X 43
132 X 25
132 X 43
132 X 25

registered

expansion

sale

market

slot

MODES

trademarks

trademark

is

for

of

Commodore

slots

are

short

CHAR

8X8

9X

8X8

9X
9XxX14
9X

7X9
7X16
7X9
7X

of

International

conform

available

cards

MATRIX

16

16

16

16

Business

Business

to

the

on

that

Machine.

standard

this

unit.

do

Machine.

AT

not

require a full

RESOLUTION

320 X
360 X

200

400

640 X 200

720 X 400
720 X 350
720 X 400

924 X 387
924

X 400

924 X 387
924 X 400

bus

structure,

length

therefore,

slot.

all

options

COLORS

16
16

OF

256K

16
16

OF

256K

MONOCHROME
MONOCHROME

COLOR
COLOR

MONOCHROME
MONOCHROME

that

are

available

STANDARD

CGA

(1)

VGA

(2)

CGA

(I)

VGA

(2)

MDA

VGA

(2)

ENHANCED
ENHANCED
ENHANCED
ENHANCED

for

1-1

PC40-III

SERVICE

MANUAL

GRAPHICS

MODE

#

4,5

6

D

E

F

10
11
12
13

NOTES

(1)

All

200

(2)

The

VGA

VIDEO

Vertical

Resolution

350

400
480

600

SIGNALS

lines
lines
lines
lines*

MODES:

line

modes

implementation

Horizontal

Frequency

31.5

KHz

31.5

KHz

31.5

KHz

35.2

KHz

RESOLUTION

320 X 200

640 X 200

320 X 200

640 X 200
640 X 350
640 X 350
640 X 480
640 X 480

320 X 200

are

double

of

scanned

these

sync

Polarity

+

_
_
_

for

modes

COLORS

4

4

OF

2
2

OF

16

OF

16

OF

MONOCHROME

16

OF

2

OF

16

OF

256

OF

400

line

is

the

default.

Vertical

Frequency

70.1

Hz

70.1

Hz

59.9

Hz

56.2

Hz

256K

256K

256K
256K

256K

256K

256K

256K

resolution.

sync

Polarity

-

+

_
_

STANDARD

CGA

(I)

VGA

(1) & (2)

CGA

VGA

(1)&

VGA

(I)

VGA

(I)

VGA
VGA
VGA/MCGA
VGA
VGA/MCGA

(2)

(1)

*Requires

BLOCK

Standard

640

384

The

MEMORY

KBytes
KBytes

top

384

an

Memory

range 0 to
range

KBytes

KEYBOARD

standard

optional

Special

Germany,

keyboards

Spain,

ADDITIONAL

OTHER

Security

Built

External

Battery

Metal

FEATURES

lock

in

speaker

Configuration

backed-up

Case

(can

Analog

MultiSync

MAP

655360

1048576

of

memory

FEATURES

United

International

Dvorak

States

and

drivers

France,

FEATURES

Numeric

4

cursor

for

keypad

keys

keyboard

real

support

switches

time

compatible

decimal

to

1441792

can

ASCII

are

available

Italy

and

in

an

inverted T formation

lock

out

clock/calendar.

monitor)

be

102

the

monitor.

(Oh

to

decimal

disabled

101

key

to

United

9FFFFh)

(100000h

to

function

customize

Kingdom.

to

160000h)

the

with

third

keyboard

party

for

add

the

on

boards.

following

countries.

MultiSync

is a registered

trademark

of

NEC

PC40-III

SERVICE

MANUAL

SPEED

One

Default

Control
Control
Control

PHYSICAL

Height

Depth

Width
Weight

Minimum

Right

Back

ENVIRONMENT

Operational

Non-Operate

Non-Operate

SELECTION

of

the

three

operating

speed

is 6 MHz.

Alternate S for
Alternate T for
Alternate D for

SPECIFICATIONS

Clearances

side

side

SPECIFICATION

ENVIRONMENTAL

—temperature—

Operational

Storage

Gradient

—humidity—

Relative

Gradient

Wet

Bulb

VIBRATION

SHOCK

Operational

Non-Operate

ALTITUDE

Operational

ACOUSTIC

NOISE

speeds

The

operator

standard 6 MHz
turbo

double

5.75

inches

15

inches

14

inches

21

pounds

4

inches

4

inches

is

selected

8MHz

12

MHz

4t040C.(+39to

-40

to

+10

C/Hour

8%

to

20%

per

26

C, 78

0.048

in.

0.73

G,

0.33

G,

use

linear

1.0

G, 5 -

10

G,

50

G,

25

25

G,

25

—

457

to

—457

to

45

dBA

by

or

program

+60

C.

80%

RH

Hour

C (no

Dbl.

17 - 150

200

to

interpolation

2000

11

mS

Half

mS

Square

mS

Square

2,972

12,192

at 1 meter

either a program

14.6

38.1

35.6

9.55

10.2

10.2

(-40

(+18

(no

(no

condensation),

Amplitude

500

Hz,

Meters

Meters

can

change

cm

cm

cm

Kg

cm
cm

+122

F)

to

+160

F/Hour)

condensation)

condensation)

(5 - 17

Hz

Hz

for

sweep

Sine

Wave;

Wave;

Wave;

(-

1,500

(-

or

the

speed

F)

maximum

Hz)

acceleration

of

.067

decades/minute

any

axis.

any

axis.

heads

over

to + 9,750

1,500

to

+40,000

by

the

by

levels

data.

operator.

issuing

between

Ft)

Ft)

the

150

following

Hz

and

command

200

Hz

strings.

REGULATORY

STANDARD

USA/Canada:

UL

478

FCC

CSA

22.2

EUROPE
VDE

IEC

435

APPROVALS:

DESCRIPTION

Electronic

FCC

Class

Data

Processing

Data

B,

Processing

Part

15

Equipment,

Units

Subpart

and

J

Consumer

Systems

and

Commercial

Products.

PC40-IH

SERVICE

MANUAL

THEORY

e

SYSTEM

e

SYSTEM

e

NOTES

SECTION

OF

OPERATIONS

BLOCK

DIAGRAM:

OVERVIEW

—

OPERATIONS

2

GUIDE

PC40-III

SERVICE

MANUAL

DIAGRAM

CLK

GEN

CNTL

SYSTEM

DRAM

LOGIC

AUDIO

CN1201

BLOCK

SYSTEM

PC40-II

SERVICE

MANUAL

SYSTEM

(To

OVERVIEW

be

released)

2-2

PC40-III

SERVICE

MANUAL

AUTOCONFIG"
AUTOCONFIGuration

to

automatically

the

resident

AUTOCONFIG”

expansion

The

AUTOCONFIG”

Video

The

PC40-IIl

memory

and

is

You

two

NOTE:

and

you

If

compatible

Also,

PC40-III

it

back

VGA

In

The

range.

the

onboard

configured

can

add

video

When

1450

(monochrome)

have

selected).

you

want

if

you

will

has

been

of

the

monitor

either

case,

syntax

e

sense

peripherals

feature

cards.

first

examines

If

an

VGA

in

accordance

an

expansion

screens.

to

adapter — one

were

initialized.

System

for

MODE

using

use

boot

will

you

the

(This

the

two

to

using

Unit

be

can

MODE

MONO

is a unique

additional

on

the

can

process

the

expansion

controller

with

MDA

makes

PC40-III’s

or

1950

video

that

use

an

MDA/Herc

your

If,

while using

set

initialized

switch

command

—

feature

peripheral

PC40-III

prevent

is

described

expansion

video

is

the

default

or

CGA

many

onboard

(color)

screens,

has

VGA

monitor

t0

MDA/Herc,

with

between

sets

the

NOTES

motherboard

hardware

bus

BIOS

disabled

compatible

CAD

must

there

no

BIOS

adapter

the

MDA/Herc

the

blinking

the

is

as

MDA

FROM

of

Commodore

devices

damage

in

this

for

any

is

found,

to

avoid

CONFIG

packages

video

be

connected

are

several

ROM

(monochrome)

and you

your

VGA

and

follows:

as

the

OPERATIONS

plugged

are

to

section.

expansion

then

conflict.

Control

controller

easier

controller,

things

of

any

will

see a blinking

adapter

PC40-III

cursor.

the

monochrome

default

PC

personal

into

the

expansion

adjusted

peripherals

Advanced

an

external

If

an

video

setting,

in

conjunction

to

use.)

aVGA

to

the

15

you

should

kind.

and

in

the

will

use

monitor

computers

so

as

not

and

Video

VGA

expansion

as

compatible

pin

video

remember.

you

have

cursor

expansion
the

monochrome

monitors

GUIDE

like

the

bus.

Once

to

conflict

motherboard,

Adapter

or

EGA

controller

video

BIOS

defined

output

on

with

monitor

the

your

port,

by

the

connector

First,

CONFIG

monochrome

you

monitor

by

using

PC40-III,

these

additional

with

as

well

BIOS

is

the

CONFIG

onboard

such

you

switches

have

the

allowing

expansion

as

ease

in

the

OC0000h — OC7FFFh

is

assumed

not

found,

dip

VGA

as

Commodore

(no

matter

should

set

monitor,

the

CONFIG

as

the

MS-DOS

the

devices

peripherals.

the

installation

to

be

the

switches

controller

what

use a CGA,

for

VGA

indicating

switches

boot

monitor

MODE

computer

are

detected,

on

the

video

1, 2 and

or

provide

Models

video

MDA

color,

and

command.

The

of

bus

output

3.

1403

mode

or

the

that

on

the
the

Serial

Before

(serial

If

both

onboard

figured

If

the

e

MODE

©

MODE

Port

(COMn:)

the

onboard

card/modem)

available

serial

and

onboard

COM:

port

tested

serial

co80 2 —
c0o40

serial

is

—

port

found

addresses

will

be

to

the

unused

port

is

places
places

is

enabled a scan

operational,

are

configured

COM:

configured

the

onboard

the

onboard

occupied

and

address

and

VGA
VGA

of

the

possible

EXPANSION

EXPANSION

by

expansion

tested

at

if

tested

ONBOARD

ONBOARD

adapter
adapter

two

bootup

I/O

address

only

one

successfully a message

into
into

standard

message(s)

COM

and/or

COM

boards,

expansion

COM

40

COMn:

at

at

03F8h

at

80

may

03F8h

02F8h

then

if

COM:

03F8h

or

COM

at

02F8h

column
column

hardware

be:

the

no

expansion

will

mode
mode

onboard

is

found.

be

output

and

sets

and

sets

locations

serial

port

COM:

’s

during

it

as

it

as

is

made.

will

are

bootup:

the
the

not

found

default
default

If

serial

be

enabled.

and

monitor

monitor

hardware

will

be

The

con-

2-3

PC40-III

SERVICE

MANUAL

Parallel

Before

(e.g.,

ware

If

all

available

onboard

figured

onboard

If

the

Mouse

A

check

mouse

If

no

expansion

will

appear

NOTE:

will

appear

Port

the

onboard

a

parallel

and

tested

parallel

onboard

Port

is

made

hardware

during

The

onboard

even

(LPTn:

printer

LPT:

port

to

port

or

parallel

card)

addresses

will

the

will

parallel

for a standard

is

never

mouse

bootup:

mouse

if

the

PRN:)

port

found

is

are

be

configured

unused

port

be

enabled

is

configured

LPT:

Microsoft

enabled.

is

found

the

hardware

Commodore

is

enabled a scan

operational,

occupied

and

address

to

the

and

Bus

The

following

onboard

is

enabled/tested

PC

Mouse

of

the

possible

EXPANSION

EXPANSION

EXPANSION

by

expansion

tested

at

I/O

if

two

expansion

first

available

03BCh,

tested

successfully, a message

ONBOARD

ONBOARD

ONBOARD

Mouse.

If

message

EXPANSION

mouse

is

enabled

ONBOARD

independent

Kit

is

not

three

bootup

and/or

and/or

boards,

address

/O

0378h,

it

is

found

will

MOUSE

attached.

standard

message(s)

LPT

LPT

LPT

03BCh

LPT:’s

address,

LPT

at

or

LPT

or

LPT

in

appear

MOUSE

and

tested.

at

0378h

at

0278h

at

03BCh

then

0278h

03BCh

at

0378h

at

0278h

the

during

at

at

of

the

LPTn:

the

if

no

are

found.

when

I/O

023Ch

If

023Ch

presence

hardware

may

onboard

expansion

searching

will

channel

bootup:

mouse

be:

parallel

If

only

be

output

then

is

operational

of

the

actual

locations

port

LPT:’s

one

expansion

in

the

during

the

onboard

mouse.

is

made.

will

not

are

found,

following

bootup:

Microsoft

then

the

The

If

parallel

be

enabled.

and

LPT:

is

sequence:

following

bootup

hard-

The

will

be

con-

found,

the

compatible

message

messages

80287

Numeric

A

test

is

made

will

be

output:

NOTE:

—

function

an

NOTES

It

with

NOTE:

taken

Configuration

read/write

80287

for

example,

80287-8

is

possible

experience

If

into

properly

(an 8 MHz

FOR

software

account

with

Coprocessor

for

the

presence

coprocessors

an 8 MHz

if

the

THE

PROGRAMMER

to

override

with

low-level

override

to

prevent

is

performed

only

bit7

are

coprocessor

PC40-III

part)

is

the

configuration

of

hardware

via

changing

of

an

80287

Numeric

available

necessary.

hardware/software

the

is

running

default

in

5,

6, 8 and

will

function

at

done

configuration

conflict

the

COMMODORE

its

meaning

Coprocessor

80287

Numeric

12

MHz

if

the

PC40-IH

12

MHz.

In

order

at

bootup.

interaction

is

resulting

from

in

damage

CONFIGURATION

read

to

during

Coprocessor

speeds.

to

use

We

STRONGLY

attempt

performed,

of

write.

The

bootup.

However,

is

running

the

this.

the

the

expansion

REGISTER

register

If

an

the

at 6

80287

at

recommend

presence

values

80287

is

units

are

or 8 MHz,

all

three

that

of

any

hardware

at

I/O

are

detected

downwardly

but a 6

CPU

speeds

only

advanced

expansion

or

the

PC40-III

address

shown

in

the

following

MHz

hardware

0230h.

the

following

message

compatible

unit

will

(6,

8,

12

MHz),

programmers

should

motherboard.

This

register

table.

only

not

be

is

2-4

COMMODORE

R/W

R

W

mono

venb’

rte

X

mouse — when

—

indicates

—

when

—

when

—

this

bit7

mono

venb’

CONFIGurstion

bit6

rtc X

rtc

that

the

set

low

the

set

high

the

bit

is

reserved

set

high

the

REGISTER

onboard

onboard

onboard

for

future

onboard

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9 — Onboard

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11 — Unused

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13 — Unused
14 — AT
15 — Unused

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Disk

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PC40-III

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WARNING:

IMPORTANT:

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THROUGH
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THROUGH

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WHEN

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controller 1 error

controller 2 error

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time

clock

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Troubleshooting

CMOS

board

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POD

Test

Test

Test

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Test

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realtime

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11

17

18

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test

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for

message:

DIAGNOSTICS

Shooting — Section

ROM

80286

prior

of

the

test

routine

is

initialized

must

be

correct

all

instruction

located

internal

0000

performed

detected

local

test

checks

or

is

number

shutdown

‘“Illegal

0001

bus.

to

the

01

to

further

shutdown

state

halt,

Al

three

ROM,

(B)

by

in

Test

The

the

next

indicates

(B)

see

processing.

on

low

is

moved

begins

unexpected

Shutdown

3

control

run

is

address
about

diagnostic

be

forced

bit

after

80286.

a

passed

and

instruction

contains

bios

to

passing

being

by

the

and

*‘HOLD’’

execution

at

physical

this

takes

the

power

01, a “HALT”?
80286

can

interrupt

instruction

enable

defective

“RESET”

on

if a ‘‘SHUTDOWN’”’

condition

M/IO'

is

is

signaled

indicate a halt

shutdown.

to

the

parallel

by

examining

shutdown

Code

in

conditions,

CMOS”

Diagnostic’’

“Power

must

FF

38

of

the

has

externally,

port a check

the

on

to

the

operating

to

addr

signal.

Refer

not

be

active

local

bus

activity

FF

FO

(H),

ticks.

checks

out

flag

halt

or

8242

the

is

executed.

of

the

register

instruction).

occurred. A shutdown

by

shutdown.

for

keyboard

numbers

03

78

to

RESET

for

the

8088

halted

must

the

80286

The

keyboard

6, 7 or

program

system.

(H)

prior

description

34

ticks

until

it

is

80286,

flags,

This

state

by

be

on

(set

as a bus

state of

reset

controller

8,

which

to

the

in

from

leading

negated.

in

real

address

the

arithmetic

will

stop

“RESET”,

to

1),

can

indicate a severe

operation.

address

is

conducted

status

port.

any

one

of

tests

start

of

IC

pinout

edge

Prior

to

mode,

logical

program

“NMI”

and

the

Low

line 1 will

In

which

functions

the

each

section,

to

trailing

fetching,

processes

unit,

execution

or

effective

states

indicate

and

the

all

ten

if

true,

test

section.

note

decoding

and

and

“INTR”

address

error

which

on

SO’, St’,

program

shutdown

will

of

that

edge

some

the

prevent

(when

computed

which

branches

generate

hardware

““VCC’”

of

initial

reset.

and

executing,

micro

code

CPU

registers.
the

CPU

““INTR’”

from

would

conditions

prevent

COD/INTA',

condition,

to

the

console

and

and

Al

test

are

NOTE:

An

message.

In

error

real

Branch

the

address

Interrupt

is

ODD.

Routines

interrupt

set

the

I/O

***Failures

or

any

Test

03

(H)

Eprom

tored

Detection

***Fajlure

checksum

into

information

UPI

status

code,

F6,

mode a shutdown

number

also

control

third

perform

check

in

test

0000

8,

words

bit.

02

party

0011

test

the

addition

of

an

error

in

test

03

port,

F7

or

interrupt

valid

(ICW)

could

cards.

(B)

verifies

to

results

indicates

for

which

F8,

(HEX)

number

shutdowns

indicate

contents

make

in a halt

defective

shutdown

will

halt

is

sent

could

occur

13,

to

1,

2, 3 and 4 will

problems

of

eprom

the

sum

zero.

condition

ROM.

routines

to

the

the

under

are

CPU.

parallel

or a “‘CALL

exit

protected

be

reinitialized.

on

the

local

by

adding

and

stored

Return

the

following

INT”

mode.

bus,

would

in

CMOS

depends

port

before

or

or

bytes

invalidate

memory.

on

calling

conditions:

“PUSH”

During

Other

these

routines

expansion

and

checking

tests

The

the

shutdown

the

display

instruction

the

DMA

within

bus.

This

for

result

01

and

shutdown

which

would

of

02.

command

code

in

routine

which

wraps

page

register

the

test

enable

include:

zero. A compensation

CMOS

stack

will

80286,

is

sent

memory.

generates

segment

be

initialized

‘“NMI’,

FE3000,

to

the

the

when

parity

byte

8242,

above

SP

and

and

FE3010,

is

fac-

Test

04

(H)

Test

04

checks

***Eailure

Test

05

(H)

Timer 1 and

***Fajlure

Test

06

(H)

Memory

calculated.

***Failure

Test

Test

***Rajlure

07

07

refresh

(H)

checks

0000

0100

the

in

test

04

0000

0101

timer 2 are

5

test

in

0000 0110

test.

in

test

06

0000

0111

the

in

test

07

(B)

DMA

indicates

(B)

indicates

(B)

Timer

indicates

(B)

8242

keyboard

indicates

page

registers

possible

checked

for

possible

and

DMA

possible

controller

possible defective

by

writing

defective

correct

defective

are

setup

FE3010,

and

FE3010,

operation.

FE3010.

to

initiate

Refresh

by

writing

8242

reading

or

Interrupts

refresh

logic

and

or

associated

bits

local

or

memory

reading

starting

bus.

are

masked

cycles

the

circuitry.

at

address

off

every

15.1

problem.

keyboard

PC40-III

80

(H).

during

buffers.

the

microseconds.

SERVICE

test.

Size

of

MANUAL

virual

memory

is

Test

08

(H)

Test

08

writes

pass

writes

***Eajlure

Test

09

(H)

Test

and

configure

onboard

NOTE:

VGA

The

adapters

On

completion

Test

0A

(H)

Test

RAM

Blocks

that

complement

The

At

NOTE:

of

is,

the

test

displays

completion

See

***Fajlure

0000

and

the

complement

in

test

0000

is

mode

of

0000

from

128K,

address

of

of

test

in

test

1000

(B)

reads

the

first

of

08

indicates

1001

(B)

video.

enabled

register

are

this

1010

128K

starting

which

address

results

the

26

OA

A search

and a callto

setting

found

test

on

the

(B)

to

640K. A display

at

128K

defines

into

in

blocks

onboard

(H).

indicates a defective

128K

the

address

possible

in

the

title

are

the

data.

of

memory

of

RAM

into

defective

is

made

VGA

the

5720

expansion

and

copyright

message

then

tested

physical

128K

test

the

RAM.

and

data.

RAM

to

determine

bios

is

controls

bus

by

location

to

the

CPU

verifies

Memory

executed.

the

then

message

is

generated

writing,

is

also

console

is

placed

block

size

is

cleared

or

RAM

if

MDA,

The

reset

signal

“NOVID’”

are

displayed.

reading

used

as

each

time a 128K

in

virual

is

128K.

after

logic.

CGA

or a special

dip

switches

to

the

from

indicating

and

verifying

the

bit

mode

and a test

First

test.

are

onboard

the

5720

that

pattern

boundary

pass

The

read

the

RAM.

that

for

writes

battery

video

to

VGA

to

the

base

The

is

being

is

virtual

addresses

status

adapter

determine

controller

PVGA

RAM

of

first

pass

written.

reached.

memory

into

is

also

confirmed

is

configured,

the

default

chip.

is

negated.

128K,

writes

The

(over 1 MEG)

data,

video

If

no

special

Test

08,

addresses

second

the

in

if

is

pass

is

second

test

08.

not

the

mode.

video

OK.

to

data,

writes

started.

Test

OB

DMA

controller

NOTE:

Appendix L of

part

Four

current

four

DMA

A

failure

The

beeper

**+*Failure

(H)

0000

#1

number

address

channels

in

test

OB

“DMA 1 error”

will

sound,

in

test

1011

(B)

register

the

PC40-III

check.

319983-01.

registers

are

will

(16

written

generate

bits

to

the

and a halt

OB

indicates A defective

operator

wide, each)

and

read

following

instruction

FE3010.

guide

from

display

will

lists

and

to

be

error

messages

four

current

verify

operation.

on

the

executed.

word

console:

starting

count

with

this

registers

test,

(16

see

bits

page

wide,

85

each)

of

operations

for

each

guide

of

the

Test

0C

(H)

DMA

controller

and

four

Successful

(DMA

6

and

5

A

failure

The

beeper

***Fajlure

Test

OD

Interrupt

rupt

request

A

verification

service

A

A

The

*+*A

test

for

failure

beeper

failure

routine

0000

#2

current

word

completion

|).

in

test

OC

“DMA 2 error”

will

sound,

OC

test

in

(H)

0000

controller

register

is

made

in

the

correct

in

test

OD

““Interrupt

will

sound,

in

test

1100

(B)

register

will

1101

#1

count

of

the

generate

and a halt

indicates

(B)

test.

(IRR).

that

no

event

check.

registers

test

0C

defective

a

Patterns

interrupts

of a failure.

timer 0 interrupt

will

generate

controller 1 error”

and a halt

OD

indicates a defective

The

second

(16

bits

will

set

the

following

instruction

are

written

can

is

also

the

following

instruction

functional

wide,

the

\

will

FE3010.

to,

occur

made.

will

FE3010.

each)

modes

display

be

and

if

‘“IMR’”

display

be

8237

within

for

DMA

on

the

executed.

read

from

is

on

the

executed.

PC40-III

containing

the

channels 0 through 3 and

console:

the

set

to

console:

FE3010

interrupt

FF

(H). A vector

four

are

current

written

mask

address

to

and

register

is

initialized

SERVICE

registers

read

from

enable

(IMR)

MANUAL

(16

bits

to

verify

cascading

which

to a temporary

by

.

controls

wide,

each)

operation.

channels

the

inter-

interrupt

4,

Test

0E

(H)

Interrupt

A

failure

The

beeper

***A

failure

Test

OF

(H)

Check

A

The

***A

Test

RAM

succ

NOTE:

peripheral

failure

beeper

failure

10

parity

ful

ess

(H)

PC40-III

“NMI”

The

beeper

***Failure

0000 1110

controller

in

test

“Interrupt

will

in

0000

in

test

“PIO

will

in

0001

test.

test.

is

enabled

“Parity

will

in

test

(B)

#2

test.

The

OE

will

generate

controller 2 error”

sound,

test

OF

sound,

test

and a halt

OE

indicates a defective

1111

(B)

in/out

0000

Blocks

does

register.

will

generate

error”

and a halt

OF

indicates a defective

(B)

RAM

of

not

use

and a service

error”

sound,

and a halt

10

indicates a defective

second

the

instruction

Write

the

instruction

are

parity,

routine

instruction

functional

following

FE3010.

and

read

following

FE3010.

en

writt

third

parity

for a parity

RAM,

display

will

from

display

will

and

to

will

third

8259

be

executed.

be

executed.

read

boards

error

be

executed.

party

contained

on

the

PIO

register.

on

the

from,

that

generates

card,

in

console:

console:

parity

use

parity

NMI,

the

the

FE3010

check

for

will

enable

following

or

local

is

tested

odd

console

bus.

parity

parity.

as

in

is

message.

test

made.

OD,

without

Parity

timer

disabled

test.

after

Test

11

(H)

Test

CMOS

Beeper

will

***Failure

0001

clock

sound

“Battery

of

test

0001

(B)

for

battery

if

failure

failure’

11

indicates a defective

failure

is

detected.

or

and

Console

‘“CMOS

checksum

will

checksum

battery,

failure.

display:

failure’’

defective

or

both.

oscillator,

or

M146818A.

3-4

Test

12

This

test

The

beeper

the

beeper

Test

13

Setup

interrupt

NOTE:

Master

Test

13

Test

14

Keyboard

Check

A

***Error

is

failure

(H)

0001

0010

(B)

is

sound

(H)

disabled.

will

0001

sound

heard

0011

It

is

for a set

(B)

controller

Vectors

and

does

(H)

made

indicates a defective

slave

not

0001

test.

in

test

“Keyboard

for

video

interrupts

create

0100

(B)

Functional
to

see

if

14

will

any

display

used

now

and

were

test

key

error”

would

move

are

error

of

lock

8242

only

in

length

be

setup

enabled

messages.

the

is

locked.

the

following

controller

manufacturing

prior

to

the

one

vector

in

test

at

8242

tables

09.

this

keyboard

error

or a defective

the

start

heard

to

point.

tests.

of

in

the

RAM.

controller

message

test

13

power

Vector

at

on

console:

keyboard.

(H).

In a system

up

routine.

addresses

U203. A test

PC40-III

which

are

fetched

for a stuck

has

from

key

passed

SERVICE

all

tests

top

8K

module.

on

keyboard

MANUAL

to

this

point

is

performed.

Test

15

(H)

Test

and

configure

No

error

messages

NOTE:

Test

Configure

No

Test

Configure

Memory

16

error

17

PPC1

(H)

serial

messages

(H)

memory

was

comparison
sound

and

The

new

configuration

***Check

Test

Configure

CMOS

error

The

***Check

the

18

(H)

memory

status

message

new configuration

the

0001

0101

at

U602

0001

0110

COMI

0001 0111

tested

of

the

the

following

“Base

settings

0001

1000

is

checked

on

the

“Extended

settings

(B)

the

are

generated

parallel

controls

port.

parallel

(B)

and

COM2

are

generated

(B)

less

than

640K.

in

test

OA,

and

old

and

new

memory

non-fatal

memory

for

configuration

is

stored.

RAM

(B)

over 1 megabyte

as

in

test

console:

memory

is

stored.

for

RAM

Parallel

by

this

test.

output.

for

8250

by

this

test.

Parity

°‘CMOS

(for

configuration

error

message

size

in

the

(virtual

17, a memory

configuration

size

in

the

port

at

U604.

EXPANSION

STATUS”

will

error”

setup

utility

memory).

size

error”

setup

utility

addresses

Read

set. A check

is

performed.

be

displayed

if

Check

mismatch

if

you

is

you

are

serial

made

setup,

interrupt

RAM)

is

for a warm

If a memory

on

encounter

on

will

sound

encounter

reads

enabled.

the

console:

this

address

the

this

and

writes

ID,

set

boot

size

message.

line

beeper

message.

to

ports

are

number

20, a low

and

of

serial

(ALT/CNTRL/DEL)

mismatch

is

detected,

indicates

generate

done.

channels.

virtual

the

following

Set

time

is

made

the

beeper

address

out.

and

will

mode.

non-fatal

a

Test

19

(H)

Configure

If

the

key

NOTE:

0001

keyboard

switch

You

are

1001

is

“Key

in a loop

(B)

test.

off

the

switch

Setup

following

is

off.

until

keyboard

message

Turn

you

turn

buffers,

it

on

on

enable

will

to

continue.”

the

key

be

displayed

switch.

keyboard

interrupt

on

the

and

console:

test

if

key

switch

is

turned

to

the

on

position.

Test

1A

(H)

Configure

the

if a mismatch

***Check

Test

**+Check

New
NOTE:

Test

Configure

No

settings

checks

settings

configuration

Refer

on

drive

1B

(H)

the

error

message

0001

1010

(B)

floppy

disk

drive.

Calculate

the

following

“Fjoppy 0 configuration

in

setup

second

floppy

message

utility

configuration,

“F]oppy 1 configuration

in

setup

utility

is

to

installation

for

0001

hard

stored

proper

1011

drive.

is

generated.

(B)

Check

in

CMOS.

instructions
operation.

configuration

if

if

number

will

be

error”

above

if a mismatch

error”

above

Floppy

when

of

floppy

displayed

message

message

is

is

interrupt

adding a second

if a mismatch

drives

on

console:

displayed.

the

following

displayed.

is

enabled.

present.

floppy

hard

message

to

drive

Check

the

system.

will

drive

will

not

PC40-III

type,

compare

be

displayed

It

may

be

setup.

SERVICE

on

be

necessary

settings

the

MANUAL

stored

console:

to

change

in

CMOS,

jumpers

Test

1C

(H)

0001

Test

number

FLAG”.

No

error

Test

1D

Configure

Compare

changed.

“**Check

Test

IE

Check

detected,

OR:

**#Check

Test

1F

Generate a new

No

error

is

message

(H)

0001

80287

configuration

*-

setup

(H)

0001

CMOS

then

“...
*“..

the

(H)

0001

message

1100

not

moved

is

generated.

1101

coprocessor.

Coprocessor

utility

1110

clock

to

display

The

Real

Real

RTC

chip,

1111

CMS

generated.

(B)

to

parallel

(B)

with

CMOS,

for

correct

(B)

see

if

it

one

of

Time

Time

Clock

M146818A

(B)

checksum

Check

(80287)

settings

was

the

following

Clock

and

port

for

if

80287

store

new

configuration

if

initialized

has

error”

at

U201

save

it

this

configuration.

is

present.

configuration,

error”

this

message

and

is

working.

messages

not

been

if

second

in

CMOS

Enable

beep

is

displayed.

Enable

on

the

console:

initialized’’

message

RAM.

Call

This

80287

above

routine

the

timer

made

only

interrupt

speaker,

interrupt.

is

displayed.

to

auto

turns

on

the

and

set

“EQUIP

and

display

Sound

configuration

game

the

following

beeper,

program

card

bit

FLAG”

and

in

the

if

it

message

initialize

at

this

“EQUIP

is.

is

if

failure

point.

setup

Test 20

Test

21

Initialize

System
System

***Refer

Tests

22,

(H)

(H)

ROM

will

speed

to

23

Not

Implemented

0010

0001

(B)

drivers,

now

begin

is

determined, 6 MHz,

operations

Not

including

boot

manual

Implemented

up.

hard

for

drive.

8MHz

opening

Checksum

or

12MHz.

screen

generated,

display.

and

all

ROMS

tested.

Test

24

(H)

Test

operation

System

Test

Used

Test

Virutal

Display
Display

During

A

And

Test
to

81

82

8
84

8
86
87
88
89

8A

8B
8C

8D

8E

will

25

(H)

in

manufacturing

26

(H)

memory

Message:
Message:

this

test

of

address

send

F3 (H)

address

shutdown.

(H)

(CH)

(H)
(H)

(H)
(H)
(H)

(H)
(H)
(H)

(H)
(H)
(H)

(H)

8F (H)

9

(H)

Power

Note

All

which

10

11

12

13

Messages

main

is

on

that

error

messages

are

“‘Parity

““Parity

‘“Non-recoverable

“Press

10,

board,

found

after

0010

0100

of

the

RTC

execute a halt

0010

0101

0010 0110

test

(over 1 megabyte).

‘Testing
‘Total

test

the

exception

line

20

“Test

__

(1111

lines

19

through

The

following

EXECP

INT

EXECPINTO2

EXECP
EXECP

EXECP
EXECP

INT
INT

INT
INT

EXECPINT07
EXECP
EXECP

INT
INT

EXECPINTIO

EXECP
EXECP
EXECP

INT
INT
INT

EXECPINT14

EXECPINTIS

EXECP

diagnostic
during

generated

error

error on

Fl

11

or

execution

listed

on

key

are

the

the

check,

INT

program

from

main

expansion

to

continue”

generated

expansion

(B)

chip.

Recheck

instruction

(B)

to

loop

through

(B)

System

is

26:

0011

01

Extended

interrupt

made

Virtual

to

23

list

RAM”

RAM = XXXX’”

(controls

Mode

parallel

are

tested.

defines

Single

NMI

03

DBreakpoint

04

Into

Detect

05

Boundary

06

Invalid

—

08

Double

09

Processor

—

11

Segment

12

Stack

13

General

—

—

16

Processor

is

finished

of

‘‘POD’’

in

appendix L of

the

miscellaneous

circuit

error - Processor

message

board’

bus’”’

after a parity

bus.

If

13

battery,

on

memory

diagnostics.

Call

vector

real

CPU

port.

Shutdown

the

code

Step

OP

Code

Exception

Segment

Not

Segment

Protection

Extension

at

the

calls

operations

halted’”’

error

the

check

is

displayed

make

failure.

made

to

tables

or

virtual

error”

Then

sent

Error

Present

Not

Present

Error

time

are

made

guide

interrupt

has

finds

and

sure

clock

No

error

this

routine

at

finish.

and

descriptor

CPU

mode).

execute a halt

if

error.

Exception

to

the

port

Error

of

boot

up ( end

to

auto

configure

are

listed

routines.

been

detected

the

error

the

processing

is

counting,

message

from

test

tables

are

If

not

instruction.

interrupt

and

the

type

of

test

and

in

the

overview

and a memory

CPU

is

halted

will

continue.

PC40-III

test

is

generated.

09.

built,

in

virtual

codes

of

exception

21).

to

miscellaneous

above

check

and

memory.

and

moved

mode

are

moved

with

has

message

SERVICE

from

ROM

display

interupt ( EXECP

interrupt

the

determined

12

following

to

the

routines.

exception

is

displayed.

parallel

of

that

MANUAL

to

RAM.

message:

port

prior

INT).

the

following

it

was

on

the

If

no

error

PC40-II

SERVICE

MANUAL

SECTION

PARTS

4

SECTION

Refer

Top

Spacer

Mounting

ruDm

PBC

Main

Foot

Bezel

os

Keyswitch

Plate

vo

Name

©

Dh

FD

dt
und

dd

du

u

bi

eb

bu

vu

DD

DD

DD

Hole

LED

LED

pm

Power

Floppy

Hard

Extension Card

onau

Keyboard

1352

Floppy

Hard

pnbmoyy

PCB

Ground

Power

PC40-IIl

1403

PC40-II

to

Cover

Plate

Bracket

Guide

Chassis

Assy.

Logo

Plate

Cover

Power

Hard

Supply

Disk

Disk

Assy.

Mouse

Drive

Drive

Assy.

Cable

Cord

Service

Monitor

H

MAJOR

Service

Base

On

Drive

Assy

Drive

Drive

Option

Cable

Cable

(HD)

Service

Reference

Panel

Manual

PARTS

Manual

LIST

Diagram

312226-01
313011-01
313066-02

251118-01

312225-01
380128-01
312244-01
313061-01
380133-05
316468-01
312679-01
380016-01
380020-02
390269-02
380825-02
313065-01
380120-01

312709-01

-1352
380012-08
312695-01
313055-01

380811-01

903508-15

314134-01
314882-01

Sub:-02
Sub:-01

(US)

(US/Canada)

(Not

shown)

(US) (Not

shown)

PC40-III

Software

DOS

Basis

Operations

Disk

MAJOR

Sub. Assy.

3.30A

Manual

3.22

Manual

Guide

Assembly

Includes

PARTS

(US)

315835-01

LIST

319293-01
319292-01
319983-01
317768-01

©

SPACER

©

TOP

COVER

312226-01

313011-01

MOUNTING

BRACKET

313066-02

PBC

251118-01

MAIN

BASE

312225-01

PLATE

GUIDE

CHASSIS

®

®

@

POWER

390269-02

(us)

FLOPPY

®

DRIVE

380825-02

HARD

DRIVE

313065-01

EXT

CARD

380120-01

KEYBOARD

312702-02

(us)

SUPPLY

DISK

DISK

PANEL

ASSY.

PC40-III

SERVICE

MANUAL

O

KEYSWITCH

©)

®

PLATE

NAME

FD

POWER - 380016-01

HD - 380020-02

BEZEL

312244-01
313061-01

LOGO

380133-05

PLATE

316468-01

HOLE

COVER

312679-01

LEDS

ASSY.

N

I

N

NS

==

Zu

er

28.

et)

‘

|

wer

en

..

PCB

ASSY.

313055-01

Service

Reference

Diagram

41

PC40-III

SERVICE

MANUAL

Commodore

Industry

Transistors,

IC

COMPONENTS

390300-04 | 80286
309316-01 | FE3000A

390317-02 | FE3010B

390319-01
390318-01 | FE3030

390302-01

318091-01

390304-03 | WD37C65,
390303-01

380205-01

38025901

390341-01
318087-01
390307-02 | PAL20L8

390335-02 | PAL2OLB

390308-01 | PAL20L10

390336-02 | PAL20LIO

390309-02 | PALI6L8
390083-04
318099-02

390337-02
390338-02
390339-01 | EPROM3,

390340-01 | EPROM4,

901521-02 | 741504
901521-30 | 741514
901521-20 | 74L5125A
901521-63 | 7415174
901521-13 | 7415244

901521-46 | 7415245

318066-01 | 74F00
390110-01
390203-01 | 74F08
390313-01 | 74F10
390279-01 | 74F20
390077-01
390080-01 | 74F138
390611-01
390312-01
390109-01 | 74F240
390314-01
390315-01 | 74F258
390578-01

390089-01 | 74F245

a

579-01 | T4ALSAA

901522-06

390359-01 | 74ACTOO

390081-01 | 74F74

390323-01
318827-01

390322-01
39032401 | TLA31
901527-03 | 7905

39036401 | 7415175

901882-01 | 1488
901833-01 | 1489

CRYSTAL,

390273.01

325566-20

325566-18

315566-19
325566-17

part

numbers

standard

| FE3020

PVGA-1A

|

|PPC1,

IMsıT1,

|8250,

|MI4818A

|8242
|MOS

|DRAM,

| DRAM,

|EPROMI,
|EPROM2,

|74F04

| 74F32

|74F153
|74F175

|74F253

| 74F573

7406

|

|4069

|1LM339
|LMIOCN

OSCILLATORS

|OSCILLATOR,

|

OSCILLATOR,

|OSCILLATOR,

|OSCILLATOR,
|OSCILLATOR,

etc.

are

12

MHZ

PRINTER

INMOS

SERIAL

KEYBRD

5720,

64 X 4
256 X 4

@ 100NS

(21728-12)
(27128-12)

parts

PARADISE

FLOPPY

RTC/CMOS

MOUSE-I/O

VGA

VGA

VO

HDC

DRAM

VGA
VGA

PC40
PC40-IlI

are

(Resistors,

available

PROCESSOR

VIDEO

INTERFACE

CONTROLLER

COLOR

INTERFACE

RAM

CONTROL

DECODER

DECODER

DECODER

DECODER

DECODER

(256K

BIT)

(1

MEG

BIOS - LOW
BIOS - HIGH

III

BIOS - LOW
BIOS - HIGH

48.00

MHZ

36.00

MHZ

25.175

MHZ

28.322

MHZ

9.6

MHZ

provided

in

manual

LOOKUP

CONTROL

#

#l

@I00NS

BIT

DRAM)

(27128-15) | 108

.

COMPONENT

-PCB

Capacitors,

(27128-15) | 1109

ASSEMBLY

for

reference

Connectors)

form

through

U301
U801

U802

Una

v101

U602

U1001

v2

U604

au

U203
UL

u14

UNS

Ua0I

U%0S

U706
U118-U125
U707-U714

U1101
U1102
U206

US01
U205,U414

v3

U102,U103,U107,U110,
U91,U902,U106
U104,U105,U502,U603
U721,U807
U413,U715,
U718,U719,U1201
U717
U1204
U30S
U803,U1202
U403
U404
U704
UL
U702,U703

U705,U1205

U903,U904

UA12,UA1L,UTI6

102

U100

U720

U405-U409,U410

UM
UI6

U

u17

VR501

U1203

U605
U606

0SCA01

0SC103

0SC102

0SC101
OSC1001

PARTS

LIST

#313055-01

only

and

do

not

indicate

should

be

secured

the

Service

Department,

CRYSTAL,

900560-01
900556-13

900558-91

RESISTOR

902441-11

902442-06

902422-03

90242.02

902441-31

90244255

oo2aazas
oora10as
Soda

902441-15

RESISTORS

901550-39

901550-64

901550-63

901550-105]
901550-94
901550-45

901550-124|
901550-52

901751-70

901550-12

901550-58
901550-01

901550-49

| |

901550-18

901550-19 | CARBON

901550-03 | CARBON

901550-20 | CARBON
901550-84
901600-28

901550-17
901550-110|
901550-92
901550-70 | CARBON

RESISTORS

901751-44

901751-61
901751-55

901751-38

901751-62

RADIAL

900019-13
900019-25 | RADIAL
900019-17 | RADIAL

900020-04 | RADIAL
900019-15 | RADIAL

900019-20

900019-21 | RADIAL

000022-03

OSCILLATORS

[CRYSTAL,

|CRYSTAL,

|CRYSTAL,

NETWORKS

150

|

|68

|33

|1K

|4.7K

|4.7K, 8 PIN, 7 ELEMENT,

|1ok

-

[ak

.IK,

10K,

|330

5% @ 1/4

[CARBON

|CARBON
|CARBON

CARBON

|CARBON
|CARBON

CARBON

|CARBON
|CARBON
|CARBON
|CARBON
|CARBON

|CARBON
|CARBON

|CARBON
|CARBON

|CARBON

CARBON
|CARBON

[CARBON

|CARBON
|CARBON

CARBON

|CARBON

CERAMIC

[RADIAL

[RADIAL

|MONO.,

the

locally.

order

6P,

OHM

OHM,

8PIN, 4 ELEMENT

OHM,

8

»

OHM, 8 PIN, 4 ELEMENT,

PIN,

6

‚8

PIN, 7 ELEMENT,

10

HIN

10

PIN, 9 ELEMENT,

OHM, 6 PIN, 5 ELEMENT,

ı h :

FILM,

FILM,
FILM,
FILM,

FILM,

FILM,
FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

.

FILM,
FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

FILM,

1% @ 1/4

FILM,

FILM‘

FILM,

FILM, 4.64K

FILM,

CAPACITORS

LEAD,
LEAD,
LEAD,

CERAMIC

LEAD,

LEAD,

LEAD,

RAKIAL

”

availability

Approved

#314000-01.

(Continued)

32.768

KHZ

1.8

MHZ

14.318

MHZ

SIP

SEL

PIN,

4

E

, 4 ELEMENT,

ELEMENT,

5

, 9 ELEMENT,

WATT

3.9K

OHM

10

OHM

22

OHM

33

OHM

68

OHM

75

OHM

160

OHM

220

OHM

210K

OHM,

22K

OHM

470

OHM

IK

OHM

100

OHM

2.2K

OHM

4.7K

OHM

5.1K

OHM

10K

OHM

IM

OHM

2.2

OHM

1.2

OHM

51

OHM

20K

OHM

300

OHM

WATT

150

OHM

365

OHM

,

2K

OHM

2

OHM

340

22pF
27pF

47pF

.0047uF

100pF

10pF

1000pF

LEAD,

of

parts

cross-references

SIL

SIL

SIP

SIP

SIP

SIP

SIP

SIP

1%

OHM

5% @ 50

u

VOLT

.IuF

from

Commodore.

for

TTL

chips,

Y201
Y601

Y801

RP1001

RP701,702

06,601,602,

Ba

an

Rpadı

REIN

RP303,603,605

RP108
RP301,302
RP502,507

RPSO8

R1203
R503-R506,R210-R212
RI02,812
R402,603,R1206,609,

701,813,410

R114,1001,101,409,401,
R209

R801,RA11
R1201
R804,R902,R507,R207
R2IO
R1202
R206,207
R204,407,702,1204,412,

502,508,1003,1004

RIIS,RII7
R604,R608
R105,R404,R606,901,
R803,R1002,R904,806,

R406,R509,R903,811
R805
R202,R501,R605,905,
302,R113,R116

R203,R601,R602,R807,

205

R208,R610

R1205
R403
R301
R809

R107-R109,1005,1006

R110
RIIL,RII2

RIO4

R106

C601,C402

can

C204,C205,C602,C803,

C804

cal

CS03,CAZI-M26,CSI4

a

C206,C627,C207

C203-CB102,CBI15

CBIOI1,CBIOId,

CB2031-2034,CB205

CB206,CB3011,CB3012,

000,

2013040,

11,CB30

42

PC40-III

SERVICE

MANUAL

RADIAL

90002203

900022-05

900022.01

900402.01

MISCELLANEOUS

903025-08 | FERRITE

900850-01 | DIODE

CERAMIC

IMONO.,

(continued)

900019-07 | .047

ELECTROLYTIC

390101-08

390101-01

390101-06 | ELECT.,

251842-02

390257.01

390297.03
390297-02

390275-04

903025-01

390253-02 | FERRITE

UF

|MONO.,

|MONO.,

CAPACITORS

[ELECT.,
|CAP

ELECT.,

|ELECT.,

JEMI

FILTER

|EMI

FILTER

|EMI

FILTER

|EMI

FILTER

DSS306-55Y5101M

|EMI

FILTER

|FERRITE

CAPACITORS-

RAKIAL

RADIAL

RADIAL

ALUM.,

ALUM.,

ALUM.,

BEADS

BEADS

BEADS

1N4148

LEAD,

LEAD,

LEAD,

RADIAL,

TAN,

10uF

RADIAL,

RADIAL

100PF

22000PF
2200PF

MURRATA

150

PF

(AXIAL)

(AXIAL)

THREE

PCB

5% @ 50

.IuF

.33uF

.22uF

IuF

47uF

10uF

TURN

COMPONENT

ASSEMBLY

VOLT

(Continued)

CB302,CB3031-3039,

CB3041-3048,CB401-412| | 390280-01 | FUSE,

CB501,CB502,CB6011, | |390321-01

CB6012,CB602-605,

CB6051,CB6052,CB706,
CB716,CB722,CB80ll,

CB8012,CB8021,

CB8022,CB%02,

CB%1,CB9%05,116,

CB1002,1121,CB1101, | |
CB1102

C301,C101

CB118-125,707-714,403- | |

407,409-411,CB415,

CB416,CB701-705,715, | 39033401

717-721,803,CB903,

904,1201-1205,413,

CB30S

Cs11,CB126

C507,C513

C208

C501-C506,C508-CS10,

cs12

cı202

EM1624-1631,1201

EMI1203
EMI201,202
EMII101-105

EMI607-623

FBAR3,AA.ICL.

FB104,601-608,405,102 | |?>0204.02

FB201-204

CR201,CR202,CR501,
CR502,CR601-CR603

ION,

#313055-01

|

|

|

1001,

PARTS

LIST

(Continuea)

MISCELLANEOUS

380393-01

902658-01

|

312680-01

|

|251260-01

|

904775-01 | PIANO
904150-05 | SOCKET,

904150.06

390185-02
390185-01
390185-04

390242-01
390242-05 | D-SUB,

390241-05 | D-SUB,

903446-25 | EXPANSION
903446-04

ist

903326-03 | HEADER, 3 PIN,
903326-02 | HEADER, 2 PIN,

903345-17 | HEADER,

903345-20 | HEADER,
903349-01

390043-01
39018601 | JUMPER

SUBSTITUTE

390317.01

39030401

| IC,

(Continued)

[BATTERY,

PICO,

|DELAY

LINE

TRANSISTOR

PIEZO

BEEPER

PUSH

BUTTON

DIP

28

|SOCKET,
|SOCKET,
|SOCKET,
|SOCKET,
|D-SUB,
|D-SUB,

|EXPANSION

PACK

|POWER
|SHORTING

JIC,

|IC.

40

68

84

100

9

PIN,

15

PIN,

25

PIN,

25

PIN,

Ka

,

»

34

40

CONNECTOR, 6 PIN.

PARTS

FE3010A

WD37C65

WD37C65A

NICAD

4A

2N3904

SWITCH, I PIN, 4 POS.

PIN,
PIN,

PIN,
PIN,

PIN,

CONNECTOR,
CONNECTOR,

ROLL,

PIN,

PIN,

BLOCKS, 2 POS.

3.6V

10

TAP @ 20

QMB12

N.O.

DIP
DIP

PLCC
PLCC

PLCC

RT.

ANGLE

RT.

ANGLE

RT.

ANGLE

TR.

ANGLE

.

SIL

‚

SIL

DIL

DIL

Ns

SWITCH

MALE

FEMALE

ANGLE,

FEMALE

FEMALE

MALE

FEMALE

62

PIN

36

PIN

BT201,BT202

FU601

DL701

Q601,0801,Q1201

PZ801
PBS01

swıol

U108,U109,U1101,

U1102

1302

U301,1601
U303,304,801,802

vı0l

CN601
|[CNI0I

CN603
|CN602
CN501,CN503
CN505,CN507,CN502,

CN504,CN506,CN507

CN201

CN1201

CB902,JMP904,CNS12,

Na

Ps

CN1001

CNS0I
CN5S09

SEE 8 OF

RBIO,

US02

I001

11001

aa

R213,

SUB:

SUB:

SUB;

\

OVE

8

R103

4-3

PC40-III

I

O=

Tape

[era

stem

rg

[es

v

SERVICE

MANUAL

urn.”

=

I_

ai

Ir,

5

_

==

=

@

—.

|

vn

_

S

"Aa

TO-SSOETEF

Aıqwassy

IA

si

De

PC40-III

SERVICE

MANUAL

MOUSE

+0

De

en

5

k

OONDNROD

CN601

oS\

$

PORT

(5mm)

oe

Signal

Vertical

Horizontal

VerticalQ

Horizontal

Button
Button

+

5V

Ground

Button

(3)
(1)

(2)

VIDEO

CN101

a0

Q

ne

15

14

DTE

PORT

(3/16)

13

12

11

Function

Red

Video

Green

Video

Blue

Video

Monitor

ID

Bit 2 (not

used)

ground

Red

PRNPARR

Return

Green

Blue

Return

Key

(no

Sync

Monitor
Monitor

Horizontal

Vertical

not

used

Return

pin)

Return

ID
ID

Sync

(ground)

(ground)

(ground)

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used)
used)

SERIAL

CN603

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(5mm)

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25_

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2

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4

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12
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STROBE—————

DO
D1
D2
D3
D4
D5
D6
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INIT
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PC40-III

SERVICE

MANUAL

1

HIGH

VGA

390338-01

LOW

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5-01

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0

DECODE

390307-01

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VIDEO

390302-01

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APPENDIX

B

APPENDIX

C

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APPENDIX

390336-01

HDC

CNTRL

R

ADD

3020

DECODER

390319-01

390309-01

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1109

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MOUSE

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SERIAL

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AND

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12MHZ

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CPU

390300

80286

MOUSE-I/O

318087-01

5720

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DATA

390318-01

3030

HIGH

BIOS

390340-01

ROM

LOW

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390339-01

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390308-01

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CNTRL

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390316-01

3010

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CPU

390317-02

3000

4-6

PC40-II

SERVICE

MANUAL

INFORMATION

COMMODORE
OEM

ASSEMBLIES.

IN

THIS

WILL

SECTION

e

IC

PINOUTS

e

SCHEMATICS

SECTION

NOT

SUPPLY

5

IS

FOR

COMPONENT

REFERENCE

PARTS

ONLY.

FOR

1)

2)

3)

IC

80286

FE3000A

FE3010B

PIN

OUTS

CPU

CPU

PERP

&

SIGNAL

CNTRL

CNTRL

PC40-III

DESCRIPTIONS

SERVICE

390300-01

390316-01

390317-02

MANUAL

4)

5)

6)

n

8)

9)

10)

FE3020

FE3030

PVGA-1A

PPC

WD37C65

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DATA

BUFFER

BUFFER

PARADISE

PRINTER

FDC

SERIAL

MOUSE

INTERFACE

CONTROL

VIDEO

INTERFACE

390319-01

390318-01

390302-01

318091-01

390304-03

380205-01

318087-01

5-1

1)

80286

CPU

390300-01

PC40-III

SERVICE

MANUAL

Component

component

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SYMBOL

CLK

D15-DO

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BHE

TYPE

1

v0

0

o

NAME

AND

SYSTEM

divide-by-two

DATA

active

ADDRESS

WO

BUS

bus

BHE

BUS

whenever

COD/INTA

DD

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de

du

dat

Du

eb

zu

pub

sub

CLOCK

BUS

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transfers.

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would

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0
0

1
1

CYCLE

one

5

FUNCTION

circultry

inputs

and

BUS

outputs

The

ENABEE

normally

AO

STATUS

or

both

provides

the

can

be

data

during

floats

to

3-state

physical

address

bus

indicates transfer

use

BHE

BHE

Value

0

1

0

1

iIndicates

are

LOW,

80286

MIO

SI

ED
ED
ED

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CD

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du

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du
dh

fundamental

synchronized

memory,

OFF

memory

is

active

to

condition

and

AO

Word

transfer

Byte

transfer

Byte

transfer

Will

never

initiation

Si

and

Bus

Cycle

Ss

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ei

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DS

de

ei

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mb

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timing

to

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during

and

HIGH

or

data

chip

Encodings

on
on

occur

of a bus

50

are

Status

Interrupt

Will
Will

None;

IF

Memory
Memory

None;

Will

VO
VO

None;

Will

Memory

Will

None;

for

an

external clock

and

interrupt

bus

hold

I/O

port

and

floats

on

the

select

Function

upper

lower

cycle

active

Definition

Bus

not

occur

not

occur

not a status

Al = 1

data
data

not a status

not

occur

read

write

not a status

not

occur

instruction

not

occur

not a status

80286

systems.

acknowledge

acknowledge.
addresses.

to

3-state

upper

byte

functions.

half

of

data

half

of

data

and,

along

LOW

and

Cycle

then

read
write

Initiated

cycle

halt;

cycle

cycle

cycle

acknowledge

It

generator

AO

OFF

of

the

BHE

is

bus

bus

(D7-0)

with

float

to

else

shutdown

read

is

divided

by a LOW

read

is

LOW

during

data

active

(D15-8)

M/TÖ

3-state

cycles;

bus.

by

when

bus

D15-8.

LOW

and

COD/INTA,

OFF

two

to

HIGH

outputs

data

hold

Eight-bit

and

during

floats

inside

the

80286

transition

data

during

is

to

be

transferred

acknowledge.

oriented

to

3-state

defines

bus

hold

to

generate

on

the

memory

on

devices

OFF

during

the

type

acknowledge.

RESET

and

pins

assigned

of

bus

the

I/O

D7-0.

bus

cycle.

processor

input.

write

A23-A16

to

the

hold

The

clock.

The

cycles.

The

are

LOW

upper

byte

acknowledge.

bus

is

in a Ts

data

of

internal

bus

during

the

data

state

is

PC40-IT

SERVICE

MANUAL

SYMBOL

M/IO

COD/INTA

LOCK

READY

HOLD
HLDA

INTR

RESET

Vss

Vec

CAP

NOTE:

HLDA

TYPE

NAME
MEMORY

0

LOW,

CODE/INTERRUPT

0

{rom.J/O

BUS

0

may

or

BUS

quiring

BUS

request control

Om

hold

HLDA

signals

INTERRUPT

whenever

cycles

interrupt

before

the

NON-MASKABLE

The

is
remain

PROCESSOR

to

cessor

be

PROCESSOR

gram

vu

come

are

SYSTEM

on

1

0.

3.state

Operation

clock.
code

A

clock.

of

where

SYSTEM

SYSTEM
SUBSTRATE

of

For

(max.)

After

Is

only

Low

AND

I/O

an

/O

cycles.

LOCK

be

activated

descriptor

READY

setup

HOLD

acknowledge

and

regaining

are

active

the

to

read

acknowledge

the

current

system

clock.

interrupt

edge

triggered

HIGH

processor

extensions.

extension

asynchronous

execution

inactive.

active

LOW

RESET

RESET

which

Pin

Value

(HIGH)
(LOW)

OFF

of

Approximately

from

the

LOW

to

HIGH

The

LOW

the

processor

the

processor

GROUND: 0 Volts.

POWER:

the

internal

correct

operation

after

this

time,

If

HOLD

FUNCTION

SELECT

cycle

or

an

ACKNOWLEDGE

COD/INTA

indicates

that

explicitiy

table

access.
terminates a bus
and

hold

REQUEST

times

of

the

local

condition.

control

HIGH.

REQUEST

interrupt

enable

an

8-bit

interrupt

cycle

instruction

INTERRUPT

enable

bit

after

internal

for

at

least

EXTENSION

The

when

the

to

the

EXTENSION

on

WAIT

An

active

ERROR

and

may

clears

remains

80286

Pin

80,

M/TO,

D15-D0

the

80286

begins

38

power-on

transition

to

HIGH

clock

will

clock

+5

FILTER

CAPACITOR: a 0.047

substrate

of

the

Is

inactive

CLK

80286

the

Vcc and

distinguishes

interrupt

acknowledge

floats

other

by

LOCK

AND

requests

in

(he

four

10

system

the

“LOCK”

is

active

cycle.

Bus

relative

to

HOLD

bus.

The

is

ACKNOWLEDGE

When

local

bus

of

the

local

the

80286

bit

in

the

vector

that

completed.

ends

in

order

REQUEST

80286

flag

synchronization.

system

OPERAND

PEREQ

clock.

BUSY

some

input

be

asynchronous

internal

active

for

State

During

input

operand

PEACK

AND

ESC

causes

logic of

more

requested

system

and

the

Pin

Si,

PEACK,

COD/INTA,

CLK

execution

transition

occur

must

Volt

bias

80286,

reach

processor

A23-A0,

after a HIGH

cycles

from

address,

of

RESET

of

during

be

phase

Power

Supply.

generator. A maximum

the

substrate

their

specified

clock

(Low).

memory

distinguishes

3-state

OFF

bus

masters

instruction

LOW

cycles

are

ihe

system

control

is

will

remain

bus.

This

to

suspend

flag

word

identifies

INTR

to

interrupt

Interrupts

word

does

For

clock

cycles.

REQUEST

requests

is

being

is

ERROR

instructions

the

80286

to

the

the

than

Reset

Names

BHE,

HLDA

to

LOW

the

trailing

occurs.

synchronous

RESET

the

next

synchronous

«F + 20%

bias

AC

can

be

access

from

cycle

is

instruction

during

are

not

prefix

and

floats

extended

clock

granted,

granted

terminates

its

is

cleared.

the

is

sampled

the

not

affect

proper

AND

the

80286

transferred.

active

LOW.

indicate

until

BUSY

10

perform a processor

system

80286

and

16

system

LÖCK

(Note

1)

transition

edge

to

the

may

be

system

to

DC

generator

and

DC

synchronized

I/O

access,

in

progress.

fetch

bus

hold

to

gain

control

or

automatically

to

3-state

without

limit

be

met

for

to

the

When

the

this

correct

ownership

will

the

requesting

bus

hold

program

the

of

the

beginning

the

next

with

an

input.

control

80286

current

source

at

before

80286

recognition,

ACKNOWLEDGE

to

perform a data

PEREQ

the

operating

becomes

clock.

These

is

active

cycles.

on

RESET.

RESET

system

clock

period.

clock.

capacitor

current

must

charge

parameters.

to

another

HIGH.

clock

of

asynchronous

clock

another

12V

leakage

if

HIGH

M/TO

floats

cycles

from

acknowledge.

of

the

by

80286

OFF

during

until

terminated

operation.

of

its

bus

the

float

master

acknowledge

execution

80286

responds

interrupt.

of

each

instruction.

internaliy

The

NMI

the

input

extend

operand

is

active

HIGH

condition

of a processor

inactive

(HIGH).

extension

inputs

have

The

During

RESET

The

are

requried

will

end a processor

to

the

system

Synchronous

must

be

of 1 „A

this

capacitor

RESET

clock

during

to

3-state

memory

Its

timing

system

hardware

bus

80286

drivers

until

condition.

and

to

To

assure

processor

INTR

supplied

input

must

have

the

transfer

and

interrupt

internal

80286

HIGH

by

the

clock;

LOW

connected

is

allowed

to

may

be

by

pulsing

Ts, a memory

OFF

during

data

read

is

the

bus

for the

current

during

hold

acknowledge.

by

READY

local

to

3-state

HOLD

is

bus.

LOW.

ignored

becomes

READY

HOLD

service a pending

an

interrupt

program

cycle

and

is

level

sensitive,

vector

value

is

active

HIGH,

been

previousiy

memory

management

for a processor

floats

10

3-state

extension

The

80286

may

when

executing

pull-up

may

be

reinitialized

active,

the

output

10

LOW

transition

80286

for

internal

cycle

at

however,

to

HIGH

between

through

its

operating

applied

to

prevent

RESET

cycle

bus

cycles.

Also

same

as

M/IO.

and

memory

READY

during

The

HOLD

OFF

and

inactive

may

external

request,

interruption,

must

be

active

of

2.

No

may

LOW

extension.

OFF

t0

the

80286.

be

interrupted

WAIT

resistors.

at

pins

of

initiallzation

the

second

in

this

case

transitions

this

pin

and

the

capacitor.

voltage.

spurious

LOW

synchronous

or a halt/shutdown

hold

acknowledge.

distinguishes

the

following

XCHG

is

bus

input

then

activate

be

asynchronous

request.

it

performs

INTR

active

interrupt

be

asynchronous

for

and

during

any

time

of

the

RESET

HIGH

it

of

ground.

The

capacitor

instructions,

an

active

hold

allows

which

results

two

must

HIGH

HIGH,

acknowledge

at

least

protection

The

PEACK

bus

hold

An

active

while

waiting

or

some

with a LOW

80286

must

before

to

cannot

RESET

This

activity

to

interrupt

bus

LOW

acknowledge.

another

HLDA,

Interrupt

remain

at

and

four

BUSY

ESC

enter

be

LOW

be

predetermined

are

capacitor

chargeup

by

the

cycle

is

acknowledge

cycle.

The

Interrupt

synchronous

local

thus

entering

in

the

80286

t0

the

system

requests

interrupt

acknowledge

active

least

two

may

be

asynchronous

cycles

to

the

system

system

clock

capabilities

output

acknowledge.

Input

for

BUSY

instructions.

to

HIGH

the

state

synchronous

the

first

bus

transition

required

only

filters

time

the

CPU

during

system

clock.

in

progress.

cycles

LÖCK

signal

acknowledge,

input

re-

bus

master

the

bus

deactivating

clock.

These

are

masked

bus

until

the

performed.

clock,
cycles

of

the

the

80286

to

become

These

first

cycles

and
and

80286

pro-

may

pro-

in-

Inputs

processor

are

signals

stops

transition

shown

below:

to

the

system

cycle,

to

fetch

of

the

system

which

phase

for

systems

the

output

Is 5 milliseconds

this

time.

It

to

to

DMARDY

DMACLK

A

EAIOCK

EBRMCK

NDMAMR

PIN

10

1

12

13

14

15

16

17

np

HLDA

1

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MDPINO

MDPINI

MNIO

NAENI
NAEN2
NBUSY

NCS237 — 29

NIRQ3

——

RST27 — 32

TYPE

1

2

vo

3

vo NYIOR

4

v0

5

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6

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8

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9

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15
16

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24

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27

28

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Al

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EMBRMCK

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FUNCTION

GROUND

BUS

HIGH

Active
transfer a byte

N1/O

Active

1/O

Active

MEMORY

Active

MEMORY

Active

EXTENDED

Active

generator.

REAL
Active

clock

BUS

Active

BUS

Active

refresh

DATA
Active

of a word

READY

Active

plete

CLOCK
Clock
SYSCLK

80286

Active

80286

Active
ENABLE

Active

sion bus.

ENABLE

Active

RAM.

ENABLE

low — Indicates

READ

COMMAND

low — Indicates a read

WRITE

COMMAND

low — Indicates a write

READ

low — Indicates a read

WRITE

low — Indicates a write

1/O

high — Used

TIME

high — Used

calender

ADDRESS

high — Or

HOLD

REQUEST

high — Bus

or a DMA

LATCH

high — Latch

transfer

TO

DMA

high — Indicates

its

cycle.

TO

DMA

in

sync

(ie:

3,

ADDRESS

high — Address

ADDRESS

high — Address

//O

high — Enable

RAM

high

—

2eagzezes

on

the

COMMAND

COMMAND

WRITE

for

CLOCK

to

chip

(Motorola

LATCH

of

ALE

request

cycle.

CONTROL

data

on a byte

DEVICES

with

and

4,

or 5 MHz)

AO

Ai

CHECK

PARITY

Enable

2)

>

the

current

upper

byte.

of

of

COMMAND

external

ALE

latch

the

146818)

ENABLE

and

TO

80286

to

80286

bits

0-7

device.

that

the

half

the

bit 0 from

bit 1 from

error

signal

CHECK

parity

check

FE3000A

14

3 F119M

n

n

»

5

aa

6

|

«F—nzrows

6

|

6

6

60

|

591

58

5

|

55

54

bus

cycle

will

an

I/O

device.

of

an

I/O

device.

memory.

of

memory.

wait

state

address

in

the

HLDA.

CPU

caused

of

first

bus

DMA

may

com-

frequency

the

80286.

the

80286.

from

the

CONTROL

from

on

of

the

expan-

board

CPU

F14M

HLDA1

NENDCY

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43

RC

NENFAST

NRESIN

NRAMSL

NNMICS
NIOS16
NIOCHK

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UNUSED

IOCHCK

LSAO

by

cycle

CNTRL

PIN

18

19

20

21

27

31

32

33

4

4

390316-01

TYPE

NDMAMR

vo

SYMBOL

ENPAL?

FI6

HLDA

HRQI1

IOCRDY

MDPINO

MDPINI

MNIO

NAENI

NAEN2

NBUSY

NCS287

NIRQ13

RST287

SYSCLK

RESCPU

REFDET

Q

PCK

PCLK

PROCLK

NPCLK

NRFSH

vss

VDD

xXA0

NDENI1

DIR245

NERFSH

NNPCS

PC40-IH

FUNCTION

ENABLE
Active

generator.

16

Active
cycle

HOLD

Active
the

HOLD

Active
EXPANSION
Active

dicate

PARITY

Parity
PARITY
Parity

MEMORY

Active

next

ENABLE
BUS

Active

ENABLE
BUS

Active

BUSY

Active

80287

Active

INTERRUPT

Active

DMA

Active

controller

RESET

Active

SYSTEM

System

of

RESET

Active

exit

REFRESH
Signal

to

START

Active

external

PARITY
Active

been

CLOCK
PROCESSOR

Clock

MHz)

INVERTED
REFRESH

Active

RAM

GROUND

+5

ADDRESS
Active

GATE

Active

GATE DATA

Active

BYTE

Signal

transfer

ENABLE
Active

to

80287

Active

EXTERNAL

high — Disables

BIT

MEMORY

high — Indicates

ACKNOWLEDGE

high — Indicates

bus

in

REQUEST

high — Bus

high — Signal

that

BIT

bit

from

BIT

bit

from

high — Signal

cycle

is a memory

DMA

low

DMA

low

STATUS

low

1/O

low

low — Co-processor

MEMORY

low — Memory

TO

high

CLOCK

clock

the

PROCLK.

TO

high — Reset

protected

that

the

RAM.

OF

high — Indicates

wait

CHECK

high — Indicates a RAM

detected.

TO

twice

low — Indicates

refresh

VOLTS

high — System

DATA

low

low

SWAP

to

control

on a 8

REFRESH

low — Signal

the

address

CHIP

low

SERVICE

OPERATION

response

to a CPUHRQ

request

BUS

READY

current

FROM

on

board

FROM

on

board

SELECT

CHANNELS

CHANNELS

ASSERTED

DECODE

REQUEST

READ

in

phase

(ie:

mode

or

each

CYCLE.

state

generator.

8042

CLOCK

processor

CLOCK

cycle.

0-7

8-15

DIRECTION

byte

bit

device.

to

bus

during a RAM

SELECT

from

RAM

RAM

from

6,

to

TO

swap

ADDRESS

the

V/O

CHIP

80287

80286

DETECT

toggles

BUS

the

CYCLE

SUPPLY

AO

WAIT

external

that

the

FROM

that

the

from a DMA

the

cycle

may

BANK

RAM

BANK

RAM

the

cycle.

BY

13

error

COMMAND

read

command

with

and

8,

or

10MHz)

CPU

from a command

an

external

time

there

start

of a bus

TO

80286

speed.

8042

the

current

address

direction

enable

MANUAL

STATE

wait

state

current

memory

THE

80286

80286

has

signal.

controller.

expansion

bits

bits

80286

0-3

5-7

half

bit

the

complete.

0

0-7.

1

8-15.

indicating

TO

USE

TO

USE

80287

from a DMA

the

reset.

is a refresh

cycle

parity

error

(ie:

12, 16,

bus

0

on a 16

refresh

refresh

bus

frequency

cycle

address

cycle.

released

to

the

DATA

DATA

to

cycle

10

the

has

or

20

Is

a

bit

In-

5-4

PC40-III

SERVICE

MANUAL

PIN

50

51

64

62

67

9

70

71

RC

sı

FUNCTION

ENABLE
Active
ing a DMA

INTERRUPT

Active

rupt

NMI

Active

80287

Active
LATCHED
Active

bus

V/O

Active

sion

UNUSED

Must

80287

Active

VO

Active

16

Active

dicate

transfer.

NMI

Active

ON

Active

RESET

Active

system

ENABLE

Active

read

ZERO

Active

have

TERMINAL

Active

1.

RESET

Active

BUS
BUS

ADDRESS

Active

SYSTEM

Active
TERMINATE
Active

generator

HOLD

Active
controllers.

1.19

14.318

ENABLE

Active

on a 16

RESET

Active

SYNCHRONIZED

Active

current

CRYSTAL
CRYSTAL
CRYSTAL
CRYSTAL

DATA

Active

ADDRESS
Active

80286.

+5

DMA

low — Gates a memory

cycle.

ACKNOWLEDGE

low — Interrupt

controllers.

OUTPUT

low — Non-maskable

BUSY

TO

low

SYSTEM

high — System

cycle.

DEVICE

ERROR

high — Indicates

bus.

be

left

open

ERROR

low — Error

CHECK

low — Error

BIT

/O

TRANSFER

low — Signal

that

the

current

PORT

DECODE

low — Decode

BOARD

RAM

low

IN

low — External

reset.

LOOK

low — Causes

and

write signals

WAIT

STATES

low — Indicates

no

wait

states.

COUNT

high — Terminal

TO

CPU

high — Input

CYCLE

STATUS

CYCLE

STATUS

A3

high — System

DATA

high

CURRENT

low — Signal

to

end

ACKNOWLEDGE

high — Hold

MHz

CLOCK

MHz

SIGNAL

BUS

low — Gates

bit

transfer

TO

SYSTEM

low

low — Ready

bus

cycle

TO
TO
TO
TO

DIRECTION

low — A low

LATCH

high — Signal

VOLTS

SUPPLY

MEMORY

TO

80286

80286

ADDRESS

from

signal

from

DECODE

AHEAD

early

with

80286

to

BUS

from

the

current

acknowledge

TO

SWAP

data

on a 8

LOGIC

READY

to

may

terminate.

8284

CLOCK

8284

CLOCK

82284

CLOCK

82284

CLOCK

CONTROL

indicates a bus

ENABLE

to

READ

acknowledge

interrupt

address

bit 0 during a CPU

an

error

the

80287.

from

the

expansion

bus

cycle

of

NMI

enable

reset

in

DECODE

eneration

zero

the

current

OF

TIMER

count

generate

SO

FROM

Sı

FROM

address

bit

BIT

7

CYCLE

external

bus

TO

TIMER

TO

EXPANSION

during

bit

device.

TO

CPU

indicating

GENERATOR
GENERATOR

GENERATOR
GENERATOR

latch

the

read

AO

from

the

is a 16

used

wait

bus

CHANNEL

from

RESET

80286
80286

3

wait

cycle.

DMA

to

the

CPU

address

to

the

bus

to

the

to

80286.

the

expan-

expansion

bus

bit

I/O

port.

to

generate

of

memory

states.

cycle

timer

channel

to

state

one

of

BUS

swap

of a byte

that

read

cycle.

from

inter-

bus.

to

should

CPU.

DMA

the

dur-

in-

a

1

the

TYPE

SYMBOL

o

NEDMMR

0

NINTA

NNMI

NBZ286

LSAO

IOCHCK

UNUSED

NERROR

NIOCHK

NIOS16

NNMICS

NRAMSL

NRESIN

NENFAST

NZROWS

OUT

xXA3

XD7

NENDCY

HLDA1

F119M

F14M

oo

NRESET

3

°

NREADY

xX18284
xX28284

x1284

X2284

DTNR

09-0,

s=2833
8

oo

®

5-5

3)

FE3010A

(B)

PERP.

CNTRL

390317-02

PC40-III

(-02)

SERVICE

MANUAL

PIN

10

n

12

13

14

15

16

17

18

19

20

21
22
23

24
25

26

2

3

4

5

6

7

8

9

KBINT

IRQ

IRQ

IRQS

IRQ6

IRO7

INTR

ouTi

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SPKR

NIRQS

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IRQ
IRON
IRQI2

ALO)

AL()

AL(2)

1

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v0
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vo
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0

0

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o

I

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EB

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DEEELIETT

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16

17

18

2
21

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25

26

———i

27
28

29

———

0

3

32

BISSERATSTSSTOISTETTERER

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SYMBOL

vVss

DATA(0)
DATA(1)

DATA(2)

DATA)
DATA(4d)
DATA6()
DATA(6)
DATA(T)

HLDA

DMARDY

DMACLK

NMASTER

KBINT

IRQ3

IRQ4

IRQS

IRQ6

IRQ7

INTR

oUTı

vss

TCLK

SPKR

NIRQ8

IRQ9

FUNCTION

GROUND

DATA
DATA

DATA

DATA
DATA
DATA

DATA
DATA
HOLD

Active

for a request

DMA
Active

complete

DMA

System

BUS

Active

the

KEYBOARD
Active

INTERRUPT

Active

INTERRUPT

Active

INTERRUPT

Active

INTERRUPT

Active

INTERRUPT
INTERRUPT

Active

TIMER

GROUND

TIMER

(1.19

SPEAKER

INTERRUPT

Active

INTERRUPT

Active

FA

PraaeeeecıE

BIT

0

BITI

BIT2

BIT

3

BIT

4

BITS5
BIT

6

BIT

7

ACKNOWLEDGE

high

— Acknowledge

for the

READY

high — Signal

its

current

CLOCK

Clock

DMACLK

6

MHz

8

MHz

10

MHz

MASTER

expansion

MHz

3

or 6 MHz

4or8

5

MHz

low — Signal

bus

INTERRUPT

high

REQUEST

high

REQUEST

high

REQUEST

high

REQUEST

high

REQUEST
REQUEST

high

CHANNEL 1 OUTPUT

CLOCK

clock

for

REQUEST

low

RQUEST

high

has

wm

AY

bus

from

to

indicates

cycle.

MHz

to

indicate

control

3

4

5

6

7

TO

timer)

8

9

from

the

(hat

that a master

of

the

CPU

14

3

n|

D——

70

9

68

6

66

5

6

62

6

©

59

58

57

56

ss

4

ee

AH(12)

the

CPU

DMA

controller.

DMA

bus.

(80286)

DRQS

a

DRQ?

AEN

TC

HRQ

NDACKEN

DACKO
DACKI
Dackı

NCLEAR
NIRQ13

IRQ14
IRQIS

NINTA
NRTCCS

ALE

NRFSH

AH(13)

(80286)

may

on

27

28

29

30
3
32
33
34
35
36
37
38
39

4%
4
4
43
44
45
46
4
48
4

50
51
52
53
54
55
56

7

71

IRQ10

IRQ

IRQI2

vo

AL(0)

v0
vo

10

vo
vo
v0
vo
vo
vo

vo

vo

58
8

SE

=O00000000000

oo

AL)
ALL)
ALG)

AL(4)

AL(S)

AL(6)

ALM
AL(8)

AL(9)
AH(0)

AH()

Vss

VDD

AH)
AHG)
AH(4)
AH(5)

AH(6)

AH(ND
AH(8)
AHO)

AH(10)
AH()

AH(12)

AH(13)

NRFSH

ALE

NRTCCS

NINTA

IRQIS

IRQ14

NIRQ13

NCLEAR

vss

DACK2

DACK1
DACKO

NDACKEN

HRQ

To

AEN

DRQ7

INTERRUPT

Active

INTERRUPT

Active

INTERRUPT

Active
ADDRESS
ADDRESS
ADDRESS
ADDRESS

ADDRESS
ADDRESS

ADDRESS
ADDRESS
ADDRESS

ADDRESS
ADDRESS

ADDRESS

GROUND

+5

VOLTS

ADDRESS
ADDRESS
ADDRESS
ADDRESS

ADDRESS

ADDRESS

ADDRESS

ADDRESS

ADDRESS
ADDRESS

ADDRESS
ADDRESS

REFRESH

Active

dress

ADDRESS

Active
REAL
Active

INTERRUPT

(80286)

Active

rupt

INTERRUPT

Active

INTERRUPT

Active

INTERRUPT REQUEST

Active

SYSTEM

Active

GROUND

DMA

DACK2 DACKI DACKO

0
0
0
0

1
1
1 1
1 1 1

DMA
DMA
DMA

Active

and

DACK2

DMA

Active

DMA
Active

troller

DMA
Active

bus

is a DMA

CHANNEL 7 DMA

Active

REQUEST

high

REQUEST

high

REQUEST

high

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

BIT

8

BIT

9

BIT

10

BIT

11

SUPPLY

BIT

12

BIT

13

BIT

14

BIT

15

BIT

16

BIT

17

BIT

18

BIT

19

BIT

20

BIT

21

BIT

22

BIT

23

ADDRESS

low — Signal

bus

during a RAM

LATCH

high

TIME

CLOCK

low

ACKNOWLEDGE

low — Interrupt

controllers.

REQUEST

high

REQUEST

high

low — Error

CLEAR

low

ACKNOWLEDGE

0
0

1
1 1

0 0
0

ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGE

low — Signal

decodes.

REQUEST

high

END

high — Signal

has

AEN

high — Signal

high

OF

finished

cycle.

TO

OPERATION

to

enable

ENABLE

CHIP

acknowledge

interrupt

to

enable

CUP

to

its

cycle.

to

REQUEST

10

11

12

the

refresh

refresh

cycle.

SELECT

FROM

to

15

14

13

from

(80287).

BIT

2

DMA

Acknowledge

0 0

1

0 2

1

0

DACKO,

Ihe

that

Dlegal

DMA

the

1

0 6

BIT
BIT
ENABLE

(80286)

indicate

indicate

to

the

CPU

the

Inter-

Channel

ı

3

7

DACKI,

con-

current

ad-

PC40-III

SERVICE

MAN

UAL

PIN

73

714

75

76

77

78

79

TYPE

I

o

v0

vo

o

o

SYMBOL

DRQ6

DRQS

DRQ3

DRQ2

DRQI

DRQO

SYSALE

NIOR

NIOW

NMEMR

NMEMW

VDD

FÜNCTION
CHANNEL 6 DMA

Active

high

CHANNEL 5 DMA
Active

high

CHANNEL 3 REQUEST
Active

high

CHANNEL 2 DMA
Active

high

CHANNEL 1 DMA
Active

high

CHANNEL 0 DMA
Active

high

SYSTEM

Active

dress

1/O

Active

L/O

Active

MEMORY

Active

MEMORY

Active

+5

ALE

high — Signal

latch.

READ

low

WRITE

low

low

low

VOLTS

REQUEST

REQUEST

REQUEST

REQUEST

REQUEST

COMMAND

COMMAND

READ

COMMAND

WRITE

COMMAND

SUPPPLY

to

latch

the

address

in

the

ad-

vcc2

GDD2

ADDI14
ADD13

N.C.

AS
Al6

ADDI2

vcCc3

GDD3

ADDI1
ADDI10

ADD9I
ADDS

Al8
A19

GDD4

VCcC4

PIN

65

62

82

76

A

A4

—

TYPE

men

BB5

QIZIOFLITI2SOZZZEZZZUO

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22
23

14

115

16

17

18

19

20

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2

FE3020

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25

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27

28

129

%”

31
32

AISSFFATSSTITTTTSEERER

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an

FEEEEREFFEERSSSFFFEEE

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SYMBOL

1

NMASTER

I

HLDA

1

ADSTB

L

NRAMCS

VO

NYMEMW

VO

NYMEMR

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NGTMEMR

vo

NMEMW

vo

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from

control

from

been

released

from

board

COMMAND

to

indicate a write

or

COMMAND

to

indicate a read

Master

READ

to

indicate a read

WRITE

to

indicate a write

or

WRITE

to

indicate a read

or

WRITE

to

indicate a write

READ

to

indicate a read

ENABLE

data

bus.

HIGH

data

bus.

© =

the

the

the

the

RAM

Master

cycle.

Master

Master

DMA,

COMMAND

DMA,

ENABLE

FARADAY

D-}

>U<<

FUNCTION

MASTER

Active

the

HOLD

Active
that

HRQ

ADDRESS
Active

the

RAM
Active

MEMORY

Active

during a CPU,

MEMORY

Active

during a CPU

GATE
Active

ing a DMA

AT
Active

during a CPU,

AT
Active

during a CPU,

PC

Active

below

PC

Active

below 1 MB

AT
Active

upper

80386

Active

upper

un

nm

mon

low — Signal

bus

master

ACKNOWLEDGE

high — Signal

the

bus

has

signal.

STROBE

high — Signal

address.

CHIP

SELECT

low — On

WRITE

low — Signal

READ

low — Signal

or

MEMORY

low — Signal

cycle.

BUS

MEMORY

low — Signal

BUS

MEMORY

low — Signal

BUS

MEMORY

low — Signal

1MB

during a CPU,

BUS

MEMORY

low — Signal

during a CPU,

BUS

BYTE

low — Indicates a transfer

byte

of

the

BUS

BYTE

low — Indicates a transfer

byte

of

the

to

DMA,

DMA,

DMA,

HIGH

FE3020

14

3

Rn

nn

7”

69

68

67

m

6

65

&

62

6

|

173

|

58

57

56

55
54

AT

bus

which

bus.

80286

to

in

response

FE3010

chip

select.

cycle.

COMMAND

cycle.

COMMAND

cycle.

COMMAND

or

Master

or

Master

of

data

of

data

ADDR

vVccs

GDDS

AIS
Ald

Al3

Al2

LA20

NYMEMW
NRAMCS
NMASTER

NGTMEMR

NBHE

LASO

HLDA

ADSTB

AB
A2r

NMEMR

NEBHE

GDD7

vcc7

indicate

to a CPU

that

latches

of

memory

of

memory

memory

of

memory

of

memory

of

memory

of

memory

on

on

allows

dur-

cycle.

cycle.

the

the

BUFFER

o

Le

D

AU

SSNFZISBREHRSESHTR

ss

37

390319-01

vo

O

_NPROMSEL

o

1

vo
vo
vo
vo
vo
vo

Vo

v0
v0
vo
vo

10
10

vo
vo
vo

Vo

v0
vo
v0
v0
vo
v0

I

1

I

10

v0
vo
vo
v/0
vo
vo
vo
vo
vo
vo
vo

10

vo
vo
vo
v0
v0
v0
v0

NABHE

MEM245

DIR

LASO

ADR(0)

Al
A2
A3
A4
AS
A6
AT
Aß

A9
AlO
All
Al2
AB
A14
AIS
Al6
A17
A18
A19
A20

LA20

A20GT

A2l

a2

AB

ADDO
ADDI
ADD2
ADD3
ADD4
ADDS
ADD6
ADD7
ADDS

ADD9I
ADD10
ADD
ADDI2
ADD13
ADD14
ADD15
ADD16
ADD17

ADDI8

ADD19

N/C

vcci
vcCc2
vcc3

Vcc4
VCcc5
VCC6

vCcc7
vcc8
vcc9

GDD1

GDD2

GDD3

GDD4

GppD1

GDDS5

GDD6

GDD7

GDD8

GDD9

GDD10

PC40-III

FE3000

BUS

Active

low — Indicates a transfer

upper

byte

PROM

SELECT

Active

low — BIOS

MEMORY

Direction

FE3000
FE3000/FE3010

80286/FE3010
80286/FE3010

80286/FE3010

80286/FE3010
80286/FE3010

80286/FE3010

80286/FE3010
80286/FE3010

80286/FE3010

80286/FE3010

80286/FE3010

80286/FE3010
80286/FE3010
80286/FE3010
80286/FE3010
80286/FE3010
80286/FE3010

80286/FE3010

80286/FE3010
80286

FE3010

8042

Active

80286/FE3010

80286/FE3010

80286/FE3010

AT
AT
AT

AT

AT
AT
AT
AT
AT
AT
AT

AT

AT
AT
AT
AT
AT
AT
AT
AT

SV + 5%

5V + 5%
5V + 5%

$SV + 5%
SV + 5%
$SV + 5%
SV + 5%

5V + 5%
5V + 5%

GROUND
GROUND
GROUND

GROUND

GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND

control

ADDRESS

ADDRESS

ADDRESS

GATE

high — ENable

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

BUS

ADDRESS

SERVICE

BYTE

HIGH

of

the

data

bus.

PROM

BUFFER

for

BIT

ADDRESS
ADDRESS
ADDRESS

ADDRESS

ADDRESS
ADDRESS

ADDRESS

ADDRESS
ADDRESS

ADDRESS

ADDRESS

ADDRESS

ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS

ADDRESS

ADDRESS

BIT

BIT

ADDRESS

ADDRESS

ADDRESS

ADDRESS

DIRECTION

the

0

20

20

address

BIT
BIT
BIT

BIT

BIT
BIT
BIT

BIT

BIT
BIT
BIT

BIT

BIT

BIT

BIT

BIT

BIT

BIT

BIT
BIT

MANUAL

ENABLE

select

on

board

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

BIT

8

BIT

9

BIT

10

BIT

11

BIT

12

BIT

13

BIT

14

BIT

15

BIT

16

BIT

17

BIT

18

BIT

19

bit

BIT

21

BIT

22

BIT

23

0

1

2

3

4

5

6

7

8

9

10

11

12
13
14
15
16
17
18
19

of

data

memory

20

on

the

buffers.

5-8

5)

FE3030

DATA

BUFFER

390318-01

PC40-III

SERVICE

MANUAL

V

cin

DATA4
DATAS

DATA6

DATA7

ve

GDD3

Das

—

DATA10

pre—2

VCcc4

GDD4
DATA12
DATA13
DATA14
DATAIS

NIOW

GDDs

vVcc5

PIN

65

64

66

2

4

$

1

70

9

68

35

67

6&

6

57

[‘}

56

5

22

27
28

TYPE

I

I

I

I

o

O

_ENRAMCK

1

I

NSELDATA

I

I

o

I

1

1

I

I

ADDRESS()

I

I

DGATECTL

5 x

na_

ZESBERL22222220

ERSERgESEESSEceeseess

Il!

ronvwnn=o

ESaeronenmnmäBSssterret

u

14
15

16

17

18

19

FE3030

|

24

|

25

|

26 [.

29

3

31

3

FARADAY

RIRSFARTTSIITITTTRERT

BSSARESEAARRHRRBESZEE

»z

SYMBOL

IOCK

PCK

NGTPIO

NWRPIO

ENIOCK

NRESET

NINTA

HLDA

ACK

NMASTER

NF245DIR

NF245SEN

DTR

ND646

>»o

FUNCTION

/O

Active

dicates

PARITY
Active

dicates a parity

GATE
Active

signals

WRITE

Active
ENABLE
Active
ENABLE
Active

RESET

Active

SELECT

Active

INTERRUPT

Active

on

the

HOLD

Active
that

HRQ

ACKNOWLEDGE
Active

cle

is a DMA

MASTER

Active
the

bus

BYTE

Controls

BYTE

Active

DATA
This
AT

DATA
Active
DATA
Active

bit

rend

BUS

EN

DEVICE

ERROR

high — This

an

error

from

CHECK

high — This

error

PIO

low — This

on

to

the

data

PIO

low — Write

IO

CHECK

high

PARITY

high

low — System

DATA

low — This

ACKNOWLEDGE

low — This

EDATA

bus

ACKNOWLEDGE

high — Signal

the

bus

has

signal.

been

high — Signal

cycle.

low — Signal

master

to

SWAP

DIRECTION

the

data

SWAP

ENABLE

low — This

DIRECTION

signal

determines

ADDRESS

BUS

ENABLE D (0:7)

low — This

GATE

CONTROL

high — Signal

of a 8

bit

signal

the

signal

from

signal

bus

the

CHECK

reset

signal

signal

to

from
released

to

from

control

bus

direction

signal

the

BIT

signal

to

device.

from

PC/AT

from

the

gates

during a status

error

enable

from

gates

gates

the

CPU.

the

in

indicate

the

AT

the

bus.

enables

data

0

enables

latch

read

214

|

RB}

n|

7

|

70

|

|

68

67

sFr

64

sek

62

6

ADR(0)

5
58
57

56

|

55

|

GDD8

54

|

vcc7

the

FE3000

bus.

the

FE3000

on

board

RAM.

the

IOCK

and

read.

register.

the

FE3000.

the E data

the

80286

response

that

for

direction

interrupt

to

the

bus

byte

the

byte

the

data

data

indicate

to a CPU

current

which

swap.

swap

on

bit

0-7

bus.

vVCc8

GDD9

NWRPIO
NRESET

NSELDATA

NINTA

HLDA

NMASTER

—ı0c

PCK

NF245EN
NRTCCS

DGATECTL

NCUSEN

DTR
ND646EN

in-

in-

PCK

vector

cy-

allows

bus.

the

bus.

0-bus.

on a 16

NCU4SEN

vo

NYIOW

vo

NYIOR

vo

vo

6

NIOW

NIOR

NRTCCS

NRTCRD

NRTCWR

10

vo
vo
vo
vo
v0

10

DO

D1
D2 80286
D3

D4

DS

D6

D7
D8 80286

D9

D10

pn

D12

D13

D14

D15
DATAO
DATAI
DATA2
DATA3
DATA4
DATAS
DATA6
DATAT
DATA8
DATA9

DATA10
DATAll

DATA12

DATA13
DATA14
DATA1S

EDATAO

EDATAl1

EDATA2
EDATA3

IEI

BESBESBABSEE

DSH

EDATA4
EDATAS5S
EDATA6
EDATA7

vcci

VcCc2
VCcCc3
Vcc4
VCc5

VCC6

vCcc7

VCCc8

GDDI1

GDD2
GDD3

GDD4
GDD5
GDD6
GDD7
GDD8
GDD9

GDD10

DATA

BUS

Active

low — This

bus.

NO

WRITE

Active

low — Signal

a

CPU,

DMA,

1/O

READ

Active

low — Signal

CPU,

DMA,

PC

BUS

1/O

Active

low — Signal

a

CPU,

DMA,

PC

BUS

1/O

Active

low — Signal

CPU,

DMA,

REAL

TIME

Active

low

REAL

TIME

Active

low

REAL

TIME

Active

low

80286

DATA

80286

DATA
DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA
DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA

80286

DATA

AT

DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA

DATA

DATA
DATA
DATA

BUS

BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS

BUS

BUS
BUS
BUS

AT
AT
AT
AT
AT
AT
AT
AT
AT
AT
AT

AT

AT
AT
AT

PERIPHERAL

PERIPHERAL

PERIPHERAL
PERIPHERAL

PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL

5SV + 5%

$SV + 5%

5V + 5%
5V + 5%
5V + 5%
5V + 5%
5SV + 5%
5V + 5%

GROUND

GROUND
GROUND

GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND

ENABLE D (8:15)

signal

enables

COMMAND

to

indicate a 1/O

or

Master

Master

0

1

2

3

4

5

6

7

8

9

10
11
12

13

14
15

BIT
BIT
BIT
BIT

to

to

to

0

1

2

3

4

5

6

7

8

9

10
11

12

13
14

15

cycle.

indicate a I/O

Cycle.

COMMAND

indicate a I/O

Cycle.

COMMAND

indicate a I/O

Cycle.

CHIP

READ

WRITE

BUS

BUS

BUS
BUS
BUS
BUS
BUS
BUS

COMMAND

or

Master

WRITE

or

WRITE

or

Master

CLOCK

CLOCK

CLOCK

BIT
BIT
BIT
BIT
BIT
BIT

BIT
BIT
BIT

BIT
BIT
BIT
BIT

BIT

BIT
BIT

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

BIT

BIT
BIT
BIT

DATA

DATA

DATA
DATA
DATA
DATA
DATA
DATA

SELECT

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

the

data

write

read

write

read

bit

during

during

during

during

8-15

a

a

6)

PVGA-1A

VIDEO

CNTRL

390302-01

PC40-II

SERVICE

MANUAL

PIN

SYMBOL

RSET

MCLK

TYPE

VCLKO

VCLKI
VCLK2

DAIS
DAMM

DAI3
DAI2
DAIL
DAIO 2 IN/OUT

EMEM

EION

BHEN

AI

Al8
A17
AIG
AIS

DA9I
DAS
DA7
DA6
DAS
DA4
DA3
DA2

DA1

DAO

IN/OUT
IN/OUT

IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT

IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT

IN/OUT
IN/OUT

MRDN

MWRN

IORN

IOWN

MD15S
MD14
MD13

MD1I2

MD11

MD10

MD9

MD8

IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT

PIN

IN
IN

IN

IN
IN
IN
IN
IN

IN
IN

IN

IN

IN

IN
IN

PLCC

PINS

36

76

15

74

73

28

27

24

23
22
20

1
18
17
16
14
133
2122

46
45
44
43
4
4
4

39

21

33

9

3
32

29

30 H2

89

%

91
92
9
94
9

9%

PGA
PINS

LI

G2

H13
HR
Hi

Gl
G3

F2
F3

Ei

D1
D2

cı
ca

Bl

Al

B3

A2

M5

N4

M4

N3

M3

N2

M2

N1

E2
22

A4

H3

9

H1

A113

B12

Al2

B1

All

B10

AlO

B9

DESCRIPTION

Active

high

to

36

to

44,5

MHz
MHz

defined

bus
bus
bus
bus
bus

display

high byte

memory
memory

read
write

memory
memory
memory
memory
memory

memory

memory
memory

signal

MHz

MHz

reference
clock

bit
bit
bit
bit
bit

data

data/address

data/address
data/address

data/address

data/address
data/address

data/address

data/address

data/address
data/address
data/address

data/address
data/address

data/address
data/address

strobe.

strobe.

Up
Up

25.175

28.322

User

Address
Address

Address
Address
Address

Multiplexed

Multiplexed

Multiplexed
Multiplexed

Multiplexed

Multiplexed
Multiplexed

Multiplexed

Multiplexed

Multiplexed
Multiplexed
Multiplexed

Multiplexed
Multiplexed

Multiplexed
Multiplexed

Enable

Programmable

Bus

Display
Display

WO

1/O

Display
Display
Display
Display
Display

Display

Display
Display

from

for

for

external

19
18
17
16
15

bit

memory.

enable

enable.

read
write

Active

Active

data
data
data
data
data

data

data
data

120

100

clock

input*

clock

15

I/O.

Active

strobe.

bit
bit
bit
bit
bit

bit

bit
bit

external

ns

DRAMS

ns

with

bus

bus
bus

bus

bus
bus

bus

bus

bus
bus
bus

bus
bus

bus
bus

Active

strobe.

low

low

15
14
13
12
11

10

9

8

DRAMS

input

input*

Monitor

bit

bit

bit

bit

bit
bit

bit

bit

bit
bit
bit

bit
bit

bit
bit

high

Active

low

Active

Active

circuit

14

13
12

11

10

9

8

7

6

5

4

3

2

1

0

low

type

low

low

during

input

or

high

power

up

5-10

PC40-III

SERVICE

MANUAL

PIN PIN

SYMBOL

MD7
MD6
MDS
MD4
MD3
MD2
MD1
MDO

RASI10N

CASI0N

OEION

WEIN
WEON

RAS32N

CAS32N

OE32N

WE3N

WE2N

MAß
MA7
MA6
MAS

MA2

MAI

MAO

MA4
MA3

VID7

VID6

VIDS

vID4

VID3
VID2

viD1

VIDO OUT

PLCK

BLNKN

HSYNC

VSYNC

RPLTN

SKDBKN

WPLTN

REDY

IRQ

DSI16N

EBROMN

EABUFN
EDBUFN

DIR

VDD
VDD
VDD
VDD

vVss

vs$

vVss

vss

vVSss

vss

TYPE

IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT

OUT

oUT

OUT
OUT
OUT
OUT
OUT
OUT

oUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT

oUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

oUT

OUT
OUT
OUT
OUT
OUT
OUT

_
_

—_
_
_
_
_

—_
_ 4
_

PLCC

PINS

9
98
%9

2

3

4

5

6

79

80

a

86

85

82

8
84
88
87

68

6

6

67

70
71
72

68

9

48

4

50
53

54

55
56
57

5

62

60

6

41

10

58

34°

35

8

7

1

38

37

25

52

3

100

1

15

26

sı

71

PGA

PINS

A9

G

B8

c

A7
A6

B6
6

F13
FI2
Fi

c13

D12

E13
Ei2

D13

cı2

B13

Mi
M2
MI3

L12

K13

312
313

LB3

K12

L6

M6

N6
N?
N8

M8

L8

N9
N10
N12

MIO

N11

NS

B4

M9

Kl

K2

BS

AS

A3

L2

Mi

FI

L7

63

A8

B2

G

M7

N13

Gı

B7

DESCRIPTION
Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Row

address

Column

address

Output

enable

Write

enable

Write

enable

Row

address

Column

address

Output

enable

Write

enable

Write

enable

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Display

memory

Video

color

Video

Video
Video

Video

Video

Video

Video

Pixel

Color
Color
Color

Read

Card

Write

A

tristate

is

available

look

color

look

color look
color look

color

look

color

look

color

look

color

look

clock

monitor
monitor
monitor

color

look

select

feedback

color

look

active

Programmable
Programmable

Enable

BIOS

Enable

processor

Enable

processor

Directional

read

+5V
+5V
+5V
+5V

cycles

DC
DC
DC
DC

control

GND
GND
GND
GND
GND
GND

data

or

data

or

data

or

data

or

data

or

data

or

data

or

data

or

strobe

bank 0 (Memory

strobe

bank

bank

0.

bank 0 upper
bank 0 lower
strobe

bank 1 upper

bank 1 lower

Active

bank 1 (Memory

strobe

bank

1.

Active

multiplexed

multiplexed

multiplexed
multiplexed

multiplexed

multiplexed
multiplexed

multiplexed
multiplexed

up

table

up

table

up

table

up

table

up

table

up

table

up

table

up

table

blank

pulse.

horizontal

vertical

synchronization

up

pallet.

during

up

pallet.

high

ready

bank

processor
enable

16

ROM.

Active

address

data

buffer.

for

processor

configuration

configuration

configuration

configuration
configuration
configuration

configuration

configuration

0.

Active

low

byte

(Memory

byte

(Memory

1.

Active

low

byte

(Memory

byte

(Memory

RAS/CAS

RAS/CAS

RAS/CAS
RAS/CAS

RAS/CAS

RAS/CAS
RAS/CAS

RAS/CAS
RAS/CAS

address

bit

address

bit

address

bit

address

bit

address

bit

address

bit

address

bit

address

bit

Active

low

synchronization

Active

low

memory

Active

low

output

10

interrupt

request.

bit

word

transfer.

low

buffer.

Active

Active

data

bit 7 upon

bit 6 upon

bit 5 upon

bit 4 upon
bit 3 upon
bit 2 upon

bit 1 upon

bit 0 upon

Maps 1 &

low

map

map

maps 3 and

low

map

map

address

address

address
address

address

address
address

address
address

7

6

5

4

3

2

1

0

pulse.

pulse.

Active

or

I/O

access.

signal

processor

Active

Active

low

low

bus.

Bits 0 through

0).

1).

0).

3).

2).

bit

bit

bit

bit

bit

bit
bit

bit
bit

Active

power

power

power

power
power
power

power

power

Active

Active

Active

2).

Active

Active

8

7

6

5

2

1

0

4

3

high

Active

low

low

Active

high

that

or

up

up

up

up
up
up

up

up

low

low

low

low

low

low

low

memory

high

15

with

high

access

tristate

for

5-11

nn

PP

C1

PARALLEL

mi

IT
T

II

III

soo1anaWN

PRINTER

CNTRL

“=

ETETTTETTTITTN
I

PC40-III

318091-01

SERVICE

MANUAL

DIIIIIIIII

PIN

CODE

DESCKUFIION

GND

Ground

D7

Data

DATO

Data

AD

Address

GND

Ground

DATI

Data

Al

Address

DAT2

Data

A

Address

DAT3

Data

A3

Address

DAT4

Data

Ag

Address

DATS

Data

Address

AS

GND

Ground

DAT6

Data

PAPE

Paper

DAT?

Data

BUSY

Printer

Interrupt

IRQ

Acknowledge

TEN

Chip

Printer

SLCT

ERRN

Error

STBN

Strobe

AFXN

Autofeed

Initial

ININ

Select

SLCN

VO

IOWN

V/O

IORN

Reset

RSTN

Data

DO

Data

Di

+5V

VCC

Data

D2

Data

D3

Data

D4

Data

DS
D6

Data

ESCHUSHERSBESBENBUELREB

Bit 7 In
Bit 0 Out

Line

Bit 1 Out

Line

Bit 2 Out

Line

Bit 3 Out

Line

Bit 4 Out

Line

Bit 5 Out

Line

Bit 6 Out

Out

Bit 7 Out

busy

#7

Select

Select

Reset

From

Write

Read

Bit 0 In
Bit 1 In

Bit 2 In
Bit 3 In
Bit 4 In
Bit 5 In
Bit 6 In

III

0

1

2

3

4

5

Printer

5-12

8)

RD

WR

S—3

AU

DACK

TC

DBO

DBI

DB2
DB3

DB4
DBS

DB6
DB7

DMA

IRQ

LDOR

LDCR

RST

ADD

WD37C65

—1

1

—1

2

—|

4

—I5
—46

—J

7

—8
—19

—Ä

10

—

11

—I

12

1

13

—J

14

—4

15

—1

16

—1

17

—4

18

—1

19

—|

20

FDC

390304-03

4

>=

VCC

39 — IDX

38 — TR

37

WP

36

>

RWC,

35 — HDL
34

>»

MO2,

33

»

MOI1,

2»

032

31 — vss
30 » DS

29 > STEP
28 — DIRC

7 > wD

26 > WE
235 » ITS

24 >»

DCVAL

23»

CLKI

22

>»

DRV

21

>»

CLkK

PC40-III

RPM

Ds4

DS3

SERVICE

MANUAL

D/P

PIN

NUMBER

72

2/2

3/3

4/4

5/5

6/6

7-14
7-14

15/15

16/16

17

17/18

18/19

19/20

20/21

21/

22

3

22/24

23/

/25
/26

24/27

MNEMONIC

RD

.WR

cs

AD

TC

DBO

thru

DB7

DMA

IRQ

LDOR

LDCR

RST

RDD

CLK2

xT2

XT2

DRV

CLKI

xTi

xTi

PCVAL

SIGNAL

NAME

READ

WRITE

THIP

SELECT

ADDRESS

ACKNOWLEDGE

TERMINAL

DATA

DATA

DIRECT

INTERRUPT

OPERATIONS

LOAD

READ

DRIVE

PRECOMPEN-

SATION

DMA

COUNT

BUS 0 thru

BUS

MEMORY

ACCESS

LOAD

REGISTER

CONTROL

ISTER

RESET

Disk

DATA

CLOCK2

XTATZ
XTAL2

TYPE

CLOCKI

XTALI
XTALI

VALUE

LINE

1/0

FUNCTION
Control

signal

for

transfer

of

data

or

status

onto

the

data

bus

by

the

Control

signal

for

latching

data

from

the

bus

into

the

Selected

when 0 (low)

Address

line

Used

by

the

or

PC/AT

signal

indicates

TC

will

requires

by

DACK,

error

bi-directional,

request

Operation

request

in

base

connected

decode

the

data

decode

LSBs

from

controller,

is

the

raw

level

clock

oscillator

oscillator

type

input

never

be

level

clock

have

40/60

oscillator

oscillator

level

signal.

of

the

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be

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tion,

fied

mination

VO

7

8-Bit,

DMA

the

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driven

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latches

Address

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data.

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XTAL

XTAL

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may

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XTAL

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PRECOMPENSATION

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selecting

controller

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qualified

the

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whether

at

the

for

byte

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indicating

mode.

in

the

which

bus

which

the

placing

serial

input

drive

input

indicates

selected

input

or

drive

input

diskette.

allowing

data

this

10

WD37C6S5

by

in

DMA

completion

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transfers

This

In

Special

44

Pin

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into

the

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data

bus

microsequencer

bit

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output

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duty

output

requiring

VALUE

Logic 1 -

RD

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or

status

to

transfer

signal

that

DACK,

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or

non-DMA

of a command.

data

of

data.

pin

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the

completion

or

PC/AT

PLCC.

the

loading

Operations

loading

into

the

from

non-standard

for

44

for

non-standard

the

device

be

to

generate

cycle.

for

44

16MHz

select

125ns,

or

WR

operation

(-0)

data

is

qualified

data

transfer

but

not

in

the

signal

DMAEN

Host

bus.

DO

is

In

Special

driven

in

of

command

Mode,

of

the

Register.

of

the

Control

Control

in

idle.

the

disk

drive.

data

Pin

PLCC

that a two-speed

grounded.

all

internal

Pin

PLCC

erystal.

input.

This

Logic 0 -

WD37C65

from

information.

from

the

WD37C65

by

DMAEN

is

complete.

programmed

to

operation.

the

least

significant

or

PC/AT

the

Base

Mode.

execution

this

pin

Operations

Register.

Register.

Resets

device

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falling

rates;

Is

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data

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spindle

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This

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pin

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187

ns.

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be

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6).

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motor

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Buffer

Host.

onto

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this

or

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edge

of

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be

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true.

bit

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pin

data

enabled

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Puts

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300

driven

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used

data

for

all

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the

bus.

Operations

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Note

also that

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in

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standard

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WR

Is

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Register.

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or

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is

the

most

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requests

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with

WR

creates

in

Base

can

only

if

TTL

level

is

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if

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rates,

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Special

will

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the

Mode,

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active

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the

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disk

disk drive

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the

the

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is

for

disk

is

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be

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the

disk

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on

the

motor.

to

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Mode,

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output

Mode,

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disk

drive

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of

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against

CURRENT

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when

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disk

diskette.

data

pulse

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the

the

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the

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its

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910,

APPENDIX

DRIVE

40MB

Hard

Vendor

Model

:
:

with

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Floppy

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Model

920

:

:

with

ADD

SECTION

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Drive

PN

Quantum

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Permission

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Drive

Chinon:

FZ506

Permission

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B

DRIVE

#313065-01

40AT

of

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DISK

PN

#380825-02

of

Chinon

NOTES

Corp.

DRIVE

America

All

Inc.

rights

.

All

reserved.

rights

reserved.

INFORMATION

COMMODORE
OEM

The

information

Commodore
drive

exchange

ASSEMBLIES.

included

service

program

will

in

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provide
will

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THIS

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IS

FOR

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for

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The

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The

Quantum

ters

as

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84

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40AT

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file

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movable

to

of

parts,

and

will

will

be

used

programmed

with

reassignment

dedicated

fixed

disk

42

an

the

embedded

disks

with

the

user.

close

refer

to

V/O

11-bit

landing

disk

commands

drives

to

168

megabytes

IBM

PC-AT®

40AT/80AT

adapter

AT

three

heads.

The

control

to

refer

burst

of

new

Media

either

specifically

correction

zone

using

non-removable

board,

adapter

movable

defects

ProDrive

of

product

the

defective

and a variety

embedded

can

plug

the

ProDrive

or

into

heads;

and

Series

quality

ProDrive

to

the

capability

sectors

rigid

controller

directly

an

existing

the

ProDrive

error

drives

during

40AT

42

and

without

disk

plat-

of

interfaces.

and

into a 16-bit

40AT/80AT

adapter

80AT

recovery

feature

manufac-

or

the

an

84

need

are

are

in-

PHYSICAL

Environmental

Ambient

Ambient

Altitude

Temperature

Relative

(relative

SPECIFICATIONS

Limits

—

Humidity

to

sea

level)

AIRLOCK®

Non-Operating:

Operating:

—

Non-Operating:

Operating:

—

Non-Operating:
Operating:

©Copyright

ProDrive'“

and

and

ProDrive

DisCache®

1988,

Quantum

Series”

are

registered

Printed

—40°F

42°F/hr

39°F

to

23°F/hr

5%

to

Maximum

8%

to

Maximum

—200
—-200

Corporation.

are

trademarks

trademarks

in

U.S.A.

to

140°F

(20°C/hr)

122°F

(10°C/hr)

95%

without

wet

85%

without

wet

(-60M)
(-60M)

All

of

(-40°C

gradient

(4°C

to

50°C)

gradient

condensation

bulb = 115°F

condensation

bulb = 79°F

to

40,000

to

10,000

rights

reserved.

Quantum

of

Corporation

Quantum

Corporation

to

ft.
ft.

65°C)

(46°C)

(26°C)

(12

km)

(3

km)

B-1

PC40-IH

SERVICE

MANUAL

Mechanical

Dimensions

Height = 1.625

Width

Depth

=

=

4.0

5.75

Weight = 1.9

Heat

Dissipation

Average

Typical

Shock

The

cipal

or

is

Power

Power

and

table

drive

vibration

powered

Vibration

below

base

level

up

VIBRATION:

5-500

Hz

1

Oct/Min

SHOCK:

%

Sine

11

msec

In

addition,

on

all

and

1.5

the

surfaces,

G,

100-500

(Exclusive

in.

(41.3

in.

(101.6

in.

lb.

(0.88

Consumption

mm)

(144.9

kg)

Consumption

lists

specified

axes).

The

listed

during

after

being

Sine

Wave

Sine

Wave

of

Duration

ProDrive

six

edges

Hz

as

and

(0

mm)

mm)

(idle):

(30%

levels

term

“‘operating’’

operation.

subjected

(Peak

Sweep

(10

hits

packaged

three

to

Peak).

of

Faceplate)

Seeking):

for

shock

““Non-operating”

to

the

to

Peak)

maximum)

in

the

corners.

It

8

YWatts

and

vibration

implies

listed

shock

Vibration

shipping

will

withstand

Watts

that

or

and

10 G (1

(6 G No

container

(27.3

(30.7

BTU/Hr)

applied

the

drive

implies

vibration

Shock

Operating

0.50

soft

vibration

BTU/Hr)

to

any

will

be

that

there

in

the

Specification

G

error/shock)

soft

errors)

will

withstand

applied

of

the

three

fully

functional

will

be

no

powered-down

drops

to

the

container

mutually

change

perpendicular

while

being

in

performance

(non-operating)

Non-Operating

2.00

G

60

G

onto a concrete

of

0.5

subjected

surface

G,

5-100

axes

(the

to

the

once

the

condition.

from

48

Hz

(0

to

prin-

shock

drive

inches

Peak)

PERFORMANCE

Capacity

Formatted

Number

*40,

and

Data

Transfer

Seek

Times/Miscellaneous

DESCRIPTION
Single

Average

Y

Stroke

Full

Stoke

Average

Sequential

Power-Up

Rates

Track

Seek

Seek

Seek

Rotational

Head

Time

SPECIFICATIONS

capacity

of

512

80

Seek

(msec)

(msec)

megabytes,

byte

(msec)

(MB)

sectors

Buffer

Disk

Times

(msec)

Latency

Switch

(sec)

(msec)

respectively

to

AT-Bus

to

Buffer

NOMINAL

CONDITION

(msec)

ProDrive

40AT

42*

82,029

when a megabyte

-

Up

-

Up

to
to

is

defined

4.0

Mbytes/second

1.25

Mbytes/second

TYPICAL

6

19 21

20

35

8.2

3.0 3.0

13

ProDrive

84*

164,058

as

220

bytes

using

programmed

in

bursts

MAXIMUM

NOMINAL

CONDITION

7

23 25

40

8.2

15

80AT

I/O

WORST

CONDITION

7

23

45

8.2

3.0

18

CASE

PC40-IH

SERVICE

MANUAL

NOTES:

Media

The

completely

and

Error

Quality

ProDrive

ECC

Rates

Quoted
the

Seek

random

Sequential
to

track

Power-up

commands.

time

times

the

skewing

seek

required

seeks.

beginning

Nominal

vibration.

features

transparent

capability.

Random

Defect

Unrecoverable

Seek

times

are

measured

In

head

switch

of

feature

time

is

the

conditions

Worst

case

defect

to

the

Data

Data

Errors

Errors

(5):

include

for

the

head

actuator

by

the

rare

occurrence

time

the

next

of

the

time

from

are

defined

conditions

management,

user.

See

Errors

Data

(2):

(3):

Errors

settling

averaging

is

the

sequential

drive.

the

as

Appendix C for a detailed

(4):

to

time

(See

supply

25°C

are

which

time

seek

and

1000

seeks

of a seek

required

sector,

Appendix

voltages

ambient

defined

eliminates

but

do

settle

of

error,

for

located

temperature,

as

worst

l

error

l

error

l

error

l

error

not

on

the

any

the

B.)

reach

the

include

track.

indicated

individual

head

on

the

operating

case

extremes

need

to

description

per

1010

per

1012

per

1014

per

106

command

length.

to

move

next

track,

range

nominal

manually

bits
bits

bits

seeks

overhead

Average

seek

may

from

the

same

to

the

supply

of

temperature

indentify

of

the

ProDrive’s

read

(maximum)

read

(maximum)

read

(maximum)

(maximum)

or

seek

take

up

end

of

cylinder.

time

the

voltages,

and

defects.

latency

time

to 5 seconds

the

This

drive

and

is

the

last

time

no

supply

time.

sector

is

able

applied

voltages.

Defect

defect

handling

Seek

time

average

is

of

for

recovery.

on a track

fixed

to

accept

by

shock

management

procedure

is

1000

the

all

or

is

Error

rates

are

1) A data

different

2)

Random

a

will

3)

Defect

and

4)

Unrecoverable

error

specified

not

be

errors

cannot

sectors

errors

either a repeating

5) A seek

through a full

error

FUNCTIONAL

Nom

Max

Recording

Max

Flux

Track

Data

Data

R/W

Disks

Encoding

defined

is

number

automatically

are

be

is

as

follows:

one

(1)

sector

under

any

are

those

which

of

retry

those

which

read

without

errors

are

those

error

pattern,

any

seek

in

recalibration

SPECIFICATIONS

Rotational

Speed

Density

Density

Density

Cylinders

(fci)

(tpi)

Tracks

Heads

Scheme

read

incorrectly.

of

the

specified

do

not

exhibit a repeating

reads;

reallocated

which

routine

the

default

since

exhibit a repeating

error up

whose

or

the

to

final

eight

drive

to

locate

(RPM)

(bpi)

conditions

is

the

that

point.

retry

attempts

does

the

PHYSICAL

Data

eight.

errors

error

error

not

desired

error

rates

except

error

(Retries

are

probably

pattern,

Such

errors

pattern

without

locate

cylinder. A full

are

applied

pattern,

are

i.e.,

the

are

is

uncorrectable

reading

the

desired

FORMAT

ProDrive

defined

terminated

not

likely

shock

i.e,

due

error

as

the

occurs

due

correctly.

cylinder,

recalibration

3,662

+0.3%

22,055

14,700

1,000

834

2,502

RLL

average

or

error

once

to

media

to

using

40AT

3

2

2,7

rates

vibration.

does

data

defects.

twice

in a row

media

ECC:

or

any

seek

takes

measured

not

occur

is

read

correctly.)

within

defects.

retry

reads

.

in

which

approximately

ProDrive

3,662

22,055

RLL

over

twice

eight

are

the

80AT

+0.3%

14,700

1,000

834

5,004

2,7

at

least

in a row

The

retry

terminated

drive

five

6

3

1000

within

sectors

reads,

by

must

go

seconds.

PC40-III

SERVICE

MANUAL

The

logical

RELIABILITY

MTBF

PM

(Preventative

MTTR

Start/Stop:

ACOUSTICS

Idie

Mode:

layout

Data

Sectors/Track

R/W

(Mean

(Mean

45

is

how

the

Cylinders

Heads

SPECIFICATIONS

Time

Between

Maintenance):

Time

To

Repair):

dBa

maximum

drive

appears

Failure):

at 1 foot

in

to

any

LOGICAL

an

AT-Bus

direction

system.

50,000

Not

required

30

minutes

10,000

FORMAT

POH

(Power

cycles

ProDrive

965

On

Hours)

40AT

17 17

5

typical

ProDrive

965

10

usage

80AT

ProDrive

Mechanical

Dimensions

All

dimensions

in

millimeters

B-4

PC40-III

SERVICE

MANUAL

MOUNTING/DIMENSIONS

The

drive

may

be

mounted

Clearance from

HEIGHT

WIDTH
DEPTH

WEIGHT

the

1.625

in.

4.0

in.

5.75in.

1.9lb.

3.5+.10

Y—

F

A

drive

41.3

101.6

146.1

0.88

0

to

44

(DIMENSIONS

in

any

orientation.

any

other

mm

mm

mm

kg

tr

59.1+.15

surface

EXCLUSIVE

(except

[

Dit]

b

+3

shock

OF

FACEPLATE)

mount

brackets

or

faceplate)

rs

should

J

59.1+.13

be

0.10

inch

Typ)

|}

I

minimum.

1443

44.54.15

H

41.3+.40

kb

-—b|

41.2+.40

4-12.7+.15

[_]

1016+.30

„=

Et

DIMENSIONS

PC40-IT

HARD

ARE

DRIVE

IN

MILLIMETERS;

ILL.

44.54.13

+

|

-—i

SCREW

|}

I-12.7+.15

SIZE

IS

6-32

B-5

PC40-III

SERVICE

MANUAL

POWER

No

the

line,

REQUIREMENTS

damage

sector

and

transient

VOLTAGE

NOMINAL

TOLERANCE

CURRENT

TYPICAL
TYPICAL

MAXIMUM

RIPPLE

AND

AVERAGE
TYPICAL
MAXIMUM

POWER
When

down,

RESET

powering

the

or

loss

being

NOISE

POWER

POWER

POWER

drive

becomes

of

data

written

to

voltages + 10%

(IDLE)
(SEEKING)

(POWER-UP)

(MAXIMUM)

CONSUMPTION

CONSUMPTION

LIMITS

up, the

drive

reset

occurs

at

the

remains

when

if

power

time

of

to — 100%

(30%

reset

either

is

applied

the

power

SEEK)

(inactive)

supply

PC40-III

from

voltage

5V

12V

PIN

1

2

3

4

or

removed

loss.

nominal,

0.5A

0.8A

8W

9W

until

drops

Power

Signal

Ground
Ground

in

any

This

includes

while

powering

+12V
+12V
+10%

1.6A
100mVp-p

11W

both

supplies

below

the

4.50V

TO

4.20V

10.4V

TO

9.70V

Connector - HD

+12

Volts

+5

Volts

order

opening

reach

lower

or

manner,

up

or

up

or

0.5A

0.6A

0.65A
50mVp-p

the

upper

threshold

shorting

down.

+5V
+5V
+5%

value.

except

out

threshold

Hysteresis

that

either

value.

data

may

be

voltage

When

is

50m V minimum.

or

powering

lost

return

in

DC

POWER

The

DC

Board

utilizes

Pin 1 +12
Pin 2 +12
Pin 3 +5
Pin4

NOTE:

CONNECTOR

power

connector

(PCB)

near

the

AMP

pins

[P/N

volts
volt

volt

+5

volts

Pins 2 and 3 are

AT-Bus

350078-4

DC

return

return

DC

(J1)

is a 4-pin

connector.

(ground)

(ground)

connected

DuPont

See

(strip)

on

or

the

P/N

drive.

FIGURE 1 —

Connector

Figure

61173-4

DC

(SK

1.

The

(loose

POWER

20055-000)

recommended

piece)].

J1

CONNECTOR

mounted

mating

pins

on

connector

are

labeled

(1)

the

back

on

edge

(P2)

the

of

the

(AMP

P/N

connector.

Printed

1-480424-0)

Circuit.

PC40-III

SERVICE

MANUAL

AT-BUS

One

Interface

Connection

provided

NOTE:

JUMPER

Configuration

describes

tion.

INTERFACE

AT-Bus

and

to

Unkeyed

OPTIONS

the

Figure 3 identifies

interface

Commands.

to

prevent

cable

J2

is

through a 40-pin

incorrect

mating

of a ProDrive

user-selectable

CONNECTOR

connector

installation

connectors

jejelalaleisieleintelainielaleieieinieie]

OSOSOOSSHHSHscosscscscoonnannoann

4dAT/80AT

hardware

the

location

(J2)

is

required

Universal

of

should

FIGURE 2 —

of

disk

options

the

not

shorting

Header

the

mating

be

CENTER

AT-BUS

drive

available

for

the

connector. A connector

connector.

used

due

INTERFACE

varies

depending

on

the

plugs

ProDrive.

to

KEY

a4-—

Details

The

recommended

the

possibility

SLOT

(BOTTOM

POSITION

CONNECTOR

on

the

disk

drive

PCB.

and

terminators

of the

of

system

These

on

the

signals

sketch

mating

plugging

VIEW)

#1

INDICATOR

(J2)

in

which

jumpers

drive

required

is

shown

the

PCB.

connector
connector

it

is

to

should

in

be

can

Figure

be

be

found

2. A key

for

in

backwards.

installed.

set

prior

J2

in

is

This

to

AT-Bus

slot

xxxxx.

section

installa-

is

NOTE:

Additional

the

drive.

BACK

DRIVE

jumper

DC

OF

options

CONNECTOR

are

provided

(1)

E

FTTTRTTERTERETERTTN

JUMPERS

AT-BUS

on

the

adapter

000

CONNECTOR

board

for

systems

MICROPROCESSOR

2

(32)

in

which

the

adapter

HDA

FACE

SIDE

board

is

used

CONNECTORS

PLATE

with

FIGURE 3 —

Shorting

Plug

Locations

on

the

Drive

PCB

SELF

SEEK TEST

The

self

seek

test

perform

the

The

DRIVE

Two

drive,
is
drive

The

RESERVED

The

FACEPLATE
The

command

ADAPTER

This

ADAPTER

Five

See

J2 - Allows

J3 - Always

J4 - Forwards

J5 - Secondary
J6 - For

random

drive,

until

ProDrive

SELECT

drives

and

the

configured

(Drive

ProDrive

third

jumper

green

LED

and does

section

jumpers

Figure

BIOS

e

for

e

for

manufacturers

the

is

can

be

other

as

1).

is

JUMPER

LED

BOARD

is

relevant

BOARD

labeled

for

the

the

does

systems

systems

open.

IO

INTRODUCTION

The

ProDrive

With

the

the

Adapter

or

existing

ADAPTER

The

Adapter

bus

D8-D15,

and

performs

system

NOTE:

AT-BUS
The

AT-Bus

a

total

The

drive

40AT/80AT

Adapter

Board,

Adapter

BOARD

Board

IRQ14

address

BIOS,

are

Some

host

not

be

acknowledged. A jumper

interrupts

INTERFACE

interface

of

four

drives.

always

ELECTRICAL
All

signals

greater

than

are

TTL

0.0

OPTION

continuously

seek

patterns,

shorting

sent

from

daisy-chained

as

the

the

primary

sent

from

is

reserved

exercises

verifying

plug

is

the

factory

on

secondary

drive

the

factory

for

future

removed,

the

(Drive

OPERATION

located

drives

not

board

not

only

JUMPER

J2

locations

interrupt

read

that

that

Option

CH

RDY

enable.

Board,

the

drive

on

the

go

off

for

through

of

the

do

not

do

read

for

to

use

only; do

uses

the

ProDrive

is

faceplate

until

systems

OPTIONS

J6

are

the

jumpers

logic

STATUS

read

the

grounding

the

drive

the

standardized

compatible

Board.

is

an

IBM

PC

AT

and

IO

CS16.

The

decoding

located

systems

to

be

controlled

on

will

the

not

of

drive

the

read

by

CHARACTERISTICS

supports

Regardless

maintains

one

of

control

or

the

of

CHARACTERISTICS

compatible

volts

but

less

than

with a logic

0.7

the

actuator

track

with

shorting

AT-Bus

drive,

using

0);

with

with

the

use.

illuminates

the

command

which

provided

on

to

control

register

the

STATUS

STATUS

pin

for

not

install a jumper.

can

plug

with

I/O

bus-compatible

Adapter

Host

Address

itself.
the

STATUS

option

the

drive’s

two

hard

number

the

bus;

one

volts.

IDs

after

or

until

interface.

the

Drive

no

DS

shorting

when

is

implement

on

the

the

PCB.

IRQ14.

when

register,

register,

#34

of

use

with

IBM

directly

other

AT-Bus

Board

register

is

provided

interrupt

disk

of

drives,

there

being

of

the

drive.

every

an

error

plug

SS

When

Select

shorting

the

completed

the

adapter

This

the

drive

jumper

jumper

the

drive

systems

PC

AT

Bus

into a 16-bit

interface.

buffers

Bus.

The

after

on

the

logic.

drives

per

there

is

no

arbitration.

greater

When

seek.

The

has

occurred.

not

installed

two

drives

are

(DS)

jumper.

plug

on

jumper

plug

installed

drive

is

executing a command.

or

aborted.

ProDrive

board;

jumper

issues

from

interface.

running

interface

architectures

data

Task

the

Adapter

See

adapter

is a master/slave

than

AT-Bus

the

is

an

from

the

center

Chips & Technologies

expansion

The

and

control

File

drive

Board

jumper

board,

2.0

volts

shorting

pattern

(Self

Seek

attached,

With

DS,

(Drive

functions

provided

interrupt.

the

center

pin

and

is

available

slot

and

can

I/O

extended

signals

Registers,

issues

an

to

option

and

relationship

but

PC40-III

plug

option

will

repeat

Test

one

the

DS

the

drive

0)

drive

with

of

these

for

compatibility

pin

of

of

J2

on

an

AT

be

plugged

bus

between

which

interrupt.

overcome

J2.

will

accomodate

less

that

SS

as

disabled).

must

shorting

is

It

the

jumpers

J2

to

to

E3.

chip

with

or

compatible

into an

connector

the

accept

In

this

between

5.25

volts,

SERVICE

is

installed,

long

as

power

be

configured

plug

installed,

configured

lights

at

the

adapter

E4;

without

drive

commands

such

problem.

board.

are

with

set.

an

computer.

embedded

is

and

cases,

This

two

adapter

the

host

and a logic

MANUAL

the

is

applied

as

the

as

the

secondary

beginning

described

systems

Adapter

AT

required

the

host

from

the

interrupt

jumper

boards

and

zero

drive

primary

the

drive

below.

whose

Board.

Without

Adapter

for

data

system,

the

host

allows

the

drive.

being

will

of

will

for

to

a

B-8

PC40-IH

SERVICE

MANUAL

AT-BUS

The

ting
interface.

NOTE:

SIGNAL

—-HOST

GROUND

HOST

D0-D15

INTERFACE

AT-Bus

cable

Refer

The

AT-Bus

NAME

RESET

DATA

GROUND

KEY

-HOST

GROUND

-HOST

GROUND

-HOST

GROUND

RESERVED

HOST

RESERVED

GROUND

HOST

-HOST

HOST

IO

IOW

IOR

ALE

IRQ14

IO

ADDR

GROUND

HOST

HOST

-HOST

-HOST

-HOST

ADDR

ADDR

CS0

CS1

SLAVE

GROUND

SIGNALS

interface

connector

is a 40-conductor

to

Table 1 for

direction

Table 1 is

connector.

IN

CHRDY

CS16

1

0

2

flat

DIR

/O

OUT

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

is a 40-pin

ribbon

the

AT-Bus

in

reference

TABLE 1 —

PIN

1

2

3-18

19

20

21

22
23

24

25

26
27
28

29

30

31

32

33

34
35

36

37

38

39

40

shrouded

connector

with a maximum

interface

to

the

pinouts

drive,

AT-Bus

DESCRIPTION

Reset

signal

Ground

16-bit

bi-directional

D0O-D15
READ/WRITE.

register.

These

are

Ground

Unused

Enables

Driven

Ground

Write

strobe.

D0-D7

Ground

Read

strobe.

D8-D15

Ground

Reserved

Address

tain

compatibility.

Reserved

Ground

Interrupt

drive

interrupt

drive

is

upon

receiving

the

drive

Informs

drive

is

24mA

driver.

Address

drive.

Ground
Address
drive.
Address

drive.

Decoded

task

file

Decoded

diskette

Indicates

drive

is

Ground

length

and

i.e.,

Interface

from

between

are

used

tri-state

between

pin

for

host wait

low

by

between

Clocks

and/or

between

Clocks

on

the

between

for

future

Latch

for

future

between

signal

not

selected

is

reset.

the

host

prepared

line

from

between

line

from

line

from

address

registers

address

function

the

presence

present.

between

with

two

rows

of

18

inches.

their

relationship

IN

means

Pin

the

host

host

system

data

to

transfer

Data

Bit

lines

host

system

keying

the

D8-D15

rising

Enable

to

enable

the

ribbon

state

generation

drive

immediately

host

system

data

host

system

data

edge

host

system

definition.

from

definition.

host

system

the

host.

bit

or

the

next

that

one

to

perform a 16-bit

the

host

host

system

the

host

the

host

select

from

is

desired.

select

from

registers

of a second

Open

collector

system

host

of

20

Table 1 describes

to

the

drive.

Assignments

system;

and

bus

between

8-bit

D7

is

disabled

with

24mA

and

cable

and

from

the

on

the

rising

and

from

the

of

-HOST

and

the

host.

and

Active

is

high.

interrupt

command,

of

the

drive

to

the

and

to

the

to

the

the

the

is

desired.

output

and

male

pins

with

PINS

active

drive.

the

information

when

drivers.

drive.

to

the

to

lengthen

upon

drive.

OF—-HOST

edge

drive.

drive

IOR.

drive.

Not

currently

drive.

only

Goes

to a high

enable

when

registers

I/O

drive

that

drive.

drive

that

drive

that

host

indicating

host

indicating

drive.

with

drive.

on

100

mil

each

signal

the

AT

system

are

in

reference

low

during

host

the

drive.

the

and

host

I/O

system

the

for

reads

read

detecting a valid

to

the

of

HOST

to

host

when

bit

is

the

status

has

transer.

is

used

is

used

is

used

When

24mA

IOW.

data

used,

the

drive

impedance

low.

The

register

been

Open

to

select a register

to

select a register

to

select a register

that

access

that

access

this

signal

driver.

centers.

on

bus.

drive.

register

the

and

1/)

drive

over data

lines

DO-D7

but

provided

is

selected

state

interrupt

is

enabled

collector

to

to

is

The connec-

the

AT-Bus

to

the

40-pin

power-up.

and

ECC

digital

input

write

cycles.

address

read

low, a second

when

is

and

output

one

one

select.

lines

and/or

to

main-

and

cleared

or

when

that

with

on

on

on

of

the

of

the

the

the

the

the

the

the

8

3

AT

SYSTEM

The

table

for

the

NOTE:

below

AT-Bus

The

direction

40-pin

BUS

presents

interface

AT

SIGNALS

the

pinouts

in

Table 2 is

system

bus

signals

and

in

connector.

on

the

AT

their

reference

system

relationship

to

the

host

bus

with

system,

that

are

the

AT

i.e.,

used

IN

by

system

means

the

AT-Bus

bus.

to

the

PC4#0-II

interface.

host

system.

SERVICE

You

should

PINS

are

in

MANUAL

refer

to

Figure

reference

to

the

SIGNAL
SAO-SA9

SD0-SD15

AEN

-IOW

-IOR

BALE

IRQ14

RESET

-IO

CH

NAME

RDY

DIR

OUT

I/O

OUT

OUT

OUT

OUT

IN

OUT

IN

TABLE 2 —

PIN

A22-A31

A2-AI&

C11-C18

All

B13

B14

B28

D7

B2

AIO

AT

System
DESCRIPTION
System

System

Signal

high.

Signals

Active

Signals

bus.

Active

Indicates a valid

high

to

System

when

changing

Used

to

Pulled

the

read/write

Bus

address

address

indicating a DMA

that

the

when

low.

that

the

when

low.

interrupt

reset

or

low

during a bus

Pin

Assignments

bus

bus

address

enabled

enabled

system

request indicating

low

initialize

cycles.

low.

to

I/O

device

I/O

device

address

high.

system

transaction

Open

collector

is

on

the

should

should

is

available.

an

I/O

hardware

by

an

onto

system

read

gate

Active

device

at

power

enabled

host

address

the

data

data

needs

up.

I/O

bus.

bus.

onto

when

attention.

Active

device

Active

on

the

the

system

changing

when

to

when

data

bus.

data

from

Active

high.

lengthen

AT-Bus

DISK

CONNECTOR

PIN

NO

1

2

3

4

5

6

7

8

9

10
11
12
13
14
15

16

17
18

SIGNAL

-HOST

GROUND

HOST
HOST
HOST
HOST
HOST

HOST

HOST

HOST

HOST

HOST

HOST

HOST

HOST

HOST

HOST

HOST

NAME

RESET

DATA
DATA
DATA
DATA
DATA

DATA

DATA

DATA

DATA

DATA

DATA

DATA

DATA

DATA

DATA

DATA

7

8

6

9

5

10

4

11

3

12

2

13

1

14

0

15

Interface

DIRECTION

*—

_

>
>
>
>
>

>

>

>
>
>

>
>
>

>

>
>

Pin

Assignments

nV

PIN

A2

A3

A4

A5

A6

A7

A9

B2

cl

c12

C13

c14

C15

C16

Aß

c17

c18

AT

NO

BUS

CONNECTOR

SIGNAL

RESET

GROUND

SD10

sD11

sD12

SD13

SD14

SD15

NAME

DRV

SD7
SD8
SD6
SD9
SD5

SD4

SD3

SD2

SD1

SDO

B-10

PC40-III

SERVICE

MANUAL

AT-Bus

DISK

CONNECTOR

PIN

NO

19

20

21

22

23

24

25

26

27

28
29

30
31
32
33
34
35
36
37
38
39

40

SIGNAL

GROUND

KEY

-HOST

IO

GROUND

-HOST

GROUND

-HOST

GROUND

RESERVED

HOST

RESERVED

GROUND

HOST

-HOST
HOST

GROUND

HOST
HOST

-HOST

-HOST

-HOST

GROUND

NAME

CH

IOW

IOR

ALE

IRQI14

IOCSI6

ADDR

ADDRO
ADDR2

CS0
CS1

SLV

RDY

1

Interface

Pin

Assignments

DIRECTION

_ u

—

Ben

—

_

ni

u

—

Bun

—
—

—

u

—
—

Bu

(continued)

PIN

A29

AT

BUS

CONNECTOR

NO

AI1O

En

B13

u

B14

.

B28

Bun

D7

D2 -IOCSI16

A30

u

A31

u

SIGNAL

GROUND

NO

CONNECTION

-IO

CH

GROUND

-IOW

GROUND

-IOR

GROUND

NO

CONNECTION

BALE

NO

CONNECTION

GROUND

IRQ14

SAI

GROUND

SAO
SA2

GROUND

NAME

RDY

NOTES:

CABLE

DC
DC

I/O

[1]

[2]

[3]

All

-HOST

signals.

CONNECTOR

DESCRIPTION

POWER
POWER

CONNECTOR

THESE

PROVIDED
PROVIDED

grounds

CS0,

PLUG
PIN

NUMBERS

BY

DRIVE

BY

COMMODORE

are

connected

-HOST

ARE

together

CS1

and

FOR

SIZE

VENDOR

on

the

-HOST

SLYV

DISK

DRIVE

CONNECTOR

AMP

1-4807222-0

AMP

350079-4

BURNDY

REFERENCE

ground

are

Recommended

FRHLAOR-2

plane

generated

Connectors

[2]

ONLY

on

of

[1]

the

the

adapter

adapter

board.

board;

there

HOST

CONNECTOR

AMP
AMP

BURNDY

(CPU)

1-480424-0

350078-4

are

no directly

[3]

FRS40BD-8P

related

AT-Bus

B-11

VO

INTERFACE

CIRCUIT

PC40-III

SERVICE

MANUAL

DIMENSIONS

FIRST

POSITION
INDICATOR

=]

350

ARE

gr.

ll.

IN

INCHES

—+

F-

—rTz

024

m

DC

NOTE:

161

NOTE:

GROUND

Wiring

Wiring

shall

be

GROUND

shall

be

ribbon

CIRCUIT

ribbon

cable

cable

100K0

or

or

twisted

twisted

7

2

pair.

pair.

0.014F

SIGNAL

GROUND

03

05

06

07

08
09

CBM

PART

903451-10

903733-10

903753-10
906475-05

NUMBER

324594-02

905451-01

AC

N

H

[

GROUND

J

F

GROUND

TERMINAL

TERMINAL

TERMINAL

LEAD

WIRE

=)

CABLE

DESCRIPTION

4.6 X 0.3

RING

TONGUE & 4.3

RING

TONGUE # 3.2

LEAD

AWG

TUBEHEAT

18

FRAME

46247

DIN

DIN

60

=

46234

MM

ASSY. — 380811-01

DIN

WIRE

BLACK L =

SHRINK

u

GROUND

=)

(0)

-O)—

4623

STRIPLENGTH 2 X 3 MM

VENDOR

WEITKOWITZ

MOLEX

44113

AA

B-12

PC4-III

SERVICE

MANUAL

PC40-III

SCOPE

This
FEATURES

The

(1)

(2)

(3)

(4)

(5)

FLOPPY

specification

features

Large

Capacity

The

FZ-506

read/write

by

changing

retrieval

Pop-up

With

the

insertion.

Low

Power

As a newly

consumption
system

Built-in

With

the

reduces

disk.

DISK

Various

With

the

used

without

DISK

describes

of

the

FZ-506

Up-to

is a double-sided,

selection

either

from

250K

Mechanism

newly

employed

Consumption

designed

are

achieved.

design

Disk-in

built-in

power

CHANGE

Disk

FZ-506,

easy.

sensor

disk-in-sensor,

consumption.

Readings

the

any

conversion.

DRIVE — 380825-01

5-% ” double-sided

are

as

follows:

1.6M

bytes

high-density,

of

the

high

density

the

motor

speed

bytes,

48

TPI

disk

LSI

signal

various

pop-up

(C-MOS

In

stand-by

When

will

disk

mechanism,

chip)

when

be

readings

96-TPI

1.6M

(360

rpm/300

to

500K

is

employed

mode,

no

disk

chucking

output

(Dark

Bezel);

minifloppy

double-track

bytes,

96

rpm)

bytes,

96

the

disk

in

the

power

consumption

is

loaded,

the

disk,

by

the

sensor,

shown

below

380825-02

type

TPI

and

or

transfer

TPI

can

be

read/write

the

the

DD

also.

are

(Light

disk

drive

(hereafter

and

its

capacity

double

disk

loaded/unloaded

motor

motor

possible,

rate

is

possible,

and

is

only

is

is

existing

density

(500K

control

1.59W,

stopped.

rotated

Bezel)

abbreviated

is

1.6M

IM

bytes,

BPS/300K

the

former

with

ease,

circuits,

and

This

temporarily

software

bytes,

96

BPS).

software

preventing

high

in

operation

extends

to

written

as

FDD)

CHINON

in

unformatted

TPI

disk

can

In

addition,

packages

mischucking

performance

mode

the

motor

assure

in

48

the

TPI

mode.

be

carried

as

can

and

low

3.81W,

service

centering

format

FZ-506.

The

out

the

data

be

read.

at

disk

power

making

life

and

of

the

can

be

. .

Disk

Track

Transfer

*

Data

Density

Storage

Capacity

Rate

of

Rotational

Speed

Data

Read

Data

Write

can

Used

Data

be

read

Normal

48

TPI

250

KB

250K/300K | 250K/300K | 250K/300K | 250K/300K

BPS

300/360

rpm

o

"oO

by

this

drive,

but

500

300/360

data

can

KB

BPS

rpm rpm

oO

*o

not

Density

be

read

96

TPI

500

KB

BPS BPS

300/360

oO oO

oO oO

by a head

made

300/360

1MB

rpm

solely

for

48

High

Density

96

1.6

500K

360

oO

oO

TPI

use.

TPI

MB

BPS

rpm

B-13

SPECIFICATIONS
Specification

(1)

PC40-III

SERVICE

MANUAL

Item

Recording

2

o©

&

©

5

&

S

u

Recording

Rate

E

a

°

<

Rotation

Number

Number

Track

Number

Number

$

5

oa

3

& | track

mode

Unformatted

Formatted

density

of

data

transfer

Power-on

Single

Average

Settling

Average

speed

of

of

density

of

of

Outer

track

Inner

to

track

access

time

latency

tracks

cylinders

heads

index

ready

seek

Per

disk

Per

track

Per

disk

Per

track

Number

of

sectors

Per

sector

time

time

time

time

Side

O

Side

.

Side

O

Side

HIGH

DENSITY

FM

833

KB

5.208

4935

250K

615

3840

256

KB

KB

B

B

BPI

BPS

15

83.3

msec

360

rpm

1

1

CHARACTERISTIC

MFM

1666

KB

10.416

1229

7680

9870

500K

512B

BPS

KB

KB

B

BPI

0.5

sec

3

94

15

57.150

55.033

36.248

34.131

96

NORMAL

FM

500

3.125

368.640

2304

128B

2961

125K/150K

or

msec

msec

msec

BPS

less

100

160

80

TPI

2

1

mm

mm

mm

mm

KB

KB

KB

B

16

BPI

|

msec/83.3

300/360

DENSITY

MFM

1000

6.25

737.280

4608B

256

5922

250K/300K

BPS

msec

rpm

KB

KB

KB

B

BPI

B-14

PC40-III

SERVICE

MANUAL

Specification

Physical

Weight

Power

Power

Ripple

Noise

Cabinet

(2)

Item

dimensions

supply

consumption Write

voltage

allowance

specifications

146

approx. 1 kg

DC

DC

Stand-by

Read

Seek

Spindle
Starting

(0.5

DC

DC

Less

Front

Front

(W) x 41

+12 V +5%

+5 V +5%

Motor

current

sec.

max.)

+12V

+5

V

than

55

panel

lever

(H)x

phons

193

(D)

(class

mm

+5

V

290

mA

330

mA

330

mA

260

mA

Less

than

Less

than

A)

(separated

Material:

Material:

Specification

+12

TYP.

TYP.

TYP.

TYP.

200

210

440

900

150

mVp-p

100

mVp-p

from

the

ABS

ABS

Color:

Color:

V

14

mATYP.

mA

mA

mA

mA

(including

(including

drive

TYP. 4.05

TYP.

TYP.

MAX.

spike

spike

by

1m)

Beige

Beige

POWER

1.62

WTYP.

WTYP.

4.17WTYP.

6.58

WTYP.

noise)

noise)

B-15

PC40-II

SERVICE

MANUAL

Installation

Mounting

Environment

Vibration

Drop

Conditions

Item

position

conditions

shock

Temperature

Humidity

Temperature

During

During

and

(W/Protect

Fall

(corner:

operation

non-operation|

storage

height

in

one

L

In

horizontal

change

sheet)

packing

time,

During

During

During
During

During

During

Continuous

Single

Continuous

Single

State:

sides:

—_—_

m 17

Horizontal

position,

operation

three

the

non-operation|

storage
operation

non-operation|

storage

.

vibration

vibration

70

cm

times,

vibration

vibration

Specification

front

panel

5.

O

-20 - 60°C
20 - 80%

5

8.-

15°C/H

aa

flat

surfaces:

can

be

45'C

..

50°C

RH

90%

RH

90%

RH No

Amplitude

Less

than

-

Amplitude

Less than

six

Vertical

raised a maximum

Maximum

No

dew

condensation

dew

condensation

Less

than

10G

(10

Less than 7 mm 5 - 9 Hz

30G

(10

times)

wet

bulb

0.5

mm 5 -.

0.25G
.

ms)

0.5G 9 -

ms)

of

15°.

temperature

25

25 - 100H

-

100

Hz

29°C

Hz

z

B-16

Reliability

Drive

Error

rate

Life

MTBF
MTTR

Drive

life

Software

Hardware

Seek

errors

Number

£

Seek

Head

5

Number

=

Number

errors

errors

of

of

of

Item

mountings

identical

mountings

of

track

the

media

passes

PC%-II

30,000

10,000,000

10,000 H or

3,000,000

10,000

SERVICE

Specification

10,000

Five

102

10-12

108

POH

0.5

H

years

times/bit

times/bit

times/seek

times

seeks

passes

times

or

or

more

or

or

more

more

more

more

MANUAL

*

Maintenance

*1

Reference

is

value

not

required

under

normal

use

conditions.

B-17

DIMENSIONS

PC40-III

SERVICE

MANUAL

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S

B-18

PC40-III

SERVICE

MANUAL

INTERFACE

The

interface

Signal

The

drives

(1)

Voltage

interface

have

Input

High

Input

(2)

Output

Low

High

Output
Output

Input

Signals

(1)

DRIVE

When

is

opened.

SIGNALS

signal

Levels

signal

the

following

level

level

impedance

signal

level

level

current
current

SELECT 0 to 3 signal

one

of

Up

SELECT 0 to 3 signal

(2)

MOTOR

This

When

operation

This

(3)

DIRECTION

This

signal
it

is

The

(4)

STEP
This

HIGH
However,

edge

(5)

WRITE

This

and

status

After

(6)

WRITE

Data

(when

(7)

SIDE

This

When

Side 0 stands

The

ON

line

controls

it

is

set

is

signal

signal

line

is

set

to

high

logic

level

signal

signal

level

this

of

the

GATE

signal

the

data

Occurs.

the

writing

DATA

written

the

signal

SELECT

signal

this

signal

selection

not

operates

determines

set

line

line

and

last

line

is

line

possible.

(8)

MODE

This

The

signal

line

SELECT

status

can

has

12

input

interfaces

(for
(for

these

to

four

signal

with

specifications.

low

level)

high

level)

lines

drives

lines

signal

line

the

ON/OFF

to

high

level,

executed

SELECT

to

level

of

this

moves

the

signal

STEP

signal

specifies
stored

when

independently

signal

the

direction

low

level

and

the

signal

the

head.

head

moves

is

not

pulse,

line

drive write

on

the

operation, a period

signal

line

on

the

disk

surface

line

changes

signal

line

selects

for

is

completed

be

the

line

is

set

the

one-sided

signal

line

selects’either

configured

to

100

signal

the

0V

+2.40V

1500

0V

+5.25V

48

250

lines

goes

into

can

be

controlled

is

determined

of

the

it

stops.

no

of

line

and

the

STEP

should

With

one

accepted

and

the

disk

surface

is

from

head.

high

level,

medium

microseconds

1.6M

in

positive

lines

and 5 output

controller

to

+0.40V

to

to

+0.40V

max.

mA

(max.)

„A

(max.)

low

level,

by

spindle

0.5

seconds

disk

is

loaded.

the

DRIVE

of

movement

STEP

signal

signal

pulse

be

held

the

rise

track

in

when

the

FDD

is

and

read

by

of

1.2

ms

transferred

the

high

the

side 0 head

recording

after

Byte

mode

or

negative

signal

at

the

TTL

+5.25V

(by

receiving

the

drive

using

these

the

position

motor.

for

status.
the

level

When

is

the

SELECT

of

the

pulse

is

is

sent,

at

least 1 microsecond

of a single

the

direction

FDD

is

in

ready

for

When

WRITE

is

necessary

on

the

signal

to

the

is

surface.

the

change

or

IM

logic

lines.

level.

For

the

corresponding

four

signal

of

the

short

this

signal

required

head

sent,

the

low

start

signals.

when a pulse

the

head

moves

level

determined

WRITE

data

DATA

read/write

this

signal

signal.

mode.

before a valid

line.

With

low

level),

selected;

Byte

by

when

of

the

mode.

position

all

signals,

end

terminator)

lines.

plug

line

up

head

pulse,

line

the

data

SIDE

of

short

to

the

The

drive

in

is

set

to

time

is

sent

moves

away

after

the

this

signal

by

the

The

head

operation.

is

set

When

this

READ

decline

is

written

it

is

set

SELECT

plug.

low

is

true.

signal

line

corresponding

the

drive.

low

level,

of

the

spindie

via

the

STEP

towards

from

trailing

the

line

the

center.

edge

changes

DIRECTION

is

stabilized

to

low

level,

signal

line

DATA

to

of

on

low

signal

signal

the

the

level,

line,

pulse

The

is

selected

the

spindle

motor.

center

of

SELECT

20

write

is

appears

disk

the

and

I/O

signal

and

to

one

of

motor

The

signal

line.

of

the

the

STEP

from

LOW

signal.

ms

after

enable

set

to

high

on

the

sent

to

this

surface.

side 1 head

read/write

level

the

the

revolves.

motor

When

disk.

pulse.

the

status

level,

interface.

signal

is

into

I/O

gate

DRIVE

start

this

When

level

to

trailing

occurs

read

line

selected.

becomes

the

B-19

PC40-III

SERVICE

MANUAL

Output

(1)

INDEX

Whenever

the
the

(2)

TRACK

When

motor

(3)

WRITE

When

level

disk

(4)

READ

This

mixed.

line

(5)

READY

When

When

ON

ming

(6)

DISK

This

when a disk

Signals

signal

pulse

signal

pulse

is

00

this

is

excited.

PROTECT

this

even

when

is

inserted.

DATA

signal

The

indicates

signal

this

the

READY

signal

is

write

CHANGE

signal

line

the

disk

rotates

(when

only

output

signal

line

signal

line

is

signal

signal

line

is

no

disk

signal

line

is

used

negative-going

the

readout

line

output

turned

and

signal

signal

ON,

read

operations.

signal

line

is

set

is

loaded.

this

set to

set

is

line

for

power

to

once,

signal

when

low

line

to

low

inserted

the

edge

data

line

is

is

ON,

low

level

this

line

the

disk

level,

level,

in

the

transfer

(the

(clock

set

to

read

is

supplied.

by

signal

changes

is

inserted.

the

head

the

drive.

of

the

moment

and

data

low

level,

and

write

After

power

line

outputs a low

from

is

located

inserted

The

write

pulse

of

change

pulses).

the

operations

the

on

or

high

level

at

the

disk

cannot

function

series

read

from

disk

is

inserted

can

be

disk

is

inserted,

when a disk

level

pulse

to

low

track

be

written

of

the

from

the

high

level

performed

check

is

ejected,

level)

00

drive

disk,

to

and

indicating

indicates

position

on.

This

becomes

in

which

low

level)

the

number

on

the

that

the

and

set

the

the

and

the

signal

of

of

disk.

READY

to

high

start

of

the

start

of

specific

line

inoperative

clock

pulses

the

pulse

disk

rotations

Immediately

signal

level

track. A decline

the

track.

phase

of

the

may

also

be

when

write-inhibited

and

data

output

is

by

is

after

ON

STEP

at

fixed.

the

before

signal

However,

stepping

set

to

low

pulses

are

this

signal

MOTOR

perfor-

input

of

POWER

DISK

ON

DISK

CHANGE

PT

IN

fS

|

|

B-20

Input

Signal

The

FZ-506

more

than one
disconnected.
the

input

signal

Line

is

operable

drives

(The

lines

Terminator

with

are

connected,

termination

has a 1500

either

resistors

daisy

termination

terminal

chain

can

resistor.

or

star

resistors

be

disconnected

chain

systems.

of

all

by

drives

taking

It

is

except

away

possible

the

the

PC40-III

to

use 4 pcs.

drive

at

short-plug

the

end

at

SERVICE

Drives

of

the

connector

by

interface

MANUAL

daisy

chain.

cable

JI-1)

When

must

Each

be

of

Interface

(1)

When

Circuit

Drives-receivers

recommend

the

following

CONTROLLER

I)

7458

or

equivalent

+5V

150N

<

4

equivalent

or

SIDE

drivers-receivers.

A

|

DRIVE

|

SIDE

Pr

7

7438

equivalent

or

__

+5V

|.

|

NL

CMOS

CONTROL

LOGIC

NL

(2)

Flat

Wire

cables

material

or

twisted

pair

wires

B-21

PC40-II

SERVICE

MANUAL

CONTROLLER

MODE

IN

DRIVE

DRIVE

DRIVE

DRIVE

MOTOR

DIRECTION

STEP

WRITE

SELECT

USE/HEAD

WRITE

SIDE

SELECT

SELECT

SELECT

SELECT

ON

SELECT

DATA

GATE

LOAD

3 8

0

1

2

2

4

10

12

14

16

18

20

22

24

DRIVE

6

INDEX

SIDE

DC

J

GROUND

SIDE

SELECT

+12V

+12V

t

SV

+

svoc

DC

RETURN

RETURN

32

©

®

©

®

26

28

30

34

TRACK

WRITE

READ

READY

100xNn

00

PROTECT

DATA

*

(DISK

*

possible

pi

——

| 4

CHANGE)

to

change

0.01pF

with

J

SIGNAL

J1

GROUND

AC

GROUND

FRAME

GROUND

B-22

PC40-II

SERVICE

MANUAL

POWER-ON

Recalibration

sequence.

SEQUENCE

of

the

head

600ms

position

max

is

performed

during

(

Setto
operating

the

power-sequence

Power

on

Reset

all

eircuit

|

the

Track

00?

No

Seek

to

zero

track

mode

)

of

the

FDD.

Executed

the

DRIVE

The

figure

regardless

SELECT

+1

track

step

in

below

signal.

of

shows

the

power-on

POWER

Power

The

+5V,

Frame

The

R = 100kK0

Connect

Power

(1)

(2)

DC

frame

The

the

If

the

on

SUPPLY

Supply

power

and

Ground

the

Supply

power

specified

drive

the

Specifications

(+12V,

the

two

ground

C = 0.014F

frame

Sequence

ON

value,

is

in a status

disk

are

INTERFACE

+5V)

return

and

ground

sequence

signal

should

not

destroyed.

lines).

ground

where

is

other

POWER-ON

shown

be

the

not

specified.

set to

than

However,

in

Specification

are

connected

AC

ground

100

write

Settothe

standby

and

However,

ms

or

less.

operation,

its

contents

mode

End

SEQUENCE

is

required

through a capacitor

DC

the

and

will

ground

time

the

be

by

the

are

one

in

which

DC

power

destroyed

power

supply.

and a resistor.

point

connected

the

supplied

is

disconnected,

if

the

WRITE

There

The

power

GATE

are

values

in

the

voltage

the

four

are

host

disk
is

not

power

as

follows:

system.

rises

and

the

set

up

to

lines

to

data

high

(+12V,

90%

stored

level.

of

B-23

PC40-III

SERVICE

MANUAL

INTERFACE

Interface

(1)

(2)

Pin

The

Connector

DC

power

Interface

Assignment

assignment

CONNECTOR

connector

Connector/housing

Pin

signal

connector

Connector

of

each

pin

OO

AND

is

shown.

PJ1

(l/O

FIR

MERDERZERERER

Ba

PIN

ASSIGNMENT

Connector)

AMP

or

This

34

LI

ie

Drive

Side

172349-1

equivalent

_

Drive

Side

Card

Edge

Connector

diagram

PJ2

shows

(Power

43

Host

Side

AMP

1-480424-0

or

equivalent

AMP

60619-1

or

equivalent

the

back

of

the

drive.

Connector)

2

=—

PCB

2

ı

au

°

+

°

2.35

7.81

PIN

ASSIGNMENT

MIN

sl

ı | ı

1.2704

0.9+0.1

af

ip!

| !

1.4+0.1

40.64+

2.54+0.08

0.1

! I

ı

CARD

45,34+0.13

EDGE

CONNECTOR

Thickness

r

——

ı

1.6+0.2

B-24

(1)

DC

(2)

Interface

Power

connector

Pin

signal

Pin

14

”2

number

1

2

3

4

connector

number

2

6

8

10
12
14
16
18

20
22

24

26
28

30
32
34

Signal

+12V

DC

+12V

RETURN

+5V

RETURN

+5V

DC

Signal

MODE

IN
DRIVE
INDEX

DRIVE
DRIVE
DRIVE

MOTOR

DIRECTION

STEP

WRITE
WRITE

TRACK

WRITE
READ

SIDE
READY/DISK

SELECT

USE/HEAD

SELECT

SELECT
SELECT
SELECT

ON

DATA

GATE

00

PROTECT

DATA

SELECT

LOAD

3

0

1

2

SELECT

CHANGE

Pin

number

1

3

5

7

9

11
13
15
17
19

21
23
25
27
29

31
33

PC40-II

Signal

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

SERVICE

MANUAL

GND:

*]:
*2:

SIGNAL

“HEAD

As

for

see

paragraph

GROUND

LOAD’

switching

9;

is

optional.

over

between

SHORT

PLUG.

READY

and

DISK

CHANGE,

B-25

PC40-III

SERVICE

MANUAL

SHORT
Short

The

This

CHINON

using

1.6

*1

1.6

ble,

1.6

*1.

*2.

PLUG

Plug

assignment

diagram

FZ-506

*‘SHORT-PLUGS”

MB

to 1 MB

Pin

#2

Pin

#2:

Pin

#2:

MB

to 1 MB

Pin

#2

Pin

#2:

MB

360

(Disregards

The

short-plug

PC40-III

AND

FRONT

of

each

pin

FRONT

CL.

shows

the

side

high

density

according

Mode

variable

as

change-over

High =1.6

High = 1

switchable

as

change-over

High = 1.6

rpm non-switchable

pin

is

Close

1,

MB

MB

#2

signal

factory

3,

6,

speed
signal

(300

MB

10,

LED

is

shown.

SIDE

0000

0000

1312111

of

the

drive.

1.6

MB

to 1 MB

to

the

descriptions

switchable

input

(360

rpm)/Low = 1

rpm)/Low = 1.6

at

360

rpm,

input

(360

rpm)/Low = 1

set

at

this

13

-

0.

o0

table

using

IBM

position.

...

1.0.0.0

.

.

000

.o

SHORT

switchable

below.

MB

(300

MB

(360

PC/AT

MB

...

.00

nenne

PLUG

floppy

rpm)

rpm)

compati-

(360

rpm)

oo

oo

2,

disk

*2

drive

123

o0o0loo

o

can

o

|

o

be

configured

45|6

|

|

lol

|

|

Connector

|

oo

|

|

o

CONTROL

J

in

several

7|8

|
|

|

|

PCB

o

o

|

modes

‘°‘I1’’

910

|
|

|

o

|

of

11|122

|

o

|

000

-

l—-

o

12:

13:

“0” = Position

“—” = Position

-1I10

READY

DISK

CHANGE

operation

3

|

o

|

o

|

000

—

closed

open

Note:

Position 1 through 5 of
POS.

1:

Connect

POS.

2:

Configure

POS.

3:

Configure

POS.

4:

Configure

POS.

5:

Configure

Note:

Only

one

“DRIVE

PIN

#2:

Card-Edge

Front

LED

The

front

LED

of

the

0”

and

lights

the

““J1’’

are

the

termination

the

drive

the

drive

the

drive

the

drive

positions 2 through 5 of

the

termination

Connector

when

the

DRIVE

as

‘‘DRIVE

as

“DRIVE

as

‘DRIVE

as

“DRIVE

(PJ1)-2

resistors

resistors

SELECT

designated

when

0”

when

1°’

when

2”

when

3”

when

“‘J1”’

connected.

signal

as

closed

closed

closed

closed
closed

can

selected

follows.

be

closed.

by

Above

the

short

example

plug

is

demonstrates

set to

low

level.

in

the

case

of

B-26

PC40-III

SERVICE

MANUAL

Handling

(1

Types

1.

PJı

2.

PJ2

3.

PJ3

4.

PJ4,

5.

PJ6

6.

PJ7

7.

PJ8

8.711

(2)

Removal

Be

sure

tor

(3)

Insertion

Each

Also,

1

of

(4)

Insertion

Side 0 and

control

of

Connectors
of

5

of

that

wire

can

of

connector

as

each

the

connector.

of

PCB

TRACK

connectors

:

Interface

:

Power

:

Stepping

:

Head

:

DD

motor

:

Disk-in

:

Frond

:

Short

connector

power

be

removed

connector

wire

wire

head

side 1 of

and

W/P

INDEX

00

connector

connector

motor

connectors

connector

sensor

LED

pin

switch

has a stripe

FPC

side 1 FPC

connector

connector

connector

wire

is

from

wire

should

the

head

SENSOR

SENSOR

DD

MOTOR

SENSOR

(34-pin,

connector

and

(13-pair)

turned

the

be

set

on

FPC

into

a

card-edge

track

and

index,

for

off

whenever

connector

in a proper

one

side

are

shown

connector

00

sensor

write

drive

on

position

make

in

PJS5.

type)

connector

protect

selection

inserting

the

PC

sure

Fig.

board.

as

to

insert

Make

'

sensor

or

removing

shown

sure

DISK-IN

connector

in

Fig.

so

that

to

properly

SENSOR

8

Pas

Pus

the

connector

the

striped

insert side 0 FPC

\

ze

side

wire,

is

the

STRIPE

etc.

same

Pull

into

out

the

side

as

connector

connec-

the

pin

PJ4

no.

of

B-27

PC40-III

SERVICE

MANUAL

Functions

The

following

for

FDD

(1)

TP1,
These

Amplified

TP1

For

channel

is

used

TPI

the

tracking

(2)

TP4
This

In

FM

period

(his

of

Test

eight

adjustment

TP2

(pre-amp

are

the

about

and

TP2

accurate

is

inverted

in

grounding

and

TP2

alignment,

(read

data

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B-28