Commodore Amiga A500, Amiga A2000 Technical Reference Manual
Commodore® Amiga
®
A500/A2000
Technical Reference
Manual
COPYRIGHT
This manual is copyright © 1986,1987 by Commodore-Amiga, Inc. All Rights Reserved.
This document may not, in whole or part, be copied, photocopied, reproduced,
translated or transferred to any electronic medium or machine readable form
without prior consent, in writing, from Commodore-Amiga, Inc.
Amiga is a registered trademark of Commodore-Amiga, Inc.
Commodore and CBM are registered trademarks of Commodore Electronics Limited.
Hayes is a registered trademark of Hayes Microcomputer Products, Inc.
IBM is a registered trademark of International Business Machines Corporation,
Macintosh is a trademark of Apple Computer, Inc.
DISCLAIMER
THE INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED. THE ENTIRE RISK AS TO THE ACCURACY OF THE INFORMATION HEREIN IS
ASSUMED BY YOU. COMMODORE-AMIGA DOES NOT WARRANT, GUARANTEE. OR MAKE ANY
REPRESENTATIONS REGARDING THE USE OF. OR THE RESULTS OF THE USE OF, THE
INFORMATION IN TERMS OF CORRECTNESS, ACCURACY, RELIABILITY, CURRENTNESS. OR
OTHERWISE. IN NO EVENT WILL COMMODORE-AMIGA, INC. BE LIABLE FOR DIRECT, INDIRECT,
INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM ANY DEFECT IN THE
INFORMATION EVEN IF IT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SOME
LAWS DO NOT ALLOW THE EXCLUSION OR LIMITATION OF IMPLIED WARRANTIES OR LIABILITIES
FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES. SO THE ABOVE LIMITATION OR EXCLUSION MAY
NOT APPLY.
Schematics represent current machine which is subject to change without notice.
Credits
The material for this manual was produced by Engineering. Documentation,
and Technical Support staff at Commodore West Chester, Commodore
Braunschweig, and Commodore-Amiga. Individuals contributing major portions of information and input are Dave Haynie, Jeff Porter, Phil Lindsay,
Carolyn Scheppner, Lisa Siracusa. George Robbins. Andy Finkel. Eric
Cotton, Jeff Boyer, Steve Ahlbom, Steve Beats, Dieter Preiss, Bernd
Assmann, and Torsten Burgdorf.
This manual was compiled and edited by Steve Finkel.
Manual design by Jo-Ellen Temple and Wilson Harp.
A2000/A500 Technical Reference Manual
Table of Contents
Section 1
Summary of Differences
1
Section 2 System Block Diagrams
13
Section 3
Amiga Expansion
3.1
Designing hardware for the Amiga Expansion
Architecture
17
3.2
Driver Documentation
51
3.3 Software for Amiga Expansion
55
3.4
Amiga Expansion Connectors
100 Pin
75
86 Pin
87
Video Slot
101
Section 4
PC Bridgeboard
4.1
Description of the PC/XT emulator for the Amiga 2000
109
4.2
BIOS entry points
121
4.3 Janus library
131
Section 5
Amiga Hard Disk/SCSI Controller
159
Section 6
Custom Chips
Fat Agnus Chip
187
8520 Chip
213
Section 7
Miscellaneous Hardware Information
223
7.1
Clock/calendar registers
225
7.2 Power budgets
229
7.3
A2000 PAL equations
235
7.4
B2000 Jumpers
Appendix A.
Diagrams
A-1
Backplane Example
A-1
A-2
PIC Example
A-2
A-3
A500 Exterior (86-pin expansion connector)
A-3
A-4
Amiga 2000 Expansion Board Layout
A-4
A-5 Amiga 2000 Form Factor
A-5
A-6
Amiga 2000 Video Card
A-6
A-7
86-Pin Slot Expansion Board
A-7
A-8
A2000/B2000 Keyboard Connector Pinout
A-8
A-9
Amiga 500/2000 Mouse Diagram and Pinout
A-9
Appendix B.
Schematics
A2000 Schematics
A2000-1
B2000 Schematics
B2000-1
A500 Schematics
A500-1
Section 1
Summary of Differences
KICKSTART IN ROM
This manual presents technical documentation for three different
Amiga models, comparing them to the original Amiga, referred to as
model A1000. Technical information included in this manual is relevant for the following Commodore Amiga models:
● the Amiga 500 (A500), a low-cost version of the origi-
nal Amiga computer, software-compatible with the
A1000. Unlike the A1000, the A500 has an integrated
keyboard, provision for internal memory expansion up
to 1 megabyte, new-style hardware connectors, and
Kickstart code in ROM.
Two versions of the Amiga 2000:
● the A2000 is software-compatible with the A1000 and
has internal slots, real time clock/calendar and newstyle hardware connectors.
● the B2000, the cost-reduced version of the Amiga
2000, features some different custom chips, but is
otherwise similar to the A2000.
The B2000 is still under development, and the information presented in this document is subject to change. The information included
on the B2000 is intended to aid developers in designing software
and peripherals that are applicable for both the current and
upcoming version of the Amiga 2000.
Unless differences are specifically noted, information presented for
the A2000 also holds true for the B2000. The differences between
the two Amiga 2000 models are mainly hardware differences which
will affect peripheral design, but not the way the computers function
with software. Section 2 contains system block diagrams for all
three new Amiga models.
Both the Amiga 2000 and the Amiga 500 feature version 1.2 of
Kickstart built into ROM. Kickstart 1.2 (currently version 33.180)
boots automatically when the Amiga is turned on.
1
EXTRA KEYS ON THE
KEYBOARD
RAW KEY CODES ON
THE KEYBOARD
Both the Amiga 2000 and 500 feature 94-key keyboards, as compared to the A1000's 89-key keyboard. (The European versions of
the keyboards have 96 keys.) The new keys are all located on the
numeric keypad, and include:
KEY SCAN CODE
Left parentheses ( $5A
Right parentheses ) $5B
Slash / $5C
Asterisk * $5D
Plus + $5E
In PC mode on the Amiga 2000 (using a Bridgeboard), these keys
assume typical PC functions, including Number lock (left parenthesis), Print screen (asterisk) and Scroll lock (right parenthesis).
On some keyboards, the left Amiga key has been replaced by the
Commodore key. This key performs identically in either case.
Keyboard Layout Showing Raw Key Codes
45 50 51 52 53 54 55 56 57 58 59
3F
4A
3D 3E
14 15 16 17 18 19 1A 1B42 10 11 12 13
0D 41 46 5F
5B 5C 5D
5A
05 06 07 08 09 0A 0B 0C00 01 02 03 04
67 654064 66
1F
43
1D 1E
2E 2F 5E
2A
0F 3C
4C63 28 29 2A 2B
44
20 21 22 23 24 25 26 2762
3A 61 4F 4D 4E33 34 35 36 37 38 3960 30 31 32
Figure 1.1 Key Codes
Note: On the U.S. keyboard, the keys with codes 44 and 60 are
extended to include the European keys with codes 2B and 30,
respectively. Also note that England uses the U.S. rather than
the European keyboard, but not the U.S. keymap.
See Table 1-1 at the end of this section for a table of the raw key
codes.
2
EXTERNAL SYSTEM I/O
RS232 and MIDI Port
12345678910111213
141516171819202122232425
This section describes each I/O interface in detail, and some of the
tradeoffs made with respect to A1000 compatibility.
The Amiga 2000 and Amiga 500 have differences in the serial and
parallel ports from the Amiga 1000, the main difference being
changes in the sex of each port (changing the serial to female and
the parallel to male), which allows the new Amigas to use standard
interface cables.
The RS232 connector on the A500 and A2000 is form fit and
function identical to a Commodore PC-10/20 with a few
exceptions. This is the OPPOSITE sex connector from the
A1000. The connector is a shielded male DB25P connector. The
A1000 supplies various non-standard RS232 signals on the DB25
connector. These non-standard signals were removed wherever
possible. The RS232 connector is NOT physically compatible with
some MIDI interfaces but is compatible with the Amiga
Modem/1200 RS {model 1680). Below is a comparison chart
between the RS232 standard, a Hayes Smart-modem standard, the
A1000 RS232, and the new Amiga 500/2000 RS232 connector.
PIN RS232 A1000
A500/
A2000 PC10 HAYES® DESCRIPTION
1 GND GND GND GND GND Frame
g
round
2 TxD TxD TxD TxD TxD Transmit Data
3 RxD RxD RxD RxD RxD Receive Data
4 RTS RTS RTS RTS
—Req
uest to send
5 CTS CTS CTS CTS CTS Clear to send
6 DSR DSR DSR DSR DSR Data set read
y
7 GND GND GND GND GND Signal ground
8 DCD DCD DCD DCD DCD Carrier detec
t
9—
—
+ 12v + 12v
—
+ 12 volt power
10 —
—
- 12v - 12v
—
- 12 volt power
11 —
—
A
UDO
——A
udio outpu
t
12 S.SD
———
SI Speed Indicate
13 S.CTS
———
—
14 S.TxD -5Vdc
—
—
—
- 5 volt power
15 TxC
A
UDO
—
——A
udio outpu
t
16 S.RxD
A
UDI
—
——A
udio inpu
t
17 RxC EB
—
—
—
Port clock 716KHz
18 — INT2*
A
UDI
—
—
Interrupt line/Audio inpu
t
19
S.RTS
———
—
20 DTR DTR DTR DTR DTR Data terminal read
y
21 SQD+ 5Vdc—
—
—
+ 5 volt power
22 RI
—
RI RI RI Ring indicator
23 SS + 12Vdc —
—
—
+ 12 volt power
24 TxC1 C2*
—
—
—
3.58MHz clock
25 — RESB*
—
—
—
Buffered system
3
Centronics Port
1234
5678910
11 12
13
14
15 161718 19 20
21 222324
25
Video Output
As you will notice, the A500 and 2000 deletes clocks and interrupt
lines from the A1000. The +/-5Vdc and reset lines are also deleted.
The +/- 12Vdc lines are identical to a PC10/20.
The following signals (formerly on the RS232 connector) can be
found on other connectors:
ResB = parallel connector
C2 = video connector
The Centronics port also has some non-standard signals. Below is a
table comparing the A1000 Centronics port with the A500/A2000
Centronics port. Again, this is the opposite sex from the A1000
and the same sex connector as an IBM®-PC (i.e., a female DB25
connector).
PIN A1000 A500/A2000 PC10
1 DRDY* STROBE* STROBE*
2 Data O Data O Data O
3 Data 1 Data 1 Data 1
4 Data 2 Data 2 Data 2
5 Data 3 Data 3 Data 3
6 Data 4 Data 4 Data 4
7 Data 5 Data 5 Data 5
8 Data 6 Data 6 Data 6
9 Data 7 Data 7 Data 7
10
A
CK*
A
CK*
A
CK*
11 BUSY
(
data
)
BUS
Y
BUS
Y
12 POUT(clk
)
POUT POUT
13 SEL SEL SEL
14 GND + 5v
p
ullu
p
A
UTOFDXT*
15 GND NC ERROR*
16 GND RESET* INIT*
17 GND GND SLCT IN*
18-22 GND GND GND
23 + 5v GND GND
24 NC GND GND
25 Reset* GND GND
The A500 and A2000, like the A1000, use a DB23 video connector.
This 23 pin connector contains all the signals necessary to work with
a Genlock, but the current Genlock will need to be redesigned in order to meet the physical requirements of the A500 and A2000, in
4
Mouse and Joystick
Ports
A500 Expansion Port
A500 RAM Expansion
A500 Power Supply
Connector
stead of the A1000. An A500 genlock will also have to supply its
own power. Power will not be provided for the Genlock. All signals
on the 23 pin connector are the same except for the power.
In addition to the 23 pin video connector, the A500/B2000 provides
a monochrome composite video output, unlike the A1000. This provides the capability of using a low-cost, high persistence monochrome monitor with the A500 for viewing 640 x 400 interlaced
video without as much flickering.
Power is provided for the A520 modulator and composite video
adapter.
The mouse and joystick ports of the A500 and A2000 are identical
to the A1000, except that the current limiting protection circuitry
has been eliminated. The A500 and A2000 use a different mouse
than the one the A1000 uses. A diagram and information on this
mouse is included in Appendix A of this manual.
The expansion port is electrically compatible with the A1000, but
because of its physical location, it cannot accept any A1000
expansion peripherals without some further adapter. Power is
supplied to this connector, but only enough for a ROM cartridge.
The exact pinout of this 86 pin edge connector appears later in this
document,in the section of Amiga expansion. The A500 diagram in
Appendix A shows the new positioning of this port (relative to
A1000) and the pin numbers.
Associated with the built-in 512KB of RAM is a header socket to allow an additional 512KB of RAM and a battery backed-up real time
clock board to be added. This small PCB (the A501 RAM Expansion
Cartridge) can easily be installed by the user. The clock in this unit
functions the same as that built into the A2000, which is reviewed
in Section 7-1.
The A500 power supply connector is similar to that of the C128.
The pinout of the square 5 pin DIN connector is as follows:
PIN SIGNAL
1 + 5Vdc @ 4.3A
2 Shield Ground
3 + 12Vdc@ 1.0A
4 Signal Ground
5 -12Vdc @ .1A
5
External Disk Interface
Connector
The 23 pin D-type connector with sockets (DB23S) at the rear of the
Amiga is nominally used to interface to MFM devices.
The second disk drive port is similar to the A1000, and is therefore
compatible with the 1010 or the 1020 disk drive. The CPU will
power one external 1010 disk drive.
External Disk Connector Pin Assignment
Pin Name Dir Notes
1 RDY* I/O If motor on, indicates disk
installed and up to speed.
If motor not on, Identification
mode. See below.
2 DKRD* I MFM input data to Amiga.
3GND
4GND
5GND
6GND
7GND
8 MTRXD* OC Motor on data, clocked into
drive's motor on flip flops by the
active transistion of SELxB*.
Guaranteed setup time is 1.4
μsec
Guaranteed hold time is 1.4
μsec.
9 SEL2B*/SEL3B*0C A500:Select drive 2/A2000:
Select drive 3.
10 DRESB* OC Amiga system reset. Drives
should reset their motor on flip
flops and set their write protect
flip flops.
11 CHNG* I/0 Note: Nominally used as an open
collector input. Drive's change
flop is set at power-up or when
no disk is installed. Flop is reset
when drive is selected and the
head stepped, but only if a disk is
installed.
12 5V 270 ma maximum; 410 ma
surge.
When below 3.75V, drives are
required to reset their motor on
flops, and set their write protect
on flops.
13 SIDEB* 0 Side 1 if active, side 0 if inactive.
14 WPR0* I/O Asserted by selected, write
protected disk.
6
15 TKO* I/0 Asserted by selected drive
when read/write head is
positioned over track 0.
16 DKWEB* OC Write gate (enable) to drive.
17 DKWDB* OC MFM output data from
Amiga.
18 STEPB* OC Selected drive steps one
cylinder in the direction
indicated by DIRB.
19 DIRB OC Direction to step the head.
Inactive to step towards
center of disk (higher
numbered tracks).
20 SEL3B*/
Not Used
OC A500: Select drive 3/A2000:
Not used.
21 SEL1B/SEL2B OC A500: Select drive 1/A2000:
Select drive 2.
22 INDEX* I/O Index is pulse generated once
per disk revolution, between
the end and beginning of
cylinders. The 8520 can be
programmed to conditionally
generate a level 6 interrupt to
the 68000 whenever the
INDEX* input goes active.
23 + 12V 160 ma maximum; 540 ma
surge.
Note: * in signal name denotes active low signal.
External Disk Connector Identification Mode
An identification mode is provided for reading a 32 bit serial identification data stream from an external device. To initialize this mode,
the motor must be turned on then off. See pin 8, MTRXD* for a
discussion of how to turn the motor on and off. The transition from
motor on to motor off reinitializes the serial shift register.
After initialization, the SELxB* signal should be left in the inactive
state.
Now enter a loop where SELxB* is driven active, read serial input
data on RDY* (pin 1), and drive SELxB* inactive. Repeat this loop a
total of 32 times to read in 32 bits of data. The most significant bit
is received first.
7
Full Bus Termination
Internal RAM
Expansion on the A500
EIA Ring Indicate
Support
External Disk Connector Defined Identifications
$0000 0000 - no drive present
$FFFF FFFF - Amiga standard 3.25 diskette
$5555 5555 - 48 TPI double density double sided
As with other peripheral ID's, users should contact Commodore Technical Support for ID
Assignment.
The serial input data is active low and must therefore be inverted to be consistent with the above
table.
External Disk Connector Limitations
1. The total cable length including daisy chaining
must not exceed 1 meter.
2. A maximum of 3 external devices may reside
on this interface (2 for the A2000).
3. Each device must provide a 1000 Ohm pullup
resistor on every open collector input.
Unlike the A1000 and the A500, both versions of the Amiga 2000
have an internal expansion bus, as a function of having an internal
card cage.
On the A500, memory at $C00000 is "slow" RAM (the processor is
locked out by the custom chips) rather than fast RAM as suggested
by A1000 external expansion. Thus, when ExecBase is transferred
to $C00000 to free up chip RAM, there is no speed advantage.
However, you would still be making real chip RAM available for
other purposes. The B2000 functions as the A500 does in this
regard.
The A500. A2000 and B2000 support the RS232 RI lead to allow
operation with modem standards. When the RI signal is asserted,
the parallel port SEL line will be driven low. If this function is not
desired, the RI lead should be disconnected in the modem cable.
8
Time of Day Clock
Light Pen
Monochrome
Composite Video
Audio Filter Cut-out
A500 Reset
A2000 Expansion Bus
IPL Lines
In the A500. the Time of Day clock is tied to the VSYNC signal
rather than the power line. This results in the theoretical error of
several minutes a day. For more precise timing, use the optional
real-time clock.
In genlock mode, the genlock peripheral provides a 30 Hz V/Z
signal, which results in the clock running half speed.
The light pen input on the A500 and B2000 has been moved to the
second mouse port to allow use without a pass-thru mouse adapter.
On a B2000. the light pen can be jumpered to port 0.
The A500 and B2000 provide a full-bandwidth 16-level grey-scale
composite video output. Color composite is available with an
optional A520 composite color/rf video adapter.
The A500 and B2000 can cut out the anti-aliasing filter by programmatically turning off the "power on" LED. External bandwidth limiting to below 15 KHz will be required for most applications. This
permits wider frequency response by using faster sampling rates.
The A500 implements a "hard-wired" Control/Commodore/Amiga
key reset rather than the "soft" A1000/A2000 keyboard reset.
"Shut down" keyboard messages are not transmitted.
The A2000 does not run the processor IPL lines beyond the 86 pin
MMU connector. Instead, additional interrupt request lines are allocated for future expansion devices. These lines are not supported by
the current software.
9
Table 1 -1 RAW KEY CODES
Raw Key
Number Keycap Legend
Unshifted
Default
Value
Shifted
Default
Value
00 ‘ ~ ' (Accent grave) ~ (tilde)
01 1 ! 1 !
02 2 @ 2 @
03 3 # 3 #
04 4 $ 4 $
05 5 % 5 %
06 6 ^ 6 ^
07 7& 7 &
08 8* 8 *
09 9 ( 9 (
OA 0 ) 0 )
OB - _ - (Hyphen) _ (Underscore)
OC = + = +
OD \ │ \ │
OE (undefined)
OF 0 0 0 (Numeric pad)
10 Q q Q
11 W w W
12 E e E
13 R r R
14 T t T
15 Y y Y
16 U u U
17 I i I
18 O o O
19 P p P
1A [ { [ {
1B ] } ] }
1C (undefined)
1D 1 1 1 (Numeric pad)
1E 2 2 2 (Numeric pad)
1F 3 3 3 (Numeric pad)
20 A a A
21 S s S
22 D d D
23 F f F
24 G g G
25 H h H
26 J j J
27 K k K
28 L 1 L
29 ; :
2A ‘ ” ' (single quote) "
10
Raw
Key
Number
Keycap
Legend
Unshifted
Default
Value
Shifted
Default
Value
2B (RESERVED) (RESERVED)
2C (undefined)
2D 4 4 4 (Numeric pad)
2E 5 5 5 (Numeric pad)
2F 6 6 6 (Numeric pad)
30 (RESERVED) (RESERVED)
31 Z z Z
32 X X X
33 C c C
34 V V V
35 B b B
36 N n N
37 M m M
38 , < , (comma) <
39 . > . (period) >
3A /? / ?
3B (undefined)
3C . (Numeric pad)
3D 7 7 7 (Numeric pad)
3E 8 8 8 (Numeric pad)
3F 9 9 9 (Numeric pad)
40 (Space bar) 20 20
41 BACK SPACE 08 08
42 TAB 09 09
43 ENTER OD OD (Numeric pad)
44 RETURN OD OD
45 ESC 1B 1B
46 DEL 7F 7F
47 (undefined)
48 (undefined)
49 (undefined)
4A - - - (Numeric Pad)
4B (undefined)
4C Up Arrow <CSI>A <CS!>T
4D Down Arrow <CSI>B <CSI>S
4E Forward Arrow <CSI>C <CSI> A
1
4F Backward Arrow <CS1>D <CSI> @
1
In shifted Forward Arrow and Backward Arrow, note blank space after <CSI>.
<CSI> stands for Command Sequence Initiator.
11
Raw
Key
Number
Keycap
Legend
Unshifted
Default
Value
Shifted
Default
Value
50 F1 <CSI>0~ <CSI>10~
51 F2 <CSI>1~ <CSI>11~
52 F3 <CSI>2~ <CSI>12~
53 F4 <CSI>3~ <CSI>13~
54 F5 <CSI>4~ <CSI>14~
55 F6 <CSI>5~ <CSI>15~
56 F7 <CSI>6~ <CSI>16~
57 F8 <CSI>7~ <CSI>17~
58 F9 <CSI>8~ <CSI>18~
59 F10 <CSI>9~ <CSI>19~
5A ( ( (
5B ) ) )
5C / / /
5D * * *
5E + + +
5F HELP <CSI>?~ <CSI>?~
12
Section 2
System Block Diagrams
INTRODUCTION
This section features system block diagrams for each new Amiga,
the A2000, B2000 and A500, in that order.
13
62 pin PC - Connector
PA U L A
62 pin PC - Connector
PC
PRINTER FLO PPY
ext. int.
RS 232
AUDIO
MOUSE
JO Y -ST IC K
VIDEO
- RG B
BATTERY
REAL
TIM E
CLOCK
PARALLEL
PO R T
FLO PPY
PO R T
SERIAL INTERFACE
MOUSE INTERFACE
JOY - STICK INTERFACE
STEREO AUDIO INTERFACE
WITH 4 D/A CONVERTER
AT
36 pin Conn.
36 pin Conn.
AD
AC
AA
AD
AC
AA
100 pin AMIGA - Connector
100 pin AMIGA - Connector
D
DATA
BU FFE R
CONTROL
BU FFE R
ADDRESS
BU FFE R
C
A
86 pin MMU - Connector
D
D
C
C
A
A
A
A
A
D
D
D
D
D
C P U
6 8 0 0 0
A<1:23>
DATA
BU FFE R
ADDRESS
BU FFE R
ADDRESS
MUX
KICK
STA R T
ROM
ADDRESS
MUX
BLITTER
AGNUS
BIT D M A
CO NTRO LLER
GRAPHIC
CO NTRO LLER
512K 8 BIT∗
CHIP - RAM
DRAM
A M I G A
2 0 0 0
IA
ID
ID<0:15>
ID
IA
IA<1:8>
IA
ID
IA
ID
ID
D E N I S E
VIDEO CONTROLLER
VIDEO MOD.
14
62 pin PC - Connector
PA U L A
PC
PRIN TER
FLO PPY CO NTROL
RS 232
DATA
AUDIO
PO TS
CO M PO SITE/
M ONOCHROM E
VIDEO
- RG B
BATTERY
REAL
TIM E
CLOCK
PARALLEL
PO R T
FLO PPY
PO R T
SERIAL INTERFACE
MOUSE INTERFACE
JOY - STICK INTERFACE
STEREO AUDIO INTERFACE
WITH 4 D/A CONVERTER
AT
36 pin Conn.
AD
AC
AA
AD
AC
AA
100 pin AMIGA - Connector
100 pin AMIGA - Connector
D
DATA
BU FFE R
CONTROL
BU FFE R
ADDRESS
BU FFE R
C
A
86 pin MMU - Connector
D
D
C
C
A
A
A
D
D
D
D
D
C P U
68000
A<1:23>
DATA
BU FFE R
KICK
STA R T
ROM
BLITTER
FAT
AGNUS
BIT DMA
CONTROLLER
GRAPHIC
CONTROLLER
CHIP RAM
512K 8 BIT∗
DRAM
B 2000
ID
ID<0:15>
ID
IA
IA<1:8>
IA
ID
IA
ID
D E N I S E
VIDEO CONTROLLER
VIDEO MOD.
62 pin PC - Connector
36 pin Conn.
BUS CONTROL
&
ARBITRATION
BUSTER
BUFFER
CONTROL
KEYBOARD
RS 232
CONTROL
FLO PPY
DATA
MOUSE
Video
Hybrid
Video 1
36
PIN
36
PIN
Video 2
RA
ID
NONCHIP RAM
512K 8 BIT∗
DRAM
15
68000
CPU
AS
R/W
DTACK
Clocks
GARY
Full 68000
Bus
REAL
TIME
CLO CK
EXPANSION POR T
(Up to 8M Bytes)
28 Mhz
Clock
8520 CHIPS (2)
KEYBOARD
AS
R/W
Clocks
Control
DBR
FAT
AGNUS
Address Bus
Bi Directional
Tri State Latch
ROM
Data Bus
(16)
DRAM
512K Std.
1MB optional
Data Bus (16)
Multiplexed
Addresses
(9)
RAS0 1
CAS0 1
R/W
DMA Request
(DMAL)
DENISE
PAULA
RGA Register Address (8)
Printer Port
Disk Control
RS232 Control
VIDEO HYBRI
D
Mouse
Ports (2)
Video
RGB
Composite
Video
Disk
UART
Audio
Pot Port
A 500 BLOCK DIAGRAM
16
Section 3.1
Designing Hardware for the Amiga Expansion
Architecture
INTRODUCTION
This section gives guidelines for designing hardware to reside on the
Amiga expansion bus. The Amiga expansion bus is a relatively
straightforward extension of the 68000 bus.
Hardware for the bus can be viewed as two categories: backplanes
and PICs. Backplanes interface to the 86 pin connector of either
another backplane or the Amiga itself. Backplanes buffer the bus
and provide 100 pin connectors for PICs to plug into.
PIC is an acronym for plug-in card. A PIC is usually a card that plugs
into the standard 100 pin Amiga connectors.
A sub-type of PIC is a combination of backplane and PIC integrated
into one package. These combination products should follow all of
the applicable backplane and PIC rules, especially auto-configuration.
Software never sees backplanes; all expansion hardware appears to
the software as PICs.
WARNING
These specifications represent "worst case" design targets.
Products that do not comply with these specifications can be expected to fail on worst case production units.
Following conservative design practices and allowing the widest
safety margins is your best assurance against problems in the
field.
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EXPANSION
ARCHITECTURE
OVERVIEW
As shown in Figure 3.1, "Expansion Architecture Overview," the expansion bus is implemented as backplane (an expansion box) which
accept PICs (boards). The recommended number of PICs to a backplane is five.
Due to timing considerations, it is not possible to daisy-chain more
than two buffered backplanes without inserting wait states.
NOTE
You should also take extreme care in controlling signal
radiation from your product, in order to pass FCC class B
regulations.
DOWNSTREAM BACKPLANE
PIC PIC PIC
S
L
A
V
E
O
W
N
B
U
F
F
E
R
S
A
M
I
G
A
COLLISION
BUS STEERING and ENABLE
BUS ARBITRATION
UPSTREAM BACKPLANE
PIC
PIC
PIC
DATA
COLLISION
BUS STEERING and ENABLE
BUS ARBITRATION
ADDRESS
SLAVE*
DMA*
Figure 3.1. Expansion Architecture Overview
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GLOSSARY
Active Active high signals are considered active when they are in
the "one state" or "high state". Active low signals are considered active when they are "low" or in the “zero state”. Active high signals
do not have barred signal names. Active low signals do have barred
signal names. Active means that the signal is
1. is true (non-barred) and is currently in the one state, or
2. is a barred signal name and is currently in the zero state.
An example is AS* (the * = bar). AS* is active when it is equal to
zero. A counter example is the signal AS (the inverse of AS*), which
is active when it is in the one state.
Auto Configuration The protocol (specified in this section) that
Amiga uses to configure expansion cards into the system.
Downstream Downstream means closer to the Amiga. For instance, if two backplanes are daisy chained on the bus, the closer-in
backplane is downstream from the further-out backplane. The concepts of upstream and downstream are important in determining
which direction the address and data drivers should drive.
Master A PIC which is capable of initiating DMA cycles on the bus.
PIC A PIC is a plug-in card or a product which behaves in the system
as a plug-in card. That is, it provides a resource that resides on the
expansion bus, and follows the rules for auto-config, master protocol, slave protocol, etc.
Slave A slave is a PIC that can only respond to bus cycles. A slave
cannot initiate bus cycles: in other words, it does not drive the address lines on the backplane, nor AS*, UDS*, LDS*.
Upstream Upstream means further away from the processor. For
instance, all PICs are upstream from the buffers on the backplane
that they are plugged into because the buffers are between the PIC
and the Amiga.
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DESIGN GUIDELINES
FOR BACKPLANES
Collision Detection
Circuit
Bus Arbitration Logic
In this context, collisions are defined as any instance of two slaves
attempting to respond to the same bus cycle.
All backplanes must have a collision detect circuit. The reason is that
the PICs are auto-configurable and can be accidently instructed by
software to respond to overlapping address spaces. Without collision
detection, erroneous software can damage the hardware by causing
bus contention.
Collision detect works in the following way: As soon as a PIC knows
that it has been selected as the slave for this bus cycle, it asserts
SLAVE* low and holds SLAVE* low until the end of the bus cycle
(AS* going high).
The collision detect circuit (usually part of a PAL) detects whether
more than one slave is responding and, if so, asserts BERR*. All data
drivers on the expansion bus must be designed to enter high impedance mode whenever BERR* is active. Because data drivers are not
turned on until S4 (ASDELAYED* active), BERR* will have disabled
the drivers before the contention can begin.
Note that in order to detect all cases of multiple slave response, the
circuit must watch A23-A19 for Amiga address spaces and also
watch SLAVEIN* from the next box out. See discussion of the example schematic for specific PAL equations that implement collision
detect.
Because BERR* is listened to by all PICs, it will in some systems be
heavily loaded, so it should be driven with a hefty open collector or
tri-state driver. Each backplane should provide a 1000-ohm pull-up
resistor on BERR*.
The bus arbitration logic is based on the 68000 BR*. BG*. BGACK*
protocol as described in the 68000 manual. In order to avoid metastable states in the backplane latches, all changes in state of the BR*
lines from the PICs must be clocked by the rising edge of 7M.
The example design gives our current recommended bus arbitration
logic. Refer to the ARBITRATE PAL equation in Table 3-3.
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Buffer Control Logic
Data Driver Timing
Clock Buffers, 7M, and
ASDELAYED*
THE PROTOCOLS
Read or Write Cycle
With Amiga as Master
The buffer control logic controls output enable and direction of the
bidirectional tri-state bus drivers. See the STEERING PAL equation.
Table 3-2.
It should be noted that the backplane drivers must not turn on until
the rise of S4 during a read. This is okay because data from the
Amiga internal RAMs is not valid during S4 anyway, so nothing is to
be gained by turning the data buffers on earlier.
There are three clocks coming from the Amiga. These are CDAC,
C1*, and C3*. The backplane must generate 7M (equivalent to the
Processor clock) by the following equation: 7M = C1 * XNOR C3*.
The bus protocols are basically the same as standard 68000 protocols; however, the timing margins are tighter due to the potentially
long paths of Amiga and PICs talking to each other across two buffered backplanes.
One unusual feature is that when you are doing a DMA transfer into
or out of the Amiga display RAM (the half megabyte starting at
address 000000). the DTACK* circuit will synch the master up with
C1. Because C1 is twice as slow as 7M. there are two possible phase
relationships between C1 and the beginning of the DMA bus cycle. If
AS* is asserted during the last quartile of C1 (C1 low and C3 low.
see Fig. 3.2. System clock timing diagram), we call this an "in sync"
bus cycle, and DTACK* is given in time to do a normal 4-clock (7M)
bus cycle. (Note: Occasionally, DTACK* is delayed due to contention
with the graphics chips, but that does not matter in this discussion.)
However, DTACK works differently if the DMA controller asserts
AS* in the other phase. In the second quartile (C1 high and C3
high), the DTACK* circuit holds off DTACK* long enough to insert
one wait state, thus synching up the "out of sync" bus cycle.
Since the Amiga bus master is a 68000. the bus cycle is a 68000
cycle. However, the responding slave does not pull DTACK*. Our internal circuitry pulls DTACK* unless the slave pulls XRDY low.
Also, the slave (PIC) must pull its SLAVE* output low as soon as it is
selected, and at the end of the cycle, disassert SLAVE* when AS*
goes away.
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Read or Write Cycle
with a PIC as Master
Bus Arbitration
SYSTEM LEVEL
ORGANIZATION (AND
IDIOSYNCRASIES)
Address Override(OVR*)
INTERRUPTS
A PIC as master must drive the bus using the same protocol as the
68000. Some of the timing margins must be better than those from
the 68000, because the PIC is driving through several levels of buffers, and the Amiga logic is designed to the 68000 (8 megahertz
part) specs. Specific timing requirements can be found in the tables
later in this section.
The bus arbitration scheme is based on the 68000 BR*.BG*.BGACK*
protocol. PICs are required to assert BR* clocked by the rising edge
of 7M. This makes it less expensive to design bus arbitration logic
that will be reliable. Specifically, synchronous arbitration logic can be
clocked on 7M without danger of going metastable.
Pin 17 OVR* can only be used in between address $200000 and
A0000, and implies you have to supply your own DTACK*. OVR* is
not supported for the purpose of disabling system decoding in the
C00000 to DFFFFF range. Worst case 68000 timing requires modifications to the system decode gate array to accomplish this reliably.
Other uses of OVR* are not supported.
USE INT2* OR INT6* (DON'T
PULL IPL0*-IPL2*)
There are two interrupt input lines on the
Amiga: INT2* and INT6*. INT2* = pin
19, INT6* = pin 22. these lines assert
levels 2 and 6 to the processor.
Do not assert the IPL0* thru IPL2* lines,
because they are already driven by internal
logic.
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INTERRUPT LATENCY--
-BLITTER, MASKED INTS
Interrupt latency on the Amiga is highly
application software dependent, this is
because the Blitter can be operated in
"nasty mode" at the software's option.
If the blitter is "nasty" and is given a lot
of work to do. the processor receives
very few memory cycles, so the
interrupt latency will suffer.
The software can also mask out
interrupts using on-board interrupt
control logic.
VPA Is Not
Recommended
Do Not Use Pins
Marked EXP
TIMING GENERAL
DISCUSSION
We recommend that you design your peripherals to run asynchronously on the 68000 bus, that is, a slow peripheral should be memory mapped and use pulling XRDY low as a means of making the
68000 run a slower cycle. The use of XRDY to delay DTACK is discussed elsewhere in this document
We do not recommend using VPA. If you decide to use VPA, you
must pull OVR* low 30ns before asserting VPA* low. Pulling OVR*
low will tri-state VPA* in the current design PAL, thus allowing your
logic to drive VPA*. Pulling OVR* will also prevent DTACK* from
being asserted by the PAL. However, this will not disable the onboard 8520 CIA chips.
If your slave uses the VPA VMA protocol to be synchronous with the
68000's E clock, you must only use addresses in which A12 and
A13 are high. This is because we have synchronous ports on board
which are activated by (A12* AND VMA), also (A13* AND VMA).
Do not drive or load pins marked EXP or RESERVE.
Timing specifications are listed in Table 3-1.
There are two main problems to be dealt with in the expansion
architecture timing: propagation delays and skews in the clock,
address, data, and control paths. The timing is tight; thus, we
recommend using FAST and AS parts to buffer these lines. To
guarantee meeting the timing requirements, you must be careful to
not exceed the recommended operating conditions of the parts you
chose, for example the capacitive loading. In calculating your
loading, note that all PICs are specified to present no more than two
"F" loads plus minimal trace capacitance to each connector pin.
Backplanes are specified to present no more than one "F" load plus
trace capacitance to the Amiga. Do not use "typical" numbers;
reliable systems can be built by using "worst case" numbers.
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Expansion Notes
1) The loading, buffering and layout requirements specified for the
A1000/A500 expansion connector must be strictly followed for
reliable operation. Unbuffered devices and bus line extension are
known problem areas.
2) Unbuffered daisy-chaining of multiple external expansion devices
is not supported.
3) The A500 provides only nominal amounts of power for expansion devices. All devices having significant power requirements
are expected to be self-powered and should not make connec
tions to the power pins on the expansion connector.
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DESIGN GUIDELINES
FOR PICs
Auto Configuration
General Description of
Auto Configuration
All PICs implement the auto-configuration protocol. The auto config
protocol is designed so that system auto-config software can interrogate the PICs ID locations, build a system table of the installed
PICs, and place the PICs in the 68000 memory space.
If it is difficult to imagine how to implement this protocol while it's
being described, don't worry. The design requires one PAL, one
latch, and one address match circuit. Complete details are given in
the example design.
Upon reset, all PICs come up in the unconfigured state. In the unconfigured state, the PIC responds to the 64 kilobyte address space
starting at location E80000, if CONFIGIN* is active to the PIC. If
CONFIGIN* is not active, the PIC does not respond to any bus cycles.
The processor comes out and reads nibbles of ID data on D15-D12
from the PIC. The table of ID data and the locations of control
latches is detailed later in this section. This data includes such things
as size of address space required, manufacturer's product number,
and whether to add the PIC to the free memory pool (if it is a
memory PIC.)
Under normal conditions, the processor determines how much address space the PIC requires and then loads the PICs address latch
with an appropriate base address. This permanently relocates the
PIC at its new address (until Reset), and passes CONFIGOUT* out to
the next PIC's CONFIGIN*, whereupon the process is enacted again
until all PICs are configured.
The smallest unit of memory that a PIC can ask for is 64 kilobytes.
The largest is eight megabytes. All PICs should be designed to be
based on boundaries that match their space requirements; for example, one megabyte PICs should be designed to reside on one megabyte boundaries (match circuit matches A23-A20). There are two exceptions to this rule, however. Four megabyte PICs must be capable
of being placed on four megabyte boundaries, as well as at hex
200000 and at hex 600000. Eight megabyte PICs should be capable
of being placed on eight meg boundaries and at hex 200000. This
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requirement is because the eight megabyte space reserved for expansion in the current machine begins at hex 200000 (See auto-config notes below).
Auto-Config Notes
1)There is currently no provision for 6MB PICs. Designers of 8 MB
memory boards should consider auto-configs as two PICs to al
low partial loading flexibility.
2)PIC size/alignment rules are subject to change. If so, bit(s) will be
defined to allow a PIC to specify that it is more flexible than the
old rules require.
3)The address map is subject to change. A PIC should assume that
it may be placed anywhere in the address space.
All expansion devices are strongly encouraged to use the autoconfig protocols. Assignment of fixed I/O addresses is subject to
negotiation.
Address Specification Table
All nibbles except 00, 02, 40 and 42 should be inverted.
Descriptions:
765
4
32 1 0
(00/02)
Memory size
000 = 8 megabytes
001 = 64 kilobytes
010 = 128 kilobytes
011 = 256 kilobytes
100 = 512 kilobytes
101 = 1 megabyte
110 = 2 megabytes
111 = 4 megabytes
B
oard type and size
Chained config request, indicates that the next
auto-config device in the daisy chain is physically
tied to this device.
Optional ROM vector valid
Link into memory free list
Board type
00 = Reserved
01 = Reserved
10 = Reserved
11 = Current style board
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(04/06) 7 6 5 4 3 2 1 0 Product number, this number is defined by the
manufacturer of the board and is used by autoconfig software to initialize drivers for the
board.
(08/OA)
7654 3210
Reserved, must be as specified
Bits are currently zero
0 means this board can be shut up
1 means this board cannot be shut up
0 means any space okay
1 means preference to be put in the 8 Meg
space
(0C/0E) 7 6 5 4 3 2 1 0 Reserved, must be 0
(10/12)
(14/16)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Mfg # high byte
Mfg # low byte; These 2 bytes are assigned by
CBM. They are used by the auto-config software
to initialize drivers for boards.
(18/1A)
(1C/1E)
(20/22)
(24/26)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional serial number, byte 0 (msb)
Optional serial number, byte 1
Optional serial number, byte 2
Optional serial number, byte 3 (lsb)
(28/2A)
(2C/2E)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional ROM vector high byte
Optional ROM vector low byte. If the 'ROM addr
valid' bit (4 of nibble 0) is set. then these 2
bytes are the offset from the board's base address at which the start of the ROM code information is located (e.g., the hard disk driver). If
the bit it not set, then these 2 bytes have no
meaning.
(30/32)
(34/36)
(38/3A)
(3C/3E)
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Reserved, read must be 0; write resets base
address register
Reserved, must be 0
Reserved, must be 0
Reserved, must be 0
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