Page 1
r
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SYSTEM SCHEMATICS
A2060/A2065/A2232
AUGUST, 1990
PN-314042-01
Commodore
Page 2
Produced By:
Commodore International Spare Parts GmbH
Braunschweig, West Germany
SYSTEM SCHEMATICS
A2060/A2065/A2232
AUGUST, 1990 PN-314042-01
INTERNATIONAL EDITION
COMMODORE “INTERNATIONAL EDITION” SERVICE MANUALS CON
TAIN PART NUMBER INFORMATION WHICH MAY VARY ACCORDING TO
COUNTRY. SOME PARTS MAY NOT BE AVAILABLE IN ALL COUNTRIES.
Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no express or implied warranties with
regard to the information contained herein. The infor
mation is made available solely on an as is basis, and the
entire risk as to completeness, reliability, and accuracy
is with the user. Commodore shall not be liable for any
damages in connection with the use of the information
contained herein. The listing of any available replacement
part herein does not constitute in any case a recommenda
tion, warranty or guaranty as to quality or suitability of
such replacement part. Reproduction or use without ex
press permission, of editorial or pictorial content, in any
matter is prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical, photo
copying, recording or otherwise, without the prior written permission
of Commodore Electronics Limited.
Copyright © 1990 by Commodore Electronics Limited.
All rights reserved. Printed in U.S.A.
Page 3
TABLE OF CONTENTS
• SPECIFICATIONS
• PARTS LISTS
• SCHEMATICS
^ o n ^ ^ ^
Page 4
A2060 SYSTEM SCHEMATICS
A2060 — ARCNET CONTROLLER FOR A2000
DIMENSIONS:
WEIGHT:
ENVIRONMENTAL:
POWER REQUIREMENTS:
INCLUDES:
FEATURES:
ARCNET HAS THE FOLLOWING FEATURES:
GENERAL DESCRIPTION
The A2060 is an ARCNET controller designed for use with the A2000 computer. ARCNET is a local area network
utilizing a self-polling “modified token passing” scheme operating at a 2.5 Mbit data rate. A “modified token passing”
scheme is one in which all token passes are acknowledged by the node accepting the token. The token passing network
avoids the fluctuating channel access times caused by data collisions in so-called CSMA/CD schemes such as Ethernet.
The A2060 plugs into one of the 100 pin expansion slots in the A2000. The BNC plug on the rear of the A2060 connects
to the network in daisy chain fashion with the special “T” connector and BNC to BNC cable included. Note that most
network installations will require additional cabling and active links, and that network software is not included.
13.25 x 4.5 inches
1 lb.
OC to 70C Operating
+ 5V @ 1.75A max
- 5V @ 0.27A max
• A2060 PCB
• BNC “T” connector
• BNC to BNC cable (2 meter)
• 93 ohm network terminator
• Support of ArcNet bus protocol (uses HIT module)
• Socket for optional network Autoboot ROM
• Novelle netware software optionally available
• Allows up to 256 nodes
• Maximum distance of 2000 feet between nodes
• Data rate of 2.5 Mbps
ENVIRONMENTAL TEST REQUIREMENTS
Units shall comply with the following environmental resistance requirements.
TEMPERATURE
Operational
Storage
Gradient
Temperature Cycle
HUMIDITY
Operational (relative)
Storage (relative)
VIBRATION
Non-operating (randomfrequency) 5.2 Gs per MIL-STD 202 Method 214, 15 min. in each of three axes
SHOCK
Operational 5 Gs to each of 6 axes, two 11 mSec half sinewave shocks
Non-Operational 20 Gs applied as above
ALTITUDE
Operational
Non-Operational
5 to 55°C
-2 0 to + 70 °C
+ 10°C/hour
-2 0 to 60° C, 10 cycles, 10 minutes minimum at each extreme,
5 minutes maximum between extremes
10 to 90% (non-condensing)
5 to 95% (non-condensing)
0 to 3000 meters
0 to 15,000 meters
1-1
Page 5
A2060 SYSTEM SCHEMATICS
Commodore International Spare Parts List
SHIPPING ASSEMBLIES
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries.
532060-01
363035-05 BOX BULK PACKING 363035-05 BOX BULK PACKING
363097-05 BOX PACKING 363097-05 BOX PACKING
318928-01
363350-01
318290-01 CARD WARRANTY U.S.
314877-04 SERVICE CENTER LIST (U.S.) 390627-01 CONNECTOR BNC “T"
316846-01 LABEL UPC A2060
390627-01
390628-01
312839-01
311661-01
251006-01
A2060 SHIPPING ASSY (U.S.)
BAG PLASTIC CONDUCTIVE 318928-01
MANUAL USER A2060 (EFIGS)
CONNECTOR BNC “T”
TERMINATOR BNC 93 OHMS 311661-01 PCB ASSY A2060, REV. 2
CABLE BNC 2 M LG. 251006-01
PCB ASSY A2060, REV. 2
BAG PLASTIC
532060-02 A2060 SHIPPING ASSY (CANADA)
363035-05
363097-05 BOX PACKING
318928-01
363350-01
318882-01
316846-01 LABEL UPC A2060
390627-01
390628-01 TERMINATOR BNC 93 OHMS 251006-01 BAG PLASTIC
312839-01
311661-01
251006-01
532060-03
363035-05 BOX BULK PACKING 363351-01
363097-05 BOX PACKING
318928-01 BAG PLASTIC CONDUCTIVE
363350-01 MANUAL USER A2060 (EFIGS) 390628-01 TERMINATOR BNC 93 OHMS
318884-01
316846-01 LABEL UPC A2060
390627-01 CONNECTOR BNC “T” 251006-01 BAG PLASTIC
390628-01 TERMINATOR BNC 93 OHMS
312839-01 CABLE BNC 2 M LG.
311661-01
251006-01 BAG PLASTIC
BOX BULK PACKING
BAG PLASTIC CONDUCTIVE
MANUAL USER A2060 (EFIGS) 390627-01 CONNECTOR BNC “T”
CARD WARRANTY CANADA 390628-01 TERMINATOR BNC 93 OHMS
CONNECTOR BNC “T ”
CABLE BNC 2 M LG.
PCB ASSY A2060, REV. 2
BAG PLASTIC
A2060 SHIPPING ASSY (AUSTRALIA)
CARD WARRANTY AUSTRALIA 312839-01 CABLE BNC 2 M LG.
PCB ASSY A2060, REV. 2
532060-04
363350-01 MANUAL USER A2060 (EFIGS)
316846-01
390628-01 TERMINATOR BNC 93 OHMS
312839-01 CABLE BNC 2 M LG.
532060-05 A2060 SHIPPING ASSY (EUROPE)
363035-05
363097-05
318928-01 BAG PLASTIC CONDUCTIVE
363350-01
316846-01 LABEL UPC A2060
312839-01 CABLE BNC 2 M LG.
311661-01 PCB ASSY A2060, REV. 2
532060-06
363035-05
363097-05
318928-01
316846-01 LABEL UPC A2060
390627-01
311661-01 PCB ASSY A2060, REV. 2
A2060 SHIPPING ASSY (GERMANY)
BAG PLASTIC CONDUCTIVE
LABEL UPC A2060
BAG PLASTIC
BOX BULK PACKING
BOX PACKING
MANUAL USER A2060 (EFIGS)
A2060 SHIPPING ASSY (SCANDINAVIAN)
BOX BULK PACKING
BOX PACKING
BAG PLASTIC CONDUCTIVE
MANUAL USER A2060 (SCAND)
CONNECTOR BNC “T”
1-2
Page 6
A2060 SYSTEM SCHEMATICS
Commodore International Spare Parts List
PCB Components
PCB Assembly #311611-01
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries.
IC COMPONENTS
390554-01
390553-01
390585-01
901521-13
901521-29 74LS373
901521-31
901521-34 74LS175
901521-46
901521-71 74LS166
318041-01 74F521
390081-01
390198-01 74F86
390586-01 74F38
390575-01
390576-01
390577-01
251637-03
901521-43
325566-21
16L8A PAL CONTROL 1
20L10A PAL CONTROL 2
27C64-20 EPROM
74LS244
74LS32
74LS245 U23
74F74 U9.U10
LSI LAN COM90C26
LSI LAN TRANSCEIVER C0M92C3
HYB9068 HIT HYBRID MODULE
MEM SRAM 2K X 8 BIT 120NS U19
74LS374
OSCILLATOR 20MHZ 50MA U21
U6
U3
U1
U4,U7,U24,U25
U11.U15
U18
U5
U26
U17
U14
U13
U20
U27
U22
U16
SOCKETS
390060-01
904150-02
904150-04 IC L/P 24 PIN .6" U19
904150-05 IC L/P 28 PIN .6" U1
904150-06
904150-08
DIP 24 PIN .3" U3
IC L/P 16 PIN .3"
IC L/P 40 PIN .6" U20
IC L/P 20 PIN .3" U6
U27
RESISTOR NETWORKS
902441-22
902410-10
902410-07
SIP 1K 6 PIN 2% RN1.RN2
SIP 1K 10 PIN
SIP 10K 10 PIN RN4
RN3
RESISTORS
901550-105
901600-51 CF 5.6K 1/2W 5% R1.R2
901550-49 100 OHM 1/4W 5%
900101-51
CF 33 OHM 1/4W 5%
2.2 UF ELEC RAD
R3-R9
R10
C103
CAPACITORS
390082-04 CERM RAD .33UF 50 V C1-C26
900101-17 ELEC AXL 22 UF 35 V
390101-09
2.2UF ELEC, RAD C103
C28-C31
CONNECTOR
390673-01 | CONNECTOR INSULATED BNC |
|j i
MISCELLANEOUS
390363-02
311665-01 OPTION CARD BRACKET
906800-07
902707-01 TRANSISTOR 2N3906 Q1
903326-03 HEADER, 3 PIN SIL
316893-01
SWITCH 8 POSITION DIP R/A SW1
SCREW M3 X .5 X 4 (QTY 2)
FOR OPTION CARD BRACKET
CN3
LABEL, FCC ID
1-3
Page 7
PCB BOARD LAYOUT 0311661, REV. 2
A2060 SYSTEM SCHEMATh
Page 8
Schematic #311662, Rev. 2
Sheet 1 of 1
A2060 SYSTEM SCHEMATICS
vcc
vcc
1-5
Page 9
TABLE OF CONTENTS
• SPECIFICATIONS
• PARTS LISTS
• SCHEMATICS
o s ^ ^
Page 10
A2065 SYSTEM SCHEMATICS
A2065 FUNCTIONAL SPECIFICATION
DESCRIPTION
The A2065 Ethernet LAN Card controller implements the 802.3 type protocol which calls for a 10 Megabit/sec
CSMA/CD interface. It supports both 10Base2 Type B (Cheapernet) and 10 Base5 Type A (thick Ethernet) connec
tions. The design has been developed around the AMD LANCE chipset which is comprised of the Am7990 Local Area
Network Controller for Ethernet, the Am7992B Serial Interface Adapter, the Am7996 IEEE-802.3 Ethernet/Cheapernet
Transceiver, and other associated logic necessary to implement a complete Ethernet interface.
ARCHITECTURE
A shared memory host interface was chosen because of the bus bandwidth requirements of the Am7990. A total of
32K of onboard buffering is provided to act as a shared interface between the Am7990 and Amiga CPU. This allows
for worst case conditions of back to back Ethernet packets received by the board during loaded 68000 or graphics
chip activity. In addition to the 32K of memory mapped packet memory, the Am7990’s I/O registers are also mapped
into the Amiga memory space as two sixteen bit locations. Finally, a small 256*4 Bit Prom is used to store the autoconfig
data as well as the board’s Ethernet address. The output side consists of both thick and thin (Cheapernet) Ethernet
interfaces. The thick interface comes directly from the Am7992B SIA with transformer isolation. To implement the
Cheapernet section, various passive components along with an Am7996 are required.
Functionally, the Ethernet interface may be partitioned into the following sections: Transceiver interface, autoconfig
and configuration logic, Bus control buffers and logic, and onboard control logic/buffering including the packet memory.
In the following sections each subsystem will be explored and discussed in more detail (refer to Figure 1).
TRANSCEIVER INTERFACE
The A2065 supports two types of cable media. The first type is commonly called “Thick Ethernet” or 10Base5. Thick
Ethernet is used mainly in large installations where many nodes must be supported and distances between active repeaters
are long. Typically, a transceiver box is physically connected to the Thick Ethernet backbone and a drop cable pro
vides the actual connection to the LAN interface card present in the computer. The Thick Ethernet connection is ac
tually a 15 pin Female D connector on the A2065 board. This physical interface is driven directly via transformer
isolation by the Am7992B SIA. The transformers provide DC isolation and are designed to meet IEEE specifications.
The function of the Am7992B is to decode/encode Manchester type serial data streams as per IEEE specifications
for Ethernet. The key circuitry surrounding the Am7992B is the 20 MHz crystal (XI), which must meet exacting specifica
tions, and the 5600 pF VCO Phaselock loop filter capacitor (C34). AMD data sheets call for a 5000 pF capacitor,
but information from AMD applications engineers indicates that a value up to 6800 pF should be acceptable. Current
ly, this part is specified at 5600 pF ± 10% or better. Specifications for the 20 MHz crystal are set forth in the data
sheet for the Am7992B. The jumper JP7 is supposed to affect the output signal for 802.3 applications. This jumper
requires further testing and may need to be deleted for production. Thick Ethernet requires a + 12V, 0.750A supply.
This is supplied directly from the Amiga expansion connector. Note that a fuse is provided to protect against short
circuits which might damage the Amiga or associated peripherals.
The second type of media is Cheapernet, commonly referred to as “Thin Ethernet” or 10Base2. Cheapernet evolved
as a result of media costs associated with Thick Ethernet. Cheapernet allows for a “ Bus” topology with up to 100
nodes. Inexpensive RG58 coax is used along with BNC T connectors and terminators. The Cheapernet section is com
prised of the AM7996, a + 5V to 9V DCDC converter, and various passive components which differentially drive
the coax media and also act to recover the incoming data stream. The Cheapernet section also implements collision
detection for collisions occurring on the media. Refer to the AM7996 data sheets for a complete technical discussion
of the operation of the Cheapernet transceiver.
2-1
Page 11
A2065 SYSTEM SCHEMATICS
AUTOCONFIG LOGIC AND CONFIGURATION LOGIC
Autoconfiguration is accomplished by reading the 256*4 AutoID Prom and relocating the physical base address of
the Ethernet board within some 64K of Amiga I/O memory space. The autoconfig logic is implemented in the 16L8A
PAL along with the Prom, the 74F521 address comparator, and the 74LS373 address latch. When the Ethernet board
is ready for autoconfiguration, its _CONFIGIN line is brought low, address 0xE80000 is decoded, and a board select
is generated. During the configuration process, the Prom parameters are read into memory to create the necessary
system structure for the configed devices. It should be noted that the board serial number is used to generate the board’s
physical Ethernet address. The signal _IDP is generated from the 16L8A PAL to decode the Prom chip select. The
read signal _RD to the Prom is generated from the 20L8A PAL. Refer to the PAL equations for details. Once the
Prom has been read, the Amiga will write to address 0xE80048 to load the onboard address latch. The Ethernet board
will generate a write pulse called SATL to load a 74LS373 with the board’s new base address. The SATL signal comes
from the 16L8A PAL. It is generated from a decode of 0xE80000 and a write strobe called _SWR. The _SWR strobe
comes from the 20R6A PAL. It is essentially a delayed write pulse using delayed AS and the 7M Amiga clock. Once
the latch is written, _CONFIGOUT is generated, enabling the output buffer of the 74LS373 latch. The board is now
relocated and will respond to its new address.
BUS CONTROL BUFFERS AND CONTROL LOGIC
The Ethernet board data path consists of a 16 bit (D15:D0) wide data bus and is used for reading and writing the
Ethernet local memory and the Am7990 registers. Only 4 bits (D15:D12) are significant with respect to the AutoID
Prom. Referring to Figure 1, a pair of 74LS245 and 74LS244 isolate the Amiga’s system bus from the internal Data/Ad
dress paths. Only the Amiga 68000 or the Am7990 can have access to this internal data/address path at one time.
Normally, the Am7990 is burst DMA reading or writing the 32K memory as packets are being received or transmitted.
The host 68000 requests access to this internal bus to either read/write memory or Am7990 registers. The 68000 ac
cesses are arbitrated based on the Am7990 requiring the bus. A wait state is inserted to guaranty meeting 60ns _AS
to XRDY delay during arbitration time. The bus control function is implemented by the 20R6A PAL. This PAL generates
the data bus transceiver control _DBE. This signal is active when there is no exceptional conditions and a signal _ABE
is active. _ABE is active only when the Am7990 is not requesting the internal bus (_HOLD, _LANCE not asserted).
This satisfies the condition that a mutually exclusive relationship exists between the 68000 and the Am7990. The Ethernet
board also listens on _BERR for bus faults; if _BERR is ever active, _DBE will not be active. The signal _LANCE
is generated to enable the LS244 buffers which pass the Am7990 DMA address thru to the Ram buffers. _LANCE
in conjunction with _ABE determines which source (68000 or Am7990) drives the internal address path. The Am7990
works in a multiplexed address/data method. First an address is latched during the first part of the read/write cycle,
then the actual data transfer occurs.
ONBOARD CONTROL LOGIC/BUFFERING
The onboard control logic consists mainly of chip selects and read and write strobes to memory and the Am7990.
The 32K buffer is partitioned into a high bank and a low bank of 8K * 16 bits each. Address line A14 determines
which bank is active. The read and write strobes to the memory are qualified by bus control signals. During 68000
R/W cycles, the signals READ, _UDS, and _LDS are used from the system bus along with _BSEL to control reading
data. These same signals plus one generated onboard called _ENDCYC are used to generate write pulses. _ENDCYC
is generated by the 20R6A PAL. During Am7990 bus ownership, a different set of signals controls the R/W timing
pulses. All these control signals are generated within the 20L8A Internal Bus Control PAL. The 20L8A PAL also
generates chip selects for the 32K memory and Am7990 I/O register. For further information, refer to the PAL equa
tions and the Am7990 data sheet.
LOW LEVEL INTERFACE PROGRAMMING
For a complete discussion of programming the Ethernet board, refer to the Am7990 application sheets and the Ethernet
device driver source. A brief explanation is given here. The Amiga configures the board and builds a config structure
in memory. The Ethernet software goes out and finds the location of the board and reads the serial number. The
serial number plus the manufacturer base Ethernet address make up the complete Ethernet address. The software then
sets up the initialization block in the 32K memory which sets up two circular linked list buffers, one transmit and
one receive queue. The initialization block refers to these queues as “descriptors” . The Am7990 is then programmed
via I/O transfers into internal registers for various network and operational parameters, along with the setting up
of an interrupt handler. Finally, the action starts. The network layer software fills buffers to transmit, while emptying
buffers that are filled from incoming packets.
2-2
Page 12
A2065 SYSTEM SCHEMATICS
A2065 ETHERNET BOARD MEMORY MAP
Amiga Address Size
xxOOOO
xx4000 4 bytes
xx8000
Notes: xx denotes upper address after autoconfiguration location (initially base board address appears at hex E80000).
The Autoconfig Prom is read only. It lies on data lines D15-D12. The serial number portion is used to hold the user
specific portion of the Ethernet address. This partial address is concatenated with the vendor portion of the Ethernet
address to form a full 6 byte address.
The Register Data Port and Register Address Port are defined in the Am7990 data sheets.
The 32K buffer is organized as 16K by 16 bits for word/byte, read/writes. This buffer is managed and initialized
as per the Am7990 LANCE data sheets.
The board is decoded into two 16K chunks and one 32K chunk. Total size is 64K.
A2065 ETHERNET BOARD JUMPERS
When the shunt plug is inserted into a jumper position, the corresponding signal is active.
Interrupt Jumpers
JP1 INTI
JP2 INT2 (default setting)
JP3 INT4
JP4 INT5
JP5 INT6
JP6 INT7
Am7992 Transmit Mode Jumper
JP7 Transmit mode select. Default is to leave shunt plug out. See the Am7992 data sheets for actual usage.
Thick Ethernet/Cheapernet Jumper Block
ABC When the AB jumper is connected with the shunt block, Cheapernet is selected; otherwise, the connection
of the BC jumper will select Thick Ethernet.
256 bytes
32K bytes
Usage
Autoconfig Prom
Contains standard autoconfig data and Ethernet address.
Upper data byte only, i.e. D15-D12.
Readable before and after autoconfig.
LANCE Ethernet controller chip
xx4000 Register address port (RAP)
xx4002 Register data port (RDP)
32K Packet Buffer
ENVIRONMENTAL TEST REQUIREMENTS
Units shall comply with the following environmental resistance requirements.
TEMPERATURE
Operational
Storage
Gradient
Temperature Cycle
HUMIDITY
Operational (relative) 10 to 90% (non-condensing)
Storage (relative) 5 to 95% (non-condensing)
VIBRATION
Non-operating (randomfrequency) 5.2 Gs per MIL-STD 202 Method 214, 15 min. in each of three axes
SHOCK
Operational 5 Gs to each of 6 axes, two 11 mSec half sinewave shocks
Non-Operational 20 Gs applied as above
ALTITUDE
Operational
Non-Operational
5 to 55°C
-2 0 to + 70°C
+ 10°C/hour
-2 0 to 60° C, 10 cycles, 10 minutes minimum at each extreme,
5 minutes maximum between extremes
0 to 3,000 meters
0 to 15,000 meters
2-3
Page 13
A2065 SYSTEM SCHEMATICS
ETHERNET
FIGURE / — FUNCTIONAL BLOCK DIAGRAM
2-4
Page 14
A2065 SYSTEM SCHEMATICS
Commodore International Spare Parts List
SHIPPING ASSEMBLIES
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries. ________________________________________________________________
532065-01
363097-06
363035-05
363361-01
314877-04 SERVICE CENTER LIST
318290-01
318928-01
313430-01
A2065 SHIPPING ASSY
BOX INDIVIDUAL PACKING
BOX BULK SHIPPING
MANUAL USERS GUIDE ENGLISH
WARRANTY CARD
ANTI STATIC BAG
PCB ASSY
Commodore International Spare Parts List
PCB Components
PCB Assembly #313430-01
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries.
IC COMPONENTS
313430-01
390586-01 74F38 U5
390092-01 74F02 U6
390198-01 74F86
901521-29
901521-46 74LS245
901521-13
318041-01 74F521
390081-01 74F74
390631-01 LSI AMD7990 LANCE U2
390632-01 AMD7992B SIA U20
390633-01 AMD7996 TRANSCEIVER U10
390636-01 20L8A INTERNAL BUS CONTROL PAL U17
390637-01 20R6A BUS CONTROL PAL
390638-01 16L8B CONFIG PAL U19
390639-01 PROM 256X4 AUTOCONFIG A2065
310024-01 8K X 8 SRAM 150 NS U1.U8.U16.U24
390640-01 LIN DC - DC CONV + 5VT O - 9V U3
390641-01
390642-01 CRYSTAL 20MHZ HC - 49/U X1
PCB ASSY A2065 ETHERNET LAN CARD
74LS373
74LS244
TRANSFORMER PULSE 75 UH
U7
U11.U12.U14
U13.U21
U15.U23
U22
U9
U25
U4
U18
IC SOCKETS
904150-05 L/P 28 PIN DIP .600
904150-02 L/P 16 PIN DIP .300
251313-01 DIP 48 PIN .600
390060-01
904150-08 L/P DIP 20 PIN .300
DIP 24 PIN .300
U1.U8.U16.U24
U4
U2
U17.U20.U25
U10.U19
RESISTOR NETWORKS
902410-07
902410-10 SIP 1K OHM 10 PIN
SIP 10K OHM 10 PIN
RN1.RN3
RN2
RESISTORS 1% @ 1/4 WATT, UNLESS OTHERWISE SPECIFIED
251575-55
251575-58 METAL 510 OHM
251575-39 METAL 3K
251575-54
251575-62 METAL 150K OHM
251575-46
251575-57 METAL 499 OHM
251575-60
251575-61
251575-35
901550-18 CF 2.2K OHM,
METAL 40.2 OHM
METAL 9.09 OHM R5,R7
METAL 174 OHM R4
METAL 24.9K OHM
METAL 75K OHM
METAL 1K OHM
V* WATT, 5 %
R2,R3,R13-R16
R11
R12
R1
R8
R9
R10
R6
R17
CAPACITORS
900020-08
900014-08
900019-15 CERM RAD 100PF MLC NPO C25.C26
900050-28
900019-12 CERM RAD MLC 680PF NPO
900019-33
900019-34
390646-01
900101-08 ELEC AXL 22 UF 25V
900402-08 TANT RAD 4.7UF 25V
900402-13 TANT RAD 1.0 UF 35 V
CER RDL .22UF 100V
CERM RAD .1 UF MLC X7R
MICA RAD 47PF NPO C10
CERM RAD MLC 5600PF NPO C34
CERM RAD MLC 220PF NPO C16
CERM RAD MLC 5.0 PF NPO
C3-C8.C11 ,C12.C17-C24,
C27-C29.C31 .C32.C37,
C40
C1,C13,C15,C33,C35,C9
C36
C14
C38.C39
C30
C2
CONNECTORS
390584-02 PCB MOUNT RT/ANGLE FEMALE BNC
390241-09 15 PIN DSUB RT/ANGLE FEMALE
903345-06
903326-02
390043-01 SHUNT FEMALE 2 POS
390043-02
390043-01 SHUNT FEMALE 2 POS (SUBSTITUTE FOR
313429-01
HEADER DIL 12 PIN .100 JP1-JP6
HEADER DIL 2 PIN .100 JP7
SHUNT FEMALE DIL .100 12 POS
390043-02)
ETHERNET CARD BRACKET
J1
J2
JP2
ABC
ABC
DIODES
900750-02 1N4002
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MISCELLANEOUS
316893-01 LABEL FCC ID A2065
366189-01
LABEL COPYRIGHT
2-5
Page 15
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Schematic #313431, Rev. A
Sheet 1 of 4
A2065 SYSTEM SCHEMATICS
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Page 17
Schematic #313431, Rev. A
Sheet 2 of 4
A2065 SYSTEM SCHEMATICS
2-8
Page 18
Schematic #313431, Rev. A
Sheet 3 of 4
A2065 SYSTEM SCHEMATICS
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Page 19
Schematic #313431, Rev. A
Sheet 4 of 4
A2065 SYSTEM SCHEMATICS
RM07996
2-10
Page 20
TABLE OF CONTENTS
• SPECIFICATIONS
• PARTS LISTS
• SCHEMATICS
b g nL
Page 21
A2232 SYSTEM SCHEMATICS
A2232 MULTIPORT SERIAL CARD
FUNCTIONAL SPECIFICATION
DESCRIPTION
The A2232 Multiport Serial Card is a standard 100 pin Zorro II expansion card for the Amiga 2000. It provides the
Amiga with 7 additional standard RS232 serial ports, capable of speeds up to 19.2 kbaud. For more serial channels,
additional A2232 boards can be plugged into the system at the same time.
SERIAL PORTS
All 7 of the serial ports are available at the rear of the board via 7 8-pin mini DIN connectors. The board comes
with 7 short adapter cables which can be plugged into each of these connectors, which provides a more standard DB-25
connection.
8 pin
signal
TxD / RxD
RxD / TxD 2
Request to Send (RTS) 3
Clear to Send (CTS)
Data Set Ready (DSR)
Signal Ground 6
Data Carrier Detect (DCD)
Data Terminal Ready (DTR)
mini DIN DB-25
1
4
5 6
7
8
2
3
4 out
5
7
8
20
dir
out/in
in/out
in
in
in
out
In order to simplify connections, the transmit data (TxD) and receive data (RxD) signals can be swapped on the A2232
board. There is an 8 jumper block (JB1) at the back of the board which makes this possible. Each of the 7 serial
channels is associated with 4 possible jumper locations, and uses 2 of the jumpers. Figure 1 shows the schematic for
this jumper block. Figure 2 shows how to configure the shorting blocks for a single channel.
All unused inputs have pullups on the board which keeps them at their ‘TRUE’ value if not connected. This greatly
simplifies things if you are only using a 3-wire connection.
A2232 SYSTEM CONFIGURATION
The A2232 expansion card conforms to the auto-config protocol,
auto-config size 64k bytes
manufacturer code 202 (hex)
product number 46 (hex)
A block diagram of the board is shown in figure 3.
An 8 bit processor was incorporated in the A2232 in order to remove the burden of handling I/O from the Amiga
system’s main CPU. Also, since the Amiga is multi-tasking, it is impossible to ensure that the system’s CPU can res
pond in a timely manner in order to service the needs of the I/O channels. The 8 bit processor used is a 65CE02,
which is an enhanced version of the 6502, providing faster operation through new instructions and higher operating
speeds.
The 6502 and the Amiga communicate mainly through the 16k bytes of shared RAM. The Amiga also has control
over the 6502’s *RESET and *IRQ signals. The 6502 can interrupt the Amiga via the *1NT2 interrupt line. The Amiga
must clear this interrupt itself.
3-1
Page 22
A2232 SYSTEM SCHEMATICS
CHANNEL 7
CHANNEL 6
CH ANNEL 5
CHANNEL 4
CHANNEL 3
CH ANNEL 2
CHANNE L 1
JB 1
FIGURE 1 — JUMPER BLOCK SCHEMATIC
FIGURE 2 — OPTIONS FOR CONNECTING TXI) & RXD FOR EACH CHANNEL
3-2
Page 23
I
FIGURE 3 — A2232 SYSTEM BLOCK DIAGRAM
A2232 SYSTEM SCHEMATICS
Page 24
A2232 SYSTEM SCHEMATICS
board
offset description
$0000-$3FFF 16k bytes of shared RAM
$4000 reset the *INT2 interrupt caused by the 6502
$8000 set 6502’s *RESET line low
$A000 set 6502’s *IRQ line low
$C000 set 6502’s *RESET line high
AMIGA’s MEMORY MAP OF A2232
The control signals listed above are affected when the Amiga does an access (read or write) to the locations listed.
No information is passed over the data bus.
The 6502 executes code which is downloaded by the Amiga into shared RAM. When the Amiga goes through a hard
ware reset, the *RESET line to the 6502 is latched low, keeping it frozen. This gives the Amiga a chance to download
the code which the 6502 is to execute. After the code is downloaded, the 6502 is started when the Amiga does a dummy
access at board offset of $C000, allowing the *RESET line to go high. The Amiga can freeze the 6502 at any time
later by accessing location $8000, latching the *RESET line low again. More or different code may now be loaded,
and the 6502 restarted again.
The 6502 has control over all 7 of the 6502 ACIAs. The Amiga cannot access them directly.
address description
$0000-$3FFF
$4400
S4C00 ACIA for channel 2
$5400 ACIA for channel 3
$5C00
$6400
$6C00
$7000
$7400 ACIA for channel 7
$7C00
$8000
$C000-$FFFF
6502's MEMORY MAP OF THE A2232
Note that 16k of RAM appears to the 6502 in 2 places. This was done so that the 6502’s ‘zero page’ of memory and
the reset vectors could be handled with the same RAM.
A2232 System Timing
The 7 Megahertz clock coming from the Amiga is used to drive a state machine that generates the clocks used on
the A2232. The PHI0 clock which drives the 6502 is divided down from the 7M clock. Normally, the 6502 runs at
3.5 Mhz. However, so that the board can use the less expensive 2 Mhz 655l ’s, the 6502 must slow down to 1.75 Mhz
when accessing the ACIA’s (655l ’s). Since the 655l ’s are provided with a constant 1.75 Mhz clock, the 6502 must
first sync up with the 655l ’s clock before completing the access. The 6502 is also slowed down while the Amiga ac
cesses the shared RAM. This is done by keeping the PHI0 clock low while the 68000 accesses the RAM, effectively
halting the 6502.
16k bytes of shared RAM
ACIA for channel 1
ACIA for channel 4
ACIA for channel 5
ACIA for channel 6
set Amiga’s *INT2 interrupt low
8520 CIA
Reset (set high) the *IRQ caused by the Amiga
16k bytes of shared RAM
Figure 4 illustrates the operation of the state machine. Each of the states is 1 7M cycle long (140 nanosecs). The arrows
connecting each of the states are numbered as different transitions.
3-4
Page 25
A2232 SYSTEM SCHEMATICS
FIGURE 4 — A2232 STATE MACHINE DIAGRAM
3-5
Page 26
A2232 SYSTEM SCHEMATICS
6502 RAM ACCESS
The 6502 accesses ram during states SO and S3. If it is determined during SO that the 6502 wants to access the RAM,
TR5 is used, bypassing S1-S2. The PhiO clock is low during SO, and goes high during S3, yielding the 3.5 Mhz clock.
At the end of S3, there are 2 different transitions that can be taken. TR4 is taken if the 68000 is not waiting to access
the RAM. If the 68000 is waiting to get at the RAM,'but is not properly synched with the Cl clock, TR4 is also taken.
TR6 is taken when the 68000 is waiting, and is properly synched.
Referring to figure 5 ...
(7)
- 50
- 15 74F257 delay (max)
- 15
-100 RAM access time
- 18
read data setup time : > = 40 nsecs
280
82
Phi2 cycle time
6502 address setup time (max)
*CS goes low, 20L8B delay (max)
74LS245 delay (max)
(8)
+ 5
(10)
- 50
- 18 74LS245 delay (max)
- 30
+ 5
(11)
+ 5
+ 5
ACCESSING 6551 ’s
Since the 6551 ’s can only run at 1.75 Mhz, they must be provided with a constant 1.75 Mhz (or less) clock. In order
for the 6502 to access the 6551, it must slow down to this speed as well. During SO, the state machine determines
that the 6502 wants to access a 6551. If the clock driving the 6551 is currently low, then the 6502 is in sync with the
6551 (the PHIO clock is always low during SO). TR1 is taken and the access may continue. If the 6551 clock is high,
then they are out of sync, and TR11 is taken. TR12 immediately follows TR11, during which the 6551 clock is in
verted. The state machine now determines during SO that they are in sync, and TR1 can be taken. PHIO and the 6551
clock are both low during SI, and go high during S2 and S3, yielding 1.75 Mhz. At the end of S3 the same decisions
as described at the end of a RAM access are again executed.
read data hold time : > = 10 nsecs
5
10
write data setup time : > = 50 nsecs
140 Phi2 high time
47
write data hold time : > = 5 nsecs
5
15
20L8B delay (min)
74LS245 turn off time (min)
6502 write data delay (max)
PhiO to Phi2 delay (max)
20L8B PAL delay (min)
PhiO to Phi2 delay (min)
20L8 PAL delay (min)
74LS245 turn off (min)
3-6
Page 27
A2232 SYSTEM SCHEMATICS
3-7
FIGURE 5 — 6502 RAM ACCESS
Page 28
Referring to figure 6 ...
(1) setup time for ADR, RSO-3,R/W,CS,*CS : > = 70 nsecs
The latest of these signals is *CS.
280 6551 CLK low time
- 30 PhiO to Phi2 delay (max)
- 40 6502 Address setup time (max)
- 30 74LS138 delay (max)
180
(2) write data setup time : > = 60 nsecs
280 6551 CLK high time
- 30 PhiO to Phi2 delay (max)
- 50 6502 write data setup time (max)
- 18 74LS245 delay (max)
182
(3) write data hold time : > = 20 ns
5 PhiO to Phi2 delay (min)
+ 5 20L8B delay (min)
+ 5 74LS245 turn off time (min)
A2232 SYSTEM SCHEMATICS
15 (case 1)
5 PhiO to Phi2 delay (min)
+ 5 6502 write data hold (tHD min)
+ 5 74LS245 in to out delay (min)
15 (case 2)
(4) read data setup time : > = 40 nsecs
280 Phi2 high time
4- 5 PhiO to Phi2 delay (min)
- 150 read data access of 6551 (max)
- 18 74LS245 delay (max)
107
(5) read data hold time : > = 10 nsecs
5 20L8B delay (min)
+ 5 74LS245 turn off time (min)
10
3-8
Page 29
A2232 SYSTEM SCHEMATICS
FIGURE 6 — ACCESSING 6551’s
3-9
Page 30
A2232 SYSTEM SCHEMATICS
68000 RAM ACCESS
There are 2 states during which a 68000 request can be recognized. One of these is S3, which has already been described.
During SO a 68000 request can also be recognized. In both instances, the 68000 takes precedence. If the 68000 doesn’t
want access, then the 6502 is allowed to continue. During 68000 accesses the 6502 is halted by holding the PhiO clock
low. TR7 and TR6 both bring the state machine to S4, where the 68000 access is allowed to finish. From the time
that the board is selected, it drives the override (*OVR) and *DTACK signals until the end of S5. As long as it may
take for the state machine to get to S4, wait states are inserted into the 68000 access by keeping *DTACK high. At
the beginning of S4 *DTACK goes low signalling to the 68000 that the access may be completed.
Referring to figure 7 ...
(15) read data setup time : > = 10 nsecs
referenced from the start of 68000 T4 ...
210 time from start of T4 to end of T6
- 15 Q delay of 16R8A PAL, PhiO goes low (max)
- 30 PhiO to Phi2 delay (max)
- 15 20L8B PAL delay, MUX goes low (max) (*RAMCS goes low too)
- 15 74F257 switching delay (max)
- 100 RAM access time
- 10 74ALS245 delay (max)
- 18 74LS245 delay, on expansion bus (max)
7
(16) read data hold time : > = 0
Obvious.
(17) write data setup time : > = 50 nsecs
Assume that C3 transitions coincident with the rising edge of the 7M clock. Referenced from the ris
ing C3 at the beginning of T4, the RAM *WE goes high 140 ns later. Referenced from the same ris
ing edge of C3, the data becomes valid:
15 Q delay of 16R8A PAL (max)
-l- 35 20L8 PAL delay (max)
+ 7 74F32 delay (max)
4- 20 74ALS245 turn on time (max)
77 ns
So, 140 - 74 = 66 ns
(18) write data hold time : > = 5 nsecs
The write pulse went away half way through S5. The data and addresses stay valid through the rest
of S5, or approximately 70 nsecs.
3-10
Page 31
A2232 SYSTEM SCHEMATICS
X
X
X
X
FIGURE 7 — 68000 RAM ACCESS
UJ
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3-11
Page 32
A2232 SYSTEM SCHEMATICS
Commodore International Spare Parts List
SHIPPING ASSEMBLIES
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries.
31285901 A2232 SHIPPING ASSY (U.S.) 312859-03
363128-01 BOX PACKING
363127-01
363100-01
363375-01 MANUAL, USERS EFIGS
314877-04 BOOKLET SERVICE CENTER LIST 312864-02 CABLE ASSY MINI DIN TO DB25 (QTY = 7)
312864-02
318290-01 CARD WARRANTY U.S. 318928-01
318928-01 BAG ANTI STATIC 318896-01 S/W LICENSE AGREEMENT
318896-01 S/W LICENSE AGREEMENT
317769-01 DISKETTE ASSY
318940-01 SPACER CARDBOARD 312860-01 PCB ASSY
312860-01 PCB ASSY
318733-02 MANUAL AMIGATERM
312341-02
BOX BULK SHIPPING 363127-01 BOX BULK SHIPPING
MANUAL, USERS (SUB) 363100-01 MANUAL, USERS (SUB)
CABLE ASSY MINI DIN TO DB25 (QTY = 7)
CARD DISK EXCHANGE
312859-02 A2232 SHIPPING ASSY (EFIGS)
363128-01
363127-01
363100-01
363375-01
312864-02
318928-01
317769-01 DISKETTE ASSY
318940-01 SPACER CARDBOARD
312860-01
318733-02 MANUAL AMIGATERM
BOX PACKING
BOX BULK SHIPPING
MANUAL, USERS (SUB)
MANUAL, USERS EFIGS
CABLE ASSY MINI DIN TO DB25 (QTY = 7) (CAN SUB to -0 1 )
BAG ANTI STATIC
PCB ASSY
363128-01
363375-01 MANUAL, USERS EFIGS
318882-01
317769-01
318940-01
318733-02 MANUAL AMIGATERM
318556-02 CARD DISK EXCHANGE CANADA
312859-04
363128-01
363127-01 BOX BULK SHIPPING
363100-01 MANUAL, USERS (SUB)
363375-01 MANUAL, USERS EFIGS
312864-02 CABLE ASSY MINI DIN TO DB25 (QTY = 7)
318884-01 CARD WARRANTY AUSTRALIA
318928-01 BAG ANTI STATIC
317769-01 DISKETTE ASSY
318940-01 SPACER CARDBOARD
312860-01 PCB ASSY
318733-02 MANUAL AMIGATERM
A2232 SHIPPING ASSY (CANADA)
BOX PACKING
CARD WARRANTY CANADA
BAG ANTI STATIC
DISKETTE ASSY
SPACER CARDBOARD
A2232 SHIPPING ASSY (AUSTRALIA)
BOX PACKING
3-12
Page 33
A2232 SYSTEM SCHEMATICS
Commodore International Spare Parts List
PCB Components
PCB Assembly #311611-01
Commodore part numbers are provided for reference only and do not indicate the availability of spare parts from Commodore. Industry standard
parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may
not be available in all countries.
IC COMPONENTS
312860-01 PCB ASSY A2232 SERIAL CARD
318029-03 8520A-1
390373-01 16R8A PAL
390370-02
390371-02
390372-03
901521-06 74LS74 U18
901522-30
390077-01
318041-01 74F521 U12
901521-16 74LS138
901521-46 74LS245 U31.U32
390091-01
901521-29 74LS373
318092-01 74ALS245
901882-01 MC1488 QUAD DRIVER
901883-01
901895-03
310024-02 8K X 8 SRAM 100 NS
390375-02 LSI CPU 65CE02
901895-02 6551A UART
16L8 PAL
20L8A PAL
20L8B PAL
7407
74F32 U16
74F257
MC1489 QUAD RECEIVER U51.U53.U55.U57.U71,
6551A UART
U78
U13
U17
U15
U14
U39
U36
U3.U4.U34.U35
U11
U1.U2
U59-U61 .U79-U81
U73.U75
U52,U54,U56,U58,U72,
U74.U76
U37.U38
U33
SUB FOR ITEM 21
SOCKETS
904150-08
390060-01 24 PIN DIP SOCKET
904150-05
904150-06 40 PIN DIP
20 PIN DIP
28 PIN DIP
U13.U17
U14.U15
U52.U54.U56.U58.U72.
U74.U76
U33.U78
RESISTORS
902441-22
902441-31
902442-55
901550-01
901550-18
PAK 6 PIN SIP 1K
PAK 6 PIN SIP 4.7K
PAK 8 PIN SIP 4.7K
1K 5% 1/4 WATT
2.2K 5% 1/4 WATT
RP1.RP6
RP2
RP3-RP5
R2
R3.R4
CAPACITORS
900020-01
390101-05
.1 UF -5 0V 20%
ELECT ALUM RAD LEAD 4.7 UF
C1-C4.C11-C18.C31-C39,
C51-C58.C70-C76.C78
C96-C99
MISCELLANEOUS
325566-16
251842-04
903025-01 FERRITE BEAD
903345-29 CONN 56 PIN DIL HEADER .10 CENTERS JB1
390043-01
390218-02 CONN 8 PIN MINI DIN RECEPTACLE
312865-01
906800-05
316914-01
OSCILLATOR 1.8432 MHZ Y1
EMI FILTER 470PF EMI 1 -EMI 49
SHUNT FEMALE 2 POS
EXTENSION CARD PANEL
SCREW 3M X 6 LG PAN HEAD PHILLIPS -
QTY 2
LABEL FCC ID A2232
FB1-FB4
CN1-CN7
3-13
Page 34
3-14
f l
=0
=0
EH3l 1 EH*
EHfe[
EH7[
_____
tie
Ml
S 3
m
El?
'll
S3*
0 «
L
PCB BOARD LAYOUT #312863, REV. 5
A2232 SYSTEM SCHEMATICS
Page 35
A2232 SYSTEM SCHEMATICS
A2232 SCHEMATIC #312861, REV. A — SCHEMATIC PAGE INDEX
Sheet 1 of 8
TITLE SHEET PAGE
A2232 SCHEMATIC PAGE INDEX 1 of 8 3-15
A2232 SERIAL CARD — EXPANSION BUS CONNECTOR,
ADDRESS & DATA BUFFERS 2 of 8 3-16
A2232 SERIAL CARD — AUTOCONFIG STUFF,
MISC. CONTROL SIGNALS 3 of 8 3-17
A2232 SERIAL CARD — 6510 INTERFACE, SHARED RAM 4 of 8 3-18
A2232 SERIAL CARD — SERIAL PORTS 5 of 8 3-19
A2232 SERIAL CARD — SERIAL PORTS 6 of 8 3-20
A2232 SERIAL CARD 7 of 8 3-21
A2232 SERIAL CARD — BYPASS CAPS, SPARES 8 of 8 3-22
3-15
Page 36
Schematic #312861,
Sheet 2 of 8
A2232 SYSTEM SCHEMATICS
Rev. A
MD
3-16
Page 37
Schematic #312861,
Sheet 3 of 8
Rev. A
A2232 SYSTEM SCHEMATICS
PD
xPRECONFIG
xCQNFIGOUT
LA10
xAC I A6
LA15
XC1
xSLAUE
LAM
6510-RU
7M
\
v PD15
y P DH
v PD13
v PD12
v PD 11
v PD10
v PD9
V PD8
Ull
74LS373
18
8D
17
7D
14
6D
13
5D
4D
3D
2D
ID
E N O E
i Yi
i
U13
PAL16R8B
Q8
18
17 Q7
16 Q6
Q5
15
14 Q4
03
13
12 02
Q1
11
CK
OE
19
8Q
16
7Q
15
6Q
12
5Q
4Q
30
20
IQ
19
18 ST0
17
16 ST2
15
14
13
12
—V/v-
R4
2.2K
ST 1
.
1 •
XSYNC
FB2
G4
U39
7407
4 >
U12
74F521
A0
A1
A2
A3
11
A4
13
A5
15
A6
17
A7
A V r
A V
AAr
A V
A M
RPi
IK
X6510.IRQ1
4—W-,
4-A V
4—W
Aa \ - ^A 19
1 + 5
i RP2
j 4 • 7K
4—W -1
A23
( A22
/_A21
^ A18
^ Al?
^Ai e
U16
xCONFIGIN
XAS
_______
2
xDTACK
PH 10
, 74F32
*68K_RESET
X68KDB
xCl
xC3
CDAC 5
MA15
MA M
MA13
PH I 0
11
9
8
7
6
4
3
2
1
U17
PAL16L8
110
08
107
19
18 106
17
16
105
104
15
14
103
13 102
12
11 01
19
18
17
16
15 X6510-UNRESET
14
13
12
X6510-RESET
X6510-IRQ1
*6510_UNIRQ
3
5
7
9
12
14
16
18
x I NT 2
B0
Bi
B2
B3
B4
B5
B6
B7
A-B
ENA
19
S >
U16
,74F32
U39
7407
xSLAUE
, FB4
xOUR
6551-CLK
ST 1
________
XCQNFIGOUT
ST2
________
XUDS_______
XLPS
______
MA15
_______
ma i 4
_______
68K-RU
6510-RU
CPAC
______
*C3
________
XC1
_______
LA0
________
PH 12
U14
PAL20L8B
23
114
14
113
13
112
11
111
10
110
9
19
8
18
17
16
15
14
13
12
11
22 XRAMOE
08
15
07
21
106
105
104
103
102
101
*6510DBHIGH
20
*6510DBLOW
19
18
17
16
MUX
B68K-RU
XUP
xRAMHIGH
xRAMLOU
ST0
ST 1
ST2
6510_RU 11
B68K.RU 10
XSLAUE
XBERR
X68K-RESET
A6
A5
A4
A3 3
A2
A1
23
14
13
U15
PAL20L8
114
113
112
111
110
9
19
8
18
7
17
6
16 106
5
15
4
14
13
2
12
1
11
08
07
105
104
103
102
101
22
15
21
20
19
18
17
16
A U18
* 74LS74
PR
2
u VJ
3
xPRECONFIG
xCQNFIGOUT
*
CL
<
1
X68KDB
PH 12
ND
MD15 y
MD14 y
MD13 y
MD12 J
3-17
Page 38
Schematic #312861, Rev. A
Sheet 4 of 8
A2232 SYSTEM SCHEMATICS
LD
MD15
U31
74LS 24 5
f MD14
8
^ 0 1 3
7
^MD12
6
^ MD11 5
^ MD 10 4
^ M D9
3
^ M D8
2
A8
B8
A7
B7
A6 B6
A5
B5
A4
A3
B3
A2
B2
Ai B1
A-B
EN
11
LD7
12
LD6
13
LD5
14
LD4
15 LD3
16 LD2
17
LD1
18
LD0
\
*65 10 DB HI GH
U32
74LS 245
MD7
9
^ MD6
8
/'MD5
7
S' MD4
6
S't1D3
5
S' MD2
4
a MD1 3
^h1D0
2
A8 B8
A7 B7
A6
B6
AS
B5
A4
B4
A3 B3
A2 B2
Al
B1
A->B
EN
11
LD7y
12 LD6 y
13
LD5 y
14 LDAy
15 LD3y
16
L D2y
17
LD1
PH I 0 37
U33
6502
18 LD0 J
*651 0D BL OW
v M A12
23
V MAI 1
21
V M A10
24
v MA9
25
^ M A8 3
V MA7
4
V M A 6
5
V MA 5
6
V MA4
7
V MA3
8
v MA2
9
MAI
10
U38
6264
A12
07
All
06
A10
05
A9
04
A8
03
A7
02
A6
01
A5
00
A4
A3
WE
A2
OE
Al
CS1
A0
CS2
1 9 J 1 D1 5 /
18
MD 14 v
17
MD 13 v
16
MD 12 >
15 M D1 1
y
13
MD10 >
12
M D 9 ^
11
m s j
o27
#WP
o22
*RAM OE
_
xRAMH IG H
*651 0_I RQ 1
4 C
4 c i
2 w
! « c
7"
38c
>
V L D7
26
V L D6
27
V L D5 28
v LD4
29
v LD3
30
V LD2 31
VL D1 32
V LD0
33
PH I 0
PH 12
IRQ
RESE T
RDY
PH 11
NMI
R/W
SYNC A15
SO
A14
A13
A12
Ail
A10
A9
A8
D7
A7
D6
A6
D5
A5
D4 A4
D3 A3
D2
A2
D1
Al
D0
A0
39
40 *6510-.RESET
FB3 PH I 2
3
34
25 LA15
24 LA 14 >
23
LA13 N
22
LA 12 ^
20
LAI 1 N
19
LA1 0 ^
18
L A9^
17 LA8 N
16
LA? ^
15
L A6^
14 LA5 N
13
LA4 N
12
L A 3 n
11
L A2n
10
LAI A
9
LA0 "s
LA
V
651 0_ RW
U16
74F3 2
12
13
U39
7407
R2
IK
—Wv-
LA14
6
''l a i s
^ # SYN C
50
LA 13 3
^LA 12
2
"LA11 1
U36
74LS 13 8
G1
Y7
G2A Y6
G2B Y5
Y4
Y3
C
Y2
B
Y1
A
Y0
MA
v NA13
y N A12
V MAI 1
26
MD
2
23
21
U37
6264
y MA 10
y MA9
V MA 8
V MA7
V NA6
y M A5
y MA 4
y MA 3
v MA2
+ 5
MAI
24
25
3
4
5
6
7
8
9
10
A12
07
Ail 06
A10
05
A9
04
A8 03
A7 02
A6 01
A5 00
A4
A3
WE
A2
OE
Al CSi
A0
CS2
19 MD7y
18 MD6>
17
M D 5v
16
MD4 v
15
M D 3v
13
M D 2v
12
MD1 v
11
MD 0 V
*22—
*WP
.22
*RAM OE
,20
XRA ML OW
26 ,
*ACI A7
.9 *A CIA6
>10
*ACIA 5
>u
XACIA 4
>12
#A CI A3
,13
* A C1A2
,14
*ACIAi
■ il
__
*ACI A0
3-18
Page 39
Schematic #312861, Rev. A
Sheet 5 of 8
A2232 SYSTEM SCHEMATICS
XAC IA 0
• e*
LA2 ^ 14
LAI
655 1- C LK
X651 C RES ET
*6 51 0- IRQ1
651 0- RW
MD7
f MD6
/'t'1D4
/'MD3
/"l’1D2
^MD l
a MD0
XRXD O
2
13
27
4 0
2 6 o
28
25
24
23
22
21
20
19
18
U52
6551
CS1 RXC
CS0
RSI
RS0
PH 12
RST
IRQ
R/XU
D7
D6
D5
D4
D3
D2
D1
D0
CTS
TXD
DCD
DSR
RTS
RXD
XTL0
XTL1
UCC
GND
U51
MC14 89
DTR
10
16
17
12
15
GND
GND
_L C52
.1 UF
CLK
RXD0
2 rxo
U59
MC14 88
O
U59
MC14 88
10
O
DSR0
U59
MC14 88
t>*
U51
MC14 89
XTXD0
DTR0
RTS0
xACIA1
| CT
LA2 ^ 14
LAI
65 51 _CLK
X651 0- RE SE T
*651 0_I RQ1
6510 -RW 2 8
MD7
f MD6
^ M D5
r ftQA
^ MD3 21
^ N D 2
^M D l
/'f1D0
MD
13
27
2 6 o
25
24
23
22
20
19
18
XRXD1
U53
MC1489
DSR1 10
U54
6551
CS1
2
CS0
RSI
RS0
PH 1-2
n
RST
IRQ
R/xUI
D7
D6
D5
D4
03
02
D1
D0
RXC
CTS
TXD
DCD
DSR
DTR
RTS
RXD
XTL0
XTL1
UCC
GND
U53
MC1 48 9
10
.16
17
12
15
_L C54
GND
GND
. 1 UF
CLK
U59
MC14 88
U60
MC I 488
t o
U60
MC I 488
9
10
O
XTXD1
6
8
DTR1
RTS1
U55
MC14 89
XA CI A3
1 c*
LA2 ^ 14
LAI
655 1-C LK
x65 10 -R ES ET
X651 0-IR Q1
6510 -RW 28
MD7
MD6
a MD5
^ M D 4
/'h1D3
/'M02
^M D l
^ M D0
MD
13
27
4C
26o
25
24
23
22
21
20
19
18
XRXD3
U57
MC14 89
U58
6551
CS1
2
CS0
RSI
RS0
PH I 2
RST
IRQ
R/x U
D7
D6
D5
D4
D3
D2
D1
D0
RXC
CTS
TXD
DCD
DSR
DTR |*
RTS
RXD
XTL0
XTL1
UCC
GND
U57
MC1 48 9
---
o-^
10
o±£—
rJJ—
11
12
15
GND
GND
C58
. 1 UF
CLK
U61
MC I 488
O
U61
MC1 488
9
10
O
U61
MC14 88
3
__
_
6
8
XTXD3
DTR3
RTS3
3-19
Page 40
Schematic #312861, Rev. A
Sheet 6 of 8
DSR4
*ACI A4
j tr
—*-c
2
LA2 ^
14
LAI
13
655 1_C LK
27
* 6 5 1 C_ R E S E T
* v
#651 0_I RQ 1
2So
651 0_R W
28
MD7 25
f MD6
24
^ M D5
23
^ MD4 22
^ MD3
21
r V\02
20
r MD1
19
18
MD
*RXD 4
U72
6551
CS1
CS0
RSI
RS0
PH I 2
RST
IRQ
R/*W
D7
D6
D5
DA
03
D2
D1
D0
RXC
CTS
TXD
DCD
DSR p
DTR
RTS c>
RXD
XTL0
XTL1
UCC
GND
U71
MC1 48 9
10
16
17
LI
8
12
15
GND
GND
CLK
_L C72
.1 UF
U79
MC14 88
2 |X _ 3
U79
MC I 488
6
9
10
U79
MC148:
0 s
DSR6
*ACI A6
LA10
—
2
LA2
14
LAI
13
6551 _C LK 27
*65 10_ RE SE T
4 C
x651 0_I RQ1
2<5c
6510 -R W
28
MD7 25
MD6
24
^ M D5
23
r MD4
22
/ 'n D 3
21
r nD2
20
^M D l
19
^ M D0
18
MD
*RXD 6
U76
6551
CS1
CS0
RSI
RS0
PH 12
RST
IRQ
R/XW
D7
D6
D5
D4
D3
D2
D1
D0
RXC
CTS
TXD
DCD 0^
DSR o:
DTR
RTS
RXD
XTL0
U75
MC1 4 89
XTL1
UCC
GND
10
16
17
11
12
15
GND
GND
CLK
C76
.1 UF
U80
MC1 48 8
2 f \ _ 3
12
13
0 ^
U80
MC1 48 8
9
10
[ >
U81
MC I 488
O
A2232 SYSTEM SCHEMATICS
U71
MC1 48 9
*TXD 4
DTR4
RTS4
U73
MC I 489
U75
MC1 48 9
XTXD 6
MD
y MD0
22
V MD 1
32
V MD2
31
^ MD3
30
v M D4
29
v MD5
28
V MD6
27
MD?
26
LAI
38
LA2
37
LA3 36
LA4
35
* 65 10_R E SET3 4 V
DTR6 *65 10 _I RQ 1
-------
^
21 c
65 10 -R W
22
65 51 -C L K
25
24
RTS6
XAC IA 7
U78
8520
D0
PA0
D1
PA1
D2
PA2
D3
PA3
D4
PA4
D5
PAS
D6
PA6
D7
PA7
RS0
CNT
RSI
SP
RS2 PB 0
RS3
PB1
RESET PB2
IRQ
PB3
R/XW
PB4
PH 12
PBS
f l a g
PB6
CS1
PB7
PC
TOD
2
XDCD 0
3
xDCDi
4
XDCD 2
5
XDCD 3
6
XDCD 4
7
XDCD 5
8
XDCD 6
_2_
40
XCTS 0
39
RXD0
10
XCTS 0
11
#CTS1
12
XCTS 2
13
XCTS 3
14
XCTS 4
15
XCTS 5
16
XCTS 6
17
18
19
3-20
Page 41
Schematic #312861, Rev. A
Sheet 7 of 8
J B1
* T X D 0
i r**"'
9
C 0 P 3
LLI
t
l
C 0 P 2
* RX D0
l
l
il!
1
1
* TX D 1
i
i
C 1 P 3
lLi
l
•
C 1 P 2
#RXD 1
l
•
lU
l
l
* T X D 2
i i
i
C 2P3
lLi
i
•
C 2 P 2
* RX D 2
1
l
l
iL;
l
l
* T X D 3
i
i
C 3 P 3
l|_!
•
i
C 3 P 2
* RX D 3
•
i
i
iLi
i
i
* T X D 4
1
l
1
C 4 P 3
U_1
i
i
C 4 P 2
* RX D 4
l
•
lu
I
1
* T X D 5
1
1
•
i
C 5 P 3
lU
l
l
C 5 P 2
* RX D 5
1
1
i
i
u_i
•
i
* T X D 6
•
i
C 6 P 3
l|_!
•
i
C 6P2
* RX D6
i
i
i l :
■
•
DCD 0
D S R 0
C TS0
DC D 1
DS R 1
C T S 1
DCD 2
2 ?-
A A .
3i
V
A A _
4 i
V \r
— VV^
A A _
6!
V 'T
A A _
7 •
— V > r
2 1
Vv ^
—A V -1
—+12
R P 3
DC D 3
DSR 3
C T S3
DC D 4
DSR4
C T S4
DC D5
A2232 SYSTEM SCHEMATICS
U 5 1
MC 1 4 8 9
* DC D 0
C0P2
R T S0
E M M
D S R 0
EM I 3
DC D 0
- o
EM I 2
U 5 3
M C I4 89
*DCD 1
C 1P2
RT S 1
D SR1
DC D1
U 55
MC 1 4 89
*D C D 2
C 2 P 2
R T S2
DSR2
DC D 2
U 57
MC 1 4 8 9
*D C D 3
C 3P2
R T S3
DSR 3
DC D 3
C 4P2
R T S4
DS R4
DC D 4
C 5 P 2
R T S5
E M I 1
E MI 13
E M I 14
E M I 11
EMI 1 2
, EM I 15
E M I 16
I EMI 17
E M I 18
EM I 2 7
EM I 2 8
EM I 2 5
; EM I 2 6
EM I 2 9
EM I 30
EM I 3 1
EM I 3 2
EM I 3 6
EM I 3 7
D S R 5
DC D5
EM I 3 8
EM I 3 9
U 75
MC 1 4 8 9
*D C D 6
C 6P2
EM I 4 3
R T S6
EM I 4 4
DSR6
DC D 6
EM I 4 5
EM I 4 6
CN 1
CN2
CN3
CN4
C N 5
CN6
C N 7
EM 16
EM I 7
, EM 15
, EM I 8
■ a
EM I 9
■ a
E M I 1 0
EM 12 0
EM I 21
E M I 1 9
EM I 22
EM I 23
iE M I2 4
EM I 33
EM I 34
, EM I 3 5
EM I 40
EM I 41
EM I 4 2
, EM I 47
EM I 48
, EM I 4 9
C 0P3
C T S 0 1
GND
D T R0
C 1P 3
GND
DT R 1
C 2P3
GND
D T R2
C 3P 3
GND
D T R3
GND
D T R 4
C 5P 3
U 5 1
M CI4 8 9
3 * C TS 0
C T S 1 1
U 53
MC 1 4 89
3 xCT S l
C T S 2 1
GND
D T R5
C 6P 3
GND
D T R6
U 55
MC 1 4 89
3 * C TS 2
CT S3 1
U 57
MC 1 4 8 9
3 * C T S3
C 4P3
C T S 4 1
U 7 1
MC 1 4 8 9
3 * C TS 4
C TS5 1
U 73
MC 1 4 8 9
3 X CTS5
C TS6 1
U 7 5
MC 1 4 8 9
3 * C T S 6
2.
A
±
5.
6_
7_
JL
AV
AV-
AV
A \-
AV
A V - I
—+12
R P 4
3-21
Page 42
A2232 SYSTEM SCHEMATICS
Schematic #312861, Rev. A
Sheet 8 of 8
SPAR ES
U39 U39
7407
740 ?
GND 9
V 8
GND 5
X 6
i
U39
7407
GND 11
3-22
Page 43
o Commodore
Computer Systems Division
1200 Wilson Drive
West Chester, PA 19380
Page 44
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