Commodore 1541, 1540 Service Manual
SERVICE MANUAL
MODEL 1540/1541
DISK DRIVE
NOVEMBER, 1985 PN-314002-01
Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380
U.S.A
Commodore makes no expressed or
implied warranties with regard to
the information contained herein.
The information is made available
solely on as is basis, and the entire
risk as to quality and accuracy is
within the user. Commodore shall
not be liable for any consequential
or incidental damages in connection
with the use of the information
contained herein. The listing of any
available replacement part herein
does not constitute in any case a
recommendation, warranty or
guaranty as to quality or suitability
of such replacement part.
Reproduction or use without
expressed permission, of editorial or
pictorial content, in any matter is
prohibited.
This manual contains copyrighted and proprietary information. No
part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form by any means, electronic,
mechanical, photocopying, recording or otherwise, without the
prior written permission of Commodore Electronics Limited.
Copyright © 1985 by Commodore Electronics Limited.
All rights reserved.
• SPECIFICATIONS
• BLOCK DIAGRAM
• CARE AND MAINTENANCE
• OVERVIEW
• FLASH CODE
• CIRCUIT THEORY
o POWER SUPPLY
o RESET LOGIC
o CLOCK CIRCUITS
o MICROPROCESSOR CONTROL OF RAM AND ROM
o SERIAL INTERFACE
o MICROPROCESSOR R/W AND MOTOR CONTROL LOGIC
o READ/WRITE CONTROL LOGIC
CONTENTS
o READ AMPLIFIER
o WRITE AMPLIFIER
o POWER UP/DOWN WRITE PROTECTION
o STEPPER MOTOR CONTROL CIRCUITS
o SPINDLE MOTOR CONTROL CIRCUITS
• TROUBLESHOOTING GUIDE
• RESISTANCE CHECKS
• CASEWORK/ACCESSORY PARTS LIST
• MODEL INDENTIFICATION
• DEVICE NUMBER CHANGE
• PC ASSEMBLY 1540001
o BOARD LAYOUT
o PARTS LIST
o PIN CONFIGURATIONS
o SCHEMATIC
• PC ASSEMBLY 1540048
o BOARD LAYOUT
o PARTS LIST
o UPGRADE NOTES
o SCHEMATIC
• PC ASSEMBLY 250442, 250446
o BOARD LAYOUT
o PARTS LIST
o IC PINOUTS AND INTERNAL DIAGRAMS
o SCHEMATIC
• POWER SUPPLY ASSEMBLY 154002
o PARTS LIST
o TRANSFORMER
o ASSEMBLY DRAWING
• ALPS DRIVE ASSEMBLY
o PARTS LIST
o WIRING DIAGRAM AND LAYOUT
o MOTOR CONTROL PCB SCHEMATIC
• NEWTRONICS DRIVE ASSEMBLY
o PARTS LIST
o WIRING DIAGRAM AND LAYOUT
o MOTOR CONTROL PCB SCHEMATIC
C1541 DISK DRIVE
PRODUCT SPECIFICATION
GENERAL DESCRIPTION
MAXIMUM STORAGE
MEDIA
INPUT/OUTPUT
CONTROLLER
MEMORY
DATA TRANSFER RATE
FILE TYPES
NUMBER OF FILES
COMPUTERS
MEDIA COMPATIBILITY
POWER REQUIREMENTS
The C1541 Disk Drive is an external 5-1/4 inch floppy diskette recorder,
offering high-speed and capacity for programs and data. It is an intelligent
device, containing its own microprocessor, RAM, ROM and operating systems
software for faster speed of throughput and memory efficiency in the computer
170K of data (formatted) - 35 tracks
5-1/4 Inch floppy disk. Single sided, single density, soft sectored (double
density can be used, but not needed)
Commodore serial interface
Second serial port for chaining a second drive or printer
MOS 6502 microprocessor - 1 MHz clock
2K RAM, 16K ROM
400 Bytes/sec
Program, sequential, relative, random-access and user
Up to 144 different files per diskette
C64, VIC 20, SX64, Educator 64, Plus/4, C16
2031, 4040, C1551, C1571
120 Volts AC, 60Hz - integral power supply with external 1 Amp fuse
POWER CONSUMPTION
30 Watts maximum
CARE AND MAINTENANCE
• DO NOT use MAGNETIZED tools when repairing or adjusting a disk drive.
• DO NOT place a disk drive near any device which generates "noise" e.g., - motors, radios televisions.
• DO NOT stack drives upon each other or in any way inhibit air flow around the unit. HEAT BUILD-UP
can cause disk failures.
• Periodically CLEAN the read/write head with 90% isopropyl alcohol and a cotton swab. CHECK load
pad for excess wear. Clean or replace as necessary.
• Take the following precautions when handling a diskette:
ALWAYS store a diskette in its jacket.
Use ONLY felt-tip pens when writing on the label of a diskette.
Do not bend or physically damage a diskette.
Do not place a diskette in the area of a magnetic field.
Do not attempt to clean a diskette.
Do not touch the exposed area of a diskette.
• DIAGNOSTIC and ADJUSTMENT procedures are outlined in detail on the diagnostic disk
(Commodore Part #31405101). A manual has been added to the diagnostic package. It contain
descriptions of testing procedures and adjustment methods.
OVERVIEW
The drive itself an independent memory device. THe drive is composed of a media clamp rotating mechanism, a
head positioning mechanism and an eject mechanism. All positioning operations, excluding insertion and
removal of diskettes, are controlled by the internal guide mechanism. Closing the front door causes the media
clamp mechanism to operate. Two operations are performed in the following order:
a)
The diskette is centered.
b)
The diskette is clamped and retained between the spindle and the hub.
The spindle and hub rotates at 300 r.p.m. through a closed/loop control circuit employing a D.C
motor/tachometer. It is important that the relationship between the head and the media is maintained correctly
during operation. For this purpose, a pressure pad is used to hold and press down the media (about 12g) from the
opposite side of the head. This head assembly is coupled by a metal band to a four base stepping motor which
performs the track positioning. One step of the stepping motor corresponds to a 1/2 track movement. The control
circuit on the logic board selects the direction and number of steps to the desired track.
The Read/Write head uses a glass-bonded, ferrite/ceramic head. Track-to-track erasing is
accomplished by the straddle erase method. The surface of the Read/Write head is mirrorground to minimize wear of the head and media. Also, the head is designed in such a way that
the maximum signal can be obtained from the media surface.
The spindle drive motor operates on 12 VDC and turns the spindle, through a belt drive, at
300 revolutions per minute. The speed of the drive motor is controlled by a feedback signal
from a tachometer, which is housed in the drive motor assembly. The feedback signal controls
a servo amp that supplies the 12 VDC drive current.
FLASH CODE
The 1541, upon power-up, goes through its own internal diagnostic. If an electronic problem is detected, it's
indicated by flash code. The led's will blink a number of times, pause, and then flash again until the problem is
corrected.
Number of flashes
2
3,4
5,6,7,8
Circuitry associated with these components can also cause the failure code. Therefore, it should be suspected as
the next possible defect.
Possible failure
Zero page
DOS ROM's
RAM
1541 CIRCUIT THEORY
All circuit diagrams have been taken from the short board schematic 1540049 unless
otherwise noted. The short board use a 6116 RAM which replaces the four 2114 I.C.s on
the long board. See page 11 for the Read/Write logic differences.
The Power Supply
The input AC voltage is controlled by switch 1 (SW1). Disk circuit protection is provided by fuse 1 (F1). If SW1
is closed, the AC voltage input is applied to the primary winding of transformer one (T1). T1 steps down th AC
input voltage into two smaller AC voltages. The top secondary AC output (approx. 16VRMS) is converted to DC
by the Full Wave Bridge Rectifier CR1. The DC output of CR1 is regulated at 12VDC by VR1. The bottom
secondary AC output of T1 (approx. 9VRMS) is converted to DC by the Full Wave Rectifier CR3. The DC
output of CR3 is regulated at +5VDC by VR2. High frequency filtering is provided by C1 and C3 for the
12VDC supply, and C4, C6 to C9, C22, C27 to C30 for the 5VDC supply. Low frequency filtering is provided
by C17 and C2 for the 12VDC supply, and C5 and C16 for the 5VDC supply.
1541 CIRCUIT THEORY
The Reset Circuit
The output of the exclusive 'or' gate UD3 pin 6 will be "low" until C46 has charged through R25. Once the
voltage across C46 reaches 2 volts, the output of UD3 pin 6 will go "high". This occurs when the disk is powered
on, or a reset pulse is generated by a device connected to the serial bus. The reset pulse on the serial bus interface
is input on, pin 6 of P2 or P3. This "low" to "high" going pulse on pin 6 of UD3 is input to the microprocessors
reset interrupt input. This causes a restart on reset routine to be executed giving control of the disk drive
operation to the Disk Operating System (DOS).
1541 CIRCUIT THEORY
Tracks
Clock Frequency
1
The Clock Circuits
Crystal Y1 outputs a 16Mhz clock signal. THis is input to UD5 on pin 8. UD5 is configured as a ÷ 16 frequency
divider. The output of UD5 pin 12 is a 1 MHz clock signal used as the system clock (Phase 0) for the
microprocessor. UE6 is a programmable counter ( ÷ 16, ÷ 15, ÷ 14, ÷ 13) that outputs a varying frequency clock
used to compensate for the difference in recording area/sector for sectors on inner tracks (Trks 1,2,3) as
compared to sectors on out most tracks (Trks 33,34,35). The area/sector for inner tracks is less than the
area/sector for out most tracks, so the recording clock frequency is increased when writing on inner tracks to
keep the flux density constant. This clock output is on pin 12 of UE6.
Divide By
1-17
1.2307 MHz 13
18-24 1.1428 MHz 14
15-30 1.0666 MHz 15
31-35
MHz 16
1541 CIRCUIT THEORY
Microprocessor Control of RAM and ROM
UB3 and UB4 are 8192 x 8 bit ROMS that store the Disk Operating System (DOS). UB3 resides at memory
locations $C000-$DFFF. UB4 resides at memory locations $E000-$FFFF. UC5 and UC6 decodes the addresses
output from the microprocessor when selecting these ROMS.
UB2 is a 2048 x 8 bit RAM. UB2 resides at memory locations $0000-$07FF. This memory is
used for processor stack operations, general processor housekeeping, use program storage,
and 4 temporary buffer areas. UC5, UC6 and UC7 decode the addresses output from the
processor when selecting RAM.
1541 CIRCUIT THEORY
The Serial Interface
UC3 is a 6522 Versatile Interface Adapter (VIA). Two parallel ports, handshake control, programmable timers,
and interrupt control are standard features of the VIA. Port B signals (PB0-PB7) control the serial interface
driver ICs (UB1 and UA1). CLK and DATA signals are bidirectional signals connected to pins 4 and 5 of P2 and
P3. ANT (Attention) is an input on pin 3 of P2 and P3 that is sensed at PB7 and CA1 of UC3 after being inverted
by UA1. ATNA (Attention Acknowledge) is an output from PB4 of UC3 which is sensed on the data line pin 5
of P2 and P4 after being exclusively "ored" by UD3 and inverted by UB1. UC3 is selected by UC7 pin 7 going
"low" when the proper address is output from the processor. UC3 resides at memory locations $1C00-$1C0F.
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