In June 1998, Collis started the development of a hardware interface that should facilitate the use
of Collis‟ generic test-tool “Conclusion Smartlink” for testing SmartCards and SmartCard
terminals. The result of this effort, the “Conclusion Smartlink Box” has been in use since early
1999.
Because of the rapid development in SmartCard technology, the original hardware no longer meets
the demands placed on it by today‟s market. For example, it is not possible to use the device to
communicate with terminal/card combinations that work at 3V supply voltage, commonly used in
GSM.
Therefore a decision has been made to design a new version of the SmartLink Box that does meet
these demands and is also more flexible and easier to upgrade. This document is the basis for this
new hardware design.
SmartLink Box User Manual
Status: preliminary
2/21
Version: 3.5
Item
Description
LED color
Power On
The presence of supply voltage to the box
green
Card Inserted
A card being fully inserted into the card slot
yellow
Vcc
The presence of supply voltage on the card interface
red
CLK
The presence of a clock signal on the card interface
red
RST
The presence of a RST signal on the card interface 1
red
Card I/O
The presence of activity on the I/O line of the card 2
green
Terminal I/O
The presence of activity on the I/O line of the terminal
2
green
2 FUNCTIONAL DESCRIPTION
The CIB-1894 (Chipcard Interface Box, hereafter referred to as: “the box”) is a microprocessor
controlled interface between Conclusion Smartlink (herafter referred to as: “the driver”) and a
chipcard / terminal that facilitates monitoring and/or modification of the communication between
card and terminal. It is also possible to simulate the behaviour of either a card or a terminal.
The interface should be designed to work with all SmartCards and terminals currently in use and
also –as much as possible- be prepared for future card/terminal combinations, in as far as this is
compatible with the current ISO standards.
2.1 Signalling
The following events / statuses will be signalled by LEDs:
Table 2-1 Signals
2.2 Card/terminal interface, general
The box has three fundamental modes on the card/terminal interface: The Analyse Mode, the
Intercept Mode, and the Cardreader Mode. In Analyse Mode there is a direct connection between
card and terminal and the communication between them is merely monitored. In Intercept Mode,
the communication between the card and the terminal is diverted via the driver, which enables
modification of messages. In Cardreader Mode, all connections between card and terminal are
separated and the card receives all necessary electrical signals from the box itself.
In Analyse and Intercept Mode the box wil automatically determine the frequency of the CLK
signal as soon as the presence of VCC is detected. It will then continuously measure the CLK
frequency and compare it to the previously measured frequency, so as to determine and signal any
changes.
1
The RST LED is on when the RST signal is low, i.e. the card is in Reset.
2
In Analyse Mode these LEDs signal the origin of the communication. In Intercept Mode they show on
which interface the communication is taking place.
SmartLink Box User Manual
Status: preliminary
3/21
Version: 3.5
The following events are automatically tracked and signalled to the driver:
• Insertion and removal of a card (event 0xB1, resp. 0xB0)
• Application and removal of supply voltage (Vcc) (event 0xA1, resp. 0xA0)
• Application of RST to the card (event 0xAF)
• CLK signal stop (event 0xAA)
• CLK signal (re)start (event 0xAB)
• Clockfrequency change (event 0xAC)
• Signaling of a Parity error by card or terminal (event 0xC0)
It will be possible to introduce Parity errors while sending data to the card or the terminal, in order
to analyse the response to this. The result of the Parity check on received characters will be sent to
the driver.
2.2.1 Card/terminal interface, Analyse Mode
In this mode all elektrical signals between the terminal and the card are functionally, though not
physically, connected to eachother. The box will measure the supplyvoltage and clockfrequency
presented by the terminal and determine the communication bitrate based on the clockfrequency
and a divisor, preset by the driver. These parameters can be queried by the driver.
The box receives the data being sent between the terminal and the card and monitors the direction
of this communication. The data received is sent directly to the driver, with information added
about the message originator (card or terminal), possible parity errors and an optional timestamp.
An end-of-message is determined by either a change in the direction of the communication or a
preset timeout.
2.2.2 Card/terminal interface, Intercept Mode
This mode also connects all electrical signals between the terminal and the card, with the exception
of the I/O line. As in Analyse Mode, the box will measure suplyvoltage and clockfrequency and
determine the correct bitrate.
Upon release of the RST line, the box will send a string of characters, preset by the driver, to the
terminal. This string will usually be the same as the ATR of the card that is used. The subsequent
command received from the terminal will be sent to the driver, not the card. The driver will then
send this command, or a modified version of it, to the card. The box will send the answer from the
card to the driver, which then sends it to the terminal, et cetera.
Error signalling on the I/O line, as defined by ISO 7816-3, § 6.1.3, will be detected and signalled to
the driver. The affected byte will be resent. Send Parity errors can be forced from the driver.
This mode is independent of the presence of a card and can therefore be used to completely
simulate the behaviour of a card towards the terminal.
2.2.3 Card/terminal interface, Cardreader Mode
In this mode there is no connection between the card and the terminal. All elektrical signals are
presented to the card by the the box itself. The driver can set the supply voltage, the
clockfrequency and the bitrate divisor. Error signalling on the I/O line, as defined by ISO 7816-3,
§ 6.1.3, will be detected and signalled to the driver. The affected byte will be resent. Send Parity
errors can be forced from the driver.
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