Description
Reference Document
UT36PFD103 SPSC Data Sheet
Document Presently Supplied after NDA is in place
SPSC-EVB GUI User’s Guide
Document Presently Supplied after NDA is in place
UT32M0R500-EVB User’s Manual
https://www.cobhamaes.com/pagesproduct/datasheets/UT32M0R500
_EVB_Users_Guide.pdf
UT32M0R500 ARM M0+
Functional Manual
https://www.cobhamaes.com/pagesproduct/datasheets/UT32M0R500
_Functional_Manual.pdf)
UT32M0R500-EVB to SPSC-EVB API
Downloadable after signing End User License Agreement
SPSC-EVB-GUI Runtime Executable
Downloadable after signing End User License Agreement
Power Management
SPSC-EVB-R0 Evaluation Board
for UT36PFD103 Smart Power Switch Controller
Evaluation Kit User Manual
Cobham.com/HiRel
August 2019
The most important thing we build is trust
FEATURES
8V-36V Power Bus Switching
o Single-Supply Stand-Alone Operation
o Dual-Supply ARDUINO Hosted Operation
5ms VOUT Linear Power-Up Ramp Rate
2.5ms VOUT Linear Power-Down Ramp Rate
o Feature for Commanded Stop and
Overcurrent Limit Fault Trip
2.5A Overcurrent Fault Limit
o 162ms Overcurrent Fault Timeout
5A Short Circuit Fault Threshold
o 500ns Short Circuit eFusing Response
Stand-Alone Operation Requires User Jumper
Wires to ENABLE Operation and Issue RESET#
Command
Full-Feature Operation Achieved with ARDUINO Host
ARDUINO Shield Form Factor
o Host Microcontroller Command & Control of
SPSC Accomplished through I2C SerCom
using PMBus™ Protocol
o Software API available for UT32M0R500-EVB
o (TBD) Software API for ST-NUCLEO L053
EVB
Analog Telemetry Measured by SPSC Available
via PMBus™ Communication Port
o Telemetry: VIN, VOUT, and LOAD Current
Dual-Power FET OR’ing Switch Functionality with
Reverse Current Fault Protection
INTRODUCTION
The Smart Power Switch Controller Evaluation Board SPSC-EVB provides users with a convenient and flexible
platform from which to evaluate the manifold features and functions available with the UT36PFD103 SPSC. The
SPSC-EVB may be operated in single-supply stand-alone form (i.e. without host microcontroller) and in fullfeatured operation when installed as an ARDUINO shield onto a compatible host microcontroller evaluation board.
To facilitate rapid evaluation, Cobham provides software API for the UT32M0R500 Arm M0+ evaluation board to
service the SPSC host controller along with a run-time executable graphical user’s interface (GUI). Refer to the
SPSC_SoftwareUsersGuide.pdf for documentation on GUI operation. Additionally, the UT32M0R500 software API
is available for download on the Cobham Webpage (https://www.cobhamaes.com/pagesproduct/prods-hirel-
arm.cfm) along with an application note detailing how to program the UT32M0R500-EVB.
1 REFERENCE DOCUMENTS
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2 EVALUATION KIT CONTENTS
SPSC-EVB-R0 UT36PFD103 Evaluation Board (1)
ARDUINO Male-Male Jumper Wire (3)
SPSC-EVB-R0-GUI (1 – Download from Cobham Website)
UT32M0R500-SPSC-API (1 –Download from Cobham Website)
SPSC-EVB-R0 Evaluation Kit User Guide (1)
Figure 1a. Stand-Alone SPSC-EVB-R0
Figure 1b. SPSC-EVB-R0 Installed on UT32M0R500-EVB
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TABLE OF CONTENTS
FEATURES ...................................................................................................................................................... 1
Introduction.................................................................................................................................................... 1
1 Reference Documents ............................................................................................................................... 1
2 Evaluation Kit Contents ............................................................................................................................. 2
Table of Contents............................................................................................................................................ 3
3 Evaluation Board (EVB) Configuration ........................................................................................................ 4
4 Test Equipment List .................................................................................................................................. 5
5 Evaluation setup diagram .......................................................................................................................... 5
6 Configuring the SPSC-EVB-R0 for hosted operation..................................................................................... 6
7 Configuring the SPSC-EVB-R0 for STAND-ALONE operation ....................................................................... 17
8 EVB Electrical Schematics ....................................................................................................................... 20
9 EVB Components Bill of Materials (BoM) .................................................................................................. 22
10 EVB Layout Information ..................................................................................................................... 24
11 Revision History ................................................................................................................................. 31
Date ............................................................................................................................................................. 31
Revision ....................................................................................................................................................... 31
Change Description ....................................................................................................................................... 31
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UT36PFD103 SPSC
I_SENSE RESISTOR
VIN
BANANA JACK
VIN RETURN
BANANA JACK
VOUT
BANANA JACK
VOUT RETURN
BANANA JACK
SCHOTTKY CLAMP
SHORT CIRCUIT
CHOKE
ARDUINO SHIELD
CONNECTOR 4x
PMBus / SMBus
ADDRESS SWITCHES
STATUS LEDs
CONFIGURATION
PIANO SWITCHES
OPTIONAL
UT32M0R500-EVB
(Host Controller)
Figure 2. SPSC-EVB-R0 on UT32M0R500-EVB with Labels
3 EVALUATION BOARD (EVB) CONFIGURATION
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Item #
Description
Function/Purpose
1
SPSC-EVB-R0
UT36PFD103 Evaluation Board
2
Differential Output 3.125 Gbps Pattern Generator
(PRBS/XAUI/etc.)
Pulse Pattern Generator for Input
Stimulus
3
Differential input oscilloscope with input analog
bandwidth (BW) ≥8GHz
Oscilloscope for Output Display
4
3 Channel DC Power Supply
DC Power Supply for XPS Evaluation
Board (1.2V, 1.5V, 2.5V)
5
MS Windows Laptop Computer + USB Cable
Platform for SW GUI Operation
6
SMP-to-SMA Cable Assemblies
Test Equipment Interface to SMP
Connectors on Evaluation Board
7
SMA Cables
High-Speed Signal Connections To/From
DUT and Test Equipment
8
DC Banana Plug Power Cables
Evaluation Board DC Power Connections
4 TEST EQUIPMENT LIST
5 EVALUATION SETUP DIAGRAM
Figure 3. Evaluation Equipment Recommendations
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INPUT POWER JACKS
OUT POWER JACKS
10mΩ Sense Resistor
ORing
FET
LOAD
FET
Figure 4. Example Evaluation Platform Setup with Loads
When operating the SPSC-EVB with hosted ARDUINO™ microcontroller base, the full-featured evaluation simply
requires a PC with 16GB RAM and 2.5GHz Quad-core processor (recommended) to operate the GUI, a USB TypeA to Mini-B cable, single channel power supply (36V and 2.5A-5A capable output), banana patch cords and output
load. As seen in Figure 4, Cobham implemented a simple load box to mount the UT32M0R500-EVB and SPSCEVB-R0 and switch resistive loads of 10-ohms, 100-ohms, and a fast-blow fused short to ground.
6 CONFIGURING THE SPSC-EVB-R0 FOR HOSTED OPERATION
Step 1) Determine if you will bypass the ORing FET. As shown in Figure 5, the red shunt is NOT connecting
across the OR DISABLE header. This configuration allows the SPSC to control the ORing FET. When
shunting across this header, the ORing FET source-drain terminals are shorted effectively bypassing the
SPSC control of the PowerFET.
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Figure 5. ORing Bypass Option
SIGNAL
ARDUINO PIN
SCALED FACTOR
µC VIN
A0
(VIN) 26.1 : 1 (µC VIN)
µC VOUT
A1
(VOUT) 26.1 : 1 (µC VOUT)
µC IMON
A2
(IMON) 2 : 1 (µC IMON)
11-12 µC VIN
9-10 µC VOUT
7-8 µC IMON
5-6 N/C
3-4 SDA1
1-2 SCL1
UT36PFD103 SPSC
Figure 6. J10 Shunt Configuration
Step 2) Confirm the appropriate jumper shunts are in place on header J10, as shown in Figure 6. The µC VIN, µC
VOUT, and µC IMON are analog representations of the corresponding telemetry points on the SPSC-EVB.
The SDA1 and SCL1 signals connect the µC multi-function analog/GPIO pins to the SPSC’s redundant
SMBus Data and Clock IO.
Table 1. Analog Telemetry Scaling for µController ADC
Note, the SPSC has an internal 10-bit ADC which also measures these telemetry points and provides the
digitized value on a 2V scale to the host microcontroller via PMBus™ commands. These redundant
analog telemetry points are provided to allow the user to perform the analog telemetry digitization with
the microcontroller if desired. The scale factors provided by the SPSC-EVB-R0 are intended to keep the
maximum analog values to remain <1.6V full-scale.
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SP3T SMBus ADDRESS Switches
Configuration
Piano Switches
Status LEDs
PARITY
OPERATING MODE
MRST_B / RESTART
EN_B / RESTART
4 3 2 1
Figure 7. SMBus Address, Parity, and Configuration Switches
Step 3) There are two switch banks on the SPSC-EVB-R0 to configure SMBus addressing, selecting HOSTED or
STAND-ALONE operation and facilitating certain operational modes when using the evaluation board in
stand-alone mode. When using the SPSC-EVB-R0 in an ARDUINO hosted configuration, the OPERATING
MODE piano switch (SW1.3) must be DOWN. The PARITY piano switch (SW1.4) should be set to create
ODD parity for the ternary SMBus address set by the SP3T switches on SW2. Leaving PARITY switch UP
places the SPSC PARITY input to logic LOW, while depressing SW1.4 in the DOWN position sets PARITY
to logic HIGH. Table 4 provides a cross reference of ternary address decoding with appropriate parity
setting.
As mentioned, the SMBus address inputs on the SPSC are ternary logic. This means each pin supports
three states: LOW, MID, HIGH. The choice of ternary IO was used to provide full 7-bit SMBus addressing
with fewer pins. The SPSC supports PMBus™ plug & play through its implementation of the SMBus
Address Resolution Protocol (ARP). If the SMBus address and parity are invalid or duplicate, the SPSCEVB-GUI will issue an enumeration sequence that informs the host microcontroller to invoke the ARP and
determine which valid terminals are connected to the bus and assign new addresses to terminals that
have an invalid or duplicate address set by the switch bank. The SMBus address switches are read by the
SPSC while in reset, only.
The remaining two piano switches on SW2 are intended for STAND-ALONE operation. EN_B / RESTART
(SW2.1) is provided to implement a commanded output pulsing function, while MRST_B / RESTART
facilitates autonomous retriggering operation when current limit faults are detected. To use the SPSCEVB-R0 in STAND-ALONE operation, SW1.3 must be UP. When operating the SPSC-EVB-R0 in STANDALONE mode, it also runs with a single power supply, drawing its power from the VIN supply and selfregulating the 3V3 supply.
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SIGNAL
SWITCH
DESCRIPTION
STATES
ADDR0
SW1.1
SMBus Address 0
— = LOW
ʘ = MID
+ = HIGH
ADDR1
SW1.2
SMBus Address 1
ADDR2
SW1.3
SMBus Address 2
ADDR3
SW1.4
SMBus Address 3
ADDR4
SW1.5
SMBus Address 4
N/C
SW1.6
No Connect
N/C
SW1.7
No Connect
N/C
SW1.8
No Connect
SIGNAL
SWITCH
DESCRIPTION
STATES
EN_B / RESTART
SW2.1
Restart Operation
via EN_B Input
UP = No Delay on EN_B↑
DOWN = RC Delay Added to EN_B↑
Expected use in Stand-Alone Mode
MRST_B / RESTART
SW2.2
Restart from Current
Fault via MRST_B Input
UP = Output Latched OFF on Current Fault
DOWN = Output Retriggers on Current Fault
Expected use in Stand-Alone Mode
OPERATING MODE
SW2.3
SPSC-EVB Mode of
Operation
UP = Stand-Alone Mode of Operation
DOWN = Hosted Mode of Operation
PARITY
SW2.4
SMBus Address
ODD Parity
UP = Drives Parity input logic LOW
DOWN = Drive Parity input logic HIGH
Expected use in Hosted Mode
Table 2. SP3T Switch SW1 Settings
Table 3. Piano Switch SW2 Settings
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Decimal
Value
Ternary Pins
(LSB->MSB)
Parity
Switch
Decimal
Value
Ternary Pins
(LSB->MSB)
Parity
Switch
16
LLMHM
UP
(Logic 0)
70
LHMHM
UP
17
LLMHH
DOWN
(Logic 1)
71
LHMHH
DOWN
18
LLHLL
DOWN
76
LHHMM
UP
19
LLHLM
UP 77
LHHMH
DOWN
20
LLHLH
DOWN
78
LHHHL
DOWN
21
LLHML
UP 79
LHHHM
UP
22
LLHMM
UP 80
LHHHH
DOWN
23
LLHMH
DOWN
81
HLLLL
UP
24
LLHHL
DOWN
82
HLLLM
UP
25
LLHHM
UP 83
HLLLH
DOWN
26
LLHHH
UP 84
HLLML
UP
27
LMLLL
DOWN
85
HLLMM
DOWN
28
LMLLM
UP 86
HLLMH
DOWN
29
LMLLH
DOWN
87
HLLHL
UP
30
LMLML
DOWN
88
HLLHM
UP
31
LMLMM
UP 89
HLLHH
DOWN
32
LMLMH
UP 90
HLMLL
DOWN
33
LMLHL
DOWN
91
HLMLM
UP
34
LMLHM
DOWN
92
HLMLH
DOWN
35
LMLHH
UP 93
HLMML
UP
36
LMMLL
DOWN
94
HLMMM
UP
37
LMMLM
UP 95
HLMMH
DOWN
38
LMMLH
UP 96
HLMHL
DOWN
39
LMMML
DOWN
98
HLMHH
UP
41
LMMMH
UP 99
HLHLL
DOWN
42
LMMHL
UP 100
HLHLM
UP
43
LMMHM
DOWN
101
HLHLH
DOWN
46
LMHLM
DOWN
102
HLHML
DOWN
47
LMHLH
UP 103
HLHMM
UP
48
LMHML
DOWN
104
HLHMH
UP
49
LMHMM
UP 105
HLHHL
DOWN
50
LMHMH
UP 106
HLHHM
DOWN
51
LMHHL
DOWN
107
HLHHH
UP
52
LMHHM
UP 108
HMLLL
DOWN
53
LMHHH
DOWN
109
HMLLM
UP
54
LHLLL
DOWN
110
HMLLH
UP
56
LHLLH
UP 111
HMLML
DOWN
57
LHLML
DOWN
112
HMLMM
UP
58
LHLMM
DOWN
113
HMLMH
DOWN
59
LHLMH
UP 114
HMLHL
DOWN
60
LHLHL
DOWN
115
HMLHM
UP
61
LHLHM
UP 116
HMLHH
DOWN
62
LHLHH
UP 117
HMMLL
UP
63
LHMLL
DOWN
118
HMMLM
UP
69
LHMHL
UP 119
HMMLH
DOWN
Table 4. SMBus Address and Parity Decoding
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