COBHAM GR-CPCI-GR740 User Manual

GR-CPCI-GR740

Development Board

2017 User's Manual

The most important thing we build is trust

GR-CPCI-GR740

Development Board

User's Manual

GR-CPCI-GR740-UM, 2017, Version 1.7 www.cobham.com/gaisler

GR-CPCI-GR740

Intentionally Blank

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GR-CPCI-GR740

Table of Contents

1 Introduction......................................................................................................................7

1.1 Scope of the Document....................................................................................... 7

1.2 Reference Documents..........................................................................................7

2 Abbreviations................................................................................................................... 8

3 Introduction......................................................................................................................9

3.1 Overview............................................................................................................. 9

3.2 Handling............................................................................................................ 11

4 Board Design.................................................................................................................. 12

4.1 GR740 Processor............................................................................................... 12

4.2 Board Block Diagram........................................................................................13

4.3 Board Mechanical Configuration...................................................................... 14

4.4 Front Panel.........................................................................................................15

4.5 Memory............................................................................................................. 17

4.5.1 SDRAM Memory Interface configuration........................................................ 17

4.5.2 SDRAM SODIMM 48/96 Bit Interface............................................................ 18

4.5.3 PROMIO / Interface configuration....................................................................19

4.5.4 PROMIO / Parallel Flash...................................................................................20

4.5.5 Memory Expansion........................................................................................... 21

4.6 PCI Interface......................................................................................................23

4.6.1 PCI data/address/control bus............................................................................. 27

4.6.2 PCI Clock distribution.......................................................................................28

4.6.3 Arbiter signal distribution..................................................................................32

4.6.4 PCI Interrupts & PCI_HOSTN..........................................................................34

4.6.5 PCI_IDSEL........................................................................................................34

4.6.6 PCI Reset........................................................................................................... 35

4.6.7 33 / 66 MHz PCI Bus Speed..............................................................................35

4.7 Ethernet Interface.............................................................................................. 36

4.8 FPGA for PCI Arbiter & Versaclock Controller................................................38

4.9 Spacewire (LVDS) Interfaces............................................................................39

4.9.1 SPW interface circuit.........................................................................................39

4.9.2 SPW Connectors................................................................................................39

4.10 FTDI Serial to USB Interface............................................................................40

4.11 SPI interface...................................................................................................... 47

4.12 GPIO..................................................................................................................48

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4.13 Bootstrap Signals...............................................................................................51

4.14 Accessory Board Circuits.................................................................................. 51

4.14.1 CAN 2.0 Interfaces............................................................................................52

4.14.1.1 Configuration of Bus Termination.....................................................................53

4.14.2 MIL-STD-1553 Interface.................................................................................. 53

4.14.3 Serial Interface (RS232).................................................................................... 54

4.15 Debug Support Unit Interfaces..........................................................................55

4.16 Other Auxiliary Interfaces and Circuits.............................................................57

4.16.1 Oscillators and Clock Inputs............................................................................. 57

4.16.2 Power Supply and Voltage Regulation.............................................................. 59

4.16.3 Reset Circuit and Button................................................................................... 62

4.16.4 Watchdog...........................................................................................................62

4.16.5 JTAG interface...................................................................................................62

4.17 Heatsink/Fan......................................................................................................63

5 Setting Up and Using the Board...................................................................................64

6 Interfaces and Configuration....................................................................................... 67

6.1 List of Connectors............................................................................................. 67

6.2 List of Oscillators, Switches and LED's............................................................ 79

6.3 List of Jumpers.................................................................................................. 81

7 Change Record...............................................................................................................86

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GR-CPCI-GR740

List of Figures

Figure 3-1: GR-CPCI-GR740 Development Board............................................................................. 9

Figure 4-1: GR740 SOC Block Diagram........................................................................................... 12

Figure 4-2: GR740 Package .............................................................................................................. 12

Figure 4-3: GR-CPCI-GR740 Board Block Diagram........................................................................ 13

Figure 4-4: GR-CPCI-GR740 Board with CPCI Front Panel ........................................................... 14

Figure 4-5: Example of GR style 6U board Mounted in Enclosure.................................................. 15

Figure 4-6: GR-CPCI-GR740 board Front Panel Concept.................................................................15

Figure 4-7: Auxiliary PCB for DIP Switches and front panel GPIO connections..............................16

Figure 4-8: Configuration plugs for 48/96 bit SDRAM memory.......................................................17

Figure 4-9: Configuration plugs installation on bottom side of PCB.................................................18

Figure 4-10: Mezzanine Connector Pin Number Ordering................................................................ 22

Figure 4-11: PCI Interface Configurations.........................................................................................24

Figure 4-12: PCI Peripheral-Host-Bridge Connections..................................................................... 26

Figure 4-13: Connectors for mounting PCI-PCI Configuration Mezzanine......................................26

Figure 4-14: PCI-PCI Configuration Mezzanine Mounted – Note the orientation............................27

Figure 4-15: PCI Clock Distribution.................................................................................................. 31

Figure 4-16: Arbiter Signal Distribution............................................................................................ 33

Figure 4-17: IDSEL Distribution........................................................................................................34

Figure 4-18: PCI_Reset Configuration...............................................................................................35

Figure 4-19: Block diagram of Ethernet GMII/MII Interface (one of 2 interfaces shown)...............37

Figure 4-20: Block Diagram of the Auxiliary FPGA functions.........................................................38

Figure 4-21: SPW flex connection..................................................................................................... 40

Figure 4-22: Block diagram of FTDI Serial/JTAG to USB Interface...............................................47

Figure 4-23: SPI Interface Configuration...........................................................................................48

Figure 4-24: GPIO interface............................................................................................................... 48

Figure 4-25: GR-ACC-GR740 Accessory Board...............................................................................52

Figure 4-26: Block Diagram of the CAN interface............................................................................ 52

Figure 4-27: Transceiver and Termination Configuration (one of 2 interfaces shown).....................53

Figure 4-28: MIL-STD-1553 Transceiver and Transformer circuit .................................................. 54

Figure 4-29: Serial interface............................................................................................................... 54

Figure 4-30: Debug Support Unit connections...................................................................................55

Figure 4-31: Board level Clock Distribution Scheme........................................................................ 58

Figure 4-32: Power Regulation Scheme.............................................................................................61

Figure 4-33: Watchdog configuration.................................................................................................62

Figure 6-1: Front Panel View (pins 1 marked red).............................................................................69

Figure 6-2: PCB Top View................................................................................................................. 82

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Figure 6-3: PCB Bottom View........................................................................................................... 83

Figure 6-4: PCB Top View (Photo).................................................................................................... 84

Figure 6-5: PCB Bottom View (Photo).............................................................................................. 85

List of Tables

Table 1: JP11 individual jumper configuration.................................................................................. 20

Table 2: PCI Arbiter connections for modes 1-4................................................................................ 30

Table 3: SD-CLK Frequency Range Jumper Settings........................................................................ 36

Table 4: GPIO Definitions..................................................................................................................42

Table 5: DIP Switch S3 Definitions....................................................................................................43

Table 6: Default Setting of Jumpers................................................................................................... 56

Table 7: Default Setting of Switches.................................................................................................. 57

Table 8: List of Connectors................................................................................................................ 60

Table 9: J5 USB type Mini AB connector – FTDI Quad Serial Link.................................................62

Table 10: J2a-J2i SPW-DSU, SPW-0 – SPW-7 interface connections(9x)........................................ 62

Table 11: J1A (Top) RJ45 10/100/1000 Mbit/s Ethernet Connector 1............................................... 62

Table 12: J1B (Bottom) RJ45 10/100/1000 Mbit/s Ethernet Connector 0.........................................63

Table 13: J4 PIO Header Pin out........................................................................................................ 63

Table 14: J5 -Header for Front Panel DIP-Switch..............................................................................64

Table 15: J6– UART - Header for UART Accessory board............................................................... 64

Table 16: J7– CAN - Header for CAN Accessory board....................................................................64

Table 17: J8– MIL1553 - Header for MIL1553 Accessory board...................................................... 65

Table 18: Expansion connector J9 Pin-out (see also section 4.5.5)....................................................66

Table 19: J10- SPI Header for User SPI interface.............................................................................. 67

Table 20: J11 ASIC – JTAG Connector..............................................................................................67

Table 21: J12 PCI-Bridge – JTAG Connector.................................................................................... 67

Table 22: J13 FPGA– JTAG Connector............................................................................................. 68

Table 23: J14 POWER – External Power Connector......................................................................... 68

Table 24: J15 POWER – External Power Connector......................................................................... 68

Table 25: J16 SODIMM – 144 pin socket for SDRAM SODIMM – bits 31..0 & 79..64..................69

Table 26: J17 SODIMM – 144 pin socket for SDRAM SODIMM – bits 63..32 & 95..80................70

Table 27: List and definition of Oscillators and Crystals................................................................... 71

Table 28: List and definition of PCB mounted LED's........................................................................71

Table 29: List and definition of Switches...........................................................................................71

Table 30: DIP Switch FP-S3 definition.............................................................................................. 72

Table 31: List and definition of PCB Jumpers................................................................................... 73

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GR-CPCI-GR740

1 Introduction

1.1 Scope of the Document

This document establishes the User's Manual for the activity “GR-CPCI-GR740”
initiated by the European Space Agency under ESTEC contract N/A.

The work has been performed by Cobham Gaisler AB, Göteborg, Sweden.

1.2 Reference Documents

[RD1] "Quad Core LEON4 SPARC V8 Processor, GR740, Data Sheet and User's

Manual",Cobham Gaisler, GR740-UM-DS, available from

http://www.gaisler.com/gr740

[RD2] GR-CPCI-GR740_schematic.pdf, Schematic; provided on CD with the board

[RD3] GR-CPCI-GR740_assy_drawing.pdf, Assembly Drawing; provided on CD with board

[RD4] GRMON2 User Manual, Cobham Gaisler, part of GRMON2 package

[RD5] GR-MEZZ Technical Note , Technical Note about Mezzanine connectors

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GR-CPCI-GR740

2 Abbreviations

ASIC Application Specific Integrated Circuit.

CPCI Compact Peripheral Connect Interface

CPLD Complex Programmable Logic Device

DDR Double Data Rate

DIL Dual In-Line

DSU Debug Support Unit

ESA European Space Agency

ESD Electro-Static Discharge

ESTEC European Space Research and Technology Center

FP Front Panel

GMII Gigibit Media Independent Interface

GPIO General Purpose Input / Output

I/O Input/Output

IP Intellectual Property

LA Logic Analyser

MII Media Independent Interface

MUX Multiplexer

PCB Printed Circuit Board

SOC System On a Chip

SPW Spacewire

TBC To Be Confirmed

TBC To be Confirmed

TBD To Be Defined

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GR-CPCI-GR740

3 Introduction

3.1 Overview

This document describes the GR-CPCI-GR740 Development Board.

This equipment is intended to be used for the functional validation of the Cobham
Gaisler GR740 Processor. Furthermore, this board provides developers with a
convenient hardware platform for the evaluation and development of software for the
GR740 processor.

The GR740 processor is a radiation-hard system-on-a-chip featuring a quad-core fault­tolerant LEON4 SPARC V8 processor, with an 8-port SpaceWire router, PCI
initiator/target interface, CAN 2.0 interfaces and 10/100/1000 Mbit Ethernet interfaces.
This device is further described in [RD1].

The GR-CPCI-GR740 Development Board comprises a custom designed PCB in a 6U
Compact PCI format, making the board suitable for stand-alone bench top development,
or if required, to be mounted in a 6U CPCI Rack, or in a bench-top enclosure.

The principle interfaces and functions are accessible on the front and back edges of the
board, and secondary interfaces via headers on the board.

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Figure 3-1: GR-CPCI-GR740 Development Board

GR-CPCI-GR740

The board contains the following main items as detailed in section 4 of this document:

• GR740 Processor, in LGA 625 package

• CPCI Interface (32 bit) configurable with jumpers for Host or Peripheral operation

• PCI arbiter implemented in a separate FPGA

• Memory

• SDRAM Configurable 48/96 bits wide, PC133-SODIMM

• Parallel Boot flash64 Mbit (16bit wide x 4M or 8bit wide x 8M)

• Memory expansion connector for interface to external devices (16 bit wide Data)

• Power, Reset, Clock and Auxiliary circuits

• Interface circuits required for the features listed below

The interface connectors on the Front edge of the board provide:

• Dual RJ45 10/100/1000 Mbit GMII/MII Ethernet interface (KSZ9021GN)

• 8 port SPW interface (8 x MDM9S)

• SPW Debug Comm. Link (MDM9S)

• 16 bit General Purpose I/O (34 pin 0.1” ribbon cable style connector)

• FTDI Serial to USB interface (FT4232HL with USB-Mini-AB)

The interface connectors on the Back edge of the board provide:

• Compact PCI interface (32 bit, 33/66MHz), configurable for Host or Peripheral slot

• Input power connector : +5V nom. (Range 4.5V to 14.5V)

To enable convenient connection to the interfaces, most connector types and pin-outs
are compatible with the standard connector types for these types of interfaces.

Additionally, on-board headers and components provide access to the following
functions/ features:

• DIP switches for GPIO signal configuration

• LED indicators connected to GPIO signals

• DIP Switch for Bootstrap and PLL interface configuration

• SPI interface user connections on 0.1” header

• JTAG Debug interface

• 4 pin IDE style power connector

• Push Button switch for RESET and toggle switch (on/off) for BREAK

• LED indicators for POWER, ERRORN, DSU Active and GPIO

• Assorted jumpers and Test Points for configuration and Test of the board

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GR-CPCI-GR740

Furthermore, to accommodate the optional/alternative I/O interfaces an accessory board
provides

• Dual MIL-1553 Interface (Transceiver/Transformer and D-sub 9 Male connector)

• Dual CAN Interface (CAN Transceivers and two D-sub 9 Male connectors)

• Two Serial UART (RS232 transceivers and two D-sub 9 female connectors)

• 10 pin 0.1” Header for SPI interface

Debug interface support is demonstrated on the board with support for debugging via
the following interfaces:

• JTAG

• ETH (EDCL)

• SPW (SPW-DCL)

3.2 Handling

ATTENTION : OBSERVE PRECAUTIONS FOR

HANDLING ELECTROSTATIC SENSITIVE DEVICES

This unit contains sensitive electronic components which can be damaged by
Electrostatic Discharges (ESD). When handling or installing the unit observe
appropriate precautions and ESD safe practices.

When not in use, store the unit in an electrostatic protective container or bag.

When configuring the jumpers on the board, or connecting/disconnecting cables, ensure
that the unit is in an un-powered state.

When operating the board in a 'stand-alone' configuration, the power supply should be
current limited to prevent damage to the board or power supply in the event of an over­current situation.

This board is intended for commercial use and evaluation in a standard laboratory
environment, nominally, 20°C. All devices are standard commercial types, intended for
use over the standard commercial operating temperature range (0 to 70ºC).

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GR-CPCI-GR740

4 Board Design

4.1 GR740 Processor

The Cobham Gaisler GR740 processor is a radiation-hard system-on-a-chip featuring a
quad-core fault-tolerant LEON4 SPARC V8 processor, and a set of IP cores connected
through AMBA AHB/APB buses as represented in the figure below and as specified in
[RD1].

This GR740 processor is packaged in a 625-pin, 1mm pitch Ceramic Land Grid Array
package (29 x 29 mm).

The details of the interfaces, operation and programming of the GR740 processor are
given in [RD1].

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Figure 4-2: GR740 Package

Figure 4-1: GR740 SOC Block Diagram

GR-CPCI-GR740

4.2 Board Block Diagram

The GR-CPCI-GR740 Board provides the electrical functions and interfaces as
represented in the block diagram, Figure 4-4.

Note that not all features and interface are available at the same time, and the
configuration of jumpers and connectors plus some programming of registers is required
to access some of the features. The configurable/optional features are marked light­green in the figure above.

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Figure 4-3: GR-CPCI-GR740 Board Block Diagram

FLASH
8/16 bit

FLASH
8/16 bit

MEMORY

GR740

PROCESSOR

GR740

PROCESSOR

GBIT

ETHERNET

GBIT

ETHERNET

GBIT

ETHERNET

GBIT

ETHERNET

6 x SPW

6 x SPW

6 x SPW

6 x SPW

6 x SPW

6 x SPW

8 x SPW

16 x GPIO

(FP HEADER)

16 x GPIO

(FP HEADER)

SPI

(HEADER)

SPI

(HEADER)

16 x DIP

SWITCH + LED

16 x DIP

SWITCH + LED

BOOTSTRAP
DIP SWITCH

+ LED

JTAG

(FTDI-USB)

JTAG

(FTDI-USB)

FRONT PANEL

POWER

CIRCUITS

POWER

CIRCUITS

CLOCKS &

RESET

CIRCUITS

CLOCKS &

RESET

CIRCUITS

PCI

INTERFACE

(32 bit)

PCI

INTERFACE

(32 bit)

SRAM

SOIDMM

48/96 bit

SRAM

SOIDMM

48/96 bit

I/O

EXPANSION

16 bit

I/O

EXPANSION

16 bit

1 x SPW-DSU

1 x SPW-DSU

RESET +

BREAK

PB SWTICH

2 x CAN

2 x CAN

2 x CAN

2 x CAN

2 x CAN

2 x MIL-1553

2 x CAN

2 x CAN

2 x RS232

UART

SECONDARY FRONT PANEL

SDRAM
SOIDMM
48/96 bit

SDRAM
SOIDMM
48/96 bit

22 x GPIO
(HEADER)

22 x GPIO
(HEADER)

GR-CPCI-GR740

4.3 Board Mechanical Configuration

The Main PCB is a 6U Compact PCI format board (233.5 x 160mm) and can be used
'stand-alone' on the bench-top simply using an external +5V power supply, or can be
plugged in to a Compact PCI backplane.

Figure 3-1, shows the board as a stand alone PCB. However, for installation into a
Compact PCI rack, this board is provided with a custom CPCI front panel with the
appropriate connector cut-outs. The board in the standard configuration with the with
CPCI front panel mounted is shown in Figure 4-4.

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Figure 4-4: GR-CPCI-GR740 Board with CPCI Front Panel

GR-CPCI-GR740

As an alternative to the Compact PCI 6U format of the board, this concept allows the
same PCB design to be installed in a Elma Type 33 style to allow convenient bench-top
use of the Unit, in a similar manner to other Cobham Gaisler development boards (e.g.
as shown Figure 4-5).

4.4 Front Panel

The front panel of the GR-CPCI-GR740 Board is conceived as shown in Figure 4-6.

The main front panel of the device contains the connectors, switches and LED's for the
main functions of the board. Additionally, on this panel the second Ethernet and the
Spacewire-DSU connector are included. This panel is a standard 6U x 2 slot wide panel.
A small PCB is required behind the front panel to be able to mount and support the
GPIO switches and connector (Figure 4-7). A second optional 1 Slot wide front panel
connects to a custom accessory board and provides standard connector interfaces for
UART (RS232) MIL-1553, CAN and SPI interfaces.

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Figure 4-6: GR-CPCI-GR740 board Front Panel Concept

GPIO PINS 16x

LED's

ETH

BOOTSTRAP

DIP-SW

FTDI

CAN-0UART0 UART-1 CAN-1 MIL1553

ETH

GPIO LED's 16x

GPIO DIP-SW 16x SPW-D

SPW-1SPW-0

SPW-1SPW-1

SPW-5

SPW-1SPW-6

SPW-1SPW-7

SPW-2

SPW-1SPW-3

SPW-1SPW-4

BREAK

RESET

SPI

Header

Figure 4-5: Example of GR style 6U board Mounted in Enclosure

GR-CPCI-GR740

If the board is to be housed in an enclosure, then this same front-panel layout can be
transferred to the ELMA 33 series front panel layout.

The optional/alternative interfaces are mounted on a separate PCB, as an optional
accessory board, which will require an additional slot in the 6U rack design.

In the enclosure version of the board, since there is not enough front-panel height
available to fit these connectors, this PCB will have to be mounted at the back of the
enclosure, and the ribbon cable appropriately adapted.

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Figure 4-7: Auxiliary PCB for DIP Switches and front panel GPIO connections

GR-CPCI-GR740

4.5 Memory

The memory configuration installed on the board comprises:

• SODIMM socket for SODIMM mounted SDRAM

• 64 Mbit of flash PROM, in Parallel 8/16 bit flash device

4.5.1 SDRAM Memory Interface configuration

The GR-CPCI-GR740 board provides a 96 bit wide SDRAM data interface using two
SODIMM modules.

However, the GR740 processor has various memory operation modes which includes
both full-width (96 bit data) and half-width (48 bit data) operation, and the data/control
bits for the upper 48 data bits of the SDRAM interface are multi-functional pins shared
with the PCI and/or Ethernet_1 interfaces.

In order to accommodate this the GR-CPCI-GR740 board implements a simple scheme
where one of three bridging plugs is to be installed as represented in Figure 4-8.

Install plug on J21 => 48 bit memory + PCI

Install plug on J22 => 48 bit memory + ETH1

Install plug on J23 => 96 bit memory

Figure 4-9 shows the location of the connectors J21, J22, J23 on the bottom side of the

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Figure 4-8: Configuration plugs for 48/96 bit SDRAM memory

GR740

LOWER
SODIMM

J17

PCI interface

UPPER
SODIMM

J16

ETH1

interface

D[31..0] &
D[78..64]

D[63..32] &
D[95..80]

ADDRESS

J22

J21

J23

GR-CPCI-GR740

PCB.

Note: When the Plug-on board is connected, the PCI-MODE and MEMWIDTH signals
are automatically strapped high/low as appropriate. The state of the PCI-MODE and
MEMWIDTH signals is indicated by front-panel LED's.

4.5.2 SDRAM SODIMM 48/96 Bit Interface

The GR740 processor incorporates a 96 bit wide PC-100 SDRAM Data interface (64
bits data plus 32 bits EDAC check bits).

To accommodate this in a flexible way, two 144 pin SDRAM SODIMM sockets are
implemented on board, one socket for the 48 bit memory configuration (lower 32 bits
data plus its corresponding 16 EDAC check bits), a second socket for the upper 32 data
bits plus its corresponding 16 EDAC check bit used in the 96 bit memory configuration.

If 48 bit memory interface is selected, an SODIMM module should be installed in the
upper SODIMM socket (J16).

If 96 bit memory interface is selected, then an SODIMM module should be installed in
the each of the SODIMM sockets (J16 & J17).

Due to the size and configuration of the SODIMM sockets, one socket is mounted on
the top side and the other socket on the bottom side of the board, in a 'mirror image' as
represented in the figure below.

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Figure 4-9: Configuration plugs installation on bottom side of PCB

GR-CPCI-GR740

Note that the height of the SODIMM socket on the bottom side of the
board is approximately 5.2mm. Strictly speaking, the CPCI
specification only allows an envelope of 2.54mm for the component
heights on the bottom side of the board, and the board is therefore not

fully compliant. This is unlikely to cause an actual problem in use,
since the volume required by the bottom side socket is most likely to be 'free air' in any
normal single or dual slot board mounted in the adjacent slot. However, it is necessary
to take care when installing and removing the card from a PCI rack. Do not simply yank
the card out of the rack since this bottom side SODIMM socket will make contact
against the front panel of the adjacent card when you try to slide it out of the rack, and
this may damage the board. YOU MUST NOT TRY TO USE FORCE TO REMOVE
THE CARD! Instead the adjacent card will have to be loosened or removed first in
order to allow the GR-CPCI-GR740 card to be removed.

SDRAM Clock Phase Adjustment

A clock phase shifter circuit is defined to enable an adjustable phase shift of the
SD_CLK phase relation between ASIC and SODIMM module to be performed.

A programmable clock generator circuit based on the IDT Versa clock device
5P49V5943 (or a similar one) is implemented.

This is a flexible device which is controlled via an I2C interface. The automatic
programming of the device requires that an I2C sequencer and parameter storage which
is implemented in the on-board FPGA.

4.5.3 PROMIO / Interface configuration

For the multiplexed PROMIO signals, the GR740 and board supports two base options:

1. Full PROM/IO mode. Set GPIO[15] high and set all JP11 switches to the A-B
position, connect JP6 jumpers and disconnect the peripheral mezzanine from the
board.

2. All peripheral mode. Set GPIO[15] low and set all JP11 switches to the B-C
position, disconnect JP6 jumpers and connect the peripheral mezzanine.

Note: It is possible to also create custom configurations in between these two extremes
by starting with the GR740 in one of these two modes and then reprogram the pin
multiplexing in software during start-up through the GR740's register interface. To

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GR-CPCI-GR740

support this type of usage, the board has individual jumpers in JP11 (as shown in Table

1), JP6 and JP7. When doing this, the user must take into account that some pins are
configured in the opposite state before it has been reprogrammed, and avoid possible
output collisions and logical errors.

JP11 jumper Pin configuration at position AB Pin configuration at position BC

1 PROMIO_ADDR27 UART_TXD0

2 PROMIO_ADDR26 UART_TXD1

3 PROMIO_ADDR25 1553TXA

4 PROMIO_ADDR24 1553TXNA

5 PROMIO_ADDR23 1553RXENA

6 PROMIO_ADDR22 1553TXB

7 PROMIO_ADDR21 1553TXNB

8 PROMIO_ADDR20 1553RXENB

9 PROMIO_ADDR19 SPWDCL_DBG_TXD

10 PROMIO_ADDR18 SPWDCL_DBG_TXS

11 PROMIO_ADDR17 UART_RTSN0

12 PROMIO_ADDR16 UART_RTSN1

13 PROMIO_DATA7 UART_RXD0

14 PROMIO_DATA6 UART_RXD1

15 PROMIO_DATA5 CAN_RX0

16 PROMIO_DATA4 CAN_RX1

17 PROMIO_DATA3 1553RXA

18 PROMIO_DATA2 1553RXNA

19 PROMIO_DATA1 1553RXB

20 PROMIO_DATA0 1553RXNB

21 PROMIO_CEN1 CAN_TX0

22 PROMIO_IOSN CAN_TX1

Table 1: JP11 individual jumper configuration

Note: Revision 1.0 and revision 1.1 board have a limitation with floating address lines.
If for instance, we use all 1553 pins, which means that 1553 signals on the board (JP11
7 and 8) have to be connected to the GR740 pins instead of PROMIO_ADDR 21 and

20. This will leave PROMIO_ADDR 21 and 20 floating, which are connected to the
flash address inputs 21 and 20.

4.5.4 PROMIO / Parallel Flash

This device can be used for Program storage or as a boot device for the board.

This device (Intel/Numonyx/Micron JS28F640J3 Strataflash) provides 64Mbit of Non­Volatile storage, organised as 8M x 8 bits (4M x 16 bits), operating with an I/O voltage
of in the range of 2.7V to +3.3V.

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GR-CPCI-GR740

This device is connected to the following PROMIO pins:

ADDR[24..0]
DATA[15..8] or [15..0]

OEN
WRITEN

CEN0

The J3 series flash devices can be configured for either 8 or 16 bit operation, by means
of a jumper on the board (JP6 pins 11-12). Note: if the PROM width is changed via JP6
pins 11-12 then GPIO[10] should also be set to reflect the correct PROM width.

Programming of these flash chips can be performed using the GRMON2 debug
software.

Note: In order to support both 16-bit and 8-bit mode, GR740.DATA[7:0] is connected
to the Flash device's DQ[15:8] and GR740.DATA[15:8] is connected to the Flash
device's DQ[7:0]. This means that CFI read data and commands need to be byte­swapped in 16-bit mode. The GRMON2 debug monitor does this automatically but this
needs to be taken into account for Flash routines implemented in software running on
the GR740.

To allow the User to prevent the contents of the flash memory from being overwritten
under software control, the Write-Protect pin can be tied to DGND by installing the
jumper JP6 pin 1-2.

Under certain circumstances, it may be desirable to inhibit the operation of the Flash
PROM (e.g. if system booting and program loading via Spacewire RMAP protocol is
required instead, or if an external MRAM/PROM is installed on the memory expansion
connector, or if the PROMIO pins are to be used for their alternate Interface functions).
To facilitate this, a Jumper JP6 pin 3-4 is provided which connects/disconnects the
ROMSN0 pin of the GR740 to the Chip Enable pin of the flash Prom. In normal
operation, to boot from this flash prom, the jumper (JP6 pin 3-4) should be installed. To
inhibit the operation of the flash prom, the jumper should be removed.

4.5.5 Memory Expansion

The GR740 processor does not support the addition of SRAM memory.

However, the following memory bus signals are connected to a 120 pin AMP connector
(AMP 5-177984-5), J9:

DATA[15..0]
ADDR[27..0]

WRITEN
READ

OEN
IOSN

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GR-CPCI-GR740

CEN[1..0]

BRDYN
EXP_CLK

RESETN

This connector and these signals makes it feasible for users to define peripherals
mapped in the processor I/O space and to implement mezzanine boards which could be
connected to this Development Board in a similar manner to the other GR Development
Boards.

Note: The pins ADDR[27..16] and DATA[7..0], CEN1 and IOSN can have alternative
pin functions depending how the internal registers of the GR740 and board is
configured. The signals which are present on this connector will therefore depend on
how these pins of the GR740 are configured.

Note: The EXP_CLK signal can be used to provide a Clock to circuits on the
Mezzanine. Depending on the configuration required, this connector pin can be
connected to either the MEM_EXTCLK or SD_CLK with a zero-ohm resistor soldered
to the board to either R246 (default) or R247.

Figure 4-10 shows the pin numbering scheme as implemented on the expansion
connector.

Please note that this pin ordering on this connector does not match exactly the pin
ordering which you will find on the Tyco part datasheets for the Mezzanine board
mating connectors. The reason for this is explained in more detail in the Technical Note,
[RD5].

Therefore please take care when designing your own mezzanine boards to take account
of this pin ordering.

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Figure 4-10: Mezzanine Connector Pin Number Ordering

GR-CPCI-GR740

If there is any confusion, or you have any doubts, please do not hesitate to contact

[e-mail]. Additional dimensional data or Gerber layout information can be

provided, if required to aid in the layout of the User's mezzanine board.

4.6 PCI Interface

The GR740 processor incorporates a 33MHz/66MHz/32 bit interface and is capable of
being configured to be installed in either the SYSTEM slot (HOST) or in
PERIPHERAL slots (GUEST).

In order to ensure a compliant PCI signal drive on the CPCI backplane, the GR740
processor will require a PCI-PCI bridge circuit on board acting between the GR740 and
the Backplane.

The PCI-PCI Bridge is the Texas Instruments, PCI2060, which fully Supports PCI Local
Bus Specification Revision 2.3 and PCI-to-PCI Bridge Specification, Revision 1.1. and
is attractive due to its easy availability.

There is also a desire to also be able to test the operation of the GR740 processor with
direct connection to the backplane. Therefore 4 configurations are to be supported with
this board, as represented conceptually in Figure 4-11:

1. GR740 as Host connected to primary side of PCI-PCI Bridge and from there to
Backplane

2. GR740 as Peripheral to secondary side of PCI-PCI Bridge and from there to
Backplane

3. GR740 as Host connected directly to Backplane

4. GR740 as Peripheral connected directly to Backplane

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GR-CPCI-GR740

These multiple configurations create rather a problem for a 'clean' implementation since
a method has to be implemented to connect/disconnect and re-arrange the PCI interface
signals so that all these configuration can be accommodated.

The solution is represented in block diagram form in Figure 4-12. Four sets of signals
are identified: PCI-X (J42-Processor), PCI-Y (J27-backplane), PCI-P (J25-Bridge
primary Side) and PCI-S (J26-Bridge Secondary side). Different plug-on PCB's are
necessary to appropriately connect these sets of signals. These PCB's are simple,
without additional active components (only a few pull-up/pull-down resistors). There
exists the possibility that these PCB's can conveniently provide measurement/LA test­points for the PCI signals which could be an advantage.

The plug-on board mounts on the bottom side of the PCB in order to provide the most
convenient signal routing and layout (Figure 4-13). Note: These mezzanine connectors
are not 'keyed', although there is a visual hint whereby the pin 1 of the connectors is
marked by the diagonal corner. Ensure that the PCI-PCI Mezzanine is fitted as shown in
Figure 4-14.

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Figure 4-11: PCI Interface Configurations

GR740

GR740

PCI-PCI

Bridge

BACKPLANE

BACKPLANE

GR740 HOST, THRU BRIDGE

1

SECONDARY

PRIMARY

GR740

GR740

PCI-PCI

Bridge

BACKPLANE

BACKPLANE

GR740 PERIPHERAL, THRU BRIDGE

2

SECONDARY

PRIMARY

GR740

GR740

PCI-PCI

Bridge

BACKPLANE

BACKPLANE

GR740 direct to backplane3

SECONDARY

PRIMARY

4