COBHAM GR712RC Quick Start Manual

GR712RC

Dual-Core LEON3FT SPARC V8 Processor.

2018 User's Manual The most important thing we build is trust

Quick Start Guide for GR712RC-BOARD

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Table of Contents

1. Introduction ............................................................................................................................. 3

1.1. Overview ...................................................................................................................... 3

1.2. References .................................................................................................................... 3

2. Board Configuration .................................................................................................................. 4

2.1. Overview ...................................................................................................................... 4

2.2. Clock Sources ................................................................................................................ 4

2.3. I/O Switch Matrix .......................................................................................................... 5

2.4. UART .......................................................................................................................... 6

2.5. PROM .......................................................................................................................... 6

3. GRMON hardware debugger ...................................................................................................... 7

3.1. Overview ...................................................................................................................... 7

3.2. Debug-link alternatives .................................................................................................... 7

3.2.1. Connecting via the FTDI USB/JTAG interface .......................................................... 7

3.2.2. Connecting via SpaceWire RMAP interface .............................................................. 7

3.3. First steps ..................................................................................................................... 7

3.4. Connecting to the board .................................................................................................. 8

4. Software ................................................................................................................................ 15

4.1. Overview .................................................................................................................... 15

4.2. Bare C Cross-Compiler System ....................................................................................... 15

4.2.1. Overview .......................................................................................................... 15

4.2.2. Compiling with BCC .......................................................................................... 15

4.2.3. Running and debugging with GRMON .................................................................. 16

4.3. RTEMS Real Time Operating System .............................................................................. 17

4.3.1. Overview .......................................................................................................... 17

4.3.2. Installing RCC ................................................................................................... 17

4.3.3. Building an RTEMS sample application ................................................................. 17

4.3.4. Running and debugging with GRMON .................................................................. 18

4.4. MKPROM2 ................................................................................................................. 19

4.4.1. Overview .......................................................................................................... 19

4.4.2. Usage of MKPROM2 ......................................................................................... 19

4.5. VxWorks ..................................................................................................................... 20

4.5.1. Overview .......................................................................................................... 20

5. Frequently Asked Questions / Common Mistakes / Know Issues ...................................................... 21

5.1. Clock gating ................................................................................................................ 21

5.2. GRMON issues ............................................................................................................ 21

5.3. Clock problems ............................................................................................................ 21

5.4. Switch Matrix Configuration Problems ............................................................................. 21

5.5. GPIO .......................................................................................................................... 21

5.6. SDRAM configuration ................................................................................................... 21

5.7. Multiprocessor & legacy support ..................................................................................... 21

5.8. Interrupts ..................................................................................................................... 22

5.9. GRMON Debug Link Limitations .................................................................................... 22

5.10. MIL-1553 .................................................................................................................. 22

5.11. CAN multiplexing ....................................................................................................... 22

5.12. Concurrent CAN and Ethernet ....................................................................................... 22

5.13. Hardware behavior at CPU reset and power management ................................................... 23

6. Support ................................................................................................................................. 24

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1. Introduction

1.1. Overview

This document is a quick start guide for the GR712RC Development Board. The purpose of this document is to get users quickly started using the board. For a complete description of the board please refer to the GR712RC Development Board User Manual. The GR712RC system-on-chip is described in the GR712RC User Manual. This quick start guide does not contain as many technical details and is instead how-to oriented. However, to make

the most of the guide the user should have glanced through the aforementioned documents and should ideally also be familiar with the GRMON debug monitor.

1.2. References

Table 1.1. References

RD-1 GR712RC Development Board User Manual RD-2 GR712RC User Manual [http://gaisler.com/doc/gr712rc-usermanual.pdf] RD-3 GR712RC Data Sheet [http://www.gaisler.com/doc/gr712rc-datasheet.pdf] RD-4 GRMON User's Manual [http://www.gaisler.com/doc/grmon3.pdf] RD-5 RTEMS homepage [http://www.rtems.org] RD-6 RTEMS Cross Compilation System (RCC) [http://www.gaisler.com/index.php/products/op-

erating-systems/rtems] RD-7 RCC User's manual [http://gaisler.com/anonftp/rcc/doc] RD-8 Cobham Gaisler RTEMS driver documentation [http://gaisler.com/anonftp/rcc/doc] RD-9 GRTOOLS homepage [http://www.gaisler.com/index.php/downloads/grtools] RD-10 Bare C Cross-Compilation System [http://www.gaisler.com/index.php/products/operat-

ing-systems/bcc] RD-11 BCC User Manual [http://www.gaisler.com/doc/bcc2.pdf] RD-12 MKPROM2 User Manual [http://gaisler.com/doc/mkprom.pdf]

The referenced documents can be downloaded from http://www.gaisler.com.

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2. Board Configuration

2.1. Overview

The primary source of information for board configuration is the GR712RC Development Board User Manual. The board requires some hardware configuration to fit with the customer requirements. In particular, the number of the GR712RC-BOARD's processor I/O pins limits the simultaneously available connections to external interfaces. To overcome this limitation, the SoC features an internal switch matrix, and a set of jumpers must be configured accordingly to route the signals to the appropriate headers on the board. The internal switch matrix is configured by enabling the respective interfaces via software. Additionally, clock selection might need to be configured by a set of jumpers and possibly the insertion of custom oscillators.

Figure 2.1. GR712RC-BOARD default configuration as delivired

2.2. Clock Sources

The minimum requirement in order for the board to work and to be able to connect to it, is that the clock sources are properly configured. The 80 MHz oscillator in socket X2 provided by default with the board is connected to

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the system clock input through the JP84 jumper in the default configuration 2-3. The on-board soldered 48 MHz oscillator can be used instead by positioning the JP84 jumper on pins 1-2. Alternatively a custom oscillator can be installed in X2.

The SpaceWire clock is, by default, driven by an on board additional 100 MHz oscillator. If the user wants to use the system clock configured in the paragraph above as the source of the SpaceWire clock, then jumper JP88 must be inserted and the oscillator in socket X5 must be removed.

Refer to Section 2.14 of [RD-1] for further information about oscillators and clock inputs and more information about the system and SpaceWire clock.

Once the external clock sources are selected, further clock configuration can be done in software. The SpaceWire external clock source can be used as 1X, 2X or 4X, or the external system clock can be used in its place. This selection is done by configuring the SoC's General Purpose Register (GPREG). At reset the 1X SpaceWire clock received from the board is used internally.

For in depth information about configuring the SpaceWire and MIL-STD-1553 clocks through the GPREG, please refer to Chapter 3 and Chapter 13 of [RD-2].

2.3. I/O Switch Matrix

To overcome the limitation on the number of SoC pins, an internal switch matrix selects the input/output signals to connect to the pad. Additionally the chip I/O pins are connected to the board's I/O ports through an array of jumpers. One UART and two SpaceWire interfaces are routed independently of the internal switch matrix and the jumpers JP3 through JP66. In the default position A of jumpers JP3 through JP66, all multiplexed switch matrix signals are connected to the board's GPIO pins.

Six basic example configurations are provided to respond to typical use cases, as seen in Table 2.1. To use one of these configurations, the user has to insert jumpers JP3 through JP66 in the position described in the table. Refer to [RD-1] and GR712RC Development Board Schematic for more information on signal and GPIO configuration.

Table 2.1. Typical configurations

Cfg. description I/O enabled

Jumper position

CPU for GEO applications

UART0, UART1, UART2, UART3, UART4, UART5 SpaceWire-0, SpaceWire-1, SpaceWire-2, SpaceWire-3, SpaceWire-4, SpaceWire-5 Mil-Std-1553-A, Mil-Std-1553-B SPI I2C

CPU for TMTC applications UART0, UART1, UART2, UART3

SpaceWire-0, SpaceWire-1, SpaceWire-2, SpaceWire-3 SDRAM with optional Reed-Solomon CCSDS/ECSS TC & TM

CPU for LEO applications UART0, UART1, UART2, UART3, UART4, UART5

SpaceWire-0, SpaceWire-1 SDRAM with optional Reed-Solomon ASCS16 CAN-A, CAN-B SLINK I2C

Instrument Controller, type A UART0, UART1, UART2, UART3, UART4, UART5

SpaceWire-0, SpaceWire-1 SDRAM with optional Reed-Solomon CAN-A, CAN-B SLINK I2C

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Cfg. description I/O enabled

Jumper position

Instrument Controller, type B UART0, UART1, UART2, UART3, UART4, UART5

SpaceWire-0, SpaceWire-1, SpaceWire-2, SpaceWire-3 SDRAM with optional Reed-Solomon Ethernet SPI I2C

Once the board's jumpers are properly connected, the internal switch matrix must be driven by a set of enabling conditions. It is important to note that to obtain a proper functioning system, the I/O interfaces of the required configurations have to be enabled or clock ungated by software. See Chapter 2 and Table 9 of [RD-2] for further details on the switch matrix.

The I/O matrix is not limited to these pre-defined configurations. Jumpers can be custom configured according to the user requirements. See Section 2.4 of [RD-1] for further details.

2.4. UART

Jumpers JP1 and JP2 are used to select the output standard of the UART0 and UART1 interfaces between RS232 and RS422, and to route the signals to the J1 and J16 connectors respectively. In the default configuration the interfaces are connected to the J1 connectors UART-0 and UART-1 using the RS232 standard. While UART0 is not affected by the internal switch matrix, UART1 Rx is multiplexed and JP3 must be set to 3-4 in order to use it. Refer to the GR712RC Development Board Schematic for more information on how to configure UART0 and UART1 to use the RS422 standard.

2.5. PROM

The PROM width and PROM EDAC conditions are set by the state of the GPIO[3] and GPIO[1] pins at power up of the Processor. These pins are provided with pull-down resistors to set the default mode to 8 bit with no EDAC. If EDAC operation of the Flash PROM is desired, then jumper JP85 should be installed, to pull-up GPIO[1].

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3. GRMON hardware debugger

3.1. Overview

GRMON is a debug monitor used to develop and debug GRLIB/LEON systems. The CPU and its peripherals are accessed on the AMBA bus through a debug-link connected to the PC. GRMON has GDB support which makes C/C++ level debugging possible by connecting GDB to the GRMON's GDB socket. With GRMON one can for example:

• Inspect LEON and peripheral registers

• Upload applications and/or program the FLASH

• Control execution flow by starting applications (run), continue execution (cont), single-stepping (step), inserting breakpoints/watchpoints (bp) etc.

• Inspect the current CPU state listing the back-trace, instruction trace and disassemble machine code.

The first step is to set up a debug link in order to connect to the board. The following section outlines which debug interfaces are available and how to use them on the GR712RC Development Board, after that a basic first inspection of the board is exemplified.

Several of the SoC's peripherals may be clock gated off. GRMON will enable all clocks if started with the flag cginit. Within GRMON, the command grcg enable all will have the same effect.

GRMON is described on the homepage [http://www.gaisler.com/index.php/products/debug-tools] and in detail in [RD-4].

3.2. Debug-link alternatives

3.2.1. Connecting via the FTDI USB/JTAG interface

Please see GRMON User's Manual for how to set up the required FTDI driver software. Then connect the PC and the board using a standard USB cable into the USB-mini J12 USB-JTAG connector and issue the following command:

grmon -ftdi

3.2.2. Connecting via SpaceWire RMAP interface

GRMON has support for connecting to boards with SpaceWire interfaces as long as the SpaceWire has RMAP and automatic link start. An Ethernet to SpaceWire bridge (GRESB) is required to tunnel SpaceWire packets from the Ethernet network over to SpaceWire.

Please see the [RD-4] for information about connecting through a GRESB and optional parameters. Connect the GRESB SpW0 connector and the GR712RC-BOARD's J3 (SPW-0) or J4 (SPW-1) connector, then issue the following command:

grmon -gresb

3.3. First steps

The previous sections have described which debug-links are available and how to start using them with GRMON. The subsections below assume that GRMON, the host computer and the GR712RC-BOARD board have been set up so that GRMON can connect to the board.

When connecting to the board for the first time it is recommended to get to know the system by inspecting the current configuration and hardware present using GRMON. With the info sys command more details about the system is printed and with info reg the register contents of the I/O registers can be inspected. Below is a list of items of particular interest:

• AMBA system frequency is printed out at connect, if the frequency is wrong then it might be due to noise in auto detection (small error). See -freq flag in [RD-4].

• Memory location and size configuration is found from the info sys output. If the board has both SRAM and SDRAM interfaces, SDRAM can be mapped at the SRAM base address using the -nosram option of GRMON. See [RD-4] for further details.

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• The GR712RC has a clock-gating unit which is able to disable/enable clocking and control reset signals. Clocks must be enabled for all cores that LEON software or GRMON will be using. The grcg command is described in [RD-4].

3.4. Connecting to the board

In the following example the FTDI debug-link is used to connect to the board. The auto-detected frequency, memory parameters and stack pointer are verified by looking at the GRMON terminal output below.

daniel@daniel:~$ grmon -ftdi

GRMON2 LEON debug monitor v2.0.35 professional version

Parsing -ftdi

Commands missing help: debug datacache

JTAG chain (1): GR712RC Detected system: GR712RC Detected frequency: 80 MHz

Component Vendor LEON3-FT SPARC V8 Processor Aeroflex Gaisler LEON3-FT SPARC V8 Processor Aeroflex Gaisler JTAG Debug Link Aeroflex Gaisler GR Ethernet MAC Aeroflex Gaisler SatCAN controller Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler AMBA Wrapper for Core1553BRM Aeroflex Gaisler CCSDS Telecommand Decoder Aeroflex Gaisler CCSDS Telemetry Encoder Aeroflex Gaisler SLINK Master Aeroflex Gaisler Memory controller with EDAC Aeroflex Gaisler AHB/APB Bridge Aeroflex Gaisler LEON3 Debug Support Unit Aeroflex Gaisler AHB/APB Bridge Aeroflex Gaisler OC CAN AHB interface Aeroflex Gaisler Generic FT AHB SRAM module Aeroflex Gaisler Generic UART Aeroflex Gaisler Multi-processor Interrupt Ctrl. Aeroflex Gaisler Modular Timer Unit Aeroflex Gaisler SPI Controller Aeroflex Gaisler CAN Bus multiplexer Aeroflex Gaisler General Purpose Register Aeroflex Gaisler ASCS Master Aeroflex Gaisler General Purpose I/O port Aeroflex Gaisler General Purpose I/O port Aeroflex Gaisler AMBA Wrapper for OC I2C-master Aeroflex Gaisler Clock gating unit Aeroflex Gaisler AHB Status Register Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Timer Unit with Latches Aeroflex Gaisler

Use command 'info sys' to print a detailed report of attached cores

grmon2> info sys cpu0 Aeroflex Gaisler LEON3-FT SPARC V8 Processor AHB Master 0 cpu1 Aeroflex Gaisler LEON3-FT SPARC V8 Processor AHB Master 1 ahbjtag0 Aeroflex Gaisler JTAG Debug Link AHB Master 2 greth0 Aeroflex Gaisler GR Ethernet MAC AHB Master 3

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COBHAM GR712RC Quick Start Manual

Specifications and Main Features

Frequently Asked Questions

User Manual