CMO V546H1-LH2 Specification

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TFT LCD Approval Specification

MODEL NO.: V546H1 - LH2

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Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

Approval

Customer:

Approved by:

Note:

TV Product Marketing & Management Div

Approved By

Chao-Chun Chung

Reviewed By

QA Dept. Product Development Div.

Hsin-Nan Chen WT Lin

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

Prepared By

LCD TV Marketing and Product Management Div.

CY Chang Trina Lee

1

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Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

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CONTENTS -

REVISION HISTORY ................................................................................................................................4

1. GENERAL DESCRIPTION................................................................................................................... 5

1.1 OVERVIEW................................................................................................................................... 5

1.2 FEATURES .................................................................................................................................... 5

1.3 APPLICATION............................................................................................................................... 5

1.4 GENERAL SPECIFICATI0NS ....................................................................................................... 5

1.5 MECHANICAL SPECIFICATIONS............................................................................................... 5

2. ABSOLUTE MAXIMUM RATINGS....................................................................................................... 6

2.1 ABSOLUTE RATINGS OF ENVIRONMENT ............................................................................... 6

2.2 ELECTRICAL ABSOLUTE RATINGS.......................................................................................... 7

3. ELECTRICAL CHARACTERISTICS.................................................................................................... 8

3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)............................................................................................. 8

3.2 BACKLIGHT UNIT..................................................................................................................... 11

4. BLOCK DIAGRAM OF INTERFACE ................................................................................................. 15

4.1 TFT LCD MODULE..................................................................................................................... 15

5 .INPUT TERMINAL PIN ASSIGNMENT............................................................................................. 16

5.1 TFT LCD Module......................................................................................................................... 16

5.2 BACKLIGHT UNIT..................................................................................................................... 19

5.3 INVERTER UNIT ........................................................................................................................ 19

5.4 BLOCK DIAGRAM OF INTERFACE ......................................................................................... 21

5.5 LVDS INTERFACE...................................................................................................................... 22

5.6 COLOR DATA INPUT ASSIGNMENT........................................................................................ 23

6. INTERFACE TIMING .......................................................................................................................... 24

6.1 INPUT SIGNAL TIMING SPECIFICATIONS ............................................................................. 24

6.2 POWER ON/OFF SEQUENCE .................................................................................................... 26

7. OPTICAL CHARACTERISTICS......................................................................................................... 27

7.1 TEST CONDITIONS.................................................................................................................... 27

7.2 OPTICAL SPECIFICATIONS ...................................................................................................... 27

8. DEFINITION OF LABELS................................................................................................................... 31

8.1 CMO MODULE LABEL.............................................................................................................. 31

9. PACKING ............................................................................................................................................. 32

9.1 PACKING SPECIFICATIONS ..................................................................................................... 32

9.2 PACKING METHOD................................................................................................................... 32

10. PRECAUTIONS................................................................................................................................. 34

10.1 ASSEMBLY AND HANDLING PRECAUTIONS...................................................................... 34

10.2 SAFETY PRECAUTIONS.......................................................................................................... 34

10.3 SAFETY STANDARDS ............................................................................................................. 34

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11. MECHANICAL CHARACTERISTIC................................................................................................. 35

Appendix – TWO Wire BUS INTRODUCTION ..................................................................................... 37

A.1 PIN ASSIGNMENT..................................................................................................................... 37

A.2 I2C BUS APPLICATION NOTE.................................................................................................. 37

A.3 TWO WIRE BUS DEVICE ADDRESS ....................................................................................... 37

A.4 TWO WAY TO CONTROL THE TWO WIRE BUS .................................................................... 38

A.5 TWO WIRE BUS COMMAND TABLE ...................................................................................... 39

A.6 TWO WIRE BUS REQUIREMENT............................................................................................ 43

A.7 THE TWO WIRE BUS SEQUENCE ........................................................................................... 44

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REVISION HISTORY

Version Date

Ver 2.5 Aug. 10, 09’ All All Approval Specification Ver 2.5 was first issued.

Page

(New)

Section Description

Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

Approval

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V546H1-LH2 is a 54.6” TFT Liquid Crystal Display module with 22-CCFL Backlight unit and 2ch-LVDS

interface. This module supports 1920 x 1080 HDTV format and can display true 1.073G colors

(8bit+FRC/color). The inverter module for backlight is built-in.

1.2 FEATURES

- High brightness (500nits)

- High contrast ratio (4000:1)

- Fast response time (Gray to Gray typical 4.5ms)

- High color saturation (72% NTSC)

- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

- DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Optimized response time for 120 Hz frame rate

- Ultra wide viewing angle: Super MVA technology

1.3 APPLICATION

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Model No.: V546H1-LH2

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- Standard Living Room TVs.

- Public Display Application.

- Home Theater Application.

- MFM Application.

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note
Active Area 1209.6(H) x 680.4(V) (54.6” diagonal) mm
Bezel Opening Area 1217.6 (H) x 688.4 (V) mm
Driver Element a-si TFT active matrix - ­Pixel Number 1920x R.G.B. x 1080 pixel ­Pixel Pitch(Sub Pixel) 0.21(H) x 0.63(V) mm ­Pixel Arrangement RGB vertical stripe - ­Display Colors 1.073G (8bit+FRC/color) color ­Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to

change this feature.

Anti-Glare coating (11% Low Haze)

Hardness (3H)

- (2)

(1)

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) 1266.1 1267.6 1269.1 mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

Vertical (V) 737.2 738.4 739.6 mm
Depth (D) 38.5 40 41.5 mm

Weight - 20500 - g -

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

NOP

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Model No.: V546H1-LH2

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Value

Min. Max.

±X, ±Y 30

±Z

- 1.0 G (4), (5)

NOP

­30

Unit Note

G (3), (5)

(a) 90 %RH Max. (Ta 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in final product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in final product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

the module would not be twisted or bent by the fixture.

Љ

Relative Humidity (%RH)

100

90

80

60

Operating Range

40

20

10

Storage Range

Temperature (ºC)

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

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Model No.: V546H1-LH2

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Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.5 V

Logic Input Voltage VIN -0.3 3.6 V

Value

Unit Note

(1)

2.2.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage VW

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

Value

Min. Max.

Ё

3000 V

Unit Note

RMS

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3. ELECTRICAL CHARACTERISTICS

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Model No.: V546H1-LH2

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3.1 TFT LCD MODULE

(Ta = 25 ± 2 ºC)

Parameter Symbol

Power Supply Voltage VCC

Rush Current I

White Pattern

Power Supply
Current

Black Pattern

Vertical Stripe

Differential Input High
Threshold Voltage
Differential Input Low

LVDS
interface

Threshold Voltage

Common Input Voltage VCM

Differential input voltage |VID|

Min. Typ. Max.

10.8 12 13.2 V (1)

RUSH

Ё

Ё

Ё

-

V

V

LVT H

LVT L

+100

1.0 1.2 1.4 V

100

Ё

ЁЁЁЁ

ЁЁЁЁ

Ё

Value

Unit Note

Ё

1.7

1.7

2.6 3.1 A

Ё

Ё

5.2 A (2)

Ё

Ё

Ё

-100

A

A

mV

mV

(3)

(4)

Ё

600

mV

Ё

Terminating Resistor R

Input High Threshold
CMOS
interface

Voltage

Input Low Threshold

Voltage

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

V

V

T

IH

IL

2.7

0

100

Ё

Ё

Ё

3.3 V

0.7 V

ohm

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+12V

R1
1K

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Q1

Si4485D

FUSE

Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

Approval

C3

1uF

Vcc

(LCD Module Input)

VR1

(Low to High)

(Control Signal)

SW

R2

1K

47K

Q2

2N7002

C1

0.01

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

GND

470us

Note (3) The specified power supply current is under the conditions at Vcc = 12V, Ta = 25 ± 2 ºC, fv = 60 Hz,

whereas a power dissipation check pattern below is displayed.

a. White Pattern

Active Area

9

b. Black Pattern

Active Area

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c. Vertical Stripe Pattern

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Model No.: V546H1-LH2

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Active Area

Note (4) The LVDS input characteristics are as follows:

R

G

R

B

G

R

B

G

R R

G

B

B

B

B

R

R

R

G

G

G

G

B

B

B

B

R

R

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3.2 BACKLIGHT UNIT

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Model No.: V546H1-LH2

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3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (

Parameter Symbol

Min. Typ. Max.
Lamp Input Voltage VL - 1440 - V
Lamp Current IL 4.5 5.0 5.5 mA

Lamp Turn On Voltage VS

- - 3155 V

- - 2425 V

Value

Ta = 25 ± 2 ºC)

Unit Note

-

RMS

RMS

(2), Ta = 0 ºC

RMS

(2), Ta = 25 ºC

RMS

(1)

Operating Frequency FL 30 55 80 KHz (3)
Lamp Life Time LBL 50,000 - - Hrs (4)

3.2.2 INVERTER CHARACTERISTICS (

Parameter Symbol

Total Power Consumption P

- 160 175 W (5) ,(6) IL =5.0mA

255

Ta = 25 ± 2 ºC)

Val ue

Min. Typ. Max.

Unit Note

Power Supply Voltage VBL 22.8 24 25.2 VDC
Supply Voltage Difference VD - - 1 VDC (7)
Power Supply Current IBL - 6.67 7.3 A Non Dimming
Input Ripple Noise - - - 912 mV

VBL=22.8V

P-P

Oscillating Frequency FW 52 55 58 kHz (3)
Dimming frequency FB 150 160 170 Hz
Minimum Duty Ratio D

- 20 - %

MIN

Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring

master and slave board.

Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.

Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the display

input signals, and it may result in line flow on the display. In order to avoid interference, the lamp

frequency should be detached from the horizontal synchronous frequency and its harmonics as far

as possible.

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

±2 and I

к

Note (5) The power supply capacity should be higher than the total inverter power consumption P

= 4.5~ 5.5mArms.

L

. Since

BL

the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current

changed as PWM duty on and off. The transient response of power supply should be considered

for the changing loading when inverter dimming.

Note (6) The measurement condition of Max. value is based on 54.6" backlight unit under input voltage 24V,

average lamp current 5.3mA and lighting 30 minutes later.

Note (7) The voltage difference of power supply voltage (V

over 1V.

) between Master and Slave board could not

BL

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Inverter

(Master)

A
A

A
A

A
A

A
A

A
A

A
A

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

A

1
2

A

A

1
2

A

A

1
2

A

Inverter

(Slave2)

A

1
2

A

A

1
2

A

A

1
2

A

LCD Module

Inverter

(Slave1)

A
A

A
A

A
A

A
A

A
A

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (Pink +)

1

HV(White -)

2

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

HV (White-)
HV (Pink +)

A

1
2

A

A

1
2

A

A

1
2

A

A

1
2

A

A

1
2

A

Inverter

(Slave3)

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3.2.3 INVERTER INTERFACE CHARACTERISTICS

Parameter Symbol

On/Off Control Voltage

Voltage

Voltage

Status Signal

VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PWM Signal Falling Time T
Input impedance RIN
PWM Delay Time T

BLON Delay Time

BLON Off Time T

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

ON

OFF

MAX 2.85 3.0 3.15 V Maximum duty ratioInternal PWM Control

MIN

HI 2.0

LO

HI 3.0 3.3 3.6 V Normal

LO

V

BLON

V

IPWM

V

EPWM

Status

PW MR

PW MF

PW M

Ton

T

on1

off

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Te st

Condition

Ё

Ё

Ё

Ё

Ё

Ё

30 Ё

Ё

30 Ё

Ё

Ё

Ё

Ё

Ё

Ё

100 Ё ms

Ё

300 Ё

ЁЁЁЁ

300

Ё

300 Ё

Min. Typ. Max.

2.0
0

Ё

0

0

Ё

Ё

Ё

Ё

1

Value

Ё

Ё

0

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

ЁЁЁЁ

Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

Approval

Unit Note

5.0 V

0.8 V

Ё

5.0 V Duty on External PWM Control

0.8 V Duty off

0.8 V Abnormal

Ё

ms

Ё

ms
100 ms
100 ms

50 us
50 us

Ё

Ё

ms

Ё

ms

Ё

ms

V Minimum duty ratio

10%-90%V

BL

MΩ

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the inverter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL

Turn OFF sequence: BLOFF → PWM signal → VBL

→

PWM signal → BLON

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V

V

V

BL

V

BLON

EPWM

IPWM

9

Toff

%/

Tf1

9

%/

Tr1

9

%/

9

%/

2.0V

0.8V

Ton

Ton1

0

0

Backlight on duration

Tr

Tf

Ext. Dimming Function

T

PWMR

2.0V

0

0.8V

T

PWM

T

PWMF

Floating

3.15V

0

Floating

Int. Dimming Function

V

W

External

PWM

Period

External

PWM Duty

100%

Minimun

Duty

14

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4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

ODD_RIN0+/­ODD_RIN1+/­ODD_RIN2+/­ODD_RIN3+/­ODD_RIN4+/­ODD_CLK+/-

EVEN_RIN0+/­EVEN_RIN1+/­EVEN_RIN2+/­EVEN_RIN3+/­EVEN_RIN4+/­EVEN_CLK+/-

MEN
MCFG 0
MCFG 1
LVDS8b
GV_mode
SELLVDS
ODSE
SCL
SDA

(FI-RE51S-HF (JAE)) or equivalent

INPUT CONNECTOR

VIN
GND

FRAME

BUFFER

MEMC

DC/DC CONVERTER

& REFERENCE VOLTAGE

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FRAME

BUFFER

TIMING

CONTROLLER

GENERATOR

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SCAN DRIVER

TFT LCD PANEL

(1920x3x1080)

DATA DRIVER (RSDS

VBL

GND

Status

E_PWM

I_PWM

BLON

INVERTER

CONNECTOR

CN127

130001WR-02E

(YEONHO) (Master)

CN103-CN105: 528521070 (Molex)

CN5-CN32: SM02 -BDAS-3-TB (JST)

or equivalent

BACKLIGHT

UNIT

CN101-CN102: 528521070 (Molex)

or equivalent

or equivalent

CN 3-CN4: Cl0114M1HR0-LF

or equivalent

INVERTER

CONNECTOR

CN227

130001WR-02E

(YEONHO) (Salve)

(Cvilux)

VBL

GND

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5 .INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module

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CNF1 Connector Part No.: JAE Taiwan (

Pin Name Description Note

1 GND Ground

2 MEN MEMC function selection 5

3 MCFG0 MEMC function selection 5

4 MCFG1 MEMC function selection 5

5 LVDS8b 8bit/10bit LVDS input selection 6

6 GV_mode Graphic / Video mode selection 7

7 SELLVDS LVDS data format Selection 3

8 SCL I2C CLK Signal

9 SDA. I2C Data Signal

10 ODSEL Overdrive Lookup Table Selection 4

11 GND Ground

12 ERX0- 2nd pixel Negative LVDS differential data input. Channel 0

13 ERX0+ 2nd pixel Positive LVDS differential data input. Channel 0

14 ERX1- 2nd pixel Negative LVDS differential data input. Channel 1

15 ERX1+ 2nd pixel Positive LVDS differential data input. Channel 1

16 ERX2- 2nd pixel Negative LVDS differential data input. Channel 2

17 ERX2+ 2nd pixel Positive LVDS differential data input. Channel 2

18 GND Ground

19 ECLK- 2nd pixel Negative LVDS differential clock input.

20 ECLK+ 2nd pixel Positive LVDS differential clock input.

21 GND Ground

22 ERX3- 2nd pixel Negative LVDS differential data input. Channel 3

23 ERX3+ 2nd pixel Positive LVDS differential data input. Channel 3

24 ERX4- 2nd pixel Negative LVDS differential data input. Channel 4 ʳ

25 ERX4+ 2nd pixel Positive LVDS differential data input. Channel 4

26 N.C. No Connection 2

27 N.C. No Connection 2

28 ORX0- 1st pixel Negative LVDS differential data input. Channel 0

29 ORX0+ 1st pixel Positive LVDS differential data input. Channel 0

30 ORX1- 1st pixel Negative LVDS differential data input. Channel 1

31 ORX1+ 1st pixel Positive LVDS differential data input. Channel 1

32 ORX2- 1st pixel Negative LVDS differential data input. Channel 2

33 ORX2+ 1st pixel Positive LVDS differential data input. Channel 2

34 GND Ground

35 OCLK- 1st pixel Negative LVDS differential clock input.

36 OCLK+ 1st pixel Positive LVDS differential clock input.

37 GND Ground

38 ORX3- 1st pixel Negative LVDS differential data input. Channel 3

39 ORX3+ 1st pixel Positive LVDS differential data input. Channel 3

40 ORX4- 1st pixel Negative LVDS differential data input. Channel 4

؀᨜౰ሽ՗

) FI-RE51S-HF or equivalent.

ʳ

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ʳ

ʳ
ʳ
ʳ
ʳ
ʳ
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ʳ
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ʳ
ʳ
ʳ
ʳ

ʳ

ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ

ʳ

16

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41 ORX4+ 1st pixel Positive LVDS differential data input. Channel 4

42 N.C. No Connection 2

43 N.C. No Connection 2

44 GND Ground

45 GND Ground

46 GND Ground

47 N.C. No Connection 2

48 VCC +12V power supply

49 VCC +12V power supply

50 VCC +12V power supply

51 VCC +12V power supply

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ʳ

ʳ
ʳ
ʳ

ʳ
ʳ
ʳ
ʳ

Note (1)

Note (2) Reserved for internal use. Please leave it open

Note (3)

LVDS connector pin order defined as follows

SELLVDS Mode

L(default)

H JEIDA

VESA

L: Connect to GND, H: Connect to +3.3V

Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the

frame rate to optimize image quality.

ODSEL Description

L(default)

H Lookup table was optimized for 50 Hz frame rate input.

L: Connect to GND, H: Connect to +3.3V

Lookup table was optimized for 60 Hz frame rate input.

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Note (5) Motion Engine (ME) Level & Demo Function Table

Motion engine level must be adjusted after video mode is selected (or entered).

Adjusting the motion engine level in graphic mode has no effect

MEN MCFG1 MCFG0 Notes

Blanking disable

Blanking

Demo mode (d)

Level

Auto blanking
Blanking enable

Strong
Medium(Default)

ME

Weak
OFF
(e) (f) (g)

(a) Module re-starts processing video signals from Frontend scaler control board.

0 0 0
0 0 1
0 1 0

0 1 1 Demo Window
1 0 0 Enable Strong Strong

1 0 1 Enable Normal Normal
1 1 0 Enable × ×
1 1 1 × × ×

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(a)
(b)
(c)

Effect of ME  De blur De judder Halo

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(b) During sync unstable period such as format change, 60Hz <-> 50Hz .

MCFG0 can be used to insert blanking of 500ms. This signal is toggled.

(c) Module continues to insert blanking until blanking disable signal is received from frontend scaler board.

(d) Demo window mode: Demo Window appears to the left half of display area. Left side with frame is

120Hz with MEMC, and right side is 120Hz w/o motion compensation.

(e) GPIO (General Purpose I/O) sequence of ME Level: (1) MEN; (2) MCFG1; (3) MCFG0.

GPIO sequence of Blanking Enable, Blanking Disable and Demo window: (1) MCFG1; (2) MCFG0; (3)

MEN.

(f) Each scaler command must be maintained the same voltage level at least 100ms.

(g) 0 : Connect to GND, 1 : +3.3V

Note (6) 8bit/10bit LVDS input selection

LVDS8b Bit depth

H(default)

L

L : Connect to GND, H : Connect to +3.3V

8bit

10bit

ʳ

ʳ

Note (7) Graphic / Video mode selection

There is no prohibited time period for switching between Graphic mode and Video mode.

When this switching signal is input, LCD will be reset and will re-start selected mode.

GV_mode Mode select MEMC ON/OFF

H(default)

L

L : Connect to GND, H : Connect to +3.3V

Graphic mode MEMC OFF

Video mode MEMC ON

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5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN101-CN108: CP042ESFA00 (Cvilux)

Pin Name Description Wire Color

1 HV High Voltage Pink
2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model CP042ESFA00, manufactured by

Cvilux. The mating header on inverter part number is CP042EP1MFB-LF (Cvilux)

1 HV(White)

2 HV(Pink)

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1 HV(Pink)

2 HV(White)

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

5.3 INVERTER UNIT

CN1: Cl0114M1HR0-LF (Cvilux)

Pin № Symbol Feature

1
2
3
4
5
6
7
8
9

10

11

12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal

14 BLON BL ON/OFF
Note (1) PIN 12:External PWM Control (Use Pin 12): Pin 13 must open.
Note (2) PIN 13:Intermal PWM Control (Use Pin 13): Pin 12 must open.
Note (3) Pin 12(E_PWM) and Pin 13(I_PWM) can’t open in same period.

CN2-CN4: Cl0112M1HR0-LF (Cvilux)

VBL +24V

GND GND

Status

(Signal Output Pin)

1 HV(Pink)

2 HV(White)

1 HV(Pink)

2 HV(White)

Normal (3.3V)

Abnormal (GND)

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Pin № Symbol Feature

1
2
3
4
5
6
7
8
9

10

11 NC NC

12 NC NC

VBL +24V

GND GND

CN5-CN32: SM02 -BDAS-3-TB (JST)

Pin No. Symbol Description

1 CCFL CCFL high voltage
2 CCFL CCFL high voltage

CN103-CN105: 528521070 (Molex)

Pin No. Symbol Description

1 Board to Board
2 Board to Board

3 Board to Board

4 Board to Board

5 Board to Board

6 Board to Board
7 Board to Board
8 Board to Board
9 Board to Board

10

Control

Signal

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Note (1) Floating of any control signal is not allowed.

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5.4 BLOCK DIAGRAM OF INTERFACE

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5.5 LVDS INTERFACE

VESA Format : SELLVDS = L or Open

JEIDA Format : SELLVDS = H

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AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)

AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

RSVD : Reserved

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for

the color. The higher the binary input, the brighter the color. The table below provides the assignment of

color versus data input.

Basic
Colors

Gray
Scale
Of
Red

Gray
Scale
Of
Green

Gray
Scale
Of
Blue

Color

Black
Red
Green
Blue
Cyan
Magenta
Yel lo w
White
Red (0) / Dark
Red (1)
Red (2)

:

:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)

:

:
Green (1021)
Green (1022)
Green (1023)

Blue (0) / Dark
Blue (1)
Blue (2)

:

:
Blue (1021)
Blue (1022)
Blue (1023)

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Red Green Blue

0

0

0
1
0
0
0
1
1
1
0
0
0

:

:
1
1
1
0
0
0

:

:
0
0
0

0
0
0

:

:
0
0
0

0

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

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0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

:

:

:

:

:

:

1

1

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

1

0

0

0

0

1

1

1

0

0

1

1

1

1

1

1

0

0

0

1

0

0

0

0

0

:

:

:

:

:

:

1

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

1

1

0

1

1

0

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

Data Signal

0

0

0

0

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

Approval

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1
0
1
1
0
0
0

:

:
0
0
0
0
0
0

:

:
1
1
1

0
0
0

:

:
0
0
0

1

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

1

1

1

0

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

;

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

:

:

:

:

:

:

0

1

0

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

1

0

0

1

0

0

1

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1
1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

:

:

:

:

:

:

1

0

1

1

1

0

1

1

1

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

Frequency

(=1/TC)

Input cycle to

LVDS

Receiver

Clock

cycle jitter
Spread spectrum
modulation range

F

Spread spectrum
modulation
frequency

LVDS

Setup Time

Receiver

Data

Hold Time

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F

clkin

T

rcl

clkin_mod

F

30 50 KHz

SSM

Tlvsu 600

Tlvhd 600

60 74.25 78 MHz

Ё

F

-2%

clkin

Ё

Ё

Ё

Ё

200 ps (2)

F

+2% MHz

clkin

Ё

Ё

Model No.: V546H1-LH2

Approval

(3)

ps

ps

Fr5 47 50 53 Hz

Frame Rate

Vertical

Active

Display

Term

Total

Display

Blank

Horizontal

Active

Display

Term

Note (1)

Note (2) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI

Total

Display

Blank

ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˹˴˸ʳ˴˸ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼Κʳ ʳ ʳ

˙ʻ˴ʼʳ Њʳ ˙˶˿˾˼ʳ Яʳ ˧˧˻ʳ Љʳ ˙ʻ˼ʼʳ

Fr6 57 60 62 Hz

Tv 1110 1125 1135 Th

Tvd 1080 1080 1080 Th

Tvb 30 45 55 Th

Th 1050 1100 1150 Tc

Thd 960 960 960 Tc

Thb 90 140 190 Tc

Tv=Tvd+T vb

Ё

Ё

Th=Thd+Thb

Ё

Ё

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Note (3) The SSCG (Spread spectrum clock generator) is defined as below figures.

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram

below.

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Model No.: V546H1-LH2

Approval

10ms

50ms

50ms

ЉЉЉЉ

T4

0V

0.5

ЉЉЉЉ

T

1

ЉЉЉЉ

ЉЉЉЉ

T

ЉЉЉЉ

2

T

3

0

0

500ms

ЉЉЉЉ

ЉЉЉЉ

0.1V

CC

3

T1

T

2

T

0.1V

T4

cc

LVDS Signals

0V

Power On

VALI D

Power Off

0

ЉЉЉЉ

T

7

ЉЉЉЉ

ЉЉЉЉ

T8

T2

T7

8

T

0

Option Signals

(SELLVDS,GPIO setting..…)

Backlight (Recommended)

ЉЉЉЉ

ЉЉЉЉ

T

T5

6

1000ms

100ms

50%

5

T

50%

6

T

Note:

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal

screen.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on period.

(5) Interface signal shall not be kept at high impedance when the power is on.

Power ON/OFF Sequence

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12V V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 120 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

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25±2

50±10

5.0±0.5
55±3

Issued Date: Aug. 10, 2009

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Approval

o

C

%RH

mA

KHz

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 3000 4000 - - Note (2)

Response Time

Center Luminance of White L

White Variation
Cross Talk CT - - 4 % Note (5)

Red

Green
Color
Chromaticity

Viewing
Angle

Blue

White

Color Gamut

Horizontal

Vertical

Gray to

gray

C

δW

=0°, θY =0°

θ

Rx 0.634 ­Ry
Gx 0.294 ­Gy
Bx 0.150 -

By
Wx
Wy

θx+

θ

-

x

θY+

θ

-

Y

x

Viewing angle at

normal direction

CR≥20

- 4.5 9 ms Note (3)

400 500 -

- - 1.3 - Note (7)

0.331

Typ.-

0.03

80 88 ­80 88 ­80 88 ­80 88 -

0.598

0.058

0.280

0.290

72 - % NTSC

Typ.+

0.03

Deg. Note (1)

cd/
m

-

-

-

-

-

2

Note (4)

Note (6)

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Note (1) Definition of Viewing Angle (θx, θy):

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Viewing angles are measured by

Note (2) Definition of Contrast Ratio (CR):

θX- = 90º

6 o’clock

θ

y-

= 90º

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L1023 / L0

x-

y-

Autronic Conoscope Cono-80

Normal

θx = θy = 0º

θy- θy+

y+

θx−

θx+

12 o’clock direction

θ

y+

= 90º

x+

θX+ = 90º

L1023: Luminance of gray level 1023

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Note (3) Definition of Gray to Gray Switching Time :

The driving signal means the signal of gray level

Optical

Response

Gray to gray average time means the average switching time of gray level

100%

90%

10%

0%

Gray to gray
switching time

Gray to gray
switching time

0, 255, 511, 767

and 1023.

0, 255, 511, 767

Time

and 1023 to

each other .

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(

)

(

)

(

)

(

)

Note (4) Definition of Luminance of White (LC):

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Model No.: V546H1-LH2

Approval

Measure the luminance of gray level 1023 at center point.

LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

CT = | Y

– YA | / YA × 100 (%)

B

Where:

(a)

Y

= Luminance of measured location without gray level 1023 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 1023 pattern (cd/m2)

B

(0, 0)

Active Area

Y

(D/8,W/2)

A, L

Gray 512

Y

(D/2,7W /8)

A, D

Y

A, U

Y

A, R

D, W

(D/2,W /8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W /8)

B, D

0, 0

Active Area

Y

(D/2,W /8)

B, U

Y

(7D/8,W/2)

Gray 0

Gray 1023

Gray512

B, R

(3D/4,3W/4)

(D, W)

(b)

(0, 0)

Y

(D/8,W/2)

A, L

Y

(D/2,7W /8)

A, D

Y

= Luminance of measured location without gray level 1023 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 1023 pattern (cd/m2)

B

Active Area

Gray 0

Y

Y

A, R

D, W

A, U

(D/2,W /8)

(7D/8,W/2)

(D/8,W/2)

Y

B, L

Y

(D/2,7W /8)

B, D

0, 0

(D/4,W/4)

Active Area

Gray 0

Y

(D/2,W /8)

B, U

Y

B, R

(3D/4,3W/4)

(D, W)

(7D/8,W/2)

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Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting backlight for 1 hour in a windless room.

LCD Module

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Issued Date: Aug. 10, 2009

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LCD Panel

Note (7) Definition of White Variation (δW):

Measure the luminance of gray level 1023 at 5 points

δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

Horizontal Line

D

D/4 D/2 3D/4

Vertical Line

W

W/4

W/2

3W /4

1 2

: Test Point

5

3 4

Active Area

30

X

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8. DEFINITION OF LABELS

8.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI MEI

OPTOELECTRONICS

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V546H1 -LH2 Rev. XX

X X X X X X X Y M D L N N N N

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E207943

MADE IN Taiwan

MADE IN TAIWAN

GEMN

V546H1 -LH2 Rev. XX

CHI MEI

OPTOELECTRONICS

X X X X X X X Y M D L N N N N

E207943

MADE IN CHINA

MADE IN TAIWAN

CAPG

(a) Model Name: V546H1-LH2

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

(c) CMO barcode definition:

Serial ID: XX-XX-X-XX-YMD-L-NNNN

Code Meaning Description

XX CMO internal use ­XX Revision Cover all the change

X-XX CMO internal use -

Year, month, day

YMD

NNNN Serial number Manufacturing sequence of product

L Product line # Line 1=1, Line 2=2, Line 3=3, …

Year: 2001=1, 2002=2, 2003=3, 2004=4…
Month: Jan. ~ Dec.=1, 2, 3, ~, 9, A, B, C

st

Day: 1

to 31st =1, 2, 3, ~, 9, A, B, C, ~, W, X, Y, exclude I, O, and U

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9. PACKING

9.1 PACKING SPECIFICATIONS

(1) 2 LCD TV modules / 1 Box

(2) Box dimensions: 1334(L) X 284 (W) X 856 (H)

(3) Weight: approximately 46 Kg (2 modules per box)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

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Anti-static Bag

Cushion(Bottom)

Carton

PP Belt

Carton Label

Figure.9-1 packing method

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Sea & Land Transportation Air Transportation
Gross : 383Kg Gross : 199Kg

(L1130*50mm*50mm)

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Film

PP Belt

(L1150*W1345*H140mm)

Figure. 9-2 Packing method

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10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling

with the inverter. Do not disassemble the module or insert anything into the backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

10.3 SAFETY STANDARDS

The LCD module should be certified with safety regulations as follows:

Regulatory Item Standard

UL UL 60950-1: 2003

Information Technology equipment

Audio/Video Apparatus

If the module displays the same pattern for a long period of time, the phenomenon of image sticking may be

occurred.

cUL CAN/CSA C22.2 No.60950-1-03

CB IEC 60950-1:2001

UL

UL 60065: 2003

cUL CAN/CSA C22.2 No.60065-03

CB

IEC 60065:2001

34

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11. MECHANICAL CHARACTERISTIC

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ڻႝηިҽԖϦљ

CHI MEI

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CHI MEI

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Appendix – TWO Wire BUS INTRODUCTION

A.1 PIN ASSIGNMENT

51pins LVDS connector

Pin8: SCL

Pin9: SDA

A.2 I2C BUS APPLICATION NOTE

I2C bus: (The I2C bus must for MEMC only or prevent the I2C bus voltage drop down in initial state)

Issued Date: Aug. 10, 2009

Model No.: V546H1-LH2

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A.3 TWO WIRE BUS DEVICE ADDRESS

Two wire device address: default is 0x40, 1 byte

Two wire command: the range is 0x00 to 0xFF, 1 byte, see the two wire command table.

Two wire bus format:

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A.4 TWO WAY TO CONTROL THE TWO WIRE BUS

There are two options to control the two wires bus command.

Two wire bus 6 bytes format

Issued Date: Aug. 10, 2009

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Two wire bus 3 bytes format

Note:

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP

condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the

wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave

can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too

fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending

the SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the

slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.

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A.5 TWO WIRE BUS COMMAND TABLE

There is two wire bus command table.

Command Name
All OSD Protection 0x00 R/W OSDx Enable Flag Contorl
OSD1_Start_Protection 0x01 R/W OSD1 Protection Start Position
OSD2_Start_Protection 0x02 R/W OSD2 Protection Start Position
OSD3_Start_Protection 0x03 R/W OSD3 Protection Start Position
OSD4_Start_Protection 0x04 R/W OSD4 Protection Start Position
OSD1_End_Protection 0x05 R/W OSD1 Protection End Position
OSD2_End_Protection 0x06 R/W OSD2 Protection End Position
OSD3_End_Protection 0x07 R/W OSD3 Protection End Position
OSD4_End_Protection 0x08 R/W OSD4 Protection End Position
Demo Window 0x09 R/W ME Performance Demo
MEMC Level 0x0A R/W ME Performance
GV Mode 0x0B R/W ME Operation
Blanking 0x0C R/W Blinking the screen

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Access
Mode

Description

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Enable All OSD Protection

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OSD # 1~4 Start Protection

OSD # 1~4 End Protection

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Demo Window

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MEMC Level

GV Mode

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Blanking (Enable/Disable)

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A.6 TWO WIRE BUS REQUIREMENT

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A.7 THE TWO WIRE BUS SEQUENCE

Two Wire command can be initialized during 20ms to 60ms.

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Exam ple:

The previous state is strong mode, and the power is reset. The two wire command (strong mode

command) must be initialized during 20ms to 60ms.

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