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Model No.: V546H1 – LE1
Preliminary
TFT LCD Preliminary Specification
MODEL NO.: V546H1- LE1
Customer:
Approved by:
Note:
TV Head Division
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-nan Chen WT Lin
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang Wei-ting Hsu
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Issued Date: Dec. 1, 2009
Model No.: V546H1 – LE1
Preliminary
CONTENTS
1. GENERAL DESCRIPTION...................................................................................................................................... 5
1.1 OVERVIEW.................................................................................................................................................. 5
1.2 FEATURES .................................................................................................................................................. 5
1.3 APPLICATION.............................................................................................................................................. 5
1.4 GENERAL SPECIFICATI0NS ....................................................................................................................... 5
1.5 MECHANICAL SPECIFICATIONS ................................................................................................................ 5
2. ABSOLUTE MAXIMUM RATINGS........................................................................................................................... 6
2.1 ABSOLUTE RATINGS OF ENVIRONMENT.................................................................................................. 6
2.2 ELECTRICAL ABSOLUTE RATINGS............................................................................................................ 7
3. ELECTRICAL CHARACTERISTICS........................................................................................................................ 8
3.1.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)...........................................................................................................8
3.2 BACKLIGHT UNIT...................................................................................................................................... 11
4. BLOCK DIAGRAM OF INTERFACE...................................................................................................................... 13
4.1 TFT LCD MODULE..................................................................................................................................... 13
5 .INPUT TERMINAL PIN ASSIGNMENT.................................................................................................................. 14
5.1 TFT LCD Module Input ............................................................................................................................... 14
5.2 BACKLIGHT UNIT...................................................................................................................................... 18
5.3 DRIVING BOARD UNIT ............................................................................................................................ 18
5.4 BLOCK DIAGRAM OF INTERFACE ........................................................................................................... 20
5.5 LVDS INTERFACE ..................................................................................................................................... 21
5.6 COLOR DATA INPUT ASSIGNMENT.......................................................................................................... 22
6. INTERFACE TIMING ............................................................................................................................................ 24
6.1 INPUT SIGNAL TIMING SPECIFICATIONS................................................................................................ 24
6.2 POWER ON/OFF SEQUENCE................................................................................................................... 27
7. OPTICAL CHARACTERISTICS ............................................................................................................................ 28
7.1 TEST CONDITIONS................................................................................................................................... 28
7.2 OPTICAL SPECIFICATIONS ...................................................................................................................... 28
8. DEFINITION OF LABELS ..................................................................................................................................... 32
8.1 CMO MODULE LABEL............................................................................................................................... 32
9. Packaging............................................................................................................................................................. 33
9.1 PACKING SPECIFICATIONS...................................................................................................................... 33
9.2 PACKING METHOD ................................................................................................................................... 33
10. PRECAUTIONS.................................................................................................................................................. 35
10.1 ASSEMBLY AND HANDLING PRECAUTIONS ......................................................................................... 35
10.2 SAFETY PRECAUTIONS ......................................................................................................................... 35
10.3 SAFETY STANDARDS............................................................................................................................. 35
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Model No.: V546H1 – LE1
Preliminary
11. MECHANICAL CHARACTERISTIC ..................................................................................................................... 36
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Model No.: V546H1 – LE1
REVISION HISTORY
Version Date
Ver 1.0 Sep. 7, 09’ All All Preliminary Specification Ver 1.0 was first issued.
Ver 1.5 Dec. 1, 09’ 8
Page
(New)
10
13
14
19
22
23
28
37
17
Section Description
3.1
Update TFT LCD module Electrical Characteristic
3.2
Update Backlight Unit
4.1
Update TFT LCD module Block Diagram of Interface
5.1
Update TFT LCD module input terminal pin assignment
5.4
Update Block Diagram of interface
5.6
Update Color Data Input Assignment
6.1
Update input signal timing Specifications
7.1
Update LED current
11
Update Mechanical Characteristic
5.2
Add Backlight pin define
Preliminary
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Model No.: V546H1 – LE1
Preliminary
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V546H1-LE1 is a 54.6” TFT Liquid Crystal Display module with LED Backlight unit and 4ch-LVDS interface.
This module supports 1920 x 1080 HDTV format and can display true 1.073G colors (8-bit + Hi-FRC
/color). The driving board module for backlight is built-in.
1.2 FEATURES
- High brightness (450nits)
- High contrast ratio (4000:1)
- Fast response time (Gray to Gray typical 4.5ms)
- High color saturation (75% NTSC)
- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for 120/100 Hz frame rate
- Ultra wide viewing angle: Super MVA technology
1.3 APPLICATION
- Standard Living Room TVs.
- Public Display Application.
- Home Theater Application.
- MFM Application.
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 1209.6(H) x 680.4(V) (54.6” diagonal) mm
Bezel Opening Area 1217.6 (H) x 688.4 (V) mm
Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.21(H) x 0.63(V) mm Pixel Arrangement RGB vertical stripe - Display Colors 1.073G color Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and
back outlines.
Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to
change this feature.
Anti-Glare coating (11% Low Haze)
Hardness (3H)
- (2)
(1)
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 1266.1 1267.6 1269.1 mm Module Size
Vertical (V) 737.2 738.4 739.6 mm
Module Size
Weight
Note (1)Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
Depth (D) 11.3 12.3 13.3 mm To Rear
Weight 15235 g Weight
26.0 27.0 28.0
mm To converter
cover
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Model No.: V546H1 – LE1
Preliminary
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
Љ
±X, ±Y 30
NOP
±Z
- 1.0 G (4), (5)
NOP
Min. Max.
Value
30
Unit Note
G (3), (5)
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so
that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
40
Operating Range
20
10
Storage Range
Temperature (ºC)
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80 60 -20 40 0 20 -40
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Model No.: V546H1 – LE1
Preliminary
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.2.2 BACKLIGHT CONVERTER UNIT
Item Symbol
Light Bar Voltage VW Ta = 25
Converter Input Voltage VBL - 0 - 30 V
Control Signal Level - - -0.3 - 7 V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function
operation should be restricted to the conditions described under Normal Operating Conditions.
Value
Te st
Condition
к
Unit Note
(1)
Min. Type Max. Unit Note
- - 60 V
RMS
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Model No.: V546H1 – LE1
Preliminary
3. ELECTRICAL CHARACTERISTICS
3.1.1 TFT LCD MODULE
Parameter Symbol
Power Supply Voltage VCC 10.8 12.0 13.2 V (1)
Rush Current I
Power Supply Current
Differential Input High
Threshold Voltage
LVDS
Interface
Differential Input Low
Threshold Voltage
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 200 - 600 mV
Terminating Resistor R
Input High Threshold Voltage VIH 2.7 - 3.3 V CMOS
Interface
Input Low Threshold Voltage V
(Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
- 3.3 5 A (2)
RUSH
Unit Note
White - 0.584 0.8 A
Black - 0.425 0.6 A
Horizontal one line
stripe
I
CC
- 1.17 1.55 A
+100 - - mV
V
LVT H
- - -100 mV
V
LVTL
- 100 - ohm
T
0 - 0.7 V
IL
(3)
(4)
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
+12V
R1
1K
Q1
Si4485D
FUSE
C3
(LCD Module Input)
1uF
VR1
(Low to High)
(Control Signal)
SW
R2
1K
47K
Q2
2N7002
C1
0.01
Note (3) The specified power supply current is under the conditions at Vcc = 12V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
Vcc
= 120 Hz,
v
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Model No.: V546H1 – LE1
Preliminary
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
a. White Pattern
b. Black Pattern
c. Horizontal one line stripe
Active Area
Active Area
Active Area
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Model No.: V546H1 – LE1
Note (4) The LVDS input characteristics are as follows:
3.1.2 Vcc Power Dip Condition:
Preliminary
Vcc
10V
10.8V
Td
Dip condition: 10V Vcc 10.8V, Td 20ms
ЉЉЉЉЉ
ЉЉ
ЉЉ
Љ
ЉЉ
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Model No.: V546H1 – LE1
3.2 BACKLIGHT UNIT
3.2.1 LED LIGHT BARCHARACTERISTICS (
Parameter Symbol
Light Bar Voltage VW
Forward Voltage Vf
LED Current IL
3.2.2 CONVERTER CHARACTERISTICS (
Parameter Symbol
Power Consumption PBL - 168 183 W
Converter Input Voltage VBL
Converter Input Current IBL
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
- 5 - %
MIN
Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
- - 54
3.0 - 3.6
112.8 120 127.2
Unit Note
V
V
mA
Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
22.8 24 25.2
-
7 7.6 A
Unit Note
VDC
I
RMS
I
RMS
RMS
Preliminary
=120mA
L
=120mA
L
3.2.3 CONVERTER INTERFACE CHARACTERISTICS
External dimming: 150Hz~170Hz, duty ratio: 5%~100%
Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Te st
Condition
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Min. Typ. Max.
2.0
0
3.15
Ё
2.0
0
3.0 3.3 3.6 V Normal
0
30
30
Value
Ё
Ё
Ё
0
Ё
Ё
Ё
Ё
Ё
Unit Note
5.0 V
0.8 V
3.45
Ё
V maximum duty ratio
V minimum duty ratio
5.0 V Duty on
0.8 V Duty off
0.8 V Abnormal
Ё
ms
Ё
10%-90%V
ms
BL
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
100 ms
Ё
100 ms
Ё
50 us
Ё
50 us
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Model No.: V546H1 – LE1
Preliminary
Ё
Input Impedance Rin
PWM Delay Time TPWM
Ton
Ё
Ё
1
100
300
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
300
300
Ё
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the converter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL → PWM signal → BLON
Ё
Ё
Ё
Ё
Ё
Ё
MΩ
Ё
ms
Ё
ms
Ё
ms
Ё
ms
Turn OFF sequence: BLOFF → PWM signal → VBL
Tr1
BL
V
V
V
V
BLON
EPWM
IPWM
0
0
0
0
9
%/
2.0V
0.8V
3.3V
9
2.0V
0.8V
Ton
PWM
T
%/
Backlight on duration
Tr
Ext. Dimming Function
T
PWMR
Floating
T
PWMF
Tf
Ton1
Floating
Int. Dimming Function
9
Toff
%/
Tf1
9
%/
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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Model No.: V546H1 – LE1
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
CH3_0(+ /-)
CH3_1(+ /-)
CH3_2(+ /-)
CH3_3(+ /-)
CH3_4(+ /-)
CH3_CLK(+/-)
CNF1 or equivalent
FI-RE41S-HF (JAE)
INPUT CONNECTOR
CH4_0(+ /-)
CH4_1(+ /-)
CH4_2(+ /-)
CH4_3(+ /-)
CH4_4(+ /-)
CH4_CLK(+/-)
INPUT CONNECTOR
CNF2 or equivalent
CH1_0(+ /-)
CH1_1(+ /-)
CH1_2(+ /-)
CH1_3(+ /-)
CH1_4(+ /-)
CH1_CLK(+/-)
CH2_0(+ /-)
CH2_1(+ /-)
CH2_2(+ /-)
CH2_3(+ /-)
CH2_4(+ /-)
CH2_CLK(+/-)
SELLVDS
Vcc
GND
FI-RE51S-HF (JAE)
CONTROLLER
CONVERTER
& REFERENCE
GENERATOR
TIMING
DC/DC
VOLTAGE
Preliminary
SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER (RSDS)
CN3~CN14: 196033-10041-3
VBL
GND
Status
E_PWM
I_PWM
BLON
Driving board
CONNECTOR
CN1:
CI0114M1HR0-LF
(CvilLux) or
S14B-PH-SM4-TB(LF)
(P-TWO)
LED
BACKLIGHT
UNIT
Driving board
CONNECTOR
CN2:
CI0112M1HR0-LF
(CvilLux) or
S12B-PH-SM4-TB(LF)
(SN) (JST)
VBL
GND
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Model No.: V546H1 – LE1
5 .INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF2 Connector Pin Assignment (187059-51221(P-two) or equivalent)
Pin Name Description Note
1
GND Ground
2
N.C. No Connection
3
N.C. No Connection
4
N.C. No Connection
5
N.C. No Connection
6
N.C. No Connection
7
SELLVDS LVDS Data Format Selection
8
N.C. No Connection
9
N.C. No Connection
Preliminary
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
10
N.C. No Connection
11
GND Ground
12
CH1[0]- First pixel Negative LVDS differential data input. Pair 0
13
CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
14
CH1[1]- First pixel Negative LVDS differential data input. Pair 1
15
CH1[1]+ First pixel Positive LVDS differential data input. Pair 1
16
CH1[2]- First pixel Negative LVDS differential data input. Pair l 2
17
CH1[2]+ First pixel Positive LVDS differential data input. Pair 2
18
GND Ground
19
CH1CLK- First pixel Negative LVDS differential clock input.
20
CH1CLK+ First pixel Positive LVDS differential clock input.
21
GND Ground
22
CH1[3]- First pixel Negative LVDS differential data input. Pair 3
23
CH1[3]+ First pixel Positive LVDS differential data input. Pair 3
(1)
24
CH1[4]- First pixel Negative LVDS differential data input. Pair 4
25
CH1[4]+ First pixel Positive LVDS differential data input. Pair 4
26
N.C. No Connection
27
N.C. No Connection
28
CH2[0]- Second pixel Negative LVDS differential data input. Pair
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0
29
CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0
30
CH2[1]-
31
CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1
32
CH2[2]-
33
CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2
34
GND Ground
35
CH2CLK- Second pixel Negative LVDS differential clock input.
36
CH2CLK+ Second pixel Positive LVDS differential clock input.
37
GND Ground
38
CH2[3]-
Second pixel Negative LVDS differential data input. Pair
1
Second pixel Negative LVDS differential data input. Pair
2
Second pixel Negative LVDS differential data input. Pair
3
Preliminary
39
CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3
40
CH2[4]-
41
CH2[4]+ Second pixel Positive LVDS differential data input. Pair 4
42
N.C. No Connection
43
N.C. No Connection
44
GND Ground
45
GND Ground
46
GND Ground
47
N.C. No Connection
48
VCC +12V power supply
49
VCC +12V power supply
50
VCC +12V power supply
51
VCC +12V power supply
CNF3 Connector Pin Assignment (196225-80041(P-two) or equivalent)
Second pixel Negative LVDS differential data input. Pair
4
(1)
(1)
(1)
Pin Name Description Note
1
GND Ground
2
N.C. No Connection
3
N.C. No Connection
4
N.C. No Connection
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(1)
(1)
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Model No.: V546H1 – LE1
5
N.C. No Connection
6
N.C. No Connection
7
N.C. No Connection
8
N.C. No Connection
9
GND Ground
10
CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
11
CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0
12
CH3[1]- Third pixel Negative LVDS differential data input. Pair 1
13
CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1
14
CH3[2]- Third pixel Negative LVDS differential data input. Pair 2
15
CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2
16
GND Ground
Preliminary
(1)
(1)
(1)
(1)
17
CH3CLK- Third pixel Negative LVDS differential clock input.
18
CH3CLK+ Third pixel Positive LVDS differential clock input.
19
GND Ground
20
CH3[3]- Third pixel Negative LVDS differential data input. Pair 3
21
CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3
22
CH3[4]- Third pixel Negative LVDS differential data input. Pair 4
23
CH3[4]+ Third pixel Positive LVDS differential data input. Pair 4
24
N.C. No Connection
25
N.C. No Connection
26
CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0
27
CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0
28
CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1
29
CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1
30
CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2
(1)
(1)
31
CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2
32
GND Ground
33
CH4CLK- Fourth pixel Negative LVDS differential clock input.
34
CH4CLK+ Fourth pixel Positive LVDS differential clock input.
35
GND Ground
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Model No.: V546H1 – LE1
Preliminary
36
CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3
37
CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3
38
CH4[4]- Fourth pixel Negative LVDS differential data input. Pair 4
39
CH4[4]+ Fourth pixel Positive LVDS differential data input. Pair 4
40
N.C. No Connection
41
N.C. No Connection
Note (1) Reserved for internal use. Please leave it open.
Note (2) High=connect to +3.3V : JEIDA Format
Note (3) Interface optional pin has internal scheme as following diagram. Customer should keep the interface
voltage level requirement as below.
System Board
Panel
Ι
Low= connect to GND or Open : VESA Format.
(1)
(1)
Note (4) LVDS 4-port Data Mapping
Interface Voltage
Level
VH > 3.0V
Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
1K ohm
IC
>20K ohm
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Model No.: V546H1 – LE1
Preliminary
5.2 BACKLIGHT UNIT
The pin configuration for the housing and leader wire is shown in the table below.
CN3-CN14 (Housing): 51281-1094 (Molex) or Aces 91500-01001
Pin No. Symbol Description
1 VLED+
2 VLED+
3 NC
4 NC
5 NC
6 NC
7 NC
8 NC
9 VLED-
10 VLED-
Note (1) The backlight interface housing for high voltage side is a model 51281-1094, manufactured by Molex
Positive of LED String
No Connection
Negative of LED String
or equivalent. The mating header on converter part number is 51281-1094
5.3 DRIVING BOARD UNIT
CN1(Header): CI0114M1HR0-LF (CvilLux) or S14B-PH-SM4-TB(LF)(SN) (JST)
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 Status
12 E_PWM
13 I_PWM
VBL +24V
GND GND
Normal (3.3V)
Abnormal (0V)
External PWM
Control
Internal PWM
Control
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
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CN2(Header): CI0112M1HR0-LF (CvilLux) or S12B-PH-SM4-TB(LF)(SN) (JST)
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
VBL +24V
GND GND
Preliminary
11 NC NC
12 NC NC
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5.4 BLOCK DIAGRAM OF INTERFACE
Preliminary
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
Preliminary
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
is used differentially.
5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
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Preliminary
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
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Preliminary
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
0
0
1
0
1
0
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
;
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Color
Black
Red
Green
Blue
Cyan
Magenta
Yel lo w
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
0
:
:
1
0
1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
clkin
(=1/TC)
- - 200 ps (3)
T
rcl
clkin_mo
F
d
- - 200 KHz
F
SSM
60 74.25 80 MHz
-2% - F
F
clkin
+2% MHz
clkin
Fr5 TBD 100 TBD Hz
TBD 120 TBD Hz
F
r6
LVDS
Receiver
Clock
LVDS
Receiver
Data
Vertical
Active
Display
Term
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time Tlvsu 600 - - ps
Hold Time Tlvhd 600 - - ps
Frame Rate
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Preliminary
(4)
(5)
(6)
Tv=Tvd+Tv
b
Ё
Ё
Th=Thd+T
hb
Ё
Ё
Horizontal
Active
Display
Term
Blank Tvb 35 45 55 Th
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2) Please make sure the range of pixel clock has follow the below equation:
Fclkin(max) Fr6 Tv Th
Fr5 Tv Th Fclkin(min)
ѼѼЊ
ЊѼѼ
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Preliminary
INPUT SIGNAL TIMING DIAGRAM
Tvd
DE
Th
DCLK
DE
Tv
Tvb
Thd
DAT
Valid display data ( 480 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
14
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
3T
14
5T
14
7T
14
9T
14
11T
14
13T
14
Note (6) : (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information
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Preliminary
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram
below.
10ms
50ms
50ms
ЉЉЉЉ
T4
0V
0.5
ЉЉЉЉ
T
1
ЉЉЉЉ
ЉЉЉЉ
T
2
ЉЉЉЉ
ЉЉЉЉ
T
3
ЉЉЉЉ
0
0
500ms
0.1V
CC
3
T1
T
2
T
LVDS Signals
0V
Power On
VALI D
Power Off
0
ЉЉЉЉ
T
7
ЉЉЉЉ
0
ЉЉЉЉ
T2
T
8
ЉЉЉЉ
T3
T7
Option Signals
(SELLVDS…)
0.1V
T
cc
T4
8
Backlight (Recommended)
ЉЉЉЉ
ЉЉЉЉ
T5
T
6
500ms
100ms
50%
5
T
50%
6
T
Note:
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
Power ON/OFF Sequence
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Preliminary
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12V V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Current IL 120 mA
25±2
50±10
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (4000) - - Note (2)
Response Time
Center Luminance of White L
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color
Chromaticity
Viewing
Angle
Blue
White
Color Gamut
Horizontal
Vertical
Gray to
gray
C
δW
=0°, θY =0°
θ
Rx TBD -
Ry
Gx TBD Gy
Bx TBD By
Wx
Wy
θx+
θ
-
x
θY+
θ
-
Y
x
Viewing angle at
normal direction
CR≥20
- 4.5 9 ms Note (3)
350 450 -
- - (1.5) - Note (7)
TBD
Typ.-
0.03
80 88 80 88 80 88 80 88 -
TBD
TBD
0.285
0.293
(75%) - % NTSC
Typ.+
0.03
o
C
%RH
cd/
Note (4)
2
m
-
Note (6)
-
-
-
Deg. Note (1)
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Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80.
θX- = 90º
6 o’clock
θ
y-
= 90º
x-
y-
Normal
θx = θy = 0º
θy- θy+
θx−
θx+
12 o’clock direction
y+
θ
y+
= 90º
x+
Preliminary
θX+ = 90º
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in
Note (7)
Note (3) Definition of Gray to Gray Switching Time :
Optical
Response
100%
90%
10%
0%
Gray to gray
switching time
Gray to gray
switching time
ime
The driving signal means the signal of gray level 0, 31, 63, 95, 127, 159, 191, 223 and 255.
Gray to gray average time means the average switching time of gray level 0, 31, 63, 95, 127, 159, 191,
223 and 255 to each other .
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Note (4) Definition of Luminance of White (LC):
Measure the luminance of gray level 255 at center point.
LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | Y
– YA | / YA × 100 (%)
B
Where:
Y
= Luminance of measured location without gray level 0 pattern (cd/m2)
A
Y
= Luminance of measured location with gray level 0 pattern (cd/m2)
B
(0, 0)
Active Area
Gray 0
Y
(D/8,W/2)
A, L
Gray 128
Y
(D/2,7W/8)
A, D
Y
A, U
Y
A, R
D, W
(D/2,W /8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
(0, 0)
Active Area
Gray 255
Preliminary
Y
(D/2,W /8)
B, U
Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
D, W
Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid
abrupt temperature change during measuring. In order to stabilize the luminance,
the measurement should be executed after lighting backlight for 1 hour in a
windless room.
LCD Module
LCD Panel
Field of View = 1º
500 mm
CS-2000
Light Shield
(Ambient Luminance < 2 lu
x)
Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Preliminary
Vertical Line
W
W/4
W/2
3W /4
Horizontal Line
D
D/4 D/2 3D/4
1 2
5
3 4
X
: Test Point
X=1 to 5
Active Area
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Preliminary
8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following
explanation.
V546H1-LE1 Rev. XX
CHI MEI
OPTOELECTRONICS
X X X X X X X Y M D L N N N N
V546H1-LE1 Rev. XX
CHI MEI
OPTOELECTRONICS
X X X X X X X Y M D L N N N N
E207943
MADE IN Taiwan
MADE IN TAIWAN
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MADE IN CHINA
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(a) Model Name: V546H1-LE1
(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) CMO barcode definition:
Serial ID: XX-XX-X-XX-YMD-L-NNNN
Code Meaning Description
XX CMO internal use XX Revision Cover all the change
X-XX CMO internal use -
Year, month, day
YMD
NNNN Serial number Manufacturing sequence of product
L Product line # Line 1=1, Line 2=2, Line 3=3, …
Year: 2001=1, 2002=2, 2003=3, 2004=4…
Month: Jan. ~ Dec.=1, 2, 3, ~, 9, A, B, C
st
Day: 1
to 31st =1, 2, 3, ~, 9, A, B, C, ~, W, X, Y, exclude I, O, and U
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Model No.: V546H1 - LE1
9. Packaging
9.1 PACKING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions: 1334(L) X 284 (W) X 856 (H)
(3) Weight: approximately 48 Kg (3 modules per box)
9.2 PACKING METHOD
Figures 9-1 and 9-2 are the packing method
LCD TV Module
Anti-sta tic Bag
Carton
Preliminary
PP Belt
Cushion(Bottom)
Carton Label
Figure.9-1 packing method
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Model No.: V546H1 - LE1
Preliminary
Sea & Land Transportation Air Transportation
Gross : 399Kg Gross : 207Kg
(L1130*50mm*50mm)
Film
PP Belt
(L1150*W1345*H140mm)
Figure. 9-2 Packing method
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Model No.: V546H1 - LE1
Preliminary
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas.
The dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent
the damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
10.2 SAFETY PRECAUTIONS
(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
10.3 SAFETY STANDARDS
The LCD module should be certified with safety regulations as follows:
Regulatory Item Standard
UL UL 60950-1: 2003
Information Technology equipment
cUL CAN/CSA C22.2 No.60950-1-03
CB IEC 60950-1:2001
UL
UL 60065: 2003
Audio/Video Apparatus
If the module displays the same pattern for a long period of time, the phenomenon of image sticking may be
occurred.
cUL CAN/CSA C22.2 No.60065-03
CB
IEC 60065:2001
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11. MECHANICAL CHARACTERISTIC
Preliminary
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CHI MEI
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Preliminary
ڻႝηިҽ ԖϦљ
CHI MEI
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