CMO V546H1-LE1 Specification

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Issued Date: June. 18, 2009

Model No.: V546H1 – LE1

Tentative

TFT LCD Tentative Specification

MODEL NO.: V546H1- LE1

Customer:

Approved by:

Note:

TV Head Division

Approved By

LY Chen

Reviewed By

QA Dept. Product Development Div.

Hsin-nan Chen WT Lin

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Prepared By

LCD TV Marketing and Product Management Div.

CY Chang Wei-ting Hsu

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Model No.: V546H1 – LE1

Tentative

CONTENTS -

1. GENERAL DESCRIPTION...................................................................................................................................... 5

1.1 OVERVIEW .................................................................................................................................................. 5

1.2 FEATURES .................................................................................................................................................. 5

1.3 APPLICATION.............................................................................................................................................. 5

1.4 GENERAL SPECIFICATI0NS ....................................................................................................................... 5

1.5 MECHANICAL SPECIFICATIONS ................................................................................................................ 5

2. ABSOLUTE MAXIMUM RATINGS........................................................................................................................... 6

2.1 ABSOLUTE RATINGS OF ENVIRONMENT..................................................................................................6

2.2 ELECTRICAL ABSOLUTE RATINGS............................................................................................................7

3. ELECTRICAL CHARACTERISTICS........................................................................................................................ 8

3.1.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)...........................................................................................................8

3.2 BACKLIGHT UNIT...................................................................................................................................... 10

4. BLOCK DIAGRAM OF INTERFACE...................................................................................................................... 12

4.1 TFT LCD MODULE..................................................................................................................................... 12

5 .INPUT TERMINAL PIN ASSIGNMENT.................................................................................................................. 13

5.1 TFT LCD Module ........................................................................................................................................ 13

5.2 BACKLIGHT UNIT...................................................................................................................................... 15

5.3 DRIVING BOARD UNIT ............................................................................................................................ 16

5.4 BLOCK DIAGRAM OF INTERFACE ........................................................................................................... 17

5.5 LVDS INTERFACE ..................................................................................................................................... 19

5.6 COLOR DATA INPUT ASSIGNMENT.......................................................................................................... 20

6. INTERFACE TIMING ............................................................................................................................................ 21

6.1 INPUT SIGNAL TIMING SPECIFICATIONS................................................................................................ 21

6.2 POWER ON/OFF SEQUENCE................................................................................................................... 22

7. OPTICAL CHARACTERISTICS ............................................................................................................................ 23

7.1 TEST CONDITIONS................................................................................................................................... 23

7.2 OPTICAL SPECIFICATIONS ...................................................................................................................... 23

8. DEFINITION OF LABELS ..................................................................................................................................... 27

8.1 CMO MODULE LABEL............................................................................................................................... 27

9. Packaging............................................................................................................................................................. 28

9.1 PACKING SPECIFICATIONS...................................................................................................................... 28

9.2 PACKING METHOD ................................................................................................................................... 28

10. PRECAUTIONS .................................................................................................................................................. 30

10.1 ASSEMBLY AND HANDLING PRECAUTIONS ......................................................................................... 30

10.2 SAFETY PRECAUTIONS ......................................................................................................................... 30

10.3 SAFETY STANDARDS ............................................................................................................................. 30

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11. MECHANICAL CHARACTERISTIC ..................................................................................................................... 31

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Version Date

Page

(New)

Section Description

REVISION HISTORY

Tentative

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V546H1-LE1 is a 54.6” TFT Liquid Crystal Display module with LED Backlight unit and 4ch-LVDS interface.

This module supports 1920 x 1080 HDTV format and can display true 1.073G colors (10-bit /color). The

driving board module for backlight is built-in.

1.2 FEATURES

- High brightness (450nits)

- High contrast ratio (4000:1)

- Fast response time (Gray to Gray typical 4.5ms)

- High color saturation (80% NTSC)

- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

- DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Optimized response time for 120/100 Hz frame rate

- Ultra wide viewing angle: Super MVA technology

1.3 APPLICATION

Tentative

- Standard Living Room TVs.

- Public Display Application.

- Home Theater Application.

- MFM Application.

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 1209.6(H) x 680.4(V) (54.6” diagonal) mm Bezel Opening Area 1217.6 (H) x 688.4 (V) mm Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.21(H) x 0.63(V) mm Pixel Arrangement RGB vertical stripe - Display Colors 1.073G color Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to

change this feature.

Anti-Glare coating (11% Low Haze)

Hardness (3H)

- (2)

(1)

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) 1266.1 1267.6 1269.1 mm Module Size

Vertical (V) 737.2 738.4 739.6 mm Module Size Weight

Note (1)Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

Depth (D) 11.3 12.3 13.3 mm To Rear

Weight 14340 g Weight

26.0 27.0 28.0

mm To converter

cover

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 50 ºC (1), (2)

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in final product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

Љ

±X, ±Y 30

NOP

±Z

- 1.0 G (4), (5)

NOP

Min. Max.

Value

30

Unit Note

G (3), (5)

improper thermal management in final product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so

that the module would not be twisted or bent by the fixture.

Relative Humidity (%RH)

100

90

80

60

40

Operating Range

20

10

Storage Range

Temperature (ºC)

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80 60 -20 40 0 20 -40

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.5 V

Logic Input Voltage VIN -0.3 3.6 V

2.2.2 BACKLIGHT CONVERTER UNIT

Item Symbol

Light Bar Voltage VW Ta = 25

Converter Input Voltage VBL - 0 - 30 V

Control Signal Level - - -0.3 - 7 V

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function

operation should be restricted to the conditions described under Normal Operating Conditions.

Value

Te st

Condition

к

Unit Note

(1)

Min. Type Max. Unit Note

- - 60 V

RMS

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3. ELECTRICAL CHARACTERISTICS

3.1.1 TFT LCD MODULE

Parameter Symbol

Power Supply Voltage VCC 10.8 12.0 13.2 V (1) Power Supply Ripple Voltage VRP - - 350 mV Rush Current I

Power Supply Current

Common Input Voltage V

Interface

Terminating Resistor R Input High Threshold Voltage VIH 2.7 - 3.3 V CMOS

Interface

Input Low Threshold Voltage V

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

(Ta = 25 ± 2 ºC)

Value

Min. Typ. Max.

- 3.9 5 A (2)

RUSH

Unit Note

White - 1.5 1.59 A Black - 1.3 1.586 A Horizontal one line stripe

I

CC

- 2.9 3.5 A

1.125 1.25 1.375 V LVDS

LVC

100 Ohm

T

0 - 0.7 V

IL

(3)

+12V

R1 1K

Q1

Si4485D

FUSE

C3

1uF

Vcc

(LCD Module Input)

VR1

(Low to High)

(Control Signal)

SW

R2

1K

47K

Q2

2N7002

C1

0.01

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

GND

470us

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Note (3) The specified power supply current is under the conditions at Vcc = 12V, Ta = 25 ± 2 ºC, fv = 120 Hz,

whereas a power dissipation check pattern below is displayed.

a. White Pattern

Active Area

c. Horizontal one line stripe

b. Black Pattern

Active Area

3.1.2 Vcc Power Dip Condition:

Vcc

10.8V

Td

Dip condition:

10V

ЉЉЉЉ

Vcc

ЉЉЉЉ

10V

10.8V, Td

ЉЉЉЉ

20ms

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3.2 BACKLIGHT UNIT

3.2.1 LED LIGHT BARCHARACTERISTICS (

Parameter Symbol

Light Bar Voltage VW

Forward Voltage Vf

LED Current IL

3.2.2 CONVERTER CHARACTERISTICS (

Parameter Symbol

Power Consumption PBL - 206 TBD W

Inverter Input Voltage VBL

Inverter Input Current IBL Oscillating Frequency FW TBD TBD TBD kHz

Dimming Frequency FB 150 160 170 Hz Minimum Duty Ratio D

- 5 - %

MIN

Ta = 25 ± 2 ºC)

Value

Min. Typ. Max.

- - 44.2

3.1 3.3 3.5

TBD 60 TBD

Unit Note

V

RMS

V

RMS

mA

Ta = 25 ± 2 ºC)

Value

Min. Typ. Max.

22.8 24 25.2

-

TBD

-

Unit Note

VDC

A

I I

RMS

=60 mA

L

Tentative

=60mA

3.2.3 CONVERTER INTERFACE CHARACTERISTICS

Parameter Symbol

ON

On/Off Control Voltage

VBLON

OFF

Internal PWM Control Voltage

External PWM Control Voltage

MAX

MIN

HI

LO

VIPWM

VEPWM

HI

Status Signal

Status

LO

VBL Rising Time Tr1

VBL Falling Time Tf1

Control Signal Rising Time Tr

Te st

Condition

Ё

Min. Typ. Max.

2.0

0

3.15

Ё

2.0

0

3.0 3.3 3.6 V Normal

0

30

Ё

Value

Ё

0

Ё

Unit Note

5.0 V

0.8 V

3.45

Ё

V maximum duty ratio

V minimum duty ratio

5.0 V Duty on

0.8 V Duty off

0.8 V Abnormal

Ё

ms

Ё

ms

100 ms

10%-90%V

BL

Control Signal Falling Time Tf

PWM Signal Rising Time TPWMR

PWM Signal Falling Time TPWMF

Input Impedance Rin

Ё

1

Ё

100 ms

Ё

50 us

Ё

50 us

Ё

MΩ

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PWM Delay Time TPWM

Ton

Ё

100

300

Ё

ms

Ё

ms

Ё

BLON Delay Time

T

on1

BLON Off Time Toff

Ё

300

Ё

ms

Ё

ms

Ё

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the converter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL

Turn OFF sequence: BLOFF

Ш

PWM signal Ш BLON

Ш

PWM signal Ш VBL

Tentative

V

BL

V

BLON

EPWM

IPWM

9

Toff

%/

Tf1

9

%/

Tr1

9

%/

9

%/

2.0V

0.8V

3.3V

2.0V

0.8V

Ton

PWM

T

Backlight on duration

Tr

Ext. Dimming Function

T

PWMR

Floating

T

Ton1

Tf

PWMF

Floating

Int. Dimming Function

0

V

W

External

PWM

Period

External

PWM Duty

100%

Minimun

Duty

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4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

ODD_RIN0+/ODD_RIN1+/ODD_RIN2+/ODD_RIN3+/ODD_RIN4+/ODD_CLK+/-

EVEN_RIN0+/EVEN_RIN1+/EVEN_RIN2+/EVEN_RIN3+/EVEN_RIN4+/EVEN_CLK+/-

MEN MCFG 0 MCFG 1 LVDS8b GV_mode SELLVDS ODSEL

(FI-RE51S-HF (JAE)) or equivalent

INPUT CONNECTOR

VIN GND

FRAME

BUFFER

MEMC

DC/DC CONVERTER

& REFERENCE VOLTAGE

GENERATOR

TIMING

CONTROLLER

FRAME

BUFFER

Tentative

SCAN DRIVER

TFT LCD PANEL

(1920x3x1080)

DATA DRIVER (RSDS

VBL

GND

Status

E_PWM

I_PWM

BLON

Driving board CONNECTOR

CN1:

CI0114M1HR0-LF

(CvilLux) or

S14B-PH-SM3-1B

(JST)

CN3, CN14: 51281-0994 (Molex)

LED

BACKLIGHT

UNIT

Driving board

CONNECTOR

CN2:

CI0112M1HR0-LF

(CvilLux) or

S12B-PH-SM3-TB

(JST)

VBL

GND

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5 .INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module

CNF1 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)

Pin Name Description Note

1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 N.C. No Connection 8 N.C. No Connection

9 GND Ground 10 CH3_0N Third Pixel Negative LVDS differential data input. Channel 0 11 CH3_0P Third Pixel Positive LVDS differential data input. Channel 0 12 CH3_1N Third Pixel Negative LVDS differential data input. Channel 1 13 CH3_1P Third Pixel Positive LVDS differential data input. Channel 1 14 CH3_2N Third Pixel Negative LVDS differential data input. Channel 2 15 CH3_2P Third Pixel Positive LVDS differential data input. Channel 2 16 GND Ground 17 CH3_CLKN 18 CH3_CLKP 19 GND Ground 20 CH3_3N Third Pixel Negative LVDS differential data input. Channel 3 21 CH3_3P Third Pixel Positive LVDS differential data input. Channel 3 22 CH3_4N Third Pixel Negative LVDS differential data input. Channel 4 23 CH3_4P Third Pixel Positive LVDS differential data input. Channel 4 24 N.C. No Connection 25 N.C. No Connection 26 CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0 27 CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0 28 CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1 29 CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1 30 CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2 31 CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2 32 GND Ground 33 CH4_CLKN 34 CH4_CLKP 35 GND Ground 36 CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3 37 CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3 38 CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4 39 CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4 40 N.C. No Connection 41 N.C. No Connection

Third Pixel Negative LVDS differential clock input. Third Pixel Positive LVDS differential clock input.

Fourth Pixel Negative LVDS differential clock input. Fourth Pixel Positive LVDS differential clock input.

Tentative

(1)

(4)

(1)

(4)

(1)

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CNF2 Connector Pin Assignment (FI-RE51S-HF (JAE) or equivalent )

Pin Name Description Note

1 N.C. No Connection

2 N.C. No Connection

3 N.C. No Connection

4 N.C. No Connection

5 ODSEL Overdrive Lookup Table Selection (3)

6 N.C. No Connection (1)

7 SELLVDS LVDS data format Selection (2)

8 N.C. No Connection

9 N.C. No Connection 10 N.C. No Connection 11 GND Ground 12 CH1_0N First Pixel Negative LVDS differential data input. Channel 0 13 CH1_0P First Pixel Positive LVDS differential data input. Channel 0 14 CH1_1N First Pixel Negative LVDS differential data input. Channel 1 15 CH1_1P First Pixel Positive LVDS differential data input. Channel 1 16 CH1_2N First Pixel Negative LVDS differential data input. Channel 2 17 CH1_2P First Pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 CH1_CLKN 20 CH1_CLKP 21 GND Ground 22 CH1_3N First Pixel Negative LVDS differential data input. Channel 3 23 CH1_3P First Pixel Positive LVDS differential data input. Channel 3 24 CH1_4N First Pixel Negative LVDS differential data input. Channel 4 25 CH1_4P First Pixel Positive LVDS differential data input. Channel 4 26 N.C. No Connection 27 N.C. No Connection 28 CH2_0N Second Pixel Negative LVDS differential data input. Channel 0 29 CH2_0P Second Pixel Positive LVDS differential data input. Channel 0 30 CH2_1N Second Pixel Negative LVDS differential data input. Channel 1 31 CH2_1P Second Pixel Positive LVDS differential data input. Channel 1 32 CH2_2N Second Pixel Negative LVDS differential data input. Channel 2 33 CH2_2P Second Pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 CH2_CLKN 36 CH2_CLKP Second Pixel Positive LVDS differential clock input. 37 GND Ground 38 CH2_3N Second Pixel Negative LVDS differential data input. Channel 3 39 CH2_3P Second Pixel Positive LVDS differential data input. Channel 3

40 CH2_4N Second Pixel Negative LVDS differential data input. Channel 4

41 CH2_4P Second Pixel Positive LVDS differential data input. Channel 4 42 N.C. No Connection 43 N.C. No Connection 44 GND Ground 45 GND Ground

First Pixel Negative LVDS differential clock input. First Pixel Positive LVDS differential clock input.

Second Pixel Negative LVDS differential clock input.

(1)

(4)

(1)

(4)

(1)

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46 GND Ground 47 N.C. No Connection (1) 48 Vin Power input (+12V) 49 Vin Power input (+12V) 50 Vin Power input (+12V) 51 Vin Power input (+12V)

Note (1) Please be reserved to open.

Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to +3.3V.

Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with

the frame rate to optimize image quality.

ODSEL Note

L Lookup table was optimized for 120 Hz frame rate.

H Lookup table was optimized for 100 Hz frame rate.

Note (4) LVDS 4-Port Data Mapping

Port CH of LVDS Data Stream

1st Port First pixel 1, 5, 9, ..........., 1913, 1917

2nd Port Second pixel 2, 6, 10, ........., 1914, 1918

3rd Port Third pixel 3, 7, 11, ........., 1915, 1919

4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN3-CN13: SM02-BDAS-3-TB (JST) Pin Name Description Wire Color

1 HV High Voltage Pink 2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model SM02-BDAS-3-TB,

manufactured by JST.

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5.3 DRIVING BOARD UNIT

CN1(Header): CI0114M1HR0-LF (CviLux)

Pin № Symbol Feature

1

2

3

4

5

6

7

8

9

10

11 Status

12 E_PWM

13 I_PWM

VBL +24V

GND GND

Normal (3.3V) Abnormal (0V)

External PWM

Control

Internal PWM

Control

Tentative

14 BLON BL ON/OFF

Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.

Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.

Note (3) Pin 12 and Pin 13 can’t open in the same period.

Pin № Symbol Feature

1

2

3

4

5

6

7

8

9

10

VBL +24V

GND GND

11 NC NC

12 NC NC

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5.4 BLOCK DIAGRAM OF INTERFACE

51

Ө

100pF

Ө

100pF

Ө

51

Ө

100pF

Ө

100pF

Ө

100pF

Ө

100pF

Ө

RXAe+

RXAe-

RXBe+

RXBe-

RXCe+

RXCe-

RXDe+

RXDe-

RXEe+

RXEe-

RXCLKe+

RXCLKe-

PLL

Rx-OUT

ER0-ER9

EG0-EG9

EB0-EB9

DE

OR0-OR9

OG0-OG9

OB0-OB9

DCLK

Timing Controller

Tentative

RXAo+

RXAo-

RXBo+

RXBo-

RXCo+

RXCo-

RXDo+

RXDo-

RXEo+

RXEo-

RXCLKo+

RXCLKo-

51

Ө

100pF

Ө

100pF

Ө

51

Ө

100pF

Ө

100pF

Ө

100pF

Ө

100pF

Ө

PLL

LVDS Input

LVDS Receiver

17

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ER0~ER9 : Even pixel R data

EG0~EG9 : Even pixel G data

EB0~EB9 : Even pixel B data

OR0~OR9 : Odd pixel R data

OG0~OG9: Odd pixel G data

OB0~OB9 : Odd pixel B data

DE : Data enable signal

DCLK : Data clock signal

Note (1) The system must have the transmitter to drive the module.

Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is

used differentially.

18

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5.5 LVDS INTERFACE

VESA Format : SELLVDS = L or Open

JEIDA Format : SELLVDS = H

Tentative

AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)

AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

RSVD : Reserved

19

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Tentative

5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for

the color. The higher the binary input, the brighter the color. The table below provides the assignment of

color versus data input.

0 0 1 0 1 0 1 1 0 0 0

:

: 0 0 0 0 0 0

:

: 1 1 1

0 0 0

:

: 0 0 0

Data Signal

0

1

0

1

0

1

0

:

0

:

1

0

:

0

1

0

0 1 0 1 1 0 0 0

:

: 0 0 0 0 0 0

:

: 1 1 1

0 0 0

:

: 0 0 0

0

1

0

1

0

:

0

:

1

0

:

0

1

0

1

0

1

0

:

;

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

0

1

0

:

0

:

0

0 0

0

:

1

1 1

1

0

1

0

1

0

:

0

:

0

:

1

Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Color

Black Red Green Blue Cyan Magenta Yel lo w White Red (0) / Dark Red (1) Red (2)

:

: Red (1021) Red (1022) Red (1023) Green (0) / Dark Green (1) Green (2)

:

: Green (1021) Green (1022) Green (1023)

Blue (0) / Dark Blue (1) Blue (2)

:

: Blue (1021) Blue (1022) Blue (1023)

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

1

0

1

0

1

0

:

0

:

0

Red Green Blue

0

1

0

1

0

:

1

0

:

0

:

0

1

0

1

0

:

1

0

:

0

:

0

1

0

1

0

1

0

1

0

:

1

0

1

0

1

0

:

0

:

0

Note (1) 0: Low Level Voltage, 1: High Level Voltage

0 0 1 0 1 0 1 1 0 0 0

:

: 0 0 0 0 0 0

:

: 1 1 1

0 0 0

:

: 0 0 0

0

1

0

1

0

:

0

:

0

1

0

1

0

:

1

0

1

0

1

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

Frequency 1/Tc 60 74.25 78 MH

LVDS Receiver Clock

LVDS Receiver Data

Vertical Active Display Term

Horizontal Active Display Term

Input cycle to cycle jitter Setup Time Tlvsu 600 - - ps Hold Time Tlvhd 600 - - ps -

Frame Rate

Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb Display Tvd 1080 1080 1080 Th Blank Tvb 35 45 55 Th Total Th 525 550 575 Tc Th=Thd+Thb

Display

Blank Thb 45 70 95 Tc -

Trcl - - 200 ps -

Thd 480 480 480 Tc 4ch-LVDS

117 120 123

94 100 106

Tentative

Z

Hz

-

interface

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram

below.

10ms

50ms

ЉЉЉЉ

T4

0V

0.5

ЉЉЉЉ

T

1

ЉЉЉЉ

T

2

ЉЉЉЉ

T

3

ЉЉЉЉ

0

500ms

0.1V

CC

T

3

T1

2

T

LVDS Signals

0V

Power On

VALID

Power Off

0

ЉЉЉЉ

T

7

ЉЉЉЉ

T2

T8

T7

0

Option Signals

(SELLVDS…)

0.1V

T

cc

T4

8

Backlight (Recommended)

ЉЉЉЉ

500ms

100ms

T5

ЉЉЉЉ

T

6

50%

5

T

50%

6

T

Note:

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal

screen.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on period.

(5) Interface signal shall not be kept at high impedance when the power is on.

Power ON/OFF Sequence

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage VCC 12V V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" LED Current IL

25±2

50±10

60.0±

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR (3000) (4000) - - Note (2)

Response Time

Center Luminance of White L

White Variation Cross Talk CT - - (4) % Note (5)

Red

Green Color Chromaticity

Viewing Angle

Blue

White

Color Gamut

Horizontal

Vertical

Gray to

gray

C

δW

=0°, θY =0°

θ

Rx (0.658) Ry Gx (0.294) Gy Bx (0.151) -

By Wx Wy

θx+

θ

-

x

θY+

θ

-

Y

x

Viewing angle at

normal direction

CR≥20

- (4.5) 9 ms Note (3)

(350) (450) -

- - (1.3) - Note (7)

(0.319)

Typ.-

0.03

(76) (80) - % NTSC

(0.622)

(0.059)

0.280

0.290

80 88 80 88 80 88 80 88 -

Typ.+

0.03

o

C

%RH

mA

cd/

Note (4)

2

m

-

Note (6)

-

Deg. Note (1)

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Note (1) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Eldim EZ-Contrast 160R

θX- = 90º

6 o’clock

θ

y-

= 90º

x-

y-

Normal

θx = θy = 0º

θy- θy+

θx−

θx+

y+

12 o’clock direction

θ

y+

= 90º

x+

θX+ = 90º

Tentative

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L1023 / L0

L1023: Luminance of gray level 1023

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Note (3) Definition of Gray to Gray Switching Time :

Optical

Response

100%

90%

10%

0%

Gray to gray switching time

Time

The driving signal means the signal of gray level 0, 255,511,767,and 1023.

Gray to gray average time means the average switching time of gray level 0, 255, 511, 767, 1023 to each

other .

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Note (4) Definition of Luminance of White (L

Measure the luminance of gray level 1023 at center point.

LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

CT = | Y

– YA | / YA × 100 (%)

B

Where:

Y

= Luminance of measured location without gray level 0 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 0 pattern (cd/m2)

B

(0, 0)

Active Area

Gray 0

Y

(D/8,W/2)

A, L

Gray 512

Y

(D/2,7W/8)

A, D

Y

A, R

D, W

A, U

):

C

(D/2,W /8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W/8)

B, D

0, 0

Tentative

Active Area

Y

(D/2,W /8)

B, U

Y

(7D/8,W/2)

Gray 0

B, R

(3D/4,3W/4)

(D, W)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting backlight for 1 hour in a windless room.

LCD Module

LCD Panel

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (7) Definition of White Variation (δW):

Measure the luminance of gray level 1023 at 5 points

δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Vertical Line

W

W/4

W/2

3W /4

Horizontal Line

D

D/4 D/2 3D/4

1 2

: Test Point

5

3 4

X

X=1 to 5

Tentative

Active Area

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8. DEFINITION OF LABELS

8.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

V546H1-LE1 Rev. XX

CHI MEI

OPTOELECTRONICS

X X X X X X X Y M D L N N N N

V546H1-LE1 Rev. XX

CHI MEI

OPTOELECTRONICS

X X X X X X X Y M D L N N N N

E207943

MADE IN Taiwan

MADE IN TAIWAN

GEMN ROHS

E207943

MADE IN CHINA

MADE IN TAIWAN

CAPG

ROHS

(a) Model Name: V546H1-LE1

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

(c) CMO barcode definition:

Serial ID: XX-XX-X-XX-YMD-L-NNNN

Code Meaning Description

XX CMO internal use XX Revision Cover all the change

X-XX CMO internal use -

Year, month, day

YMD

NNNN Serial number Manufacturing sequence of product

L Product line # Line 1=1, Line 2=2, Line 3=3, …

Year: 2001=1, 2002=2, 2003=3, 2004=4… Month: Jan. ~ Dec.=1, 2, 3, ~, 9, A, B, C

st

Day: 1

to 31st =1, 2, 3, ~, 9, A, B, C, ~, W, X, Y, exclude I, O, and U

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9. Packaging

9.1 PACKING SPECIFICATIONS

(1) 3 LCD TV modules / 1 Box

(2) Box dimensions: 1334(L) X 284 (W) X 856 (H)

(3) Weight: approximately 48 Kg (3 modules per box)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

Anti-sta tic Bag

Tentative

Carton

PP Belt

Cushion(Bottom)

Carton Label

Figure.9-1 packing method

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Sea & Land Transportation Air Transportation Gross : 399Kg Gross : 207Kg

(L1130*50mm*50mm)

Film

PP Belt

(L1150*W1345*H140mm)

Figure. 9-2 Packing method

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10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling

with the inverter. Do not disassemble the module or insert anything into the backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

10.3 SAFETY STANDARDS

The LCD module should be certified with safety regulations as follows:

Regulatory Item Standard

UL UL 60950-1: 2003

Information Technology equipment

cUL CAN/CSA C22.2 No.60950-1-03

CB IEC 60950-1:2001

UL

UL 60065: 2003

Audio/Video Apparatus

If the module displays the same pattern for a long period of time, the phenomenon of image sticking may be

occurred.

cUL CAN/CSA C22.2 No.60065-03

CB

IEC 60065:2001

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11. MECHANICAL CHARACTERISTIC

Tentative

ڻႝηިҽԖ Ϧљ

CHI MEI

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ڻႝηިҽԖϦљ

CHI MEI

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CMO V546H1-LE1 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual