CMO V520H1-L08 Specification

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A

TFT LCD Approval Specification

MODEL NO.: V520H1 - L08

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Customer:

pproved by:

Note:

Approved By

TV Head Division

LY Chen

QRA Dept. Product Development Div.

Reviewed By

Tomy Chen WT Lin

LCD TV Marketing and Product

Prepared By

Ken Wu Sabrina Lin

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

- CONTENTS -

1. GENERAL DESCRIPTION ------------------------------------------------------- 4

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 6

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 PACKAGE STORAGE

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

2.3.2 BACKLIGHT INVERTER UNIT

3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 8

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

3.2.1 CCFL

3.2.2 INVERTER CHARACTERISTICS

3.2.3 INVERTER INTERFACE CHARACTERISTICS

(Cold Cathode Fluorescent Lamp) CHARACTERISTICS

4. BLOCK DIAGRAM -------------------------------------------------------14

4.1 TFT LCD MODULE

5. INPUT TERMINAL PIN ASSIGNMENT ---------------------------------------------------------15

5.1 TFT LCD MODULE INPUT

5.2 BACKLIGHT UNIT

5.3 INVERTER UNIT

5.4 BLOCK DIAGRAM OF INTERFACE

5.5 LVDS INTERFACE

5.6 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING ------------------------------------------------------- 23

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 26

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. PRECAUTIONS ------------------------------------------------------- 30

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

8.2 SAFETY PRECAUTIONS

8.3 SAFETY STANDARDS

9. REGULATORY STANDARD -------------------------------------------------------30

9.1 SAFETY

10. PACKAGING -------------------------------------------------------31

10.1 PACKING SPECIFICATIONS

10.2 PACKING METHOD

11. MECHANICAL CHARACTERISTICS

------------------------------------------------------33

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REVISION HISTORY

Version Date Page Section Description

Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Ver 2.0

Ver 2.1

Oct.25, 2007

Mar.25,2008

All

P4

P10

P26

All

1.4

3.2.1

3.2.2

7.2

Approval Specification was first issued.

Modified Surface Treatment

Modified CCFL CHARACTERISTICS

Modified INVERTER CHARACTERISTICS

Modified

OPTICAL SPECIFICATIONS

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V520H1-L08 is a 52” TFT Liquid Crystal Display module with 28-CCFL Backlight unit and 2ch-LVDS

interface. This module supports 1920 x 1080 HDTV format and can display true 16.7M colors (8-bit/color).

The inverter module for backlight is built-in.

1.2 FEATURES

- High brightness (500 nits)

- High contrast ratio (1500:1)

- Fast response time (Gray to gray average 6.5 ms)

- High color saturation (NTSC 72%)

- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

- DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Optimized response time for 50/60 Hz frame rate

- Ultra wide viewing angle : Super MVA technology

- RoHS compliance

1.3 APPLICATION

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

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- Standard Living Room TVs.

- Public Display Application.

- Home Theater Application.

- MFM Application.

1.4 GENERAL SPECIFICATIONS

Item Specification Unit Note Active Area 1152 x 648 (52.037”) mm Bezel Opening Area 1166.0x662.0 mm Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.2 (H) x 0.6 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 16.7M color -

Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 11 for more information about the front and

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to

Glare coating(Reflection ratio<1.5%)

Hard coating (3H)

- (2)

(1)

change this feature.

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1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) 1224.5 1226 1227.5 mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

Vertical (V) 718.0 719.2 720.4 mm

Depth (D)

Weight 19600 g -

To inv cover 56.0 57.5 59.0 mm To rear plate 38.5 40 41.5 mm

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Model No.:V520H1-L08

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(1), (2)

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature T Operating Ambient Temperature T

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

NOP

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Value

Min. Max.

ST

OP

±X, ±Y 40

±Z

NOP

-20 +60 ºC (1) 0 50 ºC (1), (2)

-

- 1.0 G (4), (5)

30

Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Unit Note

G (3), (5)

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in final product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in final product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

the module would not be twisted or bent by the fixture.

Relative Humidity (%RH)

100 90

80

60

Operating Range

40

20

10

-40 -20 40020 6080

Storage Range

Temperature (ºC)

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2.2 Package storage

When storing modules as spares for a long time, the following precaution is necessary.

(a) Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to

store the module with temperature from 0 to 35кat normal humidity without condensation.

(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent

light.

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Item Symbol

Power Supply Voltage V

Logic Input Voltage V

CC

IN

Min. Max.

-0.3 13.5 V

-0.3 3.6 V

Value

Unit Note

(1)

2.3.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage V

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional

operation should be restricted to the conditions described under normal operating conditions.

W

Valu e

Min. Max.

Ё

3000 V

Unit Note

RMS

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)

Parameter Symbol Power Supply Voltage V

Power Supply Ripple Voltage V Rush Current I

White - 1.5 2.1 A

Power Supply Current

Differential Input High

Differential Input Low

LVDS Interface

Common Input Voltage

Terminating Resistor

CMOS interface

Input High Threshold Voltage

Input Low Threshold Voltage

Black - 0.6 - A Vertical Stripe

Threshold Voltage

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Min. Typ. Max.

10.8 12 13.2 V (1)

- - 350 mV

- - 4.5 A (2)

- 1.1 - A

- - 100 mV

-100 - - mV

1.125 1.25 1.375 V

T

- 100 - ohm

2.7 - 3.3 V

0 - 0.7 V

RUSH

I

V

LVT H

V

LVT L

V

R

V

CC

RP

CC

LVC

IH

IL

Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Value

Unit Note

(3)

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

(High to Low)

(Control Signal)

SW

+24V

Vs (12V)

R1

47K

R2

1K

47K

VR1

C1

1uF

Q1 2SK1475

FUSE

Q2

2SK1470

C2

0.01uF

Vcc rising time is 470us

Vcc

C3

1uF

Vcc

(LCD Module Input)

0.9Vcc

0.1Vcc

GND

470us

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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,

whereas a power dissipation check pattern below is displayed.

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

a. White Pattern

Active Area

c. Vertical Stripe Pattern

b. Black Pattern

Active Area

R

G

B

R

G

B

R

G

B

R

RR

G

B

R

Active Area

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3.2 BACKLIGHT UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)

Parameter Symbol

Lamp Input Voltage V Lamp Current I

Lamp Turn On Voltage V

Operating Frequency F Lamp Life Time L

3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)

Parameter Symbol

L

S

L

BL

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Issue Date: Mar.25.2008

Model No.:V520H1-L08

Value

Min. Typ. Max.

-

1600

-V

5.5 6.0 6.5 mA

- - 2550 V

- - 2350 V

40 - 70 KHz (3)

50,000 - - Hrs (4)

Valu e

Min. Typ. Max.

Unit Note

RMS

(1)

(2), Ta = 0 ºC

(2), Ta = 25 ºC

Unit Note

Approval

-

Power Consumption P

Power Supply Voltage V Power Supply Current I

BL

Input Ripple Noise - - - 912 mV Oscillating Frequency F Dimming frequenc Minimum Duty Ratio D

F

W

B

MIN

- 288 317 W (5), IL =6.0mA

22.8 24 25.2 V

DC

- 12 - A Non Dimming

P-P

VBL=22.8V

48 50 52 kHz

150 160 170 Hz

-20-%

Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring

master and slave board:

Note (2) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

2к and I

Note (3) The power supply capacity should be higher than the total inverter power consumption P

= 5.5 ~ 6.5 mArms.

L

. Since

BL

the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current

changed as PWM duty on and off. The transient response of power supply should be considered

for the changing loading when inverter dimming.

Note (4) The measurement condition of Max. value is based on 52" backlight unit under input voltage 24V,

average lamp current 6.3 mA and lighting 30 minutes later.

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Model No.:V520H1-L08

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Inverter

(Master)

A A

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

LCD Module

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

Inverter

(Slave 2)

Inverter

(Slave 1)

A A

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

A

1 2

A

1 2

A

1 2

A

1 2

A

Inverter

(Slave 3)

A

1 2

A

1 2

A

1 2

A

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3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Parameter Symbol

On/Off Control Voltage

Internal/External PWM Select Voltage

Voltage

VBL Rising Time Tr1 Ё 30 Ё 50 ms

VBL Falling Time Tf1 Ё 30 Ё 50 ms

Control Signal Rising Time Tr

Control Signal Falling Time Tf

PWM Signal Rising Time T

PWM Signal Falling Time T

Input impedance R

PWM Delay Time T

BLON Delay Time T

BLON Off Time T

ON

OFF

HI

LO

MAX 2.85 3.0 3.15 V maximum duty ratioInternal PWM Control

MIN

HI 2.0

LO

V

BLON

SEL

IPWM

EPWM

PWMR

PWMF

IN

PWM

on

off

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Ё

Valu e

Ё

0

Ё

Ё-

0

Ё

0

Ё

0

Ё

5.0 V

0.8 V

5.0 V

0.8 V

Ё

5.0 V duty on External PWM Control

0.8 V dut

100 ms

50 us

1

ЁЁMӨ

Te st

Condition

Ё

Min. Typ. Max.

2.0

Ё Ё

2.0

Ё

V

= L

SEL

V

= H

SEL

ЁЁЁ

Ё

Ё 100 Ё 300 ms Ё 300 Ё 500 ms Ё 300 Ё 500 ms

Issue Date: Mar.25.2008

Model No.:V520H1-L08

Approval

Unit Note

V minimum dut

off

See as below

ratio

Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change

the internal/external PWM selection (SEL) during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure.

Note (3) The power sequence and control signal timing must follow the figure below. For a certain reason,

the inverter has a possibility to be damaged with wrong power sequence and control signal

timing.

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V

VBLON

VSEL

V

EPWM

V

IPWM

Tr1

BL

2.0V

0.8V

2.0V

0.8V

3.0V

2.0V

Ton

Backlight on duration

Tr

Ext. Dimming Function

TPWMR

PWM

T

Tf

Int. Dimming Function

PWMF

0

Tf1

Toff

V

W

External

PWM

Period

External

PWM Duty

100%

Minimun

Duty

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(

)

4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

ERX0(+/-)

ERX1(+/-)

ERX2(+/-)

ERX3(+/-)

ECLK(+/-)

DCLK(+/-)

DE

ORX0(+/-)

ORX1(+/-)

ORX2(+/-)

ORX3(+/-) OCLK(+/-)

Vcc

GND

INPUT CONNECTOR

(FI-RE51S-HF )

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FRAME

BUFFER

TIMING

CONTROLLER

DC/DC CONVERTER

& REFERENCE

VOLTAGE

GENERATOR

SCAN DRIVER

DATA DRIVER

Issue Date: Mar.25.2008

Model No.:V520H1-L08

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TFT LCD PANEL

(1920x3x1080)

RSDS

VBL

GND

SEL

I_PWM

E_PWM

BLON

CN100

CN101: 528520870(Molex)

INVERTER

CONNECTOR

CN100:S14B-PH-SM4

-TB(D)(LF) or

equivalent (Master)

CN102-CN103 , CN201-CN203 , CN301 , CN401: 528521070 (Molex) or equivalent

CN102,CN301: 528521070 (Molex) or equivalent

CN2-CN29:SM02 (12.0)B-BHS-1-TB(LF)(JST)

or equivalent

BACKLIGHT

UNIT

CN200-CN400

INVERTER

CONNECTOR

CN200-CN400:S12B-P

H-SM4-TB(D)(LF) or

Equivalent (Slave)

VBL

GND

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module Input

Pin Name Description Note

1 VCC +12V power supply 2 VCC +12V power supply 3 VCC +12V power supply 4 VCC +12V power supply 5 VCC +12V power supply 6 GND Ground 7 GND Ground 8 GND Ground

9 GND Ground 10 ORX0- Odd pixel Negative LVDS differential data input. Channel 0 11 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0 12 ORX1- Odd pixel Negative LVDS differential data input. Channel 1 13 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1 14 ORX2- Odd pixel Negative LVDS differential data input. Channel 2 15 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2 16 GND Ground 17 OCLK- Odd pixel Negative LVDS differential clock input. 18 OCLK+ Odd pixel Positive LVDS differential clock input. 19 GND Ground 20 ORX3- Odd pixel Negative LVDS differential data input. Channel 3 21 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3 22 N.C. No Connection 23 N.C. No Connection 24 GND Ground 25 ERX0- Even pixel, Negative LVDS differential data input. Channel 0 26 ERX0+ Even pixel, Positive LVDS differential data input. Channel 0 27 ERX1- Even pixel, Negative LVDS differential data input. Channel 1 28 ERX1+ Even pixel, Positive LVDS differential data input. Channel 1 29 ERX2- Even pixel, Negative LVDS differential data input. Channel 2 30 ERX2+ Even pixel, Positive LVDS differential data input. Channel 2 31 GND Ground 32 ECLK- Even pixel, Negative LVDS differential clock input 33 ECLK+ Even pixel, Positive LVDS differential clock input. 34 GND Ground 35 ERX3- Even pixel, Negative LVDS differential data input. Channel 3 36 ERX3+ Even pixel, Positive LVDS differential data input. Channel 3 37 N.C. No Connection 38 N.C. No Connection 39 GND Ground 40 ODSEL Overdrive Lookup Table Selection (4) 41 DCREN Dynamic Contrast Ratio Enable (3) 42 N.C. No Connection (1) 43 N.C. No Connection (1) 44 N.C. No Connection (1) 45 SELLVDS LVDS Data Format Selection (2) 46 N.C. No Connection 47 N.C. No Connection 48 N.C. No Connection

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49 N.C. No Connection 50 N.C. No Connection 51 N.C. No Connection

Note (1) Reserved for internal use. Please leave it open.

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(1)

Note (2)

Note (3) Low : function disable (default), High :

Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the

Note (5) Low =Open or Connect to GND, High = Connect to +3.3V

Low : JEIDA LVDS Format (default), High : VESA Format.

Dynamic Contrast Ratio function enable

frame rate to optimize image quality.

ODSEL Note

L Lookup table was optimized for 60 Hz frame rate.

H Lookup table was optimized for 50 Hz frame rate.

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN2-CN29: CP042CSC000 (CviLux).

Pin Name Description Wire Color

1 HV High Voltage Pink 2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model CP042CSC000,

manufactured by

CviLux. The mating header on inverter part number is CP042CP1MC0

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

1 HV(Pink)

2 HV(White)

1 HV(Pink)

2 HV(White)

1 HV(Pink)

2 HV(White)

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5.3 INVERTER UNIT

CN100 (Header): S14B-PH-SM4-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

11 SEL

12 E_PWM

13 I_PWM

14 BLON Backlight on/off control

VBL +24V

GND GND

Internal/external PWM selection High : external dimming Low : internal dimming

External PWM control signal E_PWM should be connected to ground when internal PWM was selected (SEL = Low). Internal PWM Control Signal I_PWM should be connected to ground when external PWM was selected (SEL = High).

power input

DC

Issue Date: Mar.25.2008

Model No.:V520H1-L08

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CN200-CN400 (Header): S12B-PH-SM4-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

11

12 NC NC

CN2-CN29 (Header): CP042CPIMC0-LF(CviLux) or equivalent

Pin No. Symbol Description

1 2

VBL +24V

GND GND

NC NC

CCFL HOT CCFL HOT

CCFL high voltage CCFL high voltage

power input

DC

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CN102-CN103 , CN201-CN203 , CN301 , CN401 : 528521070(Molex)

Pin No. Symbol Description

1 Board to Board

2 Board to Board

3 Board to Board

4 Board to Board

5 Board to Board

6 Board to Board 7 Board to Board 8 Board to Board 9 Board to Board

10

CN101: 528520870(Molex)

Pin No. Symbol Description

1 Board to Board

2 Board to Board

3 Board to Board

4 Board to Board

5 Board to Board

6 Board to Board 7 Board to Board 8

Control

Signal

Board to Board

Control

Signal

Board to Board

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C

OB0

OG0

G0-EG

0

r

0

p

OB0

OG0

p

ORx0

0

G0-EG

5.4 BLOCK DIAGRAM OF INTERFACE

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Model No.:V520H1-L08

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ER0-ER7

E

EB

-EB7

DE

OR0-OR7

-OG7

-OB7

D

LK

Host

Graphics

Controller

ERx0+

TxIN

ERx

ERx1+

7

ERx1-

ERx2+

ERx2-

ERx3+

ERx3-

51Ө

51Ө 51Ө

51Ө

100pF

100

100pF

F

-

RxOUT

ER0-ER7

E

EB

-EB7

DE

OR0-OR7

-OG7

7

-OB7

ECLK+

PLL

51Ө

-

100pF

51Ө

PLL

DCLK

Timing

ORx0+

-

ORx1+

ORx1-

51Ө

100pF

100

F

Controlle

LVDS Transmitter

THC63LVDM83A

(LVDF83A)

PLL

ORx2+

ORx2-

ORx3+

ORx3-

OCLK+

19

51Ө

100pF

51Ө 51Ө

100pF

51Ө

-

100pF

51Ө

LVDS Receiver

PLL

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ER0~ER7 : Even pixel R data

EG0~EG7 : Even pixel G data

EB0~EB7 : Even pixel B data

OR0~OR7 : Odd pixel R data

OG0~OG7: Odd pixel G data

OB0~OB7 : Odd pixel B data

DE : Data enable signal

DCLK : Data clock signal

Notes: (1) The system must have the transmitter to drive the module.

(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line

when it is used differentially.

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(3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel

and the second pixel is even pixel.

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5.5 LVDS INTERFACE

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SIGNAL

LVDS _SEL =HLVDS _SEL =

R0

R1

R2

R3

R4

R5

G0

G1

G2

G3

G4

G5

B0

B1

B2

24bit

B3

B4

B5

DE

R6

R7

G6

G7

B6

B7

RSVD 1

RSVD 2

RSVD 3

DCLK 31 TxCLK IN TxCLK

L or OPEN

R2

R3

R4

R5

R6

R7

G2

G3

G4

G5

G6

G7

B2

B3

B4

B5

B6

B7

DE

R0

R1

G0

G1

B0

B1

RSVD 1

RSVD 2

RSVD 3

TRANSMITTER

THC63LVDM83A

PIN INPUT Host TFT-LCD PIN OUTPUT

51

52

54

55

56

3

4

6

7

11

12

14

15

19

20

22

23

24

30

50

2

8

10

16

18

25

27

28

TxIN0

TxIN1

TxIN2

TxIN3

TxIN4

TxIN6

TxIN7

TxIN8

TxIN9

TxIN12

TxIN13

TxIN14

TxIN15

TxIN18

TxIN19

TxIN20

TxIN21

TxIN22

TxIN26

TxIN27

TxIN5

TxIN10

TxIN11

TxIN16

TxIN17

TxIN23

TxIN24

TxIN25

INTERFACE

CONNECTOR

TA OUT0 +

TA OUT0 -

TA OUT1 +

TA OUT1 -

TA OUT2 +

TA OUT2 -

TA OUT3 +

TA OUT3 -

OUT+

TxCLK

OUT-

Rx 0+

Rx 0-

Rx 1+

Rx 1-

Rx 2+

Rx 2-

Rx 3+

Rx 3-

RxCLK

IN+

RxCLK

IN-

RECEIVER

THC63LVDF84A

27

Rx OUT0

29

Rx OUT1

30

Rx OUT2

32

Rx OUT3

33

Rx OUT4

35

Rx OUT6

37

Rx OUT7

38

Rx OUT8

39

Rx OUT9

43

Rx OUT12

45

Rx OUT13

46

Rx OUT14

47

Rx OUT15

51

Rx OUT18

53

Rx OUT19

54

Rx OUT20

55

Rx OUT21

1

Rx OUT22

6

Rx OUT26

7

Rx OUT27

34

Rx OUT5

41

Rx OUT10

42

Rx OUT11

49

Rx OUT16

50

Rx OUT17

2

Rx OUT23

3

Rx OUT24

5

Rx OUT25

26 RxCLK

OUT

TFT CONTROL INPUT

LVDS _SEL=HLVDS _SEL =

L or OPEN

R0

R1

R2

R3

R4

R5

G0

G1

G2

G3

G4

G5

B0

B1

B2

B3

B4

B5

DE

R6

R7

G6

G7

B6

B7

NC

DCLK

R2

R3

R4

R5

R6

R7

G2

G3

G4

G5

G6

G7

B2

B3

B4

B5

B6

B7

DE

R0

R1

G0

G1

B0

B1

NC

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R0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)

B0~B7: Pixel B Data (7; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.

5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the

color. The higher the binary input, the brighter the color. The table below provides the assignment of the

color versus data input.

Color

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black Red

Green Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue

Cyan

Magenta

Yellow

White

Red (0) / Dark

Red (1)

Red (2)

:

: Red (253) Red (254) Red (255) Green (0) / Dark Green (1) Green (2)

:

: Green (253) Green (254) Green (255) Blue (0) / Dark Blue (1) Blue (2)

:

: Blue (253) Blue (254) Blue (255)

0

1

0

1

0

:

1

0

:

0

0 0

0

:

0

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Model No.:V520H1-L08

Data Signal

Red Green Blue

0

1

0

1

0

1

0

1

0

1

0

1

0

:

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

1

1 0

0 0

0

: :

0

0 0

0

1 0

1

: :

1

0

1

1 0

0 0

0

: :

0

1

0

1

0

:

0

:

0

:

1

Approval

0

1

0

1

0

:

0

:

0

:

1

0

1

0

1

0

:

0

:

0

1

0

1

0

:

1

0

1

0

1

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

Frequency 1/Tc 60 74 80 MHZ -

LVDS Receiver Clock

LVDS Receiver Data

Vertical Active Display Term

Horizontal Active Display Term

Note (1) (ODSEL) = (H) , (L). Please refer to 5.1 for detail information.

Input cycle to cycle jitter Setup Time Tlvsu 600 - - ps Hold Time Tlvhd 600 - - ps -

Frame Rate

Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb Display Tvd 1080 1080 1080 Th Blank Tvb 35 45 55 Th Total Th 1050 1100 1150 Tc Th=Thd+Thb Display Thd 960 960 960 Tc Blank Thb 90 140 190 Tc -

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Trcl - - 200 ps -

Fr5 47 50 53 Hz (1)

6 57 60 63 Hz (1)

Fr

Approval

Note (2) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low

logic level. Otherwise, this module would operate abnormally.

INPUT SIGNAL TIMING DIAGRAM

Tv

DE

DCLK

DE

Tvd

T

h

T

c

hb

T

hd

T

vb

T

DATA

Valid display data ( 960 clocks)

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LVDS INPUT INTERFACE TIMING DIAGRAM

RXCLK+

RXn+/-

Tlvsu

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Tc

Tlvhd

1T‘ 14

3T‘ 14

5T‘ 14

7T‘ 14

9T‘ 14

11T‘

14

13T‘

14

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Љ

6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram

below.

Power Supply

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0.9 VCC

Issue Date: Mar.25.2008

Model No.:V520H1-L08

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0.9 V

CC

V

0.5ЉT1Љ10ms

0

500ms

CC

0V

2

50ms

T

3

50ms

T

4

T

Signals

0V

Backlight (Recommended)

500ms

100msЉT6

T5

0.1V

CC

2

T

VALI D

Power On

50%

T

5

Power ON/OFF Sequence

50%

T

6

T3T1

Power Off

0.1V

cc

T4

Note.

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal

screen.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on period.

(5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Lamp Current I Oscillating Frequency (Inverter) F Vertical Frame Rate Fr 60 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio

Response Time

Center Luminance of White L

White Variation

Cross Talk CT 4 % Note (5)

Red

Green

Color

Chromaticity

Viewing

Angle

Blue

White

Color Gamut C.G

Horizontal

Vertical

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25r2

50r10

CC

L

W

CR 1200 1500

Dynamic

CR

Gray to

gray

C

GW

T

=0q, TY =0q

x

Rx 0.644 Ry

Viewing Angle at Normal Direction

Gx Gy

Bx

By Wx Wy

Tx+

T

-

x

TY+

T

Y

-

CRt20

12/18 V

6.0r0.2 50r3

6000

6.5 12 ms Note (3)

450 500 cd/m2Note (4)

1.3 - Note (7)

0.332

0.271

Typ.

-0.03

0.592

0.143

Typ.

+0.03

0.068

0.280

0.290 70 72 % NTSC 80 88 80 88 80 88 80 88

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Model No.:V520H1-L08

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o

C

%RH

mA

KHz

- Note (2)

-

Note (6)

-

Deg. Note (1)

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Note (1) Definition of Viewing Angle (Tx, Ty):

Viewing angles are measured by Eldim EZ-Contrast 160R

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Tx = Ty = 0º

yTy-

T

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Model No.:V520H1-L08

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TX- = 90º

6 o’clock

T

y- = 90º

x-

y-

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L255 / L0

L255: Luminance of gray level 255

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Tx

Tx

12 o’clock direction

y+

T

y+ = 90º

x+

T

X+ = 90º

Note (3) Definition of Gray-to-Gray Switching Time:

100%

90%

Optical

Response

10%

0%

Gray to gray Switching time

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.

Gray to gray average time means the average switching time of gray level 0, 63,127,191,255 to each

other.

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A

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Note (4) Definition of Luminance of White (LC, L

Measure the luminance of gray level 255 at center point and 5 points

= L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (7).

L

C

Note (5) Definition of Cross Talk (CT):

CT = | Y

– YA | / YAu 100 (%)

B

Where:

Y

= Luminance of measured location without gray level 0 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 0 pattern (cd/m2)

B

ctive Area

Gray 128

Y

A, U

Y

A, R

(D, W)

(D/2,W/8)

(7D/8,W/2)

Y

(D/8,W/2)

A, L

Y

(D/2,7W/8)

A, D

(0, 0)

Note (6) Measurement Setup:

AVE

):

ctive Area

Gray 0

Gray 128

Y

B, U

Y

B, R

(3D/4,3W/4)

(D, W)

(D/2,W/8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W/8)

B, D

(0, 0)

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature

change during measuring. In order to stabilize the luminance, the measurement should be

executed after lighting backlight for 1 hour in a windless room.

LCD Module

LCD Panel

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (7) Definition of White Variation (GW):

Measure the luminance of gray level 255 at 5 points

GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

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Horizontal Line

D

3D/4D/2D/4

W/4

W/2

W

Vertical Line

3W/4

5

Active Area

21

X

: Test Point

X=1 to 5

43

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8. PRECAUTIONS

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

8.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while

assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

9. REGULATORY STANDARDS

9.1

SAFETY

Regulatory Item Standard

UL UL 60950-1: 2003

Information Technology equipment

Audio/Video Apparatus

cUL CAN/CSA C22.2 No.60950-1-03

CB IEC 60950-1:2001 UL UL 60065: 2003

cUL CAN/CSA C22.2 No.60065-03

CB

IEC 60065:2001

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10. PACKAGING

10.1 PACKING SPECIFICATIONS

(1) 2 LCD TV modules / 1 Box

(2) Box dimensions : 1334(L) X 284 (W) X 856 (H)

(3) Weight : approximately 46Kg (2 modules per box)

10.2 PACKING METHOD

Figures 10-1 and 10-2 are the packing method

LCD TV Module

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Anti-static Bag

4pcs Drier

Cushion(Bottom)

Carton

PP Belt

Carton Label

Figure.10-1 packing method

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Sea & Land Transportation

(L1130*50mm*50mm)

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Film

(L1150*W1345*H140mm)

PP Belt

Figure. 10-2 Packing method

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11. MECHANICAL CHARACTERISTICS

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奇美電子股份有限公司

%*+/'+

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CMO V520H1-L08 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual