CMO V470K1-L01 Specification

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Issue Date: Aug. 13,2007

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Model No.: V470K1-L01

Preliminary

TFT LCD Preliminary Specification

MODEL NO.: V470K1 - L01

Customer:

Approved by:

Note:

Approved By

QRA Dept. Product Development Div.

Reviewed By

Tomy Chen WT Lin

LCD TV Marketing and Product Management Div.

Prepared By

Ken Wu Marcus Chang

TV Head Division

LY Chen

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- CONTENTS -

REVISION HISTORY

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

2.2.2 BACKLIGHT INVERTER UNIT

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

3.2.1 CCFL

3.2.2 INVERTER CHARACTERISTICS

3.2.3 INVERTER INTERTFACE CHARACTERISTICS

(Cold Cathode Fluorescent Lamp)

CHARACTERISTICS

4. BLOCK DIAGRAM

4.1 TFT LCD MODULE

5. V470K1-L01 LCD INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE LVDS input

5.2 TFT LCD MODULE Power input

5.3 BACKLIGHT UNIT

5.4 INVERTER UNIT

5.5 BLOCK DIAGRAM OF INTERFACE

5.6 LVDS INTERFACE

5.7 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING -

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS -

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. PRECAUTIONS -

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

8.2 SAFETY PRECAUTIONS

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3

4

5

7

13

14

24

27

31

9. Definition of labels --

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10. PACKAGING --

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11. MECHANICAL CHARACTERISTICS ---

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REVISION HISTORY

Version Date

Page

(New)

Section Description

Ver. 1. 0

Aug.13,’07

All

Preliminary Specification was first issued.

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V470K1-L01 is a 47” TFT Liquid Crystal Display module with 24-CCFL Backlight unit and 4ch-LVDS

interface. This module supports 2560 x 1440 QFHD format and can display true 16.7M colors (8-bit/color).

The inverter module for backlight is built-in.

1.2 FEATURES

- High brightness (450 nits)

- High contrast ratio (1500:1)

- Fast response time (Gray to gray average 6.5ms)

- High color saturation (NTSC 92%)

- QHDTV (2560 x 1440 pixels) resolution, future TV format

- LVDS (Low Voltage Differential Signaling) interface

- Ultra wide viewing angle: LCS MVA technology

- RoHS compliance

1.3 APPLICATION

- High-end Living Room TVs.

- Digital Home TVs

- Public Display Application.

- Home Theater Application.

- High level Application.(Medical,movie,3D….)

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 1040.64(H) x 585.36(V) (47” diagonal) mm Bezel Opening Area 1050.6(H) x 594.4(V) mm Driver Element a-si TFT active matrix - Pixel Number 2560x R.G.B. x 1440 pixel Pixel Pitch 0.4065 (H) x 0.4065(V) mm Pixel Arrangement RGB vertical stripe - Display Colors 16.7M color Display Operation Mode Transmissive mode / Normally black - Surface Treatment HC+LR coating - (2)

Note (1) Please refer to the attached drawings in chapter 11 for more information about the front and

(1)

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to change

this feature.

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) 1095 1096 1097 mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

Vertical (V) 639 640 641 mm Depth (D) 47.1 48.1 49.1 mm

Weight 18500 g -

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 45 ºC (1), (2)

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

X, Y axis - 50 G (3), (5)

NOP

Z axis - 35 G (3), (5)

- 1.0 G (4), (5)

NOP

Min. Max.

Value

Unit Note

(a) 90 %RH Max. (Ta

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in your product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in your product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, and ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

the module would not be twisted or bent by the fixture. The module would not be twisted or bent by the

fixture.

Љ

40 ºC).

10

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.2 V

Logic Input Voltage VIN -0.3 3.6 V

Value

Unit Note

(1)

2.2.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage VW Power Supply Voltage VBL 0 30 V

Ё

Control Signal Level

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

Note (2) No moisture condensation or freezing.

Note (3) The control signals include On/Off Control, Internal PWM Control, External PWM Control and

Internal/External PWM Selection.

Val ue

Min. Max.

Ё

-0.3 7 V

5000 V

Unit Note

RMS

(1)

(1), (3)

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE (

Parameter Symbol

Ta = 25 ± 2 ºC)

Min. Typ. Max.

Power Supply Voltage VCC 11.4 12 12.6 V (1)

Power Supply Ripple Voltage VRP - - 300 mV Rush Current I

White 1.6 2.2 A

Power Supply Current

Black 0.7 A Vertical Stripe

RUSH

-

- - 3.0 A (2)

1.3 A

Differential Input High

Threshold Voltage V

LVT H

- - 100 mV

Differential Input Low

LVDS Interface

Threshold Voltage V

Common Input Voltage

Terminating Resistor

CMOS interface

Input High Threshold Voltage

Input Low Threshold Voltage

V

LVTL

R

V

LVC

IH

IL

-100 - - mV

1.125 1.25 1.375 V

- 100 - ohm

T

2.7 - 3.3 V

0 - 0.7 V

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

+12.0V

Q1 AO4409

R1

200K

Value

FUSE

Unit Note

C3

1uF

Vcc

(LCD Module Input)

(3)

VR1

(Low to High)

(Control Signal)

SW

R2

1K

47K

Q2

2N7002

C1

10uF

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

GND

470us

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Note (3)&(4) The specified power supply current is under the conditions at Vcc = 18 V(Note(3)), Vcc =

12V(Note(4)), Ta = 25 ± 2 ºC, f

a. White Pattern

Active Area

c. Vertical Stripe Pattern

= 60 Hz, whereas a power dissipation check pattern below is displayed.

v

b. Black Pattern

Active Area

R

B

R

B

R R

G

B

R

G

B

R

Active Area

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3.2 BACKLIGHT UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (

Parameter Symbol

Min. Typ. Max. Lamp Input Voltage VL - 1700 - V Lamp Current IL 5.3 5.8 6.3 mA

Lamp Turn On Voltage VS

- - 2550 V

- - 2410 V

Value

Ta = 25 ± 2 ºC)

Unit Note

-

RMS

(2), Ta = 0 ºC

RMS

(2), Ta = 25 ºC

RMS

(1)

Operating Frequency FL 40 - 80 KHz (3) Lamp Life Time LBL 50,000 - - Hrs (4)

3.2.2 INVERTER CHARACTERISTICS (

Parameter Symbol

Power Consumption

Power Supply Voltage VBL 22.8 24 25.2 VDC Power Supply Current IBL - 8.8 A Non Dimming Input Ripple Noise - - - 912 mV

Backlight Turn on Voltage

Oscillating Frequency FW 44 47 50 kHz Dimming frequenc Minimum Duty Ratio D

Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring

P

- 211 221 W (5), IL = 5.8mA

BL

V

BS

F

B

- 20 - %

MIN

Ta = 25 ± 2 ºC)

Val ue

Min. Typ. Max.

2550 2410

- - V

150 160 170 Hz

Unit Note

VBL=22.8V

P-P

Ta = 0 ºC

RMS

Ta = 25 ºC

RMS

master and slave board.:

Note (2) The lamp starting voltage V

should be applied to the lamp for more than 1 second after startup.

S

Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the

display input signals, and it may result in line flow on the display. In order to avoid interference, the

lamp frequency should be detached from the horizontal synchronous frequency and its harmonics

as far as possible.

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

2к

and IL = 5.5 ~ 6.3 mArms.

Note (5) The power supply capacity should be higher than the total inverter power consumption P

. Since

BL

the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current

changed as PWM duty on and off. The transient response of power supply should be considered

for the changing loading when inverter dimming.

Note (6) The measurement condition of Max. value is based on 47" backlight unit under input voltage 24V,

average lamp current 6.1 mA and lighting 30 minutes later.

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Inverter

(Master)

A A

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

LCD Module

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

1 2

A

Inverter (Slavor)

A A

HV(Blue -)

1

HV (Pink -)

2

HV(Blue +)

1

HV (Pink +)

2

HV(Blue -)

1

HV (Pink -)

2

HV(Blue +)

1

HV (Pink +)

2

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

HV (Pink +) HV (White +)

HV (Pink -) HV (White -)

A

1 2

A

1 2

A

1 2

A

1 2

A

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3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Parameter Symbol

On/Off Control Voltage

Internal/External PWM Select Voltage

Voltage

ON

OFF

HI

LO

MA

MIN

HI 2.0

LO

V

BLON

SEL

IPWM

EPWM

Control Signal Rising Time Tr Control Signal FallingTim e Tf

VBL Rising Time Tr1

VBL Falling Time Tf1

PWM Delay Time

T

PW M

Input impedance RIN BLON Delay Time Ton BLON Off Time T

off

Te st

Condition

V

Ё

SEL

Ё

Ё Ё Ё

Ё

Min. Typ. Max.

2.0

= L

= H

100

1 Ё 1 Ё

Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change

Val ue

Ё

0

Ё Ё

Ё

0

Ё

30

1

Ё

Unit Note

-

5.0 V

0.8 V

5.0 V

0.8 V

3.0 V maximum duty ratioInternal PWM Control

0

Ё

Vminimumduty ratio

5.0 V duty onExternal PWM Control

0.8 V duty off 100 ms 100 ms

50

300

Ё

MӨ

Ё

ms

Ё

ms

mS

the internal/external PWM selection (SEL) during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure.

Note (3) The power sequence and control signal timing must follow the figure below. For a certain reason,

the inverter has a possibility to be damaged with wrong power sequence and control signal

timing.

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Tr1

BL

V

Tf1

V

BLON

V

SEL

EPWM

IPWM

V

Toff

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

3.0V

PWM

Ton

Backlight on duration

Tr

Ext. Dimming Function

T

PWMR

PWM

T

Tf

PWMF

T

External

PWM Duty

Int. Dimming Function

0

W

External

Period

100%

Minimun

Duty

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4.

BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

ERX0_R(+/-) ERX1_R(+/-) ERX2_R(+/-) ERX3_R(+/-) ECLK_R(+/-) ORX0_R(+/-) ORX1_R(+/-) ORX2_R(+/-) ORX3_R(+/-) OCLK_R(+/-)

ERX0_L(+/-) ERX1_L(+/-) ERX2_L(+/-) ERX3_L(+/-) ECLK_L(+/-) ORX0_L(+/-) ORX1_L(+/-) ORX2_L(+/-) ORX3_L(+/-) OCLK_L(+/-)

SELLVDS ODSEL

Vcc

GND

(IS050-C51B—C39-A (UJU) or equivalent)

VBL

GND

SEL

I_PWM

E_PWM

BLON

CN1

CN1:S14B-PH-SM3-TB

(D)(LF) or equivalent

INPUT CONNECTOR

INVERTER

CONNECTOR

(Master)

FRAME BUFFER

TIMING

CONTROLLER

DC/DC CONVERTER

& REFERENCE

VOLTAGE

GENERATOR

CN27,CN29: SD-52852-1070(Molex) or equivalent

CN3-CN26:SM02 (12.0)B-BHS-1-TB(LF)(JST)

or equivalent

BACKLIGHT

UNIT

CN28,CN30: SD-52852-1070Molex) or equivalent

SCAN DRIVER

TFT LCD PANEL

(2560x3x1440)

DATA DRIVER(RSDS

CN2.

INVERTER

VBL

CONNECTOR

GND

CN2:S12B-PH-SM3-TB

(D)(LF) or equivalent

(Slave)

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module

CNF1

Pin Name Description Note

1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 SELLVDS LVDS data format Selection (2) 8 N.C. No Connection (1)

9 ODSEL

10 N.C. No Connection (1) 11 GND Ground 12 ORX0_L- Odd pixel Negative LVDS differential data input. Channel 0 13 ORX0_L+ Odd pixel Positive LVDS differential data input. Channel 0 14 ORX1_L- Odd pixel Negative LVDS differential data input. Channel 1 15 ORX1_L+ Odd pixel Positive LVDS differential data input. Channel 1 16 ORX2_L- Odd pixel Negative LVDS differential data input. Channel 2 17 ORX2_L+ Odd pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 OCLK_L- Odd pixel Negative LVDS differential clock input. 20 OCLK_L+ Odd pixel Positive LVDS differential clock input. 21 GND Ground 22 ORX3_L- Odd pixel Negative LVDS differential data input. Channel 3 23 ORX3_L+ Odd pixel Positive LVDS differential data input. Channel 3 24 GND Ground 25 N.C. No Connection (1) 26 GND Ground 27 GND Ground 28 ERX0_L- Even pixel Negative LVDS differential data input. Channel 0 29 ERX0_L+ Even pixel Positive LVDS differential data input. Channel 0 30 ERX1_L- Even pixel Negative LVDS differential data input. Channel 1 31 ERX1_L+ Even pixel Positive LVDS differential data input. Channel 1 32 ERX2_L- Even pixel Negative LVDS differential data input. Channel 2 33 ERX2_L+ Even pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 ECLK_L- Even pixel Negative LVDS differential clock input. 36 ECLK_L+ Even pixel Positive LVDS differential clock input. 37 GND Ground 38 ERX3_L- Even pixel Negative LVDS differential data input. Channel 3 39 ERX3_L+ Even pixel Positive LVDS differential data input. Channel 3 40 GND Ground 41 N.C. No Connection (1) 42 GND Ground 43 GND Ground 44 GND Ground 45 GND Ground 46 GND Ground

Overdrive Lookup Table Selection

(1)

(3)

(4)

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47 N.C. No Connection (1) 48 VCC +12V power supply 49 VCC +12V power supply 50 VCC +12V power supply 51 VCC +12V power supply

CNF2

Pin Name Description Note

1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 N.C. No Connection 8 N.C. No Connection

9 N.C. No Connection 10 N.C. No Connection 11 GND Ground 12 ORX0_R- Odd pixel Negative LVDS differential data input. Channel 0 13 ORX0_R+ Odd pixel Positive LVDS differential data input. Channel 0 14 ORX1_R- Odd pixel Negative LVDS differential data input. Channel 1 15 ORX1_R+ Odd pixel Positive LVDS differential data input. Channel 1 16 ORX2_R- Odd pixel Negative LVDS differential data input. Channel 2 17 ORX2_R+ Odd pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 OCLK_R- Odd pixel Negative LVDS differential clock input. 20 OCLK_R+ Odd pixel Positive LVDS differential clock input. 21 GND Ground 22 ORX3_R- Odd pixel Negative LVDS differential data input. Channel 3 23 ORX3_R+ Odd pixel Positive LVDS differential data input. Channel 3 24 GND Ground 25 N.C. No Connection (1) 26 GND Ground 27 GND Ground 28 ERX0_R- Even pixel Negative LVDS differential data input. Channel 0 29 ERX0_R+ Even pixel Positive LVDS differential data input. Channel 0 30 ERX1_R- Even pixel Negative LVDS differential data input. Channel 1 31 ERX1_R+ Even pixel Positive LVDS differential data input. Channel 1 32 ERX2_R- Even pixel Negative LVDS differential data input. Channel 2 33 ERX2_R+ Even pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 ECLK_R- Even pixel Negative LVDS differential clock input. 36 ECLK_R+ Even pixel Positive LVDS differential clock input. 37 GND Ground 38 ERX3_R- Even pixel Negative LVDS differential data input. Channel 3 39 ERX3_R+ Even pixel Positive LVDS differential data input. Channel 3 40 GND Ground 41 N.C. No Connection (1) 42 GND Ground 43 GND Ground

(1)

(5)

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44 GND Ground 45 GND Ground 46 GND Ground 47 N.C. No Connection 48 N.C. No Connection 49 N.C. No Connection 50 N.C. No Connection 51 N.C. No Connection

Note (1) Reserved for internal use. Please leave it open.

Note (2) Low : VESA LVDS Format (default), High : JEIDA Format.

Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in

accordance with the frame rate to optimize image quality.

ODSEL Note

LLooku

HLooku

Note (4) Left side image signal input.

table was optimized for 60 Hz frame rate. table was optimized for 50 Hz frame rate.

(1)

Note (5) Right side image signal input.

Note (6) Connector part no. : IS050-C51B—C39-A (UJU) or equivalent.

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN3-CN26: BHR-04VS-1 (JST).

Pin Name Description Wire Color

1 HV High Voltage Pink 2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1 or

equivalent. The mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF)

or equivalent.

1 HV(White)

2 HV(Pink)

1 HV(Pink)

2 HV(White)

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

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1 HV(Pink)

2 HV(White)

1 HV(Pink)

2 HV(White)

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5.3 INVERTER UNIT

CN1 (Header): S14B-PH-SM3-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

11 SEL

12 E_PWM

13 I_PWM

14 BLON Backlight on/off control

VBL +24V

GND GND

Internal/external PWM selection High : external dimming Low : internal dimming

External PWM control signal E_PWM should be connected to ground when internal PWM was selected (SEL = Low). Internal PWM Control Signal I_PWM should be connected to ground when external PWM was selected (SEL = High).

power input

DC

CN2 (Header): S12B-PH-SM3-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10 11 NC NC 12 NC NC

CN3-CN26 (Header): SM02(12.0)B-BHS-1-TB (LF)(JST) or equivalent

Pin No. Symbol Description

1 CCFL HOT CCFL high voltage 2 CCFL HOT CCFL high voltage

VBL +24V

GND GND

power input

DC

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CN27-CN30 (Header): LM113P-020-TF1-3(Unicorn) or equivalent

Pin No. Symbol Description

1 Board to Board 2 Board to Board

3 Board to Board

4 Board to Board

5 Board to Board

6 Board to Board 7 Board to Board 8 Board to Board 9 Board to Board

10

Note (1) Floating of any control signal is not allowed.

Control

Signal

Board to Board

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5.4 BLOCK DIAGRAM OF INTERFACE

CNF1

ERx0+

ER0-ER7

-

ERx1+

ERx1-

ERx2+

OR0-OR7

-

ERx3+

ERx3-

ECLK+

Host

Graphics

Controller

ORx0+

ORx1+

ORx1-

51

Ө

51

51Ө

51

Ө

51

Ө

51

Ө

51

Ө

51

Ө

100pF

Ө

100

100pF

F

-

RxOUT

ER0-ER7

-

-OR7

-

51

Ө

51

100pF

Ө

-

Timing

51

Ө

51

Ө

51Ө

100pF

100

F

-

Controller

ORx2+

ORx3+

ORx3-

51

Ө

51 51

51

100pF

Ө Ө

100pF

Ө

-

OCLK+

51

Ө

51

100pF

Ө

-

LVDS Transmitter

THC63LVDM83A

(LVDF83A)

LVDS Receiver

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ER0~ER7 : Even pixel R data

EG0~EG7 : Even pixel G data

EB0~EB7 : Even pixel B data

OR0~OR7 : Odd pixel R data

OG0~OG7: Odd pixel G data

OB0~OB7 : Odd pixel B data

DE : Data enable signal

DCLK : Data clock signal

Notes: (1) The system must have the transmitter to drive the module.

(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line

when it is used differentially.

(3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is even pixel

and the second pixel is odd pixel.

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5.5 LVDS INTERFACE

24

bit

SIGNAL

LVDS_SEL

=L or OPEN

R0

R1

R2

R3

R4

R5

G0

G1

G2

G3

G4

G5

B0

B1

B2

B3

B4

B5

DE

R6

R7

G6

G7

B6

B7

RSVD 1

RSVD 2

RSVD 3

DCLK 31 TxCLK IN TxCLK OUT+

LVDS_SEL

= H

R2

R3

R4

R5

R6

R7

G2

G3

G4

G5

G6

G7

B2

B3

B4

B5

B6

B7

DE

R0

R1

G0

G1

B0

B1

RSVD 1

RSVD 2

RSVD 3

TRANSMITTER

THC63LVDM83

A

PIN INPUT Host TFT-LCD PIN OUTPUT

3

4

6

7

2

8

TxIN0

TxIN1

TxIN2

TxIN3

TxIN4

TxIN6

TxIN7

TxIN8

TxIN9

TxIN12

TxIN13

TxIN14

TxIN15

TxIN18

TxIN19

TxIN20

TxIN21

TxIN22

TxIN26

TxIN27

TxIN5

TxIN10

TxIN11

TxIN16

TxIN17

TxIN23

TxIN24

TxIN25

51

52

54

55

56

11

12

14

15

19

20

22

23

24

30

50

10

16

18

25

27

28

INTERFACE CONNECTOR

TA OUT0+

TA OUT0-

TA OUT1+

TA OUT1-

TA OUT2+

TA OUT2-

TA OUT3+

TA OUT3-

TxCLK OUT-

Rx 0+

Rx 0-

Rx 1+

Rx 1-

Rx 2+

Rx 2-

Rx 3+

Rx 3-

RxCLK IN+

RxCLK IN-

RECEIVER

THC63LVDF84A

Rx OUT0

27

Rx OUT1

29

Rx OUT2

30

Rx OUT3

32

Rx OUT4

33

Rx OUT6

35

Rx OUT7

37

Rx OUT8

38

Rx OUT9

39

Rx OUT12

43

Rx OUT13

45

Rx OUT14

46

Rx OUT15

47

Rx OUT18

51

Rx OUT19

53

Rx OUT20

54

Rx OUT21

55

Rx OUT22

1

Rx OUT26

6

Rx OUT27

7

Rx OUT5

34

Rx OUT10

41

Rx OUT11

42

Rx OUT16

49

Rx OUT17

50

Rx OUT23

2

Rx OUT24

3

Rx OUT25

5

26 RxCLK

OUT

TFT CONTROL INPUT

LVDS_SEL

=L or OPEN

R0

R1

R2

R3

R4

R5

G0

G1

G2

G3

G4

G5

B0

B1

B2

B3

B4

B5

DE

R6

R7

G6

G7

B6

B7

NC

LVDS_SEL

= H

R2

R3

R4

R5

R6

R7

G2

G3

G4

G5

G6

G7

B2

B3

B4

B5

B6

B7

DE

R0

R1

G0

G1

B0

B1

NC

DCLK

R0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)

B0~B7: Pixel B Data (7; MSB, 0; LSB)

DE : Data enable signal

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DCLK : Data clock signal

Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.

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5.7 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the

color. The higher the binary input, the brighter the color. The table below provides the assignment of the

color versus data input.

Data Signal

Color

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black Red

Green Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue

Cyan

Magenta

Yellow

White

Red (0) / Dark

Red (1)

Red (2)

:

: Red (253) Red (254) Red (255) Green (0) / Dark Green (1) Green (2)

:

: Green (253) Green (254) Green (255) Blue (0) / Dark Blue (1) Blue (2)

:

: Blue (253) Blue (254) Blue (255)

0

1

0

1

0

:

1

0

:

0

:

0

Red Green Blue

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

:

1

0

1

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

0 0

0

:

: :

:

0

:

1

0

:

0

:

0

1

:

1

0

1

0 0 0 1 1 1 0 1 0 0 0

:

: 0 0 0 0 0 0

:

: 0 0 0 0 1 0

:

: 1 0 1

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

Frequency 1/Tc (60) 78 (80) MH

LVDS Receiver Clock

LVDS Receiver Data

Vertical Active Display Term

Horizontal Active Display Term

Data Enable Term Delay Time Tde 0 (3) DCLK (3)

Note (1) (ODSEL) = (H) , (L). Please refer to 5.1 for detail information.

Input cycle to cycle jitter Setup Time Tlvsu 600 - - ps Hold Time Tlvhd 600 - - ps -

Frame Rate

Total Tv (1475) 1490 (1520) Th Tv=Tvd+Tvb Display Tvd 1440 1440 1440 Th Blank Tvb (35) 50 (80) Th Total Th (750) 872 (890) Tc Th=Thd+Thb Display Thd 640 640 640 Tc Blank Thb (110) 232 (250) Tc -

Trcl - - 200 ps -

Fr Fr

5

6

47 50 53 Hz (1) 57 60 63 Hz (1)

Z

-

Note (2) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low

logic level. Otherwise, this module would operate abnormally.

Note (3) Left side Data Enable signal (DE_L) and Right side Data Enable signal (DE_R) must be

synchronized. Otherwise, this module would operate abnormally.

INPUT SIGNAL TIMING DIAGRAM

T

v

T

vd

T

vb

DE_L

DE_R

T

de

T

h

DCLK

T

c

T

hb

T

hd

DE_L

(DE_R)

DATA

Valid display data (640 DCLK)

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RXCLK+

RXn+/-

Tlvsu

Tlvhd

1T‘ 14

LVDS INPUT INTERFACE TIMING DIAGRAM

Tc

3T‘ 14

5T‘ 14

7T‘ 14

9T‘ 14

11T‘

14

13T‘

14

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the

diagram below.

CC

Power Supply

0.9 V

CC

0.9 V

V

0.5

0

5s

CC

0V

ЉЉЉЉ

T

1

ЉЉЉЉ

10ms

ЉЉЉЉ

T

2

ЉЉЉЉ

50ms

ЉЉЉЉ

T

3

ЉЉЉЉ

50ms

ЉЉЉЉ

T4

Signals

0V

Backlight (Recommended)

ЉЉЉЉ

500ms

100ms

T5

ЉЉЉЉ

T

6

0.1V

CC

T

2

VALI D

Power On

50%

5

T

Power ON/OFF Sequence

50%

T

6

T

3

T1

Power Off

0.1V

T4

cc

Note.

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the

LCD operation or the LCD turns off before the backlight turns off, the display may momentarily

become abnormal screen.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on

period.

(5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage VCC 12/V V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Lamp Current IL Oscillating Frequency (Inverter) FW Vertical Frame Rate Fr 60 Hz

25±2

50±10

5.8±0.5 47±3

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR (1200) (1500) - -

Response Time

Center Luminance of White

White Variation

Cross Talk CT - - 4 %

Red

Green

Color Chromaticity

Viewing Angle

Blue

White

Color

Gamut

Horizontal

Vertical

Gray to

gray

L

C

δW

=0°, θY =0°

θ

x

Viewing Angle

Rx (0.659) Ry Gx Gy Bx

By Wx Wy

θx+

θ

-

x

θY+

θ

-

Y

at Normal

Direction

CR≥20

- (6.5) ms

(400) (450) - cd/m

- - (1.3) -

(0.328) (0.197)

Typ.– 0.03

(92) - % NTSC

80 88 80 88 80 88 80 88 -

(0.674) (0.151) (0.062)

0.280

0.285

Typ.+ 0.03

o

C

%RH

mA

KHz

-

Deg.

2

Note

(2)

Note

(3)

Note

(4)

Note

(7)

Note

(5)

Note

(6)

Note

(1)

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Note (1) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Eldim EZ-Contrast 160R

Note (2) Definition of Contrast Ratio (CR):

θX- = 90º

6 o’clock

θ

y-

= 90º

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L255 / L0

L255: Luminance of gray level 255

x-

y-

Normal

θx = θy = 0º

θy- θy+

θx−

θx+

y+

12 o’clock direction

θ

y+

= 90º

x+

θX+ = 90º

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Note (3) Definition of Gray to Gray Switching Time :

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.

Optical

Response

Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each

other .

100%

90%

10%

0%

Gray to gray switching time

Time

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Note (4) Definition of Luminance of White (LC):

Measure the luminance of gray level 255 at center point.

LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

CT = | Y

– YA | / YA × 100 (%)

B

Where:

Y

= Luminance of measured location without gray level 0 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 0 pattern (cd/m2)

B

(0, 0)

Active Area

Y

(D/8,W/2)

A, L

Gray 128

Y

(D/2,7W /8)

A, D

Note (6) Measurement Setup:

Y

A, U

Y

A, R

D, W

(D/2,W /8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W /8)

B, D

0, 0

Active Area

Gray 0

Gray 128

Y

(D/2,W /8)

B, U

Y

(7D/8,W/2)

B, R

(3D/4,3W/4)

D, W

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting backlight for 1 hour in a windless room.

LCD Module

LCD Panel

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (7) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points

δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line

Vertical Line

W

W/4

W/2

3W /4

D/4 D/2 3D/4

12

34

D

5

Active Area

: Test Point

X

X=1 to 5

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8. PRECAUTIONS

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) When storing modules as spares for a long time, the following precaution is necessary.

(a) Do not leave the module in high temperature, and high humidity for a long time.

It is highly recommended to store the module with temperature from 0 to 35

к

at normal

humidity without condensation.

(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight

or fluorescent light.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

8.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while

assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

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9. DEFINITION OF LABELS

9.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

V470K1 -L01 Rev. XX

MADE IN TAIWAN

CHI MEI

OPTOELECTRONICS

X X X X X X X Y M D L N N N N

(a) Model Name: V470K1-L01

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

E207943

MADE IN TAIWAN

RoHS

(c) Serial ID: X X

Serial ID includes the information as below:

Day: 1~9, A~Y, for 1

X X X X X Y M D L N N N N

(a) Manufactured Date: Year: 0~9, for 2000~2009

Month: 1~9, A~C, for Jan. ~ Dec.

(b) Revision Code: Cover all the change

(c) Serial No.: Manufacturing sequence of product

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

st

to 31st, exclude I ,O, and U.

(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

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10. PACKAGING

10.1 PACKING SPECIFICATIONS

(1) 2 LCD TV modules / 1 Box

(2) Box dimensions : 1198(L) X 331 (W) X 720 (H)

(3) Weight : approximately 43Kg ( 2 modules per box)

10.2 PACKING METHOD

Figures 10-1 and 10-2 are the packing method

LCD TV Module

Anti-static Bag

Cushion(Bottom)

4pcs Drier

Carton Label

Carton

Figure.10-1 packing

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Corner Protector:L1130*50*50mm

L1400*50*50mm Pallet:L1000*W1200*H140mm Pallet Stack:L1000*W1200*H1580mm Gross:276kg

Figure.10-2 packing

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11. MECHANICAL CHARACTERISTIC

࡛ભሽ՗ٝڶૻֆ׹

CHI MEI

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࡛ભሽ՗ٝڶૻֆ׹

CHI MEI

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CMO V470K1-L01 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual