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TFT LCD Approval Specification
MODEL NO.: V470H2 – P03
Customer: _________________________________
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
Approved by:_______________________________
Note:
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
QA Dept. Product Development Div.
Reviewed By
Hsin-nan Chen WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
CY Chang TC Chao
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
CONTENTS
REVISION HISTORY ......................................................................................................................................................... 4
1. GENERAL DESCRIPTION ............................................................................................................................................ 5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES........................................................................................................................................................... 5
1.3 MECHANICAL SPECIFICATIONS ....................................................................................................................... 5
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 6
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASE ON CMO MODULE V470H2-P03) ..................................... 6
2.2 PACKAGE STORAGE .......................................................................................................................................... 7
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 7
2.3.1 ELECTRICAL ABSOLUTE RATINGS ........................................................................................................ 7
3. ELECTRICAL CHARACTERISTICS ............................................................................................................................. 8
3.1 TFT LCD MODULE .............................................................................................................................................. 8
4. BLOCK DIAGRAM OF INTERFACE ........................................................................................................................... 11
4.1 TFT LCD MODULE ............................................................................................................................................ 11
5. INPUT TERMINAL PIN ASSIGNMENT ....................................................................................................................... 12
5.1 TFT LCD MODULE INPUT ................................................................................................................................ 12
5.2 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 15
5.3 LVDS INTERFACE ............................................................................................................................................. 16
5.4 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 18
6. INTERFACE TIMING ................................................................................................................................................... 19
6.1 INPUT SIGNAL TIMING SPECIFICATIONS ...................................................................................................... 19
6.2 POWER ON/OFF SEQUENCE .......................................................................................................................... 22
7. OPTICAL CHARACTERISTICS .................................................................................................................................. 23
7.1 TEST CONDITIONS ........................................................................................................................................... 23
7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 23
8. PRECAUTIONS ........................................................................................................................................................... 26
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 26
8.2 SAFETY PRECAUTIONS .................................................................................................................................. 26
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Model No.: V470H2-P03
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9. DEFINITION OF LABELS ............................................................................................................................................ 27
9.1 OPEN CELL LABEL ........................................................................................................................................... 27
9.2 CARTON LABEL ................................................................................................................................................ 27
10. PACKING ................................................................................................................................................................... 28
10.1 PACKING SPECIFICATIONS ........................................................................................................................... 28
10.2 PACKING METHOD ......................................................................................................................................... 28
11. MECHANICAL CHARACTERISTICS ........................................................................................................................ 30
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REVISION HISTORY
Version Date Page(New) Section Description
Ver. 2.0 Dec.07.2009 All All The approval specification was first issued.
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Model No.: V470H2-P03
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V470H2-P03 is a 47” TFT Liquid Crystal Display module with driver ICs and 2ch-LVDS interface. This product
supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit/color). The backlight unit is not
built-in.
1.2 FEATURES
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [in] 47”
Pixels [lines] 1920 1080
Active Area [mm] 1039.68 (H) x584.82 (V) (47” diagonal)
Sub-Pixel Pitch [mm] ˃ˁˈˇ˃ˈ(V) ˃ˁ˄ˋ˃ˈ(H)
Pixel Arrangement RGB vertical stripe
Weight [g] 2560
Physical Size [mm] ˄˃ˈˌˁˊˋ(W) ˉ˃ˈˁˋˊ(H) ˄ˁˋ˃(D) Typ.
Display Mode Transmissive mode / Normallly black
Contrast Ratio 4000:1 Typ.
Glass thickness (Array / CF) [mm] 0.7 / 0.7
Viewing Angle (CR>20) +88/-88(H), +88/-88(V) Typ. (CRЊ20)
Color Chromaticity R = (0.641, 0.332)
Cell Transparency [%] 4.6%
Polarizer Surface Treatment Anti-Glare coating (Haze 11%), Hard coating (3H)
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(Typical value measure at CMO’s module)
(Typical value measure at CMO’s module)
G = (0.272, 0.598)
B = (0.151, 0.0667)
W= (0.290, 0.295)
* Please refer to “color chromaticity” on p.14
1.3 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Weight
I/F connector mounting position
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Connector mounting position
The mounting inclination of the connector makes the
screen center within 0.5mm as the horizontal.
˅ˈ˄˃
2560
˅ˉ˄˃
+/- 0.5mm
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g -
(2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASE ON CMO MODULE V470H2-P03)
Value
Item Symbol
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
Unit Note
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
Storage condition: With shipping package.
Storage temperature rang: 255к
Storage humidity range: 5010%RH
Shelf life: a month
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 ELECTRICAL ABSOLUTE RATINGS
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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Model No.: V470H2-P03
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Value
Unit Note
Min. Max.
(1)
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 200
Terminating Resistor R
CMOS
interface
Input High Threshold Voltage V
Input Low Threshold Voltage VIL 0
RUSH
ЁЁ
ЁЁ
ЁЁ
V
LVT H
V
LVT L
T
2.7
IH
ЁЁ
0.48
1.2 1.4 A
0.51
+100
ЁЁ
ЁЁ
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
4.4 A (2)
Ё
A
(3) Horizontal Stripe
Ё
A
mV
-100 mV
(4)
600 mV
Ё
ohm
3.3 V
0.7 V
Note (2) Measurement condition:
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
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a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
(FI-RE51S-HF (JAE) or equivalent )
INPUT CONNECTOR
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FRAME
SCAN DRIVER
BUFFER
TFT LCD PANEL
(1920x3x1080)
SELLVDS
ODSEL
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
Vcc
GND
TIMING
CONTROLLER
DC/DC CONVERTER
& REFERENCE
VOLTAGE
GENERATOR
DATA DRIVER
(Mini-LVDS)
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
SELLVDS LVDS data format Selection
7
8 N.C. No Connection (2)
9 ODSEL Overdrive Lookup Table Selection (4)(6)
10 N.C. No Connection (2)
11 GND Ground
ERX0- Even pixel Negative LVDS differential data input. Channel 0
12
ERX0+ Even pixel Positive LVDS differential data input. Channel 0
13
ERX1- Even pixel Negative LVDS differential data input. Channel 1
14
ERX1+ Even pixel Positive LVDS differential data input. Channel 1
15
ERX2- Even pixel Negative LVDS differential data input. Channel 2
16
ERX2+ Even pixel Positive LVDS differential data input. Channel 2
17
18 GND Ground
19 ECLK20 ECLK+
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3-
ERX3+ Even pixel Positive LVDS differential data input. Channel 3
23
Even pixel Negative LVDS differential data input. Channel 3
24 N.C. No Connection (2)
25 N.C. No Connection (2)
26 GND Ground
27 GND Ground
28 ORX0-
Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX131 ORX1+
32 ORX233 ORX2+
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input
36 OCLK+
Odd pixel Positive LVDS differential clock input
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
39
40 N.C. No Connection (2)
41 N.C. No Connection (2)
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
48 VCC Power input (+12V)
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(2)
(3)(5)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
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49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)
Note (1) LVDS connector pin orderdefined as follows
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Note (2) Reserved for internal use. Please leave it open.
Note (3)
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
Low = Open or connect to GND, High = Connect to +3.3V
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
frame rate to optimize image quality.
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
R2
R2
R3
R3
Setting
Setting
Selector (pin7)
R1
R1
TCON
TCON
System side
Note (6) ODSEL signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
LCM sideSystem side
LCM side
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Selector (pin9)
Selector (pin9)
System side
System side
Notes (7) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel
and the second pixel is even pixel.
R1
R1
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R2
R2
R3
R3
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TCON
TCON
Setting
Setting
LCM side
LCM side
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G0-EG
0
G0-EG
0
r
0
p
ORx0
p
OG0
OB0
C
OG0
OB0
5.2 BLOCK DIAGRAM OF INTERFACE
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CNF1
ER0-ER7
E
-EB7
EB
DE
OR0-OR7
-OG7
-OB7
D
Host
Graphics
Controller
7
LK
TxIN
PLL
ERx0+
-
ERx
ERx1+
ERx1-
ERx2+
ERx2-
ERx3+
ERx3-
ECLK+
-
ORx0+
-
ORx1+
ORx1-
100Ө
100pF
100Ө
100Ө
100
100Ө
100Ө
100pF
100Ө
100Ө
100pF
100Ө
100Ө
100pF
100Ө
100Ө
100pF
100Ө
100Ө
100
RxOUT
ER0-ER7
F
E
EB
7
-EB7
DE
OR0-OR7
-OG7
-OB7
PLL
DCLK
Timing
Controlle
F
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
PLL
ORx2+
ORx2-
ORx3+
ORx3-
OCLK+
100Ө
100pF
100Ө
100Ө
100pF
100Ө
100Ө
-
100pF
100Ө
LVDS Receiver
15
PLL
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ER0~ER7 : Even pixel R data
EG0~EG7 : Even pixel G data
EB0~EB7 : Even pixel B data
OR0~OR7 : Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7 : Odd pixel B data
DE : Data enable signal
DCLK : Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
5.3 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=L or OPEN)
Current F\FOH
Current F\FOH
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
R5G0 R4 R3 R2 R1
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
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R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
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JEDIA LVDS formatΚ(SELLVDS pin=H)
RXCLK
RXCLK
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Current F\FOH
Current F\FOH
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ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
G5 G4G6
G5 G4G6
G5 G4G6
G5 G4G6
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
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5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus
data input.
Color
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
MSB LSB
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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Red
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
Data Signal
Green
MSB LSB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
Blue
MSB LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
18
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency
Input cycle to
LVDS
Receiver
Clock
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
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F
clkin
(=1/Tc)
-200
T
rcl
clkin_mod
F
200 KHz
F
SSM
60 74.25 80 MHz
Ё
F
-2%
clkin
Ё
200 ps (3)
F
+2% MHz
clkin
Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
(4)
LVDS
Receiver
Data
Vertica l
Active
Display
Te rm
Horizontal
Active
Display
Te rm
Setup Time Tlvsu 600
Hold Time Tlvhd 600
47 50 53 Hz
F
r5
Frame Rate
Fr6 57 60 63 Hz
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
ЁЁ
ЁЁ
ps
(5)
ps
(6)
Tv=Tvd+Tvb
Ё
Ё
Th=Thd+Thb
Ё
Ё
Note (1) ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˼˸˿ʳ˶˿˶˾ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼Κʳ ʳ ʳ
˙
˶˿˾˼ʻ˴ʼʳЊʳ˙ˉʳѼʳ˧ʳѼʳ˧˻ʳ
˙ˈʳѼʳ˧ʳѼʳ˧˻ʳЊʳ˙˶˿˾˼ʻ˼ʼʳ
Note (2) ˧˻˼ʳmodule is operated in DE only mode and please follow the input signal timing diagram beloΚʳ
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
INPUT SIGNAL TIMING DIAGRAM
Tv
DE
DCLK
DE
DATA
Th
Tc
Tvd
Thb
Tvb
Thd
Valid display data ( 960 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T
– TI
1
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
3T
5T
7T
9T
11T
13T
14
Note (6) : (ODSEL) = H/L or open for 50/60Hz frame rate. Please refer to 5.1 for detail information
14
14
14
14
14
14
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Љ
Љ
Љ
Љ
Љ
Љ
Љ
Љ
6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the
diagram below.
0V
0.5ЉT1Љ10ms
2
0
0
500ms
50ms
T
3
50ms
T
4
T
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0.1V
CC
T
2
Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
cc
0.1V
T
3T1
T4
LVDS Signals
0ЉT7ЉT2
0
T
0V
8
T3
Option Signals
(SELLVDS, ODSEL)
Backlight (Recommended)
T
5
500ms
100msЉT6
Power On
T7
50%
T
5
Power ON/OFF Sequence
VALID
50%
Power Off
8
T
T
6
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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x
Y
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current I
Oscillating Frequency (Inverter) F
Vertical Frame Rate Fr 60 Hz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (7).
Item Symbol Condition Min. Typ. Max. Unit Note
Red
Green
Color
Chromaticity
Blue
White
Center Transmittance T%
Contrast Ratio CR
Response Time
White Variation
Horizontal
Viewing Angle
Vertica l
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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o
r2
25
50r10
L
W
Rcx
Rcy
9.3r0.5
40r3
(0.641)
(0.332) -
Gcx (0.272) -
=0q, TY =0q
T
Gcy
Bcx (0.151) Bcy
Standard light source “C”
x
CS-1000T
(0.598) -
-
-
0.067) Wcx (0.290) Wcy
Gray to
gray
GW
T
+
Tx-
T
+
TY-
=0q, TY =0q
T
x
With CMO Module
=0q, TY =0q
T
x
With CMO Module
@60Hz
T
=0q, TY =0q
x
With CMO Module
CRt20
With CMO Module
(3000) (4000)
(0.295) -
- (4.6) -
(6.5) -
-
- - (1.3)
(80) (88)
(80)
(80)
(80)
(88)
(88)
(88)
-
-
-
-
C
%RH
mA
KHz
-
(1),(6)
(2), (8)
(2), (4)
-
(5)
(2), (7)
Deg. (2), (3)
Note (0) Light source is the standard light source ”C” which is defined by CIE and driving voltage are based on
suitable gamma voltages. The calculating method is as following :
1. Measure Module’s and BLU’s spectrum. White is without signal input and R,G,B are with signal input.
BLU(for V470H2-L03) is supplied by CMO.
2. Calculate cell’s spectrum.
3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”.
Note (2) Light source is the BLU which is supplied by CMO and driving voltages are based on suitable gamma
voltages.
Note (3) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Conoscope Cono-80
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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Normal
Tx = Ty = 0º
Ty- Ty
TX- = 90º
6 o’clock
T
y- = 90º
Note (4) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (1), where CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (8).
Note (5) Definition of Gray to Gray Switching Time:
x-
Tx
y-
Tx
12 o’clock direction
y+
T
y+ = 90º
x+
TX+ = 90º
100%
90%
Optical
Response
10%
0%
Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be executed
Gray to Gray
Switching Time
Gray to Gray
Time
Switching Time
24
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after lighting backlight for 1 hour in a windless room.
LCD Module
LCD Panel
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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Center of the Screen
Note (7) Definition of White Variation (GW):
Measure the luminance of gray level 255 at 5 points
GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Display Color Analyzer
(Minolta CA210)
Light Shield Room
(Ambient Luminance < 2 lux)
Horizontal Line
D
D/4 D/2 3D/4
W/4
W/2
W
Vertical Line
3W/4
Note (8) Definition of Transmittance (T%):
Module is without signal input.
Luminance of LCD module
Transmittance =
Luminance of backlight
1 2
X
5
3 4
: Test Point
X=1 to 5
Active Area
Ϡ 100%
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 OPEN CELL LABEL
The barcode nameplate is pasted on each open cell as illustration for CMO internal control.
9.2 CARTON LABEL
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Issue Date:Dec.07.2009
Model No.: V470H2-P03
Approval
V470H2-P03
The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation.
(a) Model Name: V470H2-P03
(b) Carton ID: CMO internal control
(c) Quantities: 8 pcs
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10. Packing
10.1 packing specifications
(1) 8 LCD TV Panels / 1 Box
(2) Box dimensions :1238 (L) X 842 (W) X 240(H)
(3) Weight : approximately 38Kg (8 panels per box)
10.2 packing Method
Figures 10-1 and 10-2 are the packing method
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Model No.: V470H2-P03
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Panel
Panel
Carton
Top layer for empty tray
Figure.10-1 packing method
Tape
Carton Label
Figure.9-1 packing method
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Figure.10-2 packing method
Figure.9-2 packing method
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11. MECHANICAL CHARACTERISTICS
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Model No.: V470H2-P03
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࡛ભሽٝڶૻֆ
%*+/'+
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