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TFT LCD Approval Specification
MODEL NO.: V470H2 – LH2
Customer: _________________________________
Approved by:_______________________________
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Issue Date:Aug.31.2009
Model No.: V470H2-LH2
Approval
Note:
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-nan Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang TC Chao
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Issue Date:Aug.31.2009
Model No.: V470H2-LH2
Approval
CONTENTS
REVISION HISTORY ......................................................................................................................................................... 4
1. GENERAL DESCRIPTION ............................................................................................................................................ 5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES........................................................................................................................................................... 5
1.3 APPLICATION ...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................. 5
1.5 MECHANICAL SPECIFICATION ......................................................................................................................... 6
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ........................................................................................................ 7
2.2 PACKAGE STORAGE .......................................................................................................................................... 8
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 8
2.3.1 TFT LCD MODULE .................................................................................................................................... 8
2.3.2 BACKLIGHT INVERTER UNIT .................................................................................................................. 8
3. ELECTRICAL CHARACTERISTICS ............................................................................................................................. 9
3.1 TFT LCD MODULE .............................................................................................................................................. 9
3.2 BACKLIGHT UNIT .............................................................................................................................................. 12
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta=25± 2 ºC) ....................................... 12
3.2.2 INVERTER CHARACTERISTICS ............................................................................................................ 12
3.2.3 INVERTER INTERFACE CHARACTERISTICS ...................................................................................... 14
4. BLOCK DIAGRAM OF INTERFACE ........................................................................................................................... 16
4.1 TFT LCD MODULE ............................................................................................................................................ 16
INPUT CONNECTOR ...................................................................................................................................................... 16
DATA DRIVER (RSDS) ..................................................................................................................................... 16
BACKLIGHT UNIT ............................................................................................................................................ 16
5. INPUT TERMINAL PIN ASSIGNMENT ....................................................................................................................... 17
5.1 TFT LCD Module Input ....................................................................................................................................... 17
5.3 INVERTER UNIT ................................................................................................................................................ 20
5.4 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 21
5.5 LVDS INTERFACE ............................................................................................................................................. 23
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 24
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Model No.: V470H2-LH2
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6. INTERFACE TIMING ................................................................................................................................................... 25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS (Ta = 25 ± 2 ºC) ............................................................................ 25
The input signal timing specifications are shown as the following table and timing diagram. ................................. 25
6.2 POWER ON/OFF SEQUENCE .......................................................................................................................... 27
7. OPTICAL CHARACTERISTICS .................................................................................................................................. 28
7.1 TEST CONDITIONS ........................................................................................................................................... 28
7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 29
8. PRECAUTIONS ........................................................................................................................................................... 32
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 32
8.2 SAFETY PRECAUTIONS .................................................................................................................................. 32
9. DEFINITION OF LABELS ............................................................................................................................................ 33
9.1 CMO MODULE LABEL ...................................................................................................................................... 33
10. PACKAGING.............................................................................................................................................................. 35
11. MECHANICAL CHARACTERISTICS ........................................................................................................................ 37
Appendix – TWO Wire BUS INTRODUCTION ................................................................................................................ 40
A.1 PIN ASSIGNMENT ............................................................................................................................................ 40
A.2 I2C BUS APPLICATION NOTE ......................................................................................................................... 40
A.3 TWO WIRE BUS DEVICE ADDRESS ............................................................................................................... 40
A.5 TWO WIRE BUS COMMAND TABLE ................................................................................................................ 42
A.7 THE TWO WIRE BUS SEQUENCE .................................................................................................................. 47
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REVISION HISTORY
Version Date
Ver. 2.5
Aug. 31.
2009
Page
(New)
All
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Section Description
All
Approval Specification Ver 2.5 was first issued.
Issue Date:Aug.31.2009
Model No.: V470H2-LH2
Approval
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g (3H)
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V470H2-LH2 is a 47” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (10-bit/color). The
inverter module for backlight is built-in.
1.2 FEATURES
Ё High brightness (500 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 4.0 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1039.68 (H) x584.82 (V) (47” diagonal) mm
Bezel Opening Area 1049(H) x 539 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.5415 (V) x 0.1805 (H) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 1.07G color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
Anti-Glare coating (Haze 11%)/
Hard coatin
- (2)
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1.5 MECHANICAL SPECIFICATION
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) - 1096 - mm
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Issue Date:Aug.31.2009
Model No.: V470H2-LH2
Approval
Module Size
Depth (D) - 48.5 - mm
Weight - 12500 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
(1), (2)Vertical (V) - 640 - mm
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
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Model No.: V470H2-LH2
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Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
axis
Z axis 35 G (3), (5)
- 50 G (3), (5)
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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Model No.: V470H2-LH2
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Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Contro.l Internal PWM Control and External PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
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Ё
Ё
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 100
Terminating Resistor RT
Input High Threshold Voltage V
Input Low Threshold Voltage VIL 0
Vertical Stripe
Black Pattern
RUSH
Ё
Ё
Ё
V
LVT H
V
LVT L
2.7
IH
Ё Ё
-
+100
Ё Ё
Ё
1.6
2.3ʳ 2.8 A
1.6ʳ
Ё Ё
Ё
100
Ё
Ё
5.0 A (2)
Ё
Ё
-100 mV
600 mV
Ё
3.3 V
0.7 V
A
(3)
A
mV
(4)
ohm
Note (2) Measurement condition:
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Model No.: V470H2-LH2
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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Model No.: V470H2-LH2
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a. White Pattern
Active Area
c. Vertical Stripe Pattern
b. Black Pattern
Active Area
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta=25± 2 ºC)
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Lamp Input Voltage VL - 1175 - VRMS -
Lamp Current IL 8.8 9.3 9.8 mARMS (1)
- - 1820 VRMS Ta = 0 ºC
Lamp Turn On Voltage VS
- - 1620 VRMS Ta = 25 ºC
Operating Frequency FL 40 - 70 KHz
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Model No.: V470H2-LH2
Approval
Unit Note
Lamp Life Time LBL 50,000 - Hrs (2)
3.2.2 INVERTER CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Power Consumption PBL - 130 138 W (5), IL =9.3mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 5.4 - A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 37 40 43 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 20 - %
Note (1) Lamp current is measured by utilizing AC current probe.
Unit Note
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
should be applied to the lamp for more than 1 second after startup.
S
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the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
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2к and I
Note (5) The measurement condition of Max. value is based on 47" backlight unit under input voltage 24V,
average lamp current 9.6 mA and lighting 30 minutes later.
=9.0~ 9.6mArms.
L
LCD
Module
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
1
2
1
2
1
2
Inverter
1
2
1
2
HV (Pink)
HV (White)
1
2
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Te st
Condition
Ё
Ё
Ё
Min. Typ. Max.
2.0
0
2.85 3.0 3.15 V maximum duty ratio
Ё Ё
Ё
Ё
Ё
Ё
Ё
Ё
2.0
0
3.0 3.3 3.6 V
0
30
30
Ё Ё Ё
Value
Ё
Ё
0
Ё
Ё
Ё
Ё Ё
Ё Ё
Unit Note
5.0 V
0.8 V
Ё
V minimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
Ё
Ё
1
100
300
Ё Ё
Ё Ё
Ё Ё
100 ms
50 us
50 us
M
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
Ё Ё
Ё Ё
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш PWM signal Ш BLON
Ш PWM signal Ш VBL
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Model No.: V470H2-LH2
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V
VBLON
V
EPWM
V
IPWM
9%/
Toff
Tf1
9
%/
Tr1
BL
0
9
0
%/
2.0V
0.8V
9
Ton
%/
Ton1
Backlight on duration
Tr
Tf
Ext. Dimming Function
TPWMR
PWMF
2.0V
0
0.8V
T
PWM
T
Floating
3.0V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ODD_RIN0+/ODD_RIN1+/ODD_RIN2+/ODD_RIN3+/ODD_RIN4+/ODD_CLK+/-
EVEN_RIN0+/EVEN_RIN1+/EVEN_RIN2+/EVEN_RIN3+/EVEN_RIN4+/EVEN_CLK+/-
MEN
MCFG0
MCFG 1
LVDS8b
GV_mode
SELLVDS
ODSE
SCL
SDA
VIN
GND
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
FRAME
BUFFER
MEMC
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FRAME
SCAN DRIVER
BUFFER
TFT LCD PANEL
(1920x3x1080)
TIMING
CONTROLLER
DATA DRIVER (RSDS
DC/DC CONVERTER
& REFERENCE VOLTAGE
GENERATOR
VBL
GND
Status
A_DIM
I_PWM
BLON
INVERTER
CONNECTOR
CN1:S14B-PH-SM4-TB
(D)(LF) or equivalent
CN2-CN7:SM02 (13.0)-BDAS-3-TB(LF)(JST) or equivalent
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Part No.: JAE Taiwan (ሽ) FI-RE51S-HF or equal.
Pin Name Description Note
1 GND Ground ʳ
2 MEN MEMC function selection 5
3 MCFG0 MEMC function selection 5
4 MCFG1 MEMC function selection 5
5 LVDS8b 8bit/10bit LVDS input selection 6
6 GV_mode Graphic / Video mode selection 7
7 SELLVDS LVDS data format Selection 3
8 SCL I2C CLK Signal ʳ
9 SDA. I2C Data Signal ʳ
10 ODSEL Overdrive Lookup Table Selection 4
11 GND Ground ʳ
12 ERX0- 2nd pixel Negative LVDS differential data input. Channel 0 ʳ
13 ERX0+ 2nd pixel Positive LVDS differential data input. Channel 0 ʳ
14 ERX1- 2nd pixel Negative LVDS differential data input. Channel 1 ʳ
15 ERX1+ 2nd pixel Positive LVDS differential data input. Channel 1 ʳ
16 ERX2- 2nd pixel Negative LVDS differential data input. Channel 2 ʳ
17 ERX2+ 2nd pixel Positive LVDS differential data input. Channel 2 ʳ
18 GND Ground ʳ
19 ECLK- 2nd pixel Negative LVDS differential clock input. ʳ
20 ECLK+ 2nd pixel Positive LVDS differential clock input. ʳ
21 GND Ground ʳ
22 ERX3- 2nd pixel Negative LVDS differential data input. Channel 3 ʳ
23 ERX3+ 2nd pixel Positive LVDS differential data input. Channel 3 ʳ
24 ERX4- 2nd pixel Negative LVDS differential data input. Channel 4 ʳ
25 ERX4+ 2nd pixel Positive LVDS differential data input. Channel 4 ʳ
26 N.C. No Connection 2
27 N.C. No Connection 2
28 ORX0- 1st pixel Negative LVDS differential data input. Channel 0 ʳ
29 ORX0+ 1st pixel Positive LVDS differential data input. Channel 0 ʳ
30 ORX1- 1st pixel Negative LVDS differential data input. Channel 1 ʳ
31 ORX1+ 1st pixel Positive LVDS differential data input. Channel 1 ʳ
32 ORX2- 1st pixel Negative LVDS differential data input. Channel 2 ʳ
33 ORX2+ 1st pixel Positive LVDS differential data input. Channel 2 ʳ
34 GND Ground ʳ
35 OCLK- 1st pixel Negative LVDS differential clock input. ʳ
36 OCLK+ 1st pixel Positive LVDS differential clock input. ʳ
37 GND Ground ʳ
38 ORX3- 1st pixel Negative LVDS differential data input. Channel 3 ʳ
39 ORX3+ 1st pixel Positive LVDS differential data input. Channel 3 ʳ
40 ORX4- 1st pixel Negative LVDS differential data input. Channel 4 ʳ
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41 ORX4+ 1st pixel Positive LVDS differential data input. Channel 4 ʳ
42 N.C. No Connection 2
43 N.C. No Connection 2
44 GND Ground ʳ
45 GND Ground ʳ
46 GND Ground ʳ
47 N.C. No Connection 2
48 VCC +12V power supply ʳ
49 VCC +12V power supply ʳ
50 VCC +12V power supply ʳ
51 VCC +12V power supply ʳ
Note (1) LVDS connector pin order defined as follows
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Note (2) Reserved for internal use. Please leave it open
Note (3)
SELLVDS Mode
L(default)
H JEIDA
L: Connect to GND, H: Connect to +3.3V
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Description
L(default)
H Lookup table was optimized for 50 Hz frame rate input.
Lookup table was optimized for 60 Hz frame rate input.
VESA
L: Connect to GND, H: Connect to +3.3V
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Æ
Note (5) Motion Engine (ME) Level & Demo Function Table
Motion engine level must be adjusted after video mode is selected (or entered).
Adjusting the motion engine level in graphic mode has no effect
MEN MCFG1 MCFG0 Notes
0 0 0
0 0 1
0 1 0
Blanking
Blanking disable
Auto blanking
Blanking enable
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(a)
(b)
(c)
Effect of ME
Demo mode (d)
Strong
Medium(Default)
ME
Level
(a) Module re-starts processing video signals from Frontend scaler control board.
(b) During sync unstable period such as format change, 60Hz <-> 50Hz .
(c) Module continues to insert blanking until blanking disable signal is received from frontend scaler board.
(d) Demo window mode: Demo Window appears to the left half of display area. Left side with frame is 120Hz
(e) GPIO (General Purpose I/O) sequence of ME Level: (1) MEN; (2) MCFG1; (3) MCFG0.
(f) Each scaler command must be maintained the same voltage level at least 100ms.
(g) 0 : Connect to GND, 1 : +3.3V
Weak
OFF
(e) (f) (g)
MCFG0 can be used to insert blanking of 500ms. This signal is toggled.
with MEMC, and right side is 120Hz w/o motion compensation.
GPIO sequence of Blanking Enable, Blanking Disable and Demo window: (1) MCFG1; (2) MCFG0; (3)
MEN.
0 1 1 Demo Window
1 0 0 Enable Strong Strong
1 0 1 Enable Normal Normal
1 1 0 Enable × ×
1 1 1 × × ×
De blur De judder Halo
Note (6) 8bit/10bit LVDS input selection
LVDS8b Bit depth
H(default)
L
L : Connect to GND, H : Connect to +3.3V
Note (7) Graphic / Video mode selection
There is no prohibited time period for switching between Graphic mode and Video mode.
When this switching signal is input, LCD will be reset and will re-start selected mode.
GV_mode Mode select MEMC ON/OFF
H(default)
L
L : Connect to GND, H : Connect to +3.3V
8bit
10bit
Graphic mode MEMC OFF
Video mode MEMC ON
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5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
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3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
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REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Color
Black
Red
Green
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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Data Signal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
;
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS (Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
LVDS
Receiver
Clock
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
clkin
(=1/TC)
T
rcl
clkin_mod
F
30
F
SSM
60 74.25 78 MHz
Ё Ё
F
-2%
clkin
Ё
Ё
200 ps (2)
F
+2% MHz
clkin
50 KHz
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Model No.: V470H2-LH2
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(3)
LVDS
Setup Time Tlvsu 600
Ё Ё
Receiver
Data
Hold Time Tlvhd 600
47 50 53 Hz
F
r5
Ё Ё
Frame Rate
Vertica l
Active
Display
Te rm
Total Tv 1110 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Fr6 57 60 62 Hz
Blank Tvb 30 45 55 Th
Horizontal
Active
Display
Te rm
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Note (1) ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˹˴˸ʳ˴˸ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼Κʳ ʳ ʳ
˙ʻ˴ʼʳ Њʳ ˙˶˿˾˼ʳ Яʳ ˧˧˻ʳ Љʳ ˙ʻ˼ʼʳ
ps
ps
Tv=Tvd+Tvb
Th=Thd+Thb
Note (2) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
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Note (3) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Љ
Љ
Љ
Љ
Љ
P
Љ
Љ
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram
below.
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50ms
50ms
4
T
0V
0.5ЉT1Љ10ms
0
0
500ms
2
T
3
T
0.1V
CC
3 T1
T
2
T
0.1V
cc
T4
LVDS Signals
0V
Power On
VALID
0ЉT7ЉT2
0
8
T
T7
8
T
Option Signals
(SELLVDS,GPIO setting..…)
Backlight (Recommended)
1000ms
100msЉT6
T
5
50%
T
5
50%
T
6
Note:
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
Power ON/OFF Sequence
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD Module
LCD Panel
25r2
50r10
9.3r0.5
40r3
oC
%RH
mA
KHz
Center of the Screen
Display Color Analyzer
(Minolta CA210)
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
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Contrast Ratio CR
Response Time
Center Luminance of White LC 400 500 - cd/m2Note (4)
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Gray to
gray
GW
Rx
Ry
Gx 0.272 -
Gy 0.599 -
Bx 0.152 -
By 0.067 -
Wx 0.285 -
Wy 0.293 -
Tx=0q, Ty =0q
Viewing angle
at normal direction
3000 4000 - - Note (2)
- 4.5 9 ms Note (3)
- - 1.3 - Note (7)
Typ.
-0.03
0.643
0.332
Typ.
+0.03
-
-
-
Color Gamut C.G - 72 - % NTSC
Tx+
Horizontal
Tx-
Viewing Angle
TY+
Vertica l
TY-
Note (1) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Eldim EZ-Contrast 160R
CRt20
80 88 -
80 88 -
Deg. Note (1)
80 88 -
80 88 -
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
The driving signal means the signal of gray level 0, 252, 508, 764, and 1023.Gray to gray average
time means the average switching time of gray level 0, 252,508,764,1023 to each other.
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 1023 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
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Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA u 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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Note (6) Definition of White Variation (GW):
Measure the luminance of gray level 1023 at 5 points
GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Issue Date:Aug.31.2009
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CHI MEI
OPTOELECTRONICS
V470H2 -LH2 Rev. XX
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X X X X X X X Y M D L N N N N
Issue Date:Aug.31.2009
Model No.: V470H2-LH2
E207943
MADE IN TAIWAN
RoHS
GEMN
Approval
Model Name: V470H2-LH2
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
V470H2 -LH2 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
E207943
MADE IN TAIWAN
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
CMO Internal Use
Revision
CMO Internal Use
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Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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10. PACKAGING
10.1 PACKING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1190(L)x280(W)x725(H)mm
(3) Weight : approximately 42 Kg ( 3 modules per box)
10.2 PACKING METHOD
Figures 10-1 and 10-2 are the packing method
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LCD TV Module
Anti-static Bag
Carton
PP Belt
Cushion(Bottom)
Figure.10-1 packing method
Carton Label
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(
)
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Air Transportation &
Sea / Land Transportation (40ft Container)
(L1130*50*50mm)
Film
(L1150*W1190*H140mm)
(L1400*50*50mm)
Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
(L625*50*50mm)
Film
(L1400*50*50mm)
L1150*W1190*H140mm
Gross: 534kg
Figure.10-2 packing method
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11. MECHANICAL CHARACTERISTICS
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࡛ભሽٝڶૻֆ
%*+/'+
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Appendix – TWO Wire BUS INTRODUCTION
A.1 PIN ASSIGNMENT
51pins LVDS connector
Pin8: SCL
Pin9: SDA
A.2 I2C BUS APPLICATION NOTE
I2C bus: (The I2C bus must for MEMC only or prevent the I2C bus voltage drop down in initial state)
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A.3 TWO WIRE BUS DEVICE ADDRESS
Two wire device address: default is 0x40, 1 byte
Two wire command: the range is 0x00 to 0xFF, 1 byte, see the two wire command table.
Two wire bus format:
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A.4 TWO WAY TO CONTROL THE TWO WIRE BUS
There are two options to control the two wires bus command.
Two wire bus 6 bytes format
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Two wire bus 3 bytes format
Note:
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP
condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the
wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave
can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too
fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending
the SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the
slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
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A.5 TWO WIRE BUS COMMAND TABLE
There is two wire bus command table.
Command Name
All OSD Protection 0x00 R/W OSDx Enable Flag Contorl
OSD1_Start_Protection 0x01 R/W OSD1 Protection Start Position
OSD2_Start_Protection 0x02 R/W OSD2 Protection Start Position
OSD3_Start_Protection 0x03 R/W OSD3 Protection Start Position
OSD4_Start_Protection 0x04 R/W OSD4 Protection Start Position
OSD1_End_Protection 0x05 R/W OSD1 Protection End Position
OSD2_End_Protection 0x06 R/W OSD2 Protection End Position
OSD3_End_Protection 0x07 R/W OSD3 Protection End Position
OSD4_End_Protection 0x08 R/W OSD4 Protection End Position
Demo Window 0x09 R/W ME Performance Demo
MEMC Level 0x0A R/W ME Performance
GV Mode 0x0B R/W ME Operation
Blanking 0x0C R/W Blinking the screen
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Access
Mode
Description
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Enable All OSD Protection
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OSD # 1~4 Start Protection
OSD # 1~4 End Protection
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Demo Window
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MEMC Level
GV Mode
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Blanking (Enable/Disable)
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A.6 TWO WIRE BUS REQUIREMENT
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A.7 THE TWO WIRE BUS SEQUENCE
Two Wire command can be initialized during 20ms to 60ms.
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Example:
The previous state is strong mode, and the power is reset. The two wire command (strong mode command)
must be initialized during 20ms to 60ms.
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