One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 2
Global LCD Panel Exchange Center
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
CONTENTS
REVISION HISTORY ......................................................................................................................................................... 4
1. GENERAL DESCRIPTION ............................................................................................................................................ 5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................. 5
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ........................................................................................................ 7
3.2 BACKLIGHT UNIT .............................................................................................................................................. 11
5.2 BACKLIGHT UNIT .............................................................................................................................................. 19
5.3 INVERTER UNIT ................................................................................................................................................ 20
5.4 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 21
7.1 TEST CONDITIONS ........................................................................................................................................... 29
Note (1) Lamp current is measured by utilizing AC current probe.
Unit Note
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
should be applied to the lamp for more than 1 second after startup.
S
11
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 12
Global LCD Panel Exchange Center
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
2к and I
Note (5) The measurement condition of Max. value is based on 47" backlight unit under input voltage
24V, average lamp current 9.6 mA and lighting 30 minutes later.
LCD
Module
=9.0~9.6 mArms.
L
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
1
2
1
2
1
2
Inverter
1
2
1
2
1
2
12
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 13
Global LCD Panel Exchange Center
3.2.3 INVERTER INTERFACE CHARACTERISTICS
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Te st
Condition
Ё
Ё
Ё
Min.Typ.Max.
2.0
0
2.85 3.0 3.15V maximum duty ratio
Ё Ё
Ё
Ё
Ё
Ё
Ё
Ё
2.0
0
3.0 3.3 3.6 V
0
30
30
ЁЁЁ
Value
Ё
Ё
0
Ё
Ё
Ё
Ё Ё
Ё Ё
Unit Note
5.0 V
0.8 V
Ё
V minimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
Ё
Ё
1
100
300
Ё Ё
Ё Ё
Ё Ё
100 ms
50 us
50 us
M
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
Ё Ё
Ё Ё
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш PWM signal Ш BLON
Ш PWM signal Ш VBL
Note (4) When the Dynamic CR has been turned on, the skipped range of VIPWM 2.85~3.15V, is suggested to
avoid the abnormal phenomenon.
13
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 14
Global LCD Panel Exchange Center
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
V
VBLON
V
EPWM
V
IPWM
9%/
Toff
Tf1
9
%/
Tr1
BL
0
9
0
%/
2.0V
0.8V
9
Ton
%/
Ton1
Backlight on duration
Tr
Tf
Ext. Dimming Function
TPWMR
PWMF
2.0V
0
0.8V
T
PWM
T
Floating
3.0V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
14
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 15
Global LCD Panel Exchange Center
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
15
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
!
www.panelook.com
Page 16
Global LCD Panel Exchange Center
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 N.C. No Connection
8 N.C. No Connection
9 GND Ground
10 CH3_0N Third Pixel Negative LVDS differential data input. Channel 0
11 CH3_0P Third Pixel Positive LVDS differential data input. Channel 0
12 CH3_1N Third Pixel Negative LVDS differential data input. Channel 1
13 CH3_1P Third Pixel Positive LVDS differential data input. Channel 1
14 CH3_2N Third Pixel Negative LVDS differential data input. Channel 2
15 CH3_2P Third Pixel Positive LVDS differential data input. Channel 2
16 GND Ground
17 CH3_CLKN
18 CH3_CLKP
19 GND Ground
20 CH3_3N Third Pixel Negative LVDS differential data input. Channel 3
21 CH3_3P Third Pixel Positive LVDS differential data input. Channel 3
22 CH3_4N Third Pixel Negative LVDS differential data input. Channel 4
23 CH3_4P Third Pixel Positive LVDS differential data input. Channel 4
24 N.C. No Connection
25 N.C. No Connection
26 CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0
27 CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0
28 CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1
29 CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1
30 CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2
31 CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2
32 GND Ground
33 CH4_CLKN
34 CH4_CLKP
35 GND Ground
36 CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3
37 CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3
38 CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4
39 CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4
40 N.C. No Connection
41 N.C. No Connection
Third Pixel Negative LVDS differential clock input.
Third Pixel Positive LVDS differential clock input.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 17
Global LCD Panel Exchange Center
CNF2 Connector Pin Assignment (FI-RE51S-HF (JAE) or equivalent )
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 ODSEL Overdrive Lookup Table Selection (3)
6 N.C. No Connection (1)
7 SELLVDS LVDS data format Selection (2)
8 N.C. No Connection
9 N.C. No Connection
10 DCREN Dynamic Contrast Ratio Enable (5)
11 GND Ground
12 CH1_0N First Pixel Negative LVDS differential data input. Channel 0
13 CH1_0P First Pixel Positive LVDS differential data input. Channel 0
14 CH1_1N First Pixel Negative LVDS differential data input. Channel 1
15 CH1_1P First Pixel Positive LVDS differential data input. Channel 1
16 CH1_2N First Pixel Negative LVDS differential data input. Channel 2
17 CH1_2P First Pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 CH1_CLKN
20 CH1_CLKP
21 GND Ground
22 CH1_3N First Pixel Negative LVDS differential data input. Channel 3
23 CH1_3P First Pixel Positive LVDS differential data input. Channel 3
24 CH1_4N First Pixel Negative LVDS differential data input. Channel 4
25 CH1_4P First Pixel Positive LVDS differential data input. Channel 4
26 N.C. No Connection
27 N.C. No Connection
28 CH2_0N Second Pixel Negative LVDS differential data input. Channel 0
29 CH2_0P Second Pixel Positive LVDS differential data input. Channel 0
30 CH2_1N Second Pixel Negative LVDS differential data input. Channel 1
31 CH2_1P Second Pixel Positive LVDS differential data input. Channel 1
32 CH2_2N Second Pixel Negative LVDS differential data input. Channel 2
33 CH2_2P Second Pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 CH2_CLKN
36 CH2_CLKP Second Pixel Positive LVDS differential clock input.
37 GND Ground
38 CH2_3N Second Pixel Negative LVDS differential data input. Channel 3
39 CH2_3P Second Pixel Positive LVDS differential data input. Channel 3
40 CH2_4N Second Pixel Negative LVDS differential data input. Channel 4
41 CH2_4P Second Pixel Positive LVDS differential data input. Channel 4
42 N.C. No Connection
43 N.C. No Connection
44 GND Ground
First Pixel Negative LVDS differential clock input.
First Pixel Positive LVDS differential clock input.
Second Pixel Negative LVDS differential clock input.
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
(1)
(1)
(4)
(4)
(1)
(4)
(4)
(1)
17
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 18
Global LCD Panel Exchange Center
45 GND Ground
46 GND Ground
47 N.C. No Connection (1)
48 Vin Power input (+12V)
49 Vin Power input (+12V)
50 Vin Power input (+12V)
51 Vin Power input (+12V)
Note (1) Please be reserved to open.
Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to +3.3V.
Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Note
L Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
Note (4) LVDS 4-Port Data Mapping
Port CH of LVDS Data Stream
1st Port First pixel 1, 5, 9, ..........., 1913, 1917
2nd Port Second pixel 2, 6, 10, ........., 1914, 1918
3rd Port Third pixel 3, 7, 11, ........., 1915, 1919
4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920
Note (5) Low : function disable (default), High : Dynamic Contrast Ratio function enable
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
18
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 19
Global LCD Panel Exchange Center
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN3~CN26: BHR-04VS-1 (JST).
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST. The
mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
19
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 20
Global LCD Panel Exchange Center
5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
20
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 21
Global LCD Panel Exchange Center
5.4 BLOCK DIAGRAM OF INTERFACE
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
21
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 22
Global LCD Panel Exchange Center
AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
22
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 23
Global LCD Panel Exchange Center
5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0AR5
AB1
DEVSHSAB5AB4AB3AB2
REVAB7AB6AG7AG6AR7AR6
REVAB9AB8AG9AG8AR9AR8AR8REV
AG4AR7
AB5
AB0AG5AG4AG3AG2AG1
AB4AG7AG6AG5AG9AG8
AR4AR3AR2AR1AR0
AR6AR5AR4AR9AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DEVSHSAB7AB6AB9AB8
REVAB3AB2AG3AG2AR3AR2
REVAB1AB0AG1AG0AR1AR0AR0REV
DE
REV
23
Version 2.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Page 24
Global LCD Panel Exchange Center
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color