CMO V470H2-LH1 Specification

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TFT LCD Approval Specification
MODEL NO.: V470H2 – LH1
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-Nan Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang TC Chao
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
CONTENTS
REVISION HISTORY ......................................................................................................................................................... 4
1. GENERAL DESCRIPTION ............................................................................................................................................ 5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES........................................................................................................................................................... 5
1.3 APPLICATION ...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................. 5
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ........................................................................................................ 7
2.2 PACKAGE STORAGE .......................................................................................................................................... 8
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 8
2.3.1 TFT LCD MODULE .................................................................................................................................... 8
2.3.2 BACKLIGHT INVERTER UNIT .................................................................................................................. 8
3. ELECTRICAL CHARACTERISTICS ............................................................................................................................. 9
3.1 TFT LCD MODULE .............................................................................................................................................. 9
3.2 BACKLIGHT UNIT .............................................................................................................................................. 11
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS ............................................................. 11
3.2.2 INVERTER CHARACTERISTICS (Ta= 25 ± 2 ºC) .................................................................................. 11
3.2.3 INVERTER INTERFACE CHARACTERISTICS ...................................................................................... 13
4. BLOCK DIAGRAM OF INTERFACE ........................................................................................................................... 15
4.1 TFT LCD MODULE ............................................................................................................................................ 15
5. INPUT TERMINAL PIN ASSIGNMENT ....................................................................................................................... 16
5.1 TFT LCD Module Input ....................................................................................................................................... 16
5.2 BACKLIGHT UNIT .............................................................................................................................................. 19
5.3 INVERTER UNIT ................................................................................................................................................ 20
5.4 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 21
5.5 LVDS INTERFACE ............................................................................................................................................. 23
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 24
6. INTERFACE TIMING ................................................................................................................................................... 25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS ...................................................................................................... 25
6.2 POWER ON/OFF SEQUENCE .......................................................................................................................... 28
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
7. OPTICAL CHARACTERISTICS .................................................................................................................................. 29
7.1 TEST CONDITIONS ........................................................................................................................................... 29
7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 30
8. PRECAUTIONS ........................................................................................................................................................... 33
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 33
8.2 SAFETY PRECAUTIONS .................................................................................................................................. 33
9. DEFINITION OF LABELS ............................................................................................................................................ 34
9.1 CMO MODULE LABEL ...................................................................................................................................... 34
10. PACKAGING.............................................................................................................................................................. 36
10.1 PACKAGING SPECIFICATIONS ..................................................................................................................... 36
10.2 PACKAGING METHOD .................................................................................................................................... 36
11. MECHANICAL CHARACTERISTICS ........................................................................................................................ 38
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REVISION HISTORY
Version Date
Ver. 1.0
Ver. 1.1
Ver. 2.0
Ver. 2.1
Apr. 22, 2009 May. 20, 2009 Jul. 01, 2009
Jul. 23, 2009
Page (New)
All
P38~P40
All
36
P39~P41
1
6
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Section Description
Al
Chapter11.
All
10.1
Chapter11
Cover.
1.4
The Preliminary specification was first issued.
Modify the enhanced ribs of Metal Frame Rear drawing.
The Approve specification was first issued.
Modify Box dimensions
Add a rectangular hole on ribs of Metal Frame Rear drawing.
Modify the Approved dept. and owner as TV Product Marketing & Management Div and . Chao-Chun Chung.
Modify the Depth of module size
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
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g
(3H)
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V470H2-LH1 is a 47” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (10-bit/color). The
inverter module for backlight is built-in.
1.2 FEATURES
Ё High brightness (500 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 4.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1039.68 (H) x584.82 (V) (47” diagonal) mm
Bezel Opening Area 1049(H) x 539 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.5405 (V) x 0.1805 (H) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 1.07G color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
Anti-Glare coating (Haze 11%)/ Hard coatin
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) - 1096 - mm
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
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Module Size
Depth (D) - 48.5 - mm
Weight - (12400) - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
(1), (2)Vertical (V) - 640 - mm
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
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Model No.: V470H2-LH1
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Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
axis
Z axis 35 G (3), (5)
- 50 G (3), (5)
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
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Value
Unit Note
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control. Internal PWM Control and External PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
(1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current IRUSH - - 3.6 A (2)
White Pattern - - 1.1 -- A
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Model No.: V470H2-LH1
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Value
Unit Note
Min. Typ. Max.
Power Supply Current
Black Pattern - - 1.1 - A
LVDS interface
CMOS interface
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
Common Input Voltage VLVC 1.125 1.25 1.375 V
Terminating Resistor RT - 100 - ohm
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage VIL 0 - 0.7 V
-
- 1.8 2.1 A
(3) Vertical Stripe
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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Model No.: V470H2-LH1
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a. White Pattern
Active Area
c. Vertical Stripe Pattern
b. Black Pattern
Active Area
Active Area
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3.2 BACKLIGHT UNIT
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Lamp Input Voltage VL - 1175 - VRMS -
Lamp Current IL 8.8 9.3 9.8 mARMS (1)
- - 1820 VRMS Ta = 0 ºC
Lamp Turn On Voltage VS
- - 1620 VRMS Ta = 25 ºC
Operating Frequency FL 40 - 70 KHz
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Model No.: V470H2-LH1
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Unit Note
Lamp Life Time LBL 50,000 - Hrs (2)
3.2.2 INVERTER CHARACTERISTICS (Ta= 25 ± 2 ºC)
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Power Consumption PBL - 130 138 W (5), IL =9.3mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 5.4 - A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 37 40 43 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 20 - %
Note (1) Lamp current is measured by utilizing AC current probe.
Unit Note
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
should be applied to the lamp for more than 1 second after startup.
S
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the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
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Model No.: V470H2-LH1
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2к and I
Note (5) The measurement condition of Max. value is based on 47" backlight unit under input voltage
24V, average lamp current 9.6 mA and lighting 30 minutes later.
LCD
Module
=9.0~9.6 mArms.
L
HV (Pink) HV (White)
HV (Pink) HV (White)
HV (Pink) HV (White)
HV (Pink)
HV (White)
HV (Pink) HV (White)
HV (Pink)
HV (White)
1 2
1 2
1 2
Inverter
1
2
1
2
1
2
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Model No.: V470H2-LH1
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Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control Voltage
External PWM Control Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Te st
Condition
Ё
Ё
Ё
Min. Typ. Max.
2.0
0
2.85 3.0 3.15 V maximum duty ratio
Ё Ё
Ё
Ё
Ё
Ё
Ё
Ё
2.0
0
3.0 3.3 3.6 V
0
30
30
Ё Ё Ё
Value
Ё
Ё
0
Ё
Ё
Ё
Ё Ё
Ё Ё
Unit Note
5.0 V
0.8 V
Ё
V minimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
Ё
Ё
1
100
300
Ё Ё
Ё Ё
Ё Ё
100 ms
50 us
50 us
M
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
Ё Ё
Ё Ё
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш PWM signal Ш BLON
Ш PWM signal Ш VBL
Note (4) When the Dynamic CR has been turned on, the skipped range of VIPWM 2.85~3.15V, is suggested to
avoid the abnormal phenomenon.
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Model No.: V470H2-LH1
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V
VBLON
V
EPWM
V
IPWM
9%/
Toff
Tf1
9
%/
Tr1
BL
0
9
0
%/
2.0V
0.8V
9
Ton
%/
Ton1
Backlight on duration
Tr
Tf
Ext. Dimming Function
TPWMR
PWMF
2.0V
0
0.8V
T
PWM
T
Floating
3.0V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 N.C. No Connection 8 N.C. No Connection 9 GND Ground
10 CH3_0N Third Pixel Negative LVDS differential data input. Channel 0 11 CH3_0P Third Pixel Positive LVDS differential data input. Channel 0 12 CH3_1N Third Pixel Negative LVDS differential data input. Channel 1 13 CH3_1P Third Pixel Positive LVDS differential data input. Channel 1 14 CH3_2N Third Pixel Negative LVDS differential data input. Channel 2 15 CH3_2P Third Pixel Positive LVDS differential data input. Channel 2 16 GND Ground 17 CH3_CLKN 18 CH3_CLKP 19 GND Ground 20 CH3_3N Third Pixel Negative LVDS differential data input. Channel 3 21 CH3_3P Third Pixel Positive LVDS differential data input. Channel 3 22 CH3_4N Third Pixel Negative LVDS differential data input. Channel 4 23 CH3_4P Third Pixel Positive LVDS differential data input. Channel 4 24 N.C. No Connection 25 N.C. No Connection 26 CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0 27 CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0 28 CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1 29 CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1 30 CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2 31 CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2 32 GND Ground 33 CH4_CLKN 34 CH4_CLKP 35 GND Ground 36 CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3 37 CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3 38 CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4 39 CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4 40 N.C. No Connection 41 N.C. No Connection
Third Pixel Negative LVDS differential clock input. Third Pixel Positive LVDS differential clock input.
Fourth Pixel Negative LVDS differential clock input. Fourth Pixel Positive LVDS differential clock input.
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(4)
(4)
(1)
(4)
(4)
(1)
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CNF2 Connector Pin Assignment (FI-RE51S-HF (JAE) or equivalent )
Pin Name Description Note
1 N.C. No Connection 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 ODSEL Overdrive Lookup Table Selection (3) 6 N.C. No Connection (1) 7 SELLVDS LVDS data format Selection (2) 8 N.C. No Connection
9 N.C. No Connection 10 DCREN Dynamic Contrast Ratio Enable (5) 11 GND Ground 12 CH1_0N First Pixel Negative LVDS differential data input. Channel 0 13 CH1_0P First Pixel Positive LVDS differential data input. Channel 0 14 CH1_1N First Pixel Negative LVDS differential data input. Channel 1 15 CH1_1P First Pixel Positive LVDS differential data input. Channel 1 16 CH1_2N First Pixel Negative LVDS differential data input. Channel 2 17 CH1_2P First Pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 CH1_CLKN 20 CH1_CLKP 21 GND Ground 22 CH1_3N First Pixel Negative LVDS differential data input. Channel 3 23 CH1_3P First Pixel Positive LVDS differential data input. Channel 3 24 CH1_4N First Pixel Negative LVDS differential data input. Channel 4 25 CH1_4P First Pixel Positive LVDS differential data input. Channel 4 26 N.C. No Connection 27 N.C. No Connection 28 CH2_0N Second Pixel Negative LVDS differential data input. Channel 0 29 CH2_0P Second Pixel Positive LVDS differential data input. Channel 0 30 CH2_1N Second Pixel Negative LVDS differential data input. Channel 1 31 CH2_1P Second Pixel Positive LVDS differential data input. Channel 1 32 CH2_2N Second Pixel Negative LVDS differential data input. Channel 2 33 CH2_2P Second Pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 CH2_CLKN 36 CH2_CLKP Second Pixel Positive LVDS differential clock input. 37 GND Ground 38 CH2_3N Second Pixel Negative LVDS differential data input. Channel 3 39 CH2_3P Second Pixel Positive LVDS differential data input. Channel 3 40 CH2_4N Second Pixel Negative LVDS differential data input. Channel 4 41 CH2_4P Second Pixel Positive LVDS differential data input. Channel 4 42 N.C. No Connection 43 N.C. No Connection 44 GND Ground
First Pixel Negative LVDS differential clock input. First Pixel Positive LVDS differential clock input.
Second Pixel Negative LVDS differential clock input.
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(1)
(4)
(4)
(1)
(4)
(4)
(1)
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45 GND Ground 46 GND Ground 47 N.C. No Connection (1) 48 Vin Power input (+12V) 49 Vin Power input (+12V) 50 Vin Power input (+12V) 51 Vin Power input (+12V)
Note (1) Please be reserved to open.
Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to +3.3V.
Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Note
L Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
Note (4) LVDS 4-Port Data Mapping
Port CH of LVDS Data Stream
1st Port First pixel 1, 5, 9, ..........., 1913, 1917
2nd Port Second pixel 2, 6, 10, ........., 1914, 1918
3rd Port Third pixel 3, 7, 11, ........., 1915, 1919
4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920
Note (5) Low : function disable (default), High : Dynamic Contrast Ratio function enable
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN3~CN26: BHR-04VS-1 (JST).
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST. The
mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
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5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin  Symbol Feature
1
2
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3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V) Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin  Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Current Cycle
AR 0P AR 0N
AR 1P AR 1N
AR 2P AR 2N
AR 3P AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
DE
REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Basic Colors
Gray Scale Of Red
Gray Scale Of Green
Gray Scale Of Blue
Color
Black Red Green Blue Cyan Magenta Yellow White
Red (0) / Dark Red (1) Red (2)
:
: Red (1021) Red (1022) Red (1023)
Green (0) / Dark Green (1) Green (2)
:
: Green (1021) Green (1022) Green (1023)
Blue (0) / Dark Blue (1) Blue (2)
:
: Blue (1021) Blue (1022) Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0 1 0 0 0 1 1 1
0 0 0
:
: 1 1 1
0 0 0
:
: 0 0 0
0 0 0
:
: 0 0 0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1 0 1 1
0 0 0
:
: 0 0 0
0 0 0
:
: 1 1 1
0 0 0
:
: 0 0 0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
: :
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
;
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
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LVDS Re cei ver Clock
LVDS Re cei ver Data
Vertica l Active Display Te rm
Horizontal Active Display Te rm
Note : Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low logic
Frequency 1/Tc 60 74.25 80 MHz -
Input cycle to cycle jitter
Setup Time Tlvsu 600 - - ps -
Hold Time Tlvhd 600 - - ps -
Frame Rate - 120 - Hz
Total Tv 1115 1125 113 5 Th
Display Tvd 1080 1080 1080 Th -
Blank Tvb 35 45 55 Th -
Total T h
Display Thd
Blank Thb
Trcl - - 200 ps -
Tv=Tvd+Tvb
1050 1100 1150
960 960 960
90 140 190
Tc
Tc -
Tc -
Th=Thd+Thb
level. Otherwise, this module would operate abnormally.
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Valid display data (960 clocks)
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Љ
Љ
Љ
Љ
Љ
Љ
Љ
6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram
below.
0.5ЉT1Љ10ms 0 0 500ms
2
T
3
T
100ms 100ms
T
4
0V
LVDS Signals
0V
0ЉT7ЉT2
0
8
T
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2
T
Power On
T7
VALID
3 T1
T
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0.1V
cc
T4
Power Off
8
T
Option Signals
(SELLVDS)
Backlight (Recommended)
T5
500ms
50%
50%
T
5
T
6
Note.
Power ON/OFF Sequence
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance. If T2<0,
that maybe cause electrical overstress failures.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD Module
LCD Panel
25r2
50r10
9.3r0.5
40r3
oC
%RH
mA
KHz
Center of the Screen
Display Color Analyzer
(Minolta CA210)
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
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Contrast Ratio CR
Response Time
Center Luminance of White LC (400) (500) - cd/m2Note (4)
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color Chromaticity
Blue
White
Gray to
gray
GW
Rx
Ry
Gx (0.272) -
Gy (0.599) -
Bx (0.152) -
By (0.067) -
Wx (0.285) -
Wy (0.295) -
Tx=0q, Ty =0q
Viewing angle
at normal direction
(3000) (4000) - - Note (2)
- (4.5) (9) ms Note (3)
- - (1.3) - Note (7)
Typ.
-0.03
(0.643)
(0.332)
Typ.
+0.03
-
-
-
Color Gamut C.G (68) (72) - % NTSC
Tx+
Horizontal
Tx-
Viewing Angle
TY+
Vertica l
TY-
Note (1) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Eldim EZ-Contrast 160R
CRt20
80 88 -
80 88 -
Deg. Note (1)
80 88 -
80 88 -
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023.
Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636,
764, 892, 1023 to each other.
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 1023 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
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Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA u 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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Note (6) Definition of White Variation (GW):
Measure the luminance of gray level 1023 at 5 points
GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CHI MEI
OPTOELECTRONICS
V470H2 -LH1 Rev. XX
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Model No.: V470H2-LH1
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E207943
MADE IN TAIWAN
RoHS
X X X X X X X Y M D L N N N N
Model Name: V470H2-LH1
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
V470H2 -LH1 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
E207943
MADE IN TAIWAN
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
CMO Internal Use
Revision
CMO Internal Use
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Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1190(L)x280(W)x725(H)mm
(3) Weight : approximately 42 Kg ( 3 modules per box)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method
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LCD TV Module
Anti-static Bag
Carton
PP Belt
Cushion(Bottom)
Figure.10-1 packing method
Carton Label
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(
)
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
Air Transportation &
Sea / Land Transportation (40ft Container)
(L1130*50*50mm)
Film
(L1150*W1190*H140mm)
(L1400*50*50mm)
Gross: 351kg
Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
(L625*50*50mm)
Film
(L1400*50*50mm)
L1150*W1190*H140mm
Gross: 534kg
Figure.10-2 packing method
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11. MECHANICAL CHARACTERISTICS
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
࡛ભሽ՗ٝڶૻֆ׹
%*+/'+
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Global LCD Panel Exchange Center
www.panelook.com
Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
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Global LCD Panel Exchange Center
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Issue Date:Jul.23.2009
Model No.: V470H2-LH1
Approval
40
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