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TFT LCD Approval Specification
MODEL NO.: V470H1 – LH3
Customer: _________________________________
Approved by:_______________________________
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Note:
TV Head Division
Approved By
LY C hen
Reviewed By
QRA Dept. Product Development Div.
Tomy Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
Ken Wu HT Hung
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
CONTENTS
REVISION HISTORY ..................................................................................................................................................4
1. GENERAL DESCRIPTION......................................................................................................................................5
1.1 OVERVIEW....................................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
1.3 APPLICATION................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS ........................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS ..................................................................................................................6
2. ABSOLUTE MAXIMUM RATINGS ...........................................................................................................................7
2.1 ELECTRICAL ABSOLUTE RATINGS..............................................................................................................7
2.1.1 TFT LCD MODULE...............................................................................................................................7
2.2 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
2.3 RELIABILITY TEST CONDITION....................................................................................................................8
3. ELECTRICAL CHARACTERISTICS........................................................................................................................9
3.1 TFT LCD MODULE.........................................................................................................................................9
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION.....................................................................................10
3.2.1 LAMP SPECIFICATION......................................................................................................................10
3.2.2 ELECTRICAL SPECIFICATION .......................................................................................................... 11
4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................... 12
4.1 TFT LCD MODULE.......................................................................................................................................12
5. INPUT TERMINAL PIN ASSIGNMENT..................................................................................................................13
5.1 TFT LCD Module Input .................................................................................................................................13
5.2 BACKLIGHT UNIT........................................................................................................................................ 16
5.3 BLOCK DIAGRAM OF INTERFACE .............................................................................................................17
5.4 LVDS INTERFACE ....................................................................................................................................... 19
5.5 COLOR DATA INPUT ASSIGNMENT............................................................................................................20
6. INTERFACE TIMING............................................................................................................................................. 21
6.1 INPUT SIGNAL TIMING SPECIFICATIONS..................................................................................................21
6.2 POWER ON/OFF SEQUENCE..................................................................................................................... 23
7. OPTICAL CHARACTERISTICS.............................................................................................................................24
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
7.1 TEST CONDITIONS..................................................................................................................................... 24
7.2 OPTICAL SPECIFICATIONS........................................................................................................................25
8. PRECAUTIONS ....................................................................................................................................................28
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .............................................................................................28
8.2 SAFETY PRECAUTIONS ............................................................................................................................. 28
9. DEFINITION OF LABELS......................................................................................................................................29
9.1 CMO MODULE LABEL.................................................................................................................................29
10. PACKAGING .......................................................................................................................................................30
10.1 PACKAGING SPECIFICATIONS.................................................................................................................30
10.2 PACKAGING METHOD .............................................................................................................................. 30
11. MECHANICAL CHARACTERISTICS ...................................................................................................................32
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REVISION HISTORY
Version Date
Ver.1.0
Dec, 26,’07
Page
(New)
All
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Section Description
All
Preliminary Specification was first issued.
Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V470H1-LH3 is a 47” TFT Liquid Crystal Display module with 20-CCFL Backlight unit and 4ch-LVDS
interface. This module supports 1920 x 1080 Full HDTV format and can display true 1.0G colors
(10-bit/color). The inverter module for backlight isn’t built-in.
1.2 FEATURES
Ё
High brightness (500 nits)
Ё
High contrast ratio (2000:1)
Ё
Fast response time (Gray to gray average 4.0 ms)
Ё
High color saturation (NTSC 72%)
Ё
Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё
DE (Data Enable) only mode
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Model No.: V470H1-LH3
Preliminary
Ё
LVDS (Low Voltage Differential Signaling) interface
Ё
Optimized response time for 100 Hz frame rate
Ё
Ultra wide viewing angle : Super MVA technology
Ё
RoHS compliance
1.3 APPLICATION
Ё
Standard Living Room TVs.
Ё
Public Display Application.
Ё
Home Theater Application.
Ё
MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1039.68(H) x 584.82 (V) (47” diagonal) mm
Bezel Opening Area 1049 (H) x 593 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
Pixel Pitch(Sub Pixel) 0.5415 (H) x 0.1805 (V) mm -
Pixel Arrangement RGB vertical stripe - -
(1)
Display Colors 1.0G color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment Anti-Glare coating / 3H - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 1094.5 1096.0 1097.5 mm
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Module Size
Weight - 14750 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
Vertical (V) 638.0 640.0 641.5 mm
Depth (D) 47.1 48.1 49.1 mm
(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ELECTRICAL ABSOLUTE RATINGS
2.1.1 TFT LCD MODULE
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.2 V
Logic Input Voltage VIN -0.3 3.6 V
Value
Unit Note
2.2 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
Љ
40 ºC).
Min. Max.
Value
Unit Note
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.3 RELIABILITY TEST CONDITION
No Test Item Codition
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
1 High temperature storage test
2 Low temperature storage test
High temperature high humidity storage
3
test
4 High temperature operation test
5 Low temperature operation test
High temperature high humidity operation
6
test
7 Vibration test (non-operation)
8 Shock test (non-operation)
Ta = 6 0
Ta = -20
Ta = 5 0
Ta = 5 0
Ta = 0
Ta = 5 0
Wave form: Sine wave
Vibration level: 1.0G
Fre. range : 10~200Hz
Duration: X, Y, Z, 10min,
One time each direction
Wave form: half sine wave
Shock level: 50G
One time each direction
к
, 240hrs
к
, 240hrs
к
, 90%RH, 240hrs
к
, 240hrs
к
, 240hrs
к
, 80%RH, 240hrs
X, Y, Z, 11ms
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current IRUSH - - 7.5 A (2)
White Pattern - - 2.5 3.0 A
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Value
Unit Note
Min. Typ. Max.
Power Supply Current
Mosaic Pattern
-
- 1.5 - A
Black Pattern - - 1.9 - A
LVDS
Interface
Differential Input High Threshold
Voltage
Differential Input Low Threshold
Voltage
Common Input Voltage VLVC 1.125 1.25 1.375 V
VLVTH - - 100 mV
VLVTL -100 - - mV
Terminating Resistor RT - 100 - ohm
CMOS
interface
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage VIL 0 - 0.7 V
Note (1) The module should be always operated within the above ranges.
Note (2) The duration of rush current is about 2ms and measurement condition is shown below:
+12V
Q1 Si4485DY
Fus e
R1
1k
Vcc
(LCD Modu le Input)
C3
1uF
(3)
VR1
47k
(Low to High)
Control Signal
SW
R2
1k
Q2
2N7002
C1
0.01uF
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv =120 Hz,
whereas a power dissipation check pattern below is displayed.
a. White Pattern
c. Vertical Stripe Pattern
Active Area
b. Black Pattern
Active Area
R
G
R
G
B
R
G
B
G
R R
B
R
G
B
B
R
B
R
B
R
G
B
R
G
B
G
B
Active Area
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
- - 2370 VRMS Ta = 0 ºC
Lamp Starting Voltage VSL
- - 2160 VRMS Ta = 25 ºC
Lamp Voltage VL 1368 1520 1672 VRMS
Lamp Current IL 5.5 6.0 6.5 mARMS
Value
Unit Note
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Lamp Frequency FL 40 - 80 KHz
Lamp Life Time LBL 50,000 60,000 - Hrs (1)
Note(1) Condition: PWM 100% dimming duty ratio
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
BL Lamp Voltage VBL 1032 1147 1262 VRMS (1)
BL Lamp Current IBL 115 125 135 mARMS 20 lamps
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Model No.: V470H1-LH3
Preliminary
Value
Unit Note
Min. Typ. Max.
Oscillating Frequency FW 43 45 47 KHz
PWM Dimming Range PDIM 20 - 100 % (2)
Striking Time ST - - 2 Sec
Lamp Type - Straight Type -
Number of Lamps - 20 PCS
Type of Current Balance - C-Balance -
C Ballaster CB - 22 - pF
Note (1) Single size: Half lamp voltage + capacitor voltage
Note (2) V470H1-LH3 are designed without Inverter. These items are for reference and based on V470H1-L03
Inverter model.
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)
(+/
)
)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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Model No.: V470H1-LH3
Preliminary
4RX0(+/4RX1(+/-)
4RX2(+/-)
4RX3(+/-)
4RX4(+/-)
4CLK(+/-)
3RX0(+/-)
3RX1(+/-)
3RX2(+/-)
3RX3(+/-)
3RX4(+/-)
3CLK
2RX0(+/2RX1(+/-)
2RX2(+/-)
2RX3(+/-)
2RX4(+/-)
2CLK(+/-)
1RX0(+/-)
1RX1(+/-)
1RX2(+/-)
1RX3(+/-)
1RX4(+/-)
1CLK(+/-)
SELLVDS
VCC
GND
INPUT CONNECTOR
FI-RE41S-HF (JAE)
CNF2
FRAME BUFFER
SCAN DRIVER
TFT LCD PANEL
TIMING
(1920x3x1080)
CONTROLLER
-
INPUT CONNECTOR
FI-RE51S-HF (JAE)
CNF1
(SLAVE)
FRAME BUFFER
TIMING
DATA DRIVER (RSDS)
CONTROLLER
(MASTER)
DC/DC
CONVERTER
& REFERENCE
VOLTAGE
GENERATOR
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment( FI-RE51S-HF (JAE) or equivalent )
Pin Name Description Note
1 GND Ground
2 N.C.
3 N.C.
N.C. No Connection (1)
4
N.C. No Connection (1)
5
N.C. No Connection (1)
6
7 SELLVDS LVDS data format Selection (2)
N.C. No Connection (1)
8
9 N.C. No Connection (1)
N.C. No Connection (1)
10
11 GND Ground
12
RxAo-
13
RxAo+
14
RxBo-
15
RxBo+
16
RxCo-
17
RxCo+
18
GND
19
RxClko-
20
RxClko+
21
GND
22
RxDo-
23
RxDo+
24
RxEo-
25
RxEo+
26
NC
27
NC
28
RxAe-
29
RxAe+
30
RxBe-
31
RxBe+
32
RxCe-
33
RxCe+
34
GND
35
RxClke-
36
RxClke+
37
GND
38
RxDe-
39
RxDe+
40
RxEe-
41
RxEe+
42
GND
43
GND
44
GND
45
GND
46
GND
47
NC
48
Vin
No Connection (1)
No Connection (1)
First pixel, Negative LVDS differential data input. Channel 0
First pixel, Positive LVDS differential data input. Channel 0
First pixel, Negative LVDS differential data input. Channel 1
First pixel, Positive LVDS differential data input. Channel 1
First pixel, Negative LVDS differential data input. Channel 2
First pixel, Positive LVDS differential data input. Channel 2
Ground
First pixel, Negative LVDS differential clock input.
First pixel, Positive LVDS differential clock input.
Ground
First pixel, Negative LVDS differential data input. Channel 3
First pixel, Positive LVDS differential data input. Channel 3
First pixel, Negative LVDS differential data input. Channel 4
First pixel, Positive LVDS differential data input. Channel 4
No Connection (1)
No Connection (1)
Second pixel, Negative LVDS differential data input. Channel 0
Second pixel, Positive LVDS differential data input. Channel 0
Second pixel, Negative LVDS differential data input. Channel 1
Second pixel, Positive LVDS differential data input. Channel 1
Second pixel, Negative LVDS differential data input. Channel 2
Second pixel, Positive LVDS differential data input. Channel 2
Ground
Second pixel, Negative LVDS differential clock input.
Second pixel, Positive LVDS differential clock input.
Ground
Second pixel, Negative LVDS differential data input. Channel 3
Second pixel, Positive LVDS differential data input. Channel 3
Second pixel, Negative LVDS differential data input. Channel 4
Second pixel, Positive LVDS differential data input. Channel 4
Ground
Ground
Ground
Ground
Ground
No Connection
Power input (+12V)
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Model No.: V470H1-LH3
Preliminary
(4)
(4)
(4)
(4)
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49
Vin
50
Vin
51
Vin
CNF2 Connector Pin Assignment ( FI-RE41S-HF (JAE) or equivalent )
Pin Name Description Note
1 GND Ground
2 N.C.
3 N.C.
N.C. No Connection
4
N.C. No Connection
5
N.C. No Connection
6
7 NC No Connection (1)
N.C. No Connection
8
9 GND Ground
10
RxAo-
11
RxAo+
12
RxBo-
13
RxBo+
14
RxCo-
15
RxCo+
16
GND
17
RxClko-
18
RxClko+
19
GND
20
RxDo-
21
RxDo+
22
RxEo-
23
RxEo+
24
NC
25
NC
26
RxAe-
27
RxAe+
28
RxBe-
29
RxBe+
30
RxCe-
31
RxCe+
32
GND
33
RxClke-
34
RxClke+
35
GND
36
RxDe-
37
RxDe+
38
RxEe-
39
RxEe+
N.C. No Connection (1)
40
41 N.C. No Connection (1)
Note (1) Please be reserved to open.
Power input (+12V)
Power input (+12V)
Power input (+12V)
No Connection
No Connection
Third pixel, Negative LVDS differential data input. Channel 0
Third pixel, Positive LVDS differential data input. Channel 0
Third pixel, Negative LVDS differential data input. Channel 1
Third pixel, Positive LVDS differential data input. Channel 1
Third pixel, Negative LVDS differential data input. Channel 2
Third pixel, Positive LVDS differential data input. Channel 2
Ground
Third pixel, Negative LVDS differential clock input.
Third pixel, Positive LVDS differential clock input.
Ground
Third pixel, Negative LVDS differential data input. Channel 3
Third pixel, Positive LVDS differential data input. Channel 3
Third pixel, Negative LVDS differential data input. Channel 4
Third pixel, Positive LVDS differential data input. Channel 4
No Connection (1)
No Connection (1)
Fourth pixel, Negative LVDS differential data input. Channel 0
Fourth pixel, Positive LVDS differential data input. Channel 0
Fourth pixel, Negative LVDS differential data input. Channel 1
Fourth pixel, Positive LVDS differential data input. Channel 1
Fourth pixel, Negative LVDS differential data input. Channel 2
Fourth pixel, Positive LVDS differential data input. Channel 2
Ground
Fourth pixel, Negative LVDS differential clock input.
Fourth pixel, Positive LVDS differential clock input.
Ground
Fourth pixel, Negative LVDS differential data input. Channel 3
Fourth pixel, Positive LVDS differential data input. Channel 3
Fourth pixel, Negative LVDS differential data input. Channel 4
Fourth pixel, Positive LVDS differential data input. Channel 4
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Model No.: V470H1-LH3
Preliminary
(1)
(1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
Note (2) Low or Open : VESA LVDS Format (default), High : JEIDA Format.
Note (3) Low =Open or Connect to GND, High = Connect to +3.3V
Note (4) LVDS 4-Port Data Mapping
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Port CH of LVDS Data Stream
1st Port First pixel 1, 5, 9, ..........., 1913, 1917
2nd Port Second pixel 2, 6, 10, ........., 1914, 1918
3rd Port Third pixel 3, 7, 11, ........., 1915, 1919
4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920
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5.2 BACKLIGHT UNIT
CN1-CN2: 65002WR-03.
Pin Symbol Description
1 H.V. High Voltage for Backlight Unit
2 H.V. High Voltage for Backlight Unit
3 N.C. No Connection
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CN1
CN2
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5.3 BLOCK DIAGRAM OF INTERFACE
51
51
51
51
51
51
51
51
51
51
51
Ө
100pF
Ө
Ө
100pF
Ө
51
Ө
100pF
Ө
Ө
100pF
Ө
Ө
100pF
Ө
Ө
100pF
Ө
RXAe+
RXAe-
RXBe+
RXBe-
RXCe+
RXCe-
RXDe+
RXDe-
RXEe+
RXEe-
RXCLKe+
RXCLKe-
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Rx-OUT
PLL
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Model No.: V470H1-LH3
Preliminary
ER0-ER9
EG0-EG9
EB0-EB9
DE
OR0-OR9
OG0-OG9
OB0-OB9
DCLK
Timing
Controller
RXAe+
RXAe-
RXBe+
RXBe-
RXCe+
RXCe-
RXDe+
RXDe-
RXEe+
RXEe-
RXCLKe+
RXCLKe-
LVDS Input
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
LVDS Receiver
PLL
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ER0~ER9 : Even pixel R data
EG0~EG9 : Even pixel G data
EB0~EB9 : Even pixel B data
OR0~OR9 : Odd pixel R data
OG0~OG9: Odd pixel G data
OB0~OB9 : Odd pixel B data
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) The system must have the transmitter to drive the module.
(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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Model No.: V470H1-LH3
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is used differentially.
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5.4 LVDS INTERFACE
SELLVDS = L or Open
RXCLK
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Model No.: V470H1-LH3
Preliminary
SELLVDS = H
RXAo
RXBo
RXCo
RXDo
RXEo
RXAe
RXBe
RXCe
RXDe
RXEe
OR5OG0 OR4 OR3 OR2 OR1
OB0 OG5OB1
ER5EG0 ER4 ER3 ER2 ER1
EB0 EG5EB1
OG3 OG2OG4
EG3 EG2EG4
OR0
OG1
OB2OB4 OB3OB5VS HSDE
OR6OG6 OR7OG7OB7 OB6RSVD
OR8OG8 OR9OG9OB9 OB8RSVD
ER0
EG1
EB2EB4 EB3EB5VS HSDE
ER6EG6 ER7EG7EB7 EB6RSVD
ER8EG8 ER9EG9EB9 EB8RSVD
RXCLK
RXAo
RXBo
RXCo
RXDo
RXEo
RXAe
RXBe
RXCe
RXDe
RXEe
OR9OG4 OR8 OR7 OR6 OR5
OB4 OG9OB5
ER9EG4 ER8 ER7 ER6 ER5
EB4 EG9EB5
OG7 OG6OG8
EG7 EG6EG8
OR4
OG5
OB6OB8 OB7OB9VS HSDE
OR2OG2 OR3OG3OB3 OB2RSVD
OR0OG0 OR1OG1OB1 OB0RSVD
ER4
EG5
EB6EB8 EB7EB9VS HSDE
ER2EG2 ER3EG3EB3 EB2RSVD
ER0EG0 ER1EG1EB1 EB0RSVD
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R0~R9: Pixel R Data (9; MSB, 0; LSB)
G0~G9: Pixel G Data (9; MSB, 0; LSB)
B0~B9: Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
RSVD
: Reserved.
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of the
color versus data input.
0
0
1
0
1
0
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
;
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Color
Black
Red
Green
Blue
Cyan
Magenta
Yel lo w
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc 60 74.25 80 MH
Clock
Data
Vertical Active
Display Term
Horizontal Active
Display Term
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low logic
Input cycle to cycle jitter Trcl - - 200 ps Setup Time Tlvsu 600 - - ps LVDS Receiver
Hold Time Tlvhd 600 - - ps
Frame Rate Fr
Total Tv 1115 1125 1139 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th Blank Tvb 35 45 59 Th Total Th 540 550 575 Tc Th=Thd+Thb
Display Thd 480 480 480 Tc Blank Thb 45 70 95 Tc -
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120 Hz
Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Z
=297/4 LVDS Receiver
level. Otherwise, this module would operate abnormally..
INPUT SIGNAL TIMING DIAGRAM
Tvd
DE
T
h
DCLK
DE
Tv
Tvb
Thd
DATA
Valid display data ( 480 clocks)
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
RXCLK+/-
RXn+/-
LVDS INPUT INTERFACE TIMING DIAGRAM
Tlvsu
Tlvhd
1T‘
14
3T‘
14
5T‘
14
Tc
7T‘
14
9T‘
14
11T‘
14
13T‘
14
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6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the
diagram below.
Power Supply
V
0.5
ЉЉЉЉ
0
0
500ms
ЉЉЉЉ
ЉЉЉЉ
CC
T
1
ЉЉЉЉ
10ms
T
2
ЉЉЉЉ
50ms
T
3
ЉЉЉЉ
50ms
ЉЉЉЉ
Signals
0V
T4
0V
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0.9 V
CC
0.1V
CC
T
2
Power On
VALI D
0.9 V
T
3
T1
Power Off
Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
CC
cc
0.1V
T4
Backlight (Recommended)
ЉЉЉЉ
500ms
100ms
T5
ЉЉЉЉ
T
6
50%
5
T
50%
6
T
Power ON/OFF Sequence
Note.
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the
LCD operation or the LCD turns off before the backlight turns off, the display may momentarily
become abnormal screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on
period.
Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 100 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD Module
LCD Panel
Center of the Screen
25±2
50±10
125±10
45±2
Display Color Analyzer
(Minolta CA210)
oC
%RH
mA
KHz
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (1800) (2000) - Note (2)
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Response Time
Center Luminance of White LC (400) (500)
White Variation
Gray to
gray
δW
(4.0) (8.0) ms Note (3)
cd/m
Note (4)
2
(1.3) - Note (7)
Cross Talk CT (4) % Note (5)
Color
Chromaticity
Viewing Angle
Red
Rx (0.638) -
Ry (0.331) -
Gx
Green
Gy
Bx
Blue
By
Wx
White
Wy
Color Gamut C.G
Horizontal
θx+
θx-
Vertical
θY+
θY-
θx=0°, θy =0°
Viewing angle
at normal direction
CR≥20
Typ.
-0.03
(0.268)
(0.593)
(0.143)
(0.068)
(0.280)
(0.285)
Typ.
+0.03
-
Note (6)
-
-
-
-
(70) (72) % NTSC
80 88
80 88
Deg. Note (1)
80 88
80 88
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Eldim EZ-Contrast 160R
θX- = 90º
6 o
ϗ
clock
θy- = 90º
x-
y-
Normal
θ x = θ y = 0º
y-
θ
θ
θx−
y+
θx+
25
y+
12 o
ϗ
clock direction
θy+ = 90º
x+
θX+ = 90º
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p
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Surface Luminance with all white
Contrast Ratio (CR) =
Surface Luminance with all black pixels
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).
Note (3) Definition of Gray-to-Gray Switching Time:
Optical Response
100 %
90 %
10 %
0 %
Gray to Gray
Switching Time
The driving signal means the signal of luminance 0%, 20%, 40%, 60%, 80%, 100%.
ixels
Gray to Gray
Switching Time
Time
Gray to gray average time means the average switching time of luminance 0%, 20%, 40%, 60%, 80%,
100% to each other.
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA × 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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(0,0)
Active Area
(D/2,W/8)
Y
A,U
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(0,0)
Active Area
(D/4,W/4)
Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
(D/2,W/8)
Y
B,U
Gray 128
Y
(D/8,W/2) Y
A,L
(D/2,7W/8)
Y
A,D
Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
D
4
1 2
W
4
W
W
2
Vertical Line
3W
4
3 4
(7D/8,W/2)
A,R
Horizontal Line
D
5
Gray 0
Gray 128
Y
(D/8,W/2) Y
B,L
D
2
3D
4
Y
(D/2,7W/8)
B,D
(7D/8,W/2)
B,R
X
Test point :
X = 1 ~ 5
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
к
at normal humidity without
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
Model Name: V470H1-LH3
CHI MEI
OPTOELECTRONICS
V470H1 -LH3 Rev. XX
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
E207943
MADE IN TAIWAN
RoHS
X X X X X X X Y M D L N N N N
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
3 LCD TV modules / 1 Box
Box dimensions: 1190(L) X 280 (W) X 720(H)
Weight: approximately 52Kg (3 modules per box)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method.
LCD TV Module
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
Anti-static Bag
Carton
PP Belt
3pcs Drier
Carton Label
Cushion(Bottom)
Figure.10-1 packing method
Figure.10-2 Packing method
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
(L1130*50*50mm)
Film
(L1150*W1195*H140mm)
(L1400*50*50mm)
Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
(L625*50*50mm)
Film
(L1400*50*50mm)
(L1150*W1195*H140mm)
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11. MECHANICAL CHARACTERISTICS
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
࡛ભሽٝڶૻֆ
CHI MEI
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Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
࡛ભሽٝڶૻֆ
CHI MEI
33
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
Version 1.0
www.panelook.com
Page 34
Global LCD Panel Exchange Center
www.panelook.com
Issue Date:Dec.26.2007
Model No.: V470H1-LH3
Preliminary
࡛ભሽٝڶૻֆ
CHI MEI
34
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
Version 1.0
www.panelook.com
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